WO2020183842A1 - Control circuit and ranging system - Google Patents
Control circuit and ranging system Download PDFInfo
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- WO2020183842A1 WO2020183842A1 PCT/JP2019/049480 JP2019049480W WO2020183842A1 WO 2020183842 A1 WO2020183842 A1 WO 2020183842A1 JP 2019049480 W JP2019049480 W JP 2019049480W WO 2020183842 A1 WO2020183842 A1 WO 2020183842A1
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S17/00—Systems using the reflection or reradiation of electromagnetic waves other than radio waves, e.g. lidar systems
- G01S17/02—Systems using the reflection of electromagnetic waves other than radio waves
- G01S17/06—Systems determining position data of a target
- G01S17/08—Systems determining position data of a target for measuring distance only
- G01S17/10—Systems determining position data of a target for measuring distance only using transmission of interrupted, pulse-modulated waves
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/48—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S17/00
- G01S7/483—Details of pulse systems
- G01S7/486—Receivers
- G01S7/487—Extracting wanted echo signals, e.g. pulse detection
Definitions
- the present disclosure relates to a control circuit and a ranging system.
- a distance measurement method called the direct ToF (Time of Flight) method As one of the distance measurement methods that measure the distance to the object to be measured using light, a distance measurement method called the direct ToF (Time of Flight) method is known.
- the direct ToF method the light emitted from the light source receives the reflected light reflected by the object to be measured by the light receiving element, and the distance to the target is based on the time from the emission of the light to the reception as the reflected light.
- This disclosure proposes a control circuit and a distance measuring system capable of expanding the dynamic range.
- a control circuit includes a pulse output unit, an addition unit, and a pulse shaping unit.
- the pulse output unit outputs a plurality of first pulse signals corresponding to the signals generated by the plurality of SPAD (Single Photon Avalanche Diode) elements.
- the addition unit adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal.
- the pulse shaping unit shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
- the dynamic range can be expanded.
- the effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
- a distance measuring method called a direct ToF method As one of the distance measuring methods for measuring the distance to the object to be measured using light, a distance measuring method called a direct ToF method is known.
- the light emitted from the light source receives the reflected light reflected by the object to be measured by the light receiving element, and the distance to the target is based on the time from the emission of the light to the reception as the reflected light. To measure.
- the difference between the minimum and maximum number of photons that can be measured becomes small, and the dynamic range of the distance measurement system may decrease.
- the present disclosure relates to a technique for performing distance measurement using light. Therefore, in order to facilitate understanding of the embodiment of the present disclosure, a distance measuring method applicable to the embodiment will be described with reference to FIGS. 1 and 2.
- FIG. 1 is a diagram schematically showing distance measurement by the direct ToF method applicable to the embodiment of the present disclosure.
- the ToF method is directly applied as the distance measuring method.
- the light emitted from the light source unit 2 L1 receives the reflected light L2 reflected by the object 100 to be measured by the light receiving unit 3, and the distance is measured based on the time difference between the light emission timing and the light receiving timing. It is a method to do.
- the distance measuring device 1 includes a light source unit 2 and a light receiving unit 3.
- the distance measuring device 1 is an example of a distance measuring system.
- the light source unit 2 has, for example, a light source 4 (see FIG. 3) which is a laser diode, and is driven so as to emit laser light in a pulsed manner.
- the emitted light L1 from the light source unit 2 is reflected by the object to be measured 100 and is received by the light receiving unit 3 as reflected light L2.
- the light receiving unit 3 includes a pixel array unit 6 (see FIG. 3) that converts light into an electric signal by photoelectric conversion, and outputs a signal corresponding to the received light.
- time t 0 the time when the light source unit 2 emits light
- time t 3 the time when the light receiving unit 3 receives the reflected light L2 reflected by the object 100 from the light source unit 2 (light receiving timing). ) Is time t 1 .
- the distance D between the distance measurement apparatus 1 and the object to be measured 100 is calculated by the following equation (1).
- D (c / 2) ⁇ (t 1 ⁇ t 0 )... (1)
- the distance measuring device 1 may repeat the above-mentioned processing a plurality of times. Further, the light receiving unit 3 may have a plurality of SPAD elements 6a (see FIG. 4), and the distance D may be calculated based on each light receiving timing when the reflected light L2 is received by each SPAD element 6a.
- the distance measuring device 1 sets the time t m (hereinafter, also referred to as “light receiving time t m ”) from the light emitting timing time t 0 to the light receiving timing when the light is received by the light receiving unit 3 (bins). ) To classify and generate a histogram.
- FIG. 2 is a diagram showing an example of a histogram based on the time when the light receiving unit 3 is applicable, which is applicable to the embodiment of the present disclosure.
- the horizontal axis indicates the bin and the vertical axis indicates the frequency for each bin.
- the bins are obtained by classifying the light receiving time t m for each predetermined unit time d.
- bin # 0 is 0 ⁇ t m ⁇ d
- bin # 1 is d ⁇ t m ⁇ 2 ⁇ d
- bin # 2 is 2 ⁇ d ⁇ t m ⁇ 3 ⁇ d
- Bin # (N). -2) is (N-2) ⁇ d ⁇ t m ⁇ (N-1) ⁇ d.
- the distance measuring device 1 counts the number of times the light receiving time t m is acquired based on the bin, obtains the frequency 200 for each bin, and generates a histogram.
- the light receiving unit 3 also receives light other than the reflected light L2 from which the emitted light L1 emitted from the light source unit 2 is reflected.
- ambient light is light that is randomly incident on the light receiving unit 3, and the ambient light component 201 due to the ambient light in the histogram becomes noise for the target reflected light L2.
- the target reflected light L2 is light received according to a specific distance and appears as an active light component 202 in the histogram.
- the bin corresponding to the frequency of the peak in the active light component 202 is the bin corresponding to the distance D of the object to be measured 100.
- the distance measuring device 1 acquires the representative time of the bottle (for example, the time in the center of the bottle) as the time t 1 described above, and calculates the distance D to the object to be measured 100 according to the above formula (1). be able to. As described above, by using a plurality of light reception results, it is possible to perform appropriate distance measurement for random noise.
- FIG. 3 is a block diagram showing a configuration example of the distance measuring device 1 according to the embodiment of the present disclosure.
- the distance measuring device 1 includes a light source unit 2 and a light receiving unit 3.
- the light source unit 2 has a light source 4 and a light source driving unit 5.
- the light source 4 is composed of, for example, a laser diode such as a vertical cavity surface emitting laser (VCSEL: Vertical Cavity Surface Emitting LASER).
- VCSEL Vertical Cavity Surface Emitting LASER
- the light source 4 is not limited to the VCSEL, and a laser diode array in which laser diodes are arranged on a line may be used.
- the light source driving unit 5 drives the light source 4.
- the light source driving unit 5 drives the light source 4 so that the emitted light L1 having a predetermined timing and pulse width is emitted from the light source 4 based on the light emission control signal from the control unit 11 of the light receiving unit 3.
- the light source driving unit 5 can drive the light source 4 so that the laser light is scanned in the direction perpendicular to the line, for example, from the light source 4 having the laser diodes arranged on the line.
- the light receiving unit 3 includes a pixel array unit 6, a pulse output unit 7, an addition unit 8, a pulse shaping unit 9, a counter unit 10, and a control unit 11.
- the pixel array unit 6 has a plurality of SPAD elements 6a (see FIG. 4) arranged in a two-dimensional lattice pattern.
- SPAD element 6a when a large reverse bias voltage that causes an avalanche multiplier is applied to the cathode, the avalanche multiplier is internally generated due to the electrons generated in response to the incident of one photon.
- the SPAD element 6a has a characteristic that a large current flows according to the incident of one photon. Then, the SPAD element 6a can detect the incident of one photon contained in the reflected light L2 with high sensitivity by utilizing such a characteristic.
- the operation of the plurality of SPAD elements 6a in the pixel array unit 6 is controlled by the control unit 11.
- the control unit 11 may control the reading of signals from each SPAD element 6a for each block including (n ⁇ m) SPAD elements 6a having n pixels in the row direction and m pixels in the column direction. it can.
- control unit 11 can scan each SPAD element 6a in the row direction and further scan each row in the column direction in units of the block, and can read a signal from each SPAD element 6a.
- control unit 11 may independently read a signal from each SPAD element 6a.
- the signal generated by the SPAD element 6a of the pixel array unit 6 is supplied to the pulse output circuit 7a (see FIG. 5) of the pulse output unit 7.
- the pulse output unit 7 has the same number of pulse output circuits 7a as the SPAD elements 6a.
- the pulse output circuit 7a outputs a predetermined first pulse signal P1 (see FIG. 6) to the adder 8 as a digital signal according to the signal generated by the corresponding SPAD element 6a.
- the pulse output unit 7 outputs a plurality of first pulse signals P1 corresponding to the signals generated by the plurality of SPAD elements 6a, respectively. Details of the pulse output unit 7 and the pulse output circuit 7a will be described later.
- the addition unit 8 adds a plurality of first pulse signals P1 output from the pulse output unit 7 to generate an addition signal Pa (see FIG. 8). The details of the addition unit 8 will be described later.
- the pulse shaping unit 9 shapes the addition signal Pa into the second pulse signal P2 (see FIG. 11).
- the second pulse signal P2 is a signal having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than a predetermined period ⁇ T (see FIG. 10). Details of the pulse shaping unit 9 will be described later.
- the counter unit 10 counts the number corresponding to the pulse width of the second pulse signal P2 as the number of photons incident on the plurality of SPAD elements 6a. Details of the counter unit 10 will be described later.
- the control unit 11 controls the overall operation of the distance measuring device 1 according to, for example, a program incorporated in advance.
- the control unit 11 controls the light source driving unit 5 to control the light emission timing of the light source 4.
- control unit 11 generates the histogram shown in FIG. 2 based on the count number output from the counter unit 10. Further, the control unit 11 performs a predetermined arithmetic process based on the generated histogram data, and calculates the distance D to the object to be measured 100.
- FIG. 4 is a schematic diagram showing an example of a device configuration applicable to the light receiving unit 3 according to the embodiment of the present disclosure.
- the light receiving unit 3 is configured by laminating a light receiving chip 3a made of a semiconductor chip and a logic chip 3b, respectively.
- the light receiving chip 3a and the logic chip 3b are shown in a separated state for easy understanding.
- the logic chip 3b is provided with a pulse output unit 7, an addition unit 8, a pulse shaping unit 9, a counter unit 10, and a control unit 11 (not shown).
- the configuration of the light receiving chip 3a and the logic chip 3b is not limited to the example of FIG.
- FIG. 5 is a circuit diagram showing a configuration example of the pulse output circuit 7a of the pulse output unit 7 according to the embodiment of the present disclosure.
- the pulse output unit 7 has a pulse output circuit 7a.
- One pulse output circuit 7a is provided for one SPAD element 6a. That is, the same number of pulse output circuits 7a as the SPAD elements 6a are provided in the pulse output unit 7.
- each pulse output circuit 7a is connected to the corresponding SPAD element 6a.
- FIG. 5 for easy understanding, one SPAD element 6a and one pulse output circuit 7a are shown.
- the pulse output circuit 7a includes a P-type transistor 21, an inverter 22, a negative logic product circuit 23, a delay circuit 24, and a P-type transistor 25. Further, the delay circuit 24 has four inverters 31 to 34.
- the source of the P-type transistor 21 is connected to the power supply voltage Vdd, the drain of the P-type transistor 21 is connected to the signal line 26, and the gate of the P-type transistor 21 is connected to the node 27.
- the signal line 26 connects between the cathode of the SPAD element 6a and the input terminal of the inverter 22 via the connection unit 6b of the pixel array unit 6. Further, the anode of the SPAD element 6a is grounded, and the output terminal of the inverter 22 is connected to the adder 8 (see FIG. 3) via the node 27.
- the two input terminals of the negative AND circuit 23 are connected to the node 27 and the output terminal of the inverter 34.
- the output terminal of the negative conjunction circuit 23 is connected to the input terminal of the inverter 31.
- the output terminal of the inverter 31 is connected to the input terminal of the inverter 32.
- the output terminal of the inverter 32 is connected to the input terminal of the inverter 33.
- the output terminal of the inverter 33 is connected to the input terminal of the inverter 34.
- the negative AND circuit 23 and the four inverters 31 to 34 serve as ring oscillators.
- the source of the P-type transistor 25 is connected to the power supply voltage Vdd, the drain of the P-type transistor 25 is connected to the signal line 26, and the gate of the P-type transistor 25 is connected to the output terminal of the inverter 34.
- the low-level signal S2 is input to the gate of the P-type transistor 21 via the node 27. Therefore, in the initial state of the pulse output circuit 7a, a predetermined current is supplied to the cathode of the SPAD element 6a by the first supply path R1 including the P-type transistor 21.
- the pulse output circuit 7a can operate the SPAD element 6a by the predetermined current.
- a high level signal S3 is input to the gate of the P-type transistor 25 in the initial state.
- no current is supplied to the cathode of the SPAD element 6a from other than the first supply path R1 described above.
- FIG. 6 is an explanatory diagram showing the operation of the pulse output circuit 7a according to the embodiment of the present disclosure in a timing chart.
- a reverse bias voltage Va is applied to the SPAD element 6a until a state called Geiger mode is reached on the verge of avalanche amplification. That is, in the initial state, the signal S1 output from the cathode of the SPAD element 6a becomes this voltage Va.
- the inverter 22 since the voltage Va equal to or higher than the threshold voltage Vth is input to the inverter 22 as the signal S1, the inverter 22 outputs the low-level signal S2. Further, since the low level signal S2 is input to the negative AND circuit 23 from the inverter 22, the high level signal S3 is output from the delay circuit 24.
- the SPAD element 6a breaks down and a current flows through the first supply path R1.
- the signal S1 sharply decreases from the voltage Va.
- the inverter 22 outputs the high-level signal S2.
- the signal S1 stops lowering at the voltage Vb.
- the pulse output circuit 7a since the signal S2 that has reached a high level at time T2 is input to the gate of the P-type transistor 21, the first supply path R1 is cut off.
- the cathode of the SPAD element 6a is in a floating state cut off from the power supply voltage Vdd. Therefore, the signal S1 is fixed at the voltage Vb even after the time T3.
- the signal S2 that has reached a high level at time T2 is also input to the negative AND circuit 23.
- the negative logical product circuit 23 outputs a low level signal.
- the delay circuit 24 outputs the low-level signal S3 to the time T4 when a predetermined delay time has elapsed from the time T2 based on the low-level signal from the negative logical product circuit 23.
- the low level signal S3 at this time T4 is input to the gate of the P-type transistor 25.
- the P-type transistor 25 becomes conductive, so that the second supply path R2 including the P-type transistor 25 is opened in the pulse output circuit 7a.
- the signal S1 rises when the SPAD element 6a is recharged via the second supply path R2.
- the pulse output circuit 7a of the embodiment is provided with a first supply path R1 and a second supply path R2 as supply paths for supplying current to the SPAD element 6a.
- the first supply path R1 includes a P-type transistor 21 and supplies a current to the SPAD element 6a in the initial state and when avalanche amplification is occurring in the SPAD element 6a.
- the second supply path R2 includes the P-type transistor 25, and supplies a current to the SPAD element 6a after the avalanche amplification is stopped in the SPAD element 6a.
- the internal resistance of the P-type transistor 25 may be smaller than the internal resistance of the P-type transistor 21. That is, in the embodiment, the resistance value of the second supply path R2 may be smaller than the resistance value of the first supply path R1.
- the internal resistance of the P-type transistor 21 may be set to a resistance value capable of supplying a current value within a range in which the SPAD element 6a can operate well.
- the second supply path R2 does not supply current when avalanche amplification occurs in the SPAD element 6a. Therefore, even if the internal resistance of the P-type transistor 25 is reduced, there is no adverse effect such as avalanche amplification not stopping in the SPAD element 6a.
- the inverter 22 At the time T5 when the signal S1 becomes equal to or higher than the threshold voltage Vth, the inverter 22 outputs the low-level signal S2. Further, the SPAD element 6a returns to the initial voltage Va at time T6.
- the pulse output circuit 7a converts the signal S1 generated by the SPAD element 6a due to the incident of one photon into the first pulse signal P1 by the inverter 22 and outputs the signal S1.
- the first pulse signal P1 is a signal having a pulse width from time T2 to time T5 in the example of FIG.
- the signal S2 that has become low level at time T5 is input to the gate of the P-type transistor 21.
- a predetermined current is supplied to the cathode of the SPAD element 6a via the P-type transistor 21 (that is, the first supply path R1).
- the signal S2 that becomes low level at time T5 is also input to the negative AND circuit 23.
- the negative AND circuit 23 outputs a high-level signal, so that the delay circuit 24 outputs the high-level signal S3 at the time T7 when a predetermined delay time has elapsed from the time T5.
- the P-type transistor 25 is disconnected, and the SPAD element 6a and the pulse output circuit 7a return to the initial state.
- the pulse output circuit 7a of the embodiment provides SPAD by providing a plurality of supply paths (first supply path R1 and second supply path R2) for supplying current to the cathode of the SPAD element 6a.
- the element 6a can be recovered quickly.
- FIG. 7 is a circuit diagram showing a configuration example of the addition unit 8 according to the embodiment of the present disclosure.
- the addition unit 8 has (n-1) ORs. It has a sum circuit 8a-2, 8a-3 ... 8an.
- the output terminal of the pulse output circuit 7a-1 and the output terminal of the pulse output circuit 7a-2 are connected to the input terminal of the OR circuit 8a-2. Further, the output terminal of the OR circuit 8a-2 and the output terminal of the pulse output circuit 7a-3 are connected to the input terminal of the OR circuit 8a-3.
- the OR circuits 8a-2 to 8an are connected in series, and the output terminals of the pulse output circuits 7a-2 to 7an are connected to the OR circuits 8a-2 to 8an, respectively. To. Then, the output terminal of the OR circuit 8an is connected to the pulse shaping unit 9.
- FIG. 8 is an explanatory diagram showing the operation of the addition unit 8 according to the embodiment of the present disclosure in a timing chart.
- FIG. 8 is an explanatory diagram showing the operation of the addition unit 8 according to the embodiment of the present disclosure in a timing chart.
- one photon is incident on one of the SPAD elements 6a (hereinafter, also referred to as “SPAD element A”) at time T11, and another photon is incident at time T14.
- the pulse output circuit 7a (hereinafter, also referred to as “pulse output circuit A”) connected to the SPAD element A is the first having two pulse signals having predetermined pulse widths from the times T11 and T14, respectively.
- the pulse signal P1A is output.
- one photon is incident on the other SPAD element 6a (hereinafter, also referred to as “SPAD element B”) at time T12, time T13, and time T15, respectively.
- the pulse output circuit 7a (hereinafter, also referred to as “pulse output circuit B”) connected to the SPAD element B has three pulse signals having predetermined pulse widths from the times T12, T13, and T15, respectively.
- the first pulse signal P1B is output.
- the addition unit 8 generates an addition signal Pa in which the first pulse signal P1A output from the pulse output circuit A and the first pulse signal P1B output from the pulse output circuit B are added.
- the addition signal Pa has five pulse signals having predetermined pulse widths from the times T11, T12, T13, T14 and T15, respectively.
- the addition unit 8 adds a plurality of first pulse signals P1 generated by each pulse output circuit 7a to generate an addition signal Pa.
- the addition signal Pa has a pulse signal generated due to photons incident on each SPAD element 6a.
- the pulse width of the pulse signal output from the pulse output circuit 7a may be as short as possible. As a result, as shown in FIG. 8, even when a plurality of photons are incident on the pixel array unit 6 in a short time, the plurality of photons can be output as pulse signals.
- FIG. 9 is a circuit diagram showing a configuration example of the pulse shaping unit 9 according to the embodiment of the present disclosure.
- the pulse shaping unit 9 includes an RS flip-flop circuit 41, an OR circuit 42, and a delay circuit 43.
- the S terminal of the RS flip-flop circuit 41 is connected to the output terminal of the adder 8.
- the R terminal of the RS flip-flop circuit 41 is connected to the output terminal of the delay circuit 43.
- the Q terminal of the RS flip-flop circuit 41 is connected to the input terminal of the counter unit 10.
- the XQ terminal of the RS flip-flop circuit 41 is connected to the input terminal of the OR circuit 42.
- the other input terminal of the OR circuit 42 is connected to the output terminal of the adder 8.
- the output terminal of the OR circuit 42 is connected to the input terminal of the delay circuit 43.
- the delay circuit 43 When the high level signal is input from the OR circuit 42, the delay circuit 43 continues to output the low level signal to the R terminal of the RS flip-flop circuit 41 without delay. Further, when the low level signal is input from the OR circuit 42, the delay circuit 43 transmits the high level signal to the RS flip-flop circuit after a predetermined period ⁇ T has elapsed from the input of the low level signal. Output to the R terminal of 41.
- the delay circuit 43 waits after the high-level signal is switched to the low-level signal. After the period ⁇ T has elapsed, a high level signal is output.
- the delay circuit 43 outputs the high level signal to the R terminal of the RS flip-flop circuit 41 when a predetermined period ⁇ T has elapsed since the signal was finally switched from the high level to the low level.
- FIG. 10 is an explanatory diagram showing the operation of the pulse shaping unit 9 according to the embodiment of the present disclosure in a timing chart.
- a low-level signal is input to the S terminal of the RS flip-flop circuit 41. Therefore, the Q terminal of the RS flip-flop circuit 41 outputs a low-level signal to the RS flip-flop circuit.
- the XQ terminal of 41 outputs a high level signal.
- a high-level signal is input to the OR circuit 42 from the XQ terminal of the RS flip-flop circuit 41, a high-level signal is output from the OR circuit 42 and a low-level signal is output from the delay circuit 43. Is output.
- the delay circuit 43 outputs a high-level signal to the R terminal of the RS flip-flop circuit 41 at the time T25 when the predetermined period ⁇ T has elapsed from the time T24.
- a low-level signal is output from the Q terminal of the RS flip-flop circuit 41 at time T26, and a high-level signal is output from the XQ terminal of the RS flip-flop circuit 41.
- a high-level signal is output from the OR circuit 42 at time T27, and such a high-level signal is input to the delay circuit 43. Then, at time T28, a low-level signal is output from the delay circuit 43, and the pulse shaping unit 9 returns to the initial state.
- the pulse shaping unit 9 shapes the addition signal Pa having a pulse width from time T21 to time T23 into a second pulse signal P2 having a pulse width from time T22 to time T26 and outputs it. To do.
- the pulse shaping unit 9 shapes the input pulse signal so as to lengthen it to a width based on the predetermined period ⁇ T. That is, in the embodiment, the first pulse signal P1 whose pulse width is shortened as much as possible by the pulse output unit 7 is shaped into a pulse width that can be processed by the counter unit 10 in the subsequent stage.
- the pulse shaping unit 9 shapes the pulse width so as to be further lengthened with reference to the new pulse signal. That is, the pulse shaping unit 9 according to the embodiment shapes the addition signal Pa into a second pulse signal P2 having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ⁇ T. To do.
- the pulse shaping unit 9 can be processed by the counter unit 10 in the subsequent stage, and the pulse width is based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ⁇ T.
- the second pulse signal P2 can be output to the counter unit 10.
- FIG. 11 is an explanatory diagram showing the operation of the pulse shaping unit 9 according to the embodiment of the present disclosure in a timing chart, and is a diagram showing a case where the addition signal Pa shown in the example of FIG. 8 is processed by the pulse shaping unit 9. is there.
- the next pulse signal does not rise until a predetermined period ⁇ T elapses after the pulse signal Pa-1 that rises at time T11. Therefore, the pulse signal Pa-1 rises at the time T11 and is shaped into a pulse signal P2-1 having a pulse width from the time T11 to the time T11a after a predetermined period ⁇ T has elapsed.
- the addition signal Pa shown in the example of FIG. 11 has a pulse signal Pa-3 that rises by the lapse of a predetermined period ⁇ T after the pulse signal Pa-2 that rises at time T12. Therefore, the pulse signals Pa-2 and Pa-3 rise at time T12 and are shaped into pulse signals P2-2 having a pulse width from time T13 to time T13a after a predetermined period ⁇ T has elapsed.
- the addition signal Pa shown in the example of FIG. 11 has a pulse signal Pa-5 that rises by the lapse of a predetermined period ⁇ T after the pulse signal Pa-4 that rises at time T14. Therefore, the pulse signals Pa-4 and Pa-5 rise at time T14 and are shaped into pulse signals P2-3 having a pulse width from time T15 to time T15a after a predetermined period ⁇ T has elapsed.
- the pulse signal shaping method is not limited to such an example.
- the pulse width is doubled, and if three pulse signals are input before the predetermined period elapses, 3 is formed. It may be shaped to double the pulse width.
- the pulse shaping unit 9 may shape the pulse signal to a pulse width based on the number of pulse signals input before the lapse of a predetermined period.
- FIG. 12 is a circuit diagram showing a configuration example of the counter unit 10 according to the embodiment of the present disclosure.
- the counter unit 10 includes a counting pulse output unit 51, a logical product circuit 52, and a counting counting unit 53.
- the counting pulse output unit 51 outputs a pulse signal having a narrow pulse width (hereinafter, also referred to as a counting pulse signal) to the input terminal of the logic product circuit 52 at regular time intervals. For example, the counting pulse output unit 51 outputs a counting pulse signal at a time interval shorter than the above period ⁇ T.
- the input terminal of the AND circuit 52 is connected to the output terminal of the counting pulse output unit 51 and the output terminal of the pulse shaping unit 9.
- the output terminal of the AND circuit 52 is connected to the input terminal of the counting / counting unit 53. Further, the output terminal of the counting / counting unit 53 is connected to the control unit 11.
- FIG. 13 is an explanatory diagram showing the operation of the counter unit 10 according to the embodiment of the present disclosure in a timing chart.
- the second pulse signal P2 having a pulse signal P2-4 having a pulse width from time T31 to time T32 and a pulse signal P2-5 having a pulse width from time T33 to time T34 is A case where the signal is output from the pulse shaping unit 9 will be described.
- the pulse signal P2-4 is a pulse signal having the same pulse width as the pulse signal output when one photon is input to the SPAD element 6a.
- the counting pulse output unit 51 outputs a counting pulse signal so that the two counting pulse signals overlap with the pulse signal output when one photon is input to the SPAD element 6a. Output.
- the AND circuit 52 outputs a pulse signal having two consecutive counts between the time T31 and the time T32 to the count counting unit 53. Further, the AND circuit 52 outputs a pulse signal having 11 counts continuous from the time T33 to the time T34 to the count counting unit 53.
- the count counting unit 53 counts the number of continuous pulse signals at predetermined intervals.
- the predetermined interval is the same interval as the output interval of the counting pulse signal. Then, the count counting unit 53 counts the number of photons input to the plurality of SPAD elements 6a based on the number of such counted pulse signals.
- the counter unit 10 counts the number corresponding to the pulse width of the second pulse signal P2, for example, the number of continuous pulse signals described above as the number of photons incident on the plurality of SPAD elements 6a.
- the embodiment it is possible to convert the second pulse signal P2 whose pulse width is long due to the incident of a plurality of photons at short time intervals into the number of photons based on the long pulse width.
- the number of photons is obtained based on the number of rising pulses signals (that is, the number of pulse signals) in the second pulse signal P2, the number of photons from time T31 to time T34 is It is calculated as "2 pieces".
- the difference between the minimum value and the maximum value of the number of measurable photons can be increased, so that the dynamic range of the distance measuring device 1 can be expanded.
- the pulse width of the first pulse signal P1 may be shorter than the pulse width that can be processed by the counter unit 10.
- the dead time of the SPAD element 6a can be minimized without being limited to the specifications of the counter unit 10. Therefore, according to the embodiment, it is possible to prevent the photons from being undetectable due to the incident of photons during the dead time of the SPAD element 6a.
- the pulse width of the second pulse signal P2 may be longer than the pulse width that can be processed by the counter unit 10. As a result, the second pulse signal P2 can be processed by the counter unit 10 without any problem.
- FIG. 14 is a diagram for explaining the difference in signal processing between the embodiment of the present disclosure, Reference Example 1 and Reference Example 2.
- Reference example 1 is an example in which the pulse output circuit 7a has only one supply path for supplying current to the SPAD element 6a.
- the recovery time of the SPAD element 6a can be shortened by increasing the value of the current supplied from the supply path.
- the recovery time of the SPAD element 6a in Reference Example 1 is longer than the recovery time of the SPAD element 6a in the embodiment (for example, about several times).
- the first pulse signal P1 output from the pulse output circuit A is formed by two pulse signals having a long pulse width and is output from the pulse output circuit B.
- the first pulse signal P1 is formed by one pulse signal having a longer pulse width.
- the addition signal Pa is formed by one pulse signal having a very long pulse width, so that the dynamic range is reduced.
- Reference example 2 is an example in which the pulse width of the first pulse signal P1 is extended to a pulse width that can be processed by the counter unit 10 in the pulse output circuit 7a.
- a signal that can be processed by the counter unit 10 by adding the first pulse signal P1 output from the pulse output circuit A and the first pulse signal P1 output from the pulse output circuit B by the addition unit 8. Can be obtained.
- the first pulse signal P1 of the pulse output circuit B output based on these two photons is It is the same as the pulse width of the first pulse signal P1 output based on one photon.
- the pulse output circuit B detects such new photons. can do.
- the difference between the minimum value and the maximum value of the number of measurable photons can be increased, so that the dynamic range of the distance measuring device 1 can be expanded.
- the control circuit includes a pulse output unit 7, an addition unit 8, and a pulse shaping unit 9.
- the pulse output unit 7 outputs a plurality of first pulse signals P1 corresponding to the signals generated by the plurality of SPAD elements 6a, respectively.
- the addition unit 8 adds a plurality of first pulse signals P1 output from the pulse output unit 7 and converts them into an addition signal Pa.
- the pulse shaping unit 9 shapes the addition signal Pa into a second pulse signal P2 having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ⁇ T.
- the dynamic range of the ranging device 1 can be expanded.
- control circuit further includes a counter unit 10 that counts a number corresponding to the pulse width of the second pulse signal P2 as the number of photons incident on the plurality of SPAD elements 6a.
- the second pulse signal P2 whose pulse width is lengthened due to the incident of a plurality of photons at short time intervals can be converted into the number of photons based on the lengthened pulse width.
- the pulse width of the first pulse signal P1 is shorter than the pulse width that can be processed by the counter unit 10
- the pulse width of the second pulse signal P2 is a pulse that can be processed by the counter unit 10. Longer than the width.
- the dead time of the SPAD element 6a can be minimized, and the second pulse signal P2 can be processed by the counter unit 10 without any problem.
- the pulse output unit 7 has a first supply path R1 and a second supply path R2.
- the first supply path R1 supplies a current to the SPAD element 6a when avalanche amplification is occurring in the SPAD element 6a.
- the second supply path R2 supplies a current to the SPAD element 6a after the avalanche amplification is stopped in the SPAD element 6a.
- the recovery time of the SPAD element 6a can be shortened, so that the dead time of the SPAD element 6a can be shortened.
- the present technology can also have the following configurations.
- a pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by a plurality of SPAD (Single Photon Avalanche Diode) elements, and a pulse output unit.
- An addition unit that adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal.
- a pulse shaping unit that shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
- Control circuit including.
- the pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
- the pulse output unit connects to the first supply path for supplying a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element.
- the control circuit according to any one of (1) to (3) above, which has a second supply path for supplying an electric current.
- a light source that irradiates the object to be measured with light, A plurality of SPAD elements that output a signal when the light reflected from the object to be measured is received, and A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by the plurality of SPAD elements and a plurality of the first pulse signals output from the pulse output unit are added and converted into an addition signal.
- a control having an addition unit for shaping the addition signal and a pulse shaping unit for shaping the addition signal into a second pulse signal having a pulse width based on the number of pulse signals in the addition signal generated at a time interval shorter than a predetermined period. Circuit and Distance measuring system equipped with.
- the control circuit The ranging system according to (5) above, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements.
- the pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
- the distance measuring system according to (6), wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit.
- the pulse output unit connects to the first supply path that supplies a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element.
- the distance measuring system according to any one of (5) to (7) above, which has a second supply path for supplying an electric current.
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Abstract
A control circuit according to the present disclosure is provided with a pulse output unit (7), an addition unit (8), and a pulse shaping unit (9). The pulse output unit (7) outputs a plurality of first pulse signals (P1) in accordance with signals respectively generated in a plurality of single-photon avalanche diode (SPAD) elements (6a). The addition unit (8) adds the plurality of first pulse signals (P1) outputted from the pulse output unit (7) and converts same into a summed signal (Pa). The pulse shaping unit (9) shapes the summed signal (Pa) into second pulse signals (P2) of pulse width based on the number of pulse signals within a summed signal (Pa) generated in a time interval shorter than a prescribed period (ΔT).
Description
本開示は、制御回路および測距システムに関する。
The present disclosure relates to a control circuit and a ranging system.
光を用いて被測定物までの距離を測定する測距方式の一つとして、直接ToF(Time of Flight)方式と呼ばれる測距手法が知られている。かかる直接ToF方式では、光源から射出された光が被測定物により反射された反射光を受光素子により受光し、光が射出されてから反射光として受光されるまでの時間に基づき対象までの距離を計測する(たとえば、特許文献1参照)。
As one of the distance measurement methods that measure the distance to the object to be measured using light, a distance measurement method called the direct ToF (Time of Flight) method is known. In such a direct ToF method, the light emitted from the light source receives the reflected light reflected by the object to be measured by the light receiving element, and the distance to the target is based on the time from the emission of the light to the reception as the reflected light. (See, for example, Patent Document 1).
本開示では、ダイナミックレンジを拡大することができる制御回路および測距システムを提案する。
This disclosure proposes a control circuit and a distance measuring system capable of expanding the dynamic range.
本開示によれば、制御回路が提供される。制御回路は、パルス出力部と、加算部と、パルス整形部とを備える。パルス出力部は、複数のSPAD(Single Photon Avalanche Diode)素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力する。加算部は、前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する。パルス整形部は、前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形する。
According to the present disclosure, a control circuit is provided. The control circuit includes a pulse output unit, an addition unit, and a pulse shaping unit. The pulse output unit outputs a plurality of first pulse signals corresponding to the signals generated by the plurality of SPAD (Single Photon Avalanche Diode) elements. The addition unit adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal. The pulse shaping unit shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
本開示によれば、ダイナミックレンジを拡大することができる。なお、ここに記載された効果は必ずしも限定されるものではなく、本開示中に記載されたいずれかの効果であってもよい。
According to this disclosure, the dynamic range can be expanded. The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.
以下に、本開示の各実施形態について図面に基づいて詳細に説明する。なお、以下の各実施形態において、同一の部位には同一の符号を付することにより重複する説明を省略する。
Hereinafter, each embodiment of the present disclosure will be described in detail based on the drawings. In addition, in each of the following embodiments, the same portions are denoted by the same reference numerals and overlapping description will be omitted.
光を用いて被測定物までの距離を測定する測距方式の一つとして、直接ToF方式と呼ばれる測距手法が知られている。かかる直接ToF方式では、光源から射出された光が被測定物により反射された反射光を受光素子により受光し、光が射出されてから反射光として受光されるまでの時間に基づき対象までの距離を計測する。
As one of the distance measuring methods for measuring the distance to the object to be measured using light, a distance measuring method called a direct ToF method is known. In such a direct ToF method, the light emitted from the light source receives the reflected light reflected by the object to be measured by the light receiving element, and the distance to the target is based on the time from the emission of the light to the reception as the reflected light. To measure.
しかしながら、上記の従来技術では、受光素子として用いられるSPAD素子のデッドタイムより短い間隔で再度SPAD素子が受光した場合、SPAD素子から出力されるパルス信号は数が増えずに幅だけが長くなってしまう。
However, in the above-mentioned conventional technique, when the SPAD element receives light again at an interval shorter than the dead time of the SPAD element used as the light receiving element, the number of pulse signals output from the SPAD element does not increase and only the width becomes longer. It ends up.
これにより、SPAD素子から出力されるパルス信号の数に基づいて入射した光子の数を計測する場合に、入射光子数が多くなるにしたがい、計測された光子の数とSPAD素子に実際入射した光子の数との差異が大きくなる場合がある。
As a result, when measuring the number of incident photons based on the number of pulse signals output from the SPAD element, as the number of incident photons increases, the measured number of photons and the photons actually incident on the SPAD element The difference from the number of is large.
したがって、計測可能な光子数の最小値と最大値との差が小さくなってしまうことから、測距システムのダイナミックレンジが減少してしまう恐れがある。
Therefore, the difference between the minimum and maximum number of photons that can be measured becomes small, and the dynamic range of the distance measurement system may decrease.
そこで、上述の問題点を克服し、ダイナミックレンジを拡大することができる制御回路および測距システムの実現が期待されている。
Therefore, it is expected to realize a control circuit and a distance measuring system that can overcome the above-mentioned problems and expand the dynamic range.
[測距方法]
本開示は、光を用いて測距を行う技術に関するものである。そこで、本開示の実施形態の理解を容易とするために、図1および図2を参照しながら、実施形態に適用可能な測距方法について説明する。 [Distance measurement method]
The present disclosure relates to a technique for performing distance measurement using light. Therefore, in order to facilitate understanding of the embodiment of the present disclosure, a distance measuring method applicable to the embodiment will be described with reference to FIGS. 1 and 2.
本開示は、光を用いて測距を行う技術に関するものである。そこで、本開示の実施形態の理解を容易とするために、図1および図2を参照しながら、実施形態に適用可能な測距方法について説明する。 [Distance measurement method]
The present disclosure relates to a technique for performing distance measurement using light. Therefore, in order to facilitate understanding of the embodiment of the present disclosure, a distance measuring method applicable to the embodiment will be described with reference to FIGS. 1 and 2.
図1は、本開示の実施形態に適用可能である直接ToF方式による測距を模式的に示す図である。実施形態では、測距方式として直接ToF方式を適用する。
FIG. 1 is a diagram schematically showing distance measurement by the direct ToF method applicable to the embodiment of the present disclosure. In the embodiment, the ToF method is directly applied as the distance measuring method.
かかる直接ToF方式は、光源部2からの射出光L1が被測定物100により反射した反射光L2を受光部3により受光し、光の射出タイミングと受光タイミングとの差分の時間に基づき測距を行う方式である。
In such a direct ToF method, the light emitted from the light source unit 2 L1 receives the reflected light L2 reflected by the object 100 to be measured by the light receiving unit 3, and the distance is measured based on the time difference between the light emission timing and the light receiving timing. It is a method to do.
測距装置1は、光源部2と、受光部3とを備える。測距装置1は、測距システムの一例である。光源部2は、たとえばレーザダイオードである光源4(図3参照)を有し、レーザ光をパルス状に発光するように駆動される。
The distance measuring device 1 includes a light source unit 2 and a light receiving unit 3. The distance measuring device 1 is an example of a distance measuring system. The light source unit 2 has, for example, a light source 4 (see FIG. 3) which is a laser diode, and is driven so as to emit laser light in a pulsed manner.
光源部2からの射出光L1は、被測定物100により反射され、反射光L2として受光部3に受光される。受光部3は、光電変換によって光を電気信号に変換する画素アレイ部6(図3参照)を含み、受光した光に応じた信号を出力する。
The emitted light L1 from the light source unit 2 is reflected by the object to be measured 100 and is received by the light receiving unit 3 as reflected light L2. The light receiving unit 3 includes a pixel array unit 6 (see FIG. 3) that converts light into an electric signal by photoelectric conversion, and outputs a signal corresponding to the received light.
ここで、光源部2が発光した時刻(発光タイミング)を時間t0、光源部2からの射出光L1が被測定物100により反射された反射光L2を受光部3が受光した時刻(受光タイミング)を時間t1とする。
Here, the time when the light source unit 2 emits light (light emission timing) is time t 0 , and the time when the light receiving unit 3 receives the reflected light L2 reflected by the object 100 from the light source unit 2 (light receiving timing). ) Is time t 1 .
定数cを光速度(2.9979×108[m/sec])とすると、測距装置1と被測定物100との間の距離Dは、次式(1)により計算される。
D=(c/2)×(t1-t0) …(1) If the constant c is the light velocity (2.9979 × 10 8 [m / sec]), the distance D between thedistance measurement apparatus 1 and the object to be measured 100 is calculated by the following equation (1).
D = (c / 2) × (t 1 −t 0 )… (1)
D=(c/2)×(t1-t0) …(1) If the constant c is the light velocity (2.9979 × 10 8 [m / sec]), the distance D between the
D = (c / 2) × (t 1 −t 0 )… (1)
なお、測距装置1は、上述の処理を、複数回繰り返して実行するとよい。また、受光部3は、複数のSPAD素子6a(図4参照)を有し、各SPAD素子6aに反射光L2が受光された各受光タイミングに基づき距離Dをそれぞれ算出してもよい。
The distance measuring device 1 may repeat the above-mentioned processing a plurality of times. Further, the light receiving unit 3 may have a plurality of SPAD elements 6a (see FIG. 4), and the distance D may be calculated based on each light receiving timing when the reflected light L2 is received by each SPAD element 6a.
測距装置1は、発光タイミングの時間t0から受光部3に光が受光された受光タイミングまでの時間tm(以下、「受光時間tm」とも呼称する。)を階級(ビン(bins))に基づき分類し、ヒストグラムを生成する。
The distance measuring device 1 sets the time t m (hereinafter, also referred to as “light receiving time t m ”) from the light emitting timing time t 0 to the light receiving timing when the light is received by the light receiving unit 3 (bins). ) To classify and generate a histogram.
図2は、本開示の実施形態に適用可能である受光部3が受光した時刻に基づく一例のヒストグラムを示す図である。図2において、横軸はビン、縦軸はビン毎の頻度を示す。ビンは、受光時間tmを所定の単位時間d毎に分類したものである。
FIG. 2 is a diagram showing an example of a histogram based on the time when the light receiving unit 3 is applicable, which is applicable to the embodiment of the present disclosure. In FIG. 2, the horizontal axis indicates the bin and the vertical axis indicates the frequency for each bin. The bins are obtained by classifying the light receiving time t m for each predetermined unit time d.
具体的には、ビン#0が0≦tm<d、ビン#1がd≦tm<2×d、ビン#2が2×d≦tm<3×d、…、ビン#(N-2)が(N-2)×d≦tm<(N-1)×dとなる。受光部3の露光時間を時間tepとした場合、tep=N×dとなる。
Specifically, bin # 0 is 0 ≦ t m <d, bin # 1 is d ≦ t m <2 × d, bin # 2 is 2 × d ≦ t m <3 × d, ..., Bin # (N). -2) is (N-2) × d ≦ t m <(N-1) × d. When the exposure time of the light receiving unit 3 is time t ep , t ep =N×d.
測距装置1は、受光時間tmを取得した回数をビンに基づき計数してビン毎の頻度200を求め、ヒストグラムを生成する。ここで、受光部3は、光源部2からの射出光L1が反射された反射光L2以外の光も受光する。
The distance measuring device 1 counts the number of times the light receiving time t m is acquired based on the bin, obtains the frequency 200 for each bin, and generates a histogram. Here, the light receiving unit 3 also receives light other than the reflected light L2 from which the emitted light L1 emitted from the light source unit 2 is reflected.
たとえば、対象となる反射光L2以外の光の例として、測距装置1の周囲の環境光がある。かかる環境光は、受光部3にランダムに入射する光であって、ヒストグラムにおける環境光による環境光成分201は、対象となる反射光L2に対するノイズとなる。
For example, as an example of light other than the target reflected light L2, there is ambient light around the distance measuring device 1. Such ambient light is light that is randomly incident on the light receiving unit 3, and the ambient light component 201 due to the ambient light in the histogram becomes noise for the target reflected light L2.
一方、対象となる反射光L2は、特定の距離に応じて受光される光であって、ヒストグラムにおいてアクティブ光成分202として現れる。このアクティブ光成分202内のピークの頻度に対応するビンが、被測定物100の距離Dに対応するビンとなる。
On the other hand, the target reflected light L2 is light received according to a specific distance and appears as an active light component 202 in the histogram. The bin corresponding to the frequency of the peak in the active light component 202 is the bin corresponding to the distance D of the object to be measured 100.
測距装置1は、そのビンの代表時間(たとえばビンの中央の時間)を上述した時間t1として取得することで、上述した式(1)に従い、被測定物100までの距離Dを算出することができる。このように、複数の受光結果を用いることで、ランダムなノイズに対して適切な測距が実行可能となる。
The distance measuring device 1 acquires the representative time of the bottle (for example, the time in the center of the bottle) as the time t 1 described above, and calculates the distance D to the object to be measured 100 according to the above formula (1). be able to. As described above, by using a plurality of light reception results, it is possible to perform appropriate distance measurement for random noise.
[測距装置の構成]
つづいて、実施形態に係る測距装置1の構成について、図3および図4を参照しながら説明する。図3は、本開示の実施形態に係る測距装置1の構成例を示すブロック図である。上述のように、測距装置1は、光源部2と、受光部3とを備える。 [Configuration of ranging device]
Next, the configuration of thedistance measuring device 1 according to the embodiment will be described with reference to FIGS. 3 and 4. FIG. 3 is a block diagram showing a configuration example of the distance measuring device 1 according to the embodiment of the present disclosure. As described above, the distance measuring device 1 includes a light source unit 2 and a light receiving unit 3.
つづいて、実施形態に係る測距装置1の構成について、図3および図4を参照しながら説明する。図3は、本開示の実施形態に係る測距装置1の構成例を示すブロック図である。上述のように、測距装置1は、光源部2と、受光部3とを備える。 [Configuration of ranging device]
Next, the configuration of the
光源部2は、光源4と、光源駆動部5とを有する。光源4は、たとえば、垂直共振器面発光レーザ(VCSEL:Vertical Cavity Surface Emitting LASER)などのレーザダイオードで構成される。なお、光源4は、VCSELに限られず、レーザダイオードがライン上に配列されたレーザダイオードアレイなどを用いてもよい。
The light source unit 2 has a light source 4 and a light source driving unit 5. The light source 4 is composed of, for example, a laser diode such as a vertical cavity surface emitting laser (VCSEL: Vertical Cavity Surface Emitting LASER). The light source 4 is not limited to the VCSEL, and a laser diode array in which laser diodes are arranged on a line may be used.
光源駆動部5は、光源4を駆動する。光源駆動部5は、たとえば、受光部3の制御部11からの発光制御信号に基づき、光源4から所定のタイミングおよびパルス幅を有する射出光L1が出射されるように光源4を駆動する。
The light source driving unit 5 drives the light source 4. For example, the light source driving unit 5 drives the light source 4 so that the emitted light L1 having a predetermined timing and pulse width is emitted from the light source 4 based on the light emission control signal from the control unit 11 of the light receiving unit 3.
光源駆動部5は、たとえば、ライン上に配列されるレーザダイオードを有する光源4から、レーザ光がラインに垂直の方向にスキャンされるように光源4を駆動することができる。
The light source driving unit 5 can drive the light source 4 so that the laser light is scanned in the direction perpendicular to the line, for example, from the light source 4 having the laser diodes arranged on the line.
受光部3は、画素アレイ部6と、パルス出力部7と、加算部8と、パルス整形部9と、カウンター部10と、制御部11とを有する。
The light receiving unit 3 includes a pixel array unit 6, a pulse output unit 7, an addition unit 8, a pulse shaping unit 9, a counter unit 10, and a control unit 11.
画素アレイ部6は、2次元格子状に配列される複数のSPAD素子6a(図4参照)を有する。かかるSPAD素子6aは、アバランシ増倍が発生する大きな逆バイアス電圧をカソードに印加することにより、1光子の入射に応じて発生した電子に起因して、内部でアバランシ増倍が生じる。
The pixel array unit 6 has a plurality of SPAD elements 6a (see FIG. 4) arranged in a two-dimensional lattice pattern. In such a SPAD element 6a, when a large reverse bias voltage that causes an avalanche multiplier is applied to the cathode, the avalanche multiplier is internally generated due to the electrons generated in response to the incident of one photon.
すなわち、SPAD素子6aは、1光子の入射に応じて大電流が流れる特性を有する。そして、SPAD素子6aでは、かかる特性を利用することで、反射光L2に含まれる1光子の入射を高感度で検知することができる。
That is, the SPAD element 6a has a characteristic that a large current flows according to the incident of one photon. Then, the SPAD element 6a can detect the incident of one photon contained in the reflected light L2 with high sensitivity by utilizing such a characteristic.
画素アレイ部6における複数のSPAD素子6aの動作は、制御部11によって制御される。たとえば、制御部11は、各SPAD素子6aからの信号の読み出しを、行方向にn画素、列方向にm画素の、(n×m)個のSPAD素子6aを含むブロック毎に制御することができる。
The operation of the plurality of SPAD elements 6a in the pixel array unit 6 is controlled by the control unit 11. For example, the control unit 11 may control the reading of signals from each SPAD element 6a for each block including (n × m) SPAD elements 6a having n pixels in the row direction and m pixels in the column direction. it can.
また、制御部11は、当該ブロックを単位として、各SPAD素子6aを行方向にスキャンし、さらに行毎に列方向にスキャンして、各SPAD素子6aから信号を読み出すことができる。
Further, the control unit 11 can scan each SPAD element 6a in the row direction and further scan each row in the column direction in units of the block, and can read a signal from each SPAD element 6a.
なお、実施形態において、制御部11は、各SPAD素子6aからそれぞれ単独に信号を読み出してもよい。画素アレイ部6のSPAD素子6aで発生する信号は、パルス出力部7のパルス出力回路7a(図5参照)に供給される。
In the embodiment, the control unit 11 may independently read a signal from each SPAD element 6a. The signal generated by the SPAD element 6a of the pixel array unit 6 is supplied to the pulse output circuit 7a (see FIG. 5) of the pulse output unit 7.
パルス出力部7は、SPAD素子6aと同じ数のパルス出力回路7aを有する。かかるパルス出力回路7aは、対応するSPAD素子6aで発生する信号に応じて、所定の第1パルス信号P1(図6参照)をデジタル信号として加算部8に出力する。
The pulse output unit 7 has the same number of pulse output circuits 7a as the SPAD elements 6a. The pulse output circuit 7a outputs a predetermined first pulse signal P1 (see FIG. 6) to the adder 8 as a digital signal according to the signal generated by the corresponding SPAD element 6a.
すなわち、パルス出力部7は、複数のSPAD素子6aでそれぞれ発生する信号に応じた複数の第1パルス信号P1を出力する。かかるパルス出力部7およびパルス出力回路7aの詳細については後述する。
That is, the pulse output unit 7 outputs a plurality of first pulse signals P1 corresponding to the signals generated by the plurality of SPAD elements 6a, respectively. Details of the pulse output unit 7 and the pulse output circuit 7a will be described later.
加算部8は、パルス出力部7から出力された複数の第1パルス信号P1を加算して、加算信号Pa(図8参照)を生成する。かかる加算部8の詳細については後述する。
The addition unit 8 adds a plurality of first pulse signals P1 output from the pulse output unit 7 to generate an addition signal Pa (see FIG. 8). The details of the addition unit 8 will be described later.
パルス整形部9は、加算信号Paを第2パルス信号P2(図11参照)に整形する。この第2パルス信号P2とは、所定の期間ΔT(図10参照)より短い時間間隔で発生する加算信号Pa内のパルス信号の数に基づいたパルス幅を有する信号である。かかるパルス整形部9の詳細については後述する。
The pulse shaping unit 9 shapes the addition signal Pa into the second pulse signal P2 (see FIG. 11). The second pulse signal P2 is a signal having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than a predetermined period ΔT (see FIG. 10). Details of the pulse shaping unit 9 will be described later.
カウンター部10は、第2パルス信号P2のパルス幅に応じた数を、複数のSPAD素子6aに入射した光子の数としてカウントする。かかるカウンター部10の詳細については後述する。
The counter unit 10 counts the number corresponding to the pulse width of the second pulse signal P2 as the number of photons incident on the plurality of SPAD elements 6a. Details of the counter unit 10 will be described later.
制御部11は、たとえば予め組み込まれるプログラムに従い、測距装置1の全体の動作を制御する。たとえば、制御部11は、光源駆動部5を制御することにより、光源4の発光タイミングを制御する。
The control unit 11 controls the overall operation of the distance measuring device 1 according to, for example, a program incorporated in advance. For example, the control unit 11 controls the light source driving unit 5 to control the light emission timing of the light source 4.
また、制御部11は、カウンター部10から出力されるカウント数に基づいて、図2に示したヒストグラムを生成する。また、制御部11は、生成されたヒストグラムのデータに基づいて所定の演算処理を行い、被測定物100までの距離Dを算出する。
Further, the control unit 11 generates the histogram shown in FIG. 2 based on the count number output from the counter unit 10. Further, the control unit 11 performs a predetermined arithmetic process based on the generated histogram data, and calculates the distance D to the object to be measured 100.
図4は、本開示の実施形態に係る受光部3に適用可能であるデバイスの構成の例を示す模式図である。図4において、受光部3は、それぞれ半導体チップからなる受光チップ3aとロジックチップ3bとが積層されて構成される。なお、図4では、理解の容易のため、受光チップ3aとロジックチップ3bとが分離された状態で示している。
FIG. 4 is a schematic diagram showing an example of a device configuration applicable to the light receiving unit 3 according to the embodiment of the present disclosure. In FIG. 4, the light receiving unit 3 is configured by laminating a light receiving chip 3a made of a semiconductor chip and a logic chip 3b, respectively. In FIG. 4, the light receiving chip 3a and the logic chip 3b are shown in a separated state for easy understanding.
受光チップ3aには、画素アレイ部6の領域に複数のSPAD素子6aが2次元格子状に配列される。ロジックチップ3bには、パルス出力部7と、加算部8と、パルス整形部9と、カウンター部10と、制御部11(図示せず)とが設けられる。なお、受光チップ3aおよびロジックチップ3bの構成は、図4の例に限定されない。
On the light receiving chip 3a, a plurality of SPAD elements 6a are arranged in a two-dimensional lattice pattern in the region of the pixel array unit 6. The logic chip 3b is provided with a pulse output unit 7, an addition unit 8, a pulse shaping unit 9, a counter unit 10, and a control unit 11 (not shown). The configuration of the light receiving chip 3a and the logic chip 3b is not limited to the example of FIG.
[パルス出力部の構成および動作]
つづいて、実施形態に係るパルス出力部7の構成および動作について、図5および図6を参照しながら説明する。図5は、本開示の実施形態に係るパルス出力部7のパルス出力回路7aの構成例を示す回路図である。 [Configuration and operation of pulse output unit]
Subsequently, the configuration and operation of thepulse output unit 7 according to the embodiment will be described with reference to FIGS. 5 and 6. FIG. 5 is a circuit diagram showing a configuration example of the pulse output circuit 7a of the pulse output unit 7 according to the embodiment of the present disclosure.
つづいて、実施形態に係るパルス出力部7の構成および動作について、図5および図6を参照しながら説明する。図5は、本開示の実施形態に係るパルス出力部7のパルス出力回路7aの構成例を示す回路図である。 [Configuration and operation of pulse output unit]
Subsequently, the configuration and operation of the
図5に示すように、パルス出力部7は、パルス出力回路7aを有する。パルス出力回路7aは、1つのSPAD素子6aに対して1つ設けられる。すなわち、パルス出力回路7aは、パルス出力部7内にSPAD素子6aと同じ数だけ設けられる。
As shown in FIG. 5, the pulse output unit 7 has a pulse output circuit 7a. One pulse output circuit 7a is provided for one SPAD element 6a. That is, the same number of pulse output circuits 7a as the SPAD elements 6a are provided in the pulse output unit 7.
そして、各パルス出力回路7aは、それぞれ対応するSPAD素子6aに接続される。なお、図5では、理解の容易のため、SPAD素子6aとパルス出力回路7aとをそれぞれ1つずつ図示する。
Then, each pulse output circuit 7a is connected to the corresponding SPAD element 6a. In FIG. 5, for easy understanding, one SPAD element 6a and one pulse output circuit 7a are shown.
パルス出力回路7aは、P型トランジスタ21と、インバータ22と、否定論理積回路23と、遅延回路24と、P型トランジスタ25とを有する。また、遅延回路24は、4つのインバータ31~34を有する。
The pulse output circuit 7a includes a P-type transistor 21, an inverter 22, a negative logic product circuit 23, a delay circuit 24, and a P-type transistor 25. Further, the delay circuit 24 has four inverters 31 to 34.
P型トランジスタ21のソースは電源電圧Vddに接続され、P型トランジスタ21のドレインは信号線26に接続され、P型トランジスタ21のゲートはノード27に接続される。
The source of the P-type transistor 21 is connected to the power supply voltage Vdd, the drain of the P-type transistor 21 is connected to the signal line 26, and the gate of the P-type transistor 21 is connected to the node 27.
かかる信号線26は、画素アレイ部6の接続部6bを介して、SPAD素子6aのカソードとインバータ22の入力端子との間を接続する。また、SPAD素子6aのアノードは接地され、インバータ22の出力端子はノード27を介して加算部8(図3参照)に接続される。
The signal line 26 connects between the cathode of the SPAD element 6a and the input terminal of the inverter 22 via the connection unit 6b of the pixel array unit 6. Further, the anode of the SPAD element 6a is grounded, and the output terminal of the inverter 22 is connected to the adder 8 (see FIG. 3) via the node 27.
否定論理積回路23の2つの入力端子は、ノード27とインバータ34の出力端子とに接続される。否定論理積回路23の出力端子は、インバータ31の入力端子に接続される。
The two input terminals of the negative AND circuit 23 are connected to the node 27 and the output terminal of the inverter 34. The output terminal of the negative conjunction circuit 23 is connected to the input terminal of the inverter 31.
インバータ31の出力端子は、インバータ32の入力端子に接続される。インバータ32の出力端子は、インバータ33の入力端子に接続される。インバータ33の出力端子は、インバータ34の入力端子に接続される。
The output terminal of the inverter 31 is connected to the input terminal of the inverter 32. The output terminal of the inverter 32 is connected to the input terminal of the inverter 33. The output terminal of the inverter 33 is connected to the input terminal of the inverter 34.
すなわち、パルス出力回路7aでは、否定論理積回路23および4つのインバータ31~34がリングオシレータとなる。
That is, in the pulse output circuit 7a, the negative AND circuit 23 and the four inverters 31 to 34 serve as ring oscillators.
P型トランジスタ25のソースは電源電圧Vddに接続され、P型トランジスタ25のドレインは信号線26に接続され、P型トランジスタ25のゲートはインバータ34の出力端子に接続される。
The source of the P-type transistor 25 is connected to the power supply voltage Vdd, the drain of the P-type transistor 25 is connected to the signal line 26, and the gate of the P-type transistor 25 is connected to the output terminal of the inverter 34.
ここまで説明したパルス出力回路7aの初期状態では、P型トランジスタ21のゲートにローレベルの信号S2がノード27を介して入力される。したがって、パルス出力回路7aの初期状態では、P型トランジスタ21を含んだ第1の供給路R1によって、SPAD素子6aのカソードに所定の電流が供給される。
In the initial state of the pulse output circuit 7a described so far, the low-level signal S2 is input to the gate of the P-type transistor 21 via the node 27. Therefore, in the initial state of the pulse output circuit 7a, a predetermined current is supplied to the cathode of the SPAD element 6a by the first supply path R1 including the P-type transistor 21.
そして、かかる所定の電流によって、パルス出力回路7aは、SPAD素子6aを動作させることができる。
Then, the pulse output circuit 7a can operate the SPAD element 6a by the predetermined current.
また、P型トランジスタ25のゲートには、初期状態でハイレベルの信号S3が入力される。これにより、初期状態において、SPAD素子6aのカソードには上述した第1の供給路R1以外からの電流は供給されない。
Further, a high level signal S3 is input to the gate of the P-type transistor 25 in the initial state. As a result, in the initial state, no current is supplied to the cathode of the SPAD element 6a from other than the first supply path R1 described above.
次に、図5に加えて図6も参照しながら、パルス出力回路7aの動作について説明する。図6は、本開示の実施形態に係るパルス出力回路7aの動作をタイミングチャートで示す説明図である。
Next, the operation of the pulse output circuit 7a will be described with reference to FIG. 6 in addition to FIG. FIG. 6 is an explanatory diagram showing the operation of the pulse output circuit 7a according to the embodiment of the present disclosure in a timing chart.
SPAD素子6aには、ガイガーモードと呼ばれるなだれ増幅が起きる寸前の状態になるまで、逆バイアスの電圧Vaが印加されている。すなわち、初期状態において、SPAD素子6aのカソードから出力される信号S1は、この電圧Vaとなる。
A reverse bias voltage Va is applied to the SPAD element 6a until a state called Geiger mode is reached on the verge of avalanche amplification. That is, in the initial state, the signal S1 output from the cathode of the SPAD element 6a becomes this voltage Va.
そして、インバータ22にはしきい電圧Vth以上の電圧Vaが信号S1として入力されることから、インバータ22はローレベルの信号S2を出力する。また、インバータ22からローレベルの信号S2が否定論理積回路23に入力されることから、遅延回路24からはハイレベルの信号S3が出力される。
Then, since the voltage Va equal to or higher than the threshold voltage Vth is input to the inverter 22 as the signal S1, the inverter 22 outputs the low-level signal S2. Further, since the low level signal S2 is input to the negative AND circuit 23 from the inverter 22, the high level signal S3 is output from the delay circuit 24.
そして、電圧Vaが印加されたSPAD素子6aに時間T1で1光子が入射すると、SPAD素子6aがブレイクダウンして第1の供給路R1に電流が流れる。これにより、信号S1は、電圧Vaから急激に減少する。そして、時間T2で信号S1がしきい電圧Vthより小さくなると、インバータ22はハイレベルの信号S2を出力する。
Then, when one photon is incident on the SPAD element 6a to which the voltage Va is applied at time T1, the SPAD element 6a breaks down and a current flows through the first supply path R1. As a result, the signal S1 sharply decreases from the voltage Va. Then, when the signal S1 becomes smaller than the threshold voltage Vth at the time T2, the inverter 22 outputs the high-level signal S2.
そして、信号S1は、時間T3においてなだれ増幅が停止することから、電圧Vbで下げ止まる。一方で、パルス出力回路7aでは、時間T2でハイレベルとなった信号S2がP型トランジスタ21のゲートに入力されることから、第1の供給路R1は切断される。
Then, since the avalanche amplification stops at the time T3, the signal S1 stops lowering at the voltage Vb. On the other hand, in the pulse output circuit 7a, since the signal S2 that has reached a high level at time T2 is input to the gate of the P-type transistor 21, the first supply path R1 is cut off.
これにより、SPAD素子6aのカソードは、電源電圧Vddから切断されたフローティング状態となる。したがって、信号S1は、時間T3以降でも電圧Vbで固定される。
As a result, the cathode of the SPAD element 6a is in a floating state cut off from the power supply voltage Vdd. Therefore, the signal S1 is fixed at the voltage Vb even after the time T3.
さらに、時間T2でハイレベルとなった信号S2は、否定論理積回路23にも入力される。この時間T2の時点において、否定論理積回路23にはハイレベルの信号S3が入力されていることから、否定論理積回路23は、ローレベルの信号を出力する。
Further, the signal S2 that has reached a high level at time T2 is also input to the negative AND circuit 23. At the time of this time T2, since the high level signal S3 is input to the negative logical product circuit 23, the negative logical product circuit 23 outputs a low level signal.
そして、遅延回路24は、かかる否定論理積回路23からのローレベルの信号に基づいて、時間T2から所定の遅延時間だけ経過した時間T4に、ローレベルの信号S3を出力する。
Then, the delay circuit 24 outputs the low-level signal S3 to the time T4 when a predetermined delay time has elapsed from the time T2 based on the low-level signal from the negative logical product circuit 23.
この時間T4でローレベルとなった信号S3は、P型トランジスタ25のゲートに入力される。これにより、P型トランジスタ25が導通状態となることから、パルス出力回路7a内にP型トランジスタ25を含んだ第2の供給路R2が開通する。
The low level signal S3 at this time T4 is input to the gate of the P-type transistor 25. As a result, the P-type transistor 25 becomes conductive, so that the second supply path R2 including the P-type transistor 25 is opened in the pulse output circuit 7a.
したがって、信号S1は、かかる第2の供給路R2を介してSPAD素子6aが再充電されることにより上昇する。
Therefore, the signal S1 rises when the SPAD element 6a is recharged via the second supply path R2.
すなわち、実施形態のパルス出力回路7aには、SPAD素子6aに電流を供給する供給路として、第1の供給路R1および第2の供給路R2が設けられる。第1の供給路R1は、P型トランジスタ21を含み、初期状態およびSPAD素子6a内でなだれ増幅が発生している際に、SPAD素子6aに電流を供給する。
That is, the pulse output circuit 7a of the embodiment is provided with a first supply path R1 and a second supply path R2 as supply paths for supplying current to the SPAD element 6a. The first supply path R1 includes a P-type transistor 21 and supplies a current to the SPAD element 6a in the initial state and when avalanche amplification is occurring in the SPAD element 6a.
また、第2の供給路R2は、P型トランジスタ25を含み、SPAD素子6a内でなだれ増幅が停止した後に、SPAD素子6aに電流を供給する。
Further, the second supply path R2 includes the P-type transistor 25, and supplies a current to the SPAD element 6a after the avalanche amplification is stopped in the SPAD element 6a.
そして、実施形態では、P型トランジスタ25の内部抵抗をP型トランジスタ21の内部抵抗よりも小さくするとよい。すなわち、実施形態では、第2の供給路R2の抵抗値を、第1の供給路R1の抵抗値よりも小さくするとよい。
Then, in the embodiment, the internal resistance of the P-type transistor 25 may be smaller than the internal resistance of the P-type transistor 21. That is, in the embodiment, the resistance value of the second supply path R2 may be smaller than the resistance value of the first supply path R1.
これにより、第2の供給路R2からSPAD素子6aに大きな電流を供給することができることから、すばやくSPAD素子6aを再充電することができる。
As a result, a large current can be supplied to the SPAD element 6a from the second supply path R2, so that the SPAD element 6a can be quickly recharged.
なお、第1の供給路R1の抵抗値を小さくしすぎると、供給される電流の値が大きくなりすぎることから、SPAD素子6a内でのなだれ増幅が停止しなくなる恐れがある。したがって、P型トランジスタ21の内部抵抗は、SPAD素子6aが良好に動作可能な範囲の電流値を供給可能な抵抗値に設定されるとよい。
If the resistance value of the first supply path R1 is made too small, the value of the supplied current becomes too large, so that the avalanche amplification in the SPAD element 6a may not stop. Therefore, the internal resistance of the P-type transistor 21 may be set to a resistance value capable of supplying a current value within a range in which the SPAD element 6a can operate well.
一方で、第2の供給路R2は、SPAD素子6a内でなだれ増幅が発生する際には電流を供給しない。したがって、P型トランジスタ25の内部抵抗を小さくしたとしても、SPAD素子6a内でなだれ増幅が停止しないなどの弊害は生じない。
On the other hand, the second supply path R2 does not supply current when avalanche amplification occurs in the SPAD element 6a. Therefore, even if the internal resistance of the P-type transistor 25 is reduced, there is no adverse effect such as avalanche amplification not stopping in the SPAD element 6a.
図6の説明に戻る。信号S1がしきい電圧Vth以上になった時間T5で、インバータ22はローレベルの信号S2を出力する。さらに、SPAD素子6aは、時間T6で初期状態の電圧Vaに復帰する。
Return to the explanation in Fig. 6. At the time T5 when the signal S1 becomes equal to or higher than the threshold voltage Vth, the inverter 22 outputs the low-level signal S2. Further, the SPAD element 6a returns to the initial voltage Va at time T6.
このように、パルス出力回路7aは、1光子が入射することによりSPAD素子6aで発生する信号S1を、インバータ22で第1パルス信号P1に変換して出力する。この第1パルス信号P1は、図6の例において時間T2から時間T5までのパルス幅を有する信号である。
As described above, the pulse output circuit 7a converts the signal S1 generated by the SPAD element 6a due to the incident of one photon into the first pulse signal P1 by the inverter 22 and outputs the signal S1. The first pulse signal P1 is a signal having a pulse width from time T2 to time T5 in the example of FIG.
そして、時間T5でローレベルになった信号S2は、P型トランジスタ21のゲートに入力される。これにより、P型トランジスタ21(すなわち、第1の供給路R1)を介して、SPAD素子6aのカソードに所定の電流が供給される。
Then, the signal S2 that has become low level at time T5 is input to the gate of the P-type transistor 21. As a result, a predetermined current is supplied to the cathode of the SPAD element 6a via the P-type transistor 21 (that is, the first supply path R1).
さらに、時間T5でローレベルとなった信号S2は、否定論理積回路23にも入力される。これにより、否定論理積回路23がハイレベルの信号を出力することから、遅延回路24は、時間T5から所定の遅延時間だけ経過した時間T7に、ハイレベルの信号S3を出力する。
Further, the signal S2 that becomes low level at time T5 is also input to the negative AND circuit 23. As a result, the negative AND circuit 23 outputs a high-level signal, so that the delay circuit 24 outputs the high-level signal S3 at the time T7 when a predetermined delay time has elapsed from the time T5.
この時間T7でハイレベルとなった信号S3は、P型トランジスタ25のゲートに入力される。これにより、P型トランジスタ25が切断状態となり、SPAD素子6aおよびパルス出力回路7aは初期状態に戻る。
The signal S3, which has reached a high level at this time T7, is input to the gate of the P-type transistor 25. As a result, the P-type transistor 25 is disconnected, and the SPAD element 6a and the pulse output circuit 7a return to the initial state.
ここまで説明したように、実施形態のパルス出力回路7aは、SPAD素子6aのカソードに電流を供給する供給路を複数(第1の供給路R1および第2の供給路R2)設けることにより、SPAD素子6aをすばやく回復させることができる。
As described above, the pulse output circuit 7a of the embodiment provides SPAD by providing a plurality of supply paths (first supply path R1 and second supply path R2) for supplying current to the cathode of the SPAD element 6a. The element 6a can be recovered quickly.
[加算部の構成および動作]
つづいて、実施形態に係る加算部8の構成および動作について、図7および図8を参照しながら説明する。図7は、本開示の実施形態に係る加算部8の構成例を示す回路図である。 [Configuration and operation of adder]
Subsequently, the configuration and operation of theaddition unit 8 according to the embodiment will be described with reference to FIGS. 7 and 8. FIG. 7 is a circuit diagram showing a configuration example of the addition unit 8 according to the embodiment of the present disclosure.
つづいて、実施形態に係る加算部8の構成および動作について、図7および図8を参照しながら説明する。図7は、本開示の実施形態に係る加算部8の構成例を示す回路図である。 [Configuration and operation of adder]
Subsequently, the configuration and operation of the
図7に示すように、測定装置1にSPAD素子6aおよびパルス出力回路7aがn個(nは正の整数)ずつある場合、実施形態に係る加算部8は、(n-1)個の論理和回路8a-2、8a-3・・・8a-nを有する。
As shown in FIG. 7, when the measuring device 1 has n SPAD elements 6a and n pulse output circuits 7a (n is a positive integer), the addition unit 8 according to the embodiment has (n-1) ORs. It has a sum circuit 8a-2, 8a-3 ... 8an.
論理和回路8a-2の入力端子には、パルス出力回路7a-1の出力端子と、パルス出力回路7a-2の出力端子とが接続される。また、論理和回路8a-3の入力端子には、論理和回路8a-2の出力端子と、パルス出力回路7a-3の出力端子とが接続される。
The output terminal of the pulse output circuit 7a-1 and the output terminal of the pulse output circuit 7a-2 are connected to the input terminal of the OR circuit 8a-2. Further, the output terminal of the OR circuit 8a-2 and the output terminal of the pulse output circuit 7a-3 are connected to the input terminal of the OR circuit 8a-3.
このように、論理和回路8a-2~8a-nは直列に接続され、各論理和回路8a-2~8a-nにはそれぞれパルス出力回路7a-2~7a-nの出力端子が接続される。そして、論理和回路8a-nの出力端子は、パルス整形部9に接続される。
In this way, the OR circuits 8a-2 to 8an are connected in series, and the output terminals of the pulse output circuits 7a-2 to 7an are connected to the OR circuits 8a-2 to 8an, respectively. To. Then, the output terminal of the OR circuit 8an is connected to the pulse shaping unit 9.
次に、図8を参照しながら、加算部8の動作について説明する。図8は、本開示の実施形態に係る加算部8の動作をタイミングチャートで示す説明図である。なお、以降の説明では、理解の容易のため、SPAD素子6aおよびパルス出力回路7aが2つずつ設けられる場合について示す。
Next, the operation of the addition unit 8 will be described with reference to FIG. FIG. 8 is an explanatory diagram showing the operation of the addition unit 8 according to the embodiment of the present disclosure in a timing chart. In the following description, for ease of understanding, a case where two SPAD elements 6a and two pulse output circuits 7a are provided will be described.
図8に示すように、一方のSPAD素子6a(以下、「SPAD素子A」とも呼称する。)に、時間T11で1光子が入射し、時間T14でさらに1光子が入射する。この場合、SPAD素子Aに接続されるパルス出力回路7a(以下、「パルス出力回路A」とも呼称する。)は、時間T11、T14からそれぞれ所定のパルス幅がある2つのパルス信号を持つ第1パルス信号P1Aを出力する。
As shown in FIG. 8, one photon is incident on one of the SPAD elements 6a (hereinafter, also referred to as “SPAD element A”) at time T11, and another photon is incident at time T14. In this case, the pulse output circuit 7a (hereinafter, also referred to as “pulse output circuit A”) connected to the SPAD element A is the first having two pulse signals having predetermined pulse widths from the times T11 and T14, respectively. The pulse signal P1A is output.
また、もう一方のSPAD素子6a(以下、「SPAD素子B」とも呼称する。)に、時間T12、時間T13、時間T15でそれぞれ1光子が入射する。この場合、SPAD素子Bに接続されるパルス出力回路7a(以下、「パルス出力回路B」とも呼称する。)は、時間T12、T13、T15からそれぞれ所定のパルス幅がある3つのパルス信号を持つ第1パルス信号P1Bを出力する。
Further, one photon is incident on the other SPAD element 6a (hereinafter, also referred to as "SPAD element B") at time T12, time T13, and time T15, respectively. In this case, the pulse output circuit 7a (hereinafter, also referred to as “pulse output circuit B”) connected to the SPAD element B has three pulse signals having predetermined pulse widths from the times T12, T13, and T15, respectively. The first pulse signal P1B is output.
この場合、加算部8は、パルス出力回路Aから出力される第1パルス信号P1Aと、パルス出力回路Bから出力される第1パルス信号P1Bとが加算された加算信号Paを生成する。かかる加算信号Paは、時間T11、T12、T13、T14およびT15からそれぞれ所定のパルス幅がある5つのパルス信号を有する。
In this case, the addition unit 8 generates an addition signal Pa in which the first pulse signal P1A output from the pulse output circuit A and the first pulse signal P1B output from the pulse output circuit B are added. The addition signal Pa has five pulse signals having predetermined pulse widths from the times T11, T12, T13, T14 and T15, respectively.
すなわち、加算部8は、各パルス出力回路7aで生成される複数の第1パルス信号P1を加算して、加算信号Paを生成する。かかる加算信号Paは、各SPAD素子6aに入射した光子に起因して発生するパルス信号を有する。
That is, the addition unit 8 adds a plurality of first pulse signals P1 generated by each pulse output circuit 7a to generate an addition signal Pa. The addition signal Pa has a pulse signal generated due to photons incident on each SPAD element 6a.
なお、実施形態では、パルス出力回路7aから出力されるパルス信号のパルス幅を可能な限り短くするとよい。これにより、図8に示すように、短時間で複数の光子が画素アレイ部6に入射する場合でも、かかる複数の光子をそれぞれパルス信号として出力することができる。
In the embodiment, the pulse width of the pulse signal output from the pulse output circuit 7a may be as short as possible. As a result, as shown in FIG. 8, even when a plurality of photons are incident on the pixel array unit 6 in a short time, the plurality of photons can be output as pulse signals.
[パルス整形部の構成および動作]
つづいて、実施形態に係るパルス整形部9の構成および動作について、図9~図11を参照しながら説明する。図9は、本開示の実施形態に係るパルス整形部9の構成例を示す回路図である。 [Structure and operation of pulse shaping unit]
Subsequently, the configuration and operation of thepulse shaping unit 9 according to the embodiment will be described with reference to FIGS. 9 to 11. FIG. 9 is a circuit diagram showing a configuration example of the pulse shaping unit 9 according to the embodiment of the present disclosure.
つづいて、実施形態に係るパルス整形部9の構成および動作について、図9~図11を参照しながら説明する。図9は、本開示の実施形態に係るパルス整形部9の構成例を示す回路図である。 [Structure and operation of pulse shaping unit]
Subsequently, the configuration and operation of the
図9に示すように、実施形態に係るパルス整形部9は、RSフリップフロップ回路41と、論理和回路42と、ディレイ回路43とを有する。
As shown in FIG. 9, the pulse shaping unit 9 according to the embodiment includes an RS flip-flop circuit 41, an OR circuit 42, and a delay circuit 43.
RSフリップフロップ回路41のS端子は、加算部8の出力端子に接続される。RSフリップフロップ回路41のR端子は、ディレイ回路43の出力端子に接続される。RSフリップフロップ回路41のQ端子は、カウンター部10の入力端子に接続される。RSフリップフロップ回路41のXQ端子は、論理和回路42の入力端子に接続される。
The S terminal of the RS flip-flop circuit 41 is connected to the output terminal of the adder 8. The R terminal of the RS flip-flop circuit 41 is connected to the output terminal of the delay circuit 43. The Q terminal of the RS flip-flop circuit 41 is connected to the input terminal of the counter unit 10. The XQ terminal of the RS flip-flop circuit 41 is connected to the input terminal of the OR circuit 42.
また、論理和回路42のもう一つの入力端子は、加算部8の出力端子に接続される。論理和回路42の出力端子は、ディレイ回路43の入力端子に接続される。
Further, the other input terminal of the OR circuit 42 is connected to the output terminal of the adder 8. The output terminal of the OR circuit 42 is connected to the input terminal of the delay circuit 43.
ディレイ回路43は、論理和回路42からハイレベルの信号が入力されている場合、遅延無くローレベルの信号をRSフリップフロップ回路41のR端子に出力し続ける。また、ディレイ回路43は、論理和回路42からローレベルの信号が入力された場合、かかるローレベルの信号が入力されてから所定の期間ΔTが経過した後に、ハイレベルの信号をRSフリップフロップ回路41のR端子に出力する。
When the high level signal is input from the OR circuit 42, the delay circuit 43 continues to output the low level signal to the R terminal of the RS flip-flop circuit 41 without delay. Further, when the low level signal is input from the OR circuit 42, the delay circuit 43 transmits the high level signal to the RS flip-flop circuit after a predetermined period ΔT has elapsed from the input of the low level signal. Output to the R terminal of 41.
なお、ディレイ回路43は、ローレベルの信号が入力されてから期間ΔTが経過する前に再度ハイレベルの信号が入力された場合、かかる再度のハイレベルの信号がローレベルの信号に切り替わってから期間ΔTが経過した後に、ハイレベルの信号を出力する。
If the high-level signal is input again before the period ΔT elapses after the low-level signal is input, the delay circuit 43 waits after the high-level signal is switched to the low-level signal. After the period ΔT has elapsed, a high level signal is output.
すなわち、ディレイ回路43は、最後にハイレベルからローレベルに信号が切り替わってから所定の期間ΔTが経過した場合に、ハイレベルの信号をRSフリップフロップ回路41のR端子に出力する。
That is, the delay circuit 43 outputs the high level signal to the R terminal of the RS flip-flop circuit 41 when a predetermined period ΔT has elapsed since the signal was finally switched from the high level to the low level.
図10は、本開示の実施形態に係るパルス整形部9の動作をタイミングチャートで示す説明図である。パルス整形部9の初期状態では、RSフリップフロップ回路41のS端子にローレベルの信号が入力されることから、RSフリップフロップ回路41のQ端子はローレベルの信号を出力し、RSフリップフロップ回路41のXQ端子はハイレベルの信号を出力する。
FIG. 10 is an explanatory diagram showing the operation of the pulse shaping unit 9 according to the embodiment of the present disclosure in a timing chart. In the initial state of the pulse shaping unit 9, a low-level signal is input to the S terminal of the RS flip-flop circuit 41. Therefore, the Q terminal of the RS flip-flop circuit 41 outputs a low-level signal to the RS flip-flop circuit. The XQ terminal of 41 outputs a high level signal.
また、RSフリップフロップ回路41のXQ端子から論理和回路42にハイレベルの信号が入力されることから、論理和回路42からはハイレベルの信号が出力され、ディレイ回路43からはローレベルの信号が出力される。
Further, since a high-level signal is input to the OR circuit 42 from the XQ terminal of the RS flip-flop circuit 41, a high-level signal is output from the OR circuit 42 and a low-level signal is output from the delay circuit 43. Is output.
そして、時間T21で加算部8からRSフリップフロップ回路41のS端子にハイレベルの信号が入力されると、時間T22でRSフリップフロップ回路41のQ端子からハイレベルの信号が出力される。また、時間T22でRSフリップフロップ回路41のXQ端子からローレベルの信号が出力される。
Then, when a high-level signal is input from the adder 8 to the S terminal of the RS flip-flop circuit 41 at time T21, a high-level signal is output from the Q terminal of the RS flip-flop circuit 41 at time T22. Further, at time T22, a low level signal is output from the XQ terminal of the RS flip-flop circuit 41.
そして、時間T23でRSフリップフロップ回路41のS端子に入力される信号がローレベルに変わると、論理和回路42に入力される2つの信号がいずれもローレベルになる。これにより、時間T24で論理和回路42からローレベルの信号が出力され、かかるローレベルの信号がディレイ回路43に入力される。
Then, when the signal input to the S terminal of the RS flip-flop circuit 41 changes to the low level at time T23, both of the two signals input to the OR circuit 42 become the low level. As a result, a low-level signal is output from the OR circuit 42 at time T24, and such a low-level signal is input to the delay circuit 43.
すると、ディレイ回路43は、時間T24から所定の期間ΔTが経過した時間T25に、ハイレベルの信号をRSフリップフロップ回路41のR端子に出力する。これにより、時間T26でRSフリップフロップ回路41のQ端子からローレベルの信号が出力され、RSフリップフロップ回路41のXQ端子からハイレベルの信号が出力される。
Then, the delay circuit 43 outputs a high-level signal to the R terminal of the RS flip-flop circuit 41 at the time T25 when the predetermined period ΔT has elapsed from the time T24. As a result, a low-level signal is output from the Q terminal of the RS flip-flop circuit 41 at time T26, and a high-level signal is output from the XQ terminal of the RS flip-flop circuit 41.
これにより、時間T27で論理和回路42からハイレベルの信号が出力され、かかるハイレベルの信号がディレイ回路43に入力される。すると、時間T28でローレベルの信号がディレイ回路43から出力されて、パルス整形部9が初期状態に戻る。
As a result, a high-level signal is output from the OR circuit 42 at time T27, and such a high-level signal is input to the delay circuit 43. Then, at time T28, a low-level signal is output from the delay circuit 43, and the pulse shaping unit 9 returns to the initial state.
ここまで説明したように、パルス整形部9は、時間T21から時間T23までのパルス幅を有する加算信号Paを、時間T22から時間T26までのパルス幅を有する第2パルス信号P2に整形して出力する。
As described above, the pulse shaping unit 9 shapes the addition signal Pa having a pulse width from time T21 to time T23 into a second pulse signal P2 having a pulse width from time T22 to time T26 and outputs it. To do.
このように、実施形態に係るパルス整形部9は、入力されるパルス信号を所定の期間ΔTに基づいた幅に長くするよう整形する。すなわち、実施形態では、パルス出力部7でパルス幅を可能な限り短くした第1パルス信号P1が、後段のカウンター部10で処理可能なパルス幅に整形される。
In this way, the pulse shaping unit 9 according to the embodiment shapes the input pulse signal so as to lengthen it to a width based on the predetermined period ΔT. That is, in the embodiment, the first pulse signal P1 whose pulse width is shortened as much as possible by the pulse output unit 7 is shaped into a pulse width that can be processed by the counter unit 10 in the subsequent stage.
また、実施形態に係るパルス整形部9は、所定の期間ΔTが経過する前に新たなパルス信号が入力された場合、かかる新たなパルス信号を基準としてパルス幅をさらに長くするように整形する。すなわち、実施形態に係るパルス整形部9は、加算信号Paを、所定の期間ΔTより短い時間間隔で発生する加算信号Pa内のパルス信号の数に基づいたパルス幅の第2パルス信号P2に整形する。
Further, when a new pulse signal is input before the predetermined period ΔT elapses, the pulse shaping unit 9 according to the embodiment shapes the pulse width so as to be further lengthened with reference to the new pulse signal. That is, the pulse shaping unit 9 according to the embodiment shapes the addition signal Pa into a second pulse signal P2 having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ΔT. To do.
これにより、実施形態に係るパルス整形部9は、後段のカウンター部10で処理可能であるとともに、所定の期間ΔTより短い時間間隔で発生する加算信号Pa内のパルス信号の数に基づいたパルス幅の第2パルス信号P2をカウンター部10に出力することができる。
As a result, the pulse shaping unit 9 according to the embodiment can be processed by the counter unit 10 in the subsequent stage, and the pulse width is based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ΔT. The second pulse signal P2 can be output to the counter unit 10.
図11は、本開示の実施形態に係るパルス整形部9の動作をタイミングチャートで示す説明図であり、図8の例に示した加算信号Paをパルス整形部9で処理した場合について示す図である。
FIG. 11 is an explanatory diagram showing the operation of the pulse shaping unit 9 according to the embodiment of the present disclosure in a timing chart, and is a diagram showing a case where the addition signal Pa shown in the example of FIG. 8 is processed by the pulse shaping unit 9. is there.
図11の例に示す加算信号Paは、時間T11で立ち上がるパルス信号Pa-1の次に、所定の期間ΔTが経過するまで次のパルス信号が立ち上がらない。したがって、かかるパルス信号Pa-1は、時間T11で立ち上がるとともに、時間T11から所定の期間ΔT経過した時間T11aまでのパルス幅を有するパルス信号P2-1に整形される。
In the addition signal Pa shown in the example of FIG. 11, the next pulse signal does not rise until a predetermined period ΔT elapses after the pulse signal Pa-1 that rises at time T11. Therefore, the pulse signal Pa-1 rises at the time T11 and is shaped into a pulse signal P2-1 having a pulse width from the time T11 to the time T11a after a predetermined period ΔT has elapsed.
また、図11の例に示す加算信号Paは、時間T12で立ち上がるパルス信号Pa-2の次に、所定の期間ΔTが経過するまでに立ち上がるパルス信号Pa-3を有する。したがって、かかるパルス信号Pa-2、Pa-3は、時間T12で立ち上がるとともに、時間T13から所定の期間ΔT経過した時間T13aまでのパルス幅を有するパルス信号P2-2に整形される。
Further, the addition signal Pa shown in the example of FIG. 11 has a pulse signal Pa-3 that rises by the lapse of a predetermined period ΔT after the pulse signal Pa-2 that rises at time T12. Therefore, the pulse signals Pa-2 and Pa-3 rise at time T12 and are shaped into pulse signals P2-2 having a pulse width from time T13 to time T13a after a predetermined period ΔT has elapsed.
また、図11の例に示す加算信号Paは、時間T14で立ち上がるパルス信号Pa-4の次に、所定の期間ΔTが経過するまでに立ち上がるパルス信号Pa-5を有する。したがって、かかるパルス信号Pa-4、Pa-5は、時間T14で立ち上がるとともに、時間T15から所定の期間ΔT経過した時間T15aまでのパルス幅を有するパルス信号P2-3に整形される。
Further, the addition signal Pa shown in the example of FIG. 11 has a pulse signal Pa-5 that rises by the lapse of a predetermined period ΔT after the pulse signal Pa-4 that rises at time T14. Therefore, the pulse signals Pa-4 and Pa-5 rise at time T14 and are shaped into pulse signals P2-3 having a pulse width from time T15 to time T15a after a predetermined period ΔT has elapsed.
なお、実施形態では、最後のパルス信号から所定の期間ΔT経過するまでパルス幅を長くするようにパルス信号を整形する例について示したが、パルス信号の整形手法はかかる例に限られない。
In the embodiment, an example of shaping the pulse signal so as to lengthen the pulse width from the last pulse signal until a predetermined period ΔT elapses has been shown, but the pulse signal shaping method is not limited to such an example.
たとえば、所定の期間が経過するまでにパルス信号が2個入力された場合には2倍のパルス幅に整形し、所定の期間が経過するまでにパルス信号が3個入力された場合には3倍のパルス幅に整形してもよい。このように、実施形態に係るパルス整形部9は、所定の期間が経過するまでに入力されるパルス信号の個数に基づいたパルス幅に、パルス信号を整形してもよい。
For example, if two pulse signals are input before the predetermined period elapses, the pulse width is doubled, and if three pulse signals are input before the predetermined period elapses, 3 is formed. It may be shaped to double the pulse width. In this way, the pulse shaping unit 9 according to the embodiment may shape the pulse signal to a pulse width based on the number of pulse signals input before the lapse of a predetermined period.
[カウンター部の構成および動作]
つづいて、実施形態に係るカウンター部10の構成および動作について、図12および図13を参照しながら説明する。図12は、本開示の実施形態に係るカウンター部10の構成例を示す回路図である。 [Counter configuration and operation]
Subsequently, the configuration and operation of thecounter unit 10 according to the embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a circuit diagram showing a configuration example of the counter unit 10 according to the embodiment of the present disclosure.
つづいて、実施形態に係るカウンター部10の構成および動作について、図12および図13を参照しながら説明する。図12は、本開示の実施形態に係るカウンター部10の構成例を示す回路図である。 [Counter configuration and operation]
Subsequently, the configuration and operation of the
図12に示すように、実施形態に係るカウンター部10は、計数パルス出力部51と、論理積回路52と、計数カウント部53とを有する。
As shown in FIG. 12, the counter unit 10 according to the embodiment includes a counting pulse output unit 51, a logical product circuit 52, and a counting counting unit 53.
計数パルス出力部51は、一定の時間間隔でパルス幅の狭いパルス信号(以下、計数パルス信号とも呼称する。)を論理積回路52の入力端子に出力する。たとえば、計数パルス出力部51は、上記の期間ΔTよりも短い時間間隔で計数パルス信号を出力する。
The counting pulse output unit 51 outputs a pulse signal having a narrow pulse width (hereinafter, also referred to as a counting pulse signal) to the input terminal of the logic product circuit 52 at regular time intervals. For example, the counting pulse output unit 51 outputs a counting pulse signal at a time interval shorter than the above period ΔT.
論理積回路52の入力端子は、計数パルス出力部51の出力端子と、パルス整形部9の出力端子とに接続される。論理積回路52の出力端子は、計数カウント部53の入力端子に接続される。また、計数カウント部53の出力端子は、制御部11に接続される。
The input terminal of the AND circuit 52 is connected to the output terminal of the counting pulse output unit 51 and the output terminal of the pulse shaping unit 9. The output terminal of the AND circuit 52 is connected to the input terminal of the counting / counting unit 53. Further, the output terminal of the counting / counting unit 53 is connected to the control unit 11.
図13は、本開示の実施形態に係るカウンター部10の動作をタイミングチャートで示す説明図である。図13の例では、時間T31から時間T32までのパルス幅があるパルス信号P2-4と、時間T33から時間T34までのパルス幅があるパルス信号P2-5とを持つ第2パルス信号P2が、パルス整形部9から出力される場合について説明する。
FIG. 13 is an explanatory diagram showing the operation of the counter unit 10 according to the embodiment of the present disclosure in a timing chart. In the example of FIG. 13, the second pulse signal P2 having a pulse signal P2-4 having a pulse width from time T31 to time T32 and a pulse signal P2-5 having a pulse width from time T33 to time T34 is A case where the signal is output from the pulse shaping unit 9 will be described.
ここで、パルス信号P2-4は、1つの光子がSPAD素子6aに入力された場合に出力されるパルス信号と同じパルス幅のパルス信号である。
Here, the pulse signal P2-4 is a pulse signal having the same pulse width as the pulse signal output when one photon is input to the SPAD element 6a.
また、図13の例では、計数パルス出力部51が、1つの光子がSPAD素子6aに入力された場合に出力されるパルス信号に対して、2つの計数パルス信号が重なるように計数パルス信号を出力する。
Further, in the example of FIG. 13, the counting pulse output unit 51 outputs a counting pulse signal so that the two counting pulse signals overlap with the pulse signal output when one photon is input to the SPAD element 6a. Output.
そして、図13に示すように、論理積回路52は、時間T31から時間T32までの間に2カウント連続するパルス信号を計数カウント部53に出力する。また、論理積回路52は、時間T33から時間T34までの間に11カウント連続するパルス信号を計数カウント部53に出力する。
Then, as shown in FIG. 13, the AND circuit 52 outputs a pulse signal having two consecutive counts between the time T31 and the time T32 to the count counting unit 53. Further, the AND circuit 52 outputs a pulse signal having 11 counts continuous from the time T33 to the time T34 to the count counting unit 53.
ここで、計数カウント部53は、所定の間隔で連続するパルス信号の数をカウントする。かかる所定の間隔とは、計数パルス信号の出力間隔と同じ間隔である。そして、計数カウント部53は、かかるカウントされたパルス信号の数に基づいて、複数のSPAD素子6aに入力される光子の数をカウントする。
Here, the count counting unit 53 counts the number of continuous pulse signals at predetermined intervals. The predetermined interval is the same interval as the output interval of the counting pulse signal. Then, the count counting unit 53 counts the number of photons input to the plurality of SPAD elements 6a based on the number of such counted pulse signals.
たとえば、計数カウント部53は、2カウント連続するパルス信号(パルス信号P2-4に対応)を、1個の光子が入射することにより発生したパルス信号であると算出する。また、計数カウント部53は、11カウント連続するパルス信号(パルス信号P2-5に対応)を、11/2=5.5個の光子が入射することにより発生したパルス信号であると算出する。
For example, the count counting unit 53 calculates that a pulse signal (corresponding to the pulse signal P2-4) that is continuous for two counts is a pulse signal generated by the incident of one photon. Further, the counting / counting unit 53 calculates that the pulse signal (corresponding to the pulse signal P2-5) having 11 counts continuous is a pulse signal generated by the incident of 11/2 = 5.5 photons.
すなわち、実施形態に係るカウンター部10は、第2パルス信号P2のパルス幅に応じた数、たとえば上述した連続するパルス信号の数を、複数のSPAD素子6aに入射した光子の数としてカウントする。
That is, the counter unit 10 according to the embodiment counts the number corresponding to the pulse width of the second pulse signal P2, for example, the number of continuous pulse signals described above as the number of photons incident on the plurality of SPAD elements 6a.
これにより、実施形態では、短い時間間隔で複数の光子が入射することによりパルス幅が長くなった第2パルス信号P2を、長くなったパルス幅に基づく光子の数に変換することができる。
Thereby, in the embodiment, it is possible to convert the second pulse signal P2 whose pulse width is long due to the incident of a plurality of photons at short time intervals into the number of photons based on the long pulse width.
したがって、実施形態によれば、短い時間間隔で複数の光子が入射した場合でも、かかる複数の光子が入射したことを検知することができる。
Therefore, according to the embodiment, even when a plurality of photons are incident at short time intervals, it is possible to detect that the plurality of photons are incident.
たとえば、図13の例において、第2パルス信号P2内のパルス信号の立ち上がり数(すなわち、パルス信号の数)に基づいて光子の数を求めた場合、時間T31から時間T34までの光子の数は「2個」と算出される。
For example, in the example of FIG. 13, when the number of photons is obtained based on the number of rising pulses signals (that is, the number of pulse signals) in the second pulse signal P2, the number of photons from time T31 to time T34 is It is calculated as "2 pieces".
すなわち、第2パルス信号P2内のパルス信号の数に基づいて光子の数を求めた場合、計測可能な光子数の最小値と最大値との差が小さくなってしまうことから、測距装置1のダイナミックレンジが減少してしまう恐れがある。
That is, when the number of photons is obtained based on the number of pulse signals in the second pulse signal P2, the difference between the minimum value and the maximum value of the measurable number of photons becomes small, so that the distance measuring device 1 There is a risk that the dynamic range of the will decrease.
一方で、実施形態では、第2パルス信号P2を、長くなったパルス幅に基づく光子の数に変換することにより、時間T31から時間T34までの光子の数を「1+5.5=6.5個」と算出することができる。
On the other hand, in the embodiment, the number of photons from the time T31 to the time T34 is increased by "1 + 5.5 = 6.5" by converting the second pulse signal P2 into the number of photons based on the lengthened pulse width. Can be calculated.
したがって、実施形態によれば、計測可能な光子数の最小値と最大値との差を拡大することができることから、測距装置1のダイナミックレンジを拡大することができる。
Therefore, according to the embodiment, the difference between the minimum value and the maximum value of the number of measurable photons can be increased, so that the dynamic range of the distance measuring device 1 can be expanded.
また、実施形態では、第1パルス信号P1のパルス幅をカウンター部10で処理可能なパルス幅より短くするとよい。
Further, in the embodiment, the pulse width of the first pulse signal P1 may be shorter than the pulse width that can be processed by the counter unit 10.
これにより、カウンター部10の仕様に限定されることなく、SPAD素子6aのデッドタイムを最小限にすることができる。したがって、実施形態によれば、SPAD素子6aのデッドタイムの最中に光子が入射することにより、かかる光子が検出できないことを抑制することができる。
As a result, the dead time of the SPAD element 6a can be minimized without being limited to the specifications of the counter unit 10. Therefore, according to the embodiment, it is possible to prevent the photons from being undetectable due to the incident of photons during the dead time of the SPAD element 6a.
また、実施形態では、第2パルス信号P2のパルス幅をカウンター部10で処理可能なパルス幅より長くするとよい。これにより、第2パルス信号P2をカウンター部10で問題なく処理することができる。
Further, in the embodiment, the pulse width of the second pulse signal P2 may be longer than the pulse width that can be processed by the counter unit 10. As a result, the second pulse signal P2 can be processed by the counter unit 10 without any problem.
[各種参考例との比較]
つづいて、図14を参照しながら、ここまで説明した実施形態と各種参考例との違いについて説明する。図14は、本開示の実施形態、参考例1および参考例2における信号処理の違いについて説明するための図である。 [Comparison with various reference examples]
Subsequently, the difference between the embodiments described so far and various reference examples will be described with reference to FIG. FIG. 14 is a diagram for explaining the difference in signal processing between the embodiment of the present disclosure, Reference Example 1 and Reference Example 2.
つづいて、図14を参照しながら、ここまで説明した実施形態と各種参考例との違いについて説明する。図14は、本開示の実施形態、参考例1および参考例2における信号処理の違いについて説明するための図である。 [Comparison with various reference examples]
Subsequently, the difference between the embodiments described so far and various reference examples will be described with reference to FIG. FIG. 14 is a diagram for explaining the difference in signal processing between the embodiment of the present disclosure, Reference Example 1 and Reference Example 2.
参考例1は、パルス出力回路7aにおいて、SPAD素子6aに電流を供給する供給路が1つしか無い場合の例である。ここで、SPAD素子6aに電流を供給する供給路が1つしか無い場合、かかる供給路から供給される電流の値を大きくした方がSPAD素子6aの回復時間を短くすることができる。
Reference example 1 is an example in which the pulse output circuit 7a has only one supply path for supplying current to the SPAD element 6a. Here, when there is only one supply path for supplying the current to the SPAD element 6a, the recovery time of the SPAD element 6a can be shortened by increasing the value of the current supplied from the supply path.
一方で、SPAD素子6aに供給される電流の値を大きくしすぎると、光子が入射した際にSPAD素子6a内で発生するなだれ増幅が停止しなくなる。したがって、参考例1では、パルス出力回路7aからSPAD素子6aに供給される電流の値を、決まった値以上に大きくすることができない。
On the other hand, if the value of the current supplied to the SPAD element 6a is made too large, the avalanche amplification generated in the SPAD element 6a will not stop when a photon is incident. Therefore, in Reference Example 1, the value of the current supplied from the pulse output circuit 7a to the SPAD element 6a cannot be increased beyond a fixed value.
すなわち、参考例1におけるSPAD素子6aの回復時間は、実施形態におけるSPAD素子6aの回復時間よりも長くなる(たとえば、数倍程度)。
That is, the recovery time of the SPAD element 6a in Reference Example 1 is longer than the recovery time of the SPAD element 6a in the embodiment (for example, about several times).
このことから、図14に示すように、参考例1では、パルス出力回路Aから出力される第1パルス信号P1が長いパルス幅の2つのパルス信号で形成され、パルス出力回路Bから出力される第1パルス信号P1がさらに長いパルス幅の1つのパルス信号で形成される。
Therefore, as shown in FIG. 14, in Reference Example 1, the first pulse signal P1 output from the pulse output circuit A is formed by two pulse signals having a long pulse width and is output from the pulse output circuit B. The first pulse signal P1 is formed by one pulse signal having a longer pulse width.
したがって、かかる2つの第1パルス信号P1を加算部8で加算した場合、加算信号Paは非常に長いパルス幅の1つのパルス信号で形成されることから、ダイナミックレンジが減少してしまう。
Therefore, when the two first pulse signals P1 are added by the addition unit 8, the addition signal Pa is formed by one pulse signal having a very long pulse width, so that the dynamic range is reduced.
参考例2は、パルス出力回路7aにおいて、第1パルス信号P1のパルス幅を、カウンター部10で処理可能なパルス幅に延ばした場合の例である。この場合、パルス出力回路Aから出力される第1パルス信号P1と、パルス出力回路Bから出力される第1パルス信号P1とを加算部8で加算することにより、カウンター部10で処理可能な信号を取得することができる。
Reference example 2 is an example in which the pulse width of the first pulse signal P1 is extended to a pulse width that can be processed by the counter unit 10 in the pulse output circuit 7a. In this case, a signal that can be processed by the counter unit 10 by adding the first pulse signal P1 output from the pulse output circuit A and the first pulse signal P1 output from the pulse output circuit B by the addition unit 8. Can be obtained.
しかしながら、かかる参考例2では、SPAD素子6aのデッドタイムを実施形態よりも長くする必要があることから、SPAD素子6aのデッドタイムの際に光子が新たに入射する確率が高まる。
However, in Reference Example 2, since the dead time of the SPAD element 6a needs to be longer than that of the embodiment, the probability that photons are newly incident during the dead time of the SPAD element 6a increases.
そして、参考例2では、SPAD素子6aのデッドタイムの際に光子が新たに入射した場合でも、第1パルス信号P1のパルス幅は光子が新たに入射していない場合と変わらない。
Then, in Reference Example 2, even when a photon is newly incident during the dead time of the SPAD element 6a, the pulse width of the first pulse signal P1 is the same as when the photon is not newly incident.
たとえば、SPAD素子Bに入射する1つ目の光子と2つ目の光子との間は間隔が短いが、これら2つの光子に基づいて出力されるパルス出力回路Bの第1パルス信号P1は、1つの光子に基づいて出力される第1パルス信号P1のパルス幅と変わらない。
For example, although the distance between the first photon and the second photon incident on the SPAD element B is short, the first pulse signal P1 of the pulse output circuit B output based on these two photons is It is the same as the pulse width of the first pulse signal P1 output based on one photon.
なぜなら、参考例2では、新たな光子の入射の有無にかかわらず、SPAD素子6aのデッドタイムが遅延回路24の遅延時間によって定められるからである。
This is because, in Reference Example 2, the dead time of the SPAD element 6a is determined by the delay time of the delay circuit 24 regardless of the presence or absence of new photons.
したがって、参考例2では、短い時間間隔で新たな光子がSPAD素子6aに入射した場合に、かかる新たな光子を検知することが困難である。
Therefore, in Reference Example 2, when new photons are incident on the SPAD element 6a at short time intervals, it is difficult to detect such new photons.
一方で、実施形態では、SPAD素子6aのデッドタイムを可能な限り短くすることにより、短い時間間隔で新たな光子がSPAD素子6aに入射した場合でも、かかる新たな光子をパルス出力回路Bで検知することができる。
On the other hand, in the embodiment, by shortening the dead time of the SPAD element 6a as much as possible, even if new photons are incident on the SPAD element 6a at short time intervals, the pulse output circuit B detects such new photons. can do.
したがって、実施形態によれば、計測可能な光子数の最小値と最大値との差を拡大することができることから、測距装置1のダイナミックレンジを拡大することができる。
Therefore, according to the embodiment, the difference between the minimum value and the maximum value of the number of measurable photons can be increased, so that the dynamic range of the distance measuring device 1 can be expanded.
[効果]
実施形態に係る制御回路は、パルス出力部7と、加算部8と、パルス整形部9とを備える。パルス出力部7は、複数のSPAD素子6aでそれぞれ発生する信号に応じた複数の第1パルス信号P1を出力する。加算部8は、パルス出力部7から出力される複数の第1パルス信号P1を加算して加算信号Paに変換する。パルス整形部9は、加算信号Paを、所定の期間ΔTより短い時間間隔で発生する加算信号Pa内のパルス信号の数に基づいたパルス幅の第2パルス信号P2に整形する。 [effect]
The control circuit according to the embodiment includes apulse output unit 7, an addition unit 8, and a pulse shaping unit 9. The pulse output unit 7 outputs a plurality of first pulse signals P1 corresponding to the signals generated by the plurality of SPAD elements 6a, respectively. The addition unit 8 adds a plurality of first pulse signals P1 output from the pulse output unit 7 and converts them into an addition signal Pa. The pulse shaping unit 9 shapes the addition signal Pa into a second pulse signal P2 having a pulse width based on the number of pulse signals in the addition signal Pa generated at intervals shorter than the predetermined period ΔT.
実施形態に係る制御回路は、パルス出力部7と、加算部8と、パルス整形部9とを備える。パルス出力部7は、複数のSPAD素子6aでそれぞれ発生する信号に応じた複数の第1パルス信号P1を出力する。加算部8は、パルス出力部7から出力される複数の第1パルス信号P1を加算して加算信号Paに変換する。パルス整形部9は、加算信号Paを、所定の期間ΔTより短い時間間隔で発生する加算信号Pa内のパルス信号の数に基づいたパルス幅の第2パルス信号P2に整形する。 [effect]
The control circuit according to the embodiment includes a
これにより、測距装置1のダイナミックレンジを拡大することができる。
As a result, the dynamic range of the ranging device 1 can be expanded.
また、実施形態に係る制御回路は、第2パルス信号P2のパルス幅に応じた数を複数のSPAD素子6aに入射した光子の数としてカウントするカウンター部10をさらに備える。
Further, the control circuit according to the embodiment further includes a counter unit 10 that counts a number corresponding to the pulse width of the second pulse signal P2 as the number of photons incident on the plurality of SPAD elements 6a.
これにより、短い時間間隔で複数の光子が入射することによりパルス幅が長くなった第2パルス信号P2を、長くなったパルス幅に基づく光子の数に変換することができる。
As a result, the second pulse signal P2 whose pulse width is lengthened due to the incident of a plurality of photons at short time intervals can be converted into the number of photons based on the lengthened pulse width.
また、実施形態に係る制御回路において、第1パルス信号P1のパルス幅は、カウンター部10で処理可能なパルス幅より短く、第2パルス信号P2のパルス幅は、カウンター部10で処理可能なパルス幅より長い。
Further, in the control circuit according to the embodiment, the pulse width of the first pulse signal P1 is shorter than the pulse width that can be processed by the counter unit 10, and the pulse width of the second pulse signal P2 is a pulse that can be processed by the counter unit 10. Longer than the width.
これにより、SPAD素子6aのデッドタイムを最小限にすることができるとともに、第2パルス信号P2をカウンター部10で問題なく処理することができる。
As a result, the dead time of the SPAD element 6a can be minimized, and the second pulse signal P2 can be processed by the counter unit 10 without any problem.
また、実施形態に係る制御回路において、パルス出力部7は、第1の供給路R1と、第2の供給路R2とを有する。第1の供給路R1は、SPAD素子6a内でなだれ増幅が発生している際にSPAD素子6aに電流を供給する。第2の供給路R2は、SPAD素子6a内でなだれ増幅が停止した後にSPAD素子6aに電流を供給する。
Further, in the control circuit according to the embodiment, the pulse output unit 7 has a first supply path R1 and a second supply path R2. The first supply path R1 supplies a current to the SPAD element 6a when avalanche amplification is occurring in the SPAD element 6a. The second supply path R2 supplies a current to the SPAD element 6a after the avalanche amplification is stopped in the SPAD element 6a.
これにより、SPAD素子6aの回復時間を短くすることができることから、SPAD素子6aのデッドタイムを短くすることができる。
As a result, the recovery time of the SPAD element 6a can be shortened, so that the dead time of the SPAD element 6a can be shortened.
以上、本開示の実施形態について説明したが、本開示の技術的範囲は、上述の実施形態そのままに限定されるものではなく、本開示の要旨を逸脱しない範囲において種々の変更が可能である。また、異なる実施形態及び変形例にわたる構成要素を適宜組み合わせてもよい。
Although the embodiments of the present disclosure have been described above, the technical scope of the present disclosure is not limited to the above-described embodiments as they are, and various changes can be made without departing from the gist of the present disclosure. Moreover, you may combine suitably the component over different embodiment and a modification.
また、本明細書に記載された効果はあくまで例示であって限定されるものでは無く、また他の効果があってもよい。
Also, the effects described in the present specification are merely examples and are not limited, and there may be other effects.
なお、本技術は以下のような構成も取ることができる。
(1)
複数のSPAD(Single Photon Avalanche Diode)素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、
前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、
前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、
を備える制御回路。
(2)
前記第2パルス信号のパルス幅に応じた数を複数の前記SPAD素子に入射した光子の数としてカウントするカウンター部
をさらに備える
前記(1)に記載の制御回路。
(3)
前記第1パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より短く、
前記第2パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より長い
前記(2)に記載の制御回路。
(4)
前記パルス出力部は、前記SPAD素子内でなだれ増幅が発生している際に前記SPAD素子に電流を供給する第1の供給路と、前記SPAD素子内でなだれ増幅が停止した後に前記SPAD素子に電流を供給する第2の供給路とを有する
前記(1)~(3)のいずれか一つに記載の制御回路。
(5)
被測定物に光を照射する光源と、
前記被測定物から反射される光を受光した際に信号を出力する複数のSPAD素子と、
複数の前記SPAD素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、を有する制御回路と、
を備える測距システム。
(6)
前記制御回路は、
前記第2パルス信号のパルス幅に応じた数を複数の前記SPAD素子に入射した光子の数としてカウントするカウンター部
をさらに備える
前記(5)に記載の測距システム。
(7)
前記第1パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より短く、
前記第2パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より長い
前記(6)に記載の測距システム。
(8)
前記パルス出力部は、前記SPAD素子内でなだれ増幅が発生している際に前記SPAD素子に電流を供給する第1の供給路と、前記SPAD素子内でなだれ増幅が停止した後に前記SPAD素子に電流を供給する第2の供給路とを有する
前記(5)~(7)のいずれか一つに記載の測距システム。 The present technology can also have the following configurations.
(1)
A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by a plurality of SPAD (Single Photon Avalanche Diode) elements, and a pulse output unit.
An addition unit that adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal.
A pulse shaping unit that shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
Control circuit including.
(2)
The control circuit according to (1) above, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements.
(3)
The pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
The control circuit according to (2), wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit.
(4)
The pulse output unit connects to the first supply path for supplying a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element. The control circuit according to any one of (1) to (3) above, which has a second supply path for supplying an electric current.
(5)
A light source that irradiates the object to be measured with light,
A plurality of SPAD elements that output a signal when the light reflected from the object to be measured is received, and
A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by the plurality of SPAD elements and a plurality of the first pulse signals output from the pulse output unit are added and converted into an addition signal. A control having an addition unit for shaping the addition signal and a pulse shaping unit for shaping the addition signal into a second pulse signal having a pulse width based on the number of pulse signals in the addition signal generated at a time interval shorter than a predetermined period. Circuit and
Distance measuring system equipped with.
(6)
The control circuit
The ranging system according to (5) above, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements.
(7)
The pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
The distance measuring system according to (6), wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit.
(8)
The pulse output unit connects to the first supply path that supplies a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element. The distance measuring system according to any one of (5) to (7) above, which has a second supply path for supplying an electric current.
(1)
複数のSPAD(Single Photon Avalanche Diode)素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、
前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、
前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、
を備える制御回路。
(2)
前記第2パルス信号のパルス幅に応じた数を複数の前記SPAD素子に入射した光子の数としてカウントするカウンター部
をさらに備える
前記(1)に記載の制御回路。
(3)
前記第1パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より短く、
前記第2パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より長い
前記(2)に記載の制御回路。
(4)
前記パルス出力部は、前記SPAD素子内でなだれ増幅が発生している際に前記SPAD素子に電流を供給する第1の供給路と、前記SPAD素子内でなだれ増幅が停止した後に前記SPAD素子に電流を供給する第2の供給路とを有する
前記(1)~(3)のいずれか一つに記載の制御回路。
(5)
被測定物に光を照射する光源と、
前記被測定物から反射される光を受光した際に信号を出力する複数のSPAD素子と、
複数の前記SPAD素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、を有する制御回路と、
を備える測距システム。
(6)
前記制御回路は、
前記第2パルス信号のパルス幅に応じた数を複数の前記SPAD素子に入射した光子の数としてカウントするカウンター部
をさらに備える
前記(5)に記載の測距システム。
(7)
前記第1パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より短く、
前記第2パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より長い
前記(6)に記載の測距システム。
(8)
前記パルス出力部は、前記SPAD素子内でなだれ増幅が発生している際に前記SPAD素子に電流を供給する第1の供給路と、前記SPAD素子内でなだれ増幅が停止した後に前記SPAD素子に電流を供給する第2の供給路とを有する
前記(5)~(7)のいずれか一つに記載の測距システム。 The present technology can also have the following configurations.
(1)
A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by a plurality of SPAD (Single Photon Avalanche Diode) elements, and a pulse output unit.
An addition unit that adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal.
A pulse shaping unit that shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
Control circuit including.
(2)
The control circuit according to (1) above, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements.
(3)
The pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
The control circuit according to (2), wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit.
(4)
The pulse output unit connects to the first supply path for supplying a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element. The control circuit according to any one of (1) to (3) above, which has a second supply path for supplying an electric current.
(5)
A light source that irradiates the object to be measured with light,
A plurality of SPAD elements that output a signal when the light reflected from the object to be measured is received, and
A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by the plurality of SPAD elements and a plurality of the first pulse signals output from the pulse output unit are added and converted into an addition signal. A control having an addition unit for shaping the addition signal and a pulse shaping unit for shaping the addition signal into a second pulse signal having a pulse width based on the number of pulse signals in the addition signal generated at a time interval shorter than a predetermined period. Circuit and
Distance measuring system equipped with.
(6)
The control circuit
The ranging system according to (5) above, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements.
(7)
The pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
The distance measuring system according to (6), wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit.
(8)
The pulse output unit connects to the first supply path that supplies a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element. The distance measuring system according to any one of (5) to (7) above, which has a second supply path for supplying an electric current.
1 測距装置(測距システムの一例)
2 光源部
3 受光部
6a SPAD素子
7 パルス出力部
8 加算部
9 パルス整形部
10 カウンター部
P1 第1パルス信号
P2 第2パルス信号
Pa 加算信号
R1 第1の供給路
R2 第2の供給路 1 Distance measuring device (an example of distance measuring system)
2Light source unit 3 Light receiving unit 6a SPAD element 7 Pulse output unit 8 Addition unit 9 Pulse shaping unit 10 Counter unit P1 First pulse signal P2 Second pulse signal Pa Addition signal R1 First supply path R2 Second supply path
2 光源部
3 受光部
6a SPAD素子
7 パルス出力部
8 加算部
9 パルス整形部
10 カウンター部
P1 第1パルス信号
P2 第2パルス信号
Pa 加算信号
R1 第1の供給路
R2 第2の供給路 1 Distance measuring device (an example of distance measuring system)
2
Claims (5)
- 複数のSPAD(Single Photon Avalanche Diode)素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、
前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、
前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、
を備える制御回路。 A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by a plurality of SPAD (Single Photon Avalanche Diode) elements, and a pulse output unit.
An addition unit that adds a plurality of the first pulse signals output from the pulse output unit and converts them into an addition signal.
A pulse shaping unit that shapes the added signal into a second pulse signal having a pulse width based on the number of pulse signals in the added signal generated at time intervals shorter than a predetermined period.
Control circuit including. - 前記第2パルス信号のパルス幅に応じた数を複数の前記SPAD素子に入射した光子の数としてカウントするカウンター部
をさらに備える
請求項1に記載の制御回路。 The control circuit according to claim 1, further comprising a counter unit that counts a number corresponding to the pulse width of the second pulse signal as the number of photons incident on the plurality of SPAD elements. - 前記第1パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より短く、
前記第2パルス信号のパルス幅は、前記カウンター部で処理可能なパルス幅より長い
請求項2に記載の制御回路。 The pulse width of the first pulse signal is shorter than the pulse width that can be processed by the counter unit.
The control circuit according to claim 2, wherein the pulse width of the second pulse signal is longer than the pulse width that can be processed by the counter unit. - 前記パルス出力部は、前記SPAD素子内でなだれ増幅が発生している際に前記SPAD素子に電流を供給する第1の供給路と、前記SPAD素子内でなだれ増幅が停止した後に前記SPAD素子に電流を供給する第2の供給路とを有する
請求項1に記載の制御回路。 The pulse output unit connects to the first supply path for supplying a current to the SPAD element when the avalanche amplification occurs in the SPAD element, and to the SPAD element after the avalanche amplification stops in the SPAD element. The control circuit according to claim 1, further comprising a second supply path for supplying an electric current. - 被測定物に光を照射する光源と、
前記被測定物から反射される光を受光した際に信号を出力する複数のSPAD素子と、
複数の前記SPAD素子でそれぞれ発生する信号に応じた複数の第1パルス信号を出力するパルス出力部と、前記パルス出力部から出力される複数の前記第1パルス信号を加算して加算信号に変換する加算部と、前記加算信号を、所定の期間より短い時間間隔で発生する前記加算信号内のパルス信号の数に基づいたパルス幅の第2パルス信号に整形するパルス整形部と、を有する制御回路と、
を備える測距システム。 A light source that irradiates the object to be measured with light,
A plurality of SPAD elements that output a signal when the light reflected from the object to be measured is received, and
A pulse output unit that outputs a plurality of first pulse signals corresponding to signals generated by the plurality of SPAD elements and a plurality of the first pulse signals output from the pulse output unit are added and converted into an addition signal. A control having an addition unit for shaping the addition signal and a pulse shaping unit for shaping the addition signal into a second pulse signal having a pulse width based on the number of pulse signals in the addition signal generated at a time interval shorter than a predetermined period. Circuit and
Distance measuring system equipped with.
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JP2012037267A (en) * | 2010-08-04 | 2012-02-23 | Hitachi High-Technologies Corp | Method for detecting quantity of light and apparatus therefor |
JP2012060012A (en) * | 2010-09-10 | 2012-03-22 | Toyota Central R&D Labs Inc | Photodetector |
JP2014081254A (en) * | 2012-10-16 | 2014-05-08 | Toyota Central R&D Labs Inc | Optical ranging apparatus |
JP2017198611A (en) * | 2016-04-28 | 2017-11-02 | キヤノン株式会社 | Imaging device, recognition apparatus, and article manufacturing method |
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JP2012037267A (en) * | 2010-08-04 | 2012-02-23 | Hitachi High-Technologies Corp | Method for detecting quantity of light and apparatus therefor |
JP2012060012A (en) * | 2010-09-10 | 2012-03-22 | Toyota Central R&D Labs Inc | Photodetector |
JP2014081254A (en) * | 2012-10-16 | 2014-05-08 | Toyota Central R&D Labs Inc | Optical ranging apparatus |
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