WO2020155192A1 - 谐振器及半导体器件 - Google Patents

谐振器及半导体器件 Download PDF

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Publication number
WO2020155192A1
WO2020155192A1 PCT/CN2019/074933 CN2019074933W WO2020155192A1 WO 2020155192 A1 WO2020155192 A1 WO 2020155192A1 CN 2019074933 W CN2019074933 W CN 2019074933W WO 2020155192 A1 WO2020155192 A1 WO 2020155192A1
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WIPO (PCT)
Prior art keywords
substrate
curved surface
cavity
ion implantation
resonator
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PCT/CN2019/074933
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English (en)
French (fr)
Inventor
李亮
吕鑫
梁东升
Original Assignee
中国电子科技集团公司第十三研究所
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Priority to US16/970,006 priority Critical patent/US11664783B2/en
Publication of WO2020155192A1 publication Critical patent/WO2020155192A1/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
    • H03H9/15—Constructional features of resonators consisting of piezoelectric or electrostrictive material
    • H03H9/17—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator
    • H03H9/171—Constructional features of resonators consisting of piezoelectric or electrostrictive material having a single resonator implemented with thin-film techniques, i.e. of the film bulk acoustic resonator [FBAR] type
    • H03H9/172—Means for mounting on a substrate, i.e. means constituting the material interface confining the waves to a volume
    • H03H9/173—Air-gaps
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/021—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the air-gap type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H3/00—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators
    • H03H3/007—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks
    • H03H3/02—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks
    • H03H2003/023—Apparatus or processes specially adapted for the manufacture of impedance networks, resonating circuits, resonators for the manufacture of electromechanical resonators or networks for the manufacture of piezoelectric or electrostrictive resonators or networks the resonators or networks being of the membrane type

Definitions

  • This application relates to the field of semiconductor technology, in particular to resonators and semiconductor devices.
  • Resonators can be used in various electronic applications to implement signal processing functions. For example, some cellular phones and other communication devices use resonators to implement filters for transmitted and/or received signals.
  • resonators can be used according to different applications, such as film bulk acoustic resonator (FBAR), coupled resonator filter (SBAR), stacked bulk acoustic resonator (SBAR), double bulk acoustic resonator ( DBAR) and solid state mounted resonator (SMR).
  • FBAR film bulk acoustic resonator
  • SBAR coupled resonator filter
  • SBAR stacked bulk acoustic resonator
  • DBAR double bulk acoustic resonator
  • SMR solid state mounted resonator
  • a typical acoustic resonator includes an upper electrode, a lower electrode, a piezoelectric material between the upper and lower electrodes, an acoustic reflection structure under the lower electrode, and a substrate under the acoustic reflection structure.
  • the area where the upper electrode, piezoelectric layer, and lower electrode overlap in the thickness direction is usually defined as the effective area of the resonator.
  • the embodiments of the present application provide a resonator and a semiconductor device with a novel structure.
  • the first aspect of the embodiments of the present application provides a resonator, including:
  • a multilayer structure formed on the substrate including a lower electrode layer, a piezoelectric layer, and an upper electrode layer from bottom to top;
  • a cavity is formed between the substrate and the multilayer structure, and the cavity is surrounded by the upper side of the substrate and the lower side of the multilayer structure.
  • the lower side surface and the middle area of the cavity corresponding part are flat, and the edge of the middle area and the cavity edge is a smooth curved surface with a smooth transition.
  • the smooth curved surface is located on the upper side of the substrate and the Between planes.
  • the smooth curved surface includes a first curved surface and a second curved surface connected by a smooth transition.
  • the vertical section of the first curved surface is an inverted parabola shape
  • the vertical section of the second curved surface is a parabola shape
  • the first curved surface is located below the second curved surface.
  • the curvature of each point of the smooth curved surface is less than a first preset value.
  • the angle between the tangent surface where the smooth curved surface is in contact with the substrate and the substrate is less than 45 degrees.
  • the height of the cavity is any value between 100 nanometers and 2000 nanometers.
  • the substrate is any one of a gallium arsenide substrate, a silicon carbide substrate, a sapphire substrate, a lithium niobate substrate, a lithium tantalate substrate, and various composite material substrates.
  • the substrate is a Si substrate.
  • a second aspect of the embodiments of the present application provides a semiconductor device including any of the above resonators.
  • a cavity is formed between the substrate and the multilayer structure.
  • the cavity is surrounded by the upper side of the substrate and the lower side of the multilayer structure.
  • the middle region is a plane, and the edge of the middle region and the edge of the cavity is a smooth curved surface with a smooth transition.
  • the smooth curved surface is located between the upper side of the substrate and the plane, thereby forming a new type of resonator Structure, and has better performance.
  • the cavity structure in the present application makes the manufacturing process of the resonator relatively simple and less difficult, so the yield is higher and the consistency is better.
  • Fig. 1 is a schematic structural diagram of a resonator provided by an embodiment of the present application
  • Fig. 2 is an enlarged schematic diagram of area A in Fig. 1;
  • FIG. 3 is a flow chart of the manufacturing process of the resonator provided by the embodiment of the present application.
  • FIG. 4 is a schematic diagram of the manufacturing process of the resonator provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of three ion implantation provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of ion implantation in an oblique direction under a shielding layer structure provided by an embodiment of the present application;
  • FIG. 7 is a schematic diagram of four ion implantation provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of ion implantation in an oblique direction under another shielding layer structure provided by an embodiment of the present application.
  • the resonator in the present application may include a substrate 100 and a multilayer structure 200.
  • a multilayer structure 200 is formed on the substrate 100, and the multilayer structure 200 includes a lower electrode layer 203, a piezoelectric layer 202, and an upper electrode layer 201 in order from bottom to top.
  • a cavity 300 is formed between the substrate 100 and the multilayer structure 200, and the cavity 300 is surrounded by the upper side of the substrate 100 and the lower side of the multilayer structure 200,
  • the lower side of the multilayer structure 200 and the middle region 2031 of the corresponding part of the cavity 100 are flat, and the edge of the middle region 2031 and the edge of the cavity 300 are smoothly transitioned smooth curved surfaces 2032.
  • the smooth The curved surface 2032 is located between the upper side surface of the substrate 100 and the plane (a plane corresponding to the middle region 2031). Among them, the smooth curved surface 2032 can ensure the performance of the resonator cavity without sudden changes.
  • the smooth curved surface 2032 is a part of the lower side of the multilayer structure 200.
  • a cavity 300 is formed between the substrate 100 and the multilayer structure 200.
  • the cavity 300 is surrounded by the upper side of the substrate 100 and the lower side of the multilayer structure 200.
  • the lower side of the multilayer structure 200 The middle region 2031 of the part corresponding to the cavity 100 is a plane, and the edge of the middle region 2031 and the edge of the cavity 300 is a smooth curved surface 2032 with a smooth transition.
  • the smooth curved surface 2032 is located on the upper side of the substrate 100 and Between the planes, a new type of resonator structure is formed, and it has better performance.
  • the smooth curved surface 2032 may include a first curved surface 20321 and a second curved surface 20322 that are smoothly connected.
  • the smooth transition of the first curved surface 20321 and the second curved surface 20322 means that there is no sudden change in the connection between the first curved surface 20321 and the second curved surface 20322, and the first curved surface 20321 and the second curved surface 20322 are also free of sudden change.
  • the curved surface can ensure the performance of the resonator cavity.
  • the multilayer structure 200 is composed of a large number of crystals, and no sudden change means that the gap between the crystals at the first rounded curved surface should not be too large to affect the performance of the resonator.
  • the vertical section of the first curved surface 20321 may be an inverted parabola shape
  • the vertical section of the second curved surface 20322 may be a parabola shape
  • the first curved surface 20321 is located below the second curved surface 20322.
  • the first curved surface 20321 and the second curved surface 20322 are smoothly connected.
  • the first curved surface 20321 and the second curved surface 20322 can also be curved surfaces of other shapes, and the gap between the crystals at the smooth curved surface 2032 can be achieved without affecting the performance of the resonator.
  • the upper side of the substrate 100 is flat.
  • the smooth surface 2032 is smooth as a whole, which may be that the curvature of each point of the smooth surface 2032 is smaller than the first preset value.
  • the first preset value can be set according to actual conditions, so as to achieve the purpose of smoothing the gap between the crystals at the curved surface 2032 without affecting the performance of the resonator.
  • the curvature of the smooth curved surface in the transition area should be as small as possible.
  • the smallest curvature requires the length of the transition area to increase, which will increase the area of the resonator. Therefore, the curvature and length of the transition zone should be optimized.
  • the height of the cavity 300 is any value between 100 nanometers and 2000 nanometers.
  • the angle between the tangent surface where the smooth curved surface 2032 contacts the substrate 100 and the substrate 100 is less than 45 degrees.
  • the resonator can have better performance.
  • the substrate 100 may be a silicon substrate, or a gallium arsenide substrate, a silicon carbide substrate, a sapphire substrate, a lithium niobate substrate, a lithium tantalate substrate, and various composite material substrates. There is no restriction on any of them.
  • BBAR bridge-shaped bulk acoustic resonator
  • step 101 the substrate is preprocessed to form a dielectric layer with a preset thickness.
  • the pretreatment may be oxidation treatment, that is, oxidation treatment is performed on the substrate 100 to form a dielectric layer 400 with a predetermined thickness, as shown in FIG. 4(b).
  • the substrate may be placed in an oxidizing atmosphere for oxidation treatment, so that an oxide layer with a predetermined thickness is formed on the substrate.
  • high-purity oxygen gas may be introduced into the substrate, and an oxide layer may be formed on the substrate through wet oxygen oxidation or oxyhydrogen synthesis oxidation.
  • the preset temperature range may be 1000 degrees Celsius to 1200 degrees Celsius.
  • the implementation process of step 101 may also be: pre-processing the substrate 100 by vapor deposition method to form a dielectric layer 400 with a preset thickness, as shown in FIG. 4(b).
  • the vapor deposition method can be PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method) or LPCVD (Low Pressure Chemical Vapor Deposition, low pressure chemical vapor deposition method).
  • step 101 may also be: pre-processing the substrate by a sputtering method to form a dielectric layer with a preset thickness.
  • step 101 may also be: pre-processing the substrate by an electron beam evaporation method to form a dielectric layer with a preset thickness.
  • Step 102 Perform ion implantation on a predetermined area of the dielectric layer.
  • the etching or corrosion rate of the preset area of the dielectric layer can be greater than the etching or corrosion rate outside the preset area of the dielectric layer, thereby During the etching or etching of the dielectric layer, a dielectric layer with a predetermined shape can be formed.
  • the implementation process of step 102 may be: forming a shielding layer 500 in a preset area of the dielectric layer 400, and performing ion implantation on the entire dielectric layer 400 after the shielding layer 500 is formed, as shown in FIG. 4(c) .
  • the shielding layer 500 by forming the shielding layer 500 in a preset area of the dielectric layer 400, and then performing ion implantation on the entire dielectric layer 400, the shielding layer 500 can be shielded or to a certain extent reduced the impact of ion implantation on the dielectric layer 400 covered by the shielding layer 500 , So that the sacrificial material part of the preset shape can be formed in the subsequent steps.
  • forming a shielding layer in a preset area of the dielectric layer may include: forming a shielding layer 500 with an edge thickness smaller than a middle thickness in the preset area of the dielectric layer 400, and the middle area of the shielding layer 500 is flat, such as As shown in Figure 4(c).
  • ion implantation is performed on the dielectric layer 400 in Figure 4(c)
  • the dielectric layer in the region of the shielding layer 500 can be less affected by ion implantation.
  • the ion implantation energy When the ion implantation energy is small The ion implantation will not penetrate the shielding layer 500 to reach the dielectric layer under the shielding layer 500, and the part that does not cover the shielding layer 500 will be implanted with doped impurities at a predetermined depth.
  • the shape of the shielding layer 500 will affect the shape of the sacrificial material part in step 103. Generally, the shape of the sacrificial material part is consistent with the shape of the shielding layer 500. Therefore, the shape of the cavity finally required can be achieved by setting the specific shape of the shielding layer.
  • the ion implantation process on the entire dielectric layer after the shielding layer is formed in step 102 includes: implanting doping with a preset dose and a preset energy on the entire dielectric layer including the shielding layer region Impurities.
  • the preset dose affects the etching or corrosion rate in step 103
  • the preset energy affects the depth of ion implantation, and ultimately affects the height of the cavity.
  • the preset energy the greater the preset energy of a certain region to be ion implanted, the greater the depth of ion implantation in that region, and the greater the cavity height corresponding to this part after the cavity is finally formed;
  • the shape of the shielding layer 400 is preset, and only one ion implantation with a preset dose and a preset energy can be used to etch or etch the sacrificial material in the required shape in step 103, such as sacrificial material
  • the shape of the part is that the top surface is flat and the vertical section is a bridge-like structure.
  • the thickness from the edge to the edge of the middle region of the shielding layer is gradually reduced, so that the distance between the edge of the middle region of the shielding layer and the edge of the shielding layer There is no sudden change in the curved surface, thereby ensuring the performance of the resonator cavity.
  • the substrate 100 and the multilayer structure 200 of the final resonator are composed of a lot of crystals, and the non-abrupt change refers to the relatively smooth transition between the edges of the middle region of the shielding layer and the curved surfaces between the edges of the shielding layer.
  • the gap between the respective crystals of the resonator multilayer structure 200 and the corresponding part of the cavity should not be too large to affect the performance of the resonator.
  • the edge of the middle region of the shielding layer and the edge of the shielding layer is a smooth curved surface with a smooth transition, so that the resonator cavity finally formed is shown as 300 in FIG. 1.
  • the gap between the crystals in the corresponding part of the resonator cavity should not be too large to affect the performance of the resonator, and no sudden change will occur.
  • the angle between the tangent surface where the smooth curved surface is in contact with the substrate 100 and the substrate 100 is less than 45 degrees, so that the resonator cavity formed in this way has better performance.
  • the smooth curved surface may include a first curved surface and a second curved surface connected by a smooth transition.
  • the vertical section of the first curved surface is an inverted parabola shape
  • the vertical section of the second curved surface is a parabola shape
  • the first curved surface is located below the second curved surface.
  • the finally formed resonator cavity is shown as 300 in FIG. 1, corresponding to the first curved surface and the second curved surface in the smooth curved surface.
  • the ion implantation process on the entire dielectric layer after the shielding layer is formed in step 102 includes: implanting a preset dose and preset energy multiple times on the entire dielectric layer including the shielding layer region The doped impurities of, wherein the preset dose and preset energy of each ion implantation are different or different.
  • the thickness of the shielding layer may be the same everywhere, or the edge thickness may be smaller than the middle thickness and the middle area is flat, which is not limited.
  • the shape of the sacrificial material portion in step 103 can be made into a desired shape.
  • the relationship of the preset dose in each ion implantation sorted by the preset energy can be from small to large and then from large to small. In this way, after multiple ion implantation, multiple impurity doping layers will be formed at the edge of the shielding layer.
  • the ion implantation with higher energy corresponds to a thicker impurity doping layer, and the ion implantation with lower energy corresponds to a thinner impurity doping layer.
  • FIG. 5 clearly illustrates the ion implantation, so only the shielding layer 500 and the dielectric layer 400 are shown.
  • the dose of the first ion implantation is the first dose and the energy is the first energy
  • the dose of the second ion implantation is the second dose and the energy is the second energy
  • the dose of the third ion implantation is the third dose
  • the energy is the third energy
  • the first energy is greater than the second energy
  • the second energy is greater than the third energy
  • the first dose is greater than the second dose
  • the second dose is greater than the third dose
  • the depth of the first ion implantation is H1
  • the depth of the second ion implantation is H2
  • the depth of the third ion implantation is H3, then H1>H2>H3, and each doped impurity layer is shown as the dotted line in Figure 5. Shown.
  • the depth of the first ion implantation with the highest energy is less than the thickness of the shielding layer 500, so there is no ion implantation under the middle region of the shielding layer 500.
  • the direction of each ion implantation is perpendicular to the substrate 100, or
  • the direction of each ion implantation is a preset angle other than 90 degrees to the substrate 100 (the preset angle of each ion implantation is different or not the same), or
  • the direction of a part of the ion implantation is perpendicular to the substrate 100, and the direction of the remaining part of the ion implantation is an acute angle less than the predetermined angle with the substrate 100.
  • the thickness of the shielding layer relative to the direction of ion implantation can be adjusted (as shown in Figure 6) to obtain doped impurity layers of different depths, so that the sacrificial material
  • the curved surface of part of the edge is smoother.
  • the ion implantation of the preset dose and the preset energy is combined with the direction of each ion implantation to make the curved surface of the edge of the sacrificial material part smoother.
  • the edge thickness of the shielding layer is smaller than the thickness of the middle part.
  • the details are as follows.
  • step 102 forming a shielding layer in a predetermined area of the dielectric layer, and performing ion implantation on the entire dielectric layer after the shielding layer is formed, includes:
  • a shielding layer with uniform thickness is formed in the preset area of the dielectric layer
  • the removal of the shielding layer and the steps A and B are performed repeatedly in cycles, and the preset area, preset dose, and preset energy corresponding to each ion implantation are different or not the same.
  • multiple doped impurity layers can be formed on the dielectric layer 400, and then the dielectric layer 400 is etched or etched in step 103 to form a desired shape Sacrificial material part.
  • the preset area, preset dose, and preset energy corresponding to each ion implantation are different or different. That is, the preset area, preset dose, and preset energy corresponding to ion implantation are three factors. The three factors are not the same; one of the three factors of each ion implantation can also be the same.
  • FIG. 7 clearly illustrates the ion implantation, and only the shielding layer 500 and the dielectric layer 400 are shown.
  • a first shielding layer with uniform thickness is formed in the first preset area of the dielectric layer, and the first ion implantation is performed.
  • the energy of the first ion implantation is the smallest, and the corresponding ion implantation depth is the smallest; after removing the first shielding layer,
  • the second preset area of the layer forms a second shielding layer with a uniform thickness, and performs a second ion implantation.
  • the energy of the second ion implantation is greater than that of the first ion implantation, and the ion implantation depth is greater than that of the first ion implantation. Depth; after removing the second shielding layer, a third shielding layer with a uniform thickness is formed in the third preset area of the dielectric layer, and the third ion implantation is performed.
  • the energy of the third ion implantation is greater than the energy of the second ion implantation ,
  • the ion implantation depth is greater than the depth of the second ion implantation; after removing the third shielding layer, a fourth shielding layer with a uniform thickness is formed in the fourth preset area of the dielectric layer, and the fourth ion implantation is performed.
  • the energy of the implantation is greater than the energy of the third ion implantation, and the depth of the ion implantation is greater than the depth of the third ion implantation.
  • the energy in the four ion implantations is inversely proportional to the size of the preset area, and the larger preset area includes the smaller preset area.
  • step 102 the direction of each ion implantation is perpendicular to the substrate, or
  • the direction of each ion implantation is at a preset angle other than 90 degrees to the substrate (the preset angle for each ion implantation is different or different), or
  • the direction of a part of the ion implantation is perpendicular to the substrate, and the direction of the remaining part of the ion implantation is an acute angle smaller than the predetermined angle with the substrate.
  • the direction of ion implantation can be changed at the edge of the shielding layer 400, so that the direction of ion implantation is at a preset angle other than 90 degrees to the substrate 100 (as shown in FIG. 8 As shown), in the direction of ion implantation, the thickness of the shielding layer 400 is no longer the same everywhere, so that the ion implantation effect at the boundary of the shielding layer 400 is the same as that of the shielding layer whose edge thickness is less than the thickness of the middle region.
  • the injection effect is basically the same.
  • Step 103 etch or etch the dielectric layer after ion implantation to form a sacrificial material part; the shape of the sacrificial material part is a flat top surface and a bridge-like structure in vertical section.
  • the dielectric layer under the shielding layer is not ion implanted or the implantation depth is relatively shallow, and the dielectric layer outside the shielding layer is ion implanted deeper, so that the dielectric layer During etching, the shielding layer and the dielectric layer outside the shielding layer are etched or etched at a faster rate, and the dielectric layer that has not been ion implanted is etched or etched at a slower rate, and finally a sacrifice of the desired shape can be formed Material part.
  • the shape of the sacrificial material part 600 is that the top surface is flat and the vertical section is a bridge-like structure (see FIG. 2(d)). The top surface is the side surface of the sacrificial material portion 600 away from the substrate 100.
  • the shielding layer may be SiN, a multilayer film structure, or photoresist, which is not limited.
  • the shielding layer is used to shield off the ion implantation or block part of the ion implantation, which leads to a large difference in the etching or corrosion rate of the shielded area and the unshielded area: the etching or corrosion rate of the part without the shielding layer is faster, and the part with the shielding layer is etched. The etching or corrosion rate is relatively slow, and finally forms the part of the sacrificial material in this step. Since the thickness from the edge of the middle region of the shielding layer to the edge of the shielding layer is gradually reduced, a transition area without rate change can be formed at the edge of the shielding layer.
  • the transition area can be smooth by optimizing the oxidation method and the type and structure of the shielding layer.
  • a curved surface, on which a multilayer structure containing a piezoelectric film such as AlN is grown on the smooth curved surface can ensure the crystal quality of the piezoelectric film.
  • a multilayer structure is formed on the substrate on which the sacrificial material portion has been formed, and the multilayer structure includes a lower electrode layer, a piezoelectric layer, and an upper electrode layer from bottom to top.
  • a multilayer structure 200 is formed on the substrate 100 on which the sacrificial material portion 600 has been formed.
  • the multilayer structure 200 includes a lower electrode layer 203, a piezoelectric layer 202, and an upper electrode from bottom to top. ⁇ 201 ⁇ Layer 201.
  • Step 105 removing the sacrificial material part.
  • the sacrificial material portion is removed to form a cavity 300, and the shape of the cavity 300 is consistent with the shape of the sacrificial material portion.

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  • Acoustics & Sound (AREA)
  • Engineering & Computer Science (AREA)
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Abstract

一种谐振器及半导体器件，该谐振器包括：衬底（100）；多层结构（200），形成于所述衬底（100）上，所述多层结构（200）由下至上依次包括下电极层（203）、压电层（202）和上电极层（201）；其中，在所述衬底（100）和所述多层结构（200）之间形成有腔体（300），所述腔体（300）由所述衬底（100）的上侧面和所述多层结构（200）的下侧面围成，所述多层结构（200）的下侧面与所述腔体（300）对应部分的中部区域（2031）为平面，且中部区域（2031）的边缘与所述腔体（300）边缘之间为圆滑过渡的平滑曲面（2032），所述平滑曲面（2032）位于所述衬底（100）的上侧面和所述平面之间。上述谐振器通过设置顶壁为平面的腔体（300），从而形成一种新型的谐振器结构，且具有较好的性能。

Description

谐振器及半导体器件 技术领域
本申请涉及半导体技术领域，特别是涉及谐振器及半导体器件。
 背景技术
谐振器可以用于各种电子应用中实施信号处理功能，例如，一些蜂窝式电话及其它通信装置使用谐振器来实施用于所发射和/或所接收信号的滤波器。可根据不同应用而使用数种不同类型的谐振器，例如薄膜体声谐振器（FBAR）、耦合式谐振器滤波器（SBAR）、堆叠式体声谐振器（SBAR）、双重体声谐振器（DBAR）及固态安装式谐振器（SMR）。
典型的声谐振器包括上电极、下电极、位于上下电极之间的压电材料、位于下电极下面的声反射结构以及位于声反射结构下面的衬底。通常将上电极、压电层、下电极三层材料在厚度方向上重叠的区域定义为谐振器的有效区域。当在电极之间施加一定频率的电压信号时，由于压电材料所具有的逆压电效应，有效区域内的上下电极之间会产生垂直方向传播的声波，声波在上电极与空气的交界面和下电极下的声反射结构之间来回反射并在一定频率下产生谐振。
 技术问题
基于上述问题，本申请实施例提供一种新型结构的谐振器及半导体器件。
 技术解决方案
本申请实施例的第一方面提供一种谐振器，包括：
衬底；
多层结构，形成于所述衬底上，所述多层结构由下至上依次包括下电极层、压电层和上电极层；
其中，在所述衬底和所述多层结构之间形成有腔体，所述腔体由所述衬底的上侧面和所述多层结构的下侧面围成，所述多层结构的下侧面与所述腔体对应部分的中部区域为平面，且中部区域的边缘与所述腔体边缘之间为圆滑过渡的平滑曲面，所述平滑曲面位于所述衬底的上侧面和所述平面之间。
可选的，所述平滑曲面包括圆滑过渡连接的第一曲面和第二曲面。
可选的，所述第一曲面的竖截面呈倒抛物线状，所述第二曲面的竖截面呈抛物线状，且第一曲面位于第二曲面之下。
可选的，所述平滑曲面各点的曲率小于第一预设值。
可选的，所述平滑曲面与所述衬底接触处的切面与所述衬底的夹角小于45度。
可选的，所述衬底的上侧面与所述腔体对应的部分无突变。
可选的，所述腔体的高度为100纳米至2000纳米之间的任意值。
可选的，所述衬底为砷化镓衬底、碳化硅衬底、蓝宝石衬底、铌酸锂衬底、钽酸锂衬底和各种复合材料衬底中的任一种。
可选的，所述衬底为Si衬底。
本申请实施例的第二方面提供一种半导体器件，包括上述任一种谐振器。
 有益效果
本申请实施例，通过在衬底和多层结构之间形成有腔体，腔体由衬底的上侧面和多层结构的下侧面围成，多层结构的下侧面与腔体对应部分的中部区域为平面，且中部区域的边缘与腔体边缘之间为圆滑过渡的平滑曲面，所述平滑曲面位于所述衬底的上侧面和所述平面之间，从而形成一种新型的谐振器结构，且具有较好的性能。
而且，本申请中腔体结构使得谐振器的制作工艺相对简单、难度较小，因此成品率较高、一致性较好。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的谐振器的结构示意图；
图2是图1中A区域的放大示意图；
图3是本申请实施例提供的谐振器的制作过程流程图；
图4是本申请实施例提供的谐振器的制作过程示意图；
图5是本申请实施例提供的三次离子注入的示意图；
图6是本申请实施例提供的一种屏蔽层结构下进行倾斜方向的离子注入示意图；
图7是本申请实施例提供的四次离子注入的示意图；
图8是本申请实施例提供的又一种屏蔽层结构下进行倾斜方向的离子注入示意图。
本申请的实施方式
为了使本申请所要解决的技术问题、技术方案及有益效果更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
下面结合附图和具体实施方式对本申请作进一步详细的说明。
参见图1，本申请中的谐振器可以包括衬底100和多层结构200。多层结构200形成于所述衬底100上，所述多层结构200由下至上依次包括下电极层203、压电层202和上电极层201。其中，在所述衬底100和所述多层结构200之间形成有腔体300，所述腔体300由所述衬底100的上侧面和所述多层结构200的下侧面围成，所述多层结构200的下侧面与所述腔体100对应部分的中部区域2031为平面，且中部区域2031的边缘与所述腔体300边缘之间为圆滑过渡的平滑曲面2032，所述平滑曲面2032位于所述衬底100的上侧面和所述平面（中部区域2031对应的平面）之间。其中，平滑曲面2032能够保证谐振器腔体的性能，不发生突变。平滑曲面2032为多层结构200的下侧面的一部分。
上述谐振器，通过在衬底100和多层结构200之间形成有腔体300，腔体300由衬底100的上侧面和多层结构200的下侧面围成，多层结构200的下侧面与腔体100对应部分的中部区域2031为平面，且中部区域2031的边缘与腔体300边缘之间为圆滑过渡的平滑曲面2032，所述平滑曲面2032位于所述衬底100的上侧面和所述平面之间，从而形成一种新型的谐振器结构，且具有较好的性能。
参见图2，一些实施例中，所述平滑曲面2032可以包括圆滑过渡连接的第一曲面20321和第二曲面20322。其中，圆滑过渡连接的第一曲面20321和第二曲面20322是指第一曲面20321和第二曲面20322之间连接处无突变，且第一曲面20321和第二曲面20322两者也为无突变的曲面，从而能够保证谐振器腔体的性能。其中，多层结构200是由很多个晶体组成的，无突变是指第一圆滑曲面处的各个晶体之间的间隙不应过大以影响谐振器的性能。
例如，所述第一曲面20321的竖截面可以呈倒抛物线状，所述第二曲面20322的竖截面可以呈抛物线状，且第一曲面20321位于第二曲面20322之下。第一曲面20321和第二曲面20322圆滑连接。当然，第一曲面20321和第二曲面20322还可以为其他形状的曲面，能够达到平滑曲面2032处的各个晶体之间的间隙不影响谐振器的性能即可。
另外，所述衬底100的上侧面无突变。可选的，所述衬底100的上侧面为平面。
一些实施例中，对于平滑曲面2032整体是平滑的，可以为平滑曲面2032各点的曲率小于第一预设值。对于第一预设值可以根据实际情况设定，以达到平滑曲面2032处的各个晶体之间的间隙不影响谐振器的性能的目的。为了保证多层结构力学特性和电学特性，过渡区域圆滑曲面的曲率要尽可能小，在牺牲层厚度一定的情况下，尽可能小的曲率要求过渡区长度增加，会增加当个谐振器的面积，因此要优化过渡区的曲率和过渡区长度。
优选的，腔体300的高度为100纳米至2000纳米之间的任意值。
一些实施例中，所述平滑曲面2032与所述衬底100接触处的切面与所述衬底100的夹角小于45度。在切面与所述衬底100的夹角小于45度时，能够使得谐振器具有更优的性能。
以上实施例中，衬底100可以为硅衬底，也可以为砷化镓衬底、碳化硅衬底、蓝宝石衬底、铌酸锂衬底、钽酸锂衬底和各种复合材料衬底中的任一种，对此不予限制。
相对于传统的薄膜体声谐振器（FBAR）、耦合式谐振器滤波器（SBAR）、堆叠式体声谐振器（SBAR）、双重体声谐振器（DBAR）及固态安装式谐振器（SMR），由上述谐振器制作方法制作出的谐振器，可以称为桥形体声波谐振器（BBAR）。
参见图3，以下对上述谐振器的制作过程进行详细论述。
步骤101，对衬底进行预处理，形成预设厚度的介质层。
本步骤中，所述预处理可以为氧化处理，即对衬底100进行氧化处理，形成与预设厚度的介质层400，如图4（b）所示。一些实施例中，可以将所述衬底置于氧化气氛中进行氧化处理，以使得所述衬底上形成预设厚度的氧化层。示例性的，可以在预设温度范围的工艺温度环境中，向所述衬底通入高纯氧气，通过湿氧氧化或氢氧合成氧化的方式使得所述衬底上形成氧化层。其中，预设温度范围可以为1000摄氏度至1200摄氏度。
另外，步骤101的实现过程还可以为：通过气相沉积法对衬底100进行预处理，形成预设厚度的介质层400，如图4（b）所示。其中，气相沉积法可以为PECVD（Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法）或LPCVD（Low Pressure Chemical Vapor Deposition，低压力化学气相沉积法）。
另外，步骤101的实现过程还可以为：通过溅射法对衬底进行预处理，形成预设厚度的介质层。
另外，步骤101的实现过程还可以为：通过电子束蒸发法对衬底进行预处理，形成预设厚度的介质层。
步骤102，对介质层的预设区域进行离子注入处理。
本步骤中，通过在介质层的预设区域进行离子注入处理，可以使得介质层的预设区域的刻蚀或腐蚀的速率大于介质层的预设区域之外的刻蚀或腐蚀的速率，从而在在对介质层的刻蚀或腐蚀过程中能够形成预设形状的介质层。
一些实施例中，步骤102的实现过程可以为：在介质层400的预设区域形成屏蔽层500，在形成屏蔽层500后的整个介质层400进行离子注入处理，如图4（c）所示。
其中，通过在介质层400的预设区域形成屏蔽层500，然后对整个介质层400进行离子注入，可以使得屏蔽层500屏蔽或一定程度上减轻离子注入对屏蔽层500覆盖的介质层400的影响，从而能够在后续步骤中形成预设形状的牺牲材料部分。
本步骤中，所述在介质层的预设区域形成屏蔽层，可以包括：在介质层400的预设区域形成边缘厚度小于中部厚度的屏蔽层500，且屏蔽层500的中部区域为平面，如图4（c）中所示。对图4（c）中的介质层400进行离子注入时，由于由屏蔽层500的存在，可以使得屏蔽层500区域的介质层部分收到离子注入的影响较小，当离子注入的能量较小时，离子注入并不会穿透屏蔽层500到达屏蔽层500下面的介质层，而没有覆盖屏蔽层500的部分则会被注入预设深度的掺杂杂质。而屏蔽层500的形状会影响步骤103中牺牲材料部分的形状，一般情况下，牺牲材料部分的形状与屏蔽层500的形状一致。因此，可以通过设置屏蔽层的具体形状来达到最终需要的腔体的形状。
作为一种可实施方式，步骤102中所述的对形成屏蔽层后的整个介质层进行离子注入处理，包括：在包含屏蔽层区域的整个介质层上注入预设剂量和预设能量的掺杂杂质。其中，预设剂量影响步骤103中的刻蚀或腐蚀速率，预设能量影响离子注入的深度，最终影响腔体的高度。
具体的，被离子注入的某一区域的预设剂量越大，则在步骤103中对该区域的刻蚀或腐蚀速率越大；被离子注入的某一区域的预设剂量越小，则在步骤103中对该区域的刻蚀或腐蚀速率越小；若由于屏蔽层500的存在某一区域未被注入掺杂杂质，则在步骤103中对该区域的刻蚀或腐蚀速率最小。
对于预设能量，被离子注入的某一区域的预设能量越大，则对该区域的离子注入深度越大，最终形成腔体后该部分对应的腔体高度越大；被离子注入的某一区域的预设能量越小，则对该区域的离子注入深度越小，最终形成腔体后该部分对应的腔体高度越小。
以上可实施方式中，预先设置好屏蔽层400的形状，仅通过一次预设剂量和预设能量的离子注入，即可在步骤103中刻蚀或腐蚀呈需要形状的牺牲材料部分，例如牺牲材料部分的形状为顶面为平面且竖截面呈桥状结构。
可选的，为获得性能更优的谐振器腔体，对于所述屏蔽层，其中部区域的边缘到其边缘的厚度逐渐减小，从而能够使得屏蔽层中部区域的边缘到屏蔽层边缘之间的曲面无突变，进而保证谐振器腔体的性能。其中，最终的谐振器的衬底100和多层结构200是由很多个晶体构成的，无突变是指屏蔽层中部区域的边缘到屏蔽层边缘之间的曲面各点之间都是相对圆滑过渡的，最终使得谐振器多层结构200与腔体对应的部分的各个晶体之间的间隙不应过大以影响谐振器的性能。
例如，所述屏蔽层的中部区域的边缘与所述屏蔽层边缘之间为圆滑过渡的平滑曲面，这样最终形成的谐振器腔体如图1中300所示。其中，谐振器腔体对应的部分的各个晶体之间的间隙不应过大以影响谐振器的性能，不会发生突变。一些实施例中，平滑曲面与所述衬底100接触处的切面与所述衬底100的夹角小于45度，这样形成的谐振器腔体性能较优。
示例性的，所述平滑曲面可以包括圆滑过渡连接的第一曲面和第二曲面。
所述第一曲面的竖截面呈倒抛物线状，所述第二曲面的竖截面呈抛物线状，且第一曲面位于第二曲面之下。这样，最终形成的谐振器腔体如图1中300所示，与平滑曲面中的第一曲面和第二曲面相对应。
作为另一种可实施方式，步骤102中所述的对形成屏蔽层后的整个介质层进行离子注入处理，包括：在包含屏蔽层区域的整个介质层上多次注入预设剂量和预设能量的掺杂杂质，其中每次离子注入的预设剂量和预设能量均不相同或不尽相同。
其中，屏蔽层的厚度可以各处一致，也可以边缘厚度小于中部厚度且中部区域为平面，对此不予限制。此时，通过调整每次离子注入的预设剂量和预设能量，均能够使得步骤103中的牺牲材料部分的形状为需要的形状。
本实施例中，对于预设能量按照大小排序的各次离子注入中的预设剂量关系可以为由小到大再由大到小。这样，经过多次离子注入后，屏蔽层边缘处会形成多层掺杂杂质层，能量大的离子注入对应的掺杂杂质层较厚，能量小的离子注入对应的掺杂杂质层较薄，如图5所示。图5为清楚示意出离子注入的情况，故只示出了屏蔽层500和介质层400。
图5中，以三次不同剂量、不同能量的离子注入为例进行说明，但不限于此。假设，第一次离子注入的剂量为第一剂量，能量为第一能量；第二次离子注入的剂量为第二剂量，能量为第二能量；第三次离子注入的剂量为第三剂量，能量为第三能量；第一能量大于第二能量，第二能量大于第三能量；第一剂量大于第二剂量，第二剂量大于第三剂量。则第一次离子注入的深度为H1，第二次离子注入的深度为H2，第三次离子注入的深度为H3，则H1>H2>H3，每个掺杂杂质层如图5中的虚线所示。本实施例中，能量最大的第一次离子注入的深度小于屏蔽层500的厚度，因此屏蔽层500中部区域的下方未被离子注入。
可选的，每次离子注入的方向均与衬底100垂直，或
每次离子注入的方向均与衬底100呈不为90度的预设角度（每次离子注入的预设角度均不同或不尽相同），或
一部分次数的离子注入的方向与衬底100垂直，其余部分次数的离子注入的方向与衬底100呈小于预设角度的锐角。
可以理解的，对于屏蔽层的边缘处，通过变换离子注入的方向，能够调整屏蔽层相对于离子注入方向的厚度（如图6所示），从而得到不同深度的掺杂杂质层，使得牺牲材料部分边缘的曲面更为平滑。本实施例中，将预设剂量和预设能量的离子注入，再与每次离子注入的方向相结合，可以使得牺牲材料部分边缘的曲面更为平滑。
以上为屏蔽层的边缘厚度小于中部厚度的情况，对于屏蔽层厚度一致的情况，详述如下。
步骤102中所述的在介质层的预设区域形成屏蔽层，对形成屏蔽层后的整个介质层进行离子注入处理，包括：
A、在介质层的预设区域形成厚度一致的屏蔽层；
B、在形成屏蔽层区域的整个介质层上注入预设剂量和预设能量的掺杂杂质；
循环多次执行去除该屏蔽层以及步骤A和B，且各次离子注入对应的预设区域、预设剂量、预设能量均不同或不尽相同。
其中，通过循环多次执行去除该屏蔽层以及步骤A和B，能够在介质层400形成多层掺杂杂质层，然后在步骤103中对介质层400进行刻蚀或腐蚀，形成所需形状的牺牲材料部分。
各次离子注入对应的预设区域、预设剂量、预设能量均不同或不尽相同，即，离子注入对应的预设区域、预设剂量、预设能量三个因素，各次离子注入的三个因素均不相同；各次离子注入的三个因素中也可以有一个因素相同。
参见图7，以四次离子注入为例进行说明，但不以此为限。图7为清楚示意出离子注入的情况，只示出了屏蔽层500和介质层400。在介质层的第一预设区域形成厚度一致的第一屏蔽层，并进行第一次离子注入，第一次离子注入的能量最小，对应离子注入深度最小；去除第一屏蔽层后，在介质层的第二预设区域形成厚度一致的第二屏蔽层，并进行第二次离子注入，第二次离子注入的能量大于第一次离子注入的能量，离子注入深度大于第一次离子注入的深度；去除第二屏蔽层后，在介质层的第三预设区域形成厚度一致的第三屏蔽层，并进行第三次离子注入，第三次离子注入的能量大于第二次离子注入的能量，离子注入深度大于第二次离子注入的深度；去除第三屏蔽层后，在介质层的第四预设区域形成厚度一致的第四屏蔽层，并进行第四次离子注入，第四次离子注入的能量大于第三次离子注入的能量，离子注入深度大于第三次离子注入的深度。其中，四次离子注入中能量与预设区域大小呈反比关系，且较大的预设区域包含较小的预设区域。
可选的，步骤102中，每次离子注入的方向均与衬底垂直，或
每次离子注入的方向均与衬底呈不为90度的预设角度（每次离子注入的预设角度均不同或不尽相同），或
一部分次数的离子注入的方向与衬底垂直，其余部分次数的离子注入的方向与衬底呈小于预设角度的锐角。
可以理解的，当屏蔽层400的厚度各处一致时，屏蔽层400边缘处可以通过变换离子注入的方向，使得离子注入的方向与衬底100呈不为90度的预设角度（如图8所示），这样在离子注入的方向上，屏蔽层400的厚度不再是各处一致，从而使得屏蔽层400的边界处的离子注入效果与屏蔽层边缘厚度小于中部区域厚度的屏蔽层的离子注入效果基本相同。
步骤103，对经过离子注入处理后的介质层进行刻蚀或腐蚀，形成牺牲材料部分；所述牺牲材料部分的形状为顶面为平面且竖截面呈桥状结构。
其中，通过步骤102对介质层进行离子注入处理后，屏蔽层下部的介质层未被离子注入或注入深度较浅，屏蔽层之外的介质层中被离子注入的较深，从而在对介质层进行刻蚀时，屏蔽层和屏蔽层之外的介质层被刻蚀或腐蚀的速率较快，未被离子注入的介质层被刻蚀或腐蚀的速率较慢，最终能够形成所需形状的牺牲材料部分。本实施例中，所述牺牲材料部分600的形状为顶面为平面且竖截面呈桥状结构（参见图2（d）所示）。所述顶面为牺牲材料部分600远离衬底100的侧面。
一些实施例中，屏蔽层可以采用SiN，也可以采用多层膜结构，也可以为光刻胶，对此不予限制。屏蔽层用于屏蔽掉离子注入或阻挡部分离子注入，进而导致屏蔽区和非屏蔽区刻蚀或腐蚀速率相差较大：没有屏蔽层部分的刻蚀或腐蚀速率较快，有屏蔽层部分的刻蚀或腐蚀速率较慢，最终形成本步骤中的牺牲材料部分。由于屏蔽层的中部区域的边缘到屏蔽层边缘的厚度逐渐减小，因此能够在屏蔽层边缘形成一个没有速率变化的过渡区域，该过渡区域通过优化氧化方式和屏蔽层种类和结构，可以形成圆滑曲面，在该圆滑曲面上生长含AlN等压电薄膜的多层结构，可以确保压电薄膜的晶体质量。
步骤104，在已形成牺牲材料部分的衬底上形成多层结构，所述多层结构由下至上依次包括下电极层、压电层和上电极层。
参见图4（e）所示，在已形成牺牲材料部分600的衬底100上形成多层结构200，所述多层结构200由下至上依次包括下电极层203、压电层202和上电极层201。
步骤105，去除所述牺牲材料部分。
参见图4（f），本步骤中，去除所述牺牲材料部分，形成腔体300，腔体300的形状与牺牲材料部分的形状一致。
以上所述仅为本申请的较佳实施例而已，并不用以限制本申请，凡在本申请的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本申请的保护范围之内。

Claims (10)

  1. 一种谐振器，其特征在于，包括：
    衬底；
    多层结构，形成于所述衬底上，所述多层结构由下至上依次包括下电极层、压电层和上电极层；
    其中，在所述衬底和所述多层结构之间形成有腔体，所述腔体由所述衬底的上侧面和所述多层结构的下侧面围成，所述多层结构的下侧面与所述腔体对应部分的中部区域为平面，且中部区域的边缘与所述腔体边缘之间为圆滑过渡的平滑曲面，所述平滑曲面位于所述衬底的上侧面和所述平面之间。
  2. 根据权利要求1所述的谐振器，其特征在于，所述平滑曲面包括圆滑过渡连接的第一曲面和第二曲面。
  3. 根据权利要求2所述的谐振器，其特征在于，所述第一曲面的竖截面呈倒抛物线状，所述第二曲面的竖截面呈抛物线状，且第一曲面位于第二曲面之下。
  4. 根据权利要求1所述的谐振器，其特征在于，所述平滑曲面各点的曲率小于第一预设值。
  5. 根据权利要求1所述的谐振器，其特征在于，所述平滑曲面与所述衬底接触处的切面与所述衬底的夹角小于45度。
  6. 根据权利要求1所述的谐振器，其特征在于，所述衬底的上侧面与所述腔体对应的部分无突变。
  7. 根据权利要求1所述的谐振器，其特征在于，所述腔体的高度为100纳米至2000纳米之间的任意值。
  8. 根据权利要求1至7任一项所述的谐振器，其特征在于，所述衬底为砷化镓衬底、碳化硅衬底、蓝宝石衬底、铌酸锂衬底、钽酸锂衬底和各种复合材料衬底中的任一种。
  9. 根据权利要求1至7任一项所述的谐振器，其特征在于，所述衬底为Si衬底。
  10. 一种半导体器件，其特征在于，包括权利要求1至9任一项所述的谐振器。
PCT/CN2019/074933 2019-01-28 2019-02-13 谐振器及半导体器件 WO2020155192A1 (zh)

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