WO2020153770A1 - Semiconductor light-emitting device - Google Patents

Semiconductor light-emitting device Download PDF

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Publication number
WO2020153770A1
WO2020153770A1 PCT/KR2020/001132 KR2020001132W WO2020153770A1 WO 2020153770 A1 WO2020153770 A1 WO 2020153770A1 KR 2020001132 W KR2020001132 W KR 2020001132W WO 2020153770 A1 WO2020153770 A1 WO 2020153770A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor light
light emitting
solder
emitting device
flip chip
Prior art date
Application number
PCT/KR2020/001132
Other languages
French (fr)
Korean (ko)
Inventor
안상정
Original Assignee
안상정
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020190008109A external-priority patent/KR102275360B1/en
Priority claimed from KR1020190044092A external-priority patent/KR20200121488A/en
Priority claimed from KR1020190046011A external-priority patent/KR20200122803A/en
Application filed by 안상정 filed Critical 안상정
Publication of WO2020153770A1 publication Critical patent/WO2020153770A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/52—Encapsulations
    • H01L33/54—Encapsulations having a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present disclosure relates to a semiconductor light emitting device (LIGHT EMITTING DEVICE) to which a flip chip is applied as a whole, and more particularly, to a semiconductor light emitting device having improved stability of electrical connection.
  • the semiconductor light emitting device includes a flip-structured semiconductor light emitting chip 2, an encapsulant 4, and a reflector 6 (eg, white PSR).
  • the flip-structured semiconductor light-emitting chip 2 has an electrode 80 and an electrode 90, and the encapsulant 4 has an inclined surface 4b to emit light from the flip-structured semiconductor light-emitting chip 2 You can adjust the angle.
  • the reflector 6 can be formed by screen printing or spin coating a white PSR and then patterning it through a general photolithography process. If necessary, for electrical connection with the outside, the external electrode 81 and the external electrode 91 are formed through a deposition process.
  • FIG. 2 is a view showing an example of a semiconductor light emitting device to which the flip chip proposed in U.S. Patent No. 10,008,648 is applied, a problem in the case of using the reflector 6 shown in FIG. 1, that is, the reflector 6 has a white PSR and It is made of a flexible material, and in order to solve the problem that the positional accuracy of the flipped semiconductor light emitting chip 2 is deteriorated in the course of various processes, it is a frame of a preformed and rigid material.
  • a semiconductor light emitting device 200 to which a flip chip using a mold 210 (for example, an injection molded mold) is applied has been proposed.
  • the semiconductor light emitting device 200 includes a mold 210, a flipped semiconductor light emitting chip 220 and an encapsulant 230.
  • 211 is a side wall
  • 212 is a bottom
  • 213 is a hole
  • 214 is a cavity
  • 215 is a top surface of the bottom 212
  • 216 is a bottom surface of the bottom 212
  • 217 is a side wall 211
  • the outer surface, 218 is the inner surface of the sidewall 211
  • 219 is the height of the bottom portion 212
  • H is the height of the sidewall 211
  • 221 is the electrode
  • 222 is the flip-emitting semiconductor light emitting chip 220.
  • the height of, 231 is a light converting agent (for example, phosphor), 240 is a side wall of the hole 213.
  • the semiconductor light emitting device is the same as the conventional SMD (Surface-Mounted Device) type semiconductor light emitting device (for example, US Pat. No. 6,066,861) in that it has a mold 210, but the lead frame or lead electrode It has a difference in that it is not provided, and solves the problem of the semiconductor light emitting device to which the flip chip shown in FIG. 1 is applied, as described above, while the lead frame is involved in bonding with an external substrate (such as poor bonding). Can be solved.
  • SMD Surface-Mounted Device
  • the semiconductor light emitting device includes a mold 113 and a semiconductor light emitting chip 123 having a flip structure.
  • the mold 113 is provided with a conductive portion TH1 and a conductive portion TH2, and the conductive portion TH1 and the conductive portion TH2 may be formed of a conductive paste or a solder material.
  • Reference numeral C is a cavity
  • reference numerals 121 and 122 are electrodes, respectively
  • reference numeral 131 may be an external substrate (eg, a PCB), a sub-mount, or the like. It is the same as the semiconductor light emitting device to which the flip chip shown in FIG. 2 is applied in that it does not have a lead frame or a lead electrode, but a conductive part for physical and electrical bonding of the external substrate 131 and the semiconductor light emitting chip 123 having a flip structure ( TH1) and the conductive part (TH2) intervene, and thus, as pointed out in FIG.
  • the physical bonding force is weak in the SMT process or the like, so that the bonding falls or the conductive part (TH1) and the conductive part (TH2) deviate from the mold 113. It can cause problems such as.
  • the semiconductor light emitting device to which the flip chip shown in FIG. 2 is applied it has an advantage in that the lead frame or the lead electrode is removed to eliminate the light absorbed by the lead frame or the lead electrode, but the flip chip shown in FIG.
  • it has an advantage in that all light generated in the semiconductor light emitting chip 123 having a flip structure is emitted upward by fundamentally blocking light leaking under the mold 113.
  • a lateral chip is used after being wire-bonded to an SMD type package, followed by a flip chip in response to the demand for high-power and high-voltage devices.
  • problems not suitable for the SMD type package have been raised, and the CSP type package shown in FIG. 1 is partially used, but as indicated above, a problem has been raised in the adjustment and manufacturing process of the directivity angle.
  • FIGS. 2 and 3 a leadless frame or a mold type LED package having no lead frame or lead electrode is being investigated.
  • the mold 113 is made (for example, injection molding) to form the conductive part TH1 and the conductive part TH2, the conductive part ( The holes corresponding to TH1) and the conductive part (TH2) are made together, and the holes to be injection-molded have a smooth surface corresponding to the surface roughness of the mold, and thereafter, the conductive parts (TH1) formed through deposition or plating, etc. And has a problem that the physical bonding force between the conductive part TH2 is not high.
  • FIG. 4 is a view showing another example of a semiconductor light emitting device to which the flip chip proposed in US Patent Publication No. US 10,008,648 is applied, and the reinforcing member 720 is provided to firmly maintain the shape of the semiconductor light emitting device in the mold 210. It is provided.
  • the semiconductor light emitting device using the flip chip shown in FIG. 2 removes the lead frame, and the electrode 221 ) Is directly bonded to the external electrode, and the semiconductor light emitting device to which the flip chip shown in FIG.
  • a reinforcing member 720 in addition to avoid direct connection between the electrode 221 and the reinforcing member 720. Takes the form.
  • the electrode 221 may fall off the lead frame. Because.
  • FIG. 5 and 6 are views showing an example of a semiconductor light emitting device to which the flip chip proposed in Korean Patent Publication No. 10-2018-0041489 is applied, wherein the semiconductor light emitting device 300 includes a mold 310 and a semiconductor light emitting chip ( 320), a sealing agent 330, and lead frames to lead electrodes 351 and 352. Holes 361 and 362 are provided in the mold 310, and the semiconductor light emitting chip 320 having a flip structure includes electrodes 321 and 322. Each electrode 321 and 322 is electrically connected directly to each lead frame or lead electrodes 351 and 352 through each hole 361 and 362, and solders 371 and 372 are used for electrical connection.
  • Reference numeral 311 is a bottom surface of the mold 310, 312 is a slope of the mold 310.
  • the reason why the lead electrodes 351 and 352 are mixed with the lead frame is that the lead electrodes 351 and 352 are connected in the form of a frame, and finally separated into a unit package (unit semiconductor light emitting device).
  • PPA thermoplastic resin
  • EMC thermosetting resin
  • a mold 310 made of PPA, PCT having a large thermal expansion coefficient When it is expanded and the solders 371 and 372 are deformed accordingly, the electrodes 321 and 322 and the solders 371 and 372 are separated, and it will be insufficient to prevent an electrical short circuit from occurring.
  • solders 371 and 372 Special attention is required to avoid re-melting.
  • the remelting phenomenon of the solders 371 and 372 causes serious quality problems in a module stage where a plurality of packages (a plurality of semiconductor light emitting devices) are arrayed on a PCB. This is because the process parameters (eg, process temperature, 250° C.) applied to the solders 371 and 372 are equivalent or nearly similar to those applied to the solder used when mounting the unit package on the PCB. It will be difficult to solve the quality problem related to the remelting with the semiconductor light emitting device using the flip chip shown in FIGS. 5 and 6.
  • a semiconductor light emitting device to which a flip chip is applied the semiconductor light emitting chip having a flip structure including an electrode; A mold having a bottom portion placed under the flip-shaped semiconductor light emitting chip facing the electrode, and having a plurality of holes corresponding to the electrodes formed on the bottom portion; A lead frame formed integrally with the mold and exposed through a plurality of holes;
  • a semiconductor light emitting device using a flip chip including a conductive portion provided in at least a portion of solder is provided in each of a plurality of holes for electrical communication between the electrode and the lead frame.
  • FIG. 1 is a view showing an example of a semiconductor light emitting device presented in US Patent Publication No. US9,773,950,
  • FIG. 2 is a view showing an example of a semiconductor light emitting device presented in US Patent Publication No. US 10,008,648,
  • FIG. 3 is a view showing an example of a semiconductor light emitting device presented in Korean Patent Publication No. 10-2018-0131303,
  • FIG. 5 and 6 are views showing an example of a semiconductor light emitting device presented in Korean Patent Publication No. 10-2018-0041489,
  • FIG. 7 and 8 are views showing an example of a semiconductor light emitting device to which a flip chip according to the present disclosure is applied,
  • FIG. 9 is a view showing an example of a process for forming a conductive portion according to the present disclosure.
  • FIG. 10 is a view showing an example of a process of designing a plurality of conductive parts according to the present disclosure
  • FIG. 11 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure
  • FIG. 12 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure.
  • FIG. 7(a) and 7(b) are views showing an example of a semiconductor light emitting device to which a flip chip according to the present disclosure is applied, wherein the semiconductor light emitting device is a mold 710, a semiconductor light emitting chip 720 having a flip structure, And an encapsulant 730 and lead frames to lead electrodes 751 and 752.
  • the flip-structured semiconductor light emitting chip 720 includes electrodes 721 and 722, and a bottom 711 of the mold 710 corresponds to a plurality of holes 761 and electrodes 722 corresponding to the electrodes 721. A plurality of holes 762 are formed.
  • Conductive portions 771 and 772 are provided in each hole 761 and each hole 762 to electrically connect the electrodes 721 and 722 to the lead frames to lead electrodes 751 and 752.
  • the mold 710 and the lead frame to It becomes possible to flexibly cope with mechanical stress generated due to the difference in thermal expansion of the lead electrodes 751 and 752.
  • FIG. 7(a) shows a cross-sectional view along the xx' direction of FIG. 7(b)
  • FIG. 8 shows a cross-sectional view along the yy' direction of FIG. 7(b), 4 for one electrode 721
  • Two conductive parts 771 are formed.
  • FIG. 8(a) to 8(d) shows a state in which an electrical junction is separated from a state in which a conductive part and an electrode are stably bonded. Even when a part (FIG. 8(c) and FIG. 8(d)) is separated, a part (FIG. 8(a) and FIG. 8(b)) may be joined to supply electricity from the conductive portion to the electrode.
  • the plurality of conductive parts 771 and 772 is sufficient to be 2 or more, but the larger the number, the more the above-described functions can be faithfully performed, and the mold technology for forming the mold 710 and the size of the electrodes 721 and 722 are limited. Currently, it is not easy to form holes 761 and 762 below 200 ⁇ m when using a mold.
  • the holes 761,762) are less than 200 ⁇ m.
  • the flip-structured semiconductor light emitting chip 720 used in displays and the like currently has a size of 1 mm or less, it is assumed that each of the electrodes 721 and 722 has a size of 500 ⁇ m or less.
  • the conductive parts 771 and 772 will have a diameter of 250 ⁇ m or less, but the conductive parts 771 and 772 may have a rectangular shape. It should be kept in mind. Basically, the width of the holes 761 and 762 will be designed to be 1/2 or less with respect to the width of the electrodes 721 and 722 in the direction in which the holes 761 and 762 are placed in plural.
  • Reference numeral 723 is a growth substrate (eg, a sapphire substrate), is provided on the opposite side of the electrodes 721 and 722, and can be removed by a process such as laser lift-off.
  • 712 is an inclined surface to a reflective wall and may be omitted.
  • 731 is an underfill and may be provided as needed. In the case of forming the underfill 731, since the underfill 731 material is divided into a plurality of conductive parts 771 and 772, it is also easy to penetrate the flip-structured semiconductor light emitting chip 720 and the bottom 711. .
  • the thickness from the bottom portion 711 to the lead frames to the lead electrodes 751 and 752, that is, the depth of the holes 761 and 762 may be about 30 to 150 ⁇ m, and when formed thinly, the bottom portion 711 is a semiconductor light emitting chip 720 ) Does not sufficiently reflect the light generated, and since the light transmitted through it may be absorbed by the lead frames or the lead electrodes 751 and 752, the lead frames or the lead electrodes 751 and 752 are made of a reflective metal (eg, Ag, Al). It is preferably plated.
  • a reflective metal eg, Ag, Al
  • the conductive portions 771 and 772 may be formed without limitation, such as a conductive paste or a plating layer, but preferably SAC (Sn-Ag-Cu) in which at least a part of the conductive portions 771 and 772 is a tin (Sn)-based mixture; for example: SAC305, SAC405 ), an indium (In)-based mixture, In-Pd may be made of a solder.
  • SAC Sn-Ag-Cu
  • Solder formation may be performed using a method such as dotting or screen printing.
  • the Pilling-Bedworth ratio in corrosion of metals, is the ratio of the volume of the elementary cell of a metal oxide to the volume of the elementary cell of the corresponding metal from which the oxide is created). If the PB ratio is less than 1, the oxide coating is thin and thus does not serve as a protective film. If the PB ratio is greater than 2, the oxide coating is chip-off and does not function as a protective film. When the PB ratio is greater than 1 and less than 2, the oxide coating serves as a strong protective film against passivation and additional oxidation.
  • Such materials include Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, Ti, and PB ratios in the vicinity of 1 to 2 It should be borne in mind that this can be used.
  • this material By adding this material to the conductive portions 771 and 772 together with the tin (Sn)-based or indium (In)-based mixture, an oxide surface coating is formed on the conductive portions 771 and 772, thereby preventing the physical properties from collapsing.
  • the melting point of SAC depends on the content of silver (Ag) and copper (Cu) excluding tin (Sn) and the type of additionally designed material, in particular, the additionally designed material with a PB ratio greater than 1 and less than 2. Depending on the content, therefore, when the design conditions of the semiconductor light emitting device or the use environment require a somewhat higher melting point, it is possible to select a solder material in consideration of this.
  • the conductive parts 771,772 are formed with Cu or Sn, and then form the conductive parts 771,772 with SAC.
  • a material having less brittleness and toughness, such as Cu or Sn, and having good toughness into a plurality of micro-scale holes 761 and 762, the conductive parts 771 and 772 The flexibility can be further improved.
  • an LDS additive additive(s) may be added to the mold 710, for example, a heavy metal complex containing palladium (Pd) and a metal oxide, metal oxide-coated Filler, copper chromium oxide spinel (CuO ⁇ Cr 2 O 3 spinel), salt containing copper (Cu), copper hydroxy phosphate, copper phosphate, first copper thiocyanate, spinel metal oxide, copper chromium oxide (CuO ⁇ Cr 2 O 3 ), organic metal complex, antimony (Sb) doped tin (Sn) oxide, copper-containing metal oxide, zinc (Zn)-containing metal oxide, tin (Sn)-containing metal oxide, magnesium (Mg)-containing metal oxide, aluminum (Al) containing metal oxide, gold (Au).
  • a heavy metal complex containing palladium (Pd) and a metal oxide, metal oxide-coated Filler copper chromium oxide spinel (CuO ⁇ Cr 2 O 3 spinel), salt containing copper (Cu), copper hydroxy phosphate,
  • AlN aluminum nitride
  • AlC aluminum carbide
  • Al 2 aluminum oxide
  • AlN aluminum nitride
  • AlON aluminum oxynitride
  • BN boron nitride
  • MgSiN 2 magnesium silicon nitride
  • Si 3 N 4 silicon carbide
  • SiC silicon carbide
  • SiC silicon carbide
  • graphite graphene
  • carbon fiber zinc (Zn) oxide
  • TiO 2 , ZnO, BaS, CaCO 3 At least one may be added.
  • FIG. 9 is a diagram showing a step of forming a conductive in accordance with the present disclosure, the first form of the solder paste as shown in Figure 9 (a) (773: Example: Cr 0 .1 -Cu 0.5 -Ag 3.0 -Sn) is injected into the hole 761 or 762. And by performing a heat treatment (reflow), as shown in Figure 9 (b), to form an oxide (Cr 2 O 3 ) surface film 774 to enable a stable joining role at a higher temperature, the formed conductive portion collapses To be maintained. This heat treatment may be performed after the electrodes 721 or 722 are positioned.
  • a 773: Example: Cr 0 .1 -Cu 0.5 -Ag 3.0 -Sn
  • the solder (775 for example, SAC
  • the electrode 721 or 722 is positioned and then secondarily subjected to reflow.
  • the bonding of the electrode 721 or 722 and the conductive portion is completed.
  • a material 776 such as a metal such as Cu or Sn
  • less brittle than the solder 773 is formed in the hole 761 or 762 in the same manner as plating.
  • the secondary solder 775 may be made of the same material as the primary solder 773, but the oxide surface coating 774 is formed by the primary solder 773 to protect the conductive portion, and the electrode 721 or 722 ) And a solder material in a form suited to the joint can be used.
  • FIG. 10 is a view showing an example of a process of designing a plurality of conductive parts according to the present disclosure, the maximum number of challenges (n max ) for a given side length (L chip ) of the flip-emitting semiconductor light emitting chip 720
  • the longest length of the electrode 721 or 722 is the L electrode , the minimum distance between the electrode 722 and the flip-emitting semiconductor light emitting chip 720 (necessary to prevent shorting of the chip 720 by the electrode 722)
  • Distance, eg 100 ⁇ m) a the minimum diameter of the conductive portion 772 (which is defined by the limitations of current manufacturing techniques when forming the hole 762 in the process of manufacturing the mold 710.
  • L chip 1000 ⁇ m
  • a 100 ⁇ m
  • b 50 ⁇ m
  • c 50 ⁇ m
  • K becomes 5
  • n max becomes 5
  • 5 conductive parts 772 are provided.
  • L chip 1100 ⁇ m
  • K becomes 5.667
  • n max becomes 5
  • L chip 1150 ⁇ m
  • K becomes 6, and n max becomes 6.
  • the length (L electrode ) of the electrode 772 is selected from the two sides of the electrode 772 of the electrode 772, and the length (L chip ) of the semiconductor light emitting chip 720 of the flip structure is also a chip ( By selecting one of the two sides of 720), that is, by arranging the long side of the electrode 772 to extend along the long side of the chip 720, n max can be maximized.
  • each of the electrodes 721 and 722 includes conductive parts 771 and 772 in a plurality of rows.
  • the total number of conductive parts 772 for one electrode 772 is given by m*n max .
  • m is the number of rows.
  • each of the electrodes 721 and 722 is divided into two or more sub-electrodes 721a and 721b and sub-electrodes 722a and 722b,
  • Each of the sub-electrodes 721a, 721b, 722a, and 722b includes one or more conductive portions 771 and 772, so that the electrodes 721 and 722 each have a plurality of conductive portions 771 and 772.
  • a semiconductor light emitting device to which a flip chip is applied the semiconductor light emitting chip having a flip structure including an electrode; A mold having a bottom portion placed under the flip-shaped semiconductor light emitting chip facing the electrode, and having a plurality of holes corresponding to the electrodes formed on the bottom portion; A lead frame formed integrally with the mold and exposed through a plurality of holes; And, it is provided in each of the plurality of holes for electrical communication between the electrode and the lead frame, at least a portion of a conductive portion made of solder; characterized in that it comprises a flip chip semiconductor light emitting device comprising a.
  • the bottom portion has a first roughness
  • the hole is a semiconductor light emitting device to which a flip chip having a second roughness different from the first roughness is applied.
  • a semiconductor light emitting device using a flip chip in which a metal having a P-B ratio greater than 1 and less than 2 is added to solder.
  • the solder is a semiconductor light emitting device using a flip chip to which at least one of Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, and Ti is added.
  • the solder is a semiconductor light emitting device using a flip chip containing SAC (Sn-Ag-Cu), a tin (Sn)-based mixture.
  • the solder is a semiconductor light emitting device using a flip chip containing In-Pd, which is an indium-based mixture.
  • the solder is a semiconductor light emitting device to which a flip chip including Cr is additionally applied.
  • the conductive portion is a semiconductor light emitting device using a flip chip having a plating layer between solder and a lead frame.
  • a semiconductor light emitting device employing a flip chip, wherein the conductive part includes a first solder having a metal having a PB ratio greater than 1 and smaller than 2, and a second solder bonding to an electrode on top of the first solder.
  • the mold is a semiconductor light emitting device using a flip chip, characterized in that it contains an LDS additive.
  • a solder is a semiconductor light emitting device to which a flip chip having an oxide surface coating is applied.
  • the conductive portion is a semiconductor light-emitting device in which a flip chip including a conductive material having less brittleness than solder is applied to the bottom of the solder in the hole.
  • the conductive portion is a semiconductor light emitting device to which a flip chip including a primary solder and a secondary solder positioned on the primary solder is applied.
  • the primary solder is a semiconductor light emitting device using a flip chip having an oxide surface coating between the primary solder and the secondary solder.
  • L chip is the length of the side of the flip-structure semiconductor light-emitting chip
  • a is the minimum distance between the electrode and the flip-structure semiconductor light-emitting chip
  • D is the minimum diameter of the conductive portion
  • b is the minimum distance of the electrode and the conductive portion
  • c is the conductive portion And the conductive part.
  • the length (L chip ) is the length of the long side of the flip-structured semiconductor light emitting chip, and the electrode is a semiconductor light emitting device to which a flip chip extending along the long side of the flipped semiconductor light emitting chip is applied.
  • a semiconductor light-emitting device in which an electrode is formed of a plurality of sub-electrodes.
  • the semiconductor light emitting device to which one flip chip according to the present disclosure is applied it is possible to stably secure the electrical connection between the lead frame and the flipped semiconductor light emitting chip.
  • a PCT having a large coefficient of thermal expansion is used as a white mold and a semiconductor light emitting chip having a flip structure is used, it is possible to stably secure the electrical connection between the lead frame and the electrode.

Abstract

The present disclosure relates to a semiconductor light-emitting device having a flip chip applied thereto, comprising: a semiconductor light-emitting chip having a flip structure including an electrode; a mold having a bottom portion placed under the semiconductor light-emitting chip having the flip structure so as to face the electrode, and having a plurality of holes corresponding to the electrode formed on the bottom portion; a lead frame formed integrally with the mold and exposed through the plurality of holes; and a conductive part provided in each of the plurality of holes for electrical communication between the electrode and the lead frame and having at least a portion made of solder.

Description

반도체 발광소자Semiconductor light emitting device
본 개시(Disclosure)는 전체적으로 플립 칩을 적용한 반도체 발광소자(LIGHT EMITTING DEVICE)에 관한 것으로, 특히 전기적 연결의 안정성을 향상시킨 반도체 발광소자에 관한 것이다.The present disclosure (Disclosure) relates to a semiconductor light emitting device (LIGHT EMITTING DEVICE) to which a flip chip is applied as a whole, and more particularly, to a semiconductor light emitting device having improved stability of electrical connection.
여기서는, 본 개시에 관한 배경기술이 제공되며, 이들이 반드시 공지기술을 의미하는 것은 아니다(This section provides background information related to the present disclosure which is not necessarily prior art).Here, background technology is provided in connection with the present disclosure, and this does not necessarily mean prior art.
도 1은 미국 등록특허공보 제9,773,950호에 제시된 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면으로서, CSP(Chip-Scaled Package) 형태의 반도체 발광소자가 제시되어 있다. 반도체 발광소자는 플립 구조의 반도체 발광 칩(2), 봉지제(4) 및 반사체(6; 예: 백색 PSR)를 포함한다. 플립 구조의 반도체 발광 칩(2)은 전극(80)과 전극(90)을 구비하며, 봉지제(4)는 경사면(4b)을 구비하여 플립 구조의 반도체 발광 칩(2)으로부터 나온 빛의 출사각을 조절할 수 있다. 반사체(6)는 백색의 PSR을 스크린 프린팅 또는 스핀 코팅한 다음, 일반적인 포토리소그라피 공정을 통해 패터닝함으로써 형성될 수 있다. 필요에 따라, 외부와의 전기적 연결을 위해, 외부 전극(81)과 외부 전극(91)이 증착 공정을 통해 형성된다.1 is a view showing an example of a semiconductor light emitting device to which the flip chip proposed in U.S. Patent No. 9,773,950 is applied, and a semiconductor light emitting device in the form of a chip-scale package (CSP) is presented. The semiconductor light emitting device includes a flip-structured semiconductor light emitting chip 2, an encapsulant 4, and a reflector 6 (eg, white PSR). The flip-structured semiconductor light-emitting chip 2 has an electrode 80 and an electrode 90, and the encapsulant 4 has an inclined surface 4b to emit light from the flip-structured semiconductor light-emitting chip 2 You can adjust the angle. The reflector 6 can be formed by screen printing or spin coating a white PSR and then patterning it through a general photolithography process. If necessary, for electrical connection with the outside, the external electrode 81 and the external electrode 91 are formed through a deposition process.
도 2는 미국 등록특허공보 제10,008,648호에 제시된 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면으로서, 도 1에 제시된 반사체(6)를 이용하는 경우의 문제점, 즉 반사체(6)가 백색 PSR과 같이 플렉서블(flexible)한 재질로 이루어져, 여러 공정을 거치는 과정에서 플립 구조의 반도체 발광 칩(2)의 위치 정확도가 떨어지는 문제점을 해소하기 위해, 미리 성형되고(preformed), 딱딱한(rigid) 재질의 프레임 내지 몰드(210; 예: 사출성형된 몰드)를 이용하는 플립 칩을 적용한 반도체 발광소자(200)가 제시되어 있다. 반도체 발광소자(200)는 몰드(210), 플립 구조의 반도체 발광 칩(220) 및 봉지제(230)를 포함한다. 부호 211은 측벽, 부호 212는 바닥부, 부호 213은 홀, 부호 214는 캐비티, 215는 바닥부(212)의 상면, 부호 216은 바닥부(212)의 하면, 부호 217은 측벽(211)의 외면, 부호 218은 측벽(211)의 내면, 부호 219는 바닥부(212)의 높이, 부호 H는 측벽(211)의 높이, 부호 221은 전극, 부호 222는 플립 구조의 반도체 발광 칩(220)의 높이, 부호 231은 광 변환제(예: 형광체), 부호 240은 홀(213)의 측벽이다. 이러한 반도체 발광소자는 몰드(210)를 구비한다는 점에서 종래의 SMD(Surface-Mounted Device) 타입의 반도체 발광소자(예: 미국 등록특허공보 US6,066,861호)와 동일하지만, 리드 프레임 내지 리드 전극을 구비하지 않는다는 점에서 차이를 가지며, 전술한 바와 같이 도 1에 제시된 플립 칩을 적용한 반도체 발광소자의 문제점을 해소하는 한편, 리드 프레임이 외부 기판과의 접합에 관여함으로써 발생하는 문제점(접합 불량 등)을 해소할 수 있게 된다.2 is a view showing an example of a semiconductor light emitting device to which the flip chip proposed in U.S. Patent No. 10,008,648 is applied, a problem in the case of using the reflector 6 shown in FIG. 1, that is, the reflector 6 has a white PSR and It is made of a flexible material, and in order to solve the problem that the positional accuracy of the flipped semiconductor light emitting chip 2 is deteriorated in the course of various processes, it is a frame of a preformed and rigid material. A semiconductor light emitting device 200 to which a flip chip using a mold 210 (for example, an injection molded mold) is applied has been proposed. The semiconductor light emitting device 200 includes a mold 210, a flipped semiconductor light emitting chip 220 and an encapsulant 230. 211 is a side wall, 212 is a bottom, 213 is a hole, 214 is a cavity, 215 is a top surface of the bottom 212, 216 is a bottom surface of the bottom 212, and 217 is a side wall 211 The outer surface, 218 is the inner surface of the sidewall 211, 219 is the height of the bottom portion 212, H is the height of the sidewall 211, 221 is the electrode, and 222 is the flip-emitting semiconductor light emitting chip 220. The height of, 231 is a light converting agent (for example, phosphor), 240 is a side wall of the hole 213. The semiconductor light emitting device is the same as the conventional SMD (Surface-Mounted Device) type semiconductor light emitting device (for example, US Pat. No. 6,066,861) in that it has a mold 210, but the lead frame or lead electrode It has a difference in that it is not provided, and solves the problem of the semiconductor light emitting device to which the flip chip shown in FIG. 1 is applied, as described above, while the lead frame is involved in bonding with an external substrate (such as poor bonding). Can be solved.
도 3은 한국 공개특허공보 제10-2018-0131303호에 제시된 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면으로서, 도 1에 제시된 반사체(6)를 이용하는 경우의 문제점을 해소하는 다른 형태의 반도체 발광소자가 제시되어 있다. 반도체 발광소자는 몰드(113) 및 플립 구조의 반도체 발광 칩(123)을 구비한다. 몰드(113)에는 도전부(TH1)와 도전부(TH2)가 구비되어 있으며, 도전부(TH1)와 도전부(TH2)는 도전성 페이스트나 솔더 물질로 형성될 수 있다. 부호 C는 캐비티이고, 부호 121, 122는 각각 전극이며, 부호 131은 외부 기판(예: PCB), 서브 마운트 등일 수 있다. 리드 프레임 내지 리드 전극을 구비하지 않는다는 점에서 도 2에 제시된 플립 칩을 적용한 반도체 발광소자와 동일하지만, 외부 기판(131)과 플립 구조의 반도체 발광 칩(123)의 물리적 및 전기적 접합에 도전부(TH1)와 도전부(TH2)가 개입하며, 따라서 도 2에서 지적한 바와 같이, SMT 공정 등에서 물리적 결합력이 약해 접합이 떨어지거나 도전부(TH1)와 도전부(TH2)가 몰드(113)로부터 이탈하는 등의 문제를 야기할 수 있다. 다만, 도 2에 제시된 플립 칩을 적용한 반도체 발광소자의 경우에 리드 프레임 내지 리드 전극을 제거하여 리드 프레임 내지 리드 전극에 의해 흡수되는 빛을 없앴다는 점에서는 이점을 가지지만, 도 3에 제시된 플립 칩을 적용한 반도체 발광소자의 경우에 몰드(113)의 아래로 누출되는 빛을 원천적으로 봉쇄하여 플립 구조의 반도체 발광 칩(123)에서 생성된 모든 빛이 상측으로 방출된다는 점에서 이점을 가진다.3 is a view showing an example of a semiconductor light emitting device to which the flip chip proposed in Korean Patent Publication No. 10-2018-0131303 is applied, and another form of solving the problem when using the reflector 6 shown in FIG. A semiconductor light emitting device is presented. The semiconductor light emitting device includes a mold 113 and a semiconductor light emitting chip 123 having a flip structure. The mold 113 is provided with a conductive portion TH1 and a conductive portion TH2, and the conductive portion TH1 and the conductive portion TH2 may be formed of a conductive paste or a solder material. Reference numeral C is a cavity, reference numerals 121 and 122 are electrodes, respectively, and reference numeral 131 may be an external substrate (eg, a PCB), a sub-mount, or the like. It is the same as the semiconductor light emitting device to which the flip chip shown in FIG. 2 is applied in that it does not have a lead frame or a lead electrode, but a conductive part for physical and electrical bonding of the external substrate 131 and the semiconductor light emitting chip 123 having a flip structure ( TH1) and the conductive part (TH2) intervene, and thus, as pointed out in FIG. 2, the physical bonding force is weak in the SMT process or the like, so that the bonding falls or the conductive part (TH1) and the conductive part (TH2) deviate from the mold 113. It can cause problems such as. However, in the case of the semiconductor light emitting device to which the flip chip shown in FIG. 2 is applied, it has an advantage in that the lead frame or the lead electrode is removed to eliminate the light absorbed by the lead frame or the lead electrode, but the flip chip shown in FIG. In the case of the semiconductor light emitting device to which it is applied, it has an advantage in that all light generated in the semiconductor light emitting chip 123 having a flip structure is emitted upward by fundamentally blocking light leaking under the mold 113.
엘이디 패키지의 발전 과정을 정리하면, 래터럴 칩(lateral chip)이 SMD 타입 패키지에 와이어 본딩되어 사용되다가, 고휘도(high-power) 및 고전압(high-voltage) 소자의 요구에 수반하여 플립 칩(flip chip)의 사용이 검토되었으나, SMD 타입 패키지에 적합하지 않는 문제점들이 제기되었으며, 도 1에 제시된 CSP 타입의 패키지가 일부 이용되고 있지만, 앞서 지적한 바와 같이, 지향각의 조절 및 제조 공정에 문제점이 제기되었으며, 도 2 및 도 3에 제시된 바와 같이, 리드 프레임 내지 리드 전극을 구비하지 않은 형태의 리드리스 프레임 또는 몰드 타입의 엘이디 패키지가 검토되고 있는 실정이다. 그러나 도 3에 제시된 플립 칩을 적용한 반도체 발광소자의 경우에, 도전부(TH1)와 도전부(TH2)의 형성을 위해, 몰드(113)가 만들어질 때(예: 사출성형), 도전부(TH1)와 도전부(TH2)에 대응하는 홀이 함께 만들어지며, 사출성형되는 홀은 금형의 표면거칠기에 대응하는 미끈한 표면을 가지게 되므로, 이후, 증착 또는 도금 등을 통해 형성되는 도전부(TH1)와 도전부(TH2)와의 물리적 결합력이 높지 않은 문제점을 가진다.To summarize the development process of the LED package, a lateral chip is used after being wire-bonded to an SMD type package, followed by a flip chip in response to the demand for high-power and high-voltage devices. Although the use of) has been reviewed, problems not suitable for the SMD type package have been raised, and the CSP type package shown in FIG. 1 is partially used, but as indicated above, a problem has been raised in the adjustment and manufacturing process of the directivity angle. , As shown in FIGS. 2 and 3, a leadless frame or a mold type LED package having no lead frame or lead electrode is being investigated. However, in the case of the semiconductor light emitting device to which the flip chip shown in FIG. 3 is applied, when the mold 113 is made (for example, injection molding) to form the conductive part TH1 and the conductive part TH2, the conductive part ( The holes corresponding to TH1) and the conductive part (TH2) are made together, and the holes to be injection-molded have a smooth surface corresponding to the surface roughness of the mold, and thereafter, the conductive parts (TH1) formed through deposition or plating, etc. And has a problem that the physical bonding force between the conductive part TH2 is not high.
도 4는 미국 등록특허공보 US10,008,648호에 제시된 플립 칩을 적용한 반도체 발광소자의 또 다른 예를 나타내는 도면으로서, 몰드(210)에 반도체 발광소자의 형태 유지를 견고하게 하도록 보강부재(720)가 구비된다. 반도체 발광소자의 제조 공정에 수반하는 발열, 그리고 이 발열에 수반하는 몰드 및/또는 리드 프레임의 열팽창의 관점에서, 도 2에 제시된 플립 칩을 적용한 반도체 발광소자는 리드 프레임을 제거하고, 전극(221)을 직접 외부전극에 접합하는 형태를 취하며, 도 4에 제시된 플립 칩을 적용한 반도체 발광소자는 이에 더해서 보강부재(720)를 구비하되 전극(221)과 보강부재(720)의 직접 연결을 피하는 형태를 취한다. 이는 리드 프레임을 구비하는 경우에, 플립 칩을 적용한 반도체 발광소자를 외부 기판(예 : PCB 기판, 서브마운트 등)과 접합하는 SMT 공정 등의 공정에서, 전극(221)이 리드 프레임으로부터 떨어질 수 있기 때문이다.4 is a view showing another example of a semiconductor light emitting device to which the flip chip proposed in US Patent Publication No. US 10,008,648 is applied, and the reinforcing member 720 is provided to firmly maintain the shape of the semiconductor light emitting device in the mold 210. It is provided. In view of heat generated by the manufacturing process of the semiconductor light emitting device and thermal expansion of the mold and/or the lead frame accompanying the heat generation, the semiconductor light emitting device using the flip chip shown in FIG. 2 removes the lead frame, and the electrode 221 ) Is directly bonded to the external electrode, and the semiconductor light emitting device to which the flip chip shown in FIG. 4 is applied is provided with a reinforcing member 720 in addition to avoid direct connection between the electrode 221 and the reinforcing member 720. Takes the form. In the case of having a lead frame, in a process such as an SMT process in which a semiconductor chip to which a flip chip is applied is bonded to an external substrate (eg, a PCB substrate, a submount, etc.), the electrode 221 may fall off the lead frame. Because.
도 5 및 도 6은 한국 공개특허공보 제10-2018-0041489호에 제시된 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면으로서, 반도체 발광소자(300)는 몰드(310), 반도체 발광 칩(320), 봉지제(330), 그리고 리드 프레임 내지 리드 전극(351,352)을 포함한다. 몰드(310)에는 홀(361,362)이 구비되어 있으며, 플립 구조의 반도체 발광 칩(320)은 전극(321,322)을 구비한다. 각각의 전극(321,322)은 각각의 홀(361,362)을 통해 각각의 리드 프레임 내지 리드 전극(351,352)에 전기적으로 직접 연결되며, 전기적 연결에는 솔더(371,372)가 사용된다. 미설명 부호 311은 몰드(310)의 바닥면, 312는 몰드(310)의 경사면이다. 여기서, 리드 전극(351,352)이 리드 프레임과 혼용되는 이유는 리드 전극(351,352)이 프레임의 형태로 연결되어 있다가, 최종적으로 단위 패키지(단위 반도체 발광소자)로 분리되기 때문이다. 도 5 및 도 6에 제시된 플립 칩을 적용한 반도체 발광소자는 SAC(Sn-Ag-Cu)를 솔더로 사용할 때의 문제점을 지적하면서, Au, Ag, Sn, Pb, Sb, In, AuSn, AgSn, SnSb, SnAgSb, PbIn, PbSn, PbSnAg, PbInAg, PbAg 및 이들의 합금 중 적어도 하나를 솔더(371,372)로 이용하고, 솔더(371,372)를 홀(361,362)에 위치시킴으로써, 솔더의 퍼짐 현상을 막고, 나아가 이후의 공정에서 플립 구조의 반도체 발광 칩(320)이 틀어지는 것을 방지하려는 시도를 하고 있으나, 전극(321,322)의 크기 내지 이보다 큰 크기(예: 1.1~2.0배)의 홀(361,362)이 사용되고, 여기에 솔더(371,372)가 충진되므로, 열가소성 수지(예: PPA, PCT) 내지 열경화성 수지(예: EMC, SMC)로 된 몰드(310), 특히 열팽창계수가 큰 PPA, PCT로 된 몰드(310)가 팽창되고, 이에 따라 솔더(371,372)가 변형될 때, 전극(321,322)과 솔더(371,372)가 분리되어 전기적 단락이 발생하는 것을 방지하기에는 미흡하다 할 것이다. 또한 플립 칩을 적용한 반도체 발광소자를 PCB(printed circuit board) 상에 솔더(soder)를 사용하여 실장(mounting)할 때 전극(321,322)과 리드 프레임 내지 리드 전극(351,352)을 접합하고 있는 솔더(371,372)의 재용융(re-melting) 현상이 발생하지 않도록 각별한 주의가 필요하다. 솔더(371,372)의 재용융 현상은 복수의 패키지(복수의 반도체 발광소자)가 PCB에 어레이된 모듈 단에서 심각한 품질 문제를 야기한다. 이는 솔더(371,372)에 적용되는 공정 파라미터(예: 공정온도, 250℃)가 PCB 상에 단위 패키지를 실장할 때 사용되는 솔더에 적용되는 공정 파라미터와 동등 또는 거의 유사하기 때문이다. 도 5 및 도 6에 제시된 플립 칩을 적용한 반도체 발광소자로는 상기 재용융 관련 품질 문제를 해결하기가 쉽지 않다 하겠다.5 and 6 are views showing an example of a semiconductor light emitting device to which the flip chip proposed in Korean Patent Publication No. 10-2018-0041489 is applied, wherein the semiconductor light emitting device 300 includes a mold 310 and a semiconductor light emitting chip ( 320), a sealing agent 330, and lead frames to lead electrodes 351 and 352. Holes 361 and 362 are provided in the mold 310, and the semiconductor light emitting chip 320 having a flip structure includes electrodes 321 and 322. Each electrode 321 and 322 is electrically connected directly to each lead frame or lead electrodes 351 and 352 through each hole 361 and 362, and solders 371 and 372 are used for electrical connection. Reference numeral 311 is a bottom surface of the mold 310, 312 is a slope of the mold 310. Here, the reason why the lead electrodes 351 and 352 are mixed with the lead frame is that the lead electrodes 351 and 352 are connected in the form of a frame, and finally separated into a unit package (unit semiconductor light emitting device). The semiconductor light emitting device using the flip chip shown in FIGS. 5 and 6 points out problems when using SAC (Sn-Ag-Cu) as a solder, while Au, Ag, Sn, Pb, Sb, In, AuSn, AgSn, Using at least one of SnSb, SnAgSb, PbIn, PbSn, PbSnAg, PbInAg, PbAg and their alloys as solders 371,372 and placing solders 371,372 in holes 361,362 to prevent the spread of solder, furthermore In the subsequent process, an attempt is made to prevent the flipped semiconductor light emitting chip 320 from being distorted, but the holes 361 and 362 of the size of the electrodes 321 and 322 to larger than this (for example, 1.1 to 2.0 times) are used here. Since the solder 371,372 is filled, a mold 310 made of a thermoplastic resin (eg, PPA, PCT) to a thermosetting resin (eg, EMC, SMC), in particular, a mold 310 made of PPA, PCT having a large thermal expansion coefficient When it is expanded and the solders 371 and 372 are deformed accordingly, the electrodes 321 and 322 and the solders 371 and 372 are separated, and it will be insufficient to prevent an electrical short circuit from occurring. In addition, solder (371,372) joining the electrodes 321,322 and the lead frame to the lead electrodes 351,352 when mounting a semiconductor device using a flip chip on a printed circuit board (PCB) using a solder. ) Special attention is required to avoid re-melting. The remelting phenomenon of the solders 371 and 372 causes serious quality problems in a module stage where a plurality of packages (a plurality of semiconductor light emitting devices) are arrayed on a PCB. This is because the process parameters (eg, process temperature, 250° C.) applied to the solders 371 and 372 are equivalent or nearly similar to those applied to the solder used when mounting the unit package on the PCB. It will be difficult to solve the quality problem related to the remelting with the semiconductor light emitting device using the flip chip shown in FIGS. 5 and 6.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This will be described at the end of'Details for the Invention'.
여기서는, 본 개시의 전체적인 요약(Summary)이 제공되며, 이것이 본 개시의 외연을 제한하는 것으로 이해되어서는 아니된다(This section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features). Here, an overall summary of the present disclosure is provided, and this should not be understood as limiting the appearance of the present disclosure (this section provides a general summary of the disclosure and is not a comprehensive disclosure of its full scope or all of its features).
본 개시에 따른 일 측면에 의하면(According to one aspect of the present disclosure), 플립 칩을 적용한 반도체 발광소자에 있어서, 전극을 구비하는 플립 구조의 반도체 발광 칩; 전극과 면하도록 플립 구조의 반도체 발광 칩의 아래에 놓이는 바닥부를 가지고, 바닥부에 전극에 대응하는 복수의 홀이 형성되어 있는 몰드; 몰드와 일체로 함께 형성되어, 복수의 홀을 통해 노출되는 리드 프레임; 그리고, 전극과 리드 프레임의 전기적 연통을 위해 복수의 홀 각각에 구비되며, 적어도 일부가 솔더로 이루어진 도전부;를 포함하는 플립 칩을 적용한 반도체 발광소자가 제시된다.According to an aspect of the present disclosure (According to one aspect of the present disclosure), a semiconductor light emitting device to which a flip chip is applied, the semiconductor light emitting chip having a flip structure including an electrode; A mold having a bottom portion placed under the flip-shaped semiconductor light emitting chip facing the electrode, and having a plurality of holes corresponding to the electrodes formed on the bottom portion; A lead frame formed integrally with the mold and exposed through a plurality of holes; In addition, a semiconductor light emitting device using a flip chip including a conductive portion provided in at least a portion of solder is provided in each of a plurality of holes for electrical communication between the electrode and the lead frame.
이에 대하여 '발명의 실시를 위한 구체적인 내용'의 후단에 기술한다.This will be described at the end of'Details for the Invention'.
도 1은 미국 등록특허공보 US9,773,950호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,1 is a view showing an example of a semiconductor light emitting device presented in US Patent Publication No. US9,773,950,
도 2는 미국 등록특허공보 US10,008,648호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,2 is a view showing an example of a semiconductor light emitting device presented in US Patent Publication No. US 10,008,648,
도 3은 한국 공개특허공보 제10-2018-0131303호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,3 is a view showing an example of a semiconductor light emitting device presented in Korean Patent Publication No. 10-2018-0131303,
도 4는 미국 등록특허공보 US10,008,648호에 제시된 반도체 발광소자의 또 다른 예를 나타내는 도면,4 is a view showing another example of the semiconductor light emitting device presented in US Patent Publication No. US 10,008,648,
도 5 및 도 6은 한국 공개특허공보 제10-2018-0041489호에 제시된 반도체 발광소자의 일 예를 나타내는 도면,5 and 6 are views showing an example of a semiconductor light emitting device presented in Korean Patent Publication No. 10-2018-0041489,
도 7 및 도 8은 본 개시에 따른 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면,7 and 8 are views showing an example of a semiconductor light emitting device to which a flip chip according to the present disclosure is applied,
도 9는 본 개시에 따라 도전부를 형성하는 공정의 일 예를 나타내는 도면,9 is a view showing an example of a process for forming a conductive portion according to the present disclosure,
도 10은 본 개시에 따라 복수의 도전부를 설계하는 과정의 일 예를 나타내는 도면,10 is a view showing an example of a process of designing a plurality of conductive parts according to the present disclosure,
도 11은 본 개시에 따라 복수의 도전부를 설계하는 과정의 또 다른 예를 나타내는 도면,11 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure;
도 12는 본 개시에 따라 복수의 도전부를 설계하는 과정의 또 다른 예를 나타내는 도면.12 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure.
도 7(a) 및 도 7(b)는 본 개시에 따른 플립 칩을 적용한 반도체 발광소자의 일 예를 나타내는 도면으로서, 반도체 발광소자는 몰드(710), 플립 구조의 반도체 발광 칩(720), 봉지제(730), 그리고 리드 프레임 내지 리드 전극(751,752)을 포함한다. 플립 구조의 반도체 발광 칩(720)은 전극(721,722)을 구비하며, 몰드(710)의 바닥부(711)에는 전극(721)에 대응하는 복수 개의 홀(761)과 전극(722)에 대응하는 복수 개의 홀(762)이 형성되어 있다. 각 홀(761)과 각 홀(762)에는 도전부(771,772)가 구비되어, 전극(721,722)과 리드 프레임 내지 리드 전극(751,752)을 전기적으로 연결한다. 전극(721,722) 각각에 복수의 도전부(771)와 복수의 도전부(772)를 구비함으로써, 도 5 및 도 6에 제시된 플립 칩을 적용한 반도체 발광소자와 달리, 몰드(710) 및 리드 프레임 내지 리드 전극(751,752)의 열팽창 차이로 발생된 기계적 스트레스(mechanical stress)에 대해 유연하게 대처하는 것이 가능해진다. 즉, 하나의 덩어리로 된(bulky) 솔더(371,372)가 아니라 작은 질량으로 나누어진 복수의 도전부를 이용하여 몰드(710) 및 리드 프레임 내지 리드 전극(751,752)의 열팽창 차이로 발생된 기계적 스트레스(mechanical stress)에 대해 유연하게 대응하는 것이 가능해진다. 나아가 일부의 도전부가 대응하는 전극과 떨어지는 경우에도 나머지 도전부에 의해 전기적 연결을 유지하는 것이 가능해지는 것이다. 도 7(a)에 도 7(b)의 x-x' 방향을 따르는 단면도를 나타내었고, 도 8에 도 7(b)의 y-y' 방향을 따르는 단면도를 나타내었으며, 하나의 전극(721)에 대해 4개의 도전부(771)가 형성되어 있다. 도 8(a)에서 도 8(d)로 가면서 도전부와 전극이 안정적으로 접합된 상태로부터 전기적 접합이 떨어진 상태까지를 보여준다. 일부(도 8(c) 및 도 8(d))가 떨어진 경우에도 일부(도 8(a) 및 도 8(b))가 접합되어 도전부로부터 전극으로 전기가 공급될 수 있다. 복수의 도전부(771,772)는 2이상인 것으로 족하지만, 그 갯수가 많을수록 전술한 기능을 충실히 할 수 있으며, 몰드(710)를 형성하는 금형기술과 전극(721,722)의 크기에 의해 제약을 받는다. 현재로서, 금형을 이용하는 경우에 200㎛ 이하로 홀(761,762)을 형성하는 것이 쉽지 않다. 한편 레이저 드릴링(Laser Drilling)을 이용하는 경우에, 200㎛ 이하로 홀(761,762)을 형성하는 것이 가능하다. 또한, 현재로서 디스플레이 등에 이용되는 플립 구조의 반도체 발광 칩(720)이 통상 1mm 이하의 크기를 가지므로, 전극(721,722) 각각은 500㎛ 이하의 크기를 가진다 하겠다. 또한 도전부(771,772)를 홀(761,762)에 투입하는 기술에 의해서도 제약을 받는다. 여러 사정을 고려할 때, 홀(761,762)은 30~300㎛의 최대폭을 가진다 하겠다. 홀(761,762)이 원형인 경우에, 전극(721,722)이 500㎛ 이하의 크기를 가지므로, 도전부(771,772)는 250㎛ 이하 직경을 가지겠지만, 도전부(771,772)가 직사각형의 형상을 가질 수 있음을 염두에 두어야 한다. 기본적으로 홀(761,762)의 폭은 홀(761,762)이 복수 개로 놓이는 방향의 전극(721,722)의 폭에 대해 1/2 이하로 설계된다 할 것이다. 미설명 부호 723은 성장 기판(예: 사파이어 기판)이며, 전극(721,722)의 반대 측에 구비되고, 레이저 리프트-오프 등의 공정으로 제거될 수 있다. 712는 경사면 내지 반사벽이며 생략될 수 있다. 731은 언더필(underfill)이며 필요에 따라 구비될 수 있다. 언더필(731)을 형성하는 경우에, 복수의 도전부(771,772)로 나뉘어 있으므로 언더필(731) 물질이 플립 구조의 반도체 발광 칩(720)과 바닥부(711) 사이에 침투하는 것이 용이한 이점도 가진다. 바닥부(711)에서 리드 프레임 내지 리드 전극(751,752)까지의 두께, 즉 홀(761,762)의 깊이는 30~150㎛ 정도일 수 있으며, 얇게 형성되는 경우에 바닥부(711)가 반도체 발광 칩(720)으로부터 생성되는 빛을 충분히 반사하지 못하고, 이를 투과한 빛이 리드 프레임 내지 리드 전극(751,752)에 의해 흡수될 수 있으므로, 리드 프레임 내지 리드 전극(751,752)은 반사성 금속(예: Ag, Al)으로 도금되는 것이 바람직하다.7(a) and 7(b) are views showing an example of a semiconductor light emitting device to which a flip chip according to the present disclosure is applied, wherein the semiconductor light emitting device is a mold 710, a semiconductor light emitting chip 720 having a flip structure, And an encapsulant 730 and lead frames to lead electrodes 751 and 752. The flip-structured semiconductor light emitting chip 720 includes electrodes 721 and 722, and a bottom 711 of the mold 710 corresponds to a plurality of holes 761 and electrodes 722 corresponding to the electrodes 721. A plurality of holes 762 are formed. Conductive portions 771 and 772 are provided in each hole 761 and each hole 762 to electrically connect the electrodes 721 and 722 to the lead frames to lead electrodes 751 and 752. By providing a plurality of conductive parts 771 and a plurality of conductive parts 772 on each of the electrodes 721 and 722, unlike the semiconductor light emitting device to which the flip chip shown in FIGS. 5 and 6 is applied, the mold 710 and the lead frame to It becomes possible to flexibly cope with mechanical stress generated due to the difference in thermal expansion of the lead electrodes 751 and 752. That is, mechanical stress generated due to a difference in thermal expansion between the mold 710 and the lead frames to the lead electrodes 751 and 752 using a plurality of conductive parts divided into small masses instead of a single bulky solder 371 and 372 It becomes possible to flexibly respond to stress). Furthermore, even when some of the conductive parts are separated from the corresponding electrodes, it becomes possible to maintain the electrical connection by the remaining conductive parts. FIG. 7(a) shows a cross-sectional view along the xx' direction of FIG. 7(b), and FIG. 8 shows a cross-sectional view along the yy' direction of FIG. 7(b), 4 for one electrode 721 Two conductive parts 771 are formed. 8(a) to 8(d) shows a state in which an electrical junction is separated from a state in which a conductive part and an electrode are stably bonded. Even when a part (FIG. 8(c) and FIG. 8(d)) is separated, a part (FIG. 8(a) and FIG. 8(b)) may be joined to supply electricity from the conductive portion to the electrode. The plurality of conductive parts 771 and 772 is sufficient to be 2 or more, but the larger the number, the more the above-described functions can be faithfully performed, and the mold technology for forming the mold 710 and the size of the electrodes 721 and 722 are limited. Currently, it is not easy to form holes 761 and 762 below 200 µm when using a mold. On the other hand, when using laser drilling (Laser Drilling), it is possible to form the holes (761,762) less than 200㎛. In addition, since the flip-structured semiconductor light emitting chip 720 used in displays and the like currently has a size of 1 mm or less, it is assumed that each of the electrodes 721 and 722 has a size of 500 µm or less. In addition, it is also limited by the technique of putting the conductive parts 771 and 772 into the holes 761 and 762. Considering various circumstances, the holes 761 and 762 have a maximum width of 30 to 300 μm. When the holes 761 and 762 are circular, since the electrodes 721 and 722 have a size of 500 μm or less, the conductive parts 771 and 772 will have a diameter of 250 μm or less, but the conductive parts 771 and 772 may have a rectangular shape. It should be kept in mind. Basically, the width of the holes 761 and 762 will be designed to be 1/2 or less with respect to the width of the electrodes 721 and 722 in the direction in which the holes 761 and 762 are placed in plural. Reference numeral 723 is a growth substrate (eg, a sapphire substrate), is provided on the opposite side of the electrodes 721 and 722, and can be removed by a process such as laser lift-off. 712 is an inclined surface to a reflective wall and may be omitted. 731 is an underfill and may be provided as needed. In the case of forming the underfill 731, since the underfill 731 material is divided into a plurality of conductive parts 771 and 772, it is also easy to penetrate the flip-structured semiconductor light emitting chip 720 and the bottom 711. . The thickness from the bottom portion 711 to the lead frames to the lead electrodes 751 and 752, that is, the depth of the holes 761 and 762 may be about 30 to 150 μm, and when formed thinly, the bottom portion 711 is a semiconductor light emitting chip 720 ) Does not sufficiently reflect the light generated, and since the light transmitted through it may be absorbed by the lead frames or the lead electrodes 751 and 752, the lead frames or the lead electrodes 751 and 752 are made of a reflective metal (eg, Ag, Al). It is preferably plated.
도전부(771,772)는 도전성 페이스트, 도금층 등 제약없이 형성될 수 있지만, 바람직하게는 도전부(771,772)의 적어도 일부가 주석(Sn)계 혼합물인 SAC(Sn-Ag-Cu; 예: SAC305, SAC405), 인듐(In)계 혼합물인 In-Pd 같은 솔더로 이루어질 수 있다.The conductive portions 771 and 772 may be formed without limitation, such as a conductive paste or a plating layer, but preferably SAC (Sn-Ag-Cu) in which at least a part of the conductive portions 771 and 772 is a tin (Sn)-based mixture; for example: SAC305, SAC405 ), an indium (In)-based mixture, In-Pd may be made of a solder.
솔더의 형성은 도팅(dotting), 스크린 프린팅(screen printing) 같은 방식을 이용할 수 있다.Solder formation may be performed using a method such as dotting or screen printing.
또한 바람직하게는 도전부(771,772)의 형성에 Pilling-Bedworth ratio(P-B ratio; in corrosion of metals, is the ratio of the volume of the elementary cell of a metal oxide to the volume of the elementary cell of the corresponding metal from which the oxide is created)가 고려된다. P-B ratio가 1보다 작으면, 산화물 코팅이 얇아서 보호막 역할을 하지 못하며, P-B ratio가 2보다 크면, 산화물 코팅이 칩-오프(chip-off)되어 보호막 역할을 하지 못한다. P-B ratio가 1보다 크고 2보다 작은 경우에는 산화물 코팅이 패시베이션 및 추가적인 산화에 대한 강력한 보호막 기능을 한다. 이러한 물질로, Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, Ti를 예로 들 수 있으며, P-B ratio가 1의 근방 내지 2의 근방에 있는 물질이 사용될 수 있음을 염두에 두어야 한다. 이러한 물질을 주석(Sn)계 또는 인듐(In)계 혼합물과 함께 도전부(771,772)에 추가함으로써, 도전부(771,772)에 산화물 표면 피막이 형성되어 그 물성이 붕괴되는 것을 방지할 수 있게 된다. 예를 들어, 주석(Sn)계 혼합물 SAC305에 소량의 Cr을 추가(Cr0 .1-Cu0 .5-Ag3.0-Sn)함으로써, Cr2O3를 형성하여 재용융 온도를 250℃에서 270℃로 상승시켜 이러한 역할을 할 수 있다. 한편 SAC의 융점은 주석(Sn)을 제외한 은(Ag), 구리(Cu)의 함량과 별도의 첨가 설계된 물질 종류에 의존하는데, 특히 P-B ratio가 1보다 크고 2보다 작은 별도의 첨가 설계된 물질과 그 함량에 의존하게 되며, 따라서 반도체 발광소자의 설계 조건 내지 사용 환경이 다소 높은 융점을 요구하는 경우에, 이를 감안하여 솔더의 물질을 선정하는 것이 가능하다.Also preferably, in forming the conductive portion 771,772, the Pilling-Bedworth ratio (PB ratio; in corrosion of metals, is the ratio of the volume of the elementary cell of a metal oxide to the volume of the elementary cell of the corresponding metal from which the oxide is created). If the PB ratio is less than 1, the oxide coating is thin and thus does not serve as a protective film. If the PB ratio is greater than 2, the oxide coating is chip-off and does not function as a protective film. When the PB ratio is greater than 1 and less than 2, the oxide coating serves as a strong protective film against passivation and additional oxidation. Examples of such materials include Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, Ti, and PB ratios in the vicinity of 1 to 2 It should be borne in mind that this can be used. By adding this material to the conductive portions 771 and 772 together with the tin (Sn)-based or indium (In)-based mixture, an oxide surface coating is formed on the conductive portions 771 and 772, thereby preventing the physical properties from collapsing. For example, adding a small amount of Cr to the tin (Sn) based mixture SAC305 (Cr 0 .1 -Cu 0 .5 -Ag 3.0 -Sn) 270 at 250 ℃ the reflow temperature to form a Cr 2 O 3 by You can do this by raising it to °C. On the other hand, the melting point of SAC depends on the content of silver (Ag) and copper (Cu) excluding tin (Sn) and the type of additionally designed material, in particular, the additionally designed material with a PB ratio greater than 1 and less than 2. Depending on the content, therefore, when the design conditions of the semiconductor light emitting device or the use environment require a somewhat higher melting point, it is possible to select a solder material in consideration of this.
필요에 따라, 먼저 Cu 또는 Sn 등으로 도전부(771,772)를 일부 형성(예: 도금)한 다음, SAC로 도전부(771,772)를 형성하는 것도 가능하다. Cu 또는 Sn과 같이, 솔더에 비해 상대적으로 취성(brittelness)이 덜하고, 인성(toughness; 질긴 성질)이 좋은 물질을 마이크로 스케일로 복수 개로 형성된 홀(761,762)에 투입함으로써, 도전부(771,772)의 유연성을 더 향상시킬 수 있게 된다.If necessary, it is also possible to first form (eg, plate) the conductive parts 771,772 with Cu or Sn, and then form the conductive parts 771,772 with SAC. By inserting a material having less brittleness and toughness, such as Cu or Sn, and having good toughness into a plurality of micro-scale holes 761 and 762, the conductive parts 771 and 772 The flexibility can be further improved.
레이저 드릴링을 이용하는 경우에, 홀(761,762)의 표면을 거칠게 할 수 있으며, 형성된 도전부(771,772)의 열팽창에도 불구하고 안정적으로 홀(761,762) 내에 유지될 수 있게 된다. 레이저 드릴링을 이용하는 경우에, 몰드(710)에 LDS 첨가제(additive(s))가 첨가될 수 있으며, 예를 들어, 팔라듐(Pd)함유 중금속 착물과 금속산화물(metal oxide), 금속산화물-코팅된 충전제, 구리 크롬 산화물 스피넬(CuO·Cr2O3 spinel), 구리(Cu) 함유 염, 구리 아이드록시 포스페이트, 구리 포스페이트, 제일구리 티오시아네이트, 스피넬계 금속산화물, 구리 크롬 산화물(CuO·Cr2O3), 유기 금속 착물, 안티몬(Sb) 도핑된 주석(Sn) 산화물, 구리 함유 금속산화물, 아연(Zn) 함유 금속산화물, 주석(Sn) 함유 금속산화물, 마그네슘(Mg) 함유 금속산화물, 알루미늄(Al) 함유 금속산화물, 금(Au) 함유 금속산화물, 은(Ag) 함유 금속산화물, 니켈(Ni) 함유 금속산화물, 크롬(Cr) 함유 금속산화물, 철(Fe) 함유 금속산화물, 바나듐(V) 함유 금속산화물, 코발트(Co) 함유 금속산화물, 망간(Mn) 함유 금속산화물 등이 첨가될 수 있으며, 방열 특성이 좋은 첨가제로 알루미늄 질화물(AlN), 알루미늄 탄화물(AlC), 알루미늄 산화물(Al2O3), 알루미늄 산화질화물(AlON), 붕소 질화물(BN), 마그네슘실리콘 질화물(MgSiN2), 실리콘 질화물(Si3N4), 실리콘 탄화물(SiC), 그라파이트(graphite), 그래핀(graphene), 및 탄소 섬유(carbon fiber), 아연(Zn) 산화물, 칼슘(Ca) 산화물, 마그네슘(Mg) 산화물 등이 첨가될 수 있고, 광반사 기능이 우수한 첨가제로 TiO2 , ZnO, BaS, CaCO3 중의 적어도 하나가 첨가될 수 있다.In the case of using laser drilling, the surface of the holes 761 and 762 can be roughened and can be stably maintained in the holes 761 and 762 despite thermal expansion of the formed conductive parts 771 and 772. In the case of using laser drilling, an LDS additive (additive(s)) may be added to the mold 710, for example, a heavy metal complex containing palladium (Pd) and a metal oxide, metal oxide-coated Filler, copper chromium oxide spinel (CuO·Cr 2 O 3 spinel), salt containing copper (Cu), copper hydroxy phosphate, copper phosphate, first copper thiocyanate, spinel metal oxide, copper chromium oxide (CuO·Cr 2 O 3 ), organic metal complex, antimony (Sb) doped tin (Sn) oxide, copper-containing metal oxide, zinc (Zn)-containing metal oxide, tin (Sn)-containing metal oxide, magnesium (Mg)-containing metal oxide, aluminum (Al) containing metal oxide, gold (Au) containing metal oxide, silver (Ag) containing metal oxide, nickel (Ni) containing metal oxide, chromium (Cr) containing metal oxide, iron (Fe) containing metal oxide, vanadium (V) ) Containing metal oxides, cobalt (Co)-containing metal oxides, manganese (Mn)-containing metal oxides, etc. can be added, and aluminum nitride (AlN), aluminum carbide (AlC), and aluminum oxide (Al 2 ) are additives with good heat dissipation properties. O 3 ), aluminum oxynitride (AlON), boron nitride (BN), magnesium silicon nitride (MgSiN 2 ), silicon nitride (Si 3 N 4 ), silicon carbide (SiC), graphite, graphene , And carbon fiber (carbon fiber), zinc (Zn) oxide, calcium (Ca) oxide, magnesium (Mg) oxide, etc. may be added, and as an additive with excellent light reflection function in TiO 2 , ZnO, BaS, CaCO 3 At least one may be added.
도 9는 본 개시에 따라 도전부를 형성하는 공정의 일 예를 나타내는 도면으로서, 도 9(a)에 도시된 바와 같이, 먼저 페이스트 형태의 솔더(773: 예: Cr0 .1-Cu0.5-Ag3.0-Sn)를 홀(761 또는 762)에 투입한다. 그리고 열처리(reflow)를 행하여, 도 9(b)에 도시된 것과 같이, 산화물(Cr2O3) 표면 피막(774)을 형성해서 더 고온에서 안정적인 조인팅 역할을 가능케 하는 한편, 형성된 도전부가 붕괴되지 않고 유지될 수 있게 한다. 이 열처리는 전극(721 또는 722)을 위치시킨 이후에 이루어질 수도 있다. 바람직하게는 1차로 열처리를 행한 후, 2차로 솔더(775; 예: SAC)를 도팅, 스크린 프린팅 등과 같은 방식으로 투입하고, 전극(721 또는 722)을 위치시킨 다음, 2차로 열처리(reflow) 행하여, 전극(721 또는 722)과 도전부의 접합을 완료한다. 필요에 따라, 솔더(773)의 투입에 앞서, 도금과 같은 방식으로 솔더(773)보다 취성이 덜한 물질(776; 예: Cu, Sn과 같은 금속)을 홀(761 또는 762)에 형성한다. 2차 솔더(775)는 1차 솔더(773)와 동일한 물질로 이루어질 수 있지만, 1차 솔더(773)에 의해 산화물 표면 피막(774)이 형성되어, 도전부가 보호되고 있으며, 전극(721 또는 722)과 접합에 맞춘 형태의 솔더 물질을 이용할 수 있다.9 is a diagram showing a step of forming a conductive in accordance with the present disclosure, the first form of the solder paste as shown in Figure 9 (a) (773: Example: Cr 0 .1 -Cu 0.5 -Ag 3.0 -Sn) is injected into the hole 761 or 762. And by performing a heat treatment (reflow), as shown in Figure 9 (b), to form an oxide (Cr 2 O 3 ) surface film 774 to enable a stable joining role at a higher temperature, the formed conductive portion collapses To be maintained. This heat treatment may be performed after the electrodes 721 or 722 are positioned. Preferably, after the first heat treatment, the solder (775; for example, SAC) is secondarily input in the same manner as dotting, screen printing, and the like, and then the electrode 721 or 722 is positioned and then secondarily subjected to reflow. , The bonding of the electrode 721 or 722 and the conductive portion is completed. If necessary, prior to the introduction of the solder 773, a material 776 (such as a metal such as Cu or Sn) less brittle than the solder 773 is formed in the hole 761 or 762 in the same manner as plating. The secondary solder 775 may be made of the same material as the primary solder 773, but the oxide surface coating 774 is formed by the primary solder 773 to protect the conductive portion, and the electrode 721 or 722 ) And a solder material in a form suited to the joint can be used.
도 10은 본 개시에 따라 복수의 도전부를 설계하는 과정의 일 예를 나타내는 도면으로서, 플립 구조의 반도체 발광 칩(720)의 주어진 변의 길이(L칩)에 대해 최대한 많은 갯수(nmax)의 도전부를 설계하는 방법을 설명한다. 전극(721 또는 722)의 장방향 길이를 L전극, 전극(722)과 플립 구조의 반도체 발광 칩(720) 사이의 최소거리(전극(722)에 의한 칩(720)의 short를 방지하기 위해 필요한 거리, 예: 100㎛)를 a, 도전부(772)의 최소직경(이는 몰드(710)의 제조과정에서 홀(762)을 형성할 때, 현재 제조기술의 한계에 의해 규정된다. 예: 직경이 100㎛인 원형)을 D, 전극(722)과 도전부(772)의 최소거리(도전부(772)의 short를 방지하기 위해 필요한 거리, 예: 50㎛)를 b, 도전부(772)와 도전부(772) 사이의 최소 거리를 c라 할 때, 다음의 관계가 주어진다.10 is a view showing an example of a process of designing a plurality of conductive parts according to the present disclosure, the maximum number of challenges (n max ) for a given side length (L chip ) of the flip-emitting semiconductor light emitting chip 720 Explains how to design wealth. The longest length of the electrode 721 or 722 is the L electrode , the minimum distance between the electrode 722 and the flip-emitting semiconductor light emitting chip 720 (necessary to prevent shorting of the chip 720 by the electrode 722) Distance, eg 100 μm) a, the minimum diameter of the conductive portion 772 (which is defined by the limitations of current manufacturing techniques when forming the hole 762 in the process of manufacturing the mold 710. Example: Diameter D of this 100 µm circular shape, D of the minimum distance between the electrode 722 and the conductive portion 772 (the distance required to prevent short of the conductive portion 772, for example, 50 µm) b, the conductive portion 772 When c is the minimum distance between and the conductive portion 772, the following relationship is given.
L전극 ≤ L칩 - 2a, L전극 ≥ 2b + nmax*D + (nmax-1)*cL electrode ≤ L chip -2a, L electrode ≥ 2b + n max *D + (n max -1)*c
따라서, nmax는 (L칩 - 2a - 2b + c)/(D+c) = K 보다 작으면서, 가장 근접한 정수가 된다. 예를 들어, L칩 = 1000㎛, a = 100㎛, b = 50㎛, c = 50㎛ 일 때, K는 5가 되어, nmax가 5가 되고, 따라서 5개의 도전부(772)를 구비함으로써, 본 개시의 효과를 최대화할 수 있게 된다. L칩 = 1100㎛ 인 경우에, K가 5.667이 되어, nmax는 5가 되며, L칩 = 1150㎛ 인 경우에, K가 6이 되어, nmax는 6이 된다. 정리하면, 플립 구조의 반도체 발광 칩(720)의 길이(L칩)에 대하여 도전부(772)가 최대의 갯수(nmax)를 갖도록 할 수 있으며, nmax는 (L칩 - 2a - 2b + c)/(D+c) = K 보다 작으면서, 가자 근접한 정수가 된다. 이는 도전부(771)의 경우에도 동일하게 적용된다. 바람직하게는 전극(772)의 길이(L전극)를 전극(772)의 전극(772)의 두 변 중에서 긴 것으로 택하고, 플립 구조의 반도체 발광 칩(720)의 길이(L칩) 또한 칩(720)의 두 변 중에서 긴 것으로 택함으로써 즉, 전극(772)의 장방향 변이 칩(720)의 장방향 변을 따라 연장되도록 배치함으로써, nmax를 최대화할 수 있다.Therefore, n max is less than (L chip -2a-2b + c)/(D+c) = K, and becomes the nearest integer. For example, when L chip = 1000 μm, a = 100 μm, b = 50 μm, and c = 50 μm, K becomes 5, n max becomes 5, and thus 5 conductive parts 772 are provided. By doing so, it is possible to maximize the effect of the present disclosure. When L chip = 1100 μm, K becomes 5.667, n max becomes 5, and when L chip = 1150 μm, K becomes 6, and n max becomes 6. In summary, the conductive portion 772 may have a maximum number (n max ) with respect to the length (L chip ) of the flipped semiconductor light emitting chip 720, where n max is (L chip -2a-2b + c)/(D+c) = less than K, let's go to the nearest integer. This also applies to the conductive portion 771. Preferably, the length (L electrode ) of the electrode 772 is selected from the two sides of the electrode 772 of the electrode 772, and the length (L chip ) of the semiconductor light emitting chip 720 of the flip structure is also a chip ( By selecting one of the two sides of 720), that is, by arranging the long side of the electrode 772 to extend along the long side of the chip 720, n max can be maximized.
도 11은 본 개시에 따라 복수의 도전부를 설계하는 과정의 또 다른 예를 나타내는 도면으로서, 전극(721,722) 각각에 도전부(771,772)가 복수의 열로 구비되어 있다. 이 경우에, 하나의 전극(772)에 대한 도전부(772)의 전체 갯수는 m*nmax로 주어진다. m은 열의 갯수이다.11 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure, and each of the electrodes 721 and 722 includes conductive parts 771 and 772 in a plurality of rows. In this case, the total number of conductive parts 772 for one electrode 772 is given by m*n max . m is the number of rows.
도 12은 본 개시에 따라 복수의 도전부를 설계하는 과정의 또 다른 예를 나타내는 도면으로서, 전극(721,722) 각각이 2이상의 서브전극(721a,721b) 및 서브전극(722a,722b)로 나뉘어 있으며, 서브전극(721a,721b, 722a,722b) 각각이 하나의 이상의 도전부(771,772)를 구비함으로써, 전극(721,722)이 각각이 복수의 도전부(771,772)를 구비하게 된다.12 is a view showing another example of a process of designing a plurality of conductive parts according to the present disclosure, each of the electrodes 721 and 722 is divided into two or more sub-electrodes 721a and 721b and sub-electrodes 722a and 722b, Each of the sub-electrodes 721a, 721b, 722a, and 722b includes one or more conductive portions 771 and 772, so that the electrodes 721 and 722 each have a plurality of conductive portions 771 and 772.
이하 본 개시의 다양한 실시 형태에 대하여 설명한다.Hereinafter, various embodiments of the present disclosure will be described.
(1) 플립 칩을 적용한 반도체 발광소자에 있어서, 전극을 구비하는 플립 구조의 반도체 발광 칩; 전극과 면하도록 플립 구조의 반도체 발광 칩의 아래에 놓이는 바닥부를 가지고, 바닥부에 전극에 대응하는 복수의 홀이 형성되어 있는 몰드; 몰드와 일체로 함께 형성되며, 복수의 홀을 통해 노출되는 리드 프레임; 그리고, 전극과 리드 프레임의 전기적 연통을 위해 복수의 홀 각각에 구비되며, 적어도 일부가 솔더로 이루어진 도전부;를 포함하는 것을 특징으로 하는 플립 칩을 적용한 반도체 발광소자.(1) A semiconductor light emitting device to which a flip chip is applied, the semiconductor light emitting chip having a flip structure including an electrode; A mold having a bottom portion placed under the flip-shaped semiconductor light emitting chip facing the electrode, and having a plurality of holes corresponding to the electrodes formed on the bottom portion; A lead frame formed integrally with the mold and exposed through a plurality of holes; And, it is provided in each of the plurality of holes for electrical communication between the electrode and the lead frame, at least a portion of a conductive portion made of solder; characterized in that it comprises a flip chip semiconductor light emitting device comprising a.
(2) 바닥부는 제1 거칠기를 가지며, 홀은 제1 거칠기와 다른 제2 거칠기를 가지는 플립 칩을 적용한 반도체 발광소자.(2) The bottom portion has a first roughness, and the hole is a semiconductor light emitting device to which a flip chip having a second roughness different from the first roughness is applied.
(3) 솔더에 P-B ratio가 1보다 크고 2보다 작은 금속이 추가되는 플립 칩을 적용한 반도체 발광소자.(3) A semiconductor light emitting device using a flip chip in which a metal having a P-B ratio greater than 1 and less than 2 is added to solder.
(4) 솔더는 Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, Ti 중의 적어도 하나가 추가되는 플립 칩을 적용한 반도체 발광소자.(4) The solder is a semiconductor light emitting device using a flip chip to which at least one of Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, and Ti is added.
(5) 솔더는 주석(Sn)계 혼합물인 SAC(Sn-Ag-Cu)를 함유하는 플립 칩을 적용한 반도체 발광소자.(5) The solder is a semiconductor light emitting device using a flip chip containing SAC (Sn-Ag-Cu), a tin (Sn)-based mixture.
(6) 솔더는 인듐(In)계 혼합물인 In-Pd를 함유하는 플립 칩을 적용한 반도체 발광소자.(6) The solder is a semiconductor light emitting device using a flip chip containing In-Pd, which is an indium-based mixture.
(7) 솔더는 Cr을 추가적으로 포함하는 플립 칩을 적용한 반도체 발광소자.(7) The solder is a semiconductor light emitting device to which a flip chip including Cr is additionally applied.
(8) 도전부는 솔더와 리드 프레임 사이에 도금층을 구비하는 플립 칩을 적용한 반도체 발광소자.(8) The conductive portion is a semiconductor light emitting device using a flip chip having a plating layer between solder and a lead frame.
(9) 도전부는 P-B ratio가 1보다 크고 2보다 작은 금속이 추가된 제1 솔더와, 제1 솔더의 상부에서 전극과 접합하는 제2 솔더를 포함하는 것을 특징으로 하는 플립 칩을 적용한 반도체 발광소자.(9) A semiconductor light emitting device employing a flip chip, wherein the conductive part includes a first solder having a metal having a PB ratio greater than 1 and smaller than 2, and a second solder bonding to an electrode on top of the first solder. .
(10) 몰드는 LDS 첨가제를 포함하는 것을 특징으로 하는 플립 칩을 적용한 반도체 발광소자.(10) The mold is a semiconductor light emitting device using a flip chip, characterized in that it contains an LDS additive.
(11) 솔더는 산화물 표면 피막을 구비하는 플립 칩을 적용한 반도체 발광소자.(11) A solder is a semiconductor light emitting device to which a flip chip having an oxide surface coating is applied.
(12) 도전부는 홀 내에서 솔더의 아래에 솔더보다 취성이 덜한 도전성 물질을 구비하는 플립 칩을 적용한 반도체 발광소자.(12) The conductive portion is a semiconductor light-emitting device in which a flip chip including a conductive material having less brittleness than solder is applied to the bottom of the solder in the hole.
(13) 도전부는 1차 솔더와 1차 솔더의 위에 위치하는 2차 솔더를 구비하는 플립 칩을 적용한 반도체 발광소자.(13) The conductive portion is a semiconductor light emitting device to which a flip chip including a primary solder and a secondary solder positioned on the primary solder is applied.
(14) 1차 솔더는 1차 솔더와 2차 솔더 사이에 산화물 표면 피막을 구비하는 플립 칩을 적용한 반도체 발광소자.(14) The primary solder is a semiconductor light emitting device using a flip chip having an oxide surface coating between the primary solder and the secondary solder.
(15) 복수의 홀에 구비되는 도전부의 총수가 nmax(nmax는 (L칩 - 2a - 2b + c)/(D+c) = K 보다 작으면서, 가장 근접한 정수)로 주어지는 플립 칩을 적용한 반도체 발광소자. 여기서, L칩는 플립 구조의 반도체 발광 칩의 변의 길이, a는 전극과 플립 구조의 반도체 발광 칩 사이의 최소거리, D는 도전부의 최소직경, b는 전극과 도전부의 최소거리, c는 도전부와 도전부 사이의 최소 거리이다.)(15) The total number of conductive parts provided in the plurality of holes is n max (n max is (L chip -2a-2b + c) / (D + c) = less than K, the nearest integer) flip chip given by Applied semiconductor light emitting device. Here, L chip is the length of the side of the flip-structure semiconductor light-emitting chip, a is the minimum distance between the electrode and the flip-structure semiconductor light-emitting chip, D is the minimum diameter of the conductive portion, b is the minimum distance of the electrode and the conductive portion, c is the conductive portion And the conductive part.)
(16) 길이(L칩)는 플립 구조의 반도체 발광 칩의 장변의 길이이고, 전극은 플립 구조의 반도체 발광 칩의 장변을 따라 뻗어 있는 플립 칩을 적용한 반도체 발광소자.(16) The length (L chip ) is the length of the long side of the flip-structured semiconductor light emitting chip, and the electrode is a semiconductor light emitting device to which a flip chip extending along the long side of the flipped semiconductor light emitting chip is applied.
(17) 복수의 홀이 복수의 열로 배치되어 있는 플립 칩을 적용한 반도체 발광소자.(17) A semiconductor light emitting device using a flip chip in which a plurality of holes are arranged in a plurality of rows.
(18) 전극이 복수의 서브전극으로 이루어지는 반도체 발광소자.(18) A semiconductor light-emitting device in which an electrode is formed of a plurality of sub-electrodes.
본 개시에 따른 하나의 플립 칩을 적용한 반도체 발광소자에 의하면, 리드 프레임과 플립 구조의 반도체 발광 칩의 전기적 연결을 안정적으로 확보할 수 있게 된다. 특히, 열팽창계수가 큰 PCT가 백색 몰드로 이용되고, 플립 구조의 반도체 발광 칩이 이용됨에도 불구하고, 리드 프레임과 전극 간의 전기적 연결을 안정적으로 확보할 수 있게 된다.According to the semiconductor light emitting device to which one flip chip according to the present disclosure is applied, it is possible to stably secure the electrical connection between the lead frame and the flipped semiconductor light emitting chip. In particular, although a PCT having a large coefficient of thermal expansion is used as a white mold and a semiconductor light emitting chip having a flip structure is used, it is possible to stably secure the electrical connection between the lead frame and the electrode.

Claims (15)

  1. 플립 칩을 적용한 반도체 발광소자에 있어서,In the semiconductor light emitting device to which the flip chip is applied,
    전극을 구비하는 플립 구조의 반도체 발광 칩;A semiconductor light emitting chip having a flip structure including an electrode;
    전극과 면하도록 플립 구조의 반도체 발광 칩의 아래에 놓이는 바닥부를 가지고, 바닥부에 전극에 대응하는 복수의 홀이 형성되어 있는 몰드;A mold having a bottom portion placed under the flip-shaped semiconductor light emitting chip facing the electrode, and having a plurality of holes corresponding to the electrodes formed on the bottom portion;
    몰드와 일체로 함께 형성되며, 복수의 홀을 통해 노출되는 리드 프레임; 그리고,A lead frame formed integrally with the mold and exposed through a plurality of holes; And,
    전극과 리드 프레임의 전기적 연통을 위해 복수의 홀 각각에 구비되며, 적어도 일부가 솔더로 이루어진 도전부;를 포함하는 플립 칩을 적용한 반도체 발광소자.A semiconductor light emitting device to which a flip chip is applied, which is provided in each of a plurality of holes for electrical communication between the electrode and the lead frame, and includes at least a portion of a conductive part made of solder.
  2. 청구항 1에 있어서,The method according to claim 1,
    바닥부는 제1 거칠기를 가지며, 홀은 제1 거칠기와 다른 제2 거칠기를 가지는 플립 칩을 적용한 반도체 발광소자.The bottom portion has a first roughness, and the hole is a semiconductor light emitting device to which a flip chip having a second roughness different from the first roughness is applied.
  3. 청구항 1에 있어서,The method according to claim 1,
    솔더에 P-B ratio가 1보다 크고 2보다 작은 금속이 추가되는 플립 칩을 적용한 반도체 발광소자.A semiconductor light emitting device using a flip chip in which a metal having a P-B ratio greater than 1 and less than 2 is added to solder.
  4. 청구항 1에 있어서,The method according to claim 1,
    솔더는 Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, Ti 중의 적어도 하나가 추가되는 플립 칩을 적용한 반도체 발광소자.The solder is a semiconductor light emitting device using a flip chip to which at least one of Ce, Al, Pb, Ni, Be, Pd, Cu, Fe, Mn, Co, Cr, Cd, Ag, and Ti is added.
  5. 청구항 1에 있어서,The method according to claim 1,
    솔더는 SAC(Sn-Ag-Cu) 또는 In-Pd을 함유하는 플립 칩을 적용한 반도체 발광소자. The solder is a semiconductor light emitting device using a flip chip containing SAC (Sn-Ag-Cu) or In-Pd.
  6. 청구항 3 또는 청구항 4에 있어서,The method according to claim 3 or 4,
    솔더는 SAC(Sn-Ag-Cu) 또는 In-Pd을 함유하는 것을 플립 칩을 적용한 반도체 발광소자. The solder contains SAC (Sn-Ag-Cu) or In-Pd, a semiconductor light emitting device using a flip chip.
  7. 청구항 6에 있어서,The method according to claim 6,
    솔더는 Cr을 추가적으로 포함하는 플립 칩을 적용한 반도체 발광소자.The solder is a semiconductor light emitting device using a flip chip additionally containing Cr.
  8. 청구항 1에 있어서,The method according to claim 1,
    도전부는 솔더와 리드 프레임 사이에 도금층을 구비하는 플립 칩을 적용한 반도체 발광소자.The conductive portion is a semiconductor light emitting device using a flip chip having a plating layer between solder and a lead frame.
  9. 청구항 1에 있어서,The method according to claim 1,
    도전부는 P-B ratio가 1보다 크고 2보다 작은 금속이 추가된 제1 솔더와, 제1 솔더의 상부에서 전극과 접합하는 제2 솔더를 포함하는 플립 칩을 적용한 반도체 발광소자.The conductive portion is a semiconductor light emitting device to which a flip chip including a first solder having a P-B ratio greater than 1 and less than 2 added, and a second solder bonding to an electrode on top of the first solder.
  10. 청구항 1에 있어서,The method according to claim 1,
    몰드는 LDS 첨가제를 포함하는 플립 칩을 적용한 반도체 발광소자.The mold is a semiconductor light emitting device to which a flip chip including an LDS additive is applied.
  11. 청구항 3에 있어서,The method according to claim 3,
    솔더는 산화물 표면 피막을 구비하는 플립 칩을 적용한 반도체 발광소자.The solder is a semiconductor light emitting device using a flip chip having an oxide surface coating.
  12. 청구항 1에 있어서,The method according to claim 1,
    도전부는 홀 내에서 솔더의 아래에 솔더보다 취성이 덜한 도전성 물질을 구비하는 플립 칩을 적용한 반도체 발광소자.The conductive portion is a semiconductor light emitting device to which a flip chip including a conductive material having less brittleness than solder is applied to the bottom of the solder in the hole.
  13. 청구항 13에 있어서,The method according to claim 13,
    도전부는 1차 솔더와 1차 솔더의 위에 위치하는 2차 솔더를 구비하는 플립 칩을 적용한 반도체 발광소자.The conductive portion is a semiconductor light emitting device to which a flip chip including a primary solder and a secondary solder positioned on the primary solder is applied.
  14. 청구항 13에 있어서,The method according to claim 13,
    1차 솔더는 1차 솔더와 2차 솔더 사이에 산화물 표면 피막을 구비하는 플립 칩을 적용한 반도체 발광소자.The primary solder is a semiconductor light emitting device using a flip chip having an oxide surface coating between the primary solder and the secondary solder.
  15. 청구항 14에 있어서,The method according to claim 14,
    도전부는 홀 내에서 1차 솔더의 아래에 1차 솔더보다 취성이 덜한 도전성 물질을 구비하는 플립 칩을 적용한 반도체 발광소자.The conductive portion is a semiconductor light emitting device to which a flip chip including a conductive material having less brittleness than the primary solder is applied under the primary solder in the hole.
PCT/KR2020/001132 2019-01-22 2020-01-22 Semiconductor light-emitting device WO2020153770A1 (en)

Applications Claiming Priority (6)

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KR1020190008109A KR102275360B1 (en) 2019-01-22 2019-01-22 Light emitting device
KR10-2019-0008109 2019-01-22
KR1020190044092A KR20200121488A (en) 2019-04-16 2019-04-16 Light emitting device
KR10-2019-0044092 2019-04-16
KR10-2019-0046011 2019-04-19
KR1020190046011A KR20200122803A (en) 2019-04-19 2019-04-19 Light emitting device

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Publication number Priority date Publication date Assignee Title
KR20100105486A (en) * 2009-03-18 2010-09-29 에버라이트 일렉트로닉스 컴패니 리미티드 Photoelectric transmitting or receiving device and manufacturing method thereof
KR20140023512A (en) * 2012-08-16 2014-02-27 엘지이노텍 주식회사 Nitride light emitting device
KR20150078295A (en) * 2013-12-30 2015-07-08 일진엘이디(주) Side emitting type nitride semiconductor light emitting device
KR20170108633A (en) * 2016-03-18 2017-09-27 앰코 테크놀로지 코리아 주식회사 Semiconductor Device Module And Method For Fabricating The Same
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Publication number Priority date Publication date Assignee Title
KR20100105486A (en) * 2009-03-18 2010-09-29 에버라이트 일렉트로닉스 컴패니 리미티드 Photoelectric transmitting or receiving device and manufacturing method thereof
KR20140023512A (en) * 2012-08-16 2014-02-27 엘지이노텍 주식회사 Nitride light emitting device
KR20150078295A (en) * 2013-12-30 2015-07-08 일진엘이디(주) Side emitting type nitride semiconductor light emitting device
KR20170108633A (en) * 2016-03-18 2017-09-27 앰코 테크놀로지 코리아 주식회사 Semiconductor Device Module And Method For Fabricating The Same
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