WO2020143501A1 - 显示面板、驱动方法和显示装置 - Google Patents

显示面板、驱动方法和显示装置 Download PDF

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Publication number
WO2020143501A1
WO2020143501A1 PCT/CN2019/130237 CN2019130237W WO2020143501A1 WO 2020143501 A1 WO2020143501 A1 WO 2020143501A1 CN 2019130237 W CN2019130237 W CN 2019130237W WO 2020143501 A1 WO2020143501 A1 WO 2020143501A1
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Prior art keywords
display screen
display
circuit
gate drive
display panel
Prior art date
Application number
PCT/CN2019/130237
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English (en)
French (fr)
Inventor
李泽尧
Original Assignee
惠科股份有限公司
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Publication date
Priority claimed from CN201910018437.0A external-priority patent/CN109767735A/zh
Priority claimed from CN201910018513.8A external-priority patent/CN109637477B/zh
Application filed by 惠科股份有限公司 filed Critical 惠科股份有限公司
Publication of WO2020143501A1 publication Critical patent/WO2020143501A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • the present application relates to the field of display technology, in particular to a display panel, a driving method and a display device.
  • the array substrate row drive (Gate Driver on Array, GOA) technology as a representative of the new technology is to integrate the gate switch circuit on the array substrate to remove the gate drive integrated circuit part, thereby saving materials and reducing Process steps to achieve the goal of reducing product costs.
  • the present application provides a display panel, a driving method, and a display device capable of bidirectional output at the output end of a gate driving circuit.
  • the present application discloses a display panel, which includes a first display screen, a second display screen, and a first gate drive circuit; a corresponding first scan line is provided in the first display screen, and a second display screen is provided in the first display screen Corresponding to the second scan line, the first gate drive circuit is coupled to the first scan line and the second scan line, and the first scan line and the second scan line are not connected.
  • the present application discloses a display panel, which includes a plurality of display screens and a plurality of first gate drive circuits, and the plurality of display screens are arranged in X*Y and formed on the same substrate;
  • a gate drive circuit is provided between two adjacent display screens to drive the two adjacent display screens; wherein, X is the number of display screens in each column in the first direction, Y The number of display screens in each row in the second direction, the first direction and the second direction are perpendicular; X is a positive integer greater than or equal to 1, and Y is a positive integer greater than or equal to 2.
  • the present application also discloses a driving method for a display panel as described above.
  • the display panel includes a first gate drive circuit timing control circuit, including steps:
  • the first gate driving circuit receives the clock signal output by the timing control circuit
  • the first gate drive circuit scans the first scan line and the second scan line simultaneously based on the same set of clock signals.
  • the first gate drive circuit of the present application simultaneously outputs a scan signal to the first scan line of the first display screen and the second scan line of the second display screen ,
  • the first scan line and the second scan line are not connected, which is equivalent to a very long scan line divided into two segments.
  • the first scan line corresponding to the first display and the corresponding one in the second display The farthest distance between the second scan line and the first gate drive circuit or the input end of the gate start signal can be greatly reduced. After the length of the scan line to be scanned is greatly reduced, the distance between the farthest end of the scan line and the gate drive circuit The resistance value of the scan line becomes smaller and the interference becomes less.
  • the attenuation of the corresponding gate start signal will be improved very well, thereby greatly improving the scan waveform at the farthest end of the scan line, so that the scan line can work stably. Improve the problem of excessive load on large-size display panels and the problem of severe deformation of the scanning waveform caused by excessive load.
  • FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present application.
  • FIG. 2 is a schematic diagram of a gate driving sub-circuit coupled to the same clock signal trace according to an embodiment of the present application
  • FIG. 3 is a schematic diagram of a gate driving sub-circuit coupled to different signal traces according to another embodiment of the present application.
  • FIG. 4 is a schematic diagram of a timing control circuit connected to signal traces according to another embodiment of the present application.
  • FIG. 5 is a schematic diagram of multiple gate driving circuits receiving the same clock signal according to another embodiment of the present application.
  • FIG. 6 is a schematic diagram of a glass substrate according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of an M*N display screen according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of five gate drive circuits according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of ten gate driving circuits according to another embodiment of the present application.
  • FIG. 10 is a schematic diagram of a circuit structure in which two sets of gate driving sub-circuits are connected to the same set of clock signal traces according to an embodiment of the present application;
  • FIG. 11 is a schematic diagram of a clock signal waveform according to an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a circuit structure in which two sets of gate driving sub-circuits are connected to two sets of clock signal traces according to an embodiment of the present application;
  • FIG. 13 is a schematic diagram of a clock signal waveform according to an embodiment of the present application.
  • 15 is a schematic diagram of a display device according to another embodiment of the present application.
  • first and second are used only for descriptive purposes and cannot be understood as indicating relative importance, or implicitly indicating the number of technical features indicated.
  • the features defined as “first” and “second” may expressly or implicitly include one or more of the features; “multiple” means two or more.
  • the term “comprising” and any variations thereof are meant to be non-exclusive and one or more other features, integers, steps, operations, circuits, components, and/or combinations thereof may be present or added.
  • connection should be understood in a broad sense, such as fixed connection, detachable connection, or integral connection; may be mechanical connection It can also be an electrical connection; it can be directly connected, indirectly connected through an intermediary, or connected within two components.
  • an embodiment of the present application discloses a display panel 110 including at least: a first display screen 111 provided with a first scan line 120; a second display provided with a second scan line 130 Screen 112; and a first gate driving circuit 113 coupled to the first scan line 120 and the second scan line 130, the first scan line 120 and the second scan line 130 are not connected, or not directly connected.
  • the first gate driving circuit 113 simultaneously outputs scan signals to the first scan line 120 of the first display screen 111 and the second scan line 130 of the second display screen 112.
  • the first scan line 120 and the second scan line 130 themselves are not Connected, which is equivalent to a very long scan line divided into two segments.
  • the first scan line 120 corresponding to the first display 111 and the corresponding second scan line 130 in the second display 112 are away from the first grid
  • the pole drive circuit 113 or the farthest distance from the input end point of the gate start signal can be greatly reduced.
  • the resistance of the scan line between the farthest end of the scan line and the gate drive circuit changes Small and less interference, the attenuation of the corresponding gate start signal will be well improved, thus greatly improving the scanning waveform of the farthest end of the scanning line, so that the scanning line can work stably, and thus improving the load of the large-size display panel Excessively large and severely deformed scan waveform caused by excessive load.
  • the first gate driving circuit 113 includes a first gate driving sub-circuit 1131 and a second gate driving sub-circuit disposed between the first display 111 and the second display 112 1132, the display panel 110 further includes a first group of clock signal traces 141; a first gate driving sub-circuit 1131 is coupled to the first scan line 120 and the first group of clock signal traces 141, and a second gate driving sub-circuit 1132 is coupled The first group of clock signal traces 141 are on the second scan line 130.
  • the first gate driving circuit 113 includes a first gate driving sub-circuit and a second gate driving sub-circuit, and the first gate driving sub-circuit 1131 and the second gate driving sub-circuit 1132 are provided on the first display screen And the second display screen; the first gate drive sub-circuit can control the first scan line 120 of the first display screen 111 to scan, and the second gate drive sub-circuit controls the second display screen 112 to correspond to the second scan line 130 scanning, so that the distance between the farthest end of the first scan line and the second scan line and the first gate drive sub-circuit 1131 or the second gate drive sub-circuit 1132 can be greatly shortened.
  • the load of the scanning line between the first gate driving circuit 113 is greatly reduced, and the scanning waveform at the farthest end of the scanning line can be greatly improved.
  • the first gate driving sub-circuit 1131 and the second gate driving sub-circuit 1132 are both Coupled to the first group of clock signal traces 141, the same clock signal is received, so that the scan lines can work stably, thereby improving the situation that the large-size display panel is overloaded and the scan waveform is deformed seriously due to the overload.
  • the first gate driving circuit may also be provided with only one set of gate driving sub-circuits, one set of gate driving sub-circuits is coupled to the same set of clock signal traces 140, and one set of clock signal traces includes a normal phase clock signal line CLK And an inverted clock signal line CLKB, the scan lines in the display screens on both sides are connected to the set of gate drive sub-circuits at the same time, the set of gate drive sub-circuits can be increased by adding an output port, or the first scan line 120 and The second scan lines 130 are connected to each other. Of course, other applicable methods are also possible. Two sets of gate drive sub-circuits are coupled to the same set of clock signal lines 140, which can save one set of clock signal lines.
  • the scan signal of the display screen can ensure synchronization, the driving effect is good, and the display effect of the display panel 110 is better.
  • the display panel includes a first gate driving circuit 113, the display panel includes a first set of clock signal traces 141 corresponding to the first display screen 111, and the second display The second set of clock signal traces 142 corresponding to the screen 112;
  • the first gate driving circuit 113 includes a first gate driving sub-circuit 1131 disposed between the first display 111 and the second display 112 And a second gate driving sub-circuit 1132, the first gate driving sub-circuit 1131 is respectively coupled to the first scan line 120 and the first group of clock signal traces 141, and the second gate driving sub-circuit is respectively It is coupled to the second scan line and the second group of clock signal traces.
  • the gate driving sub-circuit 1132 may be disposed between the first display screen and the second display screen; when the first display screen and the second display screen are manufactured separately, and then spliced and assembled, the first display screen and the second display screen
  • a black matrix Black Matrix, BM
  • the first group of clock signal traces and the corresponding gate drive sub-circuits may be formed in the peripheral area of the first display screen. Two sets of clock signal traces and corresponding gate drive sub-circuits can be formed in the peripheral area of the second display screen, and then spliced together.
  • Two sets of clock signals can control synchronous or asynchronous output.
  • synchronous output it can display images at the same time; when it is not synchronized output, with proper backlight drive and data drive, it can better control only one of the display screens. , The scope of use is wider, and the choice is stronger.
  • the display panel 110 includes a timing control circuit 150, the first group of clock signal traces 141 and the second group of clock signal traces 142 are coupled to the timing control circuit 150, and the first gate driving sub-circuit in the first gate driving circuit A low-voltage signal trace Vss is shared with the second gate driving sub-circuit.
  • the timing control circuit sends signals to the first group of clock signal traces and the second group of clock signal traces, and the first gate drive circuit receives the same clock signal and simultaneously outputs to the scan lines corresponding to the display screens on both sides.
  • the timing control chip controls the first group of clock signal traces 141 and the second group of clock signal traces 142 to be output synchronously or asynchronously, which can adapt to more use environments and can meet more demands.
  • the display panel includes a second gate driving circuit 115 disposed on the side of the first display screen 111 away from the second display screen 112 and coupled to the first scan line 120, and A third gate drive circuit 116, a first gate drive circuit 113, and a second gate disposed on the side of the second display screen 112 away from the first display screen 111 and coupled to the second scan line 130
  • the drive circuit 115 and the third gate drive circuit 116 receive the same clock signal; specifically, two adjacent gate drive circuits may be connected to the same set of clock signal traces, or to different clock signal traces, but The same clock signal is controlled to be received by a timing control circuit coupled together.
  • the second gate driving circuit 115 and the first gate driving circuit 113 jointly drive the first display screen 111, and the third gate driving circuit 116 and the first gate driving circuit 113 jointly drive the second display screen 112, reducing the first gate
  • the pole drive circuit 113 corresponds to the workload of the first display side and the second display side, which effectively reduces the distance between the farthest end of the scanning line and the gate drive circuit, reduces the load, and improves the scanning waveform.
  • the first gate drive circuit 113 corresponds to the workload of the first display side and the second display side, which effectively reduces the distance between the farthest end of the scanning line and the gate drive circuit, reduces the load, and improves the scanning waveform.
  • the second gate driving circuit 115 and the third gate driving circuit 116 receive the same clock signal and jointly drive the display panel 110, so that the scanning performance of the scanning line is better, and the control of turning on and off the pixels is more accurate, so that the display The load of the panel 110 is small, the signals are synchronized, and the display effect of the display panel 110 is good.
  • the first gate driving circuit 113 is disposed between the first display screen 111 and the second display screen 112, and the first display screen and the second display screen are integrally formed.
  • the display panel includes an integrally formed glass substrate 114.
  • the metal traces and layer structures corresponding to the first display screen 111 and the second display screen 112 can be formed through the same process (for example: Data lines, scan lines, gate drive circuit traces, active switches, etc.) are simultaneously formed on a large glass substrate 114.
  • the metal traces and layer structure corresponding to the first display screen 111 and the metal traces and layer structure corresponding to the second display screen 112 can share the same process, or can be formed on the same large On the glass substrate 114.
  • the first display screen 111 and the second display screen 112 are formed by the same process, which saves the process and process flow, and has high production efficiency and low production cost; at the same time, the stitching of the first display screen 111 and the second display screen 112 is omitted In the step, no splicing error occurs, and the display panel 110 is not prone to quality problems.
  • the above-mentioned glass substrate is a whole large glass substrate, and of course, glass substrates made of other materials may be used as long as applicable.
  • the display panel includes N display screens including the first display screen and the second display screen, and the N display screens are aligned side by side from the first display screen 170 to the Nth display screen Setting, two adjacent display screens are coupled by the same gate drive circuit 160; the display panel includes M columns of display rows closely arranged in the vertical direction, and the M columns of display rows are from the first display row 190 to the Mth display row 200 is sequentially aligned and set, N each display row includes N display screens arranged side by side; is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1; between each two adjacent display screens Each is provided with a gate driving circuit 160, which is respectively coupled to the two adjacent display screens, and if applicable, the gate driving circuit 160 is provided on the upper side or both sides of the display screen It is also possible to connect the first scanning line and the second scanning line separately through the connecting line.
  • the display panel can be assembled by multiple display screens, and the size can be formed on the same glass substrate through the same process as needed, or they can be assembled after being formed separately; at the same time, two adjacent display screens are coupled by the same gate drive circuit It is equivalent to that each display screen has at least one correspondingly driven gate drive circuit, and the load corresponding to each gate drive circuit is not too high.
  • an infinite number of display screens can be arranged side by side to form the display panel, that is Based on the current technical level, a larger size display panel that can be manufactured and is practical.
  • a gate drive circuit 160 is provided between two adjacent display screens.
  • the gate drive circuit 160 can drive the display panels on both sides, and the gate drive circuit on the side of the edge display screen far from the middle display screen can reduce the workload of the middle gate drive circuit, and the gate drive efficiency is higher, The reaction speed is faster and the display effect of the display panel is better.
  • the scan waveform may change from a rectangular waveform to an arc waveform.
  • the conduction cannot be conducted normally during the turn-on and cannot be turned off well when the turn-off is performed. This limits the maximum size of the display panel provided on the side based on the gate drive circuit.
  • This application drives the scan lines on both sides from the middle of the scan lines corresponding to the two sets of display screens, which allows the gate drive circuit to be placed in the middle of the panel.
  • the distance of the circuit can be adjusted to avoid excessive load and severe waveform distortion, which is conducive to further increasing the size of the display panel.
  • the display panel 110 is provided with a normal phase clock signal line CLK, a reverse phase clock signal line CLKB, a low voltage signal line Vss, and a gate start signal (Start Vertical, STV );
  • CLK normal phase clock signal
  • CLKB reverse phase clock signal line
  • Vss low voltage signal line
  • STV gate start signal
  • Each display screen is provided with N scanning lines;
  • the gate drive circuit is respectively arranged between two adjacent display screens, the gate drive circuit includes two groups of gate drive sub-circuits, each group of gate drive sub-circuits The circuit includes N gate drive sub-circuits corresponding to the scan lines one-to-one.
  • the first gate driving sub-circuit and the second gate driving sub-circuit are respectively coupled to the first normal phase clock signal line, the first reverse phase clock signal line and the first low voltage signal line;
  • the first gate driving sub circuit 1131 includes N gate drive sub-circuits,
  • the second gate drive sub-circuit 1132 includes N gate drive sub-circuits, each gate drive sub-circuit has a positive phase clock signal input terminal CLK, a reverse phase clock signal input terminal CLKB and low
  • the voltage signal input terminal Vss, and the clock signal received by each driver sub-circuit is the same, and each gate driver sub-circuit also has an input terminal Input, an output terminal Output, and a reset terminal Reset.
  • the output of each row of gate drive sub-circuits is used as the input of the next row of gate drive sub-circuits and as the reset terminal of the previous row of gate drive sub-circuits.
  • the input terminals of the pole drive sub-circuit are represented as Input R and Input L, the output outputs are respectively Output R and Output L, and the reset terminals are Reset as R and Reset L respectively, and the signal timing of the gate drive sub-circuit
  • the waveform diagram is shown in Figure 11.
  • the input terminal of the Nth gate driving subcircuit is connected to the output terminal of the n-1th gate driving subcircuit, and the output terminal of the Nth gate driving subcircuit is connected to the reset of the n-1th gate driving subcircuit And the scan line, the reset end of the Nth gate drive sub-circuit is connected to the output of the N+1th gate drive sub-circuit; the input end of the first gate drive sub-circuit corresponding to the first row of scan lines is connected The gate start signal; the last gate drive sub-circuit corresponding to the last row of scanning lines is directly connected to the last row of scanning lines; N is a positive integer greater than or equal to 2.
  • Each gate drive sub-circuit is connected to the same normal-phase clock signal line CLK, reverse-phase clock signal line CLKB and low-voltage signal line Vss; the same signal can be driven simultaneously on both sides of the display screen, and the scan line is away from the gate drive circuit
  • the farthest distance can be greatly shortened, the load of the scan line between the farthest end of the scan line and the gate drive circuit is greatly reduced, and the scan waveform at the far end of the scan line can be greatly improved.
  • the improved waveform is shown in FIG. 9
  • the scanning line can be operated stably, thereby improving the problem of excessive load on the large-size display panel and the severe deformation of the scanning waveform caused by the excessive load.
  • the reasonable setting of the input terminal, output terminal and reset terminal enables each gate drive circuit to work stably.
  • the display panel 110 is provided with a first normal phase clock signal line CLK1, a second normal phase clock signal line CLK2, a first Inverted clock signal line CLKB1, second inverted clock signal line CLKB2, and low voltage signal line Vss; each display screen is provided with N scanning lines;
  • the gate drive circuit includes two groups of gate drive sub-circuits, each group The gate driving sub-circuit includes N gate driving sub-circuits corresponding to the scanning lines in one-to-one correspondence; the two groups of the gate driving sub-circuits are respectively coupled to the first normal phase clock signal line CLK1 and the second normal phase Clock signal line CLK2, two groups of the gate drive sub-circuits are respectively coupled to the first inverted clock signal line CLKB1 and the second inverted clock signal line CLKB2, in particular, the two groups of gate drive sub-circuits are respectively coupled to On the same low-voltage signal line Vss, two groups of gate drive sub-circuits that output simultaneously at
  • the present application can set the first gate drive circuit in the middle of the first display screen and the second display screen, so that the two display screens can be selected Use the same gate drive circuit to drive, and the gate drive circuit is from the middle of the entire display panel, you can choose to drive one or both sides of the display screen, the first gate drive circuit controls the scan lines corresponding to the two display screens Scanning and bidirectional output, so that the farthest distance between the scanning lines in the first display screen and the second display screen from the gate drive circuit can be greatly shortened (compared to setting the gate drive circuit on the side of the display panel ), the resistance of the scan line between the farthest end of the scan line and the gate drive circuit becomes smaller, so the load is greatly reduced, which can greatly improve the scan waveform at the far end of the scan line (the improved waveform is shown in Figure 13) (Display), so that the scan line can work stably, thereby improving the situation that the large-size display panel is overloaded,
  • the display panel 110 includes a timing control circuit, including steps:
  • the first gate driving circuit receives the clock signal output by the timing control circuit
  • the first gate driving circuit scans the first scan line and the second scan line 130 simultaneously based on the same set of clock signals.
  • the same gate drive circuit is used between two adjacent display screens, and the gate drive circuit can drive both display screens at the same time, and the maximum distance between the scanning line and the gate drive circuit can be greatly shortened ,
  • the load of the scan line between the farthest end of the scan line and the gate drive circuit is greatly reduced, and the scan waveform at the far end of the scan line can be greatly improved, so that the scan line can work stably, thereby improving the size of the large-size display panel
  • the gate drive circuit scans the first scanning line and the second scanning line simultaneously based on the same set of clock signals, making it possible to increase the display screen infinitely .
  • a gate drive circuit is correspondingly arranged between each two adjacent display screens, and the gate drive circuit between the two adjacent display screens will simultaneously drive the scanning in the display screens on both sides line.
  • the display panel includes a plurality of display screens and a first gate driving circuit, and the plurality of display screens are arranged in X*Y and formed in the same
  • the first gate driving circuit is disposed between two adjacent display screens to drive the two adjacent display screens, where X is the position of each column in the first direction
  • the number of display screens, Y is the number of display screens in each row in the second direction, the first direction is perpendicular to the second direction, and the two adjacent display screens are the first display screens respectively
  • the second direction is the extending direction of the scanning lines of the first display screen and the second display screen, and the X positions of each row of the display panel provided in the second direction of the display panel
  • the display screen is a first display screen, a second display screen... an X display screen from one end to the other end;
  • the first gate drive circuit is provided with X in each row in the second direction -1, the first gate drive circuits are respectively disposed between two adjacent display screens;
  • the display panel further includes a second gate drive circuit, and the second gate drive circuit is located in the There are two for each row in the second direction, respectively corresponding to the side of the first display screen away from the Xth display screen, and the Xth display screen away from the first display screen The side of the screen.
  • the glass size is constant, the value of X is 1, and the value of Y is 2, which can meet the requirements of large size.
  • the first gate drive circuit includes a bidirectional gate drive circuit, the bidirectional gate drive circuit receives a set of input signals, Output two sets of scan signals to simultaneously drive the scan lines of the first display screen and the second display screen; specifically, the first gate drive circuit includes a first unidirectional gate drive unit and a second unidirectional gate drive unit A gate drive unit, the first unidirectional gate drive unit receives a set of input signals, outputs a set of scan signals to drive the first display screen, and the second unidirectional gate drive unit receives another set of inputs Signal to output another set of scan signals to drive the second display screen.
  • the scan lines of the first display screen and the second display screen can also be connected;
  • the first gate drive circuit includes a bidirectional gate drive circuit, and the bidirectional gate drive circuit receives a set of input signals, Output a set of scan signals to simultaneously drive the scan lines of the first display screen and the second display screen;
  • the access position of the output end of the bidirectional gate drive circuit is located on the first display screen and the second At the connection point of the scanning line of the display screen, when the scanning line is connected, if there is a problem on one side of the bidirectional gate drive circuit, the other side can ensure that the display panel will not be unusable because the display effect is too poor.
  • the technical solution of the present application can be widely used in various display panels, such as TN type display panel (full name Twisted Nematic, namely twisted nematic panel), IPS type display panel (In-Plane Switching, plane conversion), VA type display Panel (Vertical Alignment, vertical alignment technology), MVA type display panel (Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology), of course, can also be other types of display panels, such as organic light-emitting display panel (organic light-emitting diode) , Referred to as OLED display panel), can apply the above solutions.
  • TN type display panel full name Twisted Nematic, namely twisted nematic panel
  • IPS type display panel In-Plane Switching, plane conversion
  • VA type display Panel Vertical Alignment, vertical alignment technology
  • MVA type display panel Multi-domain Vertical Alignment, multi-quadrant vertical alignment technology
  • OLED display panel organic light-emitting diode

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本申请公开了一种显示面板、驱动方法和显示装置，所述显示面板(110)包括对应设置有第一扫描线(120)的第一显示屏(111)、对应设置有第二扫描线(130)的第二显示屏(112)；以及耦接于所述第一扫描线(120)和所述第二扫描线(130)的第一栅极驱动电路(113)；所述第一扫描线(120)和所述第二扫描线(130)不连通。

Description

显示面板、驱动方法和显示装置
本申请要求于2019年1月9日提交中国专利局，申请号为CN 201910018437.0，申请名称为“一种显示面板、驱动方法和显示装置”的中国专利申请以及于2019年1月9日提交中国专利局，申请号为CN 201910018513.8，申请名称为“一种显示面板和显示装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板、驱动方法和显示装置。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
随着薄膜晶体管液晶显示器的迅速发展，各生产厂家积极采用新技术提高产品的市场竞争力以及降低产品成本。其中，阵列基板行驱动(Gate Driver on Array，GOA)技术作为新技术的代表，是将栅极(Gate)开关电路集成在阵列基板上，以去掉栅极驱动集成电路部分，从而节省材料并减少工艺步骤，达到降低产品成本的目的。
在采用GOA进行驱动时，如果尺寸较大，扫描线很长时，若单边驱动，靠近栅极驱动电路的一端对应栅启动信号将是矩形波形，而扫描线远离栅极驱动电路一端将因为阻抗等损耗，使得波形变差以致无法很好的完成开关动作，因此亟需一种能够解决大尺寸液晶显示器负载的驱动结构。
发明内容
本申请提供了一种栅极驱动电路输出端可以进行双向输出的显示面板、驱动方法和显示装置。
本申请公开了一种显示面板，包括第一显示屏、第二显示屏和第一栅极驱动电路；所述第一显示屏内设置对应的第一扫描线，所述第二显示屏内设置对应的第二扫描线，所述第一栅极驱动电路耦接于所述第一扫描线和第二扫描线，所述第一扫描线和第二扫描线不连通。
本申请公开了一种显示面板，包括多个显示屏和多个第一栅极驱动电路，多个所述显示屏成X*Y排布，形成在同一块衬底上；多个所述第一栅极驱动电路分别设置在相邻的两个所述显示屏之间以驱动相邻的两个所述显示屏；其中，X为第一方向上的每一列的显示屏的个数，Y为第二方向上的每一行的显示屏的个数，所述第一方向和所述第二方向垂直；X为 大于等于1的正整数，Y为大于等于2的正整数。
本申请还公开了一种使用于如上述所述的显示面板的驱动方法，所述显示面板包括第一栅极驱动电路时序控制电路，包括步骤：
第一栅极驱动电路接收时序控制电路输出的时钟信号；
第一栅极驱动电路基于同一组时钟信号，同时扫描所述第一扫描线和第二扫描线。
相对于输出端是单向输出的栅极驱动电路的方案来说，本申请第一栅极驱动电路同时输出扫描信号给第一显示屏的第一扫描线和第二显示屏的第二扫描线，第一扫描线和第二扫描线本身是不连通的，相当于一条非常长的扫描线分为两段，如此，第一显示屏对应的第一扫描线和第二显示屏中的对应的第二扫描线距离第一栅极驱动电路或者说距离栅启动信号的输入端点的最远距离可以大大缩减，需要扫描的扫描线长度大大缩减后，扫描线最远端和栅极驱动电路之间的扫描线的阻值变小且干扰变少，对应的栅启动信号的衰减会得到很好的改善，从而极大的改善扫描线最远端的扫描波形，使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大问题，以及负载过大带来的扫描波形变形严重等问题。
附图说明
图所包括的附图用来提供对本申请实施例的进一步的理解，其构成了说明书的一部分，用于例示本申请的实施方式，并与文字描述一起来阐释本申请的原理。显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。在附图中：
图1是本申请的一实施例的一种显示面板的示意图；
图2是本申请的一实施例的栅极驱动子电路耦接同一时钟信号走线的示意图；
图3是本申请的另一实施例的一种栅极驱动子电路耦接不同信号走线的示意图；
图4是本申请的另一实施例的时序控制电路连接信号走线的示意图；
图5是本申请的另一实施例的多个栅极驱动电路接收同一时钟信号的示意图；
图6是本申请的一实施例的玻璃基底的示意图；
图7是本申请的一实施例的M*N的显示屏的示意图；
图8是本申请的一实施例的五个栅极驱动电路的示意图；
图9是本申请的另一实施例的十个栅极驱动电路的示意图；
图10是本申请的一实施例的两组栅极驱动子电路连接同一组时钟信号走线的电路结构的示意图；
图11是本申请的一实施例的时钟信号波形的示意图；
图12是本申请的一实施例的两组栅极驱动子电路连接两组时钟信号走线的电路结构的 示意图；
图13是本申请的一实施例的时钟信号波形的示意图；
图14是本申请的一实施例的方法步骤的示意图；
图15是本申请的另一实施例的显示装置的示意图。
具体实施方式
下需要理解的是，这里所使用的术语、公开的具体结构和功能细节，仅仅是为了描述具体实施例，是代表性的，但是本申请可以通过许多替换形式来具体实现，不应被解释成仅受限于这里所阐述的实施例。
在本申请的描述中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示相对重要性，或者隐含指明所指示的技术特征的数量。由此，除非另有说明，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征；“多个”的含义是两个或两个以上。术语“包括”及其任何变形，意为不排他的包含，可能存在或添加一个或更多其他特征、整数、步骤、操作、电路、组件和/或其组合。
另外，“中心”、“横向”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系的术语，是基于附图所示的方位或相对位置关系描述的，仅是为了便于描述本申请的简化描述，而不是指示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
此外，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，或是两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。
下面参考附图和可选的实施例对本申请作进一步说明。
如图1至7所示，本申请的一实施例公开了一种显示面板110，至少包括：设置有第一扫描线120的第一显示屏111；设置有第二扫描线130的第二显示屏112；以及耦接于所述第一扫描线120和第二扫描线130的第一栅极驱动电路113，第一扫描线120和第二扫描线130不连通，或者不直接连通。
第一栅极驱动电路113同时输出扫描信号给第一显示屏111的第一扫描线120和第二显示屏112的第二扫描线130，第一扫描线120和第二扫描线130本身是不连通的，相当于一条非常长的扫描线分为两段，如此，该第一显示屏111对应的第一扫描线120和第二显示屏112中的对应的第二扫描线130距离第一栅极驱动电路113或者说距离栅启动信号的输入端点的最远距离可以大大缩减，需要扫描的扫描线长度大大缩减后，扫描线最远端和栅极驱动 电路之间的扫描线的阻值变小且干扰变少，对应的栅启动信号的衰减会得到很好的改善，从而极大的改善扫描线最远端的扫描波形，使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大，以及负载过大带来的扫描波形变形严重等情况。
如图2所示，第一栅极驱动电路113包括设置在所述第一显示屏111和所述第二显示屏112之间的第一栅极驱动子电路1131和第二栅极驱动子电路1132，显示面板110还包括第一组时钟信号走线141；第一栅极驱动子电路1131耦合于第一扫描线120和第一组时钟信号走线141，第二栅极驱动子电路1132耦合于第二扫描线130第一组时钟信号走线141。
第一栅极驱动电路113包括第一栅极驱动子电路和第二栅极驱动子电路，并且，该第一栅极驱动子电路1131和第二栅极驱动子电路1132设置在第一显示屏和第二显示屏之间；第一栅极驱动子电路可以控制第一显示屏111的第一扫描线120进行扫描，第二栅极驱动子电路控制第二显示屏112对应和第二扫描线130进行扫描,如此，第一扫描线和第二扫描线的最远端，与第一栅极驱动子电路1131或第二栅极驱动子电路1132的距离可以大大缩短，扫描线最远端和第一栅极驱动电路113之间的扫描线的负载大大降低，能够极大的改善扫描线最远端的扫描波形，另外第一栅极驱动子电路1131和第二栅极驱动子电路1132都耦合于第一组时钟信号走线141，接收相同的时钟信号，使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大，以及负载过大带来的扫描波形变形严重等情况。
该第一栅极驱动电路也可以仅设置一组栅极驱动子电路，一组栅极驱动子电路耦合于同一组时钟信号走线140，一组时钟信号走线包括一条正相时钟信号线CLK和一条反相时钟信号线CLKB，两边的显示屏中的扫描线同时连接该该一组栅极驱动子电路，该一组栅极驱动子电路可以通过增加输出端口，或者第一扫描线120和第二扫描线130相互连通的方式，当然其他适用的方式也是可以的，两组栅极驱动子电路耦合于同一组时钟信号线140，可以节省一组时钟信号线，栅极驱动电路两侧的显示屏的扫描信号能够确保同步，驱动效果好，显示面板110的显示效果更好。
如图3至图4所示，显示面板包括第一栅极驱动电路113，显示面板包括与所述第一显示屏111对应设置的第一组时钟信号走线141,以及与所述第二显示屏112对应设置的第二组时钟信号走线142；第一栅极驱动电路113包括设置在所述第一显示屏111和所述第二显示屏112之间的第一栅极驱动子电路1131和第二栅极驱动子电路1132，所述第一栅极驱动子电路1131分别耦合于第一扫描线120和所述第一组时钟信号走线141，所述第二栅极驱动子电路分别耦合于第二扫描线和第二组时钟信号走线。
具体的，如果第一显示屏111和第二显示屏112一体成型时，该第一组时钟信号走线141和第二组时钟信号走线142，以及第一栅极驱动子电路1131和第二栅极驱动子电路1132可以设置在第一显示屏和第二显示屏之间；当该第一显示屏和第二显示屏是分别制造，再拼接 组装的方式时，第一显示屏和第二显示屏之间对应第一栅极驱动电路可以设置黑矩阵(Black Matrix，BM)，该第一组时钟信号走线以及对应的栅极驱动子电路可以形成在第一显示屏的***区，第二组时钟信号走线以及对应的栅极驱动子电路可以形成在第二显示屏的***区，再拼接组装在一起。
两组时钟信号，可以控制同步或者不同步输出，同步输出时，可以同时进行画面显示；而不同步输出时，配合适当的背光驱动以及数据驱动，能够更好地控制仅其中一个显示屏显示画面，使用范围更广，可选择更强。
其中，显示面板110包括时序控制电路150，第一组时钟信号走线141和第二组时钟信号走线142耦合于时序控制电路150，第一栅极驱动电路中的第一栅极驱动子电路和第二栅极驱动子电路共用一条低电压信号走线Vss。
时序控制电路发送信号给第一组时钟信号走线和第二组时钟信号走线，第一栅极驱动电路接收相同的时钟信号，同时输出给两边的显示屏对应的扫描线。时序控制芯片控制该第一组时钟信号走线141和第二组时钟信号走线142同步输出或者异步输出，能够适应更多种使用环境，并能够胜任更多种需求。
如图5所示，显示面板括设置在所述第一显示屏111远离所述第二显示屏112的侧边、且耦合于所述第一扫描线120的第二栅极驱动电路115，以及设置在所述第二显示屏112远离所述第一显示屏111的侧边、且耦合于第二扫描线130的第三栅极驱动电路116，第一栅极驱动电路113、第二栅极驱动电路115和第三栅极驱动电路116接收相同的时钟信号；具体的,相邻两个栅极驱动电路可以连接于同一组时钟信号走线，或者分别连接于不同的时钟信号走线，但是通过共同耦接的时序控制电路来控制接收相同的时钟信号。
第二栅极驱动电路115和第一栅极驱动电路113共同驱动第一显示屏111，第三栅极驱动电路116和第一栅极驱动电路113共同驱动第二显示屏112，减轻第一栅极驱动电路113对应第一显示屏侧和第二显示屏侧的工作负荷，有效的减少了扫描线最远端跟栅极驱动电路的距离，减轻负载同时改善扫描波形，第一栅极驱动电路113、第二栅极驱动电路115和第三栅极驱动电路116接收相同的时钟信号，共同驱动显示面板110，使得扫描线的扫描性能更好，打开和关断像素的控制更加准确，使得显示面板110的负载小，信号同步，显示面板110的显示效果好。
如图6所示，第一栅极驱动电路113设置在第一显示屏111与第二显示屏112之间，所述第一显示屏和所述第二显示屏一体成型。如图7所示,该显示面板包括一体成型的玻璃基底114，具体的，可以通过同一制程将所述第一显示屏111和第二显示屏112对应的金属走线以及层膜结构(例如：数据线、扫描线、栅极驱动电路走线和主动开关等)等，同时形成在一块大的玻璃基底114上。
其中，该第一显示屏111对应的金属走线以及层膜结构，和第二显示屏112对应的金属走线以及层膜结构可以共用制程，也可以分别通过不同的制程形成在同一块大的玻璃基底114上。本方案中，第一显示屏111和第二显示屏112通过同一制程形成，节省制程和工艺流程，生产效率高，生产成本低；同时省去第一显示屏111和第二显示屏112的拼接步骤，不会出现拼接误差，显示面板110不容易出现质量问题。
其中，上述的玻璃基底即一整块大的玻璃基板，当然，其他材料制程的玻璃基底，只要适用也是可以的。
如图7所示，显示面板包括设置有包含所述第一显示屏和第二显示屏在内的N个显示屏，N个显示屏从第一个显示屏170到第N个显示屏并排对齐设置，相邻的两个显示屏通过同一栅极驱动电路160耦接；显示面板包括垂直方向紧贴设置的M列显示行，M列显示行从第一行显示行190到第M行显示行200依次对齐设置，N每列显示行包括N各并排设置的所述显示屏；为大于等于2的正整数；M为大于等于1的正整数；每两个相邻的所述显示屏之间均设置有一栅极驱动电路160，栅极驱动电路160分别耦接于相邻的两个所述显示屏，在可实施的情况下，栅极驱动电路设置在显示屏的上侧边或两侧边，通过连接线，分别连接于第一扫描线和第二扫描线也是可以的。
在大尺寸产品采用GOA进行驱动时，由于驱动电路负载很大，多采用双边驱动的模式。然而，当尺寸进一步增大时，双边驱动也可能不会满足需求。显示面板可以通过多个显示屏组装在一起，尺寸大小可以根据需要通过同一制程形成在同一玻璃基板上，或者分别形成之后再组装；同时，相邻的两个显示屏通过同一栅极驱动电路耦接，相当于每个显示屏至少有一个对应驱动的栅极驱动电路，每个栅极驱动电路对应的负载不至于过高，理论上，可以实现无限多的显示屏并排构成该显示面板，即基于当前的技术水平，可以制造得到，实用的更大尺寸的显示面板。
如图8所示，栅极驱动电路至少设置有五个，采用5个栅极驱动电路进行驱动，并且可以组数无限增加，相邻的两个显示屏中间设置一个栅极驱动电路160，中间的栅极驱动电路160可以驱动两边的显示面板，边缘的显示屏中远离中间显示屏的一侧设置栅极驱动电路可以减轻中间的栅极驱动电路的工作负荷，栅极驱动的效率更高、反应速度更快，显示面板的显示效果更佳。
同上，如图9所示，我们还可以采用10个栅极驱动电路进行驱动，即基于当前的技术水平，可以制造得到，实用的更大尺寸的显示面板并且可以组数无限增加。
如果扫描线的远端距离栅极驱动电路太远的话，可能出现扫描波形从矩形波形变成弧形波形的情况，该导通时无法正常导通，关断时无法很好关断等问题。这限制了基于栅极驱动电路设置在侧边的显示面板的最大尺寸。而本申请从两组显示屏对应的扫描线的中部，对两 侧的扫描线进行驱动，这使得该栅极驱动电路可以设置在面板中部的方面，如此，扫描线的远端跟栅极驱动电路的距离可以进行调整，避免负载过大，波形变形严重的情况，有利于进一步加大显示面板的尺寸。
如图10所示，作为本申请的另一实施例，所述显示面板110设置有正相时钟信号线CLK、反相时钟信号线CLKB、低电压信号线Vss和栅启动信号(Start Vertical，STV)；每个显示屏设置有N条扫描线；栅极驱动电路分别对应设置在两个相邻的显示屏之间，栅极驱动电路包括两组栅极驱动子电路，每组栅极驱动子电路包括N个与扫描线一一对应的栅极驱动子电路。
共用一部分bus line(公共线)来达到栅极驱动电路可以双向输出的目的。第一栅极驱动子电路和第二栅极驱动子电路分别耦合于第一正相时钟信号线、第一反相时钟信号线和第一低电压信号线；第一栅极驱动子电路1131包括N个栅极驱动子电路,第二栅极驱动子电路1132包括N个栅极驱动子电路,每个栅极驱动子电路具有正相时钟信号输入端CLK、反相时钟信号输入端CLKB和低电压信号输入端Vss，且每个驱动子电路的接收的时钟信号相同，并且，每个栅极驱动子电路还具有输入端Input、输出端Output以及复位端Reset。其中每一行栅极驱动子电路的输出作为下一行栅极驱动子电路的输入且作为上一行栅极驱动子电路的复位端，为区别两组栅极驱动子电路，图10中，两组栅极驱动子电路的输入端Input分别表示为Input R和Input L，输出端Output分别表示为Output R和Output L，复位端Reset分别表示为Reset R和Reset L，栅极驱动子电路的各信号时序的波形图如图11所示。
第N个栅极驱动子电路的输入端连接第n-1个栅极驱动子电路的输出端，第N个栅极驱动子电路的输出端连接第n-1个栅极驱动子电路的复位端和扫描线，第N个栅极驱动子电路的复位端连接第N+1个栅极驱动子电路的输出端；对应第一行扫描线的第一个栅极驱动子电路的输入端连接于栅启动信号；对应最后一行扫描线的最后一个所述栅极驱动子电路直接连接最后一行扫描线；N为大于等于2的正整数。
每个栅极驱动子电路连接相同的正相时钟信号线CLK、反相时钟信号线CLKB和低电压信号线Vss；可以对两边显示屏输出相同信号同时进行驱动，另外扫描线距离栅极驱动电路的最远距离可以大大缩短，扫描线最远端和栅极驱动电路之间的扫描线的负载大大降低，能够极大的改善扫描线最远端的扫描波形，改善后的波形如图9所示，同时使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大问题，以及负载过大带来的扫描波形变形严重等情况。输入端、输出端和复位端的合理设置，使得各个栅极驱动电路能够稳定工作。
如图12所示，作为本申请的另一实施例，与上述实施例不同的是，所述显示面板110设置有第一正相时钟信号线CLK1、第二正相时钟信号线CLK2、第一反相时钟信号线CLKB1、第二反相时钟信号线CLKB2和低电压信号线Vss；每个显示屏设置有N条扫描线； 所述栅极驱动电路包括两组栅极驱动子电路，每组栅极驱动子电路包括N个与所述扫描线一一对应的栅极驱动子电路；两组所述栅极驱动子电路分别耦合于所述第一正相时钟信号线CLK1和第二正相时钟信号线CLK2，两组所述栅极驱动子电路分别耦合于第一反相时钟信号线CLKB1和第二反相时钟信号线CLKB2，特别说明的是，两组栅极驱动子电路分别耦合于同一低电压信号线Vss，两组同时序输出的栅极驱动子电路采用共用Bus line(公共线)的方式来达到双向输出的目的。
相对于输出端是单向输出的栅极驱动电路的方案来说，本申请可以将第一栅极驱动电路设置在第一显示屏和第二显示屏的中间位置，如此两个显示屏可以选择使用同一个栅极驱动电路来驱动，并且该栅极驱动电路是从整个显示面板的中部，可以选择对一边或者两边显示屏进行驱动，第一栅极驱动电路控制两个显示屏对应的扫描线进行扫描,进行双向输出，如此，该第一显示屏和第二显示屏中的扫描线距离栅极驱动电路的最远距离可以大大缩短(相对于将栅极驱动电路设置在显示面板的侧边)，扫描线最远端和栅极驱动电路之间的扫描线的阻值变小，故而负载大大降低，能够极大的改善扫描线最远端的扫描波形(改善后的波形如图13所示)，使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大，以及负载过大带来的扫描波形变形严重等情况。
作为本申请的另一实施例，如图14所示，公开了一种显示面板的驱动方法，显示面板110包括时序控制电路，包括步骤：
S141：第一栅极驱动电路接收时序控制电路输出的时钟信号；
S142：第一栅极驱动电路基于同一组时钟信号，同时扫描所述第一扫描线和第二扫描线130。
本方案中，相邻的两个显示屏之间使用同一个栅极驱动电路，并且该栅极驱动电路可以对两边显示屏同时进行驱动，扫描线距离栅极驱动电路的最远距离可以大大缩短，扫描线最远端和栅极驱动电路之间的扫描线的负载大大降低，能够极大的改善扫描线最远端的扫描波形，使得扫描线能够稳定的工作，从而改善大尺寸显示面板的负载过大，以及负载过大带来的扫描波形变形严重等情况，栅极驱动电路基于同一组时钟信号，同时扫描所述第一扫描线和第二扫描线，使得显示屏无限增大成为可能。
以此类推，每两个相邻并排设置的显示屏之间均对应设置有栅极驱动电路，位于相邻两个显示屏之间的栅极驱动电路，将同时驱动两侧显示屏中的扫描线。
作为本申请的另一实施例，与上述实施例不同的是，所述显示面板包括多个显示屏以及第一栅极驱动电路，多个所述显示屏成X*Y排布，形成在同一块衬底上，所述第一栅极驱动电路设置在相邻的两个所述显示屏之间以驱动相邻的两个所述显示屏，其中，X为第一方向上的每一列的显示屏的个数，Y为第二方向上的每一行的显示屏的个数，所述第一方向和 所述第二方向垂直，相邻的两个所述显示屏分别为第一显示屏，以及与所述第一显示屏在所述第二方向上相邻设置的第二显示屏；所述第一栅极驱动电路分别驱动所述第一显示屏和所述第二显示屏。
需要说明的是，所述第二方向为所述第一显示屏和所述第二显示屏的扫描线的延伸方向，所述显示面板在所述第二方向上的每一行设置的X个所述显示屏从一端至另一端分别为第一个显示屏，第二个显示屏……第X个显示屏；所述第一栅极驱动电路在所述第二方向上的每一行设置有X-1个，所述第一栅极驱动电路分别对应设置在相邻两个所述显示屏之间；另外显示面板还包括第二栅极驱动电路，所述第二栅极驱动电路在所述第二方向上的每一行设置有两个，分别对应设置在所述第一个显示屏远离所述第X个显示屏的侧边，以及所述第X个显示屏远离所述第一个显示屏的侧边。在玻璃尺寸一定的情况下，所述X的取值为1，所述Y的取值为2，即可符合大尺寸的要求。
为了使得第一栅极驱动电路的驱动信号可以精确地向两边的显示屏进行输出，所述第一显示屏和所述第二显示屏的扫描线不连通；当扫描线不连通时，相邻的两个显示屏可以通过调节输入信号从而实现共同显示一个画面或者分别显示不同画面；所述第一栅极驱动电路包括双向栅极驱动电路，所述双向栅极驱动电路接收一组输入信号，输出两组扫描信号以同时驱动所述第一显示屏和所述第二显示屏的扫描线；具体的，所述第一栅极驱动电路包括第一单向栅极驱动单元和第二单向栅极驱动单元，所述第一单向栅极驱动单元接收一组输入信号，输出一组扫描信号以驱动所述第一显示屏，所述第二单向栅极驱动单元接收另一组输入信号，输出另一组扫描信号以驱动所述第二显示屏。
当然，所述第一显示屏和所述第二显示屏的扫描线也可以连通；所述第一栅极驱动电路包括双向栅极驱动电路，所述双向栅极驱动电路接收一组输入信号，输出一组扫描信号以同时驱动所述第一显示屏和所述第二显示屏的扫描线；所述双向栅极驱动电路的输出端的接入位置位于所述第一显示屏和所述第二显示屏的扫描线的连接处，当扫描线连通时，若所述双向栅极驱动电路其中一边出现问题时，另一边能够保证显示面板不会因为显示效果太差而无法使用。
需要说明的是，在不相互冲突的前提下，本申请的技术方案可以进行结合应用。
还需要说明的是，本方案中涉及到的各步骤的限定，在不影响具体方案实施的前提下，并不认定为对步骤先后顺序做出限定，写在前面的步骤可以是在先执行的，也可以是在后执行的，甚至也可以是同时执行的，只要能实施本方案，都应当视为属于本申请的保护范围。
本申请的技术方案可以广泛用于各种显示面板，如TN型显示面板(全称为Twisted Nematic，即扭曲向列型面板)、IPS型显示面板(In-Plane Switching，平面转换)、VA型显示面板(Vertical Alignment，垂直配向技术)、MVA型显示面板(Multi-domain Vertical  Alignment，多象限垂直配向技术)，当然，也可以是其他类型的显示面板，如有机发光显示面板(organic light-emitting diode，简称OLED显示面板)，均可适用上述方案。
以上内容是结合具体的优选实施方式对本申请所作的进一步详细说明，不能认定本申请的具体实施只局限于这些说明。对于本申请所属技术领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本申请的保护范围。

Claims (18)

  1. 一种显示面板，至少包括：
    第一显示屏，设置对应的第一扫描线；
    第二显示屏，设置对应的第二扫描线；
    第一栅极驱动电路，耦接于所述第一扫描线和所述第二扫描线；
    所述第一扫描线和所述第二扫描线不连通。
  2. 如权利要求1所述的一种显示面板，其中，所述第一栅极驱动电路包括设置在所述第一显示屏和所述第二显示屏之间的第一栅极驱动子电路和第二栅极驱动子电路，所述显示面板还包括第一组时钟信号走线；
    所述第一栅极驱动子电路耦合于所述第一扫描线和所述第一组时钟信号走线；
    所述第二栅极驱动子电路耦合于所述第二扫描线和所述第一组时钟信号走线。
  3. 如权利要求1所述的一种显示面板，其中，所述显示面板还包括与所述第一显示屏对应设置的第一组时钟信号走线,以及与所述第二显示屏对应设置的第二组时钟信号走线；
    所述第一栅极驱动电路包括设置在所述第一显示屏和所述第二显示屏之间的第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路分别耦合于所述第一扫描线和所述第一组时钟信号走线，所述第二栅极驱动子电路分别耦合于所述第二扫描线和所述第二组时钟信号走线。
  4. 如权利要求3所述的一种显示面板，其中，所述显示面板还包括时序控制电路，所述第一组时钟信号走线和所述第二组时钟信号走线耦合于所述时序控制电路。
  5. 如权利要求1所述的一种显示面板，其中，所述第一栅极驱动电路设置在所述第一显示屏与所述第二显示屏之间，所述显示面板还包括设置在所述第一显示屏远离所述第二显示屏的侧边、且耦合于所述第一扫描线的第二栅极驱动电路，以及设置在所述第二显示屏远离所述第一显示屏的侧边、且耦合于所述第二扫描线的第三栅极驱动电路；
    所述第一栅极驱动电路、第二栅极驱动电路和第三栅极驱动电路接收相同的时钟信号。
  6. 如权利要求1所述的一种显示面板，其中，所述第一栅极驱动电路设置在所述第一显示屏与所述第二显示屏之间，所述第一显示屏和所述第二显示屏一体成型。
  7. 如权利要求1所述的一种显示面板，其中，所述显示面板设置有包含所述第一显示屏和第二显示屏在内的N个显示屏，N个所述显示屏并排对齐设置，相邻的两个所述显示屏通过同一栅极驱动电路耦接；
    所述显示面板包括平行方向紧贴设置的M行显示行，每行所述显示行包括N个并排设置的显示屏；
    N为大于等于2的正整数，M为大于等于1的正整数；
    并排设置的所述显示屏中，每两个相邻的所述显示屏之间均设置有一个栅极驱动电路，每一个所述栅极驱动电路分别耦接于相邻的两个所述显示屏。
  8. 如权利要求7所述的一种显示面板，其中，所述M行显示行中所有的显示屏形成在同一块衬底上。
  9. 一种显示面板，包括：
    多个显示屏，多个所述显示屏成X*Y排布，形成在同一块衬底上；
    第一栅极驱动电路，设置在相邻的两个所述显示屏之间以驱动相邻的两个所述显示屏；
    其中，X为第一方向上的每一列的显示屏的个数，Y为第二方向上的每一行的显示屏的个数，所述第一方向和所述第二方向垂直；
    X为大于等于1的正整数，Y为大于等于2的正整数。
  10. 如权利要求9所述的一种显示面板，其特征在于，相邻的两个所述显示屏分别为第一显示屏，以及与所述第一显示屏在所述第二方向上相邻设置的第二显示屏；
    所述第一栅极驱动电路分别驱动所述第一显示屏和所述第二显示屏；
    其中，所述第二方向为所述第一显示屏和所述第二显示屏内的扫描线的延伸方向。
  11. 如权利要求9所述的一种显示面板，其特征在于，所述显示面板在所述第二方向上的每一行设置的X个所述显示屏从一端至另一端分别为第一个显示屏，第二个显示屏……第X个显示屏；
    所述第一栅极驱动电路在所述第二方向上的每一行设置有X-1个，所述第一栅极驱动电路分别对应设置在相邻两个所述显示屏之间；
    所述显示面板还包括：
    第二栅极驱动电路，在所述第二方向上的每一行设置有两个，分别对应设置在所述第一个显示屏远离所述第X个显示屏的侧边，以及所述第X个显示屏远离所述第一个显示屏的侧边。
  12. 如权利要求10所述的一种显示面板，其特征在于，所述第一显示屏和所述第二显示屏的扫描线不连通；
    所述第一栅极驱动电路包括双向栅极驱动电路，所述双向栅极驱动电路接收一组输入信号，输出两组扫描信号以同时驱动所述第一显示屏和所述第二显示屏的扫描线。
  13. 如权利要求10所述的一种显示面板，其特征在于，所述第一显示屏和所述第二显示屏的扫描线连通；
    所述第一栅极驱动电路包括双向栅极驱动电路，所述双向栅极驱动电路接收一组输入信号，输出一组扫描信号以同时驱动所述第一显示屏和所述第二显示屏的扫描线；
    所述双向栅极驱动电路的输出端的接入位置位于所述第一显示屏和所述第二显示屏的扫描线的连接处。
  14. 如权利要求9所述的一种显示面板，其特征在于，所述第一显示屏和所述第二显示屏的扫描线不连通；
    所述第一栅极驱动电路包括第一单向栅极驱动单元和第二单向栅极驱动单元，所述第一单向栅极驱动单元接收一组输入信号，输出一组扫描信号以驱动所述第一显示屏，所述第二单向栅极驱动单元接收另一组输入信号，输出另一组扫描信号以驱动所述第二显示屏。
  15. 如权利要求9所述的一种显示面板，其特征在于，多个所述显示屏和第一栅极驱动电路通过共用制程形成在同一块衬底上。
  16. 如权利要求9所述的一种显示面板，其特征在于，所述X的取值为1，所述Y的取值为2。
  17. 一种显示面板的驱动方法，所述显示面板包括时序控制电路，所述驱动方法包括步骤：
    第一栅极驱动电路接收时序控制电路输出的时钟信号；以及
    第一栅极驱动电路基于同一组时钟信号，同时扫描第一扫描线和第二扫描线。
  18. 如权利要求17所述的一种显示面板的驱动方法，其中，所述显示面板还包括与所述第一显示屏对应设置的第一组时钟信号走线,以及与所述第二显示屏对应设置的第二组时钟信号走线；所述第一栅极驱动电路包括设置在所述第一显示屏和所述第二显示屏之间的第一栅极驱动子电路和第二栅极驱动子电路，所述第一栅极驱动子电路分别耦合于所述第一扫描线和所述第一组时钟信号走线，所述第二栅极驱动子电路分别耦合于所述第二扫描线和所述第二组时钟信号走线。
PCT/CN2019/130237 2019-01-09 2019-12-31 显示面板、驱动方法和显示装置 WO2020143501A1 (zh)

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