WO2020119774A1 - Integrating circuit and integrating method thereof - Google Patents

Integrating circuit and integrating method thereof Download PDF

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Publication number
WO2020119774A1
WO2020119774A1 PCT/CN2019/125012 CN2019125012W WO2020119774A1 WO 2020119774 A1 WO2020119774 A1 WO 2020119774A1 CN 2019125012 W CN2019125012 W CN 2019125012W WO 2020119774 A1 WO2020119774 A1 WO 2020119774A1
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Prior art keywords
switch
capacitor
voltage
error
feedback voltage
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PCT/CN2019/125012
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French (fr)
Chinese (zh)
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张识博
卢圣晟
李亮
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华润矽威科技（上海）有限公司
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Publication of WO2020119774A1 publication Critical patent/WO2020119774A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/561—Voltage to current converters
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the invention relates to the field of integrated circuit design, in particular to an integrating circuit and its integrating method.
  • the traditional closed-loop control loop needs to be connected with a filter capacitor with a larger capacitance. Because the capacitance of the filter capacitor is larger, it cannot be integrated into the chip. Therefore, the filter capacitor needs to be set outside the chip, so it needs to be reserved on the chip Pin, the system cost increases (package cost, system cost), at the same time the peripheral circuit of the chip will become complicated, and the peripheral filter capacitor will increase the risk of closed-loop control loop failure.
  • the object of the present invention is to provide an integrating circuit and an integrating method thereof, which are used to solve the problems of complex, high cost and high failure risk of the chip peripheral circuit of the closed loop control loop in the prior art.
  • the present invention provides an integrating circuit, the integrating circuit includes at least:
  • the first input terminal of the error amplifier is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, which is used to calculate the difference between the reference voltage and the feedback voltage and amplify the output;
  • One end of the first switch is connected to the output end of the error amplifier, and the other end is connected to one end of the second switch; the other end of the second switch is connected to the input end of the control module;
  • the output terminal of the control module is connected to the second input terminal of the error amplifier to provide the feedback voltage for the error amplifier
  • the upper plate of the first capacitor is connected to the input of the first switch, and the lower plate is grounded;
  • the upper plate of the second capacitor is connected to the output of the first switch, and the lower plate is grounded;
  • the upper plate of the third capacitor is connected to the output end of the second switch, and the lower plate is grounded;
  • the switching signal of the first switch and the switching signal of the second switch are inverted.
  • the first switch is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor
  • the second switch is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.
  • the first switch, the second switch, the first capacitor, the second capacitor, and the third capacitor are integrated in a chip.
  • the integration method includes at least:
  • the first capacitor filters out the high frequency component of the error voltage
  • the second capacitor and the third capacitor filter out the intermediate frequency component of the error voltage
  • the error voltage charges and discharges the second capacitor, the second switch is turned off, and the compensation voltage does not change
  • the error voltage is disconnected from the second capacitor, the second switch is turned on, the second capacitor charges and discharges the third capacitor, and the compensation voltage varies The voltage on the third capacitor changes.
  • the equivalent resistances of the first switch, the second switch, and the second capacitor satisfy the following relationship:
  • R eq is the equivalent resistance
  • T C is the switching period of the first switch and the second switch
  • C 2 is the capacitance of the second capacitor
  • the main pole frequency of the integration circuit satisfies the following relationship:
  • T C is the switching period of the first switch and the second switch
  • C 2 is the capacitance of the second capacitor
  • C 3 is the capacitance of the third capacitor
  • the integral is decreased by increasing the switching period of the first switch and the second switch, increasing the capacitance of the third capacitor, or decreasing the capacitance of the second capacitor The main pole frequency of the circuit.
  • adjusting the feedback voltage based on the compensation voltage gradually decreases; when the feedback voltage is less than the reference voltage, adjusting the feedback voltage based on the compensation voltage The feedback voltage gradually increases.
  • the integration circuit and the integration method of the present invention have the following beneficial effects:
  • the integration circuit and the integration method of the present invention use an error amplifier, a switch and a capacitor to achieve the integration function, which can greatly reduce the capacitance value of the capacitor and avoid the capacitor from being placed outside the chip, thereby simplifying the chip peripheral circuit and reducing the system cost and packaging cost. And reduce the risk of failure and improve system reliability.
  • FIG. 1 shows a schematic structural diagram of the first integration circuit of the present invention.
  • FIG. 2 shows a schematic diagram of the working principle of the first integration circuit of the present invention.
  • FIG. 3 is a schematic structural diagram of a second integration circuit of the present invention.
  • FIG. 4 shows a schematic diagram of the working principle of the second integration circuit of the present invention.
  • this embodiment provides an integration circuit 1 that includes:
  • the non-inverting input terminal of the error amplifier 11 is connected to a reference voltage V REF
  • the inverting input terminal is connected to the output terminal of the control module 12
  • the output terminal of the error amplifier 11 is connected to the control module The input of 12.
  • the upper plate of the filter capacitor C is connected to the output end of the error amplifier 11, and the lower plate is grounded.
  • the error amplifier 11 and the control module 12 are integrated in the chip; the filter capacitor C is provided outside the chip, through the pins on the chip and the error amplifier 11 and The control module 12 is connected.
  • the output signal of the control circuit 12 is used as a feedback voltage V FB
  • the error amplifier 11 differentially amplifies the feedback voltage V FB and the reference voltage V REF to obtain a compensation voltage V COMP
  • the control circuit 12 Adjust the magnitude of the feedback voltage V FB according to the compensation voltage V COMP , thereby forming a feedback closed loop to achieve integration. Since the capacitance value of the filter capacitor C is relatively large and cannot be integrated into the chip, it can only be arranged on the periphery of the chip, which has a high cost and a high risk of failure.
  • the integration circuit 1 may not include the control module 12, the feedback voltage V FB is the voltage on the filter capacitor C, and accordingly the feedback voltage V FB slowly follows the reference voltage V REF , And the average value of the feedback voltage is equal to the average value of the reference voltage.
  • the main pole of the integration circuit 1 can be obtained, satisfying the following relationship:
  • f p is the main pole frequency
  • C is the capacitance of the filter capacitor C.
  • this embodiment provides an integrating circuit 2, which includes:
  • the error amplifier 21 the first switch S1, the second switch S2, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the control circuit 22.
  • the first input terminal of the error amplifier 21 is connected to the reference voltage V REF and the second input terminal is connected to the feedback voltage V FB .
  • the error amplifier 21 calculates the reference voltage V REF and the feedback voltage V FB difference and enlarge the output.
  • the non-inverting input terminal of the error amplifier 21 receives the reference voltage V REF and the inverting input terminal receives the feedback voltage V FB .
  • the error amplifier 21 The input terminal and the input signal can be interchangeably connected, and the polarity of the input signal can be adjusted through the inverter to satisfy the logical relationship of this embodiment, and is not limited to this embodiment.
  • one end of the first switch S1 is connected to the output end of the error amplifier 21, and the other end is connected to one end of the second switch S2; the other end of the second switch S2 is connected to the control The input end of the module 22; the upper plate of the first capacitor C1 is connected to the input end of the first switch S1, the lower plate is grounded; the upper plate of the second capacitor C2 is connected to the first switch S1 At the output end, the lower plate is grounded; the upper plate of the third capacitor C3 is connected to the output end of the second switch S2, and the lower plate is grounded.
  • the first switch S1 includes but is not limited to an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor. Any device that can realize a switching function is applicable to the first switch in this embodiment. This embodiment is limited.
  • the second switch S2 includes but is not limited to an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor. Any device that can achieve a switching function is applicable to the second switch in this embodiment, and is not implemented in this embodiment. Examples are limited.
  • the switching voltage Sw of the first switch S1 and the switching voltage Sw of the second switch S2 are inverse signals, that is, the second switch S2 is turned off when the first switch S1 is turned on, and the first When one switch S1 is turned off, the second switch S2 is turned on, and only one switch is turned on at a time.
  • the switching voltage frequency of the first switch S1 and the second switch S2 is greater than the frequency of the output voltage of the error amplifier 21.
  • the capacitance of the first capacitor C1 is relatively small, and can be integrated into the chip, and the pole of the filter unit where the first capacitor C1 is located is calculated to satisfy the following relationship:
  • f p1 is the pole frequency of the filter unit where the first capacitor C1 is located
  • R OUT is the output impedance of the error amplifier 11
  • C 1 is the capacitance of the first capacitor C1.
  • the pole frequency f p1 is set large, and only the high-frequency components of the periodic feedback voltage V FB can be filtered out.
  • the output voltage V1 of the first capacitor C1 still contains low-frequency and intermediate-frequency components, so the ripple is large and needs to be Perform post-processing.
  • first switch S1, the second switch S2, and the second capacitor C2 may be equivalent to resistances, satisfying the following relationship:
  • R eq is the equivalent resistance of the first switch S1, the second switch S2 and the second capacitor C2
  • T C is the switching period of the first switch S1 and the second switch S2
  • C 2 is the capacitance of the second capacitor C2.
  • the value of the equivalent resistance R eq can be increased by increasing the switching period T C of the first switch S1 and the second switch S2.
  • the equivalent resistance R The value of eq can be made very large, and the value of the equivalent resistance R eq can be set as needed, which will not be repeated here.
  • the capacitance of the second capacitor C2 can also be reduced accordingly, which will not be repeated here.
  • the first switch S1, the second switch S2, the second capacitor C2 and the third capacitor C3 form a low-pass filter, and the main pole frequency satisfies the following relationship:
  • the first switch S1, the second switch S2, the second capacitor C2, and the third capacitor C3 filter out the intermediate frequency component in the output voltage V1 of the first capacitor C1, so that the control module 22
  • the compensation voltage V COMP at the input contains only low-frequency components, and the ripple is small.
  • the second capacitor C2 can correspondingly reduce the capacitance (the The capacitances of the second capacitor C2 and the third capacitor C3 are subject to being integrated into the chip, and are not specifically limited.) Therefore, the first switch S1, the second switch S2, and the second Both the capacitor C2 and the third capacitor C3 can be integrated into the chip, which greatly simplifies the peripheral circuit of the chip and increases reliability.
  • control module 22 receives the compensation voltage V COMP and adjusts the feedback voltage V FB based on the compensation voltage V COMP .
  • the input terminal of the control module 22 is connected to the output terminal of the second switch S2, and the output terminal is connected to the inverting input terminal of the error amplifier 21.
  • the control module 22 includes, but is not limited to, an LED drive control module.
  • the output signal of the control module 22 is the sampling voltage V CS of the LED output current, and the power switching tube is controlled based on the compensation voltage V COMP . Then realize the control of the output current.
  • any structure that controls the output through the feedback loop is applicable, and is not limited to this embodiment.
  • the integrating circuit 2 may not include the control module 22, and the output terminal of the second switch S2 is connected to the second input terminal of the error amplifier 21 to provide the feedback to the error amplifier 21 Voltage V FB , the feedback voltage V FB is the compensation voltage V COMP , the feedback voltage V FB slowly follows the reference voltage V REF , and the average value of the feedback voltage V FB is equal to the reference voltage V REF Of the mean.
  • the working principle of the integration circuit 2 is as follows:
  • the error amplifier 21 amplifies the difference between the reference voltage V REF and the feedback voltage V FB to obtain an error voltage V1, and filters the error voltage V1 to generate a compensation voltage V COMP based on the compensation
  • the voltage V COMP regulates the feedback voltage V FB to form a feedback loop, thereby achieving integration.
  • the error amplifier 21 outputs an error voltage V1 between the reference voltage V REF and the feedback voltage V FB .
  • the error voltage V1 is filtered by the first capacitor C1 to remove high-frequency components, and then passes through the first switch S1, the second switch S2, the second capacitor C2 and the third capacitor C3.
  • the pass filter filters out the intermediate frequency component, leaving only the low frequency component to obtain the compensation voltage V COMP with a small ripple.
  • the feedback voltage V FB is adjusted based on the compensation voltage V COMP , and then the average value of the feedback voltage V FB is equal to the reference voltage V REF .
  • the switches of the first switch S1 and the second switch S2 are controlled by clock voltages whose logic states are completely opposite.
  • the first switch S1 is closed is turned on, the error voltage V1 to the second capacitor C2 is charged and discharged when the error voltage V1 is greater than the voltage on the second capacitor C2 when the The error voltage V1 charges the second capacitor C2, and the output voltage V2 of the first switch S1 rises; when the error voltage V1 is less than the voltage on the second capacitor C2, the error voltage V1 pairs The second capacitor C2 is discharged, and the output voltage V2 of the first switch S1 decreases.
  • the second switch S2 is turned off, the charge on the third capacitor C3 remains unchanged, and the compensation voltage V COMP remains unchanged.
  • the first switch S1 is turned off, and the error voltage V1 is disconnected from the second capacitor C2.
  • the second switch S2 is closed and turned on, and the second capacitor C2 charges and discharges the third capacitor C3, thereby increasing or decreasing the voltage value of the compensation voltage V COMP .
  • the compensation voltage V COMP changes stepwise (rising or falling) in units of the switching voltage periods of the first switch S1 and the second switch S2.
  • the feedback voltage V FB is adjusted based on the compensation voltage V COMP to gradually increase; when the feedback voltage V FB is greater than the reference voltage When V REF , the feedback voltage V FB is adjusted based on the compensation voltage V COMP to gradually decrease; thereby making the average value of the feedback voltage V FB equal to the reference voltage V REF .
  • the integration circuit of the present invention integrates all the devices into the chip, so that there is no need to lead out the filter capacitor pins and no external capacitors; the solution structure is simple and the integration is higher.
  • the configuration of a large filter capacitor can be eliminated, which realizes The simplification of the peripheral circuit reduces the system cost and completely eliminates the failure problem caused by the peripheral filter capacitor.
  • the present invention provides an integration circuit and an integration method thereof.
  • the integration circuit includes: an error amplifier, a first switch, a second switch, a first capacitor, a second capacitor, a third capacitor, and a control module;
  • the first input terminal of the error amplifier is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, which is used to calculate the difference between the reference voltage and the feedback voltage and amplify the output;
  • one end of the first switch is connected to the The output end of the error amplifier, the other end is connected to one end of the second switch;
  • the other end of the second switch is connected to the input end of the control module;
  • the output end of the control module is connected to the first end of the error amplifier
  • Two input terminals provide the feedback voltage for the error amplifier;
  • the upper plate of the first capacitor is connected to the input terminal of the first switch, the lower plate is grounded;
  • the upper plate of the second capacitor is connected to the The output terminal of the first switch, the lower plate is grounded;
  • the invention has a simple structure and higher integration, and can dispense with the configuration of a large filter capacitor, which simplifies the peripheral circuit, reduces the system cost, and completely eliminates the failure problem caused by the peripheral filter capacitor. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

An integrating circuit (2) and an integrating method thereof. The integrating circuit comprises: an error amplifier (21) which amplifies and outputs a difference between a reference voltage and a feedback voltage; a first switch (S1) and a second switch (S2) sequentially connected to an output end of the error amplifier (21); a first capacitor (C1) connected between the output end of the error amplifier (21) and the ground; a second capacitor (C2) connected between an output end of the first switch (S1) and the ground; and a third capacitor (C3) connected between an output end of the second switch (S2) and the ground. Phases of switch signals of the first switch (S1) and the second switch (S2) are reversed. An error voltage is obtained by amplifying a difference between a reference voltage and a feedback voltage, a compensation voltage is generated by filtering an error voltage, and a feedback voltage is generated after the compensation voltage is processed by the control module (22), so that a feedback loop is formed, and loop integration is implemented, and a mean value of the feedback voltage equals a reference voltage value. The integrating circuit (2) is simple in structure and high in integration level, configuration of a large filter capacitor (C) is omitted, a peripheral circuit is simplified, system costs are reduced, and the problem of failure caused by eliminating a peripheral filter capacitor (C) is completely eliminated.

Description

积分电路及其积分方法Integrating circuit and its integrating method 技术领域Technical field
本发明涉及集成电路设计领域，特别是涉及一种积分电路及其积分方法。The invention relates to the field of integrated circuit design, in particular to an integrating circuit and its integrating method.
背景技术Background technique
随着LED驱动电路的不断升级换代，***电路的简单化、整体方案的低成本化、高可靠性等已经成为大家一致认可的方向和目标。在LED驱动技术领域中，经常需要一个闭环控制环路，将采样电压的均值稳定在基准电压值，以此控制LED驱动***以预设输出稳定工作。With the continuous upgrading of LED drive circuits, the simplification of peripheral circuits, the cost reduction of the overall scheme, and high reliability have become the direction and goal of everyone's unanimous approval. In the field of LED drive technology, a closed-loop control loop is often required to stabilize the average value of the sampled voltage at the reference voltage value, thereby controlling the LED drive system to work stably with a preset output.
传统的闭环控制环路需要连接一容值较大的滤波电容，由于滤波电容的容值较大，无法集成到芯片内部，因此，滤波电容需要设置在芯片外，因此，需要在芯片上预留管脚，***成本增大(封装成本，***成本)，同时芯片***电路会变得复杂，且***滤波电容会增大闭环控制环路失效的风险。The traditional closed-loop control loop needs to be connected with a filter capacitor with a larger capacitance. Because the capacitance of the filter capacitor is larger, it cannot be integrated into the chip. Therefore, the filter capacitor needs to be set outside the chip, so it needs to be reserved on the chip Pin, the system cost increases (package cost, system cost), at the same time the peripheral circuit of the chip will become complicated, and the peripheral filter capacitor will increase the risk of closed-loop control loop failure.
因此，如何简化芯片***电路、降低成本、降低***滤波电容带来的失效风险，已成为本领域技术人员亟待解决的问题之一。Therefore, how to simplify the peripheral circuit of the chip, reduce the cost, and reduce the risk of failure caused by the peripheral filter capacitor has become one of the problems that those skilled in the art urgently need to solve.
发明内容Summary of the invention
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种积分电路及其积分方法，用于解决现有技术中闭环控制环路的芯片***电路复杂、成本高、失效风险高等问题。In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide an integrating circuit and an integrating method thereof, which are used to solve the problems of complex, high cost and high failure risk of the chip peripheral circuit of the closed loop control loop in the prior art.
为实现上述目的及其他相关目的，本发明提供一种积分电路，所述积分电路至少包括：In order to achieve the above object and other related objects, the present invention provides an integrating circuit, the integrating circuit includes at least:
误差放大器、第一开关、第二开关、第一电容、第二电容、第三电容及控制模块；Error amplifier, first switch, second switch, first capacitor, second capacitor, third capacitor and control module;
所述误差放大器的第一输入端连接一参考电压，第二输入端连接一反馈电压，用于计算所述参考电压与所述反馈电压的差值并放大输出；The first input terminal of the error amplifier is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, which is used to calculate the difference between the reference voltage and the feedback voltage and amplify the output;
所述第一开关的一端连接所述误差放大器的输出端，另一端连接所述第二开关的一端；所述第二开关的另一端连接于所述控制模块的输入端；One end of the first switch is connected to the output end of the error amplifier, and the other end is connected to one end of the second switch; the other end of the second switch is connected to the input end of the control module;
所述控制模块的输出端连接所述误差放大器的第二输入端，为所述误差放大器提供所述反馈电压；The output terminal of the control module is connected to the second input terminal of the error amplifier to provide the feedback voltage for the error amplifier;
所述第一电容的上极板连接所述第一开关的输入端，下极板接地；所述第二电容的上极板连接所述第一开关的输出端，下极板接地；所述第三电容的上极板连接所述第二开关的输出端，下极板接地；The upper plate of the first capacitor is connected to the input of the first switch, and the lower plate is grounded; the upper plate of the second capacitor is connected to the output of the first switch, and the lower plate is grounded; The upper plate of the third capacitor is connected to the output end of the second switch, and the lower plate is grounded;
其中，所述第一开关的开关信号与所述第二开关的开关信号反相。Wherein, the switching signal of the first switch and the switching signal of the second switch are inverted.
可选地，所述第一开关为绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管，所述第二开关为绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管。Optionally, the first switch is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor, and the second switch is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor.
可选地，所述第一开关、所述第二开关、所述第一电容、所述第二电容及所述第三电容集成于芯片内。Optionally, the first switch, the second switch, the first capacitor, the second capacitor, and the third capacitor are integrated in a chip.
为实现上述目的及其他相关目的，本发明提供一种上述积分电路的积分方法，所述积分方法至少包括：In order to achieve the above object and other related objects, the present invention provides an integration method for the above integration circuit. The integration method includes at least:
将参考电压与反馈电压的差值放大得到误差电压，对所述误差电压滤波生成补偿电压，基于所述补偿电压调整得到所述反馈电压，实现环路积分，进而使所述反馈电压的均值等于所述参考电压的值。Amplify the difference between the reference voltage and the feedback voltage to obtain an error voltage, filter the error voltage to generate a compensation voltage, adjust the compensation voltage to obtain the feedback voltage, implement loop integration, and then make the average value of the feedback voltage equal to The value of the reference voltage.
可选地，第一电容滤除所述误差电压的高频成分，第二电容及第三电容滤除所述误差电压的中频成分。Optionally, the first capacitor filters out the high frequency component of the error voltage, and the second capacitor and the third capacitor filter out the intermediate frequency component of the error voltage.
可选地，第一开关导通时，所述误差电压对第二电容充放电，第二开关关断，所述补偿电压不变；Optionally, when the first switch is turned on, the error voltage charges and discharges the second capacitor, the second switch is turned off, and the compensation voltage does not change;
所述第一开关关断时，所述误差电压与所述第二电容断开，所述第二开关导通，所述第二电容对所述第三电容充放电，所述补偿电压随所述第三电容上的电压变化。When the first switch is turned off, the error voltage is disconnected from the second capacitor, the second switch is turned on, the second capacitor charges and discharges the third capacitor, and the compensation voltage varies The voltage on the third capacitor changes.
可选地，所述第一开关、所述第二开关及所述第二电容的等效电阻满足如下关系式：Optionally, the equivalent resistances of the first switch, the second switch, and the second capacitor satisfy the following relationship:
Figure PCTCN2019125012-appb-000001
Figure PCTCN2019125012-appb-000001
其中，R eq为等效电阻，T C为所述第一开关及所述第二开关的开关周期，C 2为所述第二电容的容值。 Where R eq is the equivalent resistance, T C is the switching period of the first switch and the second switch, and C 2 is the capacitance of the second capacitor.
更可选地，所述积分电路的主极点频率满足如下关系式：More optionally, the main pole frequency of the integration circuit satisfies the following relationship:
Figure PCTCN2019125012-appb-000002
Figure PCTCN2019125012-appb-000002
其中，f p为主极点频率，T C为所述第一开关及所述第二开关的开关周期，C 2为所述第二电容的容值，C 3为所述第三电容的容值。 Where f p is the main pole frequency, T C is the switching period of the first switch and the second switch, C 2 is the capacitance of the second capacitor, and C 3 is the capacitance of the third capacitor .
更可选地，通过增大所述第一开关及所述第二开关的开关周期、增大所述第三电容的容值或减小所述第二电容的容值来减小所述积分电路的主极点频率。More optionally, the integral is decreased by increasing the switching period of the first switch and the second switch, increasing the capacitance of the third capacitor, or decreasing the capacitance of the second capacitor The main pole frequency of the circuit.
可选地，当所述反馈电压大于所述参考电压时，基于所述补偿电压调整所述反馈电压逐渐减小；当所述反馈电压小于所述参考电压时，基于所述补偿电压调整所述反馈电压逐渐增 大。Optionally, when the feedback voltage is greater than the reference voltage, adjusting the feedback voltage based on the compensation voltage gradually decreases; when the feedback voltage is less than the reference voltage, adjusting the feedback voltage based on the compensation voltage The feedback voltage gradually increases.
如上所述，本发明的积分电路及其积分方法，具有以下有益效果：As described above, the integration circuit and the integration method of the present invention have the following beneficial effects:
本发明的积分电路及其积分方法利用误差放大器、开关及电容实现积分功能，可大大减小电容的容值，避免电容外置于芯片外部，进而简化芯片***电路、降低***成本及封装成本，并减小失效风险，提升***可靠性。The integration circuit and the integration method of the present invention use an error amplifier, a switch and a capacitor to achieve the integration function, which can greatly reduce the capacitance value of the capacitor and avoid the capacitor from being placed outside the chip, thereby simplifying the chip peripheral circuit and reducing the system cost and packaging cost. And reduce the risk of failure and improve system reliability.
附图说明BRIEF DESCRIPTION
图1显示为本发明的第一种积分电路的结构示意图。FIG. 1 shows a schematic structural diagram of the first integration circuit of the present invention.
图2显示为本发明的第一种积分电路的工作原理示意图。FIG. 2 shows a schematic diagram of the working principle of the first integration circuit of the present invention.
图3显示为本发明的第二种积分电路的结构示意图。FIG. 3 is a schematic structural diagram of a second integration circuit of the present invention.
图4显示为本发明的第二种积分电路的工作原理示意图。FIG. 4 shows a schematic diagram of the working principle of the second integration circuit of the present invention.
元件标号说明Component label description
1                      积分电路1 The integration circuit of the integration circuit
11                     误差放大器11 Error Amplifier
12                     控制模块12 The control module of the control module
2                      积分电路2 Integrating circuit
21                     误差放大器21 Error Amplifier Error Amplifier
22                     控制模块22 The control module of the control module
具体实施方式detailed description
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。The following describes the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present specification. The present invention can also be implemented or applied through different specific embodiments. The details in this specification can also be based on different viewpoints and applications, and various modifications or changes can be made without departing from the spirit of the present invention.
请参阅图1～图4。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图式中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。Please refer to Figure 1 ~ Figure 4. It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, and the diagram only shows the components related to the present invention instead of the number, shape and shape of the components in actual implementation Dimension drawing, the type, number and ratio of each component can be changed at will during its actual implementation, and the component layout type may also be more complicated.
实施例一Example one
如图1所示，本实施例提供一种积分电路1，所述积分电路1包括：As shown in FIG. 1, this embodiment provides an integration circuit 1 that includes:
误差放大器11、滤波电容C及控制模块12。 Error amplifier 11, filter capacitor C and control module 12.
如图1所示，所述误差放大器11的正相输入端连接一参考电压V REF，反相输入端连接所述控制模块12的输出端，所述误差放大器11的输出端连接所述控制模块12的输入端。所述滤波电容C的上极板连接所述误差放大器11的输出端，下极板接地。 As shown in FIG. 1, the non-inverting input terminal of the error amplifier 11 is connected to a reference voltage V REF , the inverting input terminal is connected to the output terminal of the control module 12, and the output terminal of the error amplifier 11 is connected to the control module The input of 12. The upper plate of the filter capacitor C is connected to the output end of the error amplifier 11, and the lower plate is grounded.
需要说明的是，在本实施例中，所述误差放大器11及所述控制模块12集成于芯片内；所述滤波电容C设置于芯片外，通过芯片上的管脚与所述误差放大器11及所述控制模块12连接。It should be noted that, in this embodiment, the error amplifier 11 and the control module 12 are integrated in the chip; the filter capacitor C is provided outside the chip, through the pins on the chip and the error amplifier 11 and The control module 12 is connected.
具体地，所述控制电路12的输出信号作为反馈电压V FB，所述误差放大器11将所述反馈电压V FB与所述参考电压V REF进行差分放大，得到补偿电压V COMP，所述控制电路12根据所述补偿电压V COMP调节所述反馈电压V FB的大小，从而形成一个反馈闭环，实现积分。由于所述滤波电容C的容值比较大，无法集成到芯片中，就只能设置在芯片***，成本高，失效风险大。 Specifically, the output signal of the control circuit 12 is used as a feedback voltage V FB , the error amplifier 11 differentially amplifies the feedback voltage V FB and the reference voltage V REF to obtain a compensation voltage V COMP , the control circuit 12 Adjust the magnitude of the feedback voltage V FB according to the compensation voltage V COMP , thereby forming a feedback closed loop to achieve integration. Since the capacitance value of the filter capacitor C is relatively large and cannot be integrated into the chip, it can only be arranged on the periphery of the chip, which has a high cost and a high risk of failure.
需要说明的是，所述积分电路1可不包括所述控制模块12，所述反馈电压V FB即为所述滤波电容C上的电压，相应地所述反馈电压V FB缓慢跟随参考电压V REF变化，且所述反馈电压均值等于所述参考电压均值。 It should be noted that the integration circuit 1 may not include the control module 12, the feedback voltage V FB is the voltage on the filter capacitor C, and accordingly the feedback voltage V FB slowly follows the reference voltage V REF , And the average value of the feedback voltage is equal to the average value of the reference voltage.
更具体地，假设所述误差放大器11的输出阻抗为R OUT，则可得到所述积分电路1的主极点，满足如下关系式： More specifically, assuming that the output impedance of the error amplifier 11 is R OUT , the main pole of the integration circuit 1 can be obtained, satisfying the following relationship:
Figure PCTCN2019125012-appb-000003
Figure PCTCN2019125012-appb-000003
其中，f p为主极点频率，C为所述滤波电容C的容值。通过增大所述滤波电容C的容值可将所述主极点频率f p降下来，从而实现滤除所述反馈电压V FB中的中频和高频成分，最终得到只含有低频成分且纹波较小的补偿电压V COMP。 Where, f p is the main pole frequency, and C is the capacitance of the filter capacitor C. By increasing the capacitance of the filter capacitor C, the main pole frequency f p can be lowered, so as to filter out the intermediate frequency and high frequency components in the feedback voltage V FB , and finally obtain only the low frequency components and ripple The smaller compensation voltage V COMP .
如图2所示，当所述反馈电压V FB高于所述参考电压V REF电压时，所述补偿电压V COMP降低，进而所述反馈电压V FB降低；当所述反馈电压V FB低于所述参考电压V REF电压时，所述补偿电压V COMP升高，进而所述反馈电压V FB升高，最终使得控制环路达到闭环稳定状态，即所述反馈电压V FB均值等于所述参考电压V REF。 As shown in FIG. 2, when the feedback voltage V FB is higher than the reference voltage V REF voltage, the compensation voltage V COMP decreases, and thus the feedback voltage V FB decreases; when the feedback voltage V FB is lower than When the reference voltage V REF voltage is increased, the compensation voltage V COMP increases, and then the feedback voltage V FB increases, and finally the control loop reaches a closed-loop stable state, that is, the average value of the feedback voltage V FB is equal to the reference Voltage V REF .
实施例二Example 2
如图3所示，本实施例提供一种积分电路2，所述积分电路2包括：As shown in FIG. 3, this embodiment provides an integrating circuit 2, which includes:
误差放大器21、第一开关S1、第二开关S2、第一电容C1、第二电容C2、第三电容C3及控制电路22。The error amplifier 21, the first switch S1, the second switch S2, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the control circuit 22.
如图3所示，所述误差放大器21的第一输入端连接参考电压V REF，第二输入端连接反馈电压V FB，所述误差放大器21计算所述参考电压V REF与所述反馈电压V FB的差值并放大输出。 As shown in FIG. 3, the first input terminal of the error amplifier 21 is connected to the reference voltage V REF and the second input terminal is connected to the feedback voltage V FB . The error amplifier 21 calculates the reference voltage V REF and the feedback voltage V FB difference and enlarge the output.
具体地，在本实施例中，所述误差放大器21的正相输入端接收所述参考电压V REF，反相输入端接收所述反馈电压V FB，在实际应用中，所述误差放大器21的输入端与输入信号可互换连接，通过反相器可调整输入信号的极性，满足本实施例的逻辑关系即可，不以本实施例为限。 Specifically, in this embodiment, the non-inverting input terminal of the error amplifier 21 receives the reference voltage V REF and the inverting input terminal receives the feedback voltage V FB . In practical applications, the error amplifier 21 The input terminal and the input signal can be interchangeably connected, and the polarity of the input signal can be adjusted through the inverter to satisfy the logical relationship of this embodiment, and is not limited to this embodiment.
如图3所示，所述第一开关S1的一端连接所述误差放大器21的输出端，另一端连接所述第二开关S2的一端；所述第二开关S2的另一端连接于所述控制模块22的输入端；所述第一电容C1的上极板连接所述第一开关S1的输入端，下极板接地；所述第二电容C2的上极板连接所述第一开关S1的输出端，下极板接地；所述第三电容C3的上极板连接所述第二开关S2的输出端，下极板接地。As shown in FIG. 3, one end of the first switch S1 is connected to the output end of the error amplifier 21, and the other end is connected to one end of the second switch S2; the other end of the second switch S2 is connected to the control The input end of the module 22; the upper plate of the first capacitor C1 is connected to the input end of the first switch S1, the lower plate is grounded; the upper plate of the second capacitor C2 is connected to the first switch S1 At the output end, the lower plate is grounded; the upper plate of the third capacitor C3 is connected to the output end of the second switch S2, and the lower plate is grounded.
具体地，所述第一开关S1包括但不限于绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管，任意可实现开关功能的器件均适用于本实施例的所述第一开关，不以本实施例为限。所述第二开关S2包括但不限于绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管，任意可实现开关功能的器件均适用于本实施例的所述第二开关，不以本实施例为限。Specifically, the first switch S1 includes but is not limited to an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor. Any device that can realize a switching function is applicable to the first switch in this embodiment. This embodiment is limited. The second switch S2 includes but is not limited to an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor. Any device that can achieve a switching function is applicable to the second switch in this embodiment, and is not implemented in this embodiment. Examples are limited.
具体地，所述第一开关S1的开关电压Sw与所述第二开关S2的开关电压Sw为反信号，即所述第一开关S1导通时所述第二开关S2关断，所述第一开关S1关断时所述第二开关S2导通，同一时间仅一个开关导通。所述第一开关S1与所述第二开关S2的开关电压频率大于所述误差放大器21的输出电压的频率。Specifically, the switching voltage Sw of the first switch S1 and the switching voltage Sw of the second switch S2 are inverse signals, that is, the second switch S2 is turned off when the first switch S1 is turned on, and the first When one switch S1 is turned off, the second switch S2 is turned on, and only one switch is turned on at a time. The switching voltage frequency of the first switch S1 and the second switch S2 is greater than the frequency of the output voltage of the error amplifier 21.
具体地，所述第一电容C1的容值较小，可集成在芯片内，计算得到所述第一电容C1所在级滤波单元的极点满足如下关系式：Specifically, the capacitance of the first capacitor C1 is relatively small, and can be integrated into the chip, and the pole of the filter unit where the first capacitor C1 is located is calculated to satisfy the following relationship:
Figure PCTCN2019125012-appb-000004
Figure PCTCN2019125012-appb-000004
其中，f p1为所述第一电容C1所在级滤波单元的极点频率，R OUT为所述误差放大器11的输出阻抗，C 1为所述第一电容C1的容值。所述极点频率f p1设置较大，只能将周期性反馈电压V FB的高频成分滤掉，所述第一电容C1的输出电压V1仍然含有低频和中频成分，所以 纹波较大，需要进行后级处理。 Where, f p1 is the pole frequency of the filter unit where the first capacitor C1 is located, R OUT is the output impedance of the error amplifier 11, and C 1 is the capacitance of the first capacitor C1. The pole frequency f p1 is set large, and only the high-frequency components of the periodic feedback voltage V FB can be filtered out. The output voltage V1 of the first capacitor C1 still contains low-frequency and intermediate-frequency components, so the ripple is large and needs to be Perform post-processing.
具体地，所述第一开关S1、所述第二开关S2及所述第二电容C2可等效为电阻，满足如下关系式：Specifically, the first switch S1, the second switch S2, and the second capacitor C2 may be equivalent to resistances, satisfying the following relationship:
Figure PCTCN2019125012-appb-000005
Figure PCTCN2019125012-appb-000005
其中，R eq为所述第一开关S1、所述第二开关S2及所述第二电容C2的等效电阻，T C为所述第一开关S1及所述第二开关S2的开关周期，C 2为所述第二电容C2的容值。通过增大所述第一开关S1及所述第二开关S2的开关周期T C可增大所述等效电阻R eq的值，在保证可靠性和精度的前提下，所述等效电阻R eq的值可以做得很大，可根据需要设定所述等效电阻R eq的值，在此不一一赘述。同时所述第二电容C2的容值也可以相应减小，在此不一一赘述。 Where R eq is the equivalent resistance of the first switch S1, the second switch S2 and the second capacitor C2, and T C is the switching period of the first switch S1 and the second switch S2, C 2 is the capacitance of the second capacitor C2. The value of the equivalent resistance R eq can be increased by increasing the switching period T C of the first switch S1 and the second switch S2. On the premise of ensuring reliability and accuracy, the equivalent resistance R The value of eq can be made very large, and the value of the equivalent resistance R eq can be set as needed, which will not be repeated here. At the same time, the capacitance of the second capacitor C2 can also be reduced accordingly, which will not be repeated here.
具体地，所述第一开关S1、所述第二开关S2、所述第二电容C2与所述第三电容C3构成低通滤波器，其主极点频率满足如下关系式：Specifically, the first switch S1, the second switch S2, the second capacitor C2 and the third capacitor C3 form a low-pass filter, and the main pole frequency satisfies the following relationship:
Figure PCTCN2019125012-appb-000006
Figure PCTCN2019125012-appb-000006
所述第一开关S1、所述第二开关S2、所述第二电容C2与所述第三电容C3将所述第一电容C1的输出电压V1中的中频成分滤除，使得所述控制模块22输入端的补偿电压V COMP只包含低频成分，纹波较小。由于所述第一开关S1、所述第二开关S2及所述第二电容C2的等效电阻R eq可以做得很大，则相应地所述第二电容C2可以减小容值(所述第二电容C2及所述第三电容C3的容值以能集成到芯片中为准，不一一具体限定)，因此，所述第一开关S1、所述第二开关S2、所述第二电容C2及所述第三电容C3均可集成于芯片内，大大简化芯片***电路，增加可靠性。在所述第一开关S1、所述第二开关S2、所述第一电容C1、所述第二电容C2及所述第三电容C3均集成于芯片内的情况下，基于上式(4)可知，通过增大所述第一开关S1及所述第二开关S2的开关周期T C、增大所述第三电容C3的容值或减小所述第二电容C2的容值可减小所述积分电路2的主极点频率f p2。 The first switch S1, the second switch S2, the second capacitor C2, and the third capacitor C3 filter out the intermediate frequency component in the output voltage V1 of the first capacitor C1, so that the control module 22 The compensation voltage V COMP at the input contains only low-frequency components, and the ripple is small. Since the equivalent resistance R eq of the first switch S1, the second switch S2 and the second capacitor C2 can be made very large, the second capacitor C2 can correspondingly reduce the capacitance (the The capacitances of the second capacitor C2 and the third capacitor C3 are subject to being integrated into the chip, and are not specifically limited.) Therefore, the first switch S1, the second switch S2, and the second Both the capacitor C2 and the third capacitor C3 can be integrated into the chip, which greatly simplifies the peripheral circuit of the chip and increases reliability. When the first switch S1, the second switch S2, the first capacitor C1, the second capacitor C2, and the third capacitor C3 are all integrated in the chip, based on the above formula (4) It can be seen that by increasing the switching period T C of the first switch S1 and the second switch S2, increasing the capacitance of the third capacitor C3 or decreasing the capacitance of the second capacitor C2 The main pole frequency f p2 of the integration circuit 2.
如图3所示，所述控制模块22接收所述补偿电压V COMP，基于所述补偿电压V COMP对所述反馈电压V FB进行调整。 As shown in FIG. 3, the control module 22 receives the compensation voltage V COMP and adjusts the feedback voltage V FB based on the compensation voltage V COMP .
具体地，在本实施例中，所述控制模块22的输入端连接于所述第二开关S2的输出端，输出端连接所述误差放大器21的反相输入端。所述控制模块22包括但不限于LED的驱动控制模块，在本实施例中，所述控制模块22输出信号为LED输出电流的采样电压V CS，基于 所述补偿电压V COMP控制功率开关管，进而实现对输出电流的控制。在实际应用中，任意通过反馈环路控制输出的结构均适用，不以本实施例为限。 Specifically, in this embodiment, the input terminal of the control module 22 is connected to the output terminal of the second switch S2, and the output terminal is connected to the inverting input terminal of the error amplifier 21. The control module 22 includes, but is not limited to, an LED drive control module. In this embodiment, the output signal of the control module 22 is the sampling voltage V CS of the LED output current, and the power switching tube is controlled based on the compensation voltage V COMP . Then realize the control of the output current. In practical applications, any structure that controls the output through the feedback loop is applicable, and is not limited to this embodiment.
需要说明的是，所述积分电路2可不包括所述控制模块22，所述第二开关S2的输出端连接于所述误差放大器21的第二输入端，为所述误差放大器21提供所述反馈电压V FB，所述反馈电压V FB即为所述补偿电压V COMP，所述反馈电压V FB缓慢跟随所述参考电压V REF变化，且所述反馈电压V FB均值等于所述参考电压V REF的均值。 It should be noted that the integrating circuit 2 may not include the control module 22, and the output terminal of the second switch S2 is connected to the second input terminal of the error amplifier 21 to provide the feedback to the error amplifier 21 Voltage V FB , the feedback voltage V FB is the compensation voltage V COMP , the feedback voltage V FB slowly follows the reference voltage V REF , and the average value of the feedback voltage V FB is equal to the reference voltage V REF Of the mean.
所述积分电路2的工作原理如下：The working principle of the integration circuit 2 is as follows:
如图3及图4所示，所述误差放大器21将参考电压V REF与反馈电压V FB的差值放大得到误差电压V1，对所述误差电压V1滤波生成补偿电压V COMP，基于所述补偿电压V COMP调节所述反馈电压V FB，形成反馈环路，进而实现积分。 As shown in FIGS. 3 and 4, the error amplifier 21 amplifies the difference between the reference voltage V REF and the feedback voltage V FB to obtain an error voltage V1, and filters the error voltage V1 to generate a compensation voltage V COMP based on the compensation The voltage V COMP regulates the feedback voltage V FB to form a feedback loop, thereby achieving integration.
具体地，所述误差放大器21输出所述参考电压V REF与所述反馈电压V FB的误差电压V1。所述误差电压V1经所述第一电容C1滤除高频成分，然后经过所述第一开关S1、所述第二开关S2、所述第二电容C2及所述第三电容C3构成的低通滤波器滤除中频成分，只剩下低频成分，得到纹波较小的所述补偿电压V COMP。基于所述补偿电压V COMP调整得到所述反馈电压V FB，进而使所述反馈电压V FB的均值等于所述参考电压V REF。 Specifically, the error amplifier 21 outputs an error voltage V1 between the reference voltage V REF and the feedback voltage V FB . The error voltage V1 is filtered by the first capacitor C1 to remove high-frequency components, and then passes through the first switch S1, the second switch S2, the second capacitor C2 and the third capacitor C3. The pass filter filters out the intermediate frequency component, leaving only the low frequency component to obtain the compensation voltage V COMP with a small ripple. The feedback voltage V FB is adjusted based on the compensation voltage V COMP , and then the average value of the feedback voltage V FB is equal to the reference voltage V REF .
更具体地，所述第一开关S1与所述第二开关S2的开关由逻辑状态完全相反的时钟电压控制。More specifically, the switches of the first switch S1 and the second switch S2 are controlled by clock voltages whose logic states are completely opposite.
在T 1阶段，所述第一开关S1闭合导通，所述误差电压V1对所述第二电容C2进行充放电，当所述误差电压V1大于所述第二电容C2上的电压时，所述误差电压V1对所述第二电容C2充电，所述第一开关S1的输出电压V2升高；当所述误差电压V1小于所述第二电容C2上的电压时，所述误差电压V1对所述第二电容C2放电，所述第一开关S1的输出电压V2降低。此时，所述第二开关S2关断，所述第三电容C3上的电荷保持不变，所述补偿电压V COMP保持不变。 At stage T 1, the first switch S1 is closed is turned on, the error voltage V1 to the second capacitor C2 is charged and discharged when the error voltage V1 is greater than the voltage on the second capacitor C2 when the The error voltage V1 charges the second capacitor C2, and the output voltage V2 of the first switch S1 rises; when the error voltage V1 is less than the voltage on the second capacitor C2, the error voltage V1 pairs The second capacitor C2 is discharged, and the output voltage V2 of the first switch S1 decreases. At this time, the second switch S2 is turned off, the charge on the third capacitor C3 remains unchanged, and the compensation voltage V COMP remains unchanged.
在T 2阶段，所述第一开关S1关断，所述误差电压V1与所述第二电容C2断开。此时，所述第二开关S2闭合导通，所述第二电容C2对所述第三电容C3进行充放电，从而提升或降低所述补偿电压V COMP的电压值。当所述第二电容C2上的电压大于所述第三电容C3上的电压时，所述第二电容C2对所述第三电容C3充电，所述补偿电压V COMP随之增大；当所述第二电容C2上的电压小于所述第三电容C3上的电压时，所述第二电容C2对所述第三电容C3放电，所述补偿电压V COMP随之减小。所述补偿电压V COMP以所述第一开关S1及所述第二开关S2的开关电压周期为单位呈阶梯状变化(上升或下降)。 In the T 2 stage, the first switch S1 is turned off, and the error voltage V1 is disconnected from the second capacitor C2. At this time, the second switch S2 is closed and turned on, and the second capacitor C2 charges and discharges the third capacitor C3, thereby increasing or decreasing the voltage value of the compensation voltage V COMP . When the voltage on the second capacitor C2 is greater than the voltage on the third capacitor C3, the second capacitor C2 charges the third capacitor C3, and the compensation voltage V COMP increases accordingly. When the voltage on the second capacitor C2 is less than the voltage on the third capacitor C3, the second capacitor C2 discharges the third capacitor C3, and the compensation voltage V COMP decreases accordingly. The compensation voltage V COMP changes stepwise (rising or falling) in units of the switching voltage periods of the first switch S1 and the second switch S2.
更具体地，当所述反馈电压V FB小于所述参考电压V REF时，基于所述补偿电压V COMP调整所述反馈电压V FB逐渐增大；当所述反馈电压V FB大于所述参考电压V REF时，基于所述补偿电压V COMP调整所述反馈电压V FB逐渐减小；进而使得所述反馈电压V FB的均值等于所述参考电压V REF。 More specifically, when the feedback voltage V FB is less than the reference voltage V REF , the feedback voltage V FB is adjusted based on the compensation voltage V COMP to gradually increase; when the feedback voltage V FB is greater than the reference voltage When V REF , the feedback voltage V FB is adjusted based on the compensation voltage V COMP to gradually decrease; thereby making the average value of the feedback voltage V FB equal to the reference voltage V REF .
本发明的积分电路将所有器件均集成到芯片内部，从而无需引出滤波电容管脚，无需外置电容；方案结构简单且集成度更高，特别地，可免去配置大的滤波电容，实现了***电路的简化，降低了***成本，彻底消除***滤波电容造成的失效问题。The integration circuit of the present invention integrates all the devices into the chip, so that there is no need to lead out the filter capacitor pins and no external capacitors; the solution structure is simple and the integration is higher. In particular, the configuration of a large filter capacitor can be eliminated, which realizes The simplification of the peripheral circuit reduces the system cost and completely eliminates the failure problem caused by the peripheral filter capacitor.
综上所述，本发明提供一种积分电路及其积分方法，所述积分电路包括：误差放大器、第一开关、第二开关、第一电容、第二电容、第三电容及控制模块；所述误差放大器的第一输入端连接一参考电压，第二输入端连接一反馈电压，用于计算所述参考电压与所述反馈电压的差值并放大输出；所述第一开关的一端连接所述误差放大器的输出端，另一端连接所述第二开关的一端；所述第二开关的另一端连接于所述控制模块的输入端；所述控制模块的输出端连接所述误差放大器的第二输入端，为所述误差放大器提供所述反馈电压；所述第一电容的上极板连接所述第一开关的输入端，下极板接地；所述第二电容的上极板连接所述第一开关的输出端，下极板接地；所述第三电容的上极板连接所述第二开关的输出端，下极板接地；其中，所述第一开关的开关信号与所述第二开关的开关信号反相。将参考电压与反馈电压的差值放大得到误差电压，对所述误差电压滤波生成补偿电压，基于所述补偿电压调整得到所述反馈电压，实现环路积分，进而使所述反馈电压的均值等于所述参考电压的值。本发明结构简单且集成度更高，且可免去配置大的滤波电容，实现了***电路的简化，降低了***成本，彻底消除***滤波电容造成的失效问题。所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。In summary, the present invention provides an integration circuit and an integration method thereof. The integration circuit includes: an error amplifier, a first switch, a second switch, a first capacitor, a second capacitor, a third capacitor, and a control module; The first input terminal of the error amplifier is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, which is used to calculate the difference between the reference voltage and the feedback voltage and amplify the output; one end of the first switch is connected to the The output end of the error amplifier, the other end is connected to one end of the second switch; the other end of the second switch is connected to the input end of the control module; the output end of the control module is connected to the first end of the error amplifier Two input terminals provide the feedback voltage for the error amplifier; the upper plate of the first capacitor is connected to the input terminal of the first switch, the lower plate is grounded; the upper plate of the second capacitor is connected to the The output terminal of the first switch, the lower plate is grounded; the upper plate of the third capacitor is connected to the output of the second switch, and the lower plate is grounded; wherein, the switch signal of the first switch is connected to the The switching signal of the second switch is inverted. Amplify the difference between the reference voltage and the feedback voltage to obtain an error voltage, filter the error voltage to generate a compensation voltage, adjust the compensation voltage based on the compensation voltage to obtain the feedback voltage, implement loop integration, and then make the average value of the feedback voltage equal to The value of the reference voltage. The invention has a simple structure and higher integration, and can dispense with the configuration of a large filter capacitor, which simplifies the peripheral circuit, reduces the system cost, and completely eliminates the failure problem caused by the peripheral filter capacitor. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。The above-mentioned embodiments only exemplarily illustrate the principle and efficacy of the present invention, and are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims (10)

  1. 一种积分电路，其特征在于，所述积分电路至少包括：An integrating circuit, characterized in that the integrating circuit includes at least:
    误差放大器、第一开关、第二开关、第一电容、第二电容、第三电容及控制模块；Error amplifier, first switch, second switch, first capacitor, second capacitor, third capacitor and control module;
    所述误差放大器的第一输入端连接一参考电压，第二输入端连接一反馈电压，用于计算所述参考电压与所述反馈电压的差值并放大输出；The first input terminal of the error amplifier is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, which is used to calculate the difference between the reference voltage and the feedback voltage and amplify the output;
    所述第一开关的一端连接所述误差放大器的输出端，另一端连接所述第二开关的一端；所述第二开关的另一端连接于所述控制模块的输入端；One end of the first switch is connected to the output end of the error amplifier, and the other end is connected to one end of the second switch; the other end of the second switch is connected to the input end of the control module;
    所述控制模块的输出端连接所述误差放大器的第二输入端，为所述误差放大器提供所述反馈电压；The output terminal of the control module is connected to the second input terminal of the error amplifier to provide the feedback voltage for the error amplifier;
    所述第一电容的上极板连接所述第一开关的输入端，下极板接地；所述第二电容的上极板连接所述第一开关的输出端，下极板接地；所述第三电容的上极板连接所述第二开关的输出端，下极板接地；The upper plate of the first capacitor is connected to the input of the first switch, and the lower plate is grounded; the upper plate of the second capacitor is connected to the output of the first switch, and the lower plate is grounded; The upper plate of the third capacitor is connected to the output end of the second switch, and the lower plate is grounded;
    其中，所述第一开关的开关信号与所述第二开关的开关信号反相。Wherein, the switching signal of the first switch and the switching signal of the second switch are inverted.
  2. 根据权利要求1所述的积分电路，其特征在于：所述第一开关为绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管，所述第二开关为绝缘栅双极型晶体管或金属-氧化物半导体场效应晶体管。The integrating circuit according to claim 1, wherein the first switch is an insulated gate bipolar transistor or a metal-oxide semiconductor field effect transistor, and the second switch is an insulated gate bipolar transistor or a metal -Oxide semiconductor field effect transistor.
  3. 根据权利要求1所述的积分电路，其特征在于：所述第一开关、所述第二开关、所述第一电容、所述第二电容及所述第三电容集成于芯片内。The integrating circuit according to claim 1, wherein the first switch, the second switch, the first capacitor, the second capacitor, and the third capacitor are integrated in a chip.
  4. 一种如权利要求1～3任意一项所述的积分电路的积分方法，其特征在于，所述积分方法至少包括：An integration method for an integration circuit according to any one of claims 1 to 3, wherein the integration method includes at least:
    将参考电压与反馈电压的差值放大得到误差电压，对所述误差电压滤波生成补偿电压，基于所述补偿电压调整得到所述反馈电压，实现环路积分，进而使所述反馈电压的均值等于所述参考电压的值。Amplify the difference between the reference voltage and the feedback voltage to obtain an error voltage, filter the error voltage to generate a compensation voltage, adjust the compensation voltage to obtain the feedback voltage, implement loop integration, and then make the average value of the feedback voltage equal to The value of the reference voltage.
  5. 根据权利要求4所述的积分方法，其特征在于：第一电容滤除所述误差电压的高频成分，第二电容及第三电容滤除所述误差电压的中频成分。The integration method according to claim 4, wherein the first capacitor filters out the high frequency component of the error voltage, and the second capacitor and the third capacitor filter out the intermediate frequency component of the error voltage.
  6. 根据权利要求4所述的积分方法，其特征在于：The integration method according to claim 4, characterized in that:
    第一开关导通时，所述误差电压对第二电容充放电，第二开关关断，所述补偿电压 不变；When the first switch is turned on, the error voltage charges and discharges the second capacitor, the second switch is turned off, and the compensation voltage does not change;
    所述第一开关关断时，所述误差电压与所述第二电容断开，所述第二开关导通，所述第二电容对所述第三电容充放电，所述补偿电压随所述第三电容上的电压变化。When the first switch is turned off, the error voltage is disconnected from the second capacitor, the second switch is turned on, the second capacitor charges and discharges the third capacitor, and the compensation voltage varies The voltage on the third capacitor changes.
  7. 根据权利要求4所述的积分方法，其特征在于：所述第一开关、所述第二开关及所述第二电容的等效电阻满足如下关系式：The integration method according to claim 4, wherein the equivalent resistances of the first switch, the second switch, and the second capacitor satisfy the following relationship:
    Figure PCTCN2019125012-appb-100001
    Figure PCTCN2019125012-appb-100001
    其中，R eq为等效电阻，T C为所述第一开关及所述第二开关的开关周期，C 2为所述第二电容的容值。 Where R eq is the equivalent resistance, T C is the switching period of the first switch and the second switch, and C 2 is the capacitance of the second capacitor.
  8. 根据权利要求7所述的积分方法，其特征在于：所述积分电路的主极点频率满足如下关系式：The integration method according to claim 7, wherein the main pole frequency of the integration circuit satisfies the following relationship:
    Figure PCTCN2019125012-appb-100002
    Figure PCTCN2019125012-appb-100002
    其中，f p为主极点频率，T C为所述第一开关及所述第二开关的开关周期，C 2为所述第二电容的容值，C 3为所述第三电容的容值。 Where f p is the main pole frequency, T C is the switching period of the first switch and the second switch, C 2 is the capacitance of the second capacitor, and C 3 is the capacitance of the third capacitor .
  9. 根据权利要求8所述的积分方法，其特征在于：通过增大所述第一开关及所述第二开关的开关周期、增大所述第三电容的容值或减小所述第二电容的容值来减小所述积分电路的主极点频率。The integration method according to claim 8, characterized by increasing the switching period of the first switch and the second switch, increasing the capacitance of the third capacitor, or decreasing the second capacitor To reduce the main pole frequency of the integrating circuit.
  10. 根据权利要求4所述的积分方法，其特征在于：当所述反馈电压大于所述参考电压时，基于所述补偿电压调整所述反馈电压逐渐减小；当所述反馈电压小于所述参考电压时，基于所述补偿电压调整所述反馈电压逐渐增大。The integration method according to claim 4, wherein: when the feedback voltage is greater than the reference voltage, the feedback voltage is adjusted to gradually decrease based on the compensation voltage; when the feedback voltage is less than the reference voltage At this time, the feedback voltage is adjusted to gradually increase based on the compensation voltage.
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