WO2020113402A1 - Combined soft-start circuit, combined soft-start chip and electronic device - Google Patents

Combined soft-start circuit, combined soft-start chip and electronic device Download PDF

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Publication number
WO2020113402A1
WO2020113402A1 PCT/CN2018/119067 CN2018119067W WO2020113402A1 WO 2020113402 A1 WO2020113402 A1 WO 2020113402A1 CN 2018119067 W CN2018119067 W CN 2018119067W WO 2020113402 A1 WO2020113402 A1 WO 2020113402A1
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mos tube
output voltage
gate
terminal
input
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PCT/CN2018/119067
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French (fr)
Chinese (zh)
Inventor
王丁丁
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华为技术有限公司
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Priority to PCT/CN2018/119067 priority Critical patent/WO2020113402A1/en
Publication of WO2020113402A1 publication Critical patent/WO2020113402A1/en

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

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  • the present application relates to the field of circuits, in particular to a combined slow-start circuit, combined slow-start chip and electronic equipment.
  • the combined slow start circuit is a very common circuit in electronic equipment that needs to be hot swapped.
  • the combined slow start circuit includes multiple functions. The first is to combine the input multiple power supplies into one output; the second is to perform hot plug When pulling out, slowly control the starting process of the output power voltage to reduce the impact on the input power bus; the third is the current limit, through the current detection channel, if the current exceeds the threshold for a certain period of time, the control is turned off, so as to protect the superior power supply and the current The purpose of the board circuit.
  • the combined slow start circuit of the existing solution is shown in FIG. 1, the combined slow start circuit includes at least two power sources V1 and V2, a combined slow start chip IC1, and three metal oxide semiconductors semiconductor (MOS) transistors N1, N2 and N3, output Vout and so on.
  • MOS metal oxide semiconductors semiconductor
  • V1 is connected to the source of N1, the gate of N1 is connected to the OG1 pin of IC1, V2 is connected to the source of N2, the gate of N1 is connected to the OG2 pin of IC1, and the drain of N1 is connected to the drain of N2 ,
  • the combined circuit is connected to the drain of N3, the gate of N3 is connected to the GATE pin of IC1, the GATE pin can be understood as the control terminal of IC1 controlling N3, and the source of N3 is connected to the output terminal Vout.
  • the rate of rise of the output voltage Vout is controlled by controlling the rate of rise of the gate voltage of N3, thereby controlling the impact on the input bus and reducing the impact on the input power bus.
  • the existing implementation is basically a transparent transmission of the input voltage, and the input voltage will be transmitted to the next level within the design range of the chip. Therefore, if there is a surge shock at the upper stage, that is, an impulse voltage that exceeds the stable voltage instantaneously, the impulse voltage is transmitted to the next stage, and all power supply designs of the latter stage must meet the requirements of the highest voltage of the upper stage and adopt a relatively high voltage process . For example, if the power supply is output to multiple devices, the multiple devices need to withstand high voltage.
  • the chip with high voltage process has the disadvantages of higher cost and lower efficiency.
  • the embodiments of the present application provide a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of subsequent equipment using the combined slow-start circuit .
  • a combined slow start circuit of the first aspect of the present application includes: at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow start chip and an output voltage terminal; wherein, the combined slow start chip Also includes a feedback circuit;
  • the output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin of the combined slow-start chip, and the source of the first mos tube outputs the output voltage
  • the input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
  • the output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
  • the control voltage output by the feedback circuit is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is not fully turned on.
  • the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the grid of the first mos tube to control the incomplete first mos tube Turn on or off. Therefore, the voltage output from the output voltage terminal also decreases. Therefore, when there is a surge in the input voltage, the feedback circuit controls the incomplete conduction or cut-off of the first mos tube, so that the output voltage of the source of the first mos tube is reduced, so the output voltage is reduced, and the surge impact can be suppressed.
  • the feedback circuit may include an operational amplifier and a second mos tube
  • the non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the second mos tube is grounded.
  • the output voltage when the output voltage is too high, it is fed back to the gate of the second mos tube through the operational amplifier, thereby controlling the conduction of the second mos tube, and the source of the second mos tube is grounded. Therefore, it is equivalent to Ground the grid of the first mos tube.
  • the voltage of the grid of the first mos tube is reduced, so that the first mos tube is not fully turned on or off, thereby reducing the voltage output from the source of the first mos tube. Therefore, the output voltage is reduced, and surge surge can be suppressed.
  • the combined slow start circuit may further include: a first resistor and a second resistor;
  • the output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  • the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of the first resistor and the second resistor, and the divided voltage can be input to the operational amplifier through the two resistors In it, the input of the feedback circuit is realized, so as to control the on and off of the first mos tube, and then the output voltage of the output voltage terminal.
  • the at least one input power supply includes a first input power supply and a second input power supply
  • the combined slow-start circuit further includes a third mos tube and a fourth mos tube
  • the output end of the first input power supply is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin of the combined slow-start chip, and the drain of the third mos tube is connected to the The drain of the first mos tube;
  • the output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin of the combined slow-start chip, and the drain of the fourth mos tube is connected to the The drain of the first mos tube.
  • the second control pin and the third control pin may be used to control the conduction or cut-off of the second mos tube and the third mos tube. Therefore, it is avoided that the output voltage of the first input power supply or the second input power supply is too large, which may cause component loss in the circuit.
  • the combined slow-start circuit further includes a first capacitor, one end of the first capacitor is connected to the output voltage terminal, and the other end of the capacitor is grounded.
  • the combined slow start circuit further includes a second capacitor and a third resistor
  • One end of the second capacitor is connected to the gate of the first mos tube, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.
  • the delay control of the first mos tube is realized to achieve the effect of slow start.
  • the combined slow start circuit further includes a fourth resistor
  • One end of the fourth resistor is connected to the drain of the first mos tube, and the other end of the fourth resistor is connected to the drain of the second mos tube and the drain of the third mos tube.
  • the second aspect of the present application provides a combined slow-start chip applied to a combined slow-start circuit.
  • the combined slow-start circuit includes at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow-start chip and an output At the voltage end, the combined slow-start chip includes a feedback circuit and a first control pin;
  • the output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin, and the source of the first mos tube is the output voltage terminal;
  • the input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
  • the output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
  • the control voltage is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is turned off.
  • the feedback circuit includes an operational amplifier and a second mos tube
  • the non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the fourth mos tube is grounded.
  • the combined slow start circuit further includes: a first resistor and a second resistor;
  • the output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  • the at least one input power supply includes a first input power supply and a second input power supply
  • the combined slow-start circuit may further include a third mos tube and a fourth mos tube.
  • the slow start chip also includes a second control pin and a third control pin;
  • the output end of the first input power source is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin, and the drain of the third mos tube is connected to the drain of the first mos tube pole;
  • the output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin, and the drain of the fourth mos tube is connected to the drain of the first mos tube pole.
  • a third aspect of the present application provides an electronic device.
  • the electronic device includes the combined slow-start circuit as in any one of the foregoing embodiments of the first aspect.
  • a fourth aspect of the present application provides an electronic device, characterized in that the electronic device includes the combined slow-start chip in any embodiment of the foregoing second aspect.
  • the embodiment of the present application when the input voltage higher than the threshold value is input, the control voltage output by the feedback circuit is used to control the input voltage of the gate of the first mos tube to decrease, thereby making the first A MOS tube is not fully turned on or off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, the embodiment of the present application controls the output voltage within a certain range by adding a feedback circuit to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-voltage resistant process, without the need for excessive high-voltage resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
  • FIG. 1 is a schematic diagram of an embodiment of a combined slow start circuit in an existing solution
  • FIG. 2 is a schematic diagram of an embodiment of a combined slow start circuit provided in an embodiment of the present application
  • FIG. 3 is a schematic diagram of another embodiment of a combined slow start circuit provided in an embodiment of the present application
  • 5 is a schematic diagram of the control voltage of the combined slow start circuit provided in the embodiment of the present application.
  • the application provides a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of using the combined slow-start circuit.
  • the combined slow-start chip provided in the embodiments of the present application can be applied to a combined slow-start circuit, and the combined slow-start circuit or the combined slow-start chip can also be applied to various electronic devices, such as mobile phones, routers, etc. .
  • the combined slow-start circuit and the combined slow-start chip provided in the embodiments of the present application will be described below, please refer to FIG. 2, the combined slow-start circuit provided in the embodiments of the present application.
  • the combined slow-start circuit includes at least one input power supply, a first mos tube N1, a combined slow-start chip IC, and an output voltage terminal Vout; wherein, the combined slow-start chip further includes a feedback circuit.
  • the at least one input power supply may include one or more input power supplies, and the plurality of input power supplies are two or more.
  • the following uses two input power sources V1 and V2 as an example for description.
  • the first mos tube N1 is described by taking an N-Metal-Oxide-Semiconductor (NMOS) as an example, and the first mos tube may also be a P-Metal-Oxide-Semiconductor , PMOS), which can be adjusted according to the actual application scenario.
  • NMOS N-Metal-Oxide-Semiconductor
  • PMOS P-Metal-Oxide-Semiconductor
  • the output terminal of the input power supply V1 After the output terminal of the input power supply V1 is combined with the output terminal of V2, it is connected to the drain of N1, and the source of N1 is connected to the output voltage terminal.
  • the output voltage terminal outputs the output voltage of the combined slow-start circuit.
  • the gate of N1 is connected to the first control pin of the combined slow start chip, the first control pin is connected to the output terminal of the feedback circuit, and the input terminal of the feedback circuit is connected to the output voltage terminal.
  • the integrated slow start chip adds a pin, namely the SPE pin, the input terminal of the feedback circuit is the SPE pin of the combined slow start chip, and the output end of the feedback circuit is connected to the first of the combined slow start chip
  • the control pin is the GATE pin in Figure 2.
  • the output voltage at the output voltage terminal passes through the input value feedback circuit of the SPE pin.
  • the feedback circuit obtains a control voltage according to the voltage output from the output voltage terminal, and inputs it to the gate of N1 through the GATE pin to control the turning on or off of N1.
  • the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the gate of N1, thereby controlling N1 to not be fully turned on or off To reduce the output voltage at the output voltage end.
  • the combined slow-start chip in the embodiment of the present application may include other pins (not shown in the figure) in addition to the aforementioned GATE pins and SPE pins, for example, power pins and ground pins Wait, it can be adjusted according to the actual application scenario.
  • the control voltage output by the feedback circuit controls the input voltage of the gate of the first mos tube to decrease, so that the first mos tube is not fully turned on or Cut off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, in the embodiment of the present application, by adding a feedback circuit, the output voltage is controlled within a certain range to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-pressure-resistant process, without the need for excessive high-pressure-resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
  • the two power sources V1 and V2 are still used as an example for description.
  • the feedback circuit includes an operational amplifier F1 and a second mos tube N2.
  • N2 may be NMOS or PMOS. Here, only NMOS will be used as an example for description. When N2 is a PMOS, the connection structure is similar to NMOS, and will not be repeated here.
  • the non-inverting input end of F1 is connected to the SPE pin, the SPE pin is connected to the output voltage end, the inverting input end of F1 inputs the reference voltage Vi, and the output end of F1 is connected to the gate of N2.
  • the source of N2 is grounded, and the drain of N2 is connected to the GATE terminal, which is the first control terminal.
  • the non-inverting input terminal of F1 When the non-inverting input terminal of F1 receives the voltage input from the output voltage terminal, the voltage is compared with the reference voltage Vi, and an amplification operation is performed to output to the gate of N2, thereby controlling the cut-off or conduction of N2.
  • the output voltage at the output voltage terminal increases and is fed back to the non-inverting input terminal of the operational amplifier F1 through the SPE pin. If the output voltage is too high, the output voltage of the operational amplifier F1 also increases after amplification, and then the output voltage of F1 Feedback to the gate of N2, when higher than the turn-on voltage of N2, N2 is turned on.
  • N1 is turned off, the output voltage at the output voltage terminal is lowered, which is fed back to the operational amplifier F1 to reduce the output voltage of F1.
  • F1 is fed back to the operational amplifier F1 to reduce the output voltage of F1.
  • N2 is turned off and the current source inside the chip slowly turns on to output current to N1 Of the gate, thereby controlling N1 to turn on. Therefore, in the embodiment of the present application, a feedback circuit is used to feedback the output voltage at the output voltage terminal in real time to control the on or off of N1, so that the output voltage at the output voltage terminal is controlled within a preset range.
  • a current source Is is also provided inside the combined slow-start chip, and one end of the Is is connected to the GATE pin.
  • N2 When N2 is turned off, the output current of Is is turned on to the gate of N1, and the voltage input to the gate of N1 is higher than the turn-on voltage of N1, thereby turning on N1. Therefore, when the output voltage at the output voltage terminal is within the normal voltage range, N2 is turned off and N1 is turned on. Thus, the output voltage is stably output.
  • the combined slow start circuit further includes a first resistor R1 and a second resistor R2.
  • the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of R1 and R2, and the divided voltage is input to the SPE pin through two resistors to implement a feedback circuit To control the turn-on and turn-off of N1, and then the output voltage at the output voltage terminal.
  • the combined slow start circuit may further include a first capacitor C1.
  • One end of the first capacitor C1 is connected to the source of N1, and the other end of C2 is grounded. To filter the output voltage to make the output voltage more stable.
  • the combined slow start circuit may further include a second capacitor C2 and a third resistor R3.
  • One end of C2 is connected to the gate of N1, the other end of C2 is connected to one end of R3, and the other end of R3 is grounded.
  • the delay between the charging and discharging of C2 may be used to realize the delay of controlling N1, and thus the slow start.
  • a third mos tube N3 and a fourth mos tube N4 may also be included between V1, V2, and N1.
  • the input of V1 is connected to the source of N3, the gate of N3 is connected to the second control pin IN2 of the combined slow-start chip, and the drain of N3 is connected to the drain of N1.
  • the input of V2 is connected to the source of N4, the gate of N4 is connected to the third control pin IN3 of the combined slow-start chip, and the drain of N4 is connected to the drain of N1.
  • N1, N2, N3, and N4 may be NMOS, or one or more of them may be PMOS, and the connection structure thereof is combined with the foregoing combination of FIG. 2 or FIG. 3.
  • the start circuit is similar, and the embodiments of the present application will not repeat them here.
  • the ON2 and IN3 pins of the slow-start chip can be combined to control the turn-on or turn-off of N3 and N4. Therefore, the output voltage of V1 or V2 is too large, which may cause the loss of components in the circuit.
  • the combined slow start circuit may further include a fourth resistor R4.
  • One end of R4 is connected to the drain of N1, and the other end of R3 is connected to the drains of N3 and N4.
  • the comparison between the input voltage and the output voltage may be as shown in FIG. 4.
  • the amplitude of the voltage output by N1 is significantly lower, and the output voltage can be controlled within a preset range.
  • the voltage input to the gate of N1 can be as shown in FIG. 5.
  • the output voltage is divided by two resistors R1 and R2, and the divided voltage is input to the operational amplifier.
  • the feedback circuit processes the input voltage and outputs it to N2, thereby controlling the turn-on and turn-off of N2.
  • N2 When N2 is turned on, the gate of N1 is equivalent to ground. Therefore, the voltage value input to the gate of N1 is pulled down, so that N1 is not completely turned on or off.
  • N1 receives the voltage input from the integrated slow-start chip, and the voltage is greater than the turn-on voltage of N1, and N1 is turned on. Therefore, the feedback circuit can be used to control the turn-on and turn-off of N1.
  • the output voltage is too high, N1 is turned off.
  • the voltage input to the feedback circuit can be configured by configuring the values of the two resistors R1 and R2, thereby controlling the output voltage at the output voltage terminal.
  • An embodiment of the present application further provides an electronic device.
  • the electronic device may include the combined slow-start circuit in any of the foregoing embodiments in FIG. 2 or FIG. 3.
  • the electronic device may be a mobile phone, tablet computer, router, etc.
  • the electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.
  • An embodiment of the present application further provides another electronic device.
  • the electronic device may include the combined slow-start chip in any of the foregoing embodiments in FIG. 2 or FIG. 3.
  • the electronic device may be a mobile phone, tablet computer, router, etc.
  • the electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.

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Abstract

A combined soft-start circuit, a combined soft-start chip (IC), and an electronic device, which are used for improving the surge handling capability. The combined soft-start circuit comprises at least one input power supply (V1, V2), a first metal oxide semiconductor (mos) transistor (N1), a combined soft-start chip (IC) and an output voltage terminal (Vout); the combined soft-start chip (IC) comprises a feedback circuit; an output terminal of the at least one input power supply (V1, V2) is connected to a drain of the first mos transistor (N1), a gate of the first mos transistor (N1) is connected to a first control pin (GATE) of the combined soft-start chip (IC), and a source of the first mos transistor (N1) is the output voltage terminal (Vout); an input terminal (SPE) of the feedback circuit is connected to the output voltage terminal (Vout), and an output terminal of the feedback circuit is connected to the first control pin (GATE); an output voltage of the output voltage terminal (Vout) is input to the feedback circuit, and the feedback circuit generates a control voltage, and outputs same to the gate of the first mos transistor (N1) by means of the first control pin (GATE); and when the at least one input power supply (V1, V2) inputs a voltage higher than a threshold, the control voltage outputted from the feedback circuit decreases, and a gate input voltage of the first mos transistor (N1) decreases, so that the first mos transistor (N1) is not completely turned on.

Description

一种合路缓启电路、合路缓启芯片以及电子设备Combined slow start circuit, combined slow start chip and electronic equipment 技术领域Technical field
本申请涉及电路领域，特别涉及一种合路缓启电路、合路缓启芯片以及电子设备。The present application relates to the field of circuits, in particular to a combined slow-start circuit, combined slow-start chip and electronic equipment.
背景技术Background technique
合路缓启电路是需要热插拔的电子设备中非常常见的电路，合路缓启电路包括多种功能，第一是将输入的多路电源合路为一路输出；第二是在热插拔时，通过缓慢控制输出电源电压启动过程，从而减少对输入电源母线的冲击；第三是电流限制，通过电流检测通道，如果电流超过阈值一定时间则关断控制，从而达到保护上级电源和本板电路的目的。The combined slow start circuit is a very common circuit in electronic equipment that needs to be hot swapped. The combined slow start circuit includes multiple functions. The first is to combine the input multiple power supplies into one output; the second is to perform hot plug When pulling out, slowly control the starting process of the output power voltage to reduce the impact on the input power bus; the third is the current limit, through the current detection channel, if the current exceeds the threshold for a certain period of time, the control is turned off, so as to protect the superior power supply and the current The purpose of the board circuit.
示例性地，现有方案的合路缓启电路如图1所示，该合路缓启电路包括至少两个电源V1与V2、合路缓启芯片IC1、三个金属氧化物半导体(metal oxide semiconductor，MOS)管N1、N2与N3，输出Vout等等。V1接入N1的源极，N1的栅极与IC1的OG1引脚连接，V2接入N2的源极，N1的栅极与IC1的OG2引脚连接，N1的漏极与N2的漏极连接，并合路接入N3的漏极，N3的栅极接入IC1的GATE引脚，该GATE引脚可以理解为IC1控制N3的控制端，N3的源极接入输出端Vout。上电时，通过控制N3栅极电压上升速度从而控制输出电压Vout的上升速度，进而控制对输入母线的影响，减少对输入电源母线的冲击。其次是输入两路的电源V1与V2中任一路电压跌落时会控制切换到另外一路，达到输入两路合路的作用。然后对于限流的作用，当输出电流超过阈值达到一定时间时会将N3栅极电压拉低，从而切断N3的输出，达到保护上级电源和本合路缓启电路的目的。Exemplarily, the combined slow start circuit of the existing solution is shown in FIG. 1, the combined slow start circuit includes at least two power sources V1 and V2, a combined slow start chip IC1, and three metal oxide semiconductors semiconductor (MOS) transistors N1, N2 and N3, output Vout and so on. V1 is connected to the source of N1, the gate of N1 is connected to the OG1 pin of IC1, V2 is connected to the source of N2, the gate of N1 is connected to the OG2 pin of IC1, and the drain of N1 is connected to the drain of N2 , The combined circuit is connected to the drain of N3, the gate of N3 is connected to the GATE pin of IC1, the GATE pin can be understood as the control terminal of IC1 controlling N3, and the source of N3 is connected to the output terminal Vout. At power-on, the rate of rise of the output voltage Vout is controlled by controlling the rate of rise of the gate voltage of N3, thereby controlling the impact on the input bus and reducing the impact on the input power bus. Secondly, when the voltage of any one of the two input power sources V1 and V2 drops, it will be controlled to switch to the other one to achieve the effect of the two input circuits. Then for the role of current limiting, when the output current exceeds the threshold for a certain period of time, the N3 gate voltage will be pulled down, thereby cutting off the output of N3, to achieve the purpose of protecting the upper power supply and the slow start circuit of this circuit.
然而，现有实现方案基本上是对输入电压的透传，输入电压在芯片设计范围内都会传到下一级。因此如果上级存在浪涌冲击时，即瞬间出现超出稳定电压的冲击电压，冲击电压就传到了下一级，后级的所有电源设计就必须满足上级最高电压的要求而采用比较高耐压的工艺。例如，若电源输出到多个设备，那么，该多个设备则都需要耐高压。而高耐压工艺的芯片存在成本更高、效率更低的缺点。However, the existing implementation is basically a transparent transmission of the input voltage, and the input voltage will be transmitted to the next level within the design range of the chip. Therefore, if there is a surge shock at the upper stage, that is, an impulse voltage that exceeds the stable voltage instantaneously, the impulse voltage is transmitted to the next stage, and all power supply designs of the latter stage must meet the requirements of the highest voltage of the upper stage and adopt a relatively high voltage process . For example, if the power supply is output to multiple devices, the multiple devices need to withstand high voltage. However, the chip with high voltage process has the disadvantages of higher cost and lower efficiency.
发明内容Summary of the invention
本申请实施例提供了一种合路缓启电路、合路缓启芯片以及电子设备，用于提高合路缓启电路的抗浪涌冲击能力，降低使用合路缓启电路的后级设备成本。The embodiments of the present application provide a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of subsequent equipment using the combined slow-start circuit .
有鉴于此，本申请第一方面一种合路缓启电路，包括：至少一个输入电源、第一金属氧化物半导体mos管、合路缓启芯片与输出电压端；其中，合路缓启芯片还包括反馈电路；In view of this, a combined slow start circuit of the first aspect of the present application includes: at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow start chip and an output voltage terminal; wherein, the combined slow start chip Also includes a feedback circuit;
该至少一个输入电源的输出端连接该第一mos管的漏极，该第一mos管的栅极连接该合路缓启芯片的第一控制引脚，该第一mos管的源极为输出电压端；该反馈电路的输入端连接该输出电压端，该反馈电路的输出端连接该第一控制引脚；The output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin of the combined slow-start chip, and the source of the first mos tube outputs the output voltage The input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
该输出电压端的输出电压输入至该反馈电路，该反馈电路根据该输出电压得到控制电压，并通过该第一控制引脚输出至该第一mos管的栅极；The output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
当该至少一个输入电源输入高于阈值的电压时，该反馈电路输出的控制电压降低，该第一mos管的栅极输入电压降低，以使该第一mos管不完全导通。When the voltage of the at least one input power supply is higher than the threshold value, the control voltage output by the feedback circuit is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is not fully turned on.
在本申请实施例中，当至少一个输入电源输入高于阈值的电压时，反馈电路输出的控制电压降低，从而使输入到第一mos管栅极的电压降低，以控制第一mos管不完全导通或者截止。因此，输出电压端输出的电压也降低。因此，当输入电压存在浪涌时，通过反馈电路控制第一mos管的不完全导通或截止，使第一mos管源极的输出电压降低，因此得到输出电压降低，可以抑制浪涌冲击。In the embodiment of the present application, when at least one input power supply inputs a voltage higher than the threshold, the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the grid of the first mos tube to control the incomplete first mos tube Turn on or off. Therefore, the voltage output from the output voltage terminal also decreases. Therefore, when there is a surge in the input voltage, the feedback circuit controls the incomplete conduction or cut-off of the first mos tube, so that the output voltage of the source of the first mos tube is reduced, so the output voltage is reduced, and the surge impact can be suppressed.
可选地，在一些可能的实施例中，反馈电路可以包括运算放大器与第二mos管；Optionally, in some possible embodiments, the feedback circuit may include an operational amplifier and a second mos tube;
该运算放大器的同相输入端连接该输出电压端，该运算放大器的反相输入的接入参考电源，该运算放大器的输出端连接该第二mos管的栅极，该第二mos管的漏极连接该第一mos管的栅极，该第二mos管的源极接地。The non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the second mos tube is grounded.
在本申请实施例中，当输出电压过高时，经过运算放大器反馈到第二mos管的栅极，从而控制第二mos管导通，而第二mos管的源极接地，因此，相当于将第一mos管的栅极接地。从而降低了第一mos管的栅极的电压，使第一mos管不完全导通或截止，进而使第一mos管源极输出的电压降低。因此得到输出电压降低，可以抑制浪涌冲击。In the embodiment of the present application, when the output voltage is too high, it is fed back to the gate of the second mos tube through the operational amplifier, thereby controlling the conduction of the second mos tube, and the source of the second mos tube is grounded. Therefore, it is equivalent to Ground the grid of the first mos tube. As a result, the voltage of the grid of the first mos tube is reduced, so that the first mos tube is not fully turned on or off, thereby reducing the voltage output from the source of the first mos tube. Therefore, the output voltage is reduced, and surge surge can be suppressed.
可选地，在一些可能的实施例中，该合路缓启电路还可以包括：第一电阻与第二电阻；Optionally, in some possible embodiments, the combined slow start circuit may further include: a first resistor and a second resistor;
该输出电压端连接该第一电阻的一端，该第一电阻的另一端连接该运算放大器的同相输入端与该第二电阻的一端，该第二电阻的另一端接地。The output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
在本申请实施例中，可以通过配置第一电阻与第二电阻的值，来确定本申请实施例中电压钳位的具体值，并可以通过两个电阻将分压后的电压输入至运算放大器中，实现反馈电路的输入，从而控制第一mos管的导通与截止，进而控制输出电压端的输出电压。In the embodiment of the present application, the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of the first resistor and the second resistor, and the divided voltage can be input to the operational amplifier through the two resistors In it, the input of the feedback circuit is realized, so as to control the on and off of the first mos tube, and then the output voltage of the output voltage terminal.
可选地，在一些可能的实施例中，该至少一个输入电源中包括第一输入电源与第二输入电源，该合路缓启电路还包括第三mos管与第四mos管；Optionally, in some possible embodiments, the at least one input power supply includes a first input power supply and a second input power supply, and the combined slow-start circuit further includes a third mos tube and a fourth mos tube;
该第一输入电源的输出端连接该第三mos管的源极，该第三mos管的栅极连接该合路缓启芯片的第二控制引脚，该第三mos管的漏极连接该第一mos管的漏极；The output end of the first input power supply is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin of the combined slow-start chip, and the drain of the third mos tube is connected to the The drain of the first mos tube;
该第二输入电源的输出端连接该第四mos管的源极，该第四mos管的栅极连接该合路缓启芯片的第三控制引脚，该第四mos管的漏极连接该第一mos管的漏极。The output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin of the combined slow-start chip, and the drain of the fourth mos tube is connected to the The drain of the first mos tube.
在本申请实施例中，可以通过第二控制引脚与第三控制引脚，控制第二mos管与第三mos管的导通或截止。从而避免第一输入电源或第二输入电源的输出电压过大，而导致电路中的元件损耗等。In the embodiments of the present application, the second control pin and the third control pin may be used to control the conduction or cut-off of the second mos tube and the third mos tube. Therefore, it is avoided that the output voltage of the first input power supply or the second input power supply is too large, which may cause component loss in the circuit.
可选地，在一些可能的实施例中，该合路缓启电路还包括第一电容，该第一电容的一端连接该输出电压端，该电容的另一端接地。Optionally, in some possible embodiments, the combined slow-start circuit further includes a first capacitor, one end of the first capacitor is connected to the output voltage terminal, and the other end of the capacitor is grounded.
可选地，在一些可能的实施例中，该合路缓启电路还包括第二电容与第三电阻；Optionally, in some possible embodiments, the combined slow start circuit further includes a second capacitor and a third resistor;
该第二电容的一端连接该第一mos管的栅极，该第二电容的另一端连接该第三电阻的一端，该第三电阻的另一端接地。One end of the second capacitor is connected to the gate of the first mos tube, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.
在本申请实施例中，通过接入第二电容与第三电阻，实现对第一mos管的延迟控制，实现缓启动的效果。In the embodiment of the present application, by connecting the second capacitor and the third resistor, the delay control of the first mos tube is realized to achieve the effect of slow start.
可选地，在一些可能的实施例中，该合路缓启电路还包括第四电阻；Optionally, in some possible embodiments, the combined slow start circuit further includes a fourth resistor;
该第四电阻的一端连接该第一mos管的漏极，该第四电阻的另一端连接该第二mos管 的漏极与该第三mos管的漏极。One end of the fourth resistor is connected to the drain of the first mos tube, and the other end of the fourth resistor is connected to the drain of the second mos tube and the drain of the third mos tube.
本申请第二方面提供一种合路缓启芯片，应用于合路缓启电路，该合路缓启电路包括至少一个输入电源、第一金属氧化物半导体mos管、合路缓启芯片与输出电压端，该合路缓启芯片包括反馈电路、第一控制引脚；The second aspect of the present application provides a combined slow-start chip applied to a combined slow-start circuit. The combined slow-start circuit includes at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow-start chip and an output At the voltage end, the combined slow-start chip includes a feedback circuit and a first control pin;
该至少一个输入电源的输出端连接该第一mos管的漏极，该第一mos管的栅极连接该第一控制引脚，该第一mos管的源极为输出电压端；The output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin, and the source of the first mos tube is the output voltage terminal;
该反馈电路的输入端连接该输出电压端，该反馈电路的输出端连接该第一控制引脚；The input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
该输出电压端的输出电压输入至该反馈电路，该反馈电路根据该输出电压得到控制电压，并通过该第一控制引脚输出至该第一mos管的栅极；The output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
当该至少一个输入电源输入高于峰值的高电压时，该控制电压降低，该第一mos管的栅极输入电压降低，以使该第一mos管截止。When the input voltage of the at least one input power supply is higher than the peak high voltage, the control voltage is reduced, and the gate input voltage of the first mos tube is reduced, so that the first mos tube is turned off.
可选地，在一些可能的实施例中，该反馈电路包括运算放大器与第二mos管；Optionally, in some possible embodiments, the feedback circuit includes an operational amplifier and a second mos tube;
该运算放大器的同相输入端连接该输出电压端，该运算放大器的反相输入的接入参考电源，该运算放大器的输出端连接该第二mos管的栅极，该第二mos管的漏极连接该第一mos管的栅极，该第四mos管的源极接地。The non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power source, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the drain of the second mos tube The grid of the first mos tube is connected, and the source of the fourth mos tube is grounded.
可选地，在一些可能的实施例中，该合路缓启电路还包括：第一电阻与第二电阻；Optionally, in some possible embodiments, the combined slow start circuit further includes: a first resistor and a second resistor;
该输出电压端连接该第一电阻的一端，该第一电阻的另一端连接该运算放大器的同相输入端与该第二电阻的一端，该第二电阻的另一端接地。The output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
可选地，在一些可能的实施例中，该至少一个输入电源中包括第一输入电源与第二输入电源，该合路缓启电路还可以包括第三mos管与第四mos管，该合路缓启芯片还包括第二控制引脚与第三控制引脚；Optionally, in some possible embodiments, the at least one input power supply includes a first input power supply and a second input power supply, and the combined slow-start circuit may further include a third mos tube and a fourth mos tube. The slow start chip also includes a second control pin and a third control pin;
该第一输入电源的输出端连接该第三mos管的源极，该第三mos管的栅极连接该第二控制引脚，该第三mos管的漏极连接该第一mos管的漏极；The output end of the first input power source is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin, and the drain of the third mos tube is connected to the drain of the first mos tube pole;
该第二输入电源的输出端连接该第四mos管的源极，该第四mos管的栅极连接该第三控制引脚，该第四mos管的漏极连接该第一mos管的漏极。The output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin, and the drain of the fourth mos tube is connected to the drain of the first mos tube pole.
本申请第三方面提供一种电子设备，该电子设备包括如前述第一方面中任一实施例中的合路缓启电路。A third aspect of the present application provides an electronic device. The electronic device includes the combined slow-start circuit as in any one of the foregoing embodiments of the first aspect.
本申请第四方面提供一种电子设备，其特征在于，该电子设备包括前述第二方面中任一实施例中的合路缓启芯片。A fourth aspect of the present application provides an electronic device, characterized in that the electronic device includes the combined slow-start chip in any embodiment of the foregoing second aspect.
本申请实施例提供的技术方案中，在本申请实施例中，当输入高于阈值的输入电压时，通过反馈电路输出的控制电压，控制第一mos管栅极的输入电压降低，从而使第一mos管不完全导通或截止，以避免高于阈值的输入电压输出到输出电压端。因此，本申请实施例通过加入反馈电路，将输出电压控制在一定范围内，抑制浪涌冲击，后级接收输出电压端的设备降低耐高压工艺的电压，无需进行过高耐高压工艺制造，降低了后级设备的成本，提高制造效率。In the technical solution provided by the embodiment of the present application, in the embodiment of the present application, when the input voltage higher than the threshold value is input, the control voltage output by the feedback circuit is used to control the input voltage of the gate of the first mos tube to decrease, thereby making the first A MOS tube is not fully turned on or off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, the embodiment of the present application controls the output voltage within a certain range by adding a feedback circuit to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-voltage resistant process, without the need for excessive high-voltage resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
附图说明BRIEF DESCRIPTION
图1为现有方案中合路缓启电路的一个实施例的示意图；FIG. 1 is a schematic diagram of an embodiment of a combined slow start circuit in an existing solution;
图2为本申请实施例中提供的合路缓启电路的一种实施例示意图；2 is a schematic diagram of an embodiment of a combined slow start circuit provided in an embodiment of the present application;
图3为本申请实施例中提供的合路缓启电路的另一种实施例示意图3 is a schematic diagram of another embodiment of a combined slow start circuit provided in an embodiment of the present application
图4为本申请实施例中提供的合路缓启电路的输入电压与输出电压对比图；4 is a comparison diagram of input voltage and output voltage of a combined slow start circuit provided in an embodiment of the present application;
图5为本申请实施例中提供的合路缓启电路的控制电压示意图。5 is a schematic diagram of the control voltage of the combined slow start circuit provided in the embodiment of the present application.
具体实施方式detailed description
本申请提供一种合路缓启电路、合路缓启芯片以及电子设备，用于提高合路缓启电路的抗浪涌冲击能力，降低使用合路缓启电路的成本。The application provides a combined slow-start circuit, a combined slow-start chip and electronic equipment, which are used to improve the surge resistance of the combined slow-start circuit and reduce the cost of using the combined slow-start circuit.
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work fall within the protection scope of the present application.
本申请实施例提供的合路缓启芯片可以应用于合路缓启电路，该合路缓启电路或该合路缓启芯片还可以应用于各种电子设备，例如，移动电话、路由器等等。The combined slow-start chip provided in the embodiments of the present application can be applied to a combined slow-start circuit, and the combined slow-start circuit or the combined slow-start chip can also be applied to various electronic devices, such as mobile phones, routers, etc. .
下面对本申请实施例提供的合路缓启电路以及合路缓启芯片进行结合说明，请参阅图2，本申请实施例提供的合路缓启电路。该合路缓启电路包括至少一个输入电源、第一mos管N1、合路缓启芯片IC与输出电压端Vout；其中，合路缓启芯片还包括反馈电路。The combined slow-start circuit and the combined slow-start chip provided in the embodiments of the present application will be described below, please refer to FIG. 2, the combined slow-start circuit provided in the embodiments of the present application. The combined slow-start circuit includes at least one input power supply, a first mos tube N1, a combined slow-start chip IC, and an output voltage terminal Vout; wherein, the combined slow-start chip further includes a feedback circuit.
其中，该至少一个输入电源，可以包括一个或多个输入电源，该多个为两个或两个以上。下面以两个输入电源V1与V2为例进行说明。Wherein, the at least one input power supply may include one or more input power supplies, and the plurality of input power supplies are two or more. The following uses two input power sources V1 and V2 as an example for description.
第一mos管N1以N型金属氧化物半导体(N-Metal-Oxide-Semiconductor，NMOS)为例进行说明，该第一mos管也可以是P型金属氧化物半导体(P-Metal-Oxide-Semiconductor，PMOS)，具体可以根据实际应用场景调整，此处仅以NMOS进行示例性说明。The first mos tube N1 is described by taking an N-Metal-Oxide-Semiconductor (NMOS) as an example, and the first mos tube may also be a P-Metal-Oxide-Semiconductor , PMOS), which can be adjusted according to the actual application scenario. Here, only NMOS is used as an example.
输入电源V1的输出端与V2的输出端合路后，连接到N1的漏极，N1的源极连接到输出电压端，该输出电压端输出该合路缓启电路的输出电压。N1的栅极连接到合路缓启芯片的第一控制引脚，该第一控制引脚连接到反馈电路的输出端，并且反馈电路的输入端连接输出电压端。After the output terminal of the input power supply V1 is combined with the output terminal of V2, it is connected to the drain of N1, and the source of N1 is connected to the output voltage terminal. The output voltage terminal outputs the output voltage of the combined slow-start circuit. The gate of N1 is connected to the first control pin of the combined slow start chip, the first control pin is connected to the output terminal of the feedback circuit, and the input terminal of the feedback circuit is connected to the output voltage terminal.
可以理解为，合路缓启芯片增加了一个引脚，即SPE引脚，反馈电路的输入端为合路缓启芯片的SPE引脚，反馈电路的输出端连接合路缓启芯片的第一控制引脚，即图2中的GATE引脚。It can be understood that the integrated slow start chip adds a pin, namely the SPE pin, the input terminal of the feedback circuit is the SPE pin of the combined slow start chip, and the output end of the feedback circuit is connected to the first of the combined slow start chip The control pin is the GATE pin in Figure 2.
输出电压端的输出电压通过SPE引脚输入值反馈电路，反馈电路根据该输出电压端输出的电压得到控制电压，并通过GATE引脚输入到N1的栅极，以控制N1的导通或截止。The output voltage at the output voltage terminal passes through the input value feedback circuit of the SPE pin. The feedback circuit obtains a control voltage according to the voltage output from the output voltage terminal, and inputs it to the gate of N1 through the GATE pin to control the turning on or off of N1.
具体地，当该至少一个输入电源中任一个输入电源输入高于阈值的输入电压时，反馈电路输出的控制电压降低，从而输入到N1栅极的电压降低，进而控制N1不完全导通或截止，以降低输出电压端的输出电压。Specifically, when any one of the at least one input power source inputs an input voltage higher than the threshold value, the control voltage output by the feedback circuit decreases, thereby reducing the voltage input to the gate of N1, thereby controlling N1 to not be fully turned on or off To reduce the output voltage at the output voltage end.
应理解，本申请实施例中的合路缓启芯片除了前述的GATE引脚与SPE引脚外，还可以 包括其他的引脚(图中未示出)，例如，电源引脚、接地引脚等等，具体可以根据实际应用场景调整。It should be understood that the combined slow-start chip in the embodiment of the present application may include other pins (not shown in the figure) in addition to the aforementioned GATE pins and SPE pins, for example, power pins and ground pins Wait, it can be adjusted according to the actual application scenario.
因此，在本申请实施例中，当输入高于阈值的输入电压时，通过反馈电路输出的控制电压，控制第一mos管栅极的输入电压降低，从而使第一mos管不完全导通或截止，以避免高于阈值的输入电压输出到输出电压端。因此，本申请实施例通过加入反馈电路，将输出电压控制在一定范围内，抑制浪涌冲击，后级接收输出电压端的设备降低耐高压工艺的电压，无需进行过高耐高压工艺制造，降低了后级设备的成本，提高制造效率。Therefore, in the embodiment of the present application, when an input voltage higher than the threshold is input, the control voltage output by the feedback circuit controls the input voltage of the gate of the first mos tube to decrease, so that the first mos tube is not fully turned on or Cut off to avoid outputting the input voltage above the threshold to the output voltage. Therefore, in the embodiment of the present application, by adding a feedback circuit, the output voltage is controlled within a certain range to suppress the surge impact, and the equipment receiving the output voltage terminal at the subsequent stage reduces the voltage of the high-pressure-resistant process, without the need for excessive high-pressure-resistant process manufacturing, which reduces The cost of post-stage equipment improves manufacturing efficiency.
更具体地，下面对本申请实施例提供的合路缓启电路进行更进一步地说明，请参阅图3。More specifically, the combined slow start circuit provided by the embodiment of the present application is further described below, please refer to FIG. 3.
其中，还是以两个电源V1、V2进行示例性说明。Among them, the two power sources V1 and V2 are still used as an example for description.
反馈电路包括运算放大器F1与第二mos管N2。The feedback circuit includes an operational amplifier F1 and a second mos tube N2.
N2可以是NMOS，也可以是PMOS，此处仅以NMOS进行示例性说明，当N2为PMOS的连接结构与NMOS类似，此处不再赘述。N2 may be NMOS or PMOS. Here, only NMOS will be used as an example for description. When N2 is a PMOS, the connection structure is similar to NMOS, and will not be repeated here.
F1的同相输入端连接SPE引脚，SPE引脚连接输出电压端，F1的反相输入端输入参考电压Vi，F1的输出端连接N2的栅极。N2的源极接地，N2的漏极连接GATE端，即第一控制端。The non-inverting input end of F1 is connected to the SPE pin, the SPE pin is connected to the output voltage end, the inverting input end of F1 inputs the reference voltage Vi, and the output end of F1 is connected to the gate of N2. The source of N2 is grounded, and the drain of N2 is connected to the GATE terminal, which is the first control terminal.
当F1的同相输入端接收从输出电压端输入的电压时，将该电压与参考电压Vi对比，并进行放大运算，输出到N2的栅极，从而控制N2的截止或导通。当存在浪涌时，输出电压端的输出电压增高，通过SPE引脚反馈到运算放大器F1的同相输入端，若输出电压过高，则运算放大器F1的输出电压经过放大也增高，然后F1的输出电压反馈到N2的栅极，当高于N2的开启电压时，N2导通。此时，可以相当于逐渐将N1的栅极导通至接地，从而降低N1栅极的输入电压，控制N1不完全导通或截止，从而避免浪涌冲击输出到后级设备。当N1截止，输出电压端的输出电压降低，反馈到运算放大器F1，使F1的输出电压降低，当降低至N2的开启电压以下时，N2截止，合路缓启芯片内部的电流源输出电流至N1的栅极，从而控制N1导通。因此，在本申请实施例中，通过反馈电路，实时对输出电压端的输出电压进行反馈，控制N1的导通或截止，从而使输出电压端的输出电压控制在预设范围内。When the non-inverting input terminal of F1 receives the voltage input from the output voltage terminal, the voltage is compared with the reference voltage Vi, and an amplification operation is performed to output to the gate of N2, thereby controlling the cut-off or conduction of N2. When there is a surge, the output voltage at the output voltage terminal increases and is fed back to the non-inverting input terminal of the operational amplifier F1 through the SPE pin. If the output voltage is too high, the output voltage of the operational amplifier F1 also increases after amplification, and then the output voltage of F1 Feedback to the gate of N2, when higher than the turn-on voltage of N2, N2 is turned on. At this time, it can be equivalent to gradually turning on the gate of N1 to ground, thereby reducing the input voltage of the gate of N1, controlling N1 not to be fully turned on or off, so as to avoid the surge impact output to the subsequent device. When N1 is turned off, the output voltage at the output voltage terminal is lowered, which is fed back to the operational amplifier F1 to reduce the output voltage of F1. When it falls below the turn-on voltage of N2, N2 is turned off and the current source inside the chip slowly turns on to output current to N1 Of the gate, thereby controlling N1 to turn on. Therefore, in the embodiment of the present application, a feedback circuit is used to feedback the output voltage at the output voltage terminal in real time to control the on or off of N1, so that the output voltage at the output voltage terminal is controlled within a preset range.
可选地，合路缓启芯片内部还设置有电流源Is，Is的一端连接到GATE引脚。当N2截止时，Is的输出电流导通至N1的栅极，且输入至N1栅极的电压高于N1的开启电压，从而使N1导通。因此，当输出电压端的输出电压处于正常电压范围内时，N2截止，N1导通。从而使输出电压稳定输出。Optionally, a current source Is is also provided inside the combined slow-start chip, and one end of the Is is connected to the GATE pin. When N2 is turned off, the output current of Is is turned on to the gate of N1, and the voltage input to the gate of N1 is higher than the turn-on voltage of N1, thereby turning on N1. Therefore, when the output voltage at the output voltage terminal is within the normal voltage range, N2 is turned off and N1 is turned on. Thus, the output voltage is stably output.
可选地，合路缓启电路还包括第一电阻R1与第二电阻R2。R1一端连接输出电压端，另一端连接SPE引脚与R2的一端，R2的另一端接地。因此，输入到SPE的电压的值为：V＝(R2/(R1+R2))*Vout。因此，可以降低输入到运算放大器中的电压值。Optionally, the combined slow start circuit further includes a first resistor R1 and a second resistor R2. One end of R1 is connected to the output voltage end, the other end is connected to the SPE pin and one end of R2, and the other end of R2 is grounded. Therefore, the value of the voltage input to the SPE is: V=(R2/(R1+R2))*Vout. Therefore, the voltage value input to the operational amplifier can be reduced.
在本申请实施例中，可以通过配置R1与R2的值，来确定本申请实施例中电压钳位的具体值，并通过两个电阻将分压后的电压输入至SPE引脚，实现反馈电路的输入，从而控制N1的导通与截止，进而控制输出电压端的输出电压。In the embodiment of the present application, the specific value of the voltage clamping in the embodiment of the present application can be determined by configuring the values of R1 and R2, and the divided voltage is input to the SPE pin through two resistors to implement a feedback circuit To control the turn-on and turn-off of N1, and then the output voltage at the output voltage terminal.
可选地，合路缓启电路还可以包括第一电容C1。该第一电容C1的一端连接至N1的源 极，C2的另一端接地。以对输出电压进行过滤，使输出电压更稳定。Optionally, the combined slow start circuit may further include a first capacitor C1. One end of the first capacitor C1 is connected to the source of N1, and the other end of C2 is grounded. To filter the output voltage to make the output voltage more stable.
可选地，合路缓启电路还可以包括第二电容C2与第三电阻R3。C2的一端连接N1的栅极，C2的另一端连接R3的一端，R3的另一端接地。在本申请实施例中，可以通过C2的充电与放电之间的时延，从而实现对N1的控制的时延，从而实现缓启。Optionally, the combined slow start circuit may further include a second capacitor C2 and a third resistor R3. One end of C2 is connected to the gate of N1, the other end of C2 is connected to one end of R3, and the other end of R3 is grounded. In the embodiment of the present application, the delay between the charging and discharging of C2 may be used to realize the delay of controlling N1, and thus the slow start.
可选地，V1、V2与N1之间还可可以包括第三mos管N3与第四mos管N4。Optionally, a third mos tube N3 and a fourth mos tube N4 may also be included between V1, V2, and N1.
V1的输入至N3的源极，N3的栅极连接合路缓启芯片的第二控制引脚IN2，N3的漏极连接至N1的漏极。The input of V1 is connected to the source of N3, the gate of N3 is connected to the second control pin IN2 of the combined slow-start chip, and the drain of N3 is connected to the drain of N1.
V2的输入至N4的源极，N4的栅极连接合路缓启芯片的第三控制引脚IN3，N4的漏极连接至N1的漏极。The input of V2 is connected to the source of N4, the gate of N4 is connected to the third control pin IN3 of the combined slow-start chip, and the drain of N4 is connected to the drain of N1.
应理解，在本申请中，前述的N1、N2、N3、N4中除了可以都为NMOS，还可以是其中一个或多个为PMOS，其连接结构与前述图2或图3中的合路缓启电路类似，本申请实施例不再赘述。It should be understood that, in the present application, all of the foregoing N1, N2, N3, and N4 may be NMOS, or one or more of them may be PMOS, and the connection structure thereof is combined with the foregoing combination of FIG. 2 or FIG. 3. The start circuit is similar, and the embodiments of the present application will not repeat them here.
因此，在本申请实施例中，可以通过合路缓启芯片的IN2与IN3引脚，控制N3与N4的导通或截止。从而避免V1或V2的输出电压过大，而导致电路中的元件损耗等。Therefore, in the embodiment of the present application, the ON2 and IN3 pins of the slow-start chip can be combined to control the turn-on or turn-off of N3 and N4. Therefore, the output voltage of V1 or V2 is too large, which may cause the loss of components in the circuit.
可选地，合路缓启电路还可以包括第四电阻R4。R4的一端连接N1的漏极，R3的另一端连接N3与N4的漏极。Optionally, the combined slow start circuit may further include a fourth resistor R4. One end of R4 is connected to the drain of N1, and the other end of R3 is connected to the drains of N3 and N4.
示例性地，输入电压与输出电压的对比可以如图4所示。其中，当输入电压存在浪涌时，通过控制N1的栅极，使N1输出的电压提升的幅度明显较低，可以使输出电压控制在预设范围内。对应的，输入到N1栅极的电压可以如图5所示。当输入电压存在浪涌时，拉低N1栅极的输入电压，以控制N1的不完全导通或截止，进而避免输出电压过高。Exemplarily, the comparison between the input voltage and the output voltage may be as shown in FIG. 4. Among them, when there is a surge in the input voltage, by controlling the gate of N1, the amplitude of the voltage output by N1 is significantly lower, and the output voltage can be controlled within a preset range. Correspondingly, the voltage input to the gate of N1 can be as shown in FIG. 5. When there is a surge in the input voltage, pull down the input voltage of the gate of N1 to control the incomplete turn-on or cut-off of N1, thereby avoiding excessive output voltage.
可以理解为，在本申请实施例中，通过两个电阻R1与R2对输出电压进行分压，并将分压后的电压输入至运算放大器。反馈电路对输入的电压进行处理后，输出到N2，从而控制N2的导通与截止。当N2导通时，N1的栅极相当于接地，因此，拉低了N1栅极输入的电压值，使，N1不完全导通或截止。当N2截止时，N1接收合路缓启芯片内部输入的电压，且该电压大于N1的开启电压，N1导通。因此，可以通过反馈电路来控制N1的导通截止，当输出电压过高时，N1截止，输出电压低于阈值时，N1导通，可以避免浪涌冲击的冲击电压对输出电压的影响。此外，还可以通过配置两个电阻R1与R2的值，来配置输入至反馈电路的电压，从而控制输出电压端的输出电压。It can be understood that, in the embodiment of the present application, the output voltage is divided by two resistors R1 and R2, and the divided voltage is input to the operational amplifier. The feedback circuit processes the input voltage and outputs it to N2, thereby controlling the turn-on and turn-off of N2. When N2 is turned on, the gate of N1 is equivalent to ground. Therefore, the voltage value input to the gate of N1 is pulled down, so that N1 is not completely turned on or off. When N2 is turned off, N1 receives the voltage input from the integrated slow-start chip, and the voltage is greater than the turn-on voltage of N1, and N1 is turned on. Therefore, the feedback circuit can be used to control the turn-on and turn-off of N1. When the output voltage is too high, N1 is turned off. When the output voltage is lower than the threshold, N1 is turned on, which can avoid the impact of the surge voltage on the output voltage. In addition, the voltage input to the feedback circuit can be configured by configuring the values of the two resistors R1 and R2, thereby controlling the output voltage at the output voltage terminal.
本申请实施例还提供一种电子设备，该电子设备可以包括前述图2或图3中任一实施例中的合路缓启电路。该电子设备可以是移动电话、平板电脑、路由器等等。该电子设备还可以包括处理器、存储器、显示器等等，具体本申请实施例不作限定。An embodiment of the present application further provides an electronic device. The electronic device may include the combined slow-start circuit in any of the foregoing embodiments in FIG. 2 or FIG. 3. The electronic device may be a mobile phone, tablet computer, router, etc. The electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.
本申请实施例还提供另一种电子设备，该电子设备可以包括前述图2或图3中任一实施例中的合路缓启芯片。该电子设备可以是移动电话、平板电脑、路由器等等。该电子设备还可以包括处理器、存储器、显示器等等，具体本申请实施例不作限定。An embodiment of the present application further provides another electronic device. The electronic device may include the combined slow-start chip in any of the foregoing embodiments in FIG. 2 or FIG. 3. The electronic device may be a mobile phone, tablet computer, router, etc. The electronic device may further include a processor, a memory, a display, etc., which is not specifically limited in the embodiments of the present application.
本申请的说明书和权利要求书及附图中的术语“第一”、“第二”、“第三”、“第四”等(如果存在)是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。应该理解这样使用的数据在适当情况下可以互换，以便这里描述的实施例能够以除了在这里 图示或描述的内容以外的顺序实施。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、***、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。The terms "first", "second", "third", "fourth", etc. (if any) in the description, claims, and drawings of this application are used to distinguish similar objects, not necessarily Describe a specific order or sequence. It should be understood that the data so used can be interchanged under appropriate circumstances so that the embodiments described herein can be implemented in an order other than what is illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, processes, methods, systems, products or devices that contain a series of steps or units need not be limited to those clearly listed Those steps or units, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or equipment.

Claims (13)

  1. 一种合路缓启电路，其特征在于，包括：至少一个输入电源、第一金属氧化物半导体mos管、合路缓启芯片与输出电压端；其中，所述合路缓启芯片还包括反馈电路；A combined slow-start circuit, characterized by comprising: at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow-start chip and an output voltage terminal; wherein the combined slow-start chip further includes feedback Circuit
    所述至少一个输入电源的输出端连接所述第一mos管的漏极，所述第一mos管的栅极连接所述合路缓启芯片的第一控制引脚，所述第一mos管的源极为输出电压端；The output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin of the combined slow-start chip, and the first mos tube The source is the output voltage terminal;
    所述反馈电路的输入端连接所述输出电压端，所述反馈电路的输出端连接所述第一控制引脚；The input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
    所述输出电压端的输出电压输入至所述反馈电路，所述反馈电路根据所述输出电压得到控制电压，并通过所述第一控制引脚输出至所述第一mos管的栅极；The output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
    当所述至少一个输入电源输入高于阈值的电压时，所述反馈电路输出的所述控制电压降低，所述第一mos管的栅极输入电压降低，以使所述第一mos管不完全导通。When the input voltage of the at least one input power supply is higher than a threshold, the control voltage output by the feedback circuit decreases, and the gate input voltage of the first mos tube decreases, so that the first mos tube is not complete Turn on.
  2. 根据权利要求1所述的合路缓启电路，其特征在于，所述反馈电路包括运算放大器与第二mos管；The combined slow start circuit according to claim 1, wherein the feedback circuit includes an operational amplifier and a second mos tube;
    所述运算放大器的同相输入端连接所述输出电压端，所述运算放大器的反相输入的接入参考电源，所述运算放大器的输出端连接所述第二mos管的栅极，所述第二mos管的漏极连接所述第一mos管的栅极，所述第二mos管的源极接地。The non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power supply, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the first The drain of the two mos tubes is connected to the grid of the first mos tube, and the source of the second mos tube is grounded.
  3. 根据权利要求2所述的合路缓启电路，其特征在于，所述合路缓启电路还包括：第一电阻与第二电阻；The combined slow-start circuit according to claim 2, wherein the combined slow-start circuit further comprises: a first resistor and a second resistor;
    所述输出电压端连接所述第一电阻的一端，所述第一电阻的另一端连接所述运算放大器的同相输入端与所述第二电阻的一端，所述第二电阻的另一端接地。The output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  4. 根据权利要求1-3中任一项所述的合路缓启电路，其特征在于，所述至少一个输入电源中包括第一输入电源与第二输入电源，所述合路缓启电路还包括第三mos管与第四mos管；The combined slow-start circuit according to any one of claims 1 to 3, wherein the at least one input power supply includes a first input power and a second input power, and the combined slow-start circuit further includes The third mos tube and the fourth mos tube;
    所述第一输入电源的输出端连接所述第三mos管的源极，所述第三mos管的栅极连接所述合路缓启芯片的第二控制引脚，所述第三mos管的漏极连接所述第一mos管的漏极；The output end of the first input power source is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin of the combined slow-start chip, and the third mos tube Is connected to the drain of the first mos tube;
    所述第二输入电源的输出端连接所述第四mos管的源极，所述第四mos管的栅极连接所述合路缓启芯片的第三控制引脚，所述第四mos管的漏极连接所述第一mos管的漏极。The output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin of the combined slow-start chip, and the fourth mos tube Is connected to the drain of the first mos tube.
  5. 根据权利要求1-4中任一项所述的合路缓启电路，其特征在于，所述合路缓启电路还包括第一电容，所述第一电容的一端连接所述输出电压端，所述电容的另一端接地。The combined slow-start circuit according to any one of claims 1-4, wherein the combined slow-start circuit further includes a first capacitor, and one end of the first capacitor is connected to the output voltage terminal, The other end of the capacitor is grounded.
  6. 根据权利要求1-5中任一项所述的合路缓启电路，其特征在于，所述合路缓启电路还包括第二电容与第三电阻；The combined slow-start circuit according to any one of claims 1-5, wherein the combined slow-start circuit further includes a second capacitor and a third resistor;
    所述第二电容的一端连接所述第一mos管的栅极，所述第二电容的另一端连接所述第三电阻的一端，所述第三电阻的另一端接地。One end of the second capacitor is connected to the gate of the first mos tube, the other end of the second capacitor is connected to one end of the third resistor, and the other end of the third resistor is grounded.
  7. 根据权利要求2所述的合路缓启电路，其特征在于，所述合路缓启电路还包括第四电阻；The combined slow-start circuit according to claim 2, wherein the combined slow-start circuit further comprises a fourth resistor;
    所述第四电阻的一端连接所述第一mos管的漏极，所述第四电阻的另一端连接所述第二mos管的漏极与所述第三mos管的漏极。One end of the fourth resistor is connected to the drain of the first mos tube, and the other end of the fourth resistor is connected to the drain of the second mos tube and the drain of the third mos tube.
  8. 一种合路缓启芯片，应用于合路缓启电路，其特征在于，所述合路缓启电路包括至少一个输入电源、第一金属氧化物半导体mos管、合路缓启芯片与输出电压端，所述合路缓启芯片包括反馈电路、第一控制引脚；A combined slow-start chip, applied to a combined slow-start circuit, characterized in that the combined slow-start circuit includes at least one input power supply, a first metal oxide semiconductor mos tube, a combined slow-start chip and an output voltage End, the combined slow-start chip includes a feedback circuit and a first control pin;
    所述至少一个输入电源的输出端连接所述第一mos管的漏极，所述第一mos管的栅极连接所述第一控制引脚，所述第一mos管的源极为输出电压端；The output terminal of the at least one input power source is connected to the drain of the first mos tube, the gate of the first mos tube is connected to the first control pin, and the source of the first mos tube is the output voltage terminal ;
    所述反馈电路的输入端连接所述输出电压端，所述反馈电路的输出端连接所述第一控制引脚；The input terminal of the feedback circuit is connected to the output voltage terminal, and the output terminal of the feedback circuit is connected to the first control pin;
    所述输出电压端的输出电压输入至所述反馈电路，所述反馈电路根据所述输出电压得到控制电压，并通过所述第一控制引脚输出至所述第一mos管的栅极；The output voltage of the output voltage terminal is input to the feedback circuit, and the feedback circuit obtains a control voltage according to the output voltage, and outputs it to the gate of the first mos tube through the first control pin;
    当所述至少一个输入电源输入高于峰值的高电压时，所述控制电压降低，所述第一mos管的栅极输入电压降低，以使所述第一mos管不完全导通。When the input voltage of the at least one input power source is higher than the peak high voltage, the control voltage is lowered, and the gate input voltage of the first mos tube is lowered, so that the first mos tube is not fully turned on.
  9. 根据权利要求8所述的合路缓启芯片，其特征在于，所述反馈电路包括运算放大器与第二mos管；The combined slow-start chip according to claim 8, wherein the feedback circuit includes an operational amplifier and a second mos tube;
    所述运算放大器的同相输入端连接所述输出电压端，所述运算放大器的反相输入的接入参考电源，所述运算放大器的输出端连接所述第二mos管的栅极，所述第二mos管的漏极连接所述第一mos管的栅极，所述第二mos管的源极接地。The non-inverting input terminal of the operational amplifier is connected to the output voltage terminal, the inverting input of the operational amplifier is connected to a reference power supply, the output terminal of the operational amplifier is connected to the gate of the second mos tube, and the first The drain of the two mos tubes is connected to the grid of the first mos tube, and the source of the second mos tube is grounded.
  10. 根据权利要求9所述的合路缓启芯片，其特征在于，所述合路缓启电路还包括：第一电阻与第二电阻；The combined slow-start chip according to claim 9, wherein the combined slow-start circuit further comprises: a first resistor and a second resistor;
    所述输出电压端连接所述第一电阻的一端，所述第一电阻的另一端连接所述运算放大器的同相输入端与所述第二电阻的一端，所述第二电阻的另一端接地。The output voltage terminal is connected to one end of the first resistor, the other end of the first resistor is connected to the non-inverting input terminal of the operational amplifier and one end of the second resistor, and the other end of the second resistor is grounded.
  11. 根据权利要求8或9所述的合路缓启芯片，其特征在于，所述至少一个输入电源中包括第一输入电源与第二输入电源，所述合路缓启电路还包括第三mos管与第四mos管，所述合路缓启芯片还包括第二控制引脚与第三控制引脚；The combined slow-start chip according to claim 8 or 9, wherein the at least one input power supply includes a first input power and a second input power, and the combined slow-start circuit further includes a third mos tube With the fourth mos tube, the combined slow-start chip further includes a second control pin and a third control pin;
    所述第一输入电源的输出端连接所述第三mos管的源极，所述第三mos管的栅极连接所述第二控制引脚，所述第三mos管的漏极连接所述第一mos管的漏极；The output end of the first input power supply is connected to the source of the third mos tube, the gate of the third mos tube is connected to the second control pin, and the drain of the third mos tube is connected to the The drain of the first mos tube;
    所述第二输入电源的输出端连接所述第四mos管的源极，所述第四mos管的栅极连接所述第三控制引脚，所述第四mos管的漏极连接所述第一mos管的漏极。The output end of the second input power source is connected to the source of the fourth mos tube, the gate of the fourth mos tube is connected to the third control pin, and the drain of the fourth mos tube is connected to the The drain of the first mos tube.
  12. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-7中任一项所述的合路缓启电路。An electronic device, characterized in that the electronic device includes the combined slow-start circuit according to any one of claims 1-7.
  13. 一种电子设备，其特征在于，所述电子设备包括如权利要求8-11中任一项所述的合路缓启芯片。An electronic device, characterized in that the electronic device includes the combined slow-start chip according to any one of claims 8-11.
PCT/CN2018/119067 2018-12-04 2018-12-04 Combined soft-start circuit, combined soft-start chip and electronic device WO2020113402A1 (en)

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Citations (4)

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CN103218003A (en) * 2013-04-26 2013-07-24 无锡中星微电子有限公司 Low-dropout voltage stabilizer with multiple power sources input
CN103324233A (en) * 2013-05-29 2013-09-25 中科院微电子研究所昆山分所 Low pass filter and low dropout regulator
CN104699153A (en) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 Low-dropout linear regulator
CN105446404A (en) * 2014-08-19 2016-03-30 无锡华润上华半导体有限公司 Low dropout linear regulator circuit, chip and electric device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103218003A (en) * 2013-04-26 2013-07-24 无锡中星微电子有限公司 Low-dropout voltage stabilizer with multiple power sources input
CN103324233A (en) * 2013-05-29 2013-09-25 中科院微电子研究所昆山分所 Low pass filter and low dropout regulator
CN104699153A (en) * 2013-12-10 2015-06-10 展讯通信（上海）有限公司 Low-dropout linear regulator
CN105446404A (en) * 2014-08-19 2016-03-30 无锡华润上华半导体有限公司 Low dropout linear regulator circuit, chip and electric device

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