WO2020087363A1 - 测试*** - Google Patents

测试*** Download PDF

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Publication number
WO2020087363A1
WO2020087363A1 PCT/CN2018/113081 CN2018113081W WO2020087363A1 WO 2020087363 A1 WO2020087363 A1 WO 2020087363A1 CN 2018113081 W CN2018113081 W CN 2018113081W WO 2020087363 A1 WO2020087363 A1 WO 2020087363A1
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WO
WIPO (PCT)
Prior art keywords
branch
voltage drop
line
test
measured
Prior art date
Application number
PCT/CN2018/113081
Other languages
English (en)
French (fr)
Inventor
童天涯
沈丹禹
宋海宏
Original Assignee
深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to PCT/CN2018/113081 priority Critical patent/WO2020087363A1/zh
Priority to CN201880002014.3A priority patent/CN109564264B/zh
Publication of WO2020087363A1 publication Critical patent/WO2020087363A1/zh
Priority to US16/941,761 priority patent/US11486955B2/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/02—Testing or calibrating of apparatus covered by the other groups of this subclass of auxiliary devices, e.g. of instrument transformers according to prescribed transformation ratio, phase angle, or wattage rating
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31924—Voltage or current aspects, e.g. driver, receiver
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
    • G01R31/2889—Interfaces, e.g. between probe and tester
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31905—Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
    • G01R31/67—Testing the correctness of wire connections in electric apparatus or circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks

Definitions

  • the embodiments of the present application relate to the technical field of circuits, and in particular, to provide a test system for integrated circuits.
  • the equipment power supply of the automated test equipment ATE is often electrically connected to the object to be tested (Device Under Test, DUT for short) ).
  • the power supply of the device is usually equipped with a drive line (also called FORCE line, hereinafter referred to as F line) and a detection line (also referred to as SENSE line, hereinafter referred to as S line).
  • the F line is mainly used to transmit the driving current to the DUT to be tested
  • the S line is mainly used to detect whether the real driving voltage reaching the DUT to meet the voltage required for the DUT to work normally.
  • one of the technical problems solved by the embodiments of the present application is to provide a testing system to overcome the above-mentioned defects in the prior art.
  • An embodiment of the present application provides a test system, which includes: a first test device and a second test device, and a power supply of the first test device is electrically connected to an object to be tested through a driving branch and a detection branch.
  • the driving branch is used to provide the original driving current to the object to be tested through the power supply during the test
  • the detection branch is used to detect the effective driving current reaching the object to be tested
  • the second testing device includes a first voltage A drop branch, the first pressure drop branch is connected to the detection branch, and the pressure drop detected by the drive branch is used to determine the drive branch, the detection branch, and the object to be measured The effectiveness of making electrical connections.
  • the detection branch forms an effective electrical connection with the object to be measured.
  • the object to be measured includes a second voltage drop branch and the original drive current is in a negative phase, if the voltage drop detected by the drive circuit is If the pressure drop of the first pressure drop branch in the object to be measured, then all the detection branches do not form an effective electrical connection with the object to be measured.
  • the object to be measured includes a second voltage drop branch and the original drive current is in a negative phase
  • the voltage drop detected by the drive circuit is When the clamping voltage of the first test device is established, the driving branch and the object to be tested do not form an effective electrical connection.
  • the driving branch or the detection circuit and the object to be tested do not form an effective electrical connection.
  • the first voltage drop branch includes a first switching device and a second switching device, an anode of the first switching device is grounded, and a cathode of the first switching device It is connected to one end of the second switching device, and the other end of the second switching device is connected to the detection branch.
  • the detection branch forms an effective electrical connection with the object to be measured.
  • the object to be measured includes a second voltage drop branch and the original drive current is a positive phase
  • the voltage drop detected by the drive circuit is If the pressure drop of the first pressure drop branch in the object to be measured, the detection branch does not form an effective electrical connection with the object to be measured.
  • the object to be measured includes a second voltage drop branch and the original drive current is a positive phase
  • the voltage drop detected by the drive circuit is When the clamping voltage of the first test device is established, the driving branch and the object to be tested do not form an effective electrical connection.
  • the driving branch or the detection circuit and the object to be tested do not form an effective electrical connection.
  • the first voltage drop branch includes a first switching device and a second switching device, the negative electrode of the first switching device is grounded, and the positive electrode of the first switching device It is connected to one end of the second switching device, and the other end of the second switching device is connected to the detection branch.
  • the second test device is provided on a test board for building a function / performance test on the chip.
  • the test system since the test system includes a first test device and a second test device, the power supply of the first test device is electrically connected to the object to be tested through the drive branch and the detection branch, and the drive branch is used During the test, the original driving current is provided to the object to be tested through the power supply, and the detection branch is used to detect the effective driving current reaching the object to be tested; the second test device includes a first voltage drop branch, The first pressure drop branch is connected to the detection branch, and the pressure drop detected by the drive branch determines the drive branch, the detection branch and the object to be measured are electrically connected Effectiveness.
  • FIG. 1 is a schematic structural diagram of a test system according to Embodiment 1 of the present application.
  • FIG. 2 is a schematic structural diagram of a test system according to Embodiment 2 of the present application.
  • FIG. 3 is a schematic structural diagram of a test system according to Embodiment 3 of the present application.
  • FIG. 4 is a schematic structural diagram of a test system according to Embodiment 4 of the present application.
  • FIG. 5 is a schematic structural diagram of a test system according to Embodiment 5 of the present application.
  • FIG. 6 is a schematic structural diagram of a test system according to Embodiment 6 of the present application.
  • the power supply of the first test device is electrically connected to the object to be tested through a drive branch and a detection branch, and the drive branch is used to pass the power supply during testing Providing an original driving current to the object to be measured, the detection branch is used to detect an effective driving current reaching the object to be measured; the second test device includes a first pressure drop branch, the first pressure drop branch It is connected to the detection branch, and the pressure drop detected by the drive branch determines the effectiveness of the electrical connection between the drive branch, the detection branch, and the object to be measured.
  • the corresponding DUT to be tested is a chip to be tested
  • the first test device is an automated test equipment ATE.
  • the driver The branch is the F-line
  • the detection branch is the S-line.
  • the above-mentioned second test device may be independent of the test board (load board) (abbreviated as LB).
  • the second test device is directly integrated directly on the test board.
  • the test board LB not only needs related circuit configuration based on the function / performance test of the chip, but also configures the circuit based on the validity detection of the electrical connection formed between the detection branch and the object to be tested.
  • the first voltage drop branch including a first switching device (such as a diode) and a second switching device (such as a relay) as an example, and the first and second switching devices are specifically in the circuit Exemplary descriptions will be made on different setting positions and different numbers of the first pressure drop branch.
  • the second switching device may refer to a switching device capable of achieving unidirectional conduction performance.
  • the second voltage drop branch specifically includes a first switching device (such as a diode)
  • the diode in the second voltage drop branch may specifically be a diode in an electrostatic discharge circuit (Electro-Static Discharge, ESD for short) in the chip to be tested.
  • the positive test drive current also called the original drive current is positive phase
  • the negative test drive current is provided to the chip under test (Also called the original drive current is negative phase) when the electrical connection validity test.
  • FIG. 1 is a schematic structural diagram of a test system according to Embodiment 1 of the present application; in this embodiment, an electrical connection validity test is performed when a negative-phase driving current is provided to a chip under test by a power supply DPS of an automatic test equipment ATE, correspondingly,
  • the second test device includes only one first voltage drop branch (which includes diode D2 and relay K2), and the chip DUT includes a second voltage drop branch (which includes diode D4).
  • the diode D2 in the first voltage drop branch The anode is grounded, the cathode of the diode D2 is connected to one end of the relay K2, and at the same time, the other end of the relay K2 is connected to the S line; at the same time, the anode of the diode D4 in the second voltage drop branch is grounded and its cathode Connect to the PAD of the chip to be tested.
  • the F and S lines must form an effective electrical connection with the PAD of the chip under test.
  • the pressure drop detected through the F line may determine whether the F line, the S line and the PAD of the chip under test are actually in contact to form an effective electrical connection Assuming that there is no open or short circuit of the diode in the first voltage drop branch, the specific process is as follows:
  • Negative phase drive current is provided to the chip under test through the power supply (Device Power Supply, DPS) of the automated test equipment ATE.
  • DPS Device Power Supply
  • FIG. 1 due to the negative phase drive current, in the circuit structure of FIG. 1, the current flow direction
  • the power supply DPS flowing from the chip to be tested to the automated test equipment is shown as the arrow from left to right when viewed on line F in FIG. 1; at the same time, the relay in the second test device is controlled by the automated test equipment ATE K2 is closed. Therefore, if the S line is in good contact with the PAD of the chip under test, it will turn on the diode D2 and a corresponding voltage drop will occur.
  • the diode D2 in the second test device uses a germanium diode (the voltage when it is turned on) Just drop it to about 0.3V).
  • a voltage drop (corresponding to the voltage drop of a certain diode conduction) can be detected on the F line, it indicates that the F line has good contact with the PAD of the chip under test to form an effective electrical connection, otherwise, it is The voltage drop corresponding to the conduction of a certain diode (D2 or D4) cannot be detected through the F line.
  • the detected voltage drop is equal to the voltage drop of the germanium diode (that is, D2), it indicates that there is good contact between the S line and the PAD of the chip under test to form an effective electrical connection; if it is detected The voltage drop is equal to the voltage drop of the silicon diode (that is, D4), which indicates that there is no good contact between the S line and the PAD of the chip under test and no effective electrical connection is formed. If the detected voltage drop is equal to the clamping voltage of the automated testing equipment ATE, it indicates that there is no good contact between the F line and the PAD of the chip under test, and at this time between the S line and the PAD of the chip under test Whether a good contact is formed needs further confirmation.
  • the detected voltage drop is equal to the voltage drop of the germanium diode, it indicates that there is good contact between the S line and the PAD of the chip under test to form an effective electrical connection.
  • the detailed explanation is as follows: In theory, if S The line forms an effective electrical connection with the chip under test DUT, but since the voltage drop of the silicon diode is greater than the voltage drop of the germanium diode, the germanium diode is conducting and the silicon diode is not conducting. At this time, pass The voltage drop detected by the F line can only correspond to the situation where the germanium diode is turned on, and this situation will only occur if the S line has formed an effective electrical connection with the chip under test.
  • the diode D2 in the second test device is selected to be conductive when the voltage drop is greater than the voltage drop when the silicon diode D4 in the chip under test is selected, when the S line is in good contact with the PAD of the chip under test, The silicon diode D4 in the chip under test is turned on and the diode in the second test device is not turned on.
  • the voltage drop detected through the F line corresponds to the situation in which the silicon diode in the chip under test is turned on; When the PAD of the chip under test is in poor contact, the voltage drop detected through the F line can only correspond to the situation where the silicon diode in the chip under test is turned on.
  • the voltage drop is greater than the voltage drop of the silicon diode in the chip under test.
  • the F line detects The voltage drop is the voltage drop of the silicon diode in the chip under test. In other words, whether the S line is in good contact with the PAD of the chip under test, it will not cause the voltage drop detected on the F line to be different, and then it will not Determine whether the S line is in good contact with the PAD of the chip under test.
  • the diodes in the first voltage drop branch in the second test device can also be tested for open and short circuits.
  • the details are as follows:
  • the diode D2 in the second test device has an open circuit. At this time, it is preferred to determine whether there is good contact between the S line and the PAD of the chip under test. For example, use a multimeter to measure the resistance between the F line and the S line. There is no good contact between them. If the measured resistance is 0 ohms, it means that the F line and the S line are in good contact with the PAD. If it is confirmed that the contact between the S line and the PAD of the chip to be tested is good, it is determined that the diode D2 in the second test device has a short circuit.
  • FIG. 2 is a schematic structural diagram of a test system according to the second embodiment of the present application; in this embodiment, the electrical connection validity test is performed when the negative-phase drive current is supplied to the chip under test by the power supply DPS of the automatic test equipment ATE, correspondingly,
  • the second test device includes only one first pressure drop branch, but, unlike the embodiment of FIG. 1 described above, the chip to be tested DUT does not include the second pressure drop branch as an example for description.
  • the diode D2 in the first voltage drop branch Is connected to the positive pole of the diode the negative pole of the diode is connected to one end of the relay K2, and at the same time, the other end of the relay K2 is connected to the S line.
  • the F and S lines must form an effective electrical connection with the PAD of the DUT to be tested.
  • the voltage drop detected by the F line may determine whether the F line, the S line and the PAD of the chip DUT to be tested are actually in contact to form an effective electricity
  • the specific process is as follows.
  • the negative-phase drive current is provided to the chip under test DUT through the power supply DPS of the automated test equipment ATE. As shown in FIG. 2, because of the negative-phase drive current, the current flow actually flows from the chip under test to the automated test equipment ATE The power supply DPS, as shown by the arrow from left to right on the F line in FIG. 2; at the same time, the relay K2 in the second test device is controlled to be closed by the automatic test equipment ATE.
  • the table just proves that the S line is waiting
  • the PAD of the chip under test DUT is in good contact, and the F line is also in good contact with the PAD of the chip under test DUT, thereby forming an effective electrical connection.
  • the detected voltage drop is equal to the clamping voltage of the automated testing equipment ATE, it indicates that there is no good contact between the F line and the PAD of the chip under test DUT, and the S line and the chip under test at this time Whether good contact is formed between the PADs remains to be determined. For example, when it shows that there is no good contact between the F line and the PAD of the chip under test DUT, first solve the problem of no good contact between the F line and the PAD of the chip under test, and then further determine the S line and the under test Whether good contact is formed between the PAD of the chip DUT.
  • test of the open and short circuit of the diode in the first voltage drop branch in the second test device is as follows:
  • the relay K2 When the relay K2 is turned on, the negative phase drive current is provided through the F line, and the voltage drop detected by the F line is 0V (ground level), then it is determined that the F line, the S line and the PAD of the chip under test are formed A good contact is made and the diode D2 in the second test device is short-circuited. If the voltage drop detected by the F line is the clamping voltage, it indicates that there is no good contact between the F line or the S line and the PAD of the chip under test or the diode D2 in the second test device has an open circuit. At this time, determine whether the F line, S line and the PAD of the chip to be tested are in good contact. For example, use a multimeter to measure the resistance between the F line and the S line.
  • the measured resistance is infinite, it means the F line or the S line There is no good contact with the PAD of the chip under test. If the measured resistance is 0 ohms, it means that the F line and the S line are in good contact with the PAD. If it is confirmed that the contact between the F line, the S line and the PAD of the chip to be tested is good, it is determined that the diode D2 in the second test device has an open circuit.
  • FIG. 3 is a schematic structural diagram of a test system according to Embodiment 3 of the present application; in this embodiment, the electrical connection validity test is performed when the power supply DPS of the automatic test equipment ATE is used to provide the normal-phase driving current to the chip DUT to be tested.
  • the second test device includes only a first voltage drop branch (which includes the diode D1 and the relay K1), and the chip DUT includes a second voltage drop branch (which includes the diode D3).
  • the diode D1 in the first voltage drop branch The anode of the diode D1 is grounded, and the anode of the diode D1 is connected to one end of the relay K1. At the same time, the other end of the relay K1 is connected to the S line; therefore, at the same time, the cathode of the diode in the second voltage drop branch is grounded and its The positive electrode is connected to the PAD of the chip under test DUT.
  • the specific detection process is as follows.
  • the power supply DPS of the automatic test equipment ATE provides the positive-phase drive current to the chip under test DUT, as shown in FIG. DUT, as shown by the arrow from right to left on the F line in FIG. 3; at the same time, the relay K1 in the second test device is controlled to be closed by the automated test equipment ATE. Therefore, if the S line is connected to the DUT If the PAD is in good contact, it will be turned on and the corresponding voltage drop will be generated. In order to make the voltage drop detected on the F line be the voltage drop in the first test device, so in the selection, the diode D1 Preferably, the diode having a voltage drop when it is turned on is smaller than the voltage drop when the diode D3 in the second test device is turned on.
  • the diode D3 in the second test device is often a silicon diode (the voltage drop during conduction is about 0.6V)
  • the diode D1 in the second test device uses a germanium diode (the voltage during conduction) Just drop it to about 0.3V).
  • a voltage drop (corresponding to the voltage drop of a certain diode conduction) can be detected on the F line, it indicates that the F line has good contact with the PAD of the chip DUT to be tested to form an effective electrical connection, otherwise, It is because the voltage drop corresponding to a certain diode conduction cannot be detected through the F line, and only the clamping voltage of the automatic detection device ATE can be detected.
  • the detected voltage drop is equal to the voltage drop of the germanium diode D1, it indicates that there is good contact between the S line and the PAD of the chip DUT to form an effective electrical connection; if the detected voltage drop It is equal to the voltage drop of the silicon diode, indicating that there is no good contact between the S line and the PAD of the chip DUT to be tested and no effective electrical connection is formed. If the detected voltage drop is equal to the clamping voltage of the automated testing equipment ATE, it indicates that there is no good contact between the F line and the PAD of the chip under test DUT, and the S line and the PAD of the chip under test at this time Whether a good contact is formed remains to be determined.
  • the detected voltage drop is equal to the voltage drop of the germanium diode D1, it indicates that there is good contact between the S line and the PAD of the chip under test DUT and an effective electrical connection can be formed.
  • FIG. 1 see FIG. 1 above.
  • the voltage drop is greater than the voltage drop of the silicon diode in the DUT under test, regardless of whether the S line is in good contact with the PAD of the DUT under test, detected by the F line
  • the voltage drop is the voltage drop of the silicon diode D3 in the chip DUT under test. In other words, whether the S line is in good contact with the PAD of the chip DUT under test will not cause the voltage drop detected on the F line to be different. Furthermore, it is impossible to determine whether the S line is in good contact with the PAD of the chip under test DUT. For details, see the description in FIG. 1 above.
  • test of the open and short circuit of the diode in the first voltage drop branch in the second test device is as follows:
  • the positive-phase drive current is provided through the F line, and the voltage drop detected by the F line is the voltage drop of the diode D3 in the second voltage drop branch (about 0.6V), indicating that it is connected to the PAD of the chip under test.
  • the relay K1 is turned on, the positive drive current is provided through the F line, and the voltage drop detected by the F line is 0V (ground level), then the F line, S line and The PAD of the chip to be tested makes good contact and the diode D1 in the second test device is short-circuited.
  • the voltage drop detected by the F line when the relay K1 is turned on is the voltage drop of the diode D3 in the second voltage drop branch (about 0.6V), it indicates that there is no good formation between the S line and the PAD of the chip under test Or the diode D1 in the second test device has an open circuit.
  • FIG. 4 is a schematic structural diagram of a test system according to Embodiment 4 of the present application; in this embodiment, the electrical connection validity test is performed when the positive-phase driving current is supplied to the chip under test by the power supply DPS of the automatic test equipment ATE, correspondingly,
  • the second test device includes only one first voltage drop branch (which includes the diode D1 and the relay K1), but, unlike the above embodiment of FIG. 3, the chip under test DUT does not include the second voltage drop branch as Examples.
  • the specific detection process is as follows.
  • the power supply DPS of the automatic test equipment ATE provides the positive phase drive current to the chip under test DUT.
  • DUT as shown by the arrow from right to left at line F in FIG. 4; at the same time, the relay K1 in the second test device is controlled to be closed by the automated test equipment ATE.
  • the S line is connected to the chip DUT under test
  • the PAD is in good contact, and if the voltage drop corresponding to the diode voltage drop can be detected on the F line, and this voltage drop corresponds to the voltage drop when the diode D2 in the second test device is turned on, it just proves that the S line is under test
  • the PAD of the chip DUT is in good contact, and the F line is also in good contact with the PAD of the chip DUT to be tested, thereby forming an effective electrical connection.
  • the detected voltage drop is equal to the clamping voltage of the automated testing equipment ATE, it indicates that there is no good contact between the F line and the PAD of the chip under test DUT, and the S line and the chip under test at this time Whether good contact is formed between the PADs remains to be determined. For example, when it shows that there is no good contact between the F line and the PAD of the chip under test DUT, first solve the problem of no good contact between the F line and the PAD of the chip under test, and then further determine the S line and the under test Whether good contact is formed between the PAD of the chip DUT.
  • the test of the open and short circuit of the diode in the first voltage drop branch in the second test device is similar to the above-mentioned first embodiment.
  • the relay K1 When the relay K1 is turned on, the positive phase drive current is provided through the F line, and the voltage drop detected by the F line is 0V (ground level), then it is determined that the F line, the S line and the PAD of the chip under test are formed A good contact is made and the diode D1 in the second test device is short-circuited. If the voltage drop detected by the F line is the clamping voltage, it indicates that there is no good contact between the F line or the S line and the PAD of the chip under test or the diode D1 in the second test device has an open circuit. At this time, determine whether the F line, S line and the PAD of the chip to be tested are in good contact. For example, use a multimeter to measure the resistance between the F line and the S line.
  • the measured resistance is infinite, it means the F line or the S line There is no good contact with the PAD of the chip under test. If the measured resistance is 0 ohms, it means that the F line and the S line are in good contact with the PAD. If it is confirmed that the contact between the S line and the PAD of the chip to be tested is good, it is determined that the diode D1 in the second test device has an open circuit.
  • the second test device includes two first voltage drop branches, one of which is a diode in the first voltage drop branch D2, the connection mode of the relay K2 is shown in Figure 1, and the connection mode of the diode D1 and the relay K1 in the other first voltage drop branch is shown in Figure 3.
  • the chip under test also includes two second voltages in the chip DUT The connection mode of the diode D4 in one of the second voltage drop branches is shown in FIG. 1, and the connection mode of the diode D3 in the second voltage drop branch is shown in FIG. 3.
  • the negative phase drive current or the positive phase drive current can be provided by the power supply DPS to test the effectiveness of the electrical connection.
  • the negative-phase driving current and the positive-phase driving current, or the positive-phase driving current and the negative-phase driving current may be provided in sequence, and the results of the two tests are used to review each other.
  • the test of the open and short circuit of the diode in the first voltage drop branch in the second test device is similar to the above-mentioned first embodiment.
  • FIG. 6 is a schematic structural diagram of a test system according to Embodiment 6 of the present application; as shown in FIG. 6, in this embodiment, the second test device includes two first voltage drop branches, one of which is a diode in the first voltage drop branch
  • the connection mode of D2 and relay K2 is shown in FIG. 1, and the connection mode of diode D1 and relay K1 in another first voltage drop branch is shown in FIG. 3, and the second voltage drop branch is not included in the chip under test DUT.
  • the negative phase drive current or the positive phase drive current can be provided by the power supply DPS to test the effectiveness of the electrical connection.
  • the negative-phase driving current and the positive-phase driving current, or the positive-phase driving current and the negative-phase driving current may be provided in sequence, and the results of the two tests are used to review each other.
  • test of the open and short circuit of the diode in the first voltage drop branch in the second test device is similar to the above-mentioned first embodiment, please refer to the description of the above-mentioned embodiments 2 and 4 for details.
  • the automated test equipment ATE will adjust the drive transmitted through the F line according to the actual drive current detected by the S line Current, so that the real drive current to the DUT to meet the needs of the DUT to work properly.
  • the voltage can be configured to 0V, here, through the F line detection
  • the voltage drop directly corresponds to the voltage drop of the diode, for example, 0.3V or 0.6V.
  • the voltage drop measured by the F line is the clamping voltage.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.
  • computer usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • These computer program instructions can be provided to the processor of a general-purpose computer, special-purpose computer, embedded processing machine, or other programmable data processing device to produce a machine that enables the generation of instructions executed by the processor of the computer or other programmable data processing device
  • These computer program instructions may also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, the instructions The device implements the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.
  • These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are performed on the computer or other programmable device to produce computer-implemented processing, which is executed on the computer or other programmable device
  • the instructions provide steps for implementing the functions specified in one block or multiple blocks of the flowchart one flow or multiple flows and / or block diagrams.
  • the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.
  • processors CPUs
  • input / output interfaces output interfaces
  • network interfaces network interfaces
  • memory volatile and non-volatile memory
  • the memory may include non-permanent memory, random access memory (RAM) and / or non-volatile memory in computer-readable media, such as read only memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.
  • RAM random access memory
  • ROM read only memory
  • flash RAM flash memory
  • Computer-readable media including permanent and non-permanent, removable and non-removable media, can store information by any method or technology.
  • the information may be computer readable instructions, data structures, modules of programs, or other data.
  • Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, read-only compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, Magnetic tape cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media can be used to store information that can be accessed by computing devices.
  • computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data signals and carrier waves.
  • the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Moreover, the present application may take the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.
  • computer usable storage media including but not limited to disk storage, CD-ROM, optical storage, etc.
  • the present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules.
  • program modules include routines, programs, objects, components, data structures, etc. that perform specific transactions or implement specific abstract data types.
  • the present application may also be practiced in distributed computing environments in which remote processing devices connected through a communication network execute transactions.
  • program modules may be located in local and remote computer storage media including storage devices.

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Abstract

一种测试***，包括第一测试装置（ATE）以及第二测试装置（LB），所述第一测试装置（ATE）的电源通过驱动支路（F）、检测支路（S）与待测对象（DUT）形成电连接，所述驱动支路（F）用于在测试时通过所述电源向待测对象（DUT）提供原始驱动电流，所述检测支路（S）用于检测到达所述待测对象（DUT）的有效驱动电流；所述第二测试装置（LB）包括第一压降支路，所述第一压降支路与所述检测支路(S)连接，通过所述驱动支路（F）检测到的压降以确定所述检测支路（S）与所述待测对象（DUT）形成电连接的有效性。

Description

测试*** 技术领域
本申请实施例涉及电路技术领域，尤其涉及提供一种针对集成电路的测试***。
背景技术
在使用自动化测试设备(Automatic test equipment，简称ATE)对集成电路(Integrated circuit，简称IC)进行测试时，经常会将自动化测试设备ATE的设备电源电连接到待测对象(Device Under Test，简称DUT)。为实现与待测对象DUT的电连接，设备电源通常配置有驱动线(又称之为FORCE线，以下简称F线)和检测线(又称之为SENSE线，以下简称S线)。F线主要用于给待测对象DUT传输驱动电流，S线主要用于检测到达待测对象DUT的真实驱动电压是否满足待测对象DUT正常工作所需的电压。
由上述可见，为了保证在测试的过程中，通过上述F线给待测对象DUT传输驱动电流，通过上述S线检测到达待测对象DUT的真实驱动电压是否满足待测对象DUT正常工作所需的电压，一旦S线与待测对象DUT没有形成有效电连接，就会导致无法检测到达待测对象DUT的真实驱动电压是否满足待测对象DUT正常工作所需的电压，因此需要提供一种技术方案以测试F线、S线与待测对象DUT之间是否形成了有效电连接。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种测试***，用以克服现有技术中上述缺陷。
本申请实施例提供了一种测试***，其包括：第一测试装置以及第二测试装置，所述第一测试装置的电源通过驱动支路、检测支路与待测对象形成电连接，所述驱动支路用于在测试时通过所述电源向待测对象提供原始驱动电流，所述检测支路用于检测到达所述待测对象的有效驱动电流；所述第二测试装置包括第一压降支路，所述第一压降支路与所述检测支路连接，通过所述驱动支路检测到的压降以确定所述驱动支路、所述检测支路与所述待测对象形成电连 接的有效性。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一压降支路的压降，则所述检测支路与所述待测对象形成了有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述待测对象中第一压降支路的压降，则所述检测支路均与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象不包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路或者所述检测电路与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，所述第一压降支路包括第一开关器件以及第二开关器件，所述第一开关器件的正极接地，所述第一开关器件的负极与第二开关器件的一端连接，且所述第二开关器件的另一端与所述检测支路连接。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一压降支路的压降，则所述检测支路与所述待测对象形成了有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述待测对象中第一压降支路的压降，则所述检测支路与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，若所述待测对象不包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路或者所述检测电路与所述待测对象未形成有效的电连接。
可选地，在本申请的一实施例中，所述第一压降支路包括第一开关器件以及第二开关器件，所述第一开关器件的负极接地，所述第一开关器件的正极与第二开关器件的一端连接，且所述第二开关器件的另一端与所述检测支路连接。
可选地，在本申请的一实施例中，所述第二测试装置设置在用于搭建对芯片进行功能/性能测试的测试板上。
本申请实施例中，由于测试***包括第一测试装置以及第二测试装置，所述第一测试装置的电源通过驱动支路、检测支路与待测对象形成电连接，所述驱动支路用于在测试时通过所述电源向待测对象提供原始驱动电流，所述检测支路用于检测到达所述待测对象的有效驱动电流；所述第二测试装置包括第一压降支路，所述第一压降支路与所述检测支路连接，通过所述驱动支路检测到的压降以确定所述驱动支路、所述检测支路与所述待测对象形成电连接的有效性。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为本申请实施例一测试***的结构示意图；
图2为本申请实施例二测试***的结构示意图；
图3为本申请实施例三测试***的结构示意图；
图4为本申请实施例四测试***的结构示意图；
图5为本申请实施例五测试***的结构示意图；
图6为本申请实施例六测试***的结构示意图。
具体实施方式
实施本申请实施例的任一技术方案必不一定需要同时达到以上的所有优点。
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请实施例一部分实施例，而不是全部的实施例。 基于本申请实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
本申请下述实施例提供的测试***中，所述第一测试装置的电源通过驱动支路、检测支路与待测对象形成电连接，所述驱动支路用于在测试时通过所述电源向待测对象提供原始驱动电流，所述检测支路用于检测到达所述待测对象的有效驱动电流；所述第二测试装置包括第一压降支路，所述第一压降支路与所述检测支路连接，通过所述驱动支路检测到的压降以确定所述驱动支路、所述检测支路与所述待测对象形成电连接的有效性。
下述实施例中，以将上述测试***应用到测试集成电路IC领域为例进行说明，对应的待测对象DUT为待测芯片，第一测试装置为自动化测试设备ATE，进一步地，所述驱动支路即为F线，检测支路即为S线，而在对待测芯片进行测试时，F线、S线要与待测芯片上的焊脚(又称之PAD)进行有效的电连接。
上述第二测试装置可以独立于测试板(loadBoard，简称LB)之外，但是，处于成本以及紧凑度考虑，下述实施例中直接将第二测试装置直接集成在测试板，因此，相当于所述测试板LB除了要基于搭建对芯片进行功能/性能测试而进行相关的电路配置，也要基于对所述检测支路与所述待测对象形成的电连接进行有效性检测而配置电路。
另外，下述实施例中，将从如下角度进行区分：
(1)以所述第一压降支路包括第一开关器件(如二极管)以及第二开关器件(如继电器)为例，以及该第一开关器件以及第二开关器件具体在电路的中的不同设置位置以及该第一压降支路的不同设置数量进行示例性说明。本实施例中，第二开关器件可以是指能实现单向导通性能的开关器件。
(2)结合所述待待测芯片中是否同样包括第二压降支路进行示例性说明，若包括，则第二压降支路具体包括一第一开关器件(如二极管)进行示例性说明，所述第二压降支路中的二极管具体可以为待测芯片中静电释放电路(Electro-Static discharge，简称ESD)中的二极管。
(3)通过自动化测试设备ATE的电源向待测芯片提供正相驱动电流(又称之为原始驱动电流为正相)时进行电连接有效性的测试，或者向待测芯片提供负相驱动电流(又称之为原始驱动电流为负相)时进行电连接有效性的测试。
图1为本申请实施例一测试***的结构示意图；本实施例中，以通过自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流时进行电连接有效性的测试，对应地，以第二测试装置只包括一条第一压降支路(其包括二极管D2和继电器K2)、同时待测芯片DUT中包括一条第二压降支路(其包括二极管D4)为例进行说明。
具体地，如图1所示，由于自动化测试设备ATE的电源DPS向待测芯片提供负相驱动电流时进行电连接有效性的测试，因此，第一压降支路中的所述二极管D2的正极接地，所述二极管D2的负极与继电器K2的一端连接，与此同时，继电器K2的另外一端与S线连接；同时，第二压降支路中的所述二极管D4的正极接地且其负极与待测芯片的PAD连接。如前所述，要对待测芯片进行有效的测试，F线、S线必须与待测芯片的PAD形成有效的电连接。而由于在S线上连接有第一压降支路，因此，通过F线检测到的压降，即可能确定出F线、S线与待测芯片的PAD是否真正接触以形成有效的电连接，假设第一压降支路中二极管不存在开短路，具体过程具体如下：
通过自动化测试设备ATE的电源(Device Power Supplies，简称DPS)向待测芯片提供负相驱动电流，如图1所示，由于是负相驱动电流，在上述图1的电路结构中，电流的流向实际上从待测芯片流向自动化测试设备的电源DPS，即如图1中F线上看的话从左至右的箭头所示；与此同时，通过自动化测试设备ATE控制第二测试装置中的继电器K2闭合，因此，如果S线与待测芯片的PAD接触良好则其就会导通二极管D2继而会产生对应的压降。为了能使得在F线上检测到的压降即为第二测试装置中的二极管D2的压降，所以，对于二极管D2来说，在选型时，优选当导通时压降小于待测芯片DUT中的二极管D4导通时压降的二极管。在实际应用场景中，由于待测芯片DUT中的二极管D4往往是硅二极管(导通时的压降大约为0.6V)，因此第二测试装置中的二极管D2选用锗二极管(导通时的压降大约为0.3V)即可。
进一步地，如果能在F线上检测到压降(对应某个二极管导通的压降)，则表明F线与待测芯片的PAD具有良好的接触进而可形成有效的电连接，否则，是通过F线无法检测到对应某个二极管(D2或者D4)导通的压降。
进一步地，如果检测到的压降等于所述锗二极管(即D2)的压降，则表明S线与待测芯片的PAD之间具有良好的接触进而可形成有效的电连接；如果检测到的压降等于所述硅二极管(即D4)的压降，则表明S线与待测芯片的PAD之间不具有良好的接触进而未形成有效的电连接。如果检测到的压降等于所述 自动化检测设备ATE的钳位电压，则表明F线与待测芯片的PAD之间未形成良好的接触，而此时至于S线与待测芯片的PAD之间是否形成良好的接触有待进一步确定。比如，当表明F线与待测芯片的PAD之间未形成良好的接触后，首先解决F线与待测芯片的PAD之间未形成良好的接触的问题，再进一步确定S线与待测芯片的PAD之间是否形成良好的接触。
对于如果检测到的压降等于所述锗二极管的压降，则表明S线与待测芯片的PAD之间具有良好的接触进而可形成有效的电连接，详细解释如下：理论上，如果说S线与待测芯片DUT形成了有效的电连接，但是由于硅二极管的压降大于所述锗二极管的压降，因此，所述锗二极管导通而所述硅二极管未导通，此时，通过F线检测到的压降只能对应到所述锗二极管导通的情形，而只有S线与待测芯片形成了有效的电连接，才会出现此种情形。
相反，如果在选型时，第二测试装置中的二极管D2选用导通时压降大于待测芯片中硅二极管D4导通的压降，则当S线与待测芯片的PAD接触良好时，待测芯片中的硅二极管D4导通而所述第二测试装置中的二极管未导通，通过F线检测到的压降对应待测芯片中的硅二极管导通的情形；而当S线与待测芯片的PAD接触不良时，通过F线检测到的压降只能对应待测芯片中的硅二极管导通的情形。由此可见，当第二测试装置中的二极管选用导通时压降大于待测芯片中硅二极管导通的压降，无论S线是否与待测芯片的PAD接触良好，通过F线检测到的压降均是待测芯片中硅二极管导通的压降，换言之，S线是否与待测芯片的PAD接触良好，并不会导致在F线检测到的压降会有不同，进而也就无法确定出S线是否与待测芯片的PAD接触良好。
在上述实施例中，还可以对第二测试装置中的第一压降支路中的二极管开短路情况进行测试。详细如下：
继电器K2断开时，通过F线提供负相驱动电流，而F线检测到的压降为第二压降支路中的二极管D4的压降(0.6V左右)，表明第二压降支路中的二极管D4没有出现开短路；之后，继电器K2导通时，通过F线提供驱动负相电流，而F线检测到的压降为0V(接地电平)，则此时确定出第二测试装置中的二极管D2出现短路。若在继电器K2导通时，而F线检测到的压降为第二压降支路中的二极管D4的压降(0.6V左右)，表明S线与待测芯片的PAD之间没有形成良好的接触或者第二测试装置中的二极管D2出现了开路情形。此时优先确定S线与待测芯片的PAD之间是否形成良好的接触，比如使用万用表测量F线与S线之间的电阻，如果测量的电阻为无穷大，表示S线与待测芯片 的PAD之间没有形成良好的接触，如果测量的电阻为0欧姆，表示F线和S线都和PAD接触良好。若确认S线和待测芯片的PAD之间接触良好，则确定出第二测试装置中的二极管D2出现短路。
图2为本申请实施例二测试***的结构示意图；本实施例中，以通过自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流时进行电连接有效性的测试，对应地，以第二测试装置只包括一条第一压降支路，但是，与上述图1实施例不同的是，待测芯片DUT并不包括第二压降支路为例进行说明。
具体地，如图2所示，由于自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流时进行电连接有效性的测试，因此，第一压降支路中的所述二极管D2的正极接地，所述二极管的负极与继电器K2的一端连接，与此同时，继电器K2的另外一端与S线连接。与此同时，如前所述，要对待测芯片DUT进行有效的测试，F线、S线必须与待测芯片DUT的PAD形成有效的电连接。而由于在S线上连接有第一压降支路，因此，通过F线检测到的压降，即可能确定出F线、S线与待测芯片DUT的PAD是否真正接触以形成有效的电连接，假设第一压降支路中二极管不存在开短路，具体过程具体如下。
通过自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流，如图2所示，由于是负相驱动电流，因此，电流的流向实际上从待测芯片DUT流向自动化测试设备ATE的电源DPS，即如图2中F线上从左至右的箭头所示；与此同时，通过自动化测试设备ATE控制第二测试装置中的继电器K2闭合，因此，如果S线与待测芯片DUT的PAD接触良好，同时如能在F线上检测到压降对应二极管的压降，且该压降对应第二测试装置中的二极管D2导通时的压降，则表恰好证明S线与待测芯片DUT的PAD之间接触良好，且F线也与待测芯片DUT的PAD之间接触良好，进而形成了有效的电连接。反之，如果检测到的压降等于所述自动化检测设备ATE的钳位电压，则表明F线与待测芯片DUT的PAD之间未形成良好的接触，而此时至于S线与待测芯片DUT的PAD之间是否形成良好的接触有待进一步确定。比如，当表明F线与待测芯片DUT的PAD之间未形成良好的接触后，首先解决F线与待测芯片DUT的PAD之间未形成良好接触的问题，再进一步确定S线与待测芯片DUT的PAD之间是否形成良好的接触。
对第二测试装置中的第一压降支路中的二极管开短路情况进行测试详细如下：
继电器K2导通时，通过F线提供负相驱动电流，而F线检测到的压降为0V(接地电平)，则此时确定出F线、S线与待测芯片的PAD之间形成了良好的接触且第二测试装置中的二极管D2出现短路。若而F线检测到的压降为钳位电压，表明F线或者S线与待测芯片的PAD之间没有形成良好的接触或者第二测试装置中的二极管D2出现了开路情形。此时优先确定F线、S线与待测芯片的PAD之间是否形成良好的接触，比如使用万用表测量F线与S线之间的电阻，如果测量的电阻为无穷大，表示F线或者S线与待测芯片的PAD之间没有形成良好的接触，如果测量的电阻为0欧姆，表示F线和S线都和PAD接触良好。若确认F线、S线和待测芯片的PAD之间接触良好，则确定出第二测试装置中的二极管D2出现开路。
图3为本申请实施例三测试***的结构示意图；本实施例中，以通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，对应地，以第二测试装置只包括一条第一压降支路(其包括二极管D1以及继电器K1)、同时待测芯片DUT中包括一条第二压降支路(其包括二极管D3)为例进行说明。
具体地，如图3所示，由于自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，因此，第一压降支路中的所述二极管D1的负极接地，所述二极管D1的正极与继电器K1的一端连接，与此同时，继电器K1的另外一端与S线连接；因此同时，第二压降支路中的所述二极管的负极接地且其正极与待测芯片DUT的PAD连接。假设第一压降支路中二极管不存在开短路，具体检测过程具体如下。
通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流，如图3所示，由于是正相驱动电流，因此，电流的流向实际上从自动化测试设备ATE的电源DPS流向待测芯片DUT，即如图3中F线上从右至左的箭头所示；与此同时，通过自动化测试设备ATE控制第二测试装置中的继电器K1闭合，因此，如果S线与待测芯片DUT的PAD接触良好则其就会导通继而会产生对应的压降，为了能使得在F线上检测到的压降即为第一测试装置中的的压降，所以，在选型时，二极管D1优选当导通时压降小于第二测试装置中的二极管D3导通时压降的二极管。在实际应用场景中，由于第二测试装置中的二极管D3往往是硅二极管(导通时的压降大约为0.6V)，因此第二测试装置中 的二极管D1选用锗二极管(导通时的压降大约为0.3V)即可。
进一步地，如果能在F线上检测到压降(对应某个二极管导通的压降)，则表明F线与待测芯片DUT的PAD具有良好的接触进而可形成有效的电连接，否则，是通过F线无法检测到对应某个二极管导通的压降，只能检测到所述自动化检测设备ATE的钳位电压。
进一步地，如果检测到的压降等于所述锗二极管D1的压降，则表明S线与待测芯片DUT的PAD之间具有良好的接触进而可形成有效的电连接；如果检测到的压降等于所述硅二极管的压降，则表明S线与待测芯片DUT的PAD之间不具有良好的接触进而未形成有效的电连接。如果检测到的压降等于所述自动化检测设备ATE的钳位电压，则表明F线与待测芯片DUT的PAD之间未形成良好的接触，而此时至于S线与待测芯片DUT的PAD之间是否形成良好的接触有待进一步确定。比如，当表明F线与待测芯片DUT的PAD之间未形成良好的接触后，首先解决F线与待测芯片DUT的PAD之间未形成良好的接触的问题，再进一步确定S线与待测芯片DUT的PAD之间是否形成良好的接触。
如果检测到的压降等于所述锗二极管D1的压降，则表明S线与待测芯片DUT的PAD之间具有良好的接触进而可形成有效的电连接详细解释可参见上述图1所记载。
相反，当第二测试装置中的二极管D1选用导通时压降大于待测芯片DUT中硅二极管导通的压降，无论S线是否与待测芯片DUT的PAD接触良好，通过F线检测到的压降均是待测芯片DUT中硅二极管D3导通的压降，换言之，S线是否与待测芯片DUT的PAD接触良好，并不会导致在F线检测到的压降会有不同，进而也就无法确定出S线是否与待测芯片DUT的PAD接触良好，详细原因可参见上述图1的记载。
对第二测试装置中的第一压降支路中的二极管开短路情况进行测试详细如下：
继电器K1断开时，通过F线提供正相驱动电流，而F线检测到的压降为第二压降支路中的二极管D3的压降(0.6V左右)，表明与待测芯片的PAD形成了良好的接触，之后，继电器K1导通时，通过F线提供正相驱动电流，而F线检测到的压降为0V(接地电平)，则此时确定出F线、S线与待测芯片的PAD形成了良好的接触且第二测试装置中的二极管D1出现短路。若在继电器K1导通时，而F线检测到的压降为第二压降支路中的二极管D3的压降(0.6V 左右)，表明S线与待测芯片的PAD之间没有形成良好的接触或者第二测试装置中的二极管D1出现了开路情形。此时优先确定S线与待测芯片的PAD之间是否形成良好的接触，比如使用万用表测量F线与S线之间的电阻，如果测量的电阻为无穷大，表示F线或者S线与待测芯片的PAD之间没有形成良好的接触，如果测量的电阻为0欧姆，表示F线和S线都和待测芯片的PAD接触良好。若确认S线和待测芯片的PAD之间接触良好，则确定出第二测试装置中的二极管D1出现开路。
图4为本申请实施例四测试***的结构示意图；本实施例中，以通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，对应地，以第二测试装置只包括一条第一压降支路(其包括二极管D1以及继电器K1)，但是，与上述图3实施例不同的是，待测芯片DUT并不包括第二压降支路为例进行说明。
具体地，如图4所示，由于自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，因此，第一压降支路中的所述二极管D1的负极接地，所述二极管D1的正极与继电器K1的一端连接，与此同时，继电器K1的另外一端与S线连接。假设第一压降支路中二极管不存在开短路，具体检测过程具体如下。
通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流，如图4所示，由于是正相驱动电流，因此，电流的流向实际上从自动化测试设备ATE的电源DPS流向待测芯片DUT，即如图4中F线处从右至左的箭头所示；与此同时，通过自动化测试设备ATE控制第二测试装置中的继电器K1闭合，因此，假如S线与待测芯片DUT的PAD接触良好，同时如能在F线上检测到压降对应该二极管的压降，且该压降对应第二测试装置中的二极管D2导通时的压降，则恰好证明S线与待测芯片DUT的PAD之间接触良好，且F线也与待测芯片DUT的PAD之间接触良好，进而形成了有效的电连接。反之，如果检测到的压降等于所述自动化检测设备ATE的钳位电压，则表明F线与待测芯片DUT的PAD之间未形成良好的接触，而此时至于S线与待测芯片DUT的PAD之间是否形成良好的接触有待进一步确定。比如，当表明F线与待测芯片DUT的PAD之间未形成良好的接触后，首先解决F线与待测芯片DUT的PAD之间未形成良好接触的问题，再进一步确定S线与待测芯片DUT的PAD之间是否形成良好的接触。
对第二测试装置中的第一压降支路中的二极管开短路情况进行测试类似上 述实施例一，详细请参见上述实施例1的记载。
继电器K1导通时，通过F线提供正相驱动电流，而F线检测到的压降为0V(接地电平)，则此时确定出F线、S线与待测芯片的PAD之间形成了良好的接触且第二测试装置中的二极管D1出现短路。若而F线检测到的压降为钳位电压，表明F线或者S线与待测芯片的PAD之间没有形成良好的接触或者第二测试装置中的二极管D1出现了开路情形。此时优先确定F线、S线与待测芯片的PAD之间是否形成良好的接触，比如使用万用表测量F线与S线之间的电阻，如果测量的电阻为无穷大，表示F线或者S线与待测芯片的PAD之间没有形成良好的接触，如果测量的电阻为0欧姆，表示F线和S线都和PAD接触良好。若确认S线和待测芯片的PAD之间接触良好，则确定出第二测试装置中的二极管D1出现开路。
图5为本申请实施例五测试***的结构示意图；如图5所示，本实施例中，第二测试装置包括两条第一压降支路，其中一条第一压降支路中的二极管D2、继电器K2的连接方式如图1，另外一条第一压降支路中的二极管D1、继电器K1的连接方式如图3所示，对应地，待测芯片DUT中也包括两条第二压降支路，其中一条第二压降支路中的二极管D4的连接方式如图1，另外一条第二压降支路中的二极管D3的连接方式如图3所示。
如果要通过自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流时进行电连接有效性的测试，则可参照图1所示。如果要通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，则可参照图3所示。
由此可见，即本实施例中，可以由电源DPS提供负相驱动电流或者正相驱动电流以进行电连接有效性的测试。当然，在其他实施例中，也可以先后提供负相驱动电流、正相驱动电流，或者正相驱动电流、负相驱动电流，利用两次测试的结果相互进行复核。
对第二测试装置中的第一压降支路中的二极管开短路情况进行测试类似上述实施例一，详细请参见上述实施例1和图3的记载。
图6为本申请实施例六测试***的结构示意图；如图6所示，本实施例中，第二测试装置包括两条第一压降支路，其中一条第一压降支路中的二极管D2、继电器K2的连接方式如图1，另外一条第一压降支路中的二极管D1、继电器 K1的连接方式如图3所示，而待测芯片DUT中不包括第二压降支路。
如果要通过自动化测试设备ATE的电源DPS向待测芯片DUT提供负相驱动电流时进行电连接有效性的测试，则可参照图2所示。如果要通过自动化测试设备ATE的电源DPS向待测芯片DUT提供正相驱动电流时进行电连接有效性的测试，则可参照图4所示。
由此可见，即本实施例中，可以由电源DPS提供负相驱动电流或者正相驱动电流以进行电连接有效性的测试。当然，在其他实施例中，也可以先后提供负相驱动电流、正相驱动电流，或者正相驱动电流、负相驱动电流，利用两次测试的结果相互进行复核。
对第二测试装置中的第一压降支路中的二极管开短路情况进行测试类似上述实施例一，详细请参见上述实施例2和4的记载。
当通过上述实施例确定F线、S线均与待测芯片DUT的PAD之间形成了有效电连接，则自动化测试设备ATE会根据S线检测到的真实驱动电流去调整通过F线传输的驱动电流，从而使到达待测对象DUT的真实驱动电流满足待测对象DUT正常工作所需。
另外，需要说明的是，在上述实施例中，对于待测芯片DUT的电源引脚VCC来说，在测试时，为了方便数据的查看，其电压可以配置成0V，此处，通过F线检测到的压降直接对应二极管的压降，比如为0.3V或者0.6V。但是，在其他实施例中，也可以给电源引脚VCC配置一定的驱动电压，比如2.8V，那么F线测量到的压降为该驱动电压与对应二极管压降之和，比如2.8V+0.3V＝3.1V，或者2.8V+0.6V＝3.4V。对于F线与待测芯片的PAD未接触好时，F线测量的压降为钳位电压。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
本领域内的技术人员应明白，本申请的实施例可提供为方法、***、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请是参照根据本申请实施例的方法、设备(***)、和计算机程序产品的流程图和/或方框图来描述的。应理解可由计算机程序指令实现流程图和/或方框图中的每一流程和/或方框、以及流程图和/或方框图中的流程和/或方框的结合。可提供这些计算机程序指令到通用计算机、专用计算机、嵌入式处理机或其他可编程数据处理设备的处理器以产生一个机器，使得通过计算机或其他可编程数据处理设备的处理器执行的指令产生用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的装置。
这些计算机程序指令也可存储在能引导计算机或其他可编程数据处理设备以特定方式工作的计算机可读存储器中，使得存储在该计算机可读存储器中的指令产生包括指令装置的制造品，该指令装置实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能。
这些计算机程序指令也可装载到计算机或其他可编程数据处理设备上，使得在计算机或其他可编程设备上执行一系列操作步骤以产生计算机实现的处理，从而在计算机或其他可编程设备上执行的指令提供用于实现在流程图一个流程或多个流程和/或方框图一个方框或多个方框中指定的功能的步骤。
在一个典型的配置中，计算设备包括一个或多个处理器(CPU)、输入/输出接口、网络接口和内存。
内存可能包括计算机可读介质中的非永久性存储器，随机存取存储器(RAM)和/或非易失性内存等形式，如只读存储器(ROM)或闪存(flash RAM)。内存是计算机可读介质的示例。
计算机可读介质包括永久性和非永久性、可移动和非可移动媒体可以由任何方法或技术来实现信息存储。信息可以是计算机可读指令、数据结构、程序的模块或其他数据。计算机的存储介质的例子包括，但不限于相变内存(PRAM)、静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)、其他类型的随机存取存储器(RAM)、只读存储器(ROM)、电可擦除可编程只读存储器(EEPROM)、快闪记忆体或其他内存技术、只读光盘只读存储器(CD-ROM)、数字多功能光盘(DVD)或其他光学存储、磁盒式磁带，磁带磁磁盘存储或其他磁性存储设备或任何其他非传输介质，可用于存储可以被计算设备访问的信息。按照本文中的界定，计算机可读介质不包括暂存电脑可读媒体(transitory media)，如调制的数据信号和载波。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅 包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个测试***”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
本领域技术人员应明白，本申请的实施例可提供为方法、***或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、CD-ROM、光学存储器等)上实施的计算机程序产品的形式。
本申请可以在由计算机执行的计算机可执行指令的一般上下文中描述，例如程序模块。一般地，程序模块包括执行特定事务或实现特定抽象数据类型的例程、程序、对象、组件、数据结构等等。也可以在分布式计算环境中实践本申请，在这些分布式计算环境中，由通过通信网络而被连接的远程处理设备来执行事务。在分布式计算环境中，程序模块可以位于包括存储设备在内的本地和远程计算机存储介质中。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于***实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (12)

  1. 一种测试***，其特征在于，包括：第一测试装置以及第二测试装置，所述第一测试装置的电源通过驱动支路、检测支路与待测对象形成电连接，所述驱动支路用于在测试时通过所述电源向待测对象提供原始驱动电流，所述检测支路用于检测到达所述待测对象的有效驱动电流；所述第二测试装置包括第一压降支路，所述第一压降支路与所述检测支路连接，通过所述驱动支路检测到的压降以确定所述驱动支路、所述检测支路与所述待测对象形成电连接的有效性。
  2. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一压降支路的压降，则所述检测支路与所述待测对象形成了有效的电连接。
  3. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述待测对象中第二压降支路的压降，则所述检测支路与所述待测对象未形成有效的电连接。
  4. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路与所述待测对象未形成有效的电连接。
  5. 根据权利要求1所述的***，若所述待测对象不包括第二压降支路，且所述原始驱动电流为负相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路或者所述检测电路与所述待测对象未形成有效的电连接。
  6. 根据权利要求2-5任一项所述的***，其特征在于，所述第一压降支路包括第一开关器件以及第二开关器件，所述第一开关器件的正极接地，所述第一开关器件的负极与第二开关器件的一端连接，且所述第二开关器件的另一端与所述检测支路连接。
  7. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一压降支路的压降，则所述检测支路与所述待测对象形成了有效的电连 接。
  8. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述待测对象中第二压降支路的压降，则所述检测支路与所述待测对象未形成有效的电连接。
  9. 根据权利要求1所述的***，其特征在于，若所述待测对象包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路与所述待测对象未形成有效的电连接。
  10. 根据权利要求1所述的***，若所述待测对象不包括第二压降支路，且所述原始驱动电流为正相时，若通过所述驱动电路检测到的压降为所述第一测试装置的钳位电压，则所述驱动支路或者所述检测电路与所述待测对象未形成有效的电连接。
  11. 根据权利要求7-10任一项所述的***，其特征在于，所述第一压降支路包括第一开关器件以及第二开关器件，所述第一开关器件的负极接地，所述第一开关器件的正极与第二开关器件的一端连接，且所述第二开关器件的另一端与所述检测支路连接。
  12. 根据权利要求1所述的***，其特征在于，所述第二测试装置设置在用于搭建对芯片进行功能/性能测试的测试板上。
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