WO2020061813A1 - 图像处理***和图像处理方法 - Google Patents
图像处理***和图像处理方法 Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
- H04N23/80—Camera processing pipelines; Components thereof
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/222—Studio circuitry; Studio devices; Studio equipment
- H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/18—Closed-circuit television [CCTV] systems, i.e. systems in which the video signal is not broadcast
Definitions
- the present application relates to the field of image processing, and in particular, to an image processing system and an image processing method.
- An image processing system generally includes an image sensor and an image processor.
- the image sensor is responsible for converting light signals into electrical signals to the image processor.
- the image processor receives the electric signal output by the image sensor, it processes the electric signal, that is, the image signal is processed.
- the image processing system needs to process the image signals differently to meet different needs.
- the present application provides an image processing system and an image processing method that can support higher-level functions.
- an image processing system including: an image sensor configured to sense an optical signal and convert the optical signal into a corresponding original image signal, and the image sensor includes An image output interface of an image signal; an interface expansion device including an extended input interface and at least two sets of extended output interfaces, the extended input interface is electrically connected to the image output interface and configured to receive the original output from the image output interface For image signals, at least two sets of the extended output interfaces are respectively used to output image signals to be processed corresponding to the original image signals; and at least two image processors are electrically connected to at least two sets of the extended output interfaces. Receiving the image signal to be processed, and processing the image signal to be processed.
- an image processing method including: sensing an optical signal through an image sensor, and converting the optical signal into a corresponding original image signal to an interface expansion device; and expanding through the interface At least two sets of extended output interfaces of the device, sending the image signal to be processed corresponding to the original image signal to at least two image processors; and performing the image signal to be processed by at least two of the image processors deal with.
- the image processing system of the present application connects at least two image processors to an image sensor through an interface expansion device, and at least two image processors perform image processing respectively. In this way, while ensuring the quality of the image signal, image processing can be more flexibly selected.
- Device not limited to the function of a certain image processor, can take advantage of different image processors to achieve more advanced functions, so that the image processing system functions can be richer and more powerful.
- FIG. 1 is a schematic block diagram of an embodiment of an image processing system of the present application.
- FIG. 2 shows a flowchart of an embodiment of an image processing method of the present application.
- the image processing system in the embodiment of the present application includes an image sensor, an interface expansion device, and at least two image processors.
- the image sensor is used to sense an optical signal and convert the optical signal into a corresponding original image signal.
- the image sensor includes an image output interface for outputting an original image signal.
- the interface expansion device includes an expansion input interface and at least two sets of expansion output interfaces.
- the extended input interface is electrically connected to the image output interface and is used to receive the original image signal output by the image output interface.
- At least two sets of extended output interfaces are respectively used to output the image signal to be processed corresponding to the original image signal.
- At least two image processors are correspondingly electrically connected to at least two sets of extended output interfaces, and are used for receiving image signals to be processed and processing the image signals to be processed.
- the image processing system connects at least two image processors to the image sensor through the interface expansion device, and the at least two image processors perform image processing respectively.
- the image processor can be more flexibly selected.
- the advantages of different image processors can be used to achieve more advanced functions, so that the functions of the image processing system can be richer and the performance more powerful.
- the image processing method in the embodiment of the present application includes: sensing an optical signal through an image sensor, and converting the optical signal into a corresponding original image signal to an interface expansion device; and at least two sets of expansion output interfaces through the interface expansion device will be connected with the original image
- the image signal to be processed corresponding to the signal is sent to at least two image processors; and the image signal to be processed is processed by the at least two image processors.
- FIG. 1 is a schematic block diagram of an embodiment of an image processing system 100.
- the image processing system 100 may be used in a photographing device, such as a digital camera, and of course, may be used in other devices.
- the image processing system 100 may include a digital image processing system.
- the image processing system 100 in the embodiment of the present application includes an image sensor 101, an interface expansion device 102, and at least two image processors, that is, a first image processor 103 and a second image processor 104.
- the image sensor 101 is configured to sense an optical signal and convert the optical signal into a corresponding original image signal.
- the image sensor 101 includes an image output interface 105 for outputting an original image signal.
- the image sensor 101 may convert an optical signal into an analog electric signal, and convert the analog electric signal into a digital signal, and the original image signal may be a digital signal.
- the image sensor 101 includes a CMOS (Complementary Metal Oxide Semiconductor) image sensor or a CCD (Charge-coupled Device) image sensor.
- the image sensor 101 may include a CMOS image sensor or a CCD image sensor.
- the CMOS image sensor or CCD image sensor may support multi-channel output, and the bandwidth of each channel is not less than 200 Mbps, and has the characteristics of high resolution and high frame rate. A large amount of data is transmitted.
- the image sensor 101 may be a 4 / 3-inch CMOS image sensor or a 1-inch CMOS image sensor.
- the image output interface 105 includes a multi-channel data interface. For example, for a data interface of 9 channels, one channel outputs a clock signal clk0, and the other 8 channels output image data lane00-lane0n, where n is a natural number. In this example, n is 7, but is not limited thereto. In other examples, the image output interface 105 may include data interfaces of other number channels.
- the single-channel bandwidth of the data interface is not less than 200 Mbps. In some embodiments, the single-channel bandwidth of the data interface can reach more than 300Gbps. In some embodiments, the single-channel bandwidth of the data interface can reach more than 1 Gbps.
- the data interface is a high-speed data interface that can transmit the original image signals of high-end image sensors at high speed.
- the data interface includes a serial data interface.
- the serial data interface includes an LVDS (Low Voltage Differential Signaling) interface or a MIPI (Mobile Industry Processor Interface) interface.
- the serial data interface may include other high-speed serial data interfaces.
- the interface expansion device 102 includes an expansion input interface 106 and at least two sets of expansion output interfaces. In this embodiment, there are two sets of expansion output interfaces, namely a first expansion output interface 107 and a second expansion output interface 108.
- the extended input interface 106 is electrically connected to the image output interface 105 and is used to receive the original image signal output by the image output interface.
- the first extended output interface 107 and the second extended output interface 108 are respectively used to output the image to be processed corresponding to the original image signal signal.
- the extended input interface 106 can match the image output interface 105.
- the image sensor 101 outputs the original image signal through the image output interface 105, and the interface expansion device 102 receives the original image signal through the extended input interface 106.
- the extended input interface 106 includes a multi-channel data interface.
- the single-channel bandwidth of the extended input interface 106 is equivalent to or higher than the single-channel bandwidth of the image output interface 105.
- the extended input interface 106 is a high-speed data interface, which satisfies the data transmission of the high-end image sensor 101.
- the extended input interface 106 may be a serial data interface.
- the interface expansion device 102 is used to receive a clock signal from the image sensor 101, and when receiving the original image signal, adjust the phase relationship between the original image signal and the clock signal so that each channel of the received original image signal and the clock signal The phase difference between them is basically the same, thus ensuring the stability of the received data.
- One channel in the extended input interface 106 receives the clock signal clk0, and the other multiple channels can receive multiple data lane00-lane0n of the original image signal.
- the interface expansion device 102 includes two sets of expansion output interfaces, that is, a first expansion output interface 107 and a second expansion output interface 108, respectively, to output an image signal to be processed corresponding to the original image signal.
- the interface expansion device 102 may include three or more groups of expansion output interfaces.
- the first extended output interface 107 and the second extended output interface 108 may include multiple channels, and the number of channels is the same as the number of channels of the image output interface 105 and the number of channels of the extended input interface 106.
- the interface expansion device 102 is configured to adjust the phase relationship between the image signal to be processed and the clock signal when outputting the image signal to be processed, so that each of the data of the output image signal to be processed and the clock signal
- the phase difference is basically the same, so the stability of the output data is guaranteed.
- One channel in the first extended output interface 107 in FIG. 1 outputs a clock signal clk1, and the other multiple channels can output multi-channel data lane10-lane1n of an image signal to be processed.
- One channel in the second extended output interface 108 outputs a clock signal clk2, and the other multiple channels can output multi-channel data lane20-lane2n of the image signal to be processed.
- the interface expansion device 102 is configured to output the image signal to be processed that is the same as the original image signal through at least two sets of expansion output interfaces.
- the interface expansion device 102 divides the original image signal into at least two groups of outputs.
- the to-be-processed image signals lane10-lane1n output from the first extended output interface 107 and the to-be-processed image signals lane20-lane2n from the second extended output interface 108 in the figure may be the same as the original image signals lane00-lane0n output from the image sensor 101 .
- the image signal to be processed includes a first image signal to be processed, and the interface expansion device 102 is configured to process the original image signal to obtain a first image signal to be processed.
- the interface expansion device 102 is configured to pass at least one group
- the extended output interface for example, the first extended output interface 107 and / or the second extended output interface 108 in the embodiment outputs a first image signal to be processed.
- the interface expansion device 102 can process the original image signal and output it.
- the interface expansion device 102 for processing the original image signal may include: processing the number of pixels and / or the pixel width of the original image signal.
- the processing of the number of pixels may be an adjustment of the pixel resolution, for example, adjusting a 4K resolution (4096 ⁇ 2160) to a 1080p resolution (1920 ⁇ 1080).
- the interface expansion device 102 may perform other processing on the original image signal.
- the multiple sets of extended output interfaces of the interface expansion device 102 all output the first image signal to be processed.
- part of the extended output interface of the interface expansion device 102 outputs a first image signal to be processed, and other part of the extended output interface may output an image signal different from the first image signal to be processed.
- the image signal to be processed may include a second image signal to be processed.
- the second image signal to be processed is different from the first image signal to be processed.
- the interface expansion device 102 is configured to output the second image signal to be processed through at least another set of expansion output interfaces.
- the first extended output interface 107 in the figure may output a first image signal to be processed lane10-lane1n
- the second extended output interface 108 may output a second image signal to be processed lane20-lane2n
- two or more sets of extended output interfaces output a first image signal to be processed
- two or more sets of extended output interfaces output a second image signal to be processed.
- the interface expansion device 102 can output different to-be-processed image signals to corresponding image processors through different expansion output interfaces, such as the first image processor 103 and the second image processor 104 shown in FIG. 1, so that different Image processor requirements for image data.
- the second image signal to be processed is the same as the original image signal. In another embodiment, the second image signal to be processed is different from the original image signal, and the interface expansion device 102 processes the original image signal to obtain a second image signal to be processed.
- the interface expansion device 102 may perform different processing on the original image signal to obtain different first image signals to be processed and second image signals to be processed. In other embodiments, the interface expansion device 102 may output other image signals to be processed that are different from the first image signal to be processed and the second image signal to be processed.
- the interface expansion device 102 includes a programmable logic device, which can be programmed and designed according to different applications and requirements, which is convenient for designers to design and is more flexible.
- the programmable logic device may include an FPGA (Field-Programmable Gate Array, Field Programmable Gate Array).
- FPGA Field-Programmable Gate Array, Field Programmable Gate Array
- the bandwidth of some FPGA high-speed serial ports can reach more than 1Gbps, and some can even reach 1.5Gbps, which can meet the needs of high-speed image data transmission, can match many high-end image sensors, and support many image processors, so it can make device selection more flexible.
- the programmable logic device may include a CPLD (Complex Programmable Logic Device), which may also be matched with many high-end image sensors and support many image processors.
- An appropriate programmable logic device can be selected according to the number of channels of the image output interface 105 of the image sensor 101 and the number of image processors.
- the number of interface channels of the programmable logic device is equal to the number of channels of the image output interface 105 and divided into multiple sets of extended output interfaces. The sum of the number of channels.
- the image sensor 101 outputs one channel of LVDS clock data and eight channels of LVDS image data. There are nine channels of LVDS data in total. If one group of interfaces of the programmable logic device receives the data of the image sensor 101 and divides them into two groups of interfaces to output the image data to be processed, then Requires 3 sets of interfaces, a total of 27 LVDS channels. Based on this, you can choose a programmable logic device that can support 27 LVDS.
- the above is just an example, and the actual application is not limited to the above example.
- the interface expansion device 102 includes an ASIC (Application Specific Integrated Circuit) chip.
- ASIC chips can be customized according to the actual application.
- At least two image processors are correspondingly electrically connected to at least two sets of extended output interfaces, and are used for receiving image signals to be processed and processing the image signals to be processed.
- the image processing system 100 includes two image processors, namely a first image processor 103 and a second image processor 104.
- the first image processor 103 is connected to the first extended output interface 107
- the second The image processor 104 is connected to the second extended output interface 108.
- the image processing system 100 may include three or more image processors connected to corresponding extended output interfaces.
- the image processing system 100 connects at least two image processors to the image sensor 101 through the interface expansion device 102. Especially for high-end image sensors, efficient transmission of image data can be achieved. Further, image processing can be performed separately by at least two image processors, so that the image processor can be more flexibly selected when designing, not limited to the function of a certain image processor, and the advantages of different image processors can be used. Each of the dedicated functions can achieve higher performance indicators, achieve more advanced functions, and make the functions of the image processing system richer and more powerful.
- the at least two image processors include a first image processor 103 and a second image processor 104, and the processing of the image signal to be processed by the second image processor 104 is at least partially different from that of the first image processor 103. Processing of image signals.
- the first image processor 103 and the second image processor 104 may perform completely different or partially different processing on the image signals to be processed to obtain different processed images.
- the image signals to be processed received by the first image processor 103 and the second image processor 104 may be the same or different.
- the first image processor 103 and the second image processor 104 include different chips. Different chips can focus on different processing and achieve different functions through different chips. In another embodiment, the first image processor 103 and the second image processor 104 include the same chip, and the data can be processed differently through the same chip to implement different functions and reduce the workload of a single chip. Increase computing speed.
- At least two image processors are configured to perform at least one of image signal processing, image display, image compression, image storage, and image transmission on an image signal to be processed.
- performing different processing on the image signal to be processed by the first image processor 103 and the second image processor 104 may include: performing different types of processing on the image signal to be processed, such as image signal processing and image display. Different types of processing, and / or, the image signals to be processed are processed in the same kind but in different ways, such as image compression processing of different standards.
- the image signal processing includes first image signal processing, and the first image processor 103 is configured to perform first image signal processing on the image signal to be processed.
- the image signal to be processed may be processed by the number of pixels, the pixel width, the image conversion, the image enhancement and restoration, the image segmentation, the image description, and / or the image recognition.
- the second image processor 104 is configured to perform a first image compression on an image signal to be processed.
- the first image processor 103 can focus on image signal processing, and the second image processor 104 can focus on image compression.
- the first image processor 103 is configured to perform the first image signal processing on the image signal to be processed, and then further perform the second image compression on the image signal to be processed, where the second image compression is different from the first image. compression.
- the first image processor 103 may also compress an image.
- the first image processor 103 and the second image processor 104 may perform image compression of different standards to obtain different compressed images.
- the image quality of the image obtained by the second image compression is higher than the image quality of the image obtained by the first image compression.
- the first image processor 103 performs image compression of the H.264 standard
- the second image processor 104 performs image compression of the JPEG2000 standard with higher image quality, or the image compression of the H265 standard to implement higher-level image compression functions.
- the second image processor 104 is configured to perform first image storage on an image signal to be processed. In this way, the first image processor 103 can focus on image signal processing, and the second image processor 104 can focus on image storage.
- the first image processor 103 is configured to perform a first image signal processing on the image signal to be processed, and then to further store a second image on the image signal to be processed.
- the first image storage is different from the second image storage.
- the first image processor 103 may also store images, and the first image processor 103 and the second image processor 104 may store images with different storage capacities.
- the storage capacity of the second image processor 104 is larger than the storage capacity of the first image processor 103.
- the second image processor 104 can perform professional image storage, can support higher storage bandwidth, and save images with higher image quality.
- the first image processor 103 stores images using an SD card
- the second image processor 104 stores images using a storage device with a larger storage bandwidth and / or storage capacity than the SD card, such as a solid-state drive (Solid-state drive, (SSD) or Universal Flash Storage (UFS) and other suitable storage devices.
- SSD Solid-state drive
- UFS Universal Flash Storage
- the second image processor 104 is used for second image signal processing, and the second image signal processing performed by the second image processor 104 is different from the first image signal processing performed by the first image processor 103.
- the algorithm of the first image signal processing is different from the algorithm of the second image signal processing, and different images are obtained.
- the second image processor 104 can perform simple image signal processing with respect to the first image processor 103.
- the first image signal processing includes image conversion, image enhancement and restoration, image segmentation, image description, and image recognition processing of the image signal to be processed
- the second image signal processing includes pixel number processing and pixel bit processing of the image signal to be processed. Wide processing.
- the first image processor 103 may perform image recognition such as portrait recognition to complete subsequent image signal processing
- the second image processor 104 performs image display and / or image storage of a typical digital camera.
- the above are just examples and are not limited to the above examples.
- the first image processor 103 and the second image processor 104 may perform different image signal processing according to actual needs.
- the second image processor 104 may perform at least two functions of image compression, image storage, and second image signal processing.
- the second image processor 104 includes a chip that focuses on image compression, performs second image signal processing on the image signal to be processed, and compresses the processed image.
- the second image processor 104 includes a chip dedicated to image storage, performs second image signal processing on the image signal to be processed, and stores the processed image.
- the second image processor 104 performs second image signal processing on the image signal to be processed, and compresses and stores the processed image.
- the first image processor 103 may also be used for image display processing.
- the image signal is processed into data suitable for display, for example, HDMI (High Definition Multimedia Interface) image display processing.
- the first image processor 103 may also be used for processing of image transmission.
- the image transmission includes wireless image transmission.
- the first image processor 103 may be used to send the processed image to other devices wirelessly.
- the first image processor 103 and / or the second image processor 104 may perform other image processing, for example, the second image processor 104 may be used for image display and / or image transmission.
- the first image processor 103 and the second image processor 104 may communicate with each other to work in cooperation.
- the image signal processed by the first image processor 103 may be sent to the second image processor 104, and the second image processor 104 may compress, store, etc. the image signal. Realizing more and more advanced functions in this way can meet different needs and make the design more flexible.
- at least two image processors may be wired.
- the first image processor 103 and the second image processor 104 may be communicatively connected through a UART interface or an I2C interface or an SPI interface. In another embodiment, at least two image processors are wirelessly connected.
- FIG. 2 is a flowchart of an embodiment of an image processing method 200.
- the image processing method 200 may be executed by the image processing system shown in FIG. 1.
- the image processing method 200 includes steps 201-203.
- an image sensor is used to sense a light signal and convert the light signal into a corresponding original image signal to the interface expansion device.
- the image sensor may be the image sensor 101 shown in FIG. 1, and the interface extension device may be the interface extension device 102 shown in FIG. 1.
- the image sensor includes a CMOS image sensor or a CCD image sensor.
- step 202 the at least two sets of extended output interfaces of the interface expansion device are used to send the image signal to be processed corresponding to the original image signal to at least two image processors.
- the image processor may be the first image processor 103 and the second image processor 104 shown in FIG. 1.
- step 203 an image signal to be processed is processed by at least two image processors.
- the image signal to be processed corresponding to the original image signal output by the image sensor is sent to at least two image processors for processing through the interface expansion device, and the image signals to be processed can be processed differently through multiple image processors.
- step 201 includes: outputting the original image signal to the interface expansion device through a multi-channel data interface of the image sensor.
- the bandwidth of a single channel of the data interface is not less than 200 Mbps.
- the data interface includes a serial data interface.
- the serial data interface includes an LVDS interface or a MIPI interface.
- the image signal to be processed is the same as the original image signal.
- the image signal to be processed includes a first image signal to be processed; step 202 includes: processing the original image signal through an interface expansion device to obtain a first image signal to be processed; and outputting through at least one set of expansions The interface sends the first to-be-processed image signal to at least one image processor.
- the original image signal is processed by changing the number of pixels and / or the pixel bit width through the interface expansion device.
- the image signal to be processed includes a second image signal to be processed; step 202 includes: sending the second image signal to be processed to at least another image processor through at least another set of extended output interfaces.
- the interface expansion device includes a programmable logic device.
- the programmable logic device includes an FPGA or a CPLD.
- the interface expansion device includes an ASIC chip.
- the image processing method includes: receiving a clock signal from the image sensor through an interface expansion device, and adjusting a phase relationship between the original image signal and the clock signal when receiving the original image signal. In one embodiment, the phase relationship between the image signal to be processed and the clock signal is adjusted when the image signal to be processed is output through the interface expansion device.
- the at least two image processors include a first image processor and a second image processor.
- Step 203 includes: processing the image signal to be processed by the first image processor and the second image processor respectively; wherein the processing of the image to be processed by the first image processor is at least partially different from the image to be processed by the second image processor Signal processing.
- the first image processor and the second image processor include different chips. In another embodiment, the first image processor and the second image processor include the same chip.
- step 203 includes: performing at least one of image signal processing, image display, image compression, storage, and image transmission on the image signal. In one embodiment, step 203 includes: performing first image signal processing on the image signal to be processed by the first image processor. In one embodiment, step 203 includes: performing a first image compression on the image signal to be processed by the second image processor.
- step 203 includes: after the first image signal processing is performed on the image signal to be processed, the second image compression is further performed on the image to be processed by the first image processor, where the second image compression is different from the first image compression .
- the image quality of the image obtained by the second image compression is higher than the image quality of the image obtained by the first image compression.
- step 203 includes: performing a first image storage of the image signal to be processed by the second image processor. In one embodiment, step 203 includes: after the first image signal processing is performed on the image signal to be processed, the second image storage is further performed by the first image processor, and the first image storage is different from the second image storage. In one embodiment, the storage capacity of the second image processor is larger than the storage capacity of the first image processor.
- step 203 includes: performing second image signal processing by a second image processor, and the second image signal processing is different from the first image signal processing.
- the image processing method 200 includes communicating between at least two image processors. In one embodiment, communication is performed between at least two image processors in a wired manner. In one embodiment, communication is performed between at least two image processors through a UART interface or an I2C interface or an SPI interface. In another embodiment, communication is performed wirelessly between at least two image processors.
- the relevant parts may refer to the description of the device embodiment.
- the method embodiment and the device embodiment complement each other.
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Abstract
本申请公开一种图像处理***和图像处理方法。图像处理***包括图像传感器、接口扩展装置和至少两个图像处理器。图像传感器用于感应光信号,并将光信号转换成相应的原始图像信号。图像传感器包括用于输出原始图像信号的图像输出接口。接口扩展装置包括扩展输入接口和至少两组扩展输出接口。扩展输入接口与图像输出接口电连接,用于接收图像输出接口输出的原始图像信号,至少两组扩展输出接口分别用于输出与原始图像信号对应的待处理图像信号。至少两个图像处理器与至少两组扩展输出接口对应电连接,用于接收待处理图像信号,并对待处理图像信号进行处理。
Description
本申请涉及图像处理领域,特别涉及一种图像处理***和图像处理方法。
图像处理***在拍摄设备等设备中发挥很重要的作用。图像处理***一般包括图像传感器和图像处理器。图像传感器负责把光信号转换为电信号给图像处理器。图像处理器接收到图像传感器输出的电信号后,对电信号进行处理,即对图像信号进行处理。根据应用场景不同,图像处理***需要对图像信号所做的处理也不尽相同,以满足不同的需求。
现有图像处理***通过单一的图像处理器来完成所有的图像处理工作。而不同的图像处理器擅长不同的功能,每个图像处理器设计的功能往往会有局限性。因此通过单一的图像处理器对图像信号所做的处理也比较局限,不能支持更高级别的功能,如此整个***的功能受限。
发明内容
本申请提供一种可以支持更高级别功能的图像处理***和图像处理方法。
根据本申请实施例的一个方面,提供一种图像处理***,包括:图像传感器,用于感应光信号,并将所述光信号转换成相应的原始图像信号,所述图像传感器包括用于输出原始图像信号的图像输出接口;接口扩展装 置,包括扩展输入接口和至少两组扩展输出接口,所述扩展输入接口与所述图像输出接口电连接,用于接收所述图像输出接口输出的所述原始图像信号,至少两组所述扩展输出接口分别用于输出与所述原始图像信号对应的待处理图像信号;及至少两个图像处理器,与至少两组所述扩展输出接口对应电连接,用于接收所述待处理图像信号,并对所述待处理图像信号进行处理。
根据本申请实施例的另一个方面,提供一种图像处理方法,包括:通过图像传感器,感应光信号,并将所述光信号转换成相应的原始图像信号给接口扩展装置;通过所述接口扩展装置的至少两组扩展输出接口,将与所述原始图像信号对应的待处理图像信号发送给至少两个图像处理器;及通过至少两个所述图像处理器,对所述待处理图像信号进行处理。
本申请图像处理***通过接口扩展装置将至少两个图像处理器连接至图像传感器,至少两个图像处理器分别进行图像处理,如此设计时可以在保证图像信号质量的同时,更灵活地选择图像处理器,不受限于某一个图像处理器的功能,可以利用不同图像处理器的优点实现更多更高级的功能,使图像处理***的功能可以更丰富,性能更强大。
为了更清楚地说明本申请实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。
图1所示为本申请图像处理***的一个实施例的示意框图。
图2所示为本申请图像处理方法的一个实施例的流程图。
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
这里将详细地对示例性实施例进行说明,其示例表示在附图中。下面的描述涉及附图时,除非另有表示,不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施方式并不代表与本申请相一致的所有实施方式。相反,它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的,而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式,除非上下文清楚地表示其他含义。还应当理解,本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。除非另行指出,“前部”、“后部”、“下部”和/或“上部”等类似词语只是为了便于说明,而并非限于一个位置或者一种空间定向。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而且可以包括电性的连接,不管是直接的还是间接的。“多个”表示至少两个。
本申请实施例的图像处理***包括图像传感器、接口扩展装置和至少两个图像处理器。图像传感器用于感应光信号,并将光信号转换成相应的原始图像信号。图像传感器包括用于输出原始图像信号的图像输出接口。接口扩展装置包括扩展输入接口和至少两组扩展输出接口。扩展输入接口与图像 输出接口电连接,用于接收图像输出接口输出的原始图像信号,至少两组扩展输出接口分别用于输出与原始图像信号对应的待处理图像信号。至少两个图像处理器与至少两组扩展输出接口对应电连接,用于接收待处理图像信号,并对待处理图像信号进行处理。
图像处理***通过接口扩展装置将至少两个图像处理器连接至图像传感器,至少两个图像处理器分别进行图像处理,如此设计时可以在保证图像信号质量的同时,更灵活地选择图像处理器,不受限于某一个图像处理器的功能,可以利用不同图像处理器的优点实现更多更高级的功能,使图像处理***的功能可以更丰富,性能更强大。
本申请实施例的图像处理方法包括:通过图像传感器,感应光信号,并将光信号转换成相应的原始图像信号给接口扩展装置;通过接口扩展装置的至少两组扩展输出接口,将与原始图像信号对应的待处理图像信号发送给至少两个图像处理器;及通过至少两个图像处理器,对待处理图像信号进行处理。
下面结合附图,对本申请的图像处理***和图像处理方法进行详细说明。在不冲突的情况下,下述的实施例及实施方式中的特征可以相互组合。
图1所示为图像处理***100的一个实施例的原理框图。图像处理***100可以用于拍摄设备,例如数字相机,当然还可用于其他设备。图像处理***100可以包括数字图像处理***。本申请实施例的图像处理***100包括图像传感器101、接口扩展装置102和至少两个图像处理器,即第一图像处理器103、第二图像处理器104。
图像传感器101用于感应光信号,并将光信号转换成相应的原始图像信号。图像传感器101包括用于输出原始图像信号的图像输出接口105。图像传感器101可以将光信号转换为模拟电信号,并将模拟电信号转换为数字信 号,原始图像信号可以是数字信号。在一些实施例中,图像传感器101包括CMOS(Complementary Metal Oxide Semiconductor,互补金属氧化物半导体)图像传感器或CCD(Charge-coupled Device,电荷耦合器件)图像传感器。图像传感器101可以包括CMOS图像传感器或CCD图像传感器,所述CMOS图像传感器或CCD图像传感器可以支持多通道输出,每个通道的带宽不低于200Mbps,并且具有高分辨率和高帧率的特点,传输数据量大。例如图像传感器101可以是4/3英寸CMOS图像传感器或者1英寸CMOS图像传感器。
图像输出接口105包括多通道的数据接口。例如,9个通道的数据接口,其中一个通道输出时钟信号clk0,其他8个通道输出图像数据lane00-lane0n,n为自然数。在这个例子中,n为7,但不限于此,在其他例子中,图像输出接口105可以包括其他个数通道的数据接口。在一些实施例中,数据接口的单通道的带宽不低于200Mbps。在一些实施例中,数据接口的单通道的带宽可以达到300Gbps以上。在一些实施例中,数据接口的单通道的带宽可以达到1Gbps以上。数据接口为高速数据接口,可以高速传输高端图像传感器的原始图像信号。在一个实施例中,数据接口包括串行数据接口。在一个实施例中,串行数据接口包括LVDS(Low Voltage Differential Signaling,低电压差分信号)接口或MIPI(Mobile Industry Processor Interface,移动产业处理器接口)接口。在其他实施例中,串行数据接口可以包括其他高速串行数据接口。
接口扩展装置102包括扩展输入接口106和至少两组扩展输出接口,本实施例中,扩展输出接口为两组,即第一扩展输出接口107、第二扩展输出接口108。扩展输入接口106与图像输出接口105电连接,用于接收图像输出接口输出的原始图像信号,第一扩展输出接口107、第二扩展输出接口108分别用于输出与原始图像信号对应的待处理图像信号。
扩展输入接口106可以与图像输出接口105匹配,图像传感器101通过图像输出接口105输出原始图像信号,接口扩展装置102通过扩展输入接 口106接收原始图像信号。在一个实施例中,扩展输入接口106包括多通道的数据接口。扩展输入接口106的单通道带宽与图像输出接口105的单通道带宽相当,或更高。扩展输入接口106为高速数据接口,满足高端图像传感器101的数据传输。扩展输入接口106可以为串行数据接口。
接口扩展装置102用于从图像传感器101接收时钟信号,且在接收原始图像信号时,调整原始图像信号和时钟信号之间的相位关系,使接收到的原始图像信号的每一路数据与时钟信号之间的相位差基本相同,如此保证接收数据的稳定性。扩展输入接口106中的一个通道接收时钟信号clk0,其他多个通道可以接收原始图像信号的多路数据lane00-lane0n。
在图示实施例中,接口扩展装置102包括两组扩展输出接口,即第一扩展输出接口107、第二扩展输出接口108,分别输出与原始图像信号对应的待处理图像信号。在其他一些实施例中,接口扩展装置102可以包括三组或更多组扩展输出接口。进一步地,即第一扩展输出接口107、第二扩展输出接口108可以包括多路通道,通道个数与图像输出接口105的通道个数和扩展输入接口106的通道数相同。
在一些实施例中,接口扩展装置102用于在输出待处理图像信号时调整待处理图像信号和时钟信号之间的相位关系,使输出的待处理图像信号的每一路数据与时钟信号之间的相位差基本相同,如此保证输出数据的稳定性。图1中第一扩展输出接口107中的一个通道输出时钟信号clk1,其他多个通道可以输出待处理图像信号的多路数据lane10-lane1n。第二扩展输出接口108中的一个通道输出时钟信号clk2,其他多个通道可以输出待处理图像信号的多路数据lane20-lane2n。
在一个实施例中,接口扩展装置102用于通过至少两组扩展输出接口输出与原始图像信号相同的待处理图像信号。接口扩展装置102将原始图像信号分成至少两组输出。例如,图中第一扩展输出接口107输出的待处理图像信号lane10-lane1n和第二扩展输出接口108输出的待处理图像信号 lane20-lane2n可以均与图像传感器101输出的原始图像信号lane00-lane0n相同。
在另一个实施例中,待处理图像信号包括第一待处理图像信号,接口扩展装置102用于对原始图像信号进行处理,得到第一待处理图像信号,接口扩展装置102用于通过至少一组扩展输出接口,例如实施例中的第一扩展输出接口107和/或第二扩展输出接口108输出第一待处理图像信号。接口扩展装置102可以对原始图像信号进行处理后输出。在一些实施例中,接口扩展装置102用于对原始图像信号进行处理可以包括:对原始图像信号进行像素数量和/或像素位宽的处理。在一种实施例中,对于像素数量的处理可以是对像素分辨率的调整,例如将4K分辨率(4096×2160)调整为1080p分辨率(1920×1080)。在其他一些实施例中,接口扩展装置102可以对原始图像信号进行其他处理。
在一个实施例中,接口扩展装置102的多组扩展输出接口均输出第一待处理图像信号。在另一个实施例中,接口扩展装置102的部分扩展输出接口输出第一待处理图像信号,其他部分扩展输出接口可以输出与第一待处理图像信号不同的图像信号。待处理图像信号可以包括第二待处理图像信号,第二待处理图像信号与第一待处理图像信号不同,接口扩展装置102用于通过至少另一组扩展输出接口输出第二待处理图像信号。例如,图中第一扩展输出接口107可以输出第一待处理图像信号lane10-lane1n,第二扩展输出接口108可以输出第二待处理图像信号lane20-lane2n。在另一个例子中,两组或更多组扩展输出接口输出第一待处理图像信号,和/或,另外两组或更多组扩展输出接口输出第二待处理图像信号。接口扩展装置102可以通过不同的扩展输出接口输出不同的待处理图像信号给对应的图像处理器,例如图1所示的第一图像处理器103和第二图像处理器104,如此可以满足不同的图像处理器所需的图像数据的要求。
在一个实施例中,第二待处理图像信号与原始图像信号相同。在另一 个实施例中,第二待处理图像信号与原始图像信号不同,接口扩展装置102对原始图像信号进行处理,获得第二待处理图像信号。接口扩展装置102可以对原始图像信号进行不同的处理,获得不同的第一待处理图像信号和第二待处理图像信号。在其他一些实施例中,接口扩展装置102可以输出其他不同于第一待处理图像信号和第二待处理图像信号的待处理图像信号。
在一些实施例中,接口扩展装置102包括可编程逻辑器件,可以根据不同的应用和需求进行编程设计,便于设计者设计,较灵活。在一些实施例中,可编程逻辑器件可以包括FPGA(Field-Programmable Gate Array,现场可编程门阵列)。一些FPGA的高速串口的带宽可以达到1Gbps以上,有的甚至可以达到1.5Gbps,可以满足高速图像数据传输需求,可以与很多高端图像传感器匹配,也支持很多图像处理器,因此可以使器件选型更灵活。在另一些实施例中,可编程逻辑器件可以包括CPLD(Complex Programmable Logic Device,复杂可编程逻辑器件),也可以与很多高端图像传感器匹配,并支持很多图像处理器。
可以根据图像传感器101的图像输出接口105的通道数和图像处理器的数目选择合适的可编程逻辑器件,可编程逻辑器件的接口通道数量等于图像输出接口105的通道数量和分成多组扩展输出接口的通道数量的总和。例如,图像传感器101输出一路LVDS时钟数据和8路LVDS图像数据,一共9路LVDS数据,若可编程逻辑器件的1组接口接收图像传感器101的数据,分成2组接口输出待处理图像数据,则需要3组接口,一共是27路LVDS通道。据此可以选择能够支持27路LVDS的可编程逻辑器件。上述仅是一个例子,实际应用中并不限于上述例子。
在另一个实施例中,接口扩展装置102包括ASIC(Application Specific Integrated Circuit,专用集成电路)芯片。可以根据实际应用,定制ASIC芯片。
至少两个图像处理器与至少两组扩展输出接口对应电连接,用于接收待处理图像信号,并对待处理图像信号进行处理。在图示实施例中,图像处 理***100包括两个图像处理器,即第一图像处理器103和第二图像处理器104,第一图像处理器103与第一扩展输出接口107连接,第二图像处理器104与第二扩展输出接口108连接。在其他实施例中,图像处理***100可以包括三个或更多个图像处理器,连接至对应的扩展输出接口。
如此,图像处理***100通过接口扩展装置102将至少两个图像处理器连接至图像传感器101,特别是对于高端图像传感器,可以实现图像数据的高效传输。进一步地,可以通过至少两个图像处理器分别进行图像处理,如此设计时可以更灵活地选择图像处理器,不受限于某一个图像处理器的功能,可以利用不同图像处理器的优点,在各自专注的功能中可以做到更高的性能指标,实现更多更高级的功能,使图像处理***的功能可以更丰富,性能更强大。
在一个实施例中,至少两个图像处理器包括第一图像处理器103和第二图像处理器104,第二图像处理器104对待处理图像信号的处理至少部分不同于第一图像处理器103对待处理图像信号的处理。第一图像处理器103和第二图像处理器104可以对待处理图像信号进行完全不同或部分不同的处理,获得不同的处理后的图像。第一图像处理器103和第二图像处理器104接收的待处理图像信号可以相同或不同。
在一个实施例中,第一图像处理器103和第二图像处理器104包括不同的芯片。不同的芯片可以专注不同的处理,通过不同的芯片实现不同的功能。在另一个实施例中,第一图像处理器103和第二图像处理器104包括相同的芯片,可以通过相同的芯片对数据进行不同的处理,实现不同的功能,减轻单独一个芯片的工作量,提高运算速度。
在一个实施例中,至少两个图像处理器用于对待处理图像信号进行图像信号处理、图像显示、图像压缩、图像存储、图像传输中的至少一种。例如,在本实施例中,第一图像处理器103和第二图像处理器104对待处理图像信号进行不同的处理可以包括:对待处理图像信号进行不同种类的处理, 例如图像信号处理和图像显示两个不同种类的处理,和/或,对待处理图像信号进行相同种类但方式不同的处理,例如不同标准的图像压缩处理。
在一个实施例中,图像信号处理包括第一图像信号处理,第一图像处理器103用于对待处理图像信号进行第一图像信号处理。例如,可以对待处理图像信号进行像素数量的处理、像素位宽的处理、图像变换、图像增强和复原、图像分割、图像描述和/或图像识别等处理。
在一个实施例中,第二图像处理器104用于对待处理图像信号进行第一图像压缩。如此,第一图像处理器103可以专注于图像信号处理,第二图像处理器104可以专注于图像压缩。
在一个实施例中,第一图像处理器103用于对待处理图像信号进行第一图像信号处理后,进一步用于对待处理图像信号进行第二图像压缩,其中,第二图像压缩不同于第一图像压缩。第一图像处理器103也可对图像进行压缩,第一图像处理器103和第二图像处理器104可以进行不同标准的图像压缩,获得不同的压缩图像。在一个实施例中,第二图像压缩获得的图像的图像质量高于第一图像压缩获得的图像的图像质量。例如第一图像处理器103进行H.264标准的图像压缩,第二图像处理器104进行图像质量更高的JPEG2000标准的图像压缩,或者H265标准的图像压缩,实现更高级别的图像压缩功能。
在另一个实施例中,第二图像处理器104用于对待处理图像信号进行第一图像存储。如此,第一图像处理器103可以专注于图像信号处理,第二图像处理器104可以专注于图像存储。
在一个实施例中,第一图像处理器103用于对待处理图像信号进行第一图像信号处理后,进一步用于对待处理图像信号进行第二图像存储,第一图像存储不同于第二图像存储。第一图像处理器103也可对图像进行存储,第一图像处理器103和第二图像处理器104可以进行不同存储容量的图像存 储。在一个实施例中,第二图像处理器104的存储容量大于第一图像处理器103的存储容量。第二图像处理器104可以进行专业的图像存储,可以支持更高的存储带宽,保存图像质量更高的图像。例如,第一图像处理器103通过SD卡进行图像存储,第二图像处理器104通过存储带宽和/或存储容量比SD卡大的存储设备对于图像进行存储,例如固态硬盘(Solid-state drive,SSD)或通用闪存存储(Universal Flash Storage,UFS)等合适的存储设备。
在另一个实施例中,第二图像处理器104用于第二图像信号处理,第二图像处理器104执行的第二图像信号处理不同于第一图像处理器103执行的第一图像信号处理。第一图像信号处理的算法与第二图像信号处理的算法不同,获得不同的图像。第二图像处理器104可以相对于第一图像处理器103进行简单的图像信号处理。例如,第一图像信号处理包括对待处理图像信号进行图像变换、图像增强和复原、图像分割、图像描述和图像识别等处理,第二图像信号处理包括对待处理图像信号进行像素数量的处理和像素位宽的处理。例如,第一图像处理器103可以进行诸如人像识别的图像识别,以完成后续的图像信号处理,第二图像处理器104进行典型的数码相机的图像显示和/或图像存储。上述仅是列举的例子,并不限于上述例子。第一图像处理器103和第二图像处理器104可以根据实际需求进行不同的图像信号处理。
在一些实施例中,第二图像处理器104可以进行图像压缩、图像存储和第二图像信号处理中的至少两个功能。在一个实施例中,第二图像处理器104包括专注于图像压缩的芯片,对待处理图像信号进行第二图像信号处理,对处理后的图像进行压缩。在另一个实施例中,第二图像处理器104包括专注于图像存储的芯片,对待处理图像信号进行第二图像信号处理,对处理后的图像进行存储。在又一个实施例中,第二图像处理器104对待处理图像信号进行第二图像信号处理,对处理后的图像进行压缩并存储。
在一些实施例中,第一图像处理器103还可用于图像显示的处理,将图像信号处理为适于显示的数据,例如HDMI(High Definition Multimedia Interface,高清晰度多媒体接口)图像显示的处理。在一些实施例中,第一图像处理器103还可用于图像传输的处理。图像传输包括无线图像传输,第一图像处理器103可以用于将处理后的图像通过无线方式发送给其他设备。在其他一些实施例中,第一图像处理器103和/或第二图像处理器104还可进行其他图像处理,例如第二图像处理器104可用于图像显示和/或图像传输。
在一个实施例中,至少两个图像处理器之间通信连接。例如,在本实施例中,第一图像处理器103和第二图像处理器104之间可以进行通信,协同工作。例如,第一图像处理器103处理后的图像信号可以发送给第二图像处理器104,第二图像处理器104可以对该图像信号做压缩、存储等。如此实现更多更高级的功能,可以满足不同的需求,使设计更灵活。在一个实施例中,至少两个图像处理器可以有线连接。在一个实施例中,第一图像处理器103和第二图像处理器104之间可以通过UART接口或者I2C接口或者SPI接口通信连接。在另一个实施例中,至少两个图像处理器无线连接。
图2所示为图像处理方法200的一个实施例的流程图。图像处理方法200可以通过图1所示的图像处理***执行。图像处理方法200包括步骤201-203。在步骤201中,通过图像传感器,感应光信号,并将光信号转换成相应的原始图像信号给接口扩展装置。图像传感器可以是图1所示的图像传感器101,接口扩展装置可以是图1所示的接口扩展装置102。在一个实施例中,图像传感器包括CMOS图像传感器或CCD图像传感器。
在步骤202中,通过接口扩展装置的至少两组扩展输出接口,将与原始图像信号对应的待处理图像信号发送给至少两个图像处理器。图像处理器可以是图1所示的第一图像处理器103和第二图像处理器104。在步骤203中,通过至少两个图像处理器,对待处理图像信号进行处理。
图像处理方法通过接口扩展装置将与图像传感器输出的原始图像信号对应的待处理图像信号发送给至少两个图像处理器进行处理,可以通过多个图像处理器对待处理图像信号进行不同的处理,如此设计时可以在保证 图像信号质量的同时,更灵活地选择图像处理器,不受限于某一个图像处理器的功能,可以利用不同图像处理器的优点实现更多更高级的功能,实现的功能可以更丰富,性能更强大。
在一个实施例中,步骤201包括:通过图像传感器的多通道的数据接口,将原始图像信号输出给接口扩展装置。在一个实施例中,数据接口的单通道的带宽不低于200Mbps。在一个实施例中,数据接口包括串行数据接口。在一个实施例中,串行数据接口包括LVDS接口或MIPI接口。
在一个实施例中,待处理图像信号与原始图像信号相同。在另一个实施例中,待处理图像信号包括第一待处理图像信号;步骤202包括:通过接口扩展装置,对原始图像信号进行处理,得到第一待处理图像信号;且通过至少一组扩展输出接口将第一待处理图像信号发送给至少一个图像处理器。在一个实施例中,通过接口扩展装置,对原始图像信号进行像素数量和/或像素位宽变化的处理。在一个实施例中,待处理图像信号包括第二待处理图像信号;步骤202包括:通过至少另一组扩展输出接口,将第二待处理图像信号发送给至少另一个图像处理器。
在一个实施例中,接口扩展装置包括可编程逻辑器件。在一个实施例中,可编程逻辑器件包括FPGA或CPLD。在另一个实施例中,接口扩展装置包括ASIC芯片。
在一个实施例中,图像处理方法包括:通过接口扩展装置从图像传感器接收时钟信号,且在接收原始图像信号时,调整原始图像信号和时钟信号之间的相位关系。在一个实施例中,通过接口扩展装置,在输出待处理图像信号时,调整待处理图像信号和时钟信号之间的相位关系。
在一个实施例中,至少两个图像处理器包括第一图像处理器和第二图像处理器。步骤203包括:通过第一图像处理器和第二图像处理器分别对待处理图像信号进行处理;其中,通过第一图像处理器对待处理图像的处理至 少部分不同于通过第二图像处理器对待处理图像信号的处理。在一个实施例中,第一图像处理器和第二图像处理器包括不同的芯片。在另一个实施例中,第一图像处理器和所述第二图像处理器包括相同的芯片。
在一个实施例中,步骤203包括:对图像信号进行图像信号处理、图像显示、图像压缩、存储和图像传输中的至少一种。在一个实施例中,步骤203包括:通过第一图像处理器对待处理图像信号进行第一图像信号处理。在一个实施例中,步骤203包括:通过第二图像处理器对待处理图像信号进行第一图像压缩。
在一个实施例中,步骤203包括:对待处理图像信号进行第一图像信号处理后,通过第一图像处理器进一步对待处理图像进行第二图像压缩,其中,第二图像压缩不同于第一图像压缩。在一个实施例中,第二图像压缩获得的图像的图像质量高于第一图像压缩获得的图像的图像质量。
在一个实施例中,步骤203包括:通过第二图像处理器对待处理图像信号进行第一图像存储。在一个实施例中,步骤203包括:对待处理图像信号进行第一图像信号处理后,通过第一图像处理器进一步对待处理图像进行第二图像存储,第一图像存储不同于第二图像存储。在一个实施例中,第二图像处理器的存储容量大于第一图像处理器的存储容量。
在一个实施例中,步骤203包括:通过第二图像处理器进行第二图像信号处理,第二图像信号处理不同于第一图像信号处理。
在一个实施例中,图像处理方法200包括:在至少两个图像处理器之间进行通信。在一个实施例中,通过有线方式在至少两个图像处理器之间进行通信。在一个实施例中,通过UART接口或者I2C接口或者SPI接口,在至少两个图像处理器之间进行通信。在另一个实施例中,通过无线方式在至少两个图像处理器之间进行通信。
对于方法实施例而言,由于其基本对应于装置实施例,所以相关之处 参见装置实施例的部分说明即可。方法实施例和装置实施例互为补充。
需要说明的是,在本文中,诸如“第一”和“第二”等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本发明实施例所提供的方法和装置进行了详细介绍,本文中应用了具体个例对本发明的原理及实施方式进行了阐述,以上实施例的说明只是用于帮助理解本发明的方法及其核心思想;同时,对于本领域的一般技术人员,依据本发明的思想,在具体实施方式及应用范围上均会有改变之处,综上所述,本说明书内容不应理解为对本发明的限制。
本专利文件披露的内容包含受版权保护的材料。该版权为版权所有人所有。版权所有人不反对任何人复制专利与商标局的官方记录和档案中所存在的该专利文件或者该专利披露。
Claims (62)
- 一种图像处理***,其特征在于,其包括:图像传感器,用于感应光信号,并将所述光信号转换成相应的原始图像信号,所述图像传感器包括用于输出原始图像信号的图像输出接口;接口扩展装置,包括扩展输入接口和至少两组扩展输出接口,所述扩展输入接口与所述图像输出接口电连接,用于接收所述图像输出接口输出的所述原始图像信号,至少两组所述扩展输出接口分别用于输出与所述原始图像信号对应的待处理图像信号;及至少两个图像处理器,与至少两组所述扩展输出接口对应电连接,用于接收所述待处理图像信号,并对所述待处理图像信号进行处理。
- 根据权利要求1所述的图像处理***,其特征在于,所述接口扩展装置用于通过至少两组所述扩展输出接口输出与所述原始图像信号相同的所述待处理图像信号。
- 根据权利要求1所述的图像处理***,其特征在于,所述待处理图像信号包括第一待处理图像信号,所述接口扩展装置用于对所述原始图像信号进行处理,得到所述第一待处理图像信号,所述接口扩展装置用于通过至少一组所述扩展输出接口输出所述第一待处理图像信号。
- 根据权利要求3所述的图像处理***,其特征在于,所述接口扩展装置用于对所述原始图像信号进行处理包括:对所述原始图像信号进行像素数量和/或像素位宽的处理。
- 根据权利要求3所述的图像处理***,其特征在于,所述待处理图像信号包括第二待处理图像信号,所述第二待处理图像信号与所述第一待处理图像信号不同,所述接口扩展装置用于通过至少另一组所述扩展输出接口输出所述第二待处理图像信号。
- 根据权利要求1所述的图像处理***,其特征在于,所述图像输出接口包括多通道的数据接口。
- 根据权利要求6所述的图像处理***,其特征在于,所述数据接口的单通道的带宽不低于200Mbps。
- 根据权利要求6所述的图像处理***,其特征在于,所述数据接口包括串行数据接口。
- 根据权利要求8所述的图像处理***,其特征在于,所述串行数据接口包括LVDS接口或MIPI接口。
- 根据权利要求1所述的图像处理***,其特征在于,所述接口扩展装置包括可编程逻辑器件。
- 根据权利要求10所述的图像处理***,其特征在于,所述可编程逻辑器件包括FPGA或CPLD。
- 根据权利要求1所述的图像处理***,其特征在于,所述接口扩展装置包括ASIC芯片。
- 根据权利要求1所述的图像处理***,其特征在于,至少两个所述图像处理器包括第一图像处理器和第二图像处理器,所述第二图像处理器对所述待处理图像信号的处理至少部分不同于所述第一图像处理器对所述待处理图像信号的处理。
- 根据权利要求13所述的图像处理***,其特征在于,所述第一图像处理器和所述第二图像处理器包括不同的芯片。
- 根据权利要求13所述的图像处理***,其特征在于,所述第一图像处理器和所述第二图像处理器包括相同的芯片。
- 根据权利要求13所述的图像处理***,其特征在于,至少两个所述图像处理器用于对所述待处理图像信号进行图像信号处理、图像显示、图像压缩、图像存储、图像传输中的至少一种。
- 根据权利要求16所述的图像处理***,其特征在于,所述第一图像处理器用于对待处理图像信号进行第一图像信号处理。
- 根据权利要求17所述的图像处理***,其特征在于,所述第二图像处理器用于对待处理图像信号进行第一图像压缩。
- 根据权利要求18所述的图像处理***,其特征在于,所述第一图像处理器用于对待处理图像信号进行第一图像信号处理后,进一步用于对待处理图像信号进行第二图像压缩,其中,所述第二图像压缩不同于所述第一图像压缩。
- 根据权利要求19所述的图像处理***,其特征在于,所述第二图像压缩获得的图像的图像质量高于所述第一图像压缩获得的图像的图像质量。
- 根据权利要求17所述的图像处理***,其特征在于,所述第二图像处理器用于对待处理图像信号进行第一图像存储。
- 根据权利要求21所述的图像处理***,其特征在于,所述第一图像处理器用于对待处理图像信号进行第一图像信号处理后,进一步用于对待处理图像信号进行第二图像存储,所述第一图像存储不同于所述第二图像存储。
- 根据权利要求22所述的图像处理***,其特征在于,所述第二图像处理器的存储容量大于所述第一图像处理器的存储容量。
- 根据权利要求17所述的图像处理***,其特征在于,所述第二图像处理器用于第二图像信号处理,所述第二图像处理器执行的第二图像信号处理不同于所述第一图像处理器执行的第一图像信号处理。
- 根据权利要求1所述的图像处理***,其特征在于,至少两个所述图像处理器之间通信连接。
- 根据权利要求25所述的图像处理***,其特征在于,至少两个所述图像处理器有线连接。
- 根据权利要求26所述的图像处理***,其特征在于,至少两个所述图像处理器之间通过UART接口或者I2C接口或者SPI接口通信连接。
- 根据权利要求25所述的图像处理***,其特征在于,至少两个所述图像处理器无线连接。
- 根据权利要求1所述的图像处理***,其特征在于,所述接口扩 展装置用于从所述图像传感器接收时钟信号,且在接收所述原始图像信号时,调整所述原始图像信号和所述时钟信号之间的相位关系。
- 根据权利要求1所述的图像处理***,其特征在于,所述接口扩展装置用于在输出所述待处理图像信号时调整所述待处理图像信号和时钟信号之间的相位关系。
- 根据权利要求1所述的图像处理***,其特征在于,所述图像传感器包括CMOS图像传感器或CCD图像传感器。
- 一种图像处理方法,其特征在于,其包括:通过图像传感器,感应光信号,并将所述光信号转换成相应的原始图像信号给接口扩展装置;通过所述接口扩展装置的至少两组扩展输出接口,将与所述原始图像信号对应的待处理图像信号发送给至少两个图像处理器;及通过至少两个所述图像处理器,对所述待处理图像信号进行处理。
- 根据权利要求32所述的图像处理方法,其特征在于,所述待处理图像信号与所述原始图像信号相同。
- 根据权利要求32所述的图像处理方法,其特征在于,所述待处理图像信号包括第一待处理图像信号;所述方法包括:通过所述接口扩展装置,对所述原始图像信号进行处理,得到所述第一待处理图像信号;且通过至少一组所述扩展输出接口将所述第一待处理图像信号发送给至少一个所述图像处理器。
- 根据权利要求34所述的图像处理方法,其特征在于,所述通过所述接口扩展装置,对所述原始图像信号进行处理,得到所述第一待处理图像信号,包括:对所述原始图像信号进行像素数量和/或像素位宽变化的处理。
- 根据权利要求34所述的图像处理方法,其特征在于,所述待处理图像信号包括第二待处理图像信号;所述通过所述接口扩展装置的至少两组扩展输出接口,将与所述原始 图像信号对应的待处理图像信号发送给至少两个图像处理器,包括:通过至少另一组所述扩展输出接口,将所述第二待处理图像信号发送给至少另一个所述图像处理器。
- 根据权利要求32所述的图像处理方法,其特征在于,所述通过图像传感器,感应光信号,并将所述光信号转换成相应的原始图像信号给接口扩展装置,包括:通过所述图像传感器的多通道的数据接口,将所述原始图像信号输出给所述接口扩展装置。
- 根据权利要求37所述的图像处理方法,其特征在于,所述数据接口的单通道的带宽不低于200Mbps。
- 根据权利要求37所述的图像处理方法,其特征在于,所述数据接口包括串行数据接口。
- 根据权利要求39所述的图像处理方法,其特征在于,所述串行数据接口包括LVDS接口或MIPI接口。
- 根据权利要求32所述的图像处理方法,其特征在于,所述接口扩展装置包括可编程逻辑器件。
- 根据权利要求41所述的图像处理方法,其特征在于,所述可编程逻辑器件包括FPGA或CPLD。
- 根据权利要求32所述的图像处理方法,其特征在于,所述接口扩展装置包括ASIC芯片。
- 根据权利要求32所述的图像处理方法,其特征在于,至少两个所述图像处理器包括第一图像处理器和第二图像处理器;所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:通过所述第一图像处理器和所述第二图像处理器分别对所述待处理图像信号进行处理;其中,通过所述第一图像处理器对所述待处理图像的处理至少部分不同于通过所述第二图像处理器对所述待处理图像信号的处 理。
- 根据权利要求44所述的图像处理方法,其特征在于,所述第一图像处理器和所述第二图像处理器包括不同的芯片。
- 根据权利要求44所述的图像处理方法,其特征在于,所述第一图像处理器和所述第二图像处理器包括相同的芯片。
- 根据权利要求44所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:对所述图像信号进行图像信号处理、图像显示、图像压缩、存储和图像传输中的至少一种。
- 根据权利要求47所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:通过所述第一图像处理器对所述待处理图像信号进行第一图像信号处理。
- 根据权利要求48所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:通过所述第二图像处理器对所述待处理图像信号进行第一图像压缩。
- 根据权利要求49所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:对待处理图像信号进行第一图像信号处理后,通过所述第一图像处理器进一步对所述待处理图像进行第二图像压缩,其中,所述第二图像压缩不同于所述第一图像压缩。
- 根据权利要求50所述的图像处理方法,其特征在于,所述第二图像压缩获得的图像的图像质量高于所述第一图像压缩获得的图像的图像质量。
- 根据权利要求48所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:通过所述第二图像处理器对所述待处理图像信号进行第一图像存储。
- 根据权利要求52所述的图像处理方法,其特征在于,所述通过 至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:对待处理图像信号进行第一图像信号处理后,通过所述第一图像处理器进一步对所述待处理图像进行第二图像存储,所述第一图像存储不同于所述第二图像存储。
- 根据权利要求53所述的图像处理方法,其特征在于,所述第二图像处理器的存储容量大于所述第一图像处理器的存储容量。
- 根据权利要求48所述的图像处理方法,其特征在于,所述通过至少两个所述图像处理器,对所述待处理图像信号进行处理,包括:通过所述第二图像处理器进行第二图像信号处理,所述第二图像信号处理不同于所述第一图像信号处理。
- 根据权利要求32所述的图像处理方法,其特征在于,所述方法包括:在至少两个所述图像处理器之间进行通信。
- 根据权利要求56所述的图像处理方法,其特征在于,所述在至少两个所述图像处理器之间进行通信,包括:通过有线方式在至少两个所述图像处理器之间进行通信。
- 根据权利要求57所述的图像处理方法,其特征在于,所述在至少两个所述图像处理器之间进行通信,包括:通过UART接口或者I2C接口或者SPI接口,在至少两个所述图像处理器之间进行通信。
- 根据权利要求56所述的图像处理方法,其特征在于,所述在至少两个所述图像处理器之间进行通信,包括:通过无线方式在至少两个所述图像处理器之间进行通信。
- 根据权利要求32所述的图像处理方法,其特征在于,所述方法包括:通过所述接口扩展装置从所述图像传感器接收时钟信号,且在接收所述原始图像信号时,调整所述原始图像信号和所述时钟信号之间的相位关系。
- 根据权利要求32所述的图像处理方法,其特征在于,所述通过所述接口扩展装置的至少两组扩展输出接口,将与所述原始图像信号对应 的待处理图像信号发送给至少两个图像处理器,包括:通过所述接口扩展装置,在输出所述待处理图像信号时,调整所述待处理图像信号和时钟信号之间的相位关系。
- 根据权利要求32所述的图像处理方法,其特征在于,所述图像传感器包括CMOS图像传感器或CCD图像传感器。
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