WO2020048537A1 - 级联编码的方法和装置 - Google Patents

级联编码的方法和装置 Download PDF

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Publication number
WO2020048537A1
WO2020048537A1 PCT/CN2019/104786 CN2019104786W WO2020048537A1 WO 2020048537 A1 WO2020048537 A1 WO 2020048537A1 CN 2019104786 W CN2019104786 W CN 2019104786W WO 2020048537 A1 WO2020048537 A1 WO 2020048537A1
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code
subsequence
codeword
length
coding
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PCT/CN2019/104786
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English (en)
French (fr)
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张华滋
李榕
王献斌
皇甫幼睿
童佳杰
王俊
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华为技术有限公司
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Definitions

  • the present application relates to the field of coding, and in particular, to a method and an apparatus for concatenated coding.
  • Polar codes are a structured channel coding method that has been theoretically strictly proven to reach the channel capacity. In recent years, it has been widely used and made great progress. However, with the rapid evolution of wireless communication systems, some new features will emerge in future communication systems (eg, 5G). For example, high-reliability and low-latency communication (URLLC), which is one of the three most typical three communication scenarios in 5G, has very high requirements for the reliability and delay of data transmission.
  • the most popular decoding method for polar codes is a serial cancellation list (SCL) decoding algorithm.
  • SCL decoding algorithm is judged and outputted bit by bit during decoding. The decoding delay is relatively large and needs to be further optimized.
  • the present application provides a method and a device for cascade coding, which can reduce the decoding delay of a polar code.
  • a concatenated coding method includes: group coding an information bit sequence to obtain a plurality of first codewords having a code length B, where B ⁇ 1 and an integer; The first codeword undergoes n-level polarization coding to obtain a second codeword with a code length of B ⁇ 2 n, where n ⁇ 1 and is an integer; and the second codeword is transmitted.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • Sequence determining the generation matrix required to encode each subsequence according to the number of bits included in each of the plurality of subsequences; using the generation matrix corresponding to each subsequence in the plurality of subsequences for the plurality of subsequences Encoding is performed to obtain a plurality of first codewords having a code length of B.
  • each subsequence of the information bit sequence can be encoded using any one of the following codes: repeating code, BCH code, simplex code, dual code of BCH code, polar Code, parity check code, dual code of simplex code.
  • an encoding device in a second aspect, has a function of implementing the method in the first aspect and any possible implementation manners thereof.
  • the functions may be implemented by hardware, and may also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the encoding device when part or all of the functions are implemented by hardware, includes: an input interface circuit for acquiring an information bit sequence to be encoded; and a logic circuit for performing an information bit sequence Group coding to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; perform n-level polarization coding on the multiple first codewords to obtain a second code with a length of B ⁇ 2 n Words, n ⁇ 1 and an integer; an output interface circuit for outputting the second codeword.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • the encoding device may be a chip or an integrated circuit.
  • the encoding device when part or all of the functions are implemented by software, the encoding device includes: a memory for storing a computer program; and a processor for executing the computer program stored in the memory.
  • the encoding device can implement the cascade encoding method described in the first aspect and any possible design of the first aspect.
  • the memory may be a physically separate unit or integrated with the processor.
  • the encoding device when part or all of the functions are implemented by software, the encoding device includes only a processor.
  • the memory for storing the program is located outside the encoding device, and the processor is connected to the memory through a circuit / wire for reading and running the program stored in the memory to execute the first aspect described above and any possible implementation of the first aspect Method of concatenated coding in.
  • the present application provides a decoding method, which includes: obtaining a bit sequence to be decoded, the length of the bit sequence to be decoded is N, and N is a positive integer; performing SCL translation on the bit sequence to be decoded Code to obtain N / B sub-code blocks, hard-decision the bits in each sub-code block of the N / B sub-code blocks, to obtain a hard decision result of each sub-code block, and The judgment results query the symptom diagnosis table to obtain multiple candidate codewords for each subcode block; calculate path metric values of multiple candidate codewords for each subcode block, and calculate path metrics for multiple candidate codewords for each subcode block Value to determine the decoding path of each sub-code block; multiple decoding paths corresponding to the multiple sub-code blocks are sequentially output as the decoding result.
  • the present application provides a decoding device having the function of implementing the method in the third aspect and any possible implementations thereof.
  • the functions may be implemented by hardware, and may also be implemented by hardware executing corresponding software.
  • the hardware or software includes one or more units corresponding to the functions described above.
  • the decoding device when part or all of the functions are implemented by hardware, includes: an input interface circuit for acquiring a bit sequence to be decoded; and a logic circuit for performing the above third
  • the decoding method in an aspect decodes the bit sequence to be decoded to obtain a decoding result; and an output interface circuit is used to output the decoding result.
  • the decoding device may be a chip or an integrated circuit.
  • the decoding device when part or all of the functions are implemented by software, the decoding device includes: a memory for storing a computer program; and a processor for executing the computer program stored in the memory.
  • the decoding device can implement the decoding method according to the third aspect.
  • the memory may be a physically separate unit or integrated with the processor.
  • the decoding device when part or all of the functions are implemented by software, the decoding device includes only a processor.
  • the memory for storing the program is located outside the encoding device, and the processor is connected to the memory through a circuit / wire for reading and running the program stored in the memory to perform the decoding method described in the third aspect.
  • the decoding device may be a chip or an integrated circuit.
  • the present application provides a network device, including a transceiver, a processor, and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store the computer program
  • the processor is used to call and run the computer program stored in the memory, so that the network device executes the method in any possible implementation manner of the first or second aspect.
  • the network device executes the cascading method in the first aspect and any possible implementation manners of the method, and performs ranking on the information and / or data to be sent.
  • Link encoding When the network device serves as a receiving end of information and / or data, the network device executes the decoding method according to the third aspect, and decodes the bit sequence to be decoded received from the transmitting end.
  • the present application provides a terminal device including a transceiver, a processor, and a memory.
  • the processor is used to control the transceiver to send and receive signals
  • the memory is used to store the computer program
  • the processor is used to call and run the computer program stored in the memory, so that the terminal device executes the method in any possible implementation manner of the first aspect or the second aspect.
  • the terminal device when the terminal device serves as a sender of information and / or data, the terminal device executes the cascading method in the first aspect and any possible implementation manners of the terminal device, and performs ranking on the information and / or data to be transmitted Link encoding.
  • the terminal device executes the decoding method according to the third aspect, and decodes the bit sequence to be decoded received from the transmitting end.
  • the present application provides a computer-readable storage medium having instructions stored in the computer-readable storage medium, which when executed on a computer, causes the computer to execute the first aspect or any possible implementation manner of the first aspect Method.
  • the present application provides a computer program product including computer program code.
  • the computer program code runs on a computer, the computer causes the computer to execute the first aspect and any one of its possible implementation manners. method.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform the foregoing first aspect or the method in any possible implementation manner of the first aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be encoded.
  • the processor obtains the information bit sequence from the communication interface and uses the cascade encoding method described in the first aspect to perform cascade encoding on the information bit sequence. After the communication interface outputs the encoding, Sequence of bits.
  • the communication interface may be an input-output interface.
  • the present application provides a computer-readable storage medium, where the computer-readable storage medium stores instructions, and when it runs on a computer, causes the computer to execute the third aspect or any possible implementation manner of the third aspect Method.
  • the present application provides a computer program product.
  • the computer program product includes computer program code, and when the computer program code runs on a computer, the computer executes the third aspect or any possible implementation manner of the third aspect. Methods.
  • the present application provides a chip including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform the method in the third aspect or any possible implementation manner of the third aspect.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be decoded.
  • the processor obtains the bit sequence to be decoded from the communication interface, and uses the decoding method described in the third aspect to decode the bit sequence to be decoded to obtain Decoding result; the communication interface outputs the decoding result.
  • the communication interface may be an input-output interface.
  • the present application provides a communication system including the network device according to the fifth aspect and the terminal device according to the sixth aspect.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into multiple groups and encodes them respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • FIG. 1 is an architecture diagram of a wireless communication system 100 applicable to an embodiment of the present application.
  • Fig. 2 is a basic flowchart of communication using wireless technology.
  • FIG. 3 is a schematic diagram of polar polarization code encoding.
  • Figure 4 is a schematic diagram of the input and output of an F2 polarization network.
  • FIG. 5 is a schematic flowchart of a concatenated coding method 200 provided in the present application.
  • FIG. 9 is a schematic block diagram of a communication device 500 provided in the present application.
  • FIG. 10 is a schematic structural diagram of a communication device 600 provided in the present application.
  • FIG. 11 is a schematic diagram of the internal structure of the processing device 601.
  • FIG. 12 is a schematic block diagram of a communication device 700 provided in the present application.
  • FIG. 13 is a schematic block diagram of a communication device 800 provided in the present application.
  • FIG. 14 is a schematic diagram of the internal structure of the processing device 802.
  • FIG. 15 is a schematic structural diagram of a network device 3000 provided in the present application.
  • FIG. 16 is a schematic structural diagram of a terminal device 900 provided in the present application.
  • FIG. 1 is a structural diagram of a wireless communication system 100 applicable to an embodiment of the present application.
  • the wireless communication system 100 may include at least one network device and one or more terminal devices.
  • a network device (such as 101 shown in FIG. 1) can wirelessly communicate with the one or more terminal devices (such as 102 and 103 shown in FIG. 1).
  • the wireless communication system involved in this application includes, but is not limited to, a global mobile communications (GSM) system, a code division multiple access (CDMA) system, and a wideband code division multiple access (wideband code division).
  • GSM global mobile communications
  • CDMA code division multiple access
  • WCDMA wideband code division multiple access
  • GPRS general packet radio service
  • LTE long term evolution
  • FDD frequency division duplex
  • TDD time division duplex
  • TDD time division duplex
  • TDD time division duplex
  • TDD time division
  • UMTS universal mobile communication system
  • WiMAX worldwide interoperability for microwave communication
  • next-generation 5G mobile communication system Namely enhanced mobile bandwidth (eMBB), high reliability, low latency communication (ultra low latency communication, URLLC), and enhanced mass machine type communication (eMTC) or new communication systems that will appear in the future .
  • eMBB enhanced mobile bandwidth
  • URLLC ultra low latency communication
  • eMTC enhanced mass machine type communication
  • the terminal equipment involved in the embodiment of the present application may refer to user equipment (UE), terminal, access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user Terminal, terminal, wireless communication device, user agent, or user device.
  • Terminal equipment can also be cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital processing (PDA), and wireless communication Functional handheld devices, computing devices, or other processing devices connected to wireless modems, in-vehicle devices, wearable devices, terminal devices in the future 5G network, or public land mobile network (PLMN) in future evolution Terminal equipment and the like are not limited in this application.
  • SIP session initiation protocol
  • WLL wireless local loop
  • PDA personal digital processing
  • PLMN public land mobile network
  • the network device involved in this application may be a device for communicating with a terminal device.
  • the network device may be a base station, or a device in which the base station is integrated with a base station controller, or may be another device having a similar communication function.
  • the base station referred to here may be a global mobile communication (GSM) system or a base station (BTS) in code division multiple access (CDMA), or a broadband code division.
  • GSM global mobile communication
  • BTS base station
  • CDMA code division multiple access
  • the base station (nodeB, NB) in a multiple access (wideband code division, multiple access, WCDMA) system can also be an evolutionary base station (evolutional nodeB, eNB, or eNodeB) in a long term evolution (LTE) system. It is a wireless controller in a cloud radio access network (CRAN) scenario.
  • the network device may also be a relay station, an access point, a vehicle-mounted device, a wearable device, and a network device
  • Wireless technology is used for communication between the network device and the terminal device in FIG. 1.
  • a network device sends a signal, it is a sending end, and when a network device receives a signal, it is a receiving end.
  • the terminal device is the same.
  • the terminal device sends a signal, it is the sending end, and when the terminal device receives the signal, it is the receiving end.
  • Fig. 2 is a basic flowchart of communication using wireless technology.
  • the source at the sending end is transmitted on the channel after source coding, channel coding, rate matching, and modulation.
  • the receiving end obtains the sink after demodulating, de-rate matching, channel decoding, and source decoding.
  • Channel codec is one of the core technologies in the field of wireless communication, and its performance improvement will directly improve network coverage and user transmission rate.
  • polar codes are channel coding technologies that can theoretically prove to reach the Shannon limit and have practical linear complexity coding and decoding capabilities.
  • Polar code is a linear block code. Its coding matrix (also called generator matrix) is F N. The coding process can be expressed by the following formula:
  • F N is an N ⁇ N matrix, Defined as the Kronecker product of log 2 N matrices F 2 ,
  • the addition and multiplication operations involved in the above formulas are all addition and multiplication operations on the binary Galois field.
  • the encoding generated by this method will produce polarization phenomenon through the successful bit-cancellation (SC) decoding method. That is, some bits in u pass through an equivalent high-reliability channel and are translated with a high probability, and the remaining bits pass through an equivalent low-reliability channel and are translated with a low probability. Therefore, one can use a highly reliable channel for information transmission, and set the bits corresponding to the low reliability channel to zero (ie, freeze), not for transmitting data, or transmitting data known to both parties in the communication.
  • SC bit-cancellation
  • FIG. 3 is a schematic diagram of a polar polarization code encoding.
  • the symbol " ⁇ " represents binary addition, and the input is left and bottom, and the output is right.
  • Each solid line in FIG. 3 represents 1 bit.
  • the 8-bit coded bits are modulated and then sent over a noisy channel.
  • the network is polarized.
  • the input and output relationship of the F2 polarization network can be shown in FIG. 4.
  • FIG. 4 is a schematic diagram of input and output of an F2 polarization network.
  • the input-output relationship shown in Figure 4 is described by a formula, which can be expressed as:
  • [x 0 x 1 ] and [u 0 , u 1 ] are binary vectors, and all operations are performed in the binary field.
  • the decoding of polar codes uses the SCL decoding algorithm.
  • the decoder makes decisions and outputs bit by bit, and the decoding delay is large.
  • this application provides a cascade coding method, which can reduce the decoding delay and improve the decoding performance of the polar code.
  • Concatenated coding includes outer code coding and inner code coding.
  • the input of the outer code encoding is an information bit sequence to be encoded, and the output of the outer code is used as the input of the inner code.
  • the output of the inner code encoding is the codeword after the concatenated encoding is completed.
  • the outer code and the inner code are relative concepts. Take a system that includes three encodings as an example. The first encoding is an outer encoding compared to the second encoding, and the second encoding is an inner encoding relative to the first encoding.
  • the second encoding is an outer encoding relative to the third encoding
  • the third encoding is an inner encoding relative to the second encoding.
  • the outer code encoding is performed first, and the inner code encoding is performed later.
  • the output of the outer code encoding is used as the input of the inner code encoding.
  • concatenated encoding involves two encodings.
  • the outer code of the cascade coding is block coding
  • the inner code coding is polar coding
  • FIG. 5 is a schematic flowchart of a concatenated coding method 200 provided by the present application.
  • the method 200 may be performed by a transmitting end.
  • step 210 the encoder obtains the information bit sequence to be encoded, and performs group coding on the information bit sequence to obtain a plurality of first codewords.
  • step 210 is a block encoding process.
  • Block coding is to divide the information bit sequence to be coded into multiple groups and encode each group to obtain multiple first codewords with a code length of B.
  • the code length B of the block code is related to the complexity and delay of the decoding.
  • the code length B of the block code can be set in consideration of the compromise between complexity and delay.
  • step 220 the transmitting end performs n-level polarization coding on the plurality of first codewords obtained by the block coding in step 210 to obtain a second codeword having a length of B ⁇ 2n .
  • the transmitting end performs n-level polarization coding on the first codeword (also, after n polarizations), the obtained concatenated code has The length is B ⁇ 2 n .
  • the length of the concatenated code B ⁇ 2 n can be any size. That is, according to the concatenated coding method provided in this application, a concatenated code of an arbitrary code length can be generated.
  • the outer code coding of the cascade coding uses block coding
  • the inner code coding uses polar coding.
  • the outer code encoding divides the information bit sequence into a plurality of groups and performs encoding, respectively, and the obtained multiple first codewords are used as inputs for polar encoding. Since each first codeword includes multiple bits, the inner code encoding is actually polar encoding in units of a block (ie, the first codeword) including multiple bits. Therefore, when decoding, it is no longer necessary to perform decision and decoding in units of bits, as in the existing SCL decoding algorithm, but to perform decoding in units of blocks. This can reduce the decoding delay.
  • the information bit sequence is block-coded to obtain multiple first codewords with a code length of B, including:
  • N B ⁇ 2 n , where N is an integer
  • the code length of the block code is also set in advance during block coding.
  • the block code refers to the output of the block code, that is, the first codeword in this application. That is to say, before performing concatenated coding, first obtain a preset target code length N and a code length B of the block code. According to the target code length and the code length B of the block code, it is determined that the information bit sequence to be coded is specifically divided into several groups.
  • the process of grouping the information bit sequences involved in the block coding can refer to the prior art, which will not be described in detail here.
  • each subsequence includes one or more bits, or some subsequences may not include bits.
  • a generation matrix required for group coding of each subsequence is determined.
  • each sub-sequence is a sub-block of an information bit sequence, or is called a sub-code block.
  • each subsequence will be encoded into a first codeword with a length B.
  • the number of bits included in the multiple subsequences is not the same. Therefore, the generation matrix required to encode the subsequence needs to be determined according to the number of bits included in each subsequence. That is, each of the plurality of subsequences corresponds to a respective generation matrix.
  • the multiple subsequences are encoded using the multiple generation matrices to obtain multiple first codewords, each codeword having a code length of B.
  • rate matching is performed on the third codeword, and finally a second codeword having a code length of B ⁇ 2 n is obtained.
  • the plurality of codewords having a code length of 3 are subjected to 3 A level of polar coding yields a codeword with a length of 3 ⁇ 2 3 (denoted as the third codeword).
  • rate matching is performed on the third codeword with a code length of 24 (for example, 4 bits are eliminated by puncturing), and a second codeword with a length of 20 is finally obtained.
  • the target code length N and the code length B of the block code that is, the first codeword
  • the level After the concatenated coding the codeword of the target code length can be obtained directly.
  • polar codes which can only generate code lengths that are integer powers of two, no rate matching is required.
  • the target code length N and the code length B of the block code that is, the first codeword
  • R 2 n
  • N B ⁇ R
  • step 210 and step 220 the encoder completes concatenated encoding. After concatenated coding is completed, the second codeword is sent to the receiving end.
  • steps 210 and 230 may be performed by an encoder at the transmitting end.
  • Step 230 may be performed by a transceiver at the transmitting end.
  • the encoder may output the second codeword to the transceiver, so that the transceiver sends the second codeword.
  • the encoder may also send the second codeword to the transceiver after processing such as rate matching and modulation mapping, and then send the second codeword processed after the rate matching and modulation mapping to the transceiver, and the transceiver will send it Send to the receiving end.
  • the encoder performing steps 210 and 220 of the method 200 may include an outer code encoder and an inner code encoder.
  • the outer code encoder obtains the information bit sequence and performs group coding on the information bit sequence to obtain a plurality of first codewords with a code length of B, and completes the concatenated outer code encoding.
  • the outer code encoder inputs the plurality of first codewords to the inner code encoder.
  • the inner code encoder receives the plurality of first code words from the outer code encoder, performs n-level polar encoding on the plurality of first code words, obtains a second code word, and completes the inner code encoding. After the inner code encoding is completed, the inner code encoder outputs the second codeword.
  • the first bit sequence may be bit interleaved, and the interleaved bit sequence is input to the inner code encoder for inner code. coding.
  • the following factors may be considered to select a block code as the outer code.
  • the optimal block code can be selected.
  • some block codes with better code range spectrum characteristics and higher decoding parallelism are selected as outer codes.
  • they are polarized by the F N polarization network. This can improve decoding parallelism and reduce delay.
  • the code length of the outer code block code does not need to be an integer power of 2
  • the code length of the final concatenated code also has more options, and the rate matching process can be omitted, or only a small amount of rate matching is required.
  • the information bit sequence is [u 0 u 1 u 2 u 3 u 4 u 5 ]
  • the information bit sequence is divided into the following 4 subsequences: [u 0 ], [u 1 u 2 ], [u 3 u 4 u 5 ]. among them, Indicates that the subsequence contains no bits.
  • the number of bits contained in each subsequence can also be called the information length of the subsequence. According to the information length of each subsequence, its corresponding generation matrix can be expressed as:
  • the generation matrix can be expressed as
  • the generation matrix can be expressed as
  • the generation matrix can be expressed as
  • the information length is 0, which can be understood as no information input.
  • the outer code encoding uses block encoding.
  • the information bit sequence [u 0 u 1 u 2 u 3 u 4 u 5 ] is encoded by outer code, and finally 4 code words are output, which are [o 0 o 1 o 2 ], [o 3 o 4 o 5 ], [o 6 o 7 o 8 ] and [o 6 o 7 o 8 ], the code length of each codeword is 3.
  • Each codeword here is the first codeword mentioned in this application.
  • the inner code is a polar code.
  • the polarization process of the outer code codeword can be expressed as:
  • K i information bits of the i-th sub-code block of the block code before encoding B codeword bits after encoding the ith sub-code block. Is the generation matrix of the i-th sub-code block, and the size is K i ⁇ B.
  • N bits to be polarization-coded consisting of the j-th codeword bit of each sub-code block, Bits after polarization encoding.
  • the information length of the subsequence is denoted by K, and K is an integer. It should be understood that K ⁇ B.
  • the first column of Table 1 indicates the information length of the subsequence.
  • the second column of Table 1 indicates which code is selected as the outer code when concatenated.
  • the information lengths of the sub-sequences in the second column and the first column of Table 1 correspond. For example, if the information length of a certain subsequence obtained after grouping the information bit sequences is 1, a repeating code is selected as the outer code and the outer code encoding in step 210 is performed. For another example, if the information length of a certain subsequence is 6, the eBCH code is selected as the outer code and the outer code encoding of step 210 is performed. Other messages are similar in length and will not be explained one by one.
  • the third column in Table 1 shows the generator matrix used in the outer code encoding.
  • the third column of Table 1 corresponds to the second column and the first column, respectively.
  • the generator matrix used for outer code encoding is G 1 .
  • the generation matrix used for the outer code encoding is G 3 .
  • G in the third column in Table 1 is a generator matrix, and the matrix S is listed to simplify the representation of the generator matrix G.
  • the matrix H is a check matrix corresponding to some codes, and the generation matrix can be determined according to the check matrix H.
  • the generator matrix of code B is the same as the generator matrix of code A.
  • the check matrix H 9 of the dual code of the eBCH code is equal to the eBCH generation matrix.
  • the repetition code is to repeatedly transmit each bit to be transmitted, or to encode each source bit into multiple identical bits.
  • the binary repeating code (3,1) encodes each 0 in a binary bit sequence as 000 and each 1 as 111. Therefore, when the length of the information sequence is 1, the generation matrix of the repeating code is a 16-bit all-1 matrix.
  • the BCH code is taken from the abbreviations of Bose, Ray-Chaudhuri and Hocquenghem. It is a coding method that has been studied in coding theory, especially error correction codes.
  • the extended BCH code extended BCH, eBCH is obtained by expanding on the basis of the BCH code, and has the characteristics of simple structure and large code distance among known codes.
  • the linear block code generated by using the consistent check matrix of the linear block code as the generation matrix is called the dual coding of the original linear block code. It can be understood that when the length of the information sequence is 9 or 10, the linear block code generated by using the consistent check matrix of the eBCH code as the generation matrix is the dual code of the eBCH.
  • a parity check code is a coding method that adds redundant bits to a codeword so that the number of "1" s in the codeword is always odd or constant.
  • the generalized parity check code can be constructed by a cyclic shift register, whose check bit is the exclusive OR value of the binary value corresponding to the tap position in the register.
  • the shift register is divided into a feedforward shift register and a feedback shift register. If it is a feedforward shift register, the parity check code is a convolution check code. If it is a feedback shift register, the The parity code is a cyclic redundancy check code.
  • the single-bit parity code refers to a code with only one parity bit.
  • the information bit sequence is grouped to obtain multiple subsequences.
  • the corresponding outer code and generation matrix are selected from Table 2 to perform outer code encoding on the subsequence to obtain Multiple first codewords.
  • inner code encoding is performed on a plurality of first codewords obtained by outer code encoding of all subsequences to obtain a concatenated code.
  • the application of the block code to replace the outer code of the polar code herein means that the outer code of the polar code uses the block code described in this application.
  • the polar inner code is continued to be encoded.
  • K 16
  • Table 1 a repetition code is used, which is obtained by repeating the information bits in the sub-block 16 times, which is not listed in Table 2.
  • the first row of Table 2 indicates the code weight, which is the number of 1 in the codeword, and the number in the corresponding column indicates the number of codewords with the code weight.
  • the code weight distribution of all the codewords (such as one line in Table 2, not the first line) is the code distance spectrum of the code.
  • the first column of Table 2 shows the encoding method used for the outer code of the polar code.
  • the second column of Table 2 indicates the information length K of one subblock (ie, the above-mentioned subsequence).
  • the information bit sequence is [u 0 u 1 u 2 u 3 u 4 u 5 ] and is divided into three sub-blocks [u 0 ], [u 1 u 2 ], and [u 3 u 4 u 5 ].
  • the value of the first non-zero element indicates the number of code weights of the column in which the non-zero element is located. Among them, the later the position where the non-zero element appears in the line, the larger the corresponding code weight, indicating better performance. At the same time, for the same code weight, the smaller the corresponding non-zero element is, the smaller the number of code weights, the lower the possibility of bit errors, and the better the performance.
  • the code distance spectrum indicates the number of code weights of the column in which the non-zero element is located. Among them, the later the position where the non-zero element appears in the line, the larger the corresponding code weight, indicating better performance.
  • the smaller the corresponding non-zero element is, the smaller the number of code weights, the lower the possibility of bit errors, and the better the performance.
  • the line corresponding to the polar code has the first non-zero element appearing as 2, and the corresponding code weight is 8, indicating that there are 2 lines with a code weight of 8.
  • the line corresponding to Simplex encoding the first non-zero element that appears is 1, and the corresponding code weight is 10, indicating that there is 1 line with a code weight of 10.
  • the first non-zero element that appears in the row corresponding to the polar code is 6, and the corresponding code weight is 8, indicating that there are 6 rows with a code weight of 8.
  • the line corresponding to the Simplex code the first non-zero element that appears is 1, and the corresponding code weight is 8, indicating that there is 1 line with a code weight of 8.
  • the first non-zero element appears in two rows at the same position, and then the size of the non-zero element.
  • there are 6 lines with a code weight of 8, compared with only one line with a code weight of 8, the probability of bit errors is higher. Therefore, when K 3, simplex coding is used, and the performance is also better than polar coding.
  • the row corresponding to the polar code the first non-zero element that appears is 76, and the corresponding code weight is 4.
  • the first non-zero element that appears is 60, and the corresponding code weight is 4.
  • the position of the first non-zero element is the same (that is, the code weight corresponding to the first non-zero element is the same)
  • the performance of dual code using eBCH code is better than that of polar code.
  • dual eBCH indicates a dual code of the eBCH code.
  • Dual of Simplex represents a dual code of a simplex code.
  • B can be set to any positive integer.
  • the code rate allocation before polarization can be obtained recursively through the prior art until each outer code (block code) code is obtained Rate, and select the corresponding block code for outer code encoding.
  • the existing "polarization weight" method can be used to obtain the code rate allocation result of the original polar code on each sub-block, and then use this allocation result as the code rate allocation scheme for each sub-block of the concatenated code.
  • the above code rate allocation scheme may not be followed, and a method of avoiding some specific code rates may be used to reduce decoding complexity.
  • the "full expansion algorithm” and "symptom list” can be used to avoid the intermediate code rate of the concatenated code.
  • the full expansion algorithm is suitable for low-bit-rate sub-blocks
  • the symptom list method is suitable for high-bit-rate sub-blocks. It is a parallel decoding method.
  • the decoding method 300 of the present application will be described below with the symptom list method as an example.
  • the decoding method 300 in the embodiment of the present application may include the following steps 301-306.
  • the length of the bit sequence to be decoded is N, and N is a positive integer.
  • N is the length of the codeword after concatenated encoding is completed.
  • B is the length of each sub-block into which the information bit sequence is divided.
  • N is the length of the bit sequence to be decoded. B has the same meaning as the encoding side.
  • each bit of a bit sequence to be decoded is associated with a log likelihood ratio (LLR). Then, the N bits included in the bit sequence of length N to be decoded are associated with N LLRs one by one.
  • LLR log likelihood ratio
  • an F operation or a G operation is performed on the N LLRs according to a hierarchy, and a recursive operation is performed.
  • step 303 is performed.
  • the F operation and the G operation are well-known concepts of recursive operation on LLR in the SCL decoding algorithm.
  • the subcode blocks of the outer code have the same meaning as the subcode blocks of the outer code described in the above-mentioned concatenated coding method 200, and are not described again.
  • multiple candidate codewords of a subcode block are multiple candidate decoding paths of the subcode block.
  • a path metric can be used to measure the pros and cons of the decoding path.
  • PM path metric
  • the smaller the PM value the better the candidate decoding path.
  • the optimal path of each subcode block is selected as the decoding path of the subcode block according to the size of the PM.
  • steps 301-306 are only a few steps divided for the convenience of explaining the decoding process.
  • the decoding process can be designed with more steps based on steps 301-306.
  • some of the above steps 301-306 may also be combined together, and the decoding method 300 is described as fewer steps. This application is not limited.
  • the concatenated coding method 200 provided in the present application is used to perform outer code encoding and inner code encoding on the information bit sequence, and the outer code uses a block code and the inner code uses a polar code.
  • the decoding process it can be decoded by "block", so that the decoding result of each sub-block can be output at one time.
  • the decoding delay can be reduced.
  • N represents a code length
  • K represents a length of an information sequence.
  • K in FIG. 7 and FIG. 8 each includes a 16-bit cyclic redundancy check (CRC) bit.
  • Hybrid polarization refers to the cascade coding method provided in the present application.
  • outer code coding When outer code coding is performed, multiple subsequences obtained by dividing the information bit sequence are selected from Table 2 according to their information length. .
  • hybrid coding For information bit sequences, the coding methods corresponding to multiple subsequences are different, so it is called hybrid coding.
  • Hybrid polar FSL refers to a decoding method that adopts a "block-by-block” manner instead of a "bit-by-bit” manner for external code subcodes, and has a lower decoding delay.
  • the ordinate BLER in FIGS. 7 and 8 represents a block error ratio
  • the abscissa E S / N 0 represents a signal-to-noise ratio.
  • the performance curves shown in FIG. 7 and FIG. 8 are obtained by simulation under the channel condition of additive white gaussian noise (AWGN).
  • AWGN additive white gaussian noise
  • the concatenated coding method provided in the present application has been described in detail with reference to FIG. 1 to FIG. 8.
  • the process of decoding in units of "blocks" can refer to the prior art.
  • the present application provides a concatenated encoding method, so that the receiving end can perform decoding in units of blocks instead of bits, and a large number of simulation results show that the decoding performance has been improved. For example, the decoding delay is reduced and the bit error rate is reduced.
  • the process of decoding at the receiving end in units of blocks can refer to the prior art, which is not described in detail herein.
  • the communication device, the encoding device, the network device, and the terminal device provided in the present application are described below with reference to FIGS. 9 to 14.
  • FIG. 9 is a schematic block diagram of a communication apparatus 500 provided by the present application. As shown in FIG. 9, the apparatus 500 includes a processing unit 510 and a communication unit 520.
  • a processing unit 510 configured to perform group coding on the information bit sequence to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; and perform n-level polarization coding on the multiple first codewords, Get a second codeword of length B ⁇ 2 n , where n ⁇ 1 and an integer;
  • the communication unit 520 is configured to send a second codeword generated by the processing unit 510.
  • FIG. 10 is a schematic structural diagram of a communication device 600 provided by the present application.
  • the communication device 600 is configured to implement a coding function.
  • the communication device 600 includes:
  • a processing device 601 is configured to obtain an information bit sequence to be encoded, and perform group coding on the information bit sequence to obtain a plurality of first codewords having a code length B, where B ⁇ 0 and an integer; and the plurality of first codewords.
  • the word is subjected to n-level polarization coding to obtain a second codeword of length B ⁇ 2 n , where n ⁇ 1 and an integer;
  • the transceiver 602 is configured to send the second codeword.
  • the transceiver is connected to the antenna 603.
  • the processing device 601 may be a processor, a chip, or an integrated circuit.
  • the present application further provides a processing device 601, which is configured to implement the concatenated coding method in the foregoing method embodiments.
  • a processing device 601 which is configured to implement the concatenated coding method in the foregoing method embodiments.
  • Part or all of the processes of the cascade coding method 200 in the embodiment of the present application may be implemented by hardware, or may also be implemented by software.
  • the processing device 601 may be a processor.
  • FIG. 11 is a schematic diagram of the internal structure of the processing device 601.
  • the processing device 601 includes:
  • An input interface circuit 6011 configured to obtain an input information bit sequence
  • a logic circuit 6012 is configured to group and encode the information bit sequence to obtain multiple first codewords with a code length B, B ⁇ 0 and an integer; and perform n-level polarization coding on the multiple first codewords. To obtain a second codeword of length B ⁇ 2 n, where n ⁇ 1 and an integer;
  • the output interface circuit 6013 is configured to output a second codeword.
  • the above-mentioned logic circuit 6012 may be used to execute the concatenated coding method described in each embodiment of the present application. For the detailed process, refer to the description in the method embodiment above, which will not be repeated here.
  • part or all of the process of the cascade coding method 200 provided in this application may also be implemented by software.
  • the processing device 601 may be a processor.
  • the processor is configured to execute a computer program stored in a memory.
  • the processor executes the cascade coding method in the foregoing method embodiment.
  • the memory may be a physically independent unit.
  • the memory may also be integrated with the processor, which is not limited in this application.
  • the processing device 601 may include only a processor.
  • the processor is connected to the memory through a circuit / wire, and is used to read and execute the computer program stored in the memory.
  • the processing device 601 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive an input information bit sequence to be encoded.
  • the output interface is used to output the second codeword.
  • the present application further provides a communication device 700.
  • the communication device 700 is configured to execute the method 300 described above.
  • FIG. 12 is a schematic block diagram of a communication apparatus 700 provided in the present application.
  • the communication device 700 includes a communication unit 701 and a processing unit 702.
  • a communication unit 701 configured to receive a bit sequence to be decoded from a transmitting end
  • the processing unit 702 is configured to execute the decoding method 300 described above, and decode the bit sequence to be decoded to obtain a decoding result.
  • FIG. 13 is a schematic structural diagram of a communication device 800 provided in the present application.
  • the communication device 800 is configured to implement a decoding function.
  • the decoding device 800 includes:
  • a transceiver 801 configured to receive a bit sequence to be decoded from a transmitting end
  • the processing device 802 is configured to obtain a bit sequence to be decoded, execute the decoding method of the method 300 described above, and decode the bit sequence to be decoded to obtain a decoding result.
  • the transceiver 801 is connected to the antenna 803.
  • the processing device 802 may be a processor, a chip, or an integrated circuit.
  • the present application further provides a processing device 802 for implementing the decoding method 300 described above.
  • Part or all of the decoding method 300 in the embodiment of the present application may be implemented by hardware, or may also be implemented by software.
  • the processing device 802 may be a processor.
  • the processing device 802 may also be as shown in FIG. 14.
  • FIG. 14 is a schematic diagram of the internal structure of the processing device 802.
  • the processing device 601 includes:
  • An input interface circuit 8021 configured to obtain a bit sequence to be decoded
  • a logic circuit 8022 is configured to execute the decoding method 300 described above to decode the bit sequence to be decoded to obtain a decoding result;
  • An output interface circuit 8023 is used to output a decoding result.
  • the processing device 802 may be a processor.
  • the processor is configured to execute a computer program stored in a memory.
  • the processor executes the decoding method 300 described above.
  • the memory may be a physically independent unit.
  • the memory may also be integrated with the processor, which is not limited in this application.
  • the processing device 802 includes only a processor.
  • the processor is connected to the memory through a circuit / wire, and is used to read and execute the computer program stored in the memory.
  • the processing device 802 further includes a memory.
  • the chip may further include an input interface and an output interface.
  • the input interface is used to receive an input bit sequence to be decoded.
  • the output interface is used to output the decoding result.
  • the concatenated coding method 200 provided in this application may be performed by a sending end.
  • the network device 101 when the network device 101 sends a signal, the network device 101 is a transmitting end.
  • the terminal device 102 or 103 sends a signal, the terminal device 102 or 103 is a transmitting end. Therefore, the following application further provides a network device and a terminal device, and the network device and the terminal device have a function of implementing the above-mentioned cascade coding method.
  • FIG. 15 is a schematic structural diagram of a network device 3000 provided in the present application.
  • the network device 3000 may be applied to the wireless communication system shown in FIG. 1 described above, and has a function of executing the concatenated coding method provided by the present application.
  • the network device 3000 may be, for example, a base station.
  • the network device 3000 may include one or more radio frequency units, such as a remote radio unit (RRU) 3100 and one or more baseband units (BBU).
  • the baseband unit can also be referred to as a digital unit (DU) 3200.
  • the RRU 3100 may be referred to as a transceiver unit, and corresponds to the communication unit 520 in FIG. 9.
  • the transceiver unit 3100 may also be referred to as a transceiver, a transceiver circuit, or a transceiver, etc., which may include at least one antenna 3101 and a radio frequency unit 3102.
  • the transceiver unit 3100 may include a receiving unit and a transmitting unit.
  • the receiving unit may correspond to a receiver (or a receiver or a receiving circuit), and the transmitting unit may correspond to a transmitter (or a transmitter or a transmitting circuit).
  • the RRU 3100 part is mainly used for transmitting and receiving radio frequency signals and converting radio frequency signals and baseband signals, for example, for sending configuration information of a first random access resource to a terminal device.
  • the BBU 3200 part is mainly used for baseband processing and controlling base stations.
  • the RRU 3100 and the BBU 3200 may be physically located together, or may be physically separated, that is, a distributed base station.
  • the BBU 3200 is the control center of the network device 3000, and may also be called a processing unit, which may correspond to the processing unit 510 in FIG. 9 and is mainly used to complete baseband processing functions, such as channel coding, rate matching (optionally), Bit interleaving, modulation, etc.
  • the BBU Processed Unit
  • the information bit sequence to be coded is group-coded to obtain a plurality of first codewords having a code length of B; n-level polarization coding is performed on the plurality of first codewords to obtain a length of B ⁇ 2n .
  • the second codeword is the control center of the network device 3000, and may also be called a processing unit, which may correspond to the processing unit 510 in FIG. 9 and is mainly used to complete baseband processing functions, such as channel coding, rate matching (optionally), Bit interleaving, modulation, etc.
  • the BBU Processe.g., Processing Unit
  • the base station may perform the above-mentioned concat
  • the BBU 3200 may be composed of one or more boards, and multiple boards may jointly support a wireless access network (for example, an LTE network) of a single access system, or may separately support different access systems. Wireless access network (for example, LTE network, 5G network or other network).
  • the BBU 3200 further includes a memory 3201 and a processor 3202.
  • the memory 3201 is configured to store necessary instructions and data.
  • the processor 3202 is configured to control the network device 3000 to perform necessary actions.
  • the processor 3202 is configured to control the network device 3000 to execute the operation process performed by the network device in the foregoing method embodiment.
  • the memory 3201 and the processor 3202 may serve one or more single boards. That is, the memory and processor can be set separately on each board. It is also possible that multiple boards share the same memory and processor. In addition, the necessary circuits can be set on each board.
  • the network device 3000 shown in FIG. 15 can implement a method of polarization coding.
  • the operations and / or functions of the units in the network device 3000 are respectively to implement the corresponding processes in the embodiment of the method 200 for cascade coding. To avoid repetition, detailed descriptions are appropriately omitted here.
  • the above BBU 3200 can be used to perform the actions implemented by the network device described in the foregoing method embodiments, for example, performing concatenated coding on the information bit sequence.
  • the RRU 3100 can be used to perform the actions that the network device described in the foregoing method embodiment sends to or receives from the terminal device. For example, sending a second codeword to the terminal device.
  • the terminal device 102 or 103 When uplink transmission is performed in the wireless communication system shown in FIG. 1, the terminal device 102 or 103 is a transmitting end.
  • the terminal equipment provided in this application is described below.
  • FIG. 16 is a schematic structural diagram of a terminal device 900 provided in the present application.
  • the terminal device 900 includes: one or more processors 901, one or more memories 902, and one or more transceivers 903.
  • the processor 901 is configured to control the transceiver 903 to send and receive signals
  • the memory 902 is configured to store a computer program
  • the processor 901 is configured to call and run the computer program from the memory 902 to execute a corresponding method 200 of the cascade coding provided in this application. Process. For brevity, I will not repeat them here.
  • the terminal device 700 may be the terminal device 102 or 103 in the wireless communication system shown in FIG. 1.
  • the processor 901 may correspond to the processing unit 510 in FIG. 9, and the transceiver 903 may correspond to the communication unit 520 shown in FIG. 9.
  • the present application provides a computer-readable storage medium.
  • the computer-readable storage medium stores computer instructions.
  • the computer instructions When the computer instructions are run on a computer, the computer causes the computer to execute the cascade coding method 200 of the embodiment of the application. Corresponding operations and / or processes.
  • the present application also provides a computer program product.
  • the computer program product includes computer program code.
  • the computer program code runs on a computer, the computer causes the computer to perform corresponding operations of the cascade coding method 200 in the embodiment of the present application and / or Process.
  • the present application also provides a chip, including a processor.
  • the processor is configured to read and execute a computer program stored in the memory to perform corresponding operations and / or processes of the cascade-coded method 200 provided in the present application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be encoded.
  • the processor obtains the information bit sequence from the communication interface and uses the cascade encoding method 200 of the embodiment of the present application to perform cascade encoding on the information bit sequence. After the communication interface outputs the encoding Sequence of bits.
  • the communication interface may be an input-output interface.
  • This application provides a computer-readable storage medium.
  • the computer-readable storage medium stores computer instructions.
  • the computer instructions When executed on a computer, the computer is caused to perform corresponding operations of the decoding method 300 in the embodiment of the application and / Or process.
  • the present application also provides a computer program product.
  • the computer program product includes computer program code.
  • the computer program code runs on a computer, the computer causes the computer to perform corresponding operations and / or processes of the decoding method 300 in the embodiment of the present application.
  • the present application also provides a chip, including a processor.
  • the processor is configured to read and execute the computer program stored in the memory to perform corresponding operations and / or processes of the decoding method 300 provided in the application.
  • the chip further includes a memory, and the memory and the processor are connected to the memory through a circuit or a wire.
  • the chip further includes a communication interface, and the processor is connected to the communication interface.
  • the communication interface is used to receive the bit sequence to be decoded.
  • the processor obtains the bit sequence to be decoded from the communication interface, and uses the decoding method 300 in the embodiment of the present application to decode the bit sequence to be decoded.
  • the communication interface is used to output the decoding result.
  • the communication interface may be an input-output interface.
  • each step of the above method may be completed by an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the steps of the foregoing method embodiment may be directly embodied as being performed by a hardware processor, or may be performed by using a combination of hardware and software modules in the processor.
  • the software module may be located in a mature storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, and the like.
  • the storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the foregoing method in combination with its hardware.
  • the chip described in the embodiment of the present application may be a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system chip (SoC), a central Processor (central processor unit, CPU), network processor (Network processor, NP), digital signal processing circuit (digital signal processor, DSP), may also be a microcontroller (micro controller, unit, MCU, programmable controller ( programmable logic device (PLD) or other integrated chip.
  • FPGA field-programmable gate array
  • ASIC application-specific integrated circuit
  • SoC system chip
  • CPU central processor unit, CPU
  • Network processor Network processor
  • NP digital signal processing circuit
  • DSP digital signal processor
  • microcontroller microcontroller
  • MCU programmable controller
  • PLD programmable logic device
  • the processor in the embodiment of the present application may be an integrated circuit chip and has a signal processing capability.
  • each step of the foregoing method embodiment may be completed by using an integrated logic circuit of hardware in a processor or an instruction in a form of software.
  • the processor may be a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.
  • a general-purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the steps of the method disclosed in the embodiments of the present application may be directly implemented by a hardware encoding processor, or may be performed by using a combination of hardware and software modules in the encoding processor.
  • the software module may be located in a mature storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, and the like.
  • the storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the foregoing method in combination with its hardware.
  • the memory in the embodiment of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrical memory Erase programmable read-only memory (EPROM, EEPROM) or flash memory.
  • the volatile memory may be a random access memory (RAM), which is used as an external cache.
  • RAM random access memory
  • DRAM dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • double SDRAM double SDRAM
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • enhanced SDRAM enhanced SDRAM
  • SLDRAM synchronous connection dynamic random access memory
  • direct RAMbus RAM direct RAMbus RAM
  • the device embodiments described above in this application are merely schematic.
  • the division of the units is only a logical function division, and there may be another division manner in actual implementation.
  • multiple units or components may be combined or integrated into another system, or some features may be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each of the units may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium.
  • the technical solution of this application is essentially a part that contributes to the existing technology or a part of the technical solution can be embodied in the form of a software product.
  • the computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.

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Abstract

一种级联编码方法，包括：对信息比特序列进行分组编码，得到码长为B的多个第一码字（210）；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字（220）；输出第二码字（230）。

Description

级联编码的方法和装置
本申请要求于2018年09月07日提交国家知识产权局、申请号为201811045907.4、申请名称为“级联编码的方法和装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及编码领域，尤其涉及一种级联编码的方法和装置。
背景技术
极化码(polar codes)是一种理论上被严格证明可以达到信道容量的结构化的信道编码方法，近年来已经得到了广泛的应用和长足的进展。但是，随着无线通信***的快速演进，未来的通信***(例如，5G)将会出现一些新的特点。例如，作为5G中最典型的三大通信场景之一的高可靠低延迟通信(ultra reliable low latency communication，URLLC)，对于数据传输的可靠性和时延有着非常高的要求。极化码最通行的译码方法是串行抵消列表(successive cancellation list,SCL)译码算法。SCL译码算法在译码时，是一个比特一个比特进行判决并输出的，译码时延比较大，需要进一步优化。
发明内容
本申请提供一种级联编码的方法和装置，能够降低极化码的译码时延。
第一方面，提供了一种级联编码的方法，该方法包括：对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥1且为整数；对该多个第一码字进行n级的极化编码，得到码长为B×2 n的第二码字，n≥1且为整数；发送该第二码字。
本申请的技术方案中，级联编码的外码编码采用分组编码，内码编码采用polar编码。在编码时，外码编码将信息比特序列划分为多个组分别进行编码，得到的多个第一码字作为polar编码的输入。由于每个第一码字包括多个比特，因此内码编码实际上是以包括多个比特的块(即，第一码字)为单位进行polar编码的。从而在译码时，不再需要像现有的SCL译码算法那样，以比特为单位进行判决和译码，而是以块为单位进行译码。从而可以降低译码时延。
结合第一方面，在第一方面的某些实现方式中，对信息比特序列进行分组编码，得到码长为B的多个第一码字，包括：获取第二码字的目标码长N和第一码字的码长B，N＝B×2 n，N为整数；根据第二码字的目标码长N和第一码字的码长B，对信息比特序列进行分组，得到多个子序列；根据该多个子序列中每个子序列包括的比特数目，确定对每个子序列进行编码所需的生成矩阵；使用与该多个子序列中每个子序列对应的生成矩阵，对所该多个子序列进行编码，得到码长为B的多个第一码字。
结合第一方面，在第一方面的某些实现方式中，该方法还包括：根据目标码长N和第 一码字的码长B，如果确定不存在一个正整数R使得R＝2 n，则选择正整数L，对码长为B的多个第一码字进行m级的极化编码，得到码长为B×L的第三码字，L＝2 m，L>R，m>n，m、L和R为正整数；对码长为B×L的第三码字进行速率匹配，得到码长为B×2 n的第二码字。
结合第一方面，在第一方面的某些实现方式中，信息比特序列的每个子序列可以使用如下任意一种码进行编码：重复码、BCH码、单纯形码、BCH码的对偶码、polar码、奇偶检验码、单纯形码的重复码的对偶码。
第二方面，提供了一种编码装置，该编码装置具有实现上述第一方面及其任意可能的实现方式中的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
在一种可能的设计中，当所述功能的部分或全部通过硬件实现时，该编码装置包括：输入接口电路，用于获取待编码的信息比特序列；逻辑电路，用于对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥0且为整数；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字，n≥1且为整数；输出接口电路，用于输出该第二码字。
本申请的技术方案中，级联编码的外码编码采用分组编码，内码编码采用polar编码。在编码时，外码编码将信息比特序列划分为多个组分别进行编码，得到的多个第一码字作为polar编码的输入。由于每个第一码字包括多个比特，因此内码编码实际上是以包括多个比特的块(即，第一码字)为单位进行polar编码的。从而在译码时，不再需要像现有的SCL译码算法那样，以比特为单位进行判决和译码，而是以块为单位进行译码。从而可以降低译码时延。
在具体实现时，该编码装置可以是芯片或者集成电路。
在一种可能的设计中，当所述功能的部分或全部通过软件实现时，该编码装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，该编码装置可以实现如上述第一方面和第一方面的任一种可能的设计中所述的级联编码的方法。
可选的，存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一种可能的设计中，当所述功能的部分或全部通过软件实现时，该编码装置包括仅包括处理器。用于存储程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并运行存储器中存储的程序，以执行上述第一方面和第一方面的任意可能的实现方式中的级联编码的方法。
第三方面，本申请提供一种译码方法，该方法包括：获取待译码的比特序列，待译码的比特序列的长度为N，N为正整数；对待译码的比特序列执行SCL译码，得到N/B个子码块，对所述N/B个子码块中的每个子码块中的比特进行硬判决，得到每个子码块的硬判决结果，并对每个子码块的硬判决结果查询症状诊断表，得到每个子码块的多个候选码字；计算每个子码块的多个候选码字的路径度量值，并根据每个子码块的多个候选码字的路径度量值，确定每个子码块的译码路径；将该多个子码块对应的多个译码路径依序输出，作为译码结果。
第四方面，本申请提供一种译码装置，该译码装置具有实现上述第三方面及其任意可 能的实现方式中的方法的功能。所述功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。所述硬件或软件包括一个或多个与上述功能相对应的单元。
在一种可能的设计中，当所述功能的部分或全部通过硬件实现时，该译码装置包括：输入接口电路，用于获取待译码的比特序列；逻辑电路，用于执行上述第三方面中的译码方法，对所述待译码的比特序列进行译码，得到译码结果；输出接口电路，用于输出译码结果。
可选的，该译码装置可以是芯片或者集成电路。
在一种可能的设计中，当所述功能的部分或全部通过软件实现时，该译码装置包括：存储器，用于存储计算机程序；处理器，用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，该译码装置可以实现如上述第三方面所述的译码方法。
可选的，存储器可以是物理上独立的单元，也可以与处理器集成在一起。
在一种可能的设计中，当所述功能的部分或全部通过软件实现时，该译码装置包括仅包括处理器。用于存储程序的存储器位于编码装置之外，处理器通过电路/电线与存储器连接，用于读取并运行存储器中存储的程序，以执行上述第三方面中所述的译码方法。
在具体实现时，该译码装置可以为芯片或集成电路。
第五方面，本申请提供一种网络设备，包括收发器、处理器和存储器。处理器用于控制收发器收发信号，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，使得网络设备执行第一方面或第二方面任意可能的实现方式中的方法。
具体地，在网络设备作为信息和/或数据的发送端时，网络设备执行上述第一方面及其任意可能的实现方式中的级联编的方法，对需要发送的信息和/或数据进行级联编码。在网络设备作为信息和/或数据的接收端时，网络设备执行上述第三方面的译码方法，对从发送端接收到的待译码的比特序列进行译码。
第六方面，本申请提供一种终端设备，包括收发器、处理器和存储器。处理器用于控制收发器收发信号，存储器用于存储计算机程序，处理器用于调用并运行存储器中存储的计算机程序，使得终端设备执行第一方面或第二方面任意可能的实现方式中的方法。
具体地，在终端设备作为信息和/或数据的发送端时，终端设备执行上述第一方面及其任意可能的实现方式中的级联编的方法，对需要发送的信息和/或数据进行级联编码。在终端设备作为信息和/或数据的接收端时，终端设备执行上述第三方面的译码方法，对从发送端接收到的待译码的比特序列进行译码。
第七方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行第一方面或第一方面的任意可能的实现方式中的方法。
第八方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行上述第一方面及其任意一种可能的实现方式中的方法。
第九方面，本申请提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行上述第一方面或第一方面任意可能的实现方式中的方法。可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收待编码的比特序列， 处理器从通信接口获取该信息比特序列，并采用第一方面描述的级联编码的方法，对该信息比特序列进行级联编码；通信接口输出编码后的比特序列。该通信接口可以是输入输出接口。
第十方面，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有指令，当其在计算机上运行时，使得计算机执行第三方面或第三方面的任意可能的实现方式中的方法。
第十一方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行上述第三方面或第三方面任意可能的实现方式中的方法。
第十二方面，本申请提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行上述第三方面或第三方面任意可能的实现方式中的方法。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收待译码的比特序列，处理器从通信接口获取该待译码的比特序列，并采用第三方面描述的译码方法，对该待译码的比特序列进行译码，得到译码结果；通信接口输出译码结果。该通信接口可以是输入输出接口。
第十三方面，本申请提供一种通信***，包括第五方面所述的网络设备和第六方面所述的终端设备。
本申请的技术方案中，级联编码的外码编码采用分组编码，内码编码采用polar编码。在编码时，外码编码将信息比特序列划分为多个组分别进行编码，得到的多个第一码字作为polar编码的输入。由于每个第一码字包括多个比特，因此内码编码实际上是以包括多个比特的块(即，第一码字)为单位进行polar编码的。从而在译码时，不再需要像现有的SCL译码算法那样，以比特为单位进行判决和译码，而是以块为单位进行译码。从而可以降低译码时延。
附图说明
图1是适用于本申请实施例的无线通信***100的架构图。
图2是采用无线技术进行通信的基本流程图。
图3是polar极化码编码示意图。
图4是F2极化网络的输入输出示意图。
图5是本申请提供的级联编码的方200的示意性流程图。
图6是B＝3的分组码的极化过程的示意图。
图7是N＝256，K＝124的级联码与polar码的性能对比图。
图8是N＝1024，K＝512的级联码与polar码的性能对比图。
图9是本申请提供的通信装置500的示意性框图。
图10为本申请提供的通信装置600的示意性结构图。
图11为处理装置601的内部结构示意图。
图12是本申请提供的通信装置700的示意性框图。
图13是本申请提供的通信装置800的示意性框图。
图14为处理装置802的内部结构示意图。
图15是本申请提供的网络设备3000的示意性结构图。
图16是本申请提供的终端设备900的示意性结构图。
具体实施方式
下面将结合附图，对本申请中的技术方案进行描述。
参见图1，图1是适用于本申请实施例的无线通信***100的架构图。如图1所示。无线通信***100中可以包括至少一个网络设备、一个或多个终端设备。网络设备(如图1中所示的101)可以与该一个或多个终端设备(如图1中所示的102和103)进行无线通信。
本申请中涉及的无线通信***，包括但不限于全球移动通讯(global system of mobile communication，GSM)***、码分多址(code division multiple access，CDMA)***、宽带码分多址(wideband code division multiple access，WCDMA)***、通用分组无线业务(general packet radio service，GPRS)、长期演进(long term evolution，LTE)***、LTE的频分双工(frequency division duplex，FDD)***、LTE的时分双工(time division duplex，TDD)、通用移动通信***(universal mobile telecommunication system，UMTS)、全球互联微波接入(worldwide interoperability for microwave access，WiMAX)通信***、下一代5G移动通信***的三大应用场景，即增强移动带宽(enhance mobile broadband，eMBB)，高可靠性低延迟通信(ultra reliable low latency communication，URLLC)和增强海量机器连接通信(massive machine type communication，eMTC)或者将来出现的新的通信***等。
本申请实施例涉及的终端设备可以指用户设备(user equipment，UE)、终端(terminal)、接入终端、用户单元、用户站、移动站、移动台、远方站、远程终端、移动设备、用户终端、终端、无线通信设备、用户代理或用户装置。终端设备还可以是蜂窝电话、无绳电话、会话启动协议(session initiation protocol，SIP)电话、无线本地环路(wireless local loop，WLL)站、个人数字处理(personal digital assistant，PDA)、具有无线通信功能的手持设备、计算设备或连接到无线调制解调器的其它处理设备、车载设备、可穿戴设备，未来5G网络中的终端设备或者未来演进的公用陆地移动通信网络(public land mobile network，PLMN)中的终端设备等，本申请对此不作限定。
本申请涉及的网络设备可以是用于与终端设备通信的设备。该网络设备可以是基站，也可以是基站与基站控制器集成后的设备，还可以是具有类似通信功能的其它设备。这里所说的基站可以是全球移动通讯(global system of mobile communication，GSM)***或码分多址(code division multiple access，CDMA)中的基站(base transceiver station，BTS)，也可以是宽带码分多址(wideband code division multiple access，WCDMA)***中的基站(nodeB，NB)，还可以是长期演进(long term evolution,LTE)***中的演进型基站(evolutional nodeB，eNB或eNodeB)，还可以是云无线接入网络(cloud radio access network，CRAN)场景下的无线控制器。或者，该网络设备还可以是中继站、接入点、车载设备、可穿戴设备以及未来5G网络中的网络设备等，本申请实施例不作限定。
图1中的网络设备与终端设备之间采用无线技术进行通信。当网络设备发送信号时，其为发送端，当网络设备接收信号时，其为接收端。终端设备也是一样的，当终端设备发 送信号时，其为发送端，当终端设备接收信号时，其为接收端。
图2是采用无线技术进行通信的基本流程图。发送端的信源依次经过信源编码、信道编码、速率匹配和调制后在信道上发出。接收端收到信号后依次经过解调、解速率匹配、信道解码和信源解码后获得信宿。
信道编解码是无线通信领域的核心技术之一，其性能的改进将直接提升网络覆盖及用户传输速率。目前，极化码(polar codes)是可理论证明达到香农极限，并且具有可实用的线性复杂度编译码能力的信道编码技术。Polar码是一种线性块码，其编码矩阵(也称为生成矩阵)为F N，编码过程可以由下式表示：
Figure PCTCN2019104786-appb-000001
其中，
Figure PCTCN2019104786-appb-000002
是一个二进制的行矢量(也即，信息比特序列)，长度为N，且N＝2 n，n为正整数。F N是一个N×N的矩阵，
Figure PCTCN2019104786-appb-000003
定义为log2 N个矩阵F 2的克罗内克(Kronecker)乘积，
Figure PCTCN2019104786-appb-000004
以上各式中涉及的加法、乘法操作均为二进制伽罗华域上的加法、乘法操作。
通过该方法生成的编码，通过逐比特消除(successive cancellation,SC)译码方法，会产生极化现象。即，u中的一部分比特经过一个等效的高可靠信道并以高概率会被译对，剩下的比特经过一个等效的低可靠度信道并以低概率被译对。由此，人们可以将高可靠信道用于信息传输，而将低可靠度信道对应的比特置零(也即，冻结)，不用于传输数据，或者传输通信双方已知的数据。
参见图3，图3是polar极化码编码示意图。如图3所示，符号“⊕”代表二进制相加，其输入为左侧和下侧，输出为右侧。图3中每条实线代表1比特。我们将{u 1,u 2,u 3,u 5}设置为冻结比特，将{u 4,u 6,u 7,u 8}共4位信息比特进行polar编码，得到8位编码比特。编码之后，再将该8位编码比特进行调制后经过噪声信道发送。
从polar码的编码过程可以看到，从信息比特开始，就以
Figure PCTCN2019104786-appb-000005
网络进行极化。其中，F2极化网络的输入、输出关系可以参见图4所示。
参见图4，图4是F2极化网络的输入输出示意图。将图4中所示的输入、输出关系用公式描述，可以表示为：
[x 0x 1]＝[μ 0μ 1]×F 2                                         (2)
其中，[x 0x 1]和[u 0,u 1]都是二进制向量，所有的运算也都是在二元域进行。
根据上述polar编码原理，polar码的译码采用SCL译码算法。采用SCL译码算法进行译码时，译码器是逐比特进行判决和输出的，译码时延较大。
为此，本申请提供一种级联编码的方法，可以降低译码时延，提升极化码的译码性能。
为了便于理解，首先对级联编码进行简单介绍。
在将信道编码技术应用于实际中时，常常需要考虑很多实际的因素，例如，效率、性能和时延等。由信道编码理论可知，随着码长N的增加，译码错误概率以指数方式趋近于零。因此，为提高纠错码的有效性，就必须使用长码。但码长增加，码率会相应下降，译码器的复杂性与计算量也相应增加。级联码正是为了解决这个矛盾而提出，它将编码过程 分为几级完成，可以满足信道纠错对编码长度的要求，获得和长码接近甚至相同的纠错能力和高编码增益。而且，随之增加的编译码复杂度并不是很大。换句话说，如果一个***包括多次(至少两次)编码，这多次编码就认为是级联编码。级联编码包括外码编码和内码编码。其中，外码编码的输入是待编码的信息比特序列，外码的输出作为内码的输入。内码编码的输出即是完成级联编码后的码字。应理解，外码和内码是一个相对的概念。以一个***包括三次编码为例，第一次编码相对于第二次编码是外码编码，第二次编码相对于第一次编码是内码编码。第一次编码完成之后，第二次编码相对于第三次编码是外码编码，第三次编码相对于第二次编码是内码编码。再以一个***包括两次编码为例，先进行的是外码编码，后进行的是内码编码。外码编码的输出作为内码编码的输入。
在本申请提供的技术方案中，级联编码涉及两次编码。其中，级联编码的外码采用分组编码，内码编码采用polar编码。
参见图5，图5是本申请提供的级联编码的方200的示意性流程图。方法200可以由发送端执行。
210、对信息比特序列进行分组编码，得到码长为B的多个第一码字。
其中，B≥1且为整数。
在步骤210中，编码器获取待编码的信息比特序列，并对信息比特序列进行分组编码，得到多个第一码字。
这里，第一码字的长度B是预设的。应理解，步骤210是一个分组编码的过程。分组编码是将待编码的信息比特序列划分为多个组，并对每个组进行编码，得到码长均为B的多个第一码字。关于如何对信息比特序列进行分组可以参考现有技术，本申请中不作详述。
分组码的码长B与译码的复杂度和时延有关。分组码的码长B可以考虑复杂度和时延的折中而设定。
220、对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字。
其中，n≥1且为整数。
在步骤220中，发送端对步骤210中进行分组编码得到的多个第一码字，进行n级的极化编码，得到长度为B×2 n的第二码字。
如果第一码字的长度为B，且在步骤220中，发送端对第一码字进行了n级的极化编码(也可以说，经过n次极化)，则得到的级联码的长度为B×2 n。
由于B≥1且为整数，2 n为2的整数次幂，因此，级联码的长度B×2 n将可以为任意大小。也就是说，根据本申请提供的级联编码的方法，可以生成任意码长的级联码。
本申请的技术方案中，级联编码的外码编码采用分组编码，内码编码采用polar编码。具体地，外码编码将信息比特序列划分为多个组分别进行编码，得到的多个第一码字作为polar编码的输入。由于每个第一码字包括多个比特，因此内码编码实际上是以包括多个比特的块(即，第一码字)为单位进行polar编码的。从而在译码时，不再需要像现有的SCL译码算法那样，以比特为单位进行判决和译码，而是以块为单位进行译码。从而可以降低译码时延。
上述步骤210中，对信息比特序列进行分组编码，得到码长为B的多个第一码字，包括：
获取第二码字的目标码长N和第一码字的码长B，N＝B×2 n，N为整数；
根据第二码字的目标码长N和第一码字的码长B，对信息比特序列进行分组，得到多个子序列；
根据该多个子序列中每个子序列包括的比特数目，确定对每个子序列进行分组编码所需的生成矩阵；
使用与该多个子序列中每个子序列对应的生成矩阵，对该多个子序列进行分组编码，得到码长为B的多个第一码字。
应理解，在进行编码时，通常需要设定一个期望的编码后的码长N(也即，目标码长)。而在本申请中，目标码长N即是编码器最终输出的级联码(即，第二码字)的码长。因此，即，N＝B×2 n。
上文已经介绍过，分组编码时，分组码的码长也预先设定的。而分组码指的是分组编码的输出，也即本申请中的第一码字。即是说，在进行级联编码之前，首先获取预设的目标码长N和分组码的码长B。根据目标码长和分组码的码长B，确定将待编码的信息比特序列具体划分为几个组。这里，分组编码中涉及的对信息比特序列进行分组的过程可以参考现有技术，这里不作详述。
将信息比特序列进行分组之后，得到多个子序列，每个子序列中包括一个或多个比特，或者，有些子序列中也可以不包括比特。接下来，根据该多个子序列中每个子序列对应的生成矩阵，确定对每个子序列进行分组编码所需的生成矩阵。
这里，将信息比特序列进行分组之后，得到的多个子序列，也可以认为是信息比特序列的多个子块。也即，每个子序列是信息比特序列的一个子块，或者称作子码块。
应理解，将信息比特序列划分为多个子序列之后，每个子序列将会编码成为长度为B的第一码字。而这多个子序列中包括的比特的数目不尽相同，因此，需要根据每个子序列中包括的比特数目，确定对该子序列进行编码所需的生成矩阵。即是说，该多个子序列中的每一个子序列都对应各自的生成矩阵。使用该多个生成矩阵对该多个子序列进行编码，得到多个第一码字，每个码字的码长均为B。
根据上文的描述可以知道N和B之间满足N＝B×2 n，其中，n是步骤220中所说的极化次数。而N和B通常又是根据编码需要设定的，那么可能存在一种情况，即目标码长N和第一码字的码长B设定之后，却不存在一个正整数R，使得R＝2 n。例如，目标码长N＝20，第一码字的长度B＝3。此时，可以先选择一个正整数L，使得L＝2 m，m>n，并对码长为B的多个第一码字进行m级的极化编码，得到码长为B×2 m的第三码字。接下来，对第三码字进行速率匹配，最终得到码长为B×2 n的第二码字。例如，N＝20，B＝3时，选择2 m＝8(即，m＝3)。也就是说，经过步骤210，先将信息比特序列进行分组编码，得到码长为3的多个第一码字，接下来，在步骤220，对该码长为3的多个码字进行3级polar编码，得到长度为3×2 3的码字(记作，第三码字)。最后，对码长为24的第三码字进行速率匹配(例如，通过打孔的方式，打掉4个比特)，最终得到长度为20的第二码字。
根据本申请的技术方案，在目标码长N和分组码(即，第一码字)的码长B设定的情况下，如果存在正整数R＝2 n满足N＝B×R，则级联编码之后可以直接得到目标码长的码字。与polar编码只能生成2的整数次幂的码长相比，不需要进行速率匹配。
进一步地，如果在目标码长N和分组码(即，第一码字)的码长B设定的情况下，不存在正整数R＝2 n满足N＝B×R，则先根据本申请的级联编码的方法生成一个与目标码 长接近的码字，再对该码字进行少量速率匹配，也可以得到目标码长的码字。
可选地，在选择L时，通常是选择满足L＝2 m，同时使得B×L>N且与N最接近。这样，可以减少后续需要进行速率匹配的比特数目。例如，N＝20，B＝3，选择L＝2 m＝8，既满足L为2的次幂，又满足B×L与20最接近。
当然，也可以选择L只满足L＝2 m，但是B×L不一定是最接近N的。本申请不作限定。
230、发送第二码字。
经过步骤210和步骤220，编码器完成级联编码。完成级联编码后，发送将该第二码字发送给接收端。
应理解，在发送第二码字之前，可能还需要经过上文所说的少量的速率匹配，调制。资源映射等。这些过程都可以参考现有技术，这里不作赘述。
在方法200中，步骤210和步骤230可以由发送端的编码器执行。步骤230可以由发送端的收发器执行。具体地，编码器在完成步骤210和步骤220之后，可以将第二码字输出给收发器，以由收发器将第二码字发送。或者，编码器还可以对第二码字经过速率匹配、调制映射等处理后发送给收发器，再将经过速率匹配和调制映射处理后的第二码字发送给收发器，由收发器将其发送给接收端。
可选地，作为一种实现方式，执行方法200的步骤210和步骤220的编码器可以包括外码编码器和内码编码器。
具体地，外码编码器获取信息比特序列，并对信息比特序列进行分组编码，得到码长为B的多个第一码字，完成级联编码的外码编码。外码编码完成之后，外码编码器将该多个第一码字输入给内码编码器。内码编码器从外码编码器接收该多个第一码字，对该多个第一码字进行n级的polar编码，得到第二码字，完成内码编码。内码编码完成之后，内码编码器将第二码字输出。
可选地，外码编码器输出第一比特序列之后，在输入内码编码器之前，还可以对第一比特序列进行比特交织，再将交织后的比特序列输入到内码编码器进行内码编码。
进一步地，为了获得较好的译码性能，在步骤210中进行外码编码时，可以考虑如下因素，选择作为外码的分组码。
(1)选择可以支持并行译码的分组码。
(2)规避一些中间码率。
(3)考虑更大的最小码距和更好的码距谱。
(4)对于各种外码码率，可以选择最优的分组码。
考虑这些因素来选择一些较好的码距谱特性、较高的译码并行度的分组码作为外码。最后，多个分组码拼接后，由F N极化网络进行极化。这样可以提高译码并行度，降低时延。同时，由于外码分组码的码长无需为2的整数次幂，因此，最终级联码的码长也具有更多的选择，可以省去速率匹配的流程，或者仅需要少量的速率匹配。
下面给出B＝3和B＝16的两个示例，来说明上述级联编码的过程。
1、第一码字的长度B＝3。
参见图6，图6是B＝3的分组码的极化过程的示意图。如图6所示，假定信息比特序列为[u 0 u 1 u 2 u 3 u 4 u 5]，并假定信息比特序列划分为如下4个子序列：
Figure PCTCN2019104786-appb-000006
[u 0],[u 1 u 2],[u 3 u 4 u 5]。其中，
Figure PCTCN2019104786-appb-000007
表示该子序列中不包含比特。每个子序列中包含的比特数目，也可以称作 该子序列的信息长度。根据每个子序列的信息长度，其对应的生成矩阵分别可以表示为：
信息长度为0时，生成矩阵可以表示为
Figure PCTCN2019104786-appb-000008
信息长度为1时，生成矩阵可以表示为G 1＝[1 1 1]；
信息长度为2时，生成矩阵可以表示为
Figure PCTCN2019104786-appb-000009
信息长度为3时，生成矩阵可以表示为
Figure PCTCN2019104786-appb-000010
这里，信息长度为0，可以理解为无信息输入。
(1)外码编码。
在本申请中，外码编码采用分组编码。
针对上述信息长度分别为0，1，2和3，外码编码的过程可以表示为：
[o 0 o 1 o 2]＝[0 0 0]
[o 3 o 4 o 5]＝[u 0]×[1 1 1]
Figure PCTCN2019104786-appb-000011
Figure PCTCN2019104786-appb-000012
对信息比特序列[u 0 u 1 u 2 u 3 u 4 u 5]经过外码编码，最终输出4个码字，分别为[o 0 o 1 o 2]、[o 3 o 4 o 5]、[o 6 o 7 o 8]和[o 6 o 7 o 8]，每一个码字的码长为3。这里的每一个码字，即是本申请中所说的第一码字。
(2)内码编码。
在本申请中，内码编码为极化编码。
继续参见图5，外码码字的极化过程可以表示为：
[x 0 x 3 x 6 x 9]＝[o 0 o 3 o 6 o 9]×F 4
[x 1 x 4 x 7 x 10]＝[o 1 o 4 o 7 o 10]×F 4
[x 2 x 5 x 8 x 11]＝[o 2 o 5 o 8 o 11]×F 4
实际上也可以认为，是将上述4个第一码字进行拼接，得到o＝[o 0,o 1,...,o 11]，对拼接后的码字进行polar编码。采用polar码进行内码编码之后，最终输出的级联码为x＝[x 0,x 1,...,x 11]。也即，本申请中所说的第二码字。
根据本申请提供级联编码的方法，假设进行外码编码时，分组码的总的信息长度为K，分组码的第i个子码块的信息长度为K i，则满足：
Figure PCTCN2019104786-appb-000013
如果将上述级联编码的过程可以写成通式，可以表示为：
外码编码时，对于i∈{1,2,...,N}，执行
Figure PCTCN2019104786-appb-000014
在公式(4)中，
Figure PCTCN2019104786-appb-000015
为分组码的第i个子码块在编码前的K i个信息比特，
Figure PCTCN2019104786-appb-000016
为第i个子码块编码后的B个码字比特。
Figure PCTCN2019104786-appb-000017
为第i个子码块的生成矩阵，大小为K i×B。
内码编码时，对于j∈{1,2,...,B}
Figure PCTCN2019104786-appb-000018
在公式(5)中，
Figure PCTCN2019104786-appb-000019
为各个子码块的第j个码字比特组成的N个待极化编码的比特，
Figure PCTCN2019104786-appb-000020
为极化编码后比特。
以上对本申请提供的外码采用分组码，内码采用极化码的级联编码的过程作了详细说明。下面结合表1再给出一个混合分组码的示例，
2、第一码字的码长B＝16。
为了描述上的简洁，首先将信息比特序列进行分组之后，子序列的信息长度记作K，K为整数。应理解，K≤B。
表1
Figure PCTCN2019104786-appb-000021
Figure PCTCN2019104786-appb-000022
应理解，表1的第一列表示子序列的信息长度。表1的第二列表示级联编码时选择何种码作为外码。其中，表1的第二列与第一列的子序列的信息长度是对应的。例如，如果对信息比特序列进行分组后，得到的某个子序列的信息长度为1，则选择重复码作为外码执行上述步骤210的外码编码。又例如，如果某个子序列的信息长度为6，则选择eBCH码作为外码执行上述步骤210的外码编码。其它信息长度类似，不再一一说明。表1中的第三列表示进行外码编码时采用的生成矩阵。其中，表1的第三列分别于第二列和第一列也是一一对应的。例如，子序列的信息长度为1时，采用重复码进行外码编码，外码编码时使用的生成矩阵为G 1。又例如，子序列的信息长度为3时，采用单纯形码simplex码的重复码进行外码编码，外码编码使用的生成矩阵为G 3。
需要说明的是，表1中第3列中的G为生成矩阵，矩阵S是为了简化表示生成矩阵G而列出的。矩阵H为一些编码对应的校验矩阵，根据校验矩阵H可以确定生成矩阵。根据对偶码的定义，如果码A是码B的对偶码，则码B的生成矩阵与码A的生成矩阵相同。例如，子序列的信息长度为9时，采用eBCH码的对偶码对该子序列进行外码编码，因此，eBCH码的对偶码的校验矩阵H 9等于eBCH的生成矩阵。
表1中涉及如下几种分组码：
(1)重复码。
重复码是将每个要发送的比特重复发送，或者说，是将每一个信源比特编码成为多个相同的比特。例如，(3,1)这个二元重复码，是将一个二进制比特序列中的每个0编码成000，将每个1编码成111。因此，在信息序列长度为1时，重复码的生成矩阵是一个16位的全1矩阵。
(2)simplex码。
对于子序列的信息长度较短的码来说，单纯型码具有较大的码距。可通过对其进行重复获得所需的码长。
(3)eBCH码。
BCH码取自Bose、Ray-Chaudhuri与Hocquenghem的缩写，是编码理论尤其是纠错码中研究得比较多的一种编码方法。扩展的BCH码(extended BCH,eBCH)是在BCH码的基础上扩展得到的，在已知码中具有构造简便，码距较大的特点。
(4)对偶码。
以线性分组码的一致校验矩阵作为生成矩阵产生的线性分组码，称为原线性分组码的 对偶编码。由此可以理解，在信息序列的长度为9或10时，以eBCH码的一致校验矩阵作为生成矩阵产生的线性分组码即为eBCH的对偶码。
(5)奇偶校验码。
奇偶校验码是一种通过在码字中增加冗余比特，使得码字中“1”的个数恒为奇数或者恒为偶数的编码方法。广义的奇偶校验码可以由循环移位寄存器构造，其校验比特为寄存器中抽头位置对应的二进制值的异或值。移位寄存器分为前馈移位寄存器和反馈移位寄存器两种，若为前馈移位寄存器，则所述奇偶校验码为卷积校验码，若为反馈移位寄存器，则所述奇偶校验码为循环冗余校验码。
其中，单比特奇偶校验码是指只有1个奇偶校验位的码。
在B＝16的情况下，对信息比特序列进行分组之后得到多个子序，根据每个子序列的信息长度，从表2中选择对应的外码和生成矩阵对该子序列进行外码编码，得到多个第一码字。最后，再对所有子序列经过外码编码得到的多个第一码字进行内码编码，得到级联码。
需要说明的是，polar码本身可以看作polar外码和polar内码的级联编码。如果使用表2中所示的B＝16的分组码替换polar外码，可以获得更好的译码性能和译码时延。
应理解，这里所说的适用分组码替换polar编码的外码，是指polar码的外码编码使用本申请中所述的分组编码。对分组编码之后输出的第一码字，继续进行polar内码的编码。
如果使用分组码作为polar码的外码，与polar码的外码和内码编码均采用polar码相比，码距谱的对比可以参见表2
表2
Figure PCTCN2019104786-appb-000023
Figure PCTCN2019104786-appb-000024
在B＝16的情况下，K的取值为0-16。其中，K＝0时，可以认为无信息比特输入，表2中未列出。K＝1时，采用重复码，具体是将子块中的信息比特重复16次得到，表2中也未列出，可以参考表1。K＝16时，可以认为输入的需要进行外码编码的子块包括16个比特，完成外码编码后输出的码字也包含16个比特，因此无需编码，表2中也未列出，可以参考表1。对于K的其它取值可以参考表2。
如表2所示，表2的第一行表示码重，即为码字中1的个数，其对应的列中的数字表示具有该码重的码字的数量；对一个码来说，其所***字的码重分布(如表2中的一行，非第一行)即为该码的码距谱。表2的第一列表示polar码的外码采用的编码方法。表2的第二列表示一个子块(也即上文所说的子序列)的信息长度K。例如，信息比特序列为[u 0 u 1 u 2 u 3 u 4 u 5]，分为[u 0]、[u 1 u 2]和[u 3 u 4 u 5]三个子块。第一个子块[u 0]的信息长度等于1，则选择K＝1对应的重复码进行外码编码，外码编码使用的生成矩阵为G 1(可以参见表1)。第二个子块[u 1 u 2]的信息长度等于2，则从表2中选择K＝2对应的simplex编码进行外码编码，外码编码使用的生成矩阵为G 2。第三个子块[u 3 u 4 u 5]的信息长度等于3，则从表2中选择K＝3对应的simplex编码进行外码编码，外码编码使用的生成矩阵为G 3。由于B设定为16，因此这三个子块经过第一级的外码编码之后，对应输出三个码长为16的第一码字。后续，对该码长为16的第一码字拼接后进行n级的polar编码，输出第二码字，也即级联码字，码长为B×2 n＝16×2 n。
给定K的取值，从表2中可以找到相应的两行，其中一行是外码和内码均采用polar码时对应的码距谱，另一行是外码采用分组码且内码采用polar码时对应的码距谱。在这两行中，第一个非零元素的数值表示该非零元素所在列的码重的个数。其中，非零元素在所在行出现的位置越靠后，对应的码重越大，表示性能越好。同时，对于同一个码重，其对应的非零元素越小，表明该码重的数量越少，发生误码的可能性越小，表示性能越好。下面举例说明。
例如，K＝2时，polar编码对应的行，出现的第一个非零元素为2，对应码重为8，表明有2个码重为8的行。Simplex编码对应的行，出现的第一个非零元素为1，对应的码重为10，表明有1个码重为10的行。根据上述判断译码性能好坏的原则，第一个非零元素对应的码重越大，性能越好。进一步地，第一个非零元素的取值越小越好。由此可以看出，K＝2时，采用simplex编码，性能优于采用polar编码。
又例如，K＝3时，polar编码对应的行，出现的第一个非零元素为6，对应码重为8，表明有6个码重为8的行。Simplex编码对应的行，出现的第一个非零元素为1，对应的码重也为8，表明有1个码重为8的行。在这个示例中，两行出现第一个非零元素的位置相同，再看非零元素的大小。显然，有6个码重为8的行，相比于只有一个码重为8的行，发生误码的概率要高一些。因此，K＝3时，采用simplex编码，性能也优于采用polar编码。
再例如，K＝6时，polar编码对应的行，出现的第一个非零元素为4，对应码重为4。eBCH编码对应的行，出现的第一个非零元素为16，对应的码重为6。首先考虑第一个非零元素对应的码重较小者，性能更优。因此，采用eBCH编码，性能优于采用polar编码。
再例如，K＝10时，polar编码对应的行，出现的第一个非零元素为76，对应码重为4。采用eBCH码的对偶码(Dual of eBCH)编码对应的行，出现的第一个非零元素为60，对应的码重为4。在第一个非零元素出现的位置相同(也即，第一个非零元素对应的码重相同)时，考虑第一个非零元素的数值越小，性能更优。因此，采用eBCH码的对偶码进行编码，性能优于采用polar编码。
以上对表1中性能比较进行了举例说明，K取其它数值时，性能比较的原则是相同的，这里不再赘述。
此外，在K＝5，8，11的情况下，由于级联编码的外码采用polar码时，与采用分组编码相比，其性能已经较优，因此可以不用替换为其它编码。因此，K＝5，8，11时，表1中仅列出了polar编码对应的行。
另外，表1中，Dual of eBCH表示eBCH码的对偶码。Dual of Simplex表示单纯形码的对偶码。
从表1中可以看出，除了K＝5，8，11的情况，用表2中所示的分组码替换polar外码，相对于没有替换的polar码，各个信息长度对应的子块的码距谱都有明显的提升。
以上B＝3和B＝16是本申请提供的级联编码的方法的两个示例。理论上，B可以设定为任意的正整数。上文已经介绍过，B的设定与译码复杂度和译码时延的要求有关，通常是两者的折中。因此，为了与通信***中的硬件条件相适应，根据本申请提供的级联编码的思路，本领域技术人员也可能设计出B设定为其它取值时的一些具体实现，例如，B＝8，32，64等，但是设计思路都与本申请中B＝3和B＝16时的设计思路是相同的，这里不再进行列举。
根据本申请提供的级联编码的方法，给定一个级联码长和目标码率，可以通过现有技术递归地获得极化前的码率分配，直至获得每个外码(分组码)码率，并选取相应的分组码来进行外码编码。
例如，可以使用现有的“极化权重”的方法，获得原polar码在各个子块上的码率分配结果，再使用该分配结果作为级联码各个子块的码率分配方案。
又或者，在使用本申请的级联编码的方法时，也可以不遵循上述码率分配方案，可以通过规避某些特定码率的方法，降低译码复杂度。例如，可以使用“完全展开算法”和“症状列表”，使级联码的码率避免中间码率。其中，完全展开算法适用于低码率的子块，症状列表法适用于高码率的子块，是一种并行译码方法。
下面以症状列表法作为示例，对本申请的译码方法300进行说明。本申请实施例的译码方法300可以包括如下步骤301-306。
301、获取待译码的比特序列，待译码的比特序列的长度为N，N为正整数。
302、对待译码的比特序列执行SCL译码，得到N/B个子码块。
应理解，在编码侧，N是完成级联编码后的码字的长度。B是信息比特序列划分成的每个子块的长度。在译码侧，N是待译码的比特序列的长度。B与编码侧的含义相同。
具体地，本领域技术人员公知，根据SCL译码方法，待译码的比特序列的每个比特关联一个对数似然比(likelihood rate,LLR)。那么，长度为N的待译码的比特序列包括的N个比特一一关联N个LLR。在根据SCL译码算法译码时，对该N个LLR按照层级执行F运算或G运算，进行递归运算。当执行到外码的子码块所在的层级时，执行步骤 303。
这里，F运算和G运算是SCL译码算法中对LLR进行递归运算的公知概念。外码的子码块与上述级联编码的方法200中描述的外码的子码块的含义相同，均不再赘述。
303、对所述N/B个子码块中的每个子码块中的比特进行硬判决，得到每个子码块的硬判决结果。
304、对每个子码块的硬判决结果查询症状诊断表，得到每个子码块的多个候选码字。
这里，一个子码块的多个候选码字即就是该子码块的多个候选译码路径。
关于症状诊断表请参考现有技术的说明。
305、计算每个子码块的多个候选码字的路径度量值，并根据每个子码块的多个候选码字的路径度量值，确定每个子码块的译码路径。
这里，路径度量值(path metric,PM)可用于衡量译码路径的优劣。一般地，一个PM值越小，表明该候选译码路径越好。计算得到每个子码块的每个候选码字的PM之后，根据PM的大小，选出每个子码块的最优路径，作为该子码块的译码路径。
306、将该多个子码块对应的多个译码路径依序输出，作为译码结果。
以上是对译码过程的说明。
应理解，上述步骤301-306仅是为了便于说明译码过程而划分的几个步骤。实际实现时，译码过程可以在步骤301-306的基础上，设计更多的步骤。或者，也可以将上述步骤301-306中的一些步骤合并在一起，将译码方法300描述为更少的步骤。本申请不作限定。
从这个译码过程可以看出，采用本申请提供的级联编码的方法200对信息比特序列进行外码编码和内码编码，且外码采用分组码，内码采用polar码，可以使得接收端在译码过程中可以按“块”译码，从而可以一次输出每个子块的译码结果。相比于现有的SCL译码方法中按“比特”译码，可以降低译码时延。
进一步地，与现有的polar编码方法相比，采用本申请提供的级联编码的方法200，除了可以降低译码时延，大量的实验结果表明，其译码性能也有较大的提升。
下面给出两个本申请的联编码方法200和现有的polar编码的性能对比图。图7-图8中，N表示码长，K表示信息序列的长度。其中，图7和图8中的K均包含了16位的循环冗余校验(cyclic redundancy check，CRC)比特。
参见图7，图7是N＝256，K＝124的级联码与polar码的性能对比图。
参见图8，图8是N＝1024，K＝512的级联码与polar码的性能对比图。
其中，在图7和图8中，SCL表示串行抵消列表(successive cancellation list)译码算法，polar SCL对应的曲线表示采用polar编码，并采用SCL译码算法进行译码。混合极化编码(hybrid polar)表示采用本申请提供的级联编码方法，在进行外码编码时，对信息比特序列划分得到的多个子序列，根据其信息长度从表2中选择对应的编码方法。对于信息比特序列来说，多个子序列对应的编码方法不尽相同，因此称为混合编码。Hybrid polar FSL是指一种对外码子码采取“按块”方式，而非“逐比特”方式的译码方法，具有更低的译码时延。
图7和图8中的纵坐标BLER表示误块率(block error ratio)，横坐标E S/N 0表示信噪比。其中，图7和图8中所示的性能曲线均是在加性高斯白噪声(additive white gaussian  noise,AWGN)的信道条件下进行仿真得到的。
可以看出，图7和图8中，在信噪比相同的条件下，Hybrid polar FSL对应的曲线的误块率总是低于polar SCL对应的曲线的误块率。由此可见，采用本申请提供的技术方案，对polar码的外码采用分组编码，内码采用polar编码，译码性能得到了提升。
以上结合图1至图8，对本申请提供的级联编码的方法作了详细说明。对于接收端(或者称为译码端)从发送端接收到待译码的比特序列，以“块”为单位进行译码的过程可以参考现有技术。应理解，本申请提供一种级联编码的方法，使得接收端能够以块为单位进行译码，而不是以比特为单位进行译码，并且，大量仿真结果表明译码性能得到了提升。例如，译码时延降低，误码率降低。但是，接收端以块为单位进行译码的过程可以参考现有技术，本文不作详述。
下面结合图9-图14，说明本申请提供的通信装置、编码装置、网络设备和终端设备。
参见图9，图9是本申请提供的通信装置500的示意性框图。如图9所示，装置500包括处理单元510和通信单元520。
处理单元510，用于对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥0且为整数；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字，n≥1且为整数；
通信单元520，用于发送处理单元510生成的第二码字。
参见图10，图10为本申请提供的通信装置600的示意性结构图。通信装置600用于实现编码的功能，该通信装置600包括：
处理装置601，用于获取待编码的信息比特序列，并对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥0且为整数；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字，n≥1且为整数；
收发器602，用于发送该第二码字。
可选地，收发器与天线603相连接。
在具体实现时，处理装置601可以处理器、芯片或者集成电路。
本申请还提供了一种处理装置601，用于实现上述方法实施例的级联编码方法。本申请实施例的级联编码方法200的部分或全部流程可以通过硬件来实现，或者也可以通过软件来实现。当通过硬件实现时，上述处理装置601可以为处理器。
可选地，当本申请的级联编码方法200的全部或部分流程通过硬件实现时，上述处理装置601还可以如图11所示。参见图11，图11为处理装置601的内部结构示意图。该处理装置601包括：
输入接口电路6011，用于获取输入的信息比特序列；
逻辑电路6012，用于并对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥0且为整数；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字，n≥1且为整数；
输出接口电路6013，用于输出第二码字。
上述逻辑电路6012可以用于执行本申请各实施例中所述的级联编码方法。详细流程参见上文方法实施例中的描述，此处不再赘述。
可选地，本申请提供的级联编码的方法200的部分或全部流程也可以通过软件来实 现。此种情况下，处理装置601可以为处理器，处理器用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，处理器执行上述方法实施例中的级联编码方法。
这里，存储器可以是物理上独立的单元。或者，存储器也可以与处理器集成在一起，本申请不作限定。
在另一种可选的实施例中，处理装置601可以只包括处理器。处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。可选地，处理装置601还包括存储器。
可选地，处理装置601为芯片时，所述芯片还可以包括输入接口和输出接口。输入接口用于接收输入的待编码的信息比特序列。输出接口用于输出所述第二码字。
基于本申请提供的级联编码方法200，本申请还提供一种通信装置700。通信装置700用于执行上述方法300。
参见图12，图12是本申请提供的通信装置700的示意性框图。通信装置700包括通信单元701和处理单元702。
通信单元701，用于从发送端接收待译码的比特序列；
处理单元702，用于执行上述译码方法300，对所述待译码的比特序列进行译码，得到译码结果。
参见图13，图13为本申请提供的通信装置800的示意性结构图。通信装置800用于实现译码的功能，该译码装置800包括：
收发器801，用于从发送端接收待译码的比特序列；
处理装置802，用于获取待译码的比特序列，并执行上述方法300的译码方法，对所述待译码的比特序列进行译码，得到译码结果。
可选地，收发器801与天线803相连接。
在具体实现时，处理装置802可以处理器、芯片或者集成电路。
本申请还提供了一种处理装置802，用于实现上述译码方法300。本申请实施例的译码方法300的部分或全部流程可以通过硬件来实现，或者也可以通过软件来实现。
可选地，当通过硬件实现时，上述处理装置802可以为处理器。
可选地，当本申请实施例的译码的方法300的全部或部分流程通过硬件实现时，上述处理装置802还可以如图14所示。
参见图14，图14为处理装置802的内部结构示意图。该处理装置601包括：
输入接口电路8021，用于获取待译码的比特序列；
逻辑电路8022，用于执行上述译码方法300，对所述待译码的比特序列进行译码，得到译码结果；
输出接口电路8023，用于输出译码结果。
可选地，处理装置802可以为处理器，处理器用于执行存储器中存储的计算机程序，当所述计算机程序被执行时，处理器执行上述译码方法300。
这里，存储器可以是物理上独立的单元。或者，存储器也可以与处理器集成在一起，本申请不作限定。
在另一种可选的实施例中，处理装置802只包括处理器。处理器通过电路/电线与存储器连接，用于读取并执行存储器中存储的计算机程序。可选地，处理装置802还包括存 储器。
可选地，处理装置802为芯片时，所述芯片还可以包括输入接口和输出接口。输入接口用于接收输入的待译码的比特序列。输出接口用于输出译码结果。
应理解，本申请提供的级联编码的方法200可以由发送端执行。例如图1所示的无线通信***，当网络设备101发送信号时，网络设备101为发送端。当终端设备102或103发送信号时，终端设备102或103为发送端。由此，下面本申请再提供一种网络设备和终端设备，该网络设备和终端设备具有实现上述级联编码的方法的功能。
参见图15，图15是本申请提供的网络设备3000的示意性结构图。如图15所示，网络设备3000可以应用于上述图1所示的无线通信***中，具有执行本申请的提供的级联编码的方法的功能。网络设备3000例如可以是基站。
网络设备3000可以包括一个或多个射频单元，如远端射频单元(remote radio unit，RRU)3100和一个或多个基带单元(baseband unit，BBU)。基带单元也可以称为数字单元(digital unit，DU)3200。所述RRU 3100可以称为收发单元，与图9中的通信单元520对应。可选地，该收发单元3100还可以称为收发机、收发电路、或者收发器等等，其可以包括至少一个天线3101和射频单元3102。可选地，收发单元3100可以包括接收单元和发送单元，接收单元可以对应于接收器(或称接收机、接收电路)，发送单元可以对应于发射器(或称发射机、发射电路)。所述RRU 3100部分主要用于射频信号的收发以及射频信号与基带信号的转换，例如，用于向终端设备发送第一随机接入资源的配置信息。所述BBU 3200部分主要用于进行基带处理，对基站进行控制等。所述RRU 3100与BBU 3200可以是物理上设置在一起，也可以物理上分离设置的，即分布式基站。
所述BBU 3200为网络设备3000的控制中心，也可以称为处理单元，可以与图9中的处理单元510对应，主要用于完成基带处理功能，如信道编码，速率匹配(可选地)、比特交织、调制等。例如，所述BBU(处理单元)可以用于控制基站执行上述级联编码的方法200。具体地，对待编码的信息比特序列进行分组编码，得到码长为B的多个第一码字；对该多个第一码字进行n级的极化编码，得到长度为B×2 n的第二码字。
在一个示例中，所述BBU 3200可以由一个或多个单板构成，多个单板可以共同支持单一接入制式的无线接入网(例如，LTE网)，也可以分别支持不同接入制式的无线接入网(例如，LTE网、5G网或其它网)。所述BBU 3200还包括存储器3201和处理器3202。所述存储器3201用以存储必要的指令和数据。所述处理器3202用于控制网络设备3000进行必要的动作，例如，用于控制网络设备3000执行上述方法实施例中由网络设备执行的操作流程。所述存储器3201和处理器3202可以服务于一个或多个单板。也就是说，可以每个单板上单独设置存储器和处理器。也可以是多个单板共用相同的存储器和处理器。此外每个单板上还可以设置有必要的电路。
应理解，图15所示的网络设备3000能够实现极化编码的方法。网络设备3000中的各个单元的操作和/或功能，分别为了实现级联编码的方法200实施例中的相应流程。为避免重复，此处适当省略详述描述。
上述BBU 3200可以用于执行前面方法实施例中描述的由网络设备内部实现的动作，例如，对信息比特序列进行级联编码。而RRU 3100可以用于执行前面方法实施例中描述的网络设备向终端设备发送或从终端设备接收的动作。例如，向终端设备发送第二码字。
在图1所示的无线通信***中进行上行传输时，终端设备102或103为发送端。下面对本申请提供的终端设备进行说明。
参见图16，图16是本申请提供的终端设备900的示意性结构图。如图16所示，如图16所示，终端设备900包括：一个或多个处理器901，一个或多个存储器902，一个或多个收发器903。处理器901用于控制收发器903收发信号，存储器902用于存储计算机程序，处理器901用于从存储器902中调用并运行该计算机程序，以执行本申请提供的级联编码的方法200的相应流程。为了简洁，此处不再赘述。
例如，终端设备700可以是图1所示的无线通信***中的终端设备102或103。处理器901可以对应图9中的处理单元510，收发器903可以对应图9中所示的通信单元520。
此外，本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当该计算机指令在计算机上运行时，使得计算机执行本申请实施例的级联编码的方法200的相应操作和/或流程。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行本申请实施例的级联编码的方法200的相应操作和/或流程。
本申请还提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行本申请提供的级联编码的方法200的相应操作和/或流程。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收待编码的比特序列，处理器从通信接口获取该信息比特序列，并采用本申请实施例的级联编码方法200，对该信息比特序列进行级联编码；通信接口输出编码后的比特序列。该通信接口可以是输入输出接口。
本申请提供一种计算机可读存储介质，该计算机可读存储介质中存储有计算机指令，当该计算机指令在计算机上运行时，使得计算机执行本申请实施例的译码方法300的相应操作和/或流程。
本申请还提供一种计算机程序产品，该计算机程序产品包括计算机程序代码，当该计算机程序代码在计算机上运行时，使得计算机执行本申请实施例的译码方法300的相应操作和/或流程。
本申请还提供一种芯片，包括处理器。处理器用于读取并执行存储器中存储的计算机程序，以执行申请提供的译码方法300的相应操作和/或流程。
可选地，该芯片还包括存储器，该存储器与该处理器通过电路或电线与存储器连接。进一步可选地，该芯片还包括通信接口，处理器与该通信接口连接。通信接口用于接收待译码的比特序列，处理器从通信接口获取该待译码的比特序列，并采用本申请实施例中的译码方法300，对该待译码的比特序列进行译码，得到译码结果；通信接口用于输出译码结果。该通信接口可以是输入输出接口。在实现过程中，上述方法的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。上述方法实施例的步骤可以直接体现为硬件处理器执行完成，或者用处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息， 结合其硬件完成上述方法的步骤。
本申请实施例中所述的芯片，可以是现场可编程门阵列(field-programmable gate array，FPGA)、专用集成芯片(application specific integrated circuit，ASIC)、***芯片(system on chip，SoC)、中央处理器(central processor unit，CPU)、网络处理器(Network Processor，NP)、数字信号处理电路(digital signal processor，DSP)，还可以是微控制器(micro controller unit，MCU、可编程控制器(programmable logic device，PLD)或其它集成芯片。
本申请实施例中的处理器可以是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法实施例的各步骤可以通过处理器中的硬件的集成逻辑电路或者软件形式的指令完成。处理器可以是通用处理器、DSP、ASIC、FPGA或其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。本申请实施例公开的方法的步骤可以直接体现为硬件编码处理器执行完成，或者用编码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的存储介质中。该存储介质位于存储器，处理器读取存储器中的信息，结合其硬件完成上述方法的步骤。
本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(dynamic RAM，DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。应注意，本文描述的***和方法的存储器旨在包括但不限于这些和任意其它适合类型的存储器。
本领域普通技术人员可以意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、或者计算机软件和电子硬件的结合来实现，具体取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
在本申请以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。例如，多个单元或组件可以结合或者可以集成到另一个***，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本申请实施例的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本申请各个实施例所述方法的全部或部分步骤。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种级联编码的方法，其特征在于，包括：
    对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥1且为整数；
    对所述多个第一码字进行n级的极化编码，得到码长为B×2 n的第二码字，n≥1且为整数；
    发送所述第二码字。
  2. 根据权利要求1所述的方法，其特征在于，所述对信息比特序列进行分组编码，得到码长为B的多个第一码字，包括：
    获取所述第二码字的目标码长N和所述第一码字的码长B，N＝B×2 n，N为整数；
    根据所述第二码字的目标码长N和所述第一码字的码长B，对所述信息比特序列进行分组，得到多个子序列；
    根据所述多个子序列中每个子序列包括的比特数目，确定对每个子序列进行编码所需的生成矩阵；
    使用与所述多个子序列中每个子序列对应的生成矩阵，对所述多个子序列进行编码，得到所述码长为B的多个第一码字。
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：
    根据所述目标码长N和所述第一码字的码长B，如果确定不存在一个正整数R使得R＝2 n，则选择正整数L，对所述码长为B的多个第一码字进行m级的极化编码，得到码长为B×L的第三码字，L＝2 m，L>R，m>n，m、L和R为正整数；
    对所述码长为B×L的第三码字进行速率匹配，得到所述码长为B×2 n的第二码字。
  4. 根据权利要求2或3所述的方法，其特征在于，所述信息比特序列的每个子序列可以使用如下任意一种码进行编码：
    重复码、BCH码、单纯形码、BCH码的对偶码、polar码、奇偶检验码、单纯形码的重复码的对偶码。
  5. 根据权利要求4所述的方法，其特征在于，在所述B＝16的情况下，所述根据所述多个子序列中每个子序列包括的比特数目，确定对每个子序列进行分组编码所需的生成矩阵，包括：
    在子序列包括的比特数目为1时，所述生成矩阵为G 1＝[1111111111111111]，所述子序列采用所述重复码进行编码；
    在子序列包括的比特数目为2时，所述生成矩阵为
    Figure PCTCN2019104786-appb-100001
    其中，所述子序列采用所述单纯形码进行编码；
    在子序列包括的比特数目为3时，所述生成矩阵为
    Figure PCTCN2019104786-appb-100002
    所述子序列采用所述单纯形码进行编码；
    在子序列包括的比特数目为4时，所述生成矩阵为
    Figure PCTCN2019104786-appb-100003
    Figure PCTCN2019104786-appb-100004
    所述子序列采用所述单纯形码进行编码；
    在所述子序列包括的比特数目为6时，所述生成矩阵为
    Figure PCTCN2019104786-appb-100005
    所述子序列采用所述BCH码进行编码；
    在所述子序列包括的比特数目为7时，所述生成矩阵为
    Figure PCTCN2019104786-appb-100006
    所述子序列采用所述BCH码进行编码；
    在所述子序列包括的比特数目为9或10时，所述生成矩阵为所述BCH码的校验矩阵，所述子序列采用所述BCH码的对偶码进行编码；
    在所述子序列包括的比特数目为12，13或14时，所述生成矩阵为所述单纯形码的重复码的对偶码的校验矩阵，所述子序列采用所述单纯形码的重复码的对偶码进行编码；
    在所述子序列包括的比特数目为15时，所述生成矩阵为所述G 1，所述子序列采用单比特奇偶校验码进行编码。
  6. 一种通信装置，其特征在于，包括：
    处理单元，用于对信息比特序列进行分组编码，得到码长为B的多个第一码字，B≥1且为整数；
    所述处理单元，还用于对所述多个第一码字进行n级的极化编码，得到码长为B×2 n的第二码字，n≥1且为整数；
    通信单元，用于发送所述处理单元生成的所述第二码字。
  7. 根据权利要求6所述的通信装置，其特征在于，所述处理单元用于：
    获取所述第二码字的目标码长N和所述第一码字的码长B，N＝B×2 n，N为整数；
    根据所述第二码字的目标码长N和所述第一码字的码长B，对所述信息比特序列进行分组，得到多个子序列；
    根据所述多个子序列中每个子序列包括的比特数目，确定对每个子序列进行编码所需的生成矩阵；
    使用与所述多个子序列中每个子序列对应的生成矩阵，对所述多个子序列进行编码，得到所述码长为B的多个第一码字。
  8. 根据权利要求7所述的通信装置，其特征在于，所述处理单元还用于：
    根据所述目标码长N和所述第一码字的码长B，如果确定不存在一个正整数R使得R＝2 n，则选择正整数L，对所述码长为B的多个第一码字进行m级的极化编码，得到码长为B×L的第三码字，L＝2 m，L>R，m>n，m、L和R为正整数；
    对所述码长为B×L的第三码字进行速率匹配，得到所述码长为B×2 n的第二码字。
  9. 根据权利要求7或8所述的通信装置，其特征在于，所述处理单元使用如下任意一种码对信息比特序列的每个子序列进行编码：
    重复码、BCH码、单纯形码、BCH码的对偶码、polar码、奇偶检验码、单纯形码的重复码的对偶码。
  10. 根据权利要求9中任一项所述的通信装置，其特征在于，在所述B＝16的情况下，所述处理单元用于：
    对比特数目为1的子序列，采用所述重复码对所述子序列进行编码，所述生成矩阵为G 1＝[1111111111111111]；
    对比特数目为2的子序列，采用所述单纯形码对所述子序列进行编码，其中，所述生成矩阵为
    Figure PCTCN2019104786-appb-100007
    对比特数目为3的子序列，采用所述单纯形码对所述子序列进行编码，所述生成矩阵为
    Figure PCTCN2019104786-appb-100008
    比特数目为4的子序列，采用所述单纯形码对所述子序列进行编码，所述生成矩阵为
    Figure PCTCN2019104786-appb-100009
    对比特数目为6的子序列，采用所述BCH码对所述子序列进行编码，所述生成矩阵为
    Figure PCTCN2019104786-appb-100010
    对比特数目为7的子序列，采用所述BCH码对所述子序列进行编码，所述生成矩阵 为
    Figure PCTCN2019104786-appb-100011
    比特数目为9或10的子序列，采用所述BCH码的对偶码对所述子序列进行编码，所述生成矩阵为所述BCH码的校验矩阵；
    对比特数目为12，13或14的子序列，采用所述单纯形码的重复码的对偶码对所述子序列进行编码，所述生成矩阵为所述单纯形码的重复码的对偶码的校验矩阵；
    对比特数目为15的子序列，采用单比特奇偶校验码对所述子序列进行编码，所述生成矩阵为所述G 1。
  11. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质中存储有指令，当所述计算机指令在计算机上运行时，使得所述计算机执行如权利要求1-5中任一项所述的方法。
  12. 一种芯片，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于读取并执行所述存储器中存储的所述计算机程序，当所述计算机程序被执行时，所述处理器执行如权利要求1-5中任一项所述的方法。
  13. 一种计算机程序产品，其特征在于，所述计算机程序产品包括计算机程序代码，当所述计算机程序代码在计算机上运行时，使得计算机执行如权利要求1至5中任一所述的方法。
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