WO2020040550A1 - Transparent display device and method for manufacturing same - Google Patents
Transparent display device and method for manufacturing same Download PDFInfo
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- WO2020040550A1 WO2020040550A1 PCT/KR2019/010658 KR2019010658W WO2020040550A1 WO 2020040550 A1 WO2020040550 A1 WO 2020040550A1 KR 2019010658 W KR2019010658 W KR 2019010658W WO 2020040550 A1 WO2020040550 A1 WO 2020040550A1
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- Prior art keywords
- circuit board
- circuit
- layer
- pattern
- layer circuit
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims abstract description 8
- 230000001070 adhesive effect Effects 0.000 claims abstract description 8
- 229920003002 synthetic resin Polymers 0.000 claims abstract description 3
- 239000000057 synthetic resin Substances 0.000 claims abstract description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 19
- 238000007747 plating Methods 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 7
- 239000011889 copper foil Substances 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 238000003475 lamination Methods 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- 239000011347 resin Substances 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- 238000007689 inspection Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 230000007423 decrease Effects 0.000 claims 2
- 239000010410 layer Substances 0.000 description 86
- 239000004642 Polyimide Substances 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000002042 Silver nanowire Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021392 nanocarbon Inorganic materials 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 239000004417 polycarbonate Substances 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Definitions
- the present invention relates to a transparent display device and a method of manufacturing the same.
- the transparent LED (Light Emitting Diode) display has various advantages in that the internal wiring is inconspicuous.
- a transparent LED display uses a transparent electrode such as silver nanowires or nano carbon tubes on a substrate made of a transparent material.
- this type of circuit can be configured on both sides, but a lot of resistance occurs due to the configuration characteristics of the electrode.
- the conventional transparent LED display by printing a copper pattern on a transparent material to form a circuit, at this time, there is no way to reduce the circuit more than a certain width.
- the circuit since the circuit should be configured on both sides of one circuit board as much as possible, the circuit configuration is complicated, and because of the large density of the circuit, the transparent area is largely encroached by the area occupied by the circuit line width. There is a problem that can not take advantage of the properties of the material.
- the technical problem to be achieved by the present invention is to configure the substrate on which the circuit pattern is printed in a multi-layered structure, to disperse the display driving circuit in each layer, the circuit pattern of the upper substrate and the circuit pattern of the lower substrate at least partially overlap the bottom
- the circuit pattern of the substrate is concealed by the circuit pattern of the upper substrate, thereby securing more areas of the transparent portion of the circuit board, thereby making it easy to secure transparency in the side portion of the circuit board, especially where the circuit is dense.
- the present invention provides a plurality of circuit boards having a multi-layer structure formed of a flexible synthetic resin and having a circuit pattern formed on at least one side thereof, and a light emitting device mounted on a circuit board of the highest layer among the plurality of circuit boards. And a control unit connected to the circuit board to drive the light emitting device, wherein the plurality of circuit boards are bonded to each other through an adhesive material to form a single substrate, and the circuit patterns are formed to be connected to each other in layers.
- the circuit patterns of at least some of the circuit patterns respectively formed on the plurality of circuit boards are formed when at least a portion of the circuit patterns of the lower circuit board is overlapped by at least some circuit patterns of the upper circuit board when each circuit board is overlapped up and down.
- the total face of the circuit pattern of each of the plurality of circuit boards The same or similar to the total area of the pattern comparing circuit and when formed on a single circuit board and to provide a plurality of relatively wider transparent area is obtained a transparent display device, which by forming a circuit pattern on a circuit board.
- the circuit pattern is preferably electrically connected through a through-hole formed in the substrate for each layer.
- the circuit pattern is composed of a one-layer circuit board, a two-layer circuit board, a three-layer circuit board, and a four-layer circuit board. Copper plating is performed on the through holes formed in the one-layer circuit board and the two-layer circuit board. Copper plating is also applied to the through-holes formed in the circuit board and the four-layer circuit board, and through-holes are processed through all the circuit boards made of copper plating. It is preferably formed by curing after hole plugging.
- the said circuit pattern is formed by processing the copper foil layer formed in the vapor deposition method in the transparent film material by exposure method.
- the plurality of circuit boards are preferably bonded to each other using a lamination method selected from an optically clear adhesive (OCA) of a transparent double-sided tape type and an optically clear resin (OCR) of a transparent liquid type.
- OCA optically clear adhesive
- OCR optically clear resin
- the circuit width of the circuit pattern is preferably reduced as the number of circuit boards forming a multilayer increases.
- through-holes are processed (S101) on the one-layer circuit board 101-1 and the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board 101 are processed.
- Each through hole of the one-layer circuit board 101-1, the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 is copper plated (S105).
- It provides a method of manufacturing a transparent display device comprising a.
- a substrate in which a circuit pattern is printed is configured in a multi-layered structure, and the display driving circuit is dispersed in each layer, wherein the circuit pattern of the upper substrate and the circuit pattern of the lower substrate are at least partially overlapped with each other.
- the circuit pattern of the substrate is concealed by the circuit pattern of the upper substrate, thereby securing more areas of the transparent portion of the circuit board, thereby making it easy to ensure transparency especially at the side portions of the circuit board where the circuit is dense. have.
- FIG. 1 is an exploded perspective view of a transparent display device to which an embodiment of the present invention is applied.
- FIG. 2 is a view for explaining an embodiment of the present invention.
- FIG. 3 is a perspective view illustrating a multilayer structure of a circuit board according to an exemplary embodiment of the present invention.
- FIG. 4 is a perspective view of a circuit board of a multilayer structure according to an embodiment of the present invention.
- FIG. 8 is a view for comparing the circuit width of a multilayer structure according to an embodiment of the present invention and a conventional two-layer structure.
- FIG. 9 is a flowchart illustrating a process of manufacturing a transparent display device according to an embodiment of the present invention.
- circuit patterns of at least a portion of circuit patterns respectively formed on a plurality of circuit boards are visually concealed by circuit patterns of the upper circuit board when the circuit boards are overlapped up and down. It is characterized in that configured to.
- the upper circuit board is completed for signage.
- the circuit pattern of the lower circuit board is concealed from the circuit pattern of the upper circuit board so that the circuit pattern overlaps and is visually seen from the top to the bottom.
- a circuit pattern having a total area equal to the total area of each circuit pattern of the plurality of circuit boards is formed on a single circuit board.
- a wider transparent area may be secured than when a circuit pattern is formed on a single circuit board when a circuit pattern is formed on a plurality of circuit boards.
- signage transparency can be increased.
- the present invention is to solve the problem that the transparency of the signage due to the above circuit pattern by forming an excessively dense circuit pattern on a single circuit board.
- substrate became the up-and-down same pattern, it demonstrated, but it may be a similar pattern up-down. That is, the gist of the present invention is that transparency is ensured in the process while distributing the circuit patterns in a plurality of circuit patterns.
- FIG. 1 is an exploded perspective view of a transparent display device to which an embodiment of the present invention is applied
- FIG. 2 is a view for explaining an embodiment of the present invention.
- the transparent display apparatus 100 includes a transparent substrate 101 and a controller 103.
- the transparent substrate 101 is made of a transparent flexible material and is a printed circuit board (PCB) on which a circuit pattern 105 is printed.
- the transparent substrate 101 may be, for example, at least one transparent film material of polyimide (PI), polyethylene terephthalate (PET), and polycarbonate (PC).
- PI polyimide
- PET polyethylene terephthalate
- PC polycarbonate
- the circuit pattern 105 may be formed on the transparent substrate 101 by exposing and etching a copper foil surface formed by a deposition method on a transparent film material.
- the circuit pattern may be formed on one side or both sides of the printed circuit board. When formed on both sides, it is preferable because a more dense circuit pattern can be formed.
- a plurality of light emitting devices may be mounted on the transparent substrate 101, and the light emitting devices (not shown) may be RGB light-emitting diodes (LEDs).
- LEDs RGB light-emitting diodes
- the circuit pattern 105 of the transparent substrate 101 is connected to the transparent cable 107, the cable 107 is connected to the connector 109, and the connector 109 is connected to the controller 103. That is, the circuit pattern 105 on which the light emitting device (not shown) is mounted is connected to the controller 103 through the cable 107 and the connector 109.
- the control part 103 is a structure which outputs control signals, such as a power signal and a drive signal, to the circuit pattern 105, and contains a drive driver IC.
- the plurality of RGB LEDs consists of four terminals including a common terminal. Therefore, in the case of a substrate conventionally composed of a single layer or less than three layers, as shown in FIG. 2, the closer the connector or integrated circuit (IC) is, the higher the density of the circuit pattern is, and thus the transparency is inferior.
- IC integrated circuit
- the transparent substrate 101 has a multilayer structure composed of at least three layers.
- FIG. 3 is a perspective view illustrating a multilayer structure of a circuit board according to an embodiment of the present invention
- FIG. 4 is a perspective view of a circuit board having a multilayer structure according to an embodiment of the present invention
- FIGS. 5, 6, and 7 are views of the present invention.
- An example of a circuit board having a conventional two-layer structure for comparison with an embodiment is shown
- FIG. 8 is a view for comparing a circuit width of a multilayer structure and a conventional two-layer structure according to an embodiment of the present invention.
- the circuit board 101 includes a first layer substrate 101-1, a second layer substrate 101-3, a third layer substrate 101-5, and a fourth layer substrate 101. -7).
- Each printed circuit pattern 105-1, 105-3, 105-5, and 105-7 is printed on the substrates 101-1, 101-3, 101-5, and 101-7 for each layer.
- the substrates 101-1, 101-3, 101-5, and 101-7 for each layer are combined with an optical adhesive material to form a single substrate 101, as shown in FIG. 4.
- Optical adhesive materials may be employed among the optically clear adhesive (OCA) of the transparent double-sided tape type and the optically clear resin (OCR) of the transparent liquid type.
- OCA optically clear adhesive
- OCR optically clear resin
- the full lamination method may be used for adhesion.
- FIG. 8A shows the circuit width of the circuit board 101 having a two-layer structure, and the circuit width is about 3.20 mm to 3.50 mm.
- Figure 8 (b) shows the circuit width of the circuit board 101 of the multilayer structure according to the embodiment of the present invention, the circuit width is 1.31mm ⁇ 2mm.
- the circuit area of the circuit board 101 of the multilayer structure is reduced to approximately 43 to 59% when compared to the two-layer structure.
- the effect of circuit area reduction of 50% before and after through layer addition is expected, thereby increasing transmission. That is, the circuit width of the circuit pattern is preferably reduced as the number of circuit boards forming a multilayer increases. That way, more transparent areas can be secured.
- the circuit patterns formed on the layers of each circuit board 101 are made the same up and down, and the circuit patterns are viewed from the upper circuit board.
- the circuit pattern of the lower circuit board is concealed by overlapping the circuit pattern of the lower circuit board up and down and the circuit pattern of the upper circuit board, the area of the transparent area of the circuit board is more secured. This can be further secured to meet the spirit of the present invention.
- the circuit patterns overlap each other, so that when viewed from the top visually, the lower circuit pattern is completely invisible (hidden) If it constitutes, the transparent area of a circuit board will increase by that much.
- the same pattern is not necessarily implemented in the same region of the upper and lower circuit boards. That is, even if the regions of the upper circuit board and the lower circuit board on which the same pattern is formed are somewhat inconsistent, this may be configured to adjust the overlapping positions of the upper and lower circuit boards so that the same patterns overlap the upper and lower sides, but are not limited thereto.
- FIG. 9 is a flowchart illustrating a process of manufacturing a transparent display device according to an embodiment of the present invention.
- through-holes are processed (S101) in the one-layer circuit board 101-1 and the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board ( 101-7) through holes are processed (S103).
- Printed circuit patterns 105-3 and 105-5 are formed on the two-layer circuit board 101-3 and the three-layer circuit board 101-5 (S107).
- One side of the circuit board is laminated by laminating with OCA or OCR and bonded (S109).
- the adhesive layer may be two to three times the thickness of the pattern height. And 50 to 80 degrees, pressure 5 ⁇ 20kg / cm2 can be applied to strengthen the bond.
- the through-holes penetrating through the one-layer circuit board 101-1 and the two-layer circuit board 101-3 and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 are processed (S111). ), And then hardened after hole plugging with conductive paste in each through hole so that the entire circuit layer can be conductive (S113).
- Each of the printed circuit patterns 105-1 and 105-7 is formed on the one-layer circuit board 101-1 and the four-layer circuit board 101-7 positioned at the outermost layer (S117).
- TIN plating is performed on the one-layer circuit pattern 105-1 and the four-layer circuit pattern 107-7 (S119).
- the transparent solder resist is printed on the outer surfaces of the one-layer circuit board 101-1 and the four-layer circuit board 101-7 positioned at the outermost layer and then cured (S121). This order can be implemented optionally.
- the embodiments of the present invention described above are not only implemented through the apparatus and the method, but may also be implemented through a program for realizing a function corresponding to the configuration of the embodiments of the present invention or a recording medium on which the program is recorded.
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A transparent display device and a method for manufacturing same are provided. The device comprises: a plurality of circuit substrates having a multilayer structure, each of which has a circuit pattern formed on at least one side surface thereof and is made of a flexible synthetic resin material; a light emitting element mounted on the highest layer circuit substrate among the plurality of circuit substrates; and a control unit connected to the circuit substrate to drive the light emitting element, wherein the plurality of circuit substrates are bonded through an adhesive material to be formed into a single substrate, circuit patterns of the circuit substrates are electrically conductive to each other between layers, and when the plurality of circuit substrates overlap with each other, at least a part of the circuit patterns formed on the circuit substrates is disposed such that the circuit pattern of a lower circuit substrate is visually hidden by the circuit pattern of an upper circuit substrate.
Description
본 발명은 투명 디스플레이 장치, 그리고 그 제조 방법에 관한 것이다.The present invention relates to a transparent display device and a method of manufacturing the same.
공공장소나 상업용 공간 등에서, 디지털 사이니지(digital signage), 즉 디지털 정보 디스플레이를 통해 각종 정보나 광고를 제공하는 디지털 게시판 형태의 광고가 각광을 받고 있다.In public places and commercial spaces, digital signage, that is, advertisements in the form of digital bulletin boards that provide various information or advertisements through digital information displays have been in the spotlight.
디지털 사이니지의 종류 중에서, 투명 LED(Light Emitting Diode) 디스플레이는 내부의 배선이 눈에 띄지 않는 이점으로 인하여, 각종 공공 장소나 상업용 공간Among the types of digital signage, the transparent LED (Light Emitting Diode) display has various advantages in that the internal wiring is inconspicuous.
등에서 경관 연출, 정보 및 볼거리 제공 등의 수단으로서 널리 활용되고 있다.It is widely used as a means for directing scenery, providing information and attractions.
종래에 투명 LED 디스플레이는, 투명 소재의 기판 위에 은나노와이어 또는 나노 탄소 튜브 등의 투명 전극을 사용한다. 그러나, 이러한 방식은 회로를 양면으로 구성을 할 수는 있으나 전극의 구성 특성상 저항이 많이 발생한다. 또한, 고전류를 사용하는 옥외용 디스플레이의 발광체를 사용하기 어렵다.Conventionally, a transparent LED display uses a transparent electrode such as silver nanowires or nano carbon tubes on a substrate made of a transparent material. However, this type of circuit can be configured on both sides, but a lot of resistance occurs due to the configuration characteristics of the electrode. In addition, it is difficult to use a light emitting body of an outdoor display that uses a high current.
또한, 종래에 투명 LED 디스플레이는, 투명 소재에 구리 패턴을 인쇄하여 회로를 형성하는데, 이때, 회로를 특정 폭 이상 줄일 수 있는 방법이 없다.In addition, the conventional transparent LED display, by printing a copper pattern on a transparent material to form a circuit, at this time, there is no way to reduce the circuit more than a certain width.
또한, 종래에 투명 LED 디스플레이는, 1개의 회로 기판의 양면에 회로를 최대한 구성하여야 하므로 회로의 구성이 복잡하고, 회로의 밀도가 커서 그만큼 투명영역이 크게 잠식되며, 회로 선폭이 차지하는 영역으로 인해 투명 소재의 특성을 살릴 수 없는 문제가 있다.In addition, in the conventional transparent LED display, since the circuit should be configured on both sides of one circuit board as much as possible, the circuit configuration is complicated, and because of the large density of the circuit, the transparent area is largely encroached by the area occupied by the circuit line width. There is a problem that can not take advantage of the properties of the material.
따라서, 회로의 밀도를 낮추면서도 회로 본연의 기능이 저하되지 않도록 하는 기술적 개발이 필요한 실정이다.Therefore, there is a need for technical development that reduces the density of the circuit and does not degrade the original function of the circuit.
본 발명이 이루고자 하는 기술적 과제는 회로 패턴이 인쇄되는 기판을 다층 구조로 구성하여, 디스플레이 구동 회로를 각 층에 분산시키되, 상부 기판의 회로 패턴과 하부 기판의 회로 패턴이 적어도 부분적으로 중첩되어 그 하부 기판의 회로패턴이 상부 기판의 회로 패턴에 의하여 은폐되도록 하며, 따라서 회로 기판 중 투명 부분의 영역을 보다 많이 확보하도록 하며, 이로써 특히 회로가 밀집되는 회로기판의 측면부에서의 투명성 확보가 용이한 투명 디스플레이 장치, 그리고 그 제조 방법을 제공하는 것이다. The technical problem to be achieved by the present invention is to configure the substrate on which the circuit pattern is printed in a multi-layered structure, to disperse the display driving circuit in each layer, the circuit pattern of the upper substrate and the circuit pattern of the lower substrate at least partially overlap the bottom The circuit pattern of the substrate is concealed by the circuit pattern of the upper substrate, thereby securing more areas of the transparent portion of the circuit board, thereby making it easy to secure transparency in the side portion of the circuit board, especially where the circuit is dense. An apparatus and a manufacturing method thereof are provided.
본 발명은 전술한 목적을 달성하기 위하여, 적어도 일측면에 회로 패턴이 형성되고 플렉시블 합성수지 재질로 형성된 다층 구조의 복수의 회로 기판, 상기 복수의 회로 기판 중 가장 최상위 계층의 회로 기판에 탑재되는 발광 소자, 그리고 상기 회로 기판과 연결되어 상기 발광 소자를 구동하는 제어부를 포함하고, 상기 복수의 회로 기판은, 접착 소재를 통해 접합되어 하나의 기판으로 형성되고, 상기 회로 패턴은, 층 별로 서로 도통하도록 형성되며, 상기 복수의 회로 기판에 각각 형성된 회로 패턴 중 적어도 일부의 회로패턴은 각 회로 기판이 상하로 중첩되었을 때, 하부 회로기판의 적어도 일부의 회로패턴이 상부 회로기판의 적어도 일부의 회로패턴에 의하여 시각적으로 은폐되도록 배치 및 구성되고, 복수의 회로 기판 각각의 회로 패턴의 총 면적과 동일하거나 유사한 총 면적의 회로 패턴을 단일의 회로 기판에 형성하였을 때와 비교하여 복수의 회로 기판에 회로패턴을 형성함으로써 상대적으로 더 넓은 투명영역이 확보되는, 투명 디스플레이 장치를 제공한다.In order to achieve the above object, the present invention provides a plurality of circuit boards having a multi-layer structure formed of a flexible synthetic resin and having a circuit pattern formed on at least one side thereof, and a light emitting device mounted on a circuit board of the highest layer among the plurality of circuit boards. And a control unit connected to the circuit board to drive the light emitting device, wherein the plurality of circuit boards are bonded to each other through an adhesive material to form a single substrate, and the circuit patterns are formed to be connected to each other in layers. The circuit patterns of at least some of the circuit patterns respectively formed on the plurality of circuit boards are formed when at least a portion of the circuit patterns of the lower circuit board is overlapped by at least some circuit patterns of the upper circuit board when each circuit board is overlapped up and down. Placed and configured to be visually concealed, the total face of the circuit pattern of each of the plurality of circuit boards The same or similar to the total area of the pattern comparing circuit and when formed on a single circuit board and to provide a plurality of relatively wider transparent area is obtained a transparent display device, which by forming a circuit pattern on a circuit board.
상기 회로 패턴은, 각 층 별 기판에 형성된 스루홀(thru-hole)을 통해 전기적으로 연결되는 것이 바람직하다.The circuit pattern is preferably electrically connected through a through-hole formed in the substrate for each layer.
상기 회로 패턴은, 1층 회로 기판, 2층 회로 기판, 3층 회로 기판, 4층 회로 기판으로 구성되고,상기 1층 회로 기판과 2층 회로 기판에 형성된 스루홀에는 동도금이 이루어지고, 3층 회로 기판과 4층 회로 기판에 형성된 스루홀에도 동도금이 이루어지며, 동도금이 이루어진 모든 회로기판을 전체적으로 관통하는 스루홀을 가공한후, 전 회로층이 도통이 될 수 있도록 각 스루홀에 전도성 페이스트로 홀플러깅후 경화를하여 형성되는 것이 바람직하다.The circuit pattern is composed of a one-layer circuit board, a two-layer circuit board, a three-layer circuit board, and a four-layer circuit board. Copper plating is performed on the through holes formed in the one-layer circuit board and the two-layer circuit board. Copper plating is also applied to the through-holes formed in the circuit board and the four-layer circuit board, and through-holes are processed through all the circuit boards made of copper plating. It is preferably formed by curing after hole plugging.
상기 회로 패턴은, 투명 필름 소재에 증착 방식으로 형성된 동박층을 노광 방식으로 가공하여 형성되는 것이 바람직하다.It is preferable that the said circuit pattern is formed by processing the copper foil layer formed in the vapor deposition method in the transparent film material by exposure method.
상기 복수의 회로 기판은, 투명한 양면 테이프 타입의 OCA(optically clear adhesive)와 투명한 액체 타입의 OCR(optically clear resin) 중에서 선택된 라미네이션(lamination) 방식을 사용하여 서로 결합되는 것이 바람직하다. The plurality of circuit boards are preferably bonded to each other using a lamination method selected from an optically clear adhesive (OCA) of a transparent double-sided tape type and an optically clear resin (OCR) of a transparent liquid type.
상기 회로 패턴의 회로 폭은 다층을 이루는 회로 기판의 숫자가 많아질수록 감소되는 것이 바람직하다.The circuit width of the circuit pattern is preferably reduced as the number of circuit boards forming a multilayer increases.
또한, 본 발명은 1층 회로 기판(101-1)과 2층 회로 기판(101-3)에 스루홀을 가공(S101)하고, 3층 회로 기판(101-5)과 4층 회로 기판(101-7)에 스루홀을 가공하는 제1단계; In addition, according to the present invention, through-holes are processed (S101) on the one-layer circuit board 101-1 and the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board 101 are processed. A first step of processing the through hole at -7);
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)의 각 스루홀을 동도금(S105)하여 각 스루홀을 통전되도록 하는 제2단계;Each through hole of the one-layer circuit board 101-1, the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 is copper plated (S105). A second step of energizing each through hole;
2층 회로 기판(101-3) 과 3층 회로 기판(101-5)에 각각의 인쇄회로패턴(105-3, 105-5)를 형성하는 제3단계;A third step of forming respective printed circuit patterns 105-3 and 105-5 on the two-layer circuit board 101-3 and the three-layer circuit board 101-5;
1층 회로 기판(101-1)과 2층 회로 기판(101-3)이 결합된 회로 기판의 한쪽면 또는 3층 회로 기판(101-5)과 4층 회로 기판(101-7)이 결합된 회로 기판의 한쪽면을 라미네이팅(Laminating)하여, 결합하는 제4단계;One side of the circuit board on which the one-layer circuit board 101-1 and the two-layer circuit board 101-3 are coupled or the three-layer circuit board 101-5 and the four-layer circuit board 101-7 are coupled. A fourth step of laminating and bonding one side of the circuit board;
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)을 전체적으로 관통하는 스루홀을 가공하는 제5단계;The agent which processes through-hole which penetrates the 1-layer circuit board 101-1 and the 2-layer circuit board 101-3, and the 3-layer circuit board 101-5 and the 4-layer circuit board 101-7 as a whole. Step 5;
전 회로층이 도통이 될 수 있도록 각 스루홀에 전도성 페이스트로 홀플러깅후 경화를 하는 제6단계;A sixth step of hardening after hole plugging with a conductive paste in each through hole so that the entire circuit layer is conductive;
1층 회로 기판(101-1)과 4층 회로 기판(101-7)에 각각의 인쇄회로패턴(105-1, 105-7)을 형성하는 제7단계;A seventh step of forming printed circuit patterns 105-1 and 105-7 on the one-layer circuit board 101-1 and the four-layer circuit board 101-7;
1층 회로 패턴(105-1)과 4층 회로 패턴(107-7)에 TIN 도금을 실시하는 제8단계;An eighth step of applying TIN plating to the one-layer circuit pattern 105-1 and the four-layer circuit pattern 107-7;
전체 회로의 도통검사 후 외형을 가공하는 제9단계;A ninth step of processing the appearance after the conduction inspection of the entire circuit;
를 포함하는, 투명 디스플레이 장치의 제조방법을 제공한다.It provides a method of manufacturing a transparent display device comprising a.
제6단계 이후에, 기존의 1층 및 4층의 동박면과 홀플러깅 경계면의 접지력을 향상 시키기 위해 전체적인 동도금을 실시하는 단계;를 더 포함하는 것이 바람직하다.After the sixth step, performing a total copper plating to improve the grounding force of the existing copper foil surface and hole plugging interface of the first and fourth layers;
제8단계 이후에, 1층 회로 기판(101-1)과 4층 회로 기판(101-7)의 외부면에 투명 솔더 레지스트를 인쇄한 후 경화하는 제9단계;를 더 포함하는 것이 바람직하다.After the eighth step, a ninth step of hardening after printing a transparent solder resist on the outer surface of the one-layer circuit board 101-1 and the four-layer circuit board 101-7.
제4단계는, OCA 또는 OCR로 라미네이팅하는 것이 바람직하다.In the fourth step, laminating with OCA or OCR is preferable.
본 발명의 실시예에 따르면, 회로 패턴이 인쇄되는 기판을 다층 구조로 구성하여, 디스플레이 구동 회로를 각 층에 분산시키되, 상부 기판의 회로 패턴과 하부 기판의 회로 패턴이 적어도 부분적으로 중첩되어 그 하부 기판의 회로패턴이 상부 기판의 회로 패턴에 의하여 은폐되도록 하며, 따라서 회로 기판 중 투명 부분의 영역을 보다 많이 확보하도록 하며, 이로써 특히 회로가 밀집되는 회로기판의 측면부에서의 투명성 확보가 용이한 효과가 있다.According to an embodiment of the present invention, a substrate in which a circuit pattern is printed is configured in a multi-layered structure, and the display driving circuit is dispersed in each layer, wherein the circuit pattern of the upper substrate and the circuit pattern of the lower substrate are at least partially overlapped with each other. The circuit pattern of the substrate is concealed by the circuit pattern of the upper substrate, thereby securing more areas of the transparent portion of the circuit board, thereby making it easy to ensure transparency especially at the side portions of the circuit board where the circuit is dense. have.
도 1은 본 발명의 실시예가 적용되는 투명 디스플레이 장치의 분해 사시도이다.1 is an exploded perspective view of a transparent display device to which an embodiment of the present invention is applied.
도 2는 본 발명의 실시예를 설명하기 위한 도면이다.2 is a view for explaining an embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 회로 기판의 다층 구조를 도시한 사시도이다.3 is a perspective view illustrating a multilayer structure of a circuit board according to an exemplary embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 다층 구조의 회로 기판의 사시도이다.4 is a perspective view of a circuit board of a multilayer structure according to an embodiment of the present invention.
도 5, 6, 7은 본 발명의 실시예와 대비하기 위한 종래의 2층 구조의 회로 기판의 예시를 나타낸다.5, 6, and 7 show examples of a conventional two-layer circuit board for comparison with an embodiment of the present invention.
도 8은 본 발명의 실시예에 따른 다층 구조와 종래의 이층 구조의 회로 폭을 비교하기 위한 도면이다.8 is a view for comparing the circuit width of a multilayer structure according to an embodiment of the present invention and a conventional two-layer structure.
도 9는 본 발명의 실시예에 따른 투명 디스플레이 장치를 제조하는 공정을 도시한 순서도이다.9 is a flowchart illustrating a process of manufacturing a transparent display device according to an embodiment of the present invention.
이하, 실시예들을 첨부된 도면을 참조하여 상세하게 설명한다. 그러나, 특허출원의 범위가 이러한 실시예들에 의해 제한되거나 한정되는 것은 아니다. 각 도면에 제시된 동일한 참조 부호는 동일한 부재를 나타낸다. Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference numerals in the drawings denote like elements.
또한, 첨부 도면을 참조하여 설명함에 있어, 도면 부호에 관계없이 동일한 구성 요소는 동일한 참조 부호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다. 실시예를 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 실시예의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생략한다.In addition, in the description with reference to the accompanying drawings, the same components regardless of reference numerals will be given the same reference numerals and redundant description thereof will be omitted. In the following description of the embodiment, if it is determined that the detailed description of the related known technology may unnecessarily obscure the gist of the embodiment, the detailed description thereof will be omitted.
명세서 전체에서, 어떤 부분이 어떤 구성요소를 "포함"한다고 할 때, 이는 특별히 반대되는 기재가 없는 한 다른 구성요소를 제외하는 것이 아니라 다른 구성요소를 더 포함할 수 있는 것을 의미한다. 또한, 명세서에 기재된 "…부", "…기", "모듈" 등의 용어는 적어도 하나의 기능이나 동작을 처리하는 단위를 의미하며, 이는 하드웨어나 소프트웨어 또는 하드웨어 및 소프트웨어의 결합으로 구현될 수 있다.Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, except to exclude other components unless specifically stated otherwise. In addition, the terms “… unit”, “… unit”, “module”, and the like described in the specification mean a unit that processes at least one function or operation, which may be implemented by hardware or software or a combination of hardware and software. have.
이제, 도면을 참조하여 본 발명의 실시예에 따른 투명 디스플레이 장치, 그리고 그 제조 방법의 구성에 대해 설명한다.Now, a configuration of a transparent display device and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the drawings.
본 발명은 복수의 회로 기판에 각각 형성된 회로 패턴 중 적어도 일부의 회로패턴이, 각 회로 기판이 상하로 중첩되었을 때, 하부 회로기판의 회로패턴이 상부 회로기판의 회로패턴에 의하여 시각적으로 은폐되도록 배치되도록 구성된 것을 특징으로 한다. According to an embodiment of the present invention, circuit patterns of at least a portion of circuit patterns respectively formed on a plurality of circuit boards are visually concealed by circuit patterns of the upper circuit board when the circuit boards are overlapped up and down. It is characterized in that configured to.
예를 들어 상부 회로 기판에 형성된 어느 회로 패턴의 X, Y 좌표와 동일한 좌표의 하부 회로 기판 일 지점에 상부 회로 기판의 회로 패턴과 동일한 회로 패턴을 구현하게 되면, 사이니지의 완성을 위하여 상부 회로 기판과 하부 회로 기판을 중첩하게 되면 회로 패턴이 중첩되어 상부에서 하부를 향하는 시각 방향 기준으로 하부 회로 기판의 회로 패턴이 상부 회로 기판의 회로 패턴에 은폐되어 보이지 않게 된다. For example, if a circuit pattern identical to the circuit pattern of the upper circuit board is implemented at one point of the lower circuit board having the same coordinates as the X and Y coordinates of the circuit pattern formed on the upper circuit board, the upper circuit board is completed for signage. When the circuit board overlaps with the lower circuit board, the circuit pattern of the lower circuit board is concealed from the circuit pattern of the upper circuit board so that the circuit pattern overlaps and is visually seen from the top to the bottom.
이 때, 전제가 있는데, 복수의 회로 기판 각각의 회로 패턴의 총 면적과 동일한 총 면적의 회로 패턴을 단일의 회로 기판에 형성하였다는 점이다. 이 때, 복수의 회로 기판과 단일의 회로 기판을 비교하면, 복수의 회로 기판에 회로 패턴이 형성된 경우에 있어 단일의 회로 기판에 회로 패턴이 형성된 경우에 비하여 더 넓은 투명영역이 확보될 수 있으며, 궁극적으로 사이니지의 투명성을 높일 수 있게 된다. At this time, there is a premise that a circuit pattern having a total area equal to the total area of each circuit pattern of the plurality of circuit boards is formed on a single circuit board. In this case, when a plurality of circuit boards and a single circuit board are compared, a wider transparent area may be secured than when a circuit pattern is formed on a single circuit board when a circuit pattern is formed on a plurality of circuit boards. Ultimately, signage transparency can be increased.
즉, 본 발명은 단일의 회로 기판에 무리하게 조밀한 회로 패턴을 형성함으로써 위 회로 패턴으로 인하여 사이니지의 투명성이 저하되는 문제점을 해결하기 위한 것이다.That is, the present invention is to solve the problem that the transparency of the signage due to the above circuit pattern by forming an excessively dense circuit pattern on a single circuit board.
물론, 각 기판간 회로 패턴이 상하 동일한 패턴이 되는 것으로써 설명하였으나, 상하 유사한 패턴일 수도 있다. 즉, 회로 패턴을 복수의 회로 패턴에 분산 배치하면서 그 과정에서 투명성을 확보하도록 하였다는 점이 본 발명의 요지이다.Of course, although the circuit pattern between each board | substrate became the up-and-down same pattern, it demonstrated, but it may be a similar pattern up-down. That is, the gist of the present invention is that transparency is ensured in the process while distributing the circuit patterns in a plurality of circuit patterns.
도 1은 본 발명의 실시예가 적용되는 투명 디스플레이 장치의 분해 사시도이고, 도 2는 본 발명의 실시예를 설명하기 위한 도면이다.1 is an exploded perspective view of a transparent display device to which an embodiment of the present invention is applied, and FIG. 2 is a view for explaining an embodiment of the present invention.
도 1을 참조하면, 투명 디스플레이 장치(100)는 투명 기판(101) 및 제어부(103)를 포함한다. 투명 기판(101)은 투명한 연성(Flexible) 소재로 이루어지고, 회로 패턴(105)이 인쇄된 인쇄회로기판(PCB, Printed Circuit Board)이다. 투명 기판(101)은 예를 들어, PI(polyimide), PET(polyethylene terephthalate), PC(Polycarbonate) 중 적어도 하나의 투명 필름 소재일 수 있다. 다만, 투명 필름 소재는 위 재질로만 한정되는 것은 아님은 자명하다. 투명 기판(101)은 투명 필름 소재에 증착 방식으로 형성된 동박면을 노광 및 에칭함으로써 회로 패턴(105)이 형성될 수 있다. 회로패턴은 인쇄회로기판의 일면 또는 양면에 모두 형성될 수 있다. 양면에 형성되는 경우 보다 밀집한 회로패턴을 형성할 수 있으므로 바람직하다.Referring to FIG. 1, the transparent display apparatus 100 includes a transparent substrate 101 and a controller 103. The transparent substrate 101 is made of a transparent flexible material and is a printed circuit board (PCB) on which a circuit pattern 105 is printed. The transparent substrate 101 may be, for example, at least one transparent film material of polyimide (PI), polyethylene terephthalate (PET), and polycarbonate (PC). However, it is obvious that the transparent film material is not limited to the above materials. The circuit pattern 105 may be formed on the transparent substrate 101 by exposing and etching a copper foil surface formed by a deposition method on a transparent film material. The circuit pattern may be formed on one side or both sides of the printed circuit board. When formed on both sides, it is preferable because a more dense circuit pattern can be formed.
투명 기판(101)에는 복수의 발광소자(미도시)가 장착되며, 발광소자(미도시)는 RGB LED(Light-emitting diode)일 수 있다.A plurality of light emitting devices (not shown) may be mounted on the transparent substrate 101, and the light emitting devices (not shown) may be RGB light-emitting diodes (LEDs).
투명 기판(101)의 회로 패턴(105)은 투명 케이블(107)과 연결되고, 케이블(107)은 커넥터(109)와 연결되며, 커넥터(109)는 제어부(103)와 연결된다. 즉, 발광소자(미도시)가 장착된 회로 패턴(105)은 케이블(107) 및 커넥터(109)를 통해 제어부(103)와 연결된다. 제어부(103)는 회로 패턴(105)에 전원 신호, 구동 신호 등의 제어 신호를 출력하는 구성으로서, 구동 Driver IC 등을 포함한다.The circuit pattern 105 of the transparent substrate 101 is connected to the transparent cable 107, the cable 107 is connected to the connector 109, and the connector 109 is connected to the controller 103. That is, the circuit pattern 105 on which the light emitting device (not shown) is mounted is connected to the controller 103 through the cable 107 and the connector 109. The control part 103 is a structure which outputs control signals, such as a power signal and a drive signal, to the circuit pattern 105, and contains a drive driver IC.
복수의 RGB LED는 공통(Common) 단자를 포함한 4개의 단자로 이루어진다. 따라서, 도 2와 같이 종래에 단층 또는 3개 미만의 층으로 구성되는 기판의 경우, 커넥터 또는 IC(Integrated Circuit)에 근접할수록 회로패턴의 밀집도가 높아질 수밖에 없으므로, 투명도가 떨어진다. The plurality of RGB LEDs consists of four terminals including a common terminal. Therefore, in the case of a substrate conventionally composed of a single layer or less than three layers, as shown in FIG. 2, the closer the connector or integrated circuit (IC) is, the higher the density of the circuit pattern is, and thus the transparency is inferior.
따라서, 본 발명의 실시예에서는 투명 기판(101)은 적어도 3개층(layer)으로 구성된 다층 구조이며, 이에 대해 설명하면, 다음과 같다.Therefore, in the embodiment of the present invention, the transparent substrate 101 has a multilayer structure composed of at least three layers.
도 3은 본 발명의 실시예에 따른 회로 기판의 다층 구조를 도시한 사시도이고, 도 4는 본 발명의 실시예에 따른 다층 구조의 회로 기판의 사시도이고, 도 5, 6, 7은 본 발명의 실시예와 대비하기 위한 종래의 2층 구조의 회로 기판의 예시를 나타내며, 도 8은 본 발명의 실시예에 따른 다층 구조와 종래의 이층 구조의 회로 폭을 비교하기 위한 도면이다.3 is a perspective view illustrating a multilayer structure of a circuit board according to an embodiment of the present invention, FIG. 4 is a perspective view of a circuit board having a multilayer structure according to an embodiment of the present invention, and FIGS. 5, 6, and 7 are views of the present invention. An example of a circuit board having a conventional two-layer structure for comparison with an embodiment is shown, and FIG. 8 is a view for comparing a circuit width of a multilayer structure and a conventional two-layer structure according to an embodiment of the present invention.
먼저, 도 3을 참조하면, 회로 기판(101)은 제1층 기판(101-1), 제2층 기판(101-3), 제3층 기판(101-5) 및 제4 층 기판(101-7)으로 구성된다. First, referring to FIG. 3, the circuit board 101 includes a first layer substrate 101-1, a second layer substrate 101-3, a third layer substrate 101-5, and a fourth layer substrate 101. -7).
각 층 별 기판(101-1, 101-3, 101-5, 101-7)에는 각각의 인쇄회로패턴(105-1, 105-3, 105-5, 105-7)이 인쇄되어 있다. 그리고 각 층 별 기판(101-1, 101-3, 101-5, 101-7)을 광학용 접착소재로 결합하여 하나의 기판(101)으로 형성하면, 도 4와 같다. Each printed circuit pattern 105-1, 105-3, 105-5, and 105-7 is printed on the substrates 101-1, 101-3, 101-5, and 101-7 for each layer. When the substrates 101-1, 101-3, 101-5, and 101-7 for each layer are combined with an optical adhesive material to form a single substrate 101, as shown in FIG. 4.
광학용 접착소재는 투명한 양면 테이프 타입의 OCA(optically clear adhesive)와 투명한 액체 타입의 OCR(optically clear resin) 중에서 채택될 수 있다. 이때, 접착은 풀 라미네이션(full lamination) 방식이 사용될 수 있다.Optical adhesive materials may be employed among the optically clear adhesive (OCA) of the transparent double-sided tape type and the optically clear resin (OCR) of the transparent liquid type. In this case, the full lamination method may be used for adhesion.
이처럼, 다층 구조의 회로 기판(101)을 종래의 방식과 비교하면, 도 5와 같이, 2층의 기판을 도 6과 같이 하나의 기판으로 접합할 수 있다. 이런 경우, 도 7에 보인 바와 같이, 그 투명도는 도 1에 비해 떨어짐을 알 수 있다.As described above, when the circuit board 101 having a multi-layer structure is compared with the conventional method, two substrates can be joined to one substrate as shown in FIG. In this case, as shown in FIG. 7, it can be seen that the transparency is inferior to FIG.
도 8의 (a)는 2층 구조의 회로 기판(101)의 회로 폭을 도시한 것으로서, 회로 폭이 3.20mm ~ 3.50mm정도이다. 반면, 도 8의 (b)는 본 발명의 실시예에 따른 다층 구조의 회로 기판(101)의 회로 폭을 도시한 것으로서, 회로 폭이 1.31mm~2mm이다. 이처럼, 다층 구조의 회로 기판(101)의 회로면적은 이층 구조에 대비할 때, 대략 43~59%로 감소을 알 수 있다. 이처럼, 층 추가를 통해 50% 전/후의 회로 면적 감소의 효과가 예상되며 이로 인하여 투과도가 증가한다. 즉, 상기 회로 패턴의 회로 폭은 다층을 이루는 회로 기판의 숫자가 많아질수록 감소되는 것이 바람직하다. 그래야 보다 더 많은 투명 영역이 확보될 수 있는 것이다. FIG. 8A shows the circuit width of the circuit board 101 having a two-layer structure, and the circuit width is about 3.20 mm to 3.50 mm. On the other hand, Figure 8 (b) shows the circuit width of the circuit board 101 of the multilayer structure according to the embodiment of the present invention, the circuit width is 1.31mm ~ 2mm. As such, it can be seen that the circuit area of the circuit board 101 of the multilayer structure is reduced to approximately 43 to 59% when compared to the two-layer structure. As such, the effect of circuit area reduction of 50% before and after through layer addition is expected, thereby increasing transmission. That is, the circuit width of the circuit pattern is preferably reduced as the number of circuit boards forming a multilayer increases. That way, more transparent areas can be secured.
다만, 이와 같이 회로 폭의 감축만으로는 투명도 확보에 대한 실효성을 거두기가 용이하지 않으므로 각 회로 기판(101)의 각 층에 형성된 회로 패턴을 상하 동일하게 하고, 그 회로 패턴이 상부 회로 기판의 시각에서 볼 때, 하부 회로 기판의 회로 패턴과 상하로 중첩되어 상부 회로 기판의 회로 패턴에 의하여 하부 회로 기판의 회로 패턴이 은폐되도록 구성되면 회로 기판 중 투명 영역의 면적이 보다 더 많이 확보되므로 그만큼 사이니지의 투명성이 더욱 확보될 수 있어 본 발명의 취지에 부합된다. However, it is not easy to achieve the effectiveness of securing transparency only by reducing the circuit width. Thus, the circuit patterns formed on the layers of each circuit board 101 are made the same up and down, and the circuit patterns are viewed from the upper circuit board. At this time, when the circuit pattern of the lower circuit board is concealed by overlapping the circuit pattern of the lower circuit board up and down and the circuit pattern of the upper circuit board, the area of the transparent area of the circuit board is more secured. This can be further secured to meet the spirit of the present invention.
즉, 예를 들어 상부 회로 기판과 하부 회로 기판의 동일한 영역에 동일한 회로 패턴을 구현하고, 그 회로 패턴이 서로 중첩되되, 상부에서 시각적으로 보았을 때, 하부의 회로 패턴이 전혀 안보이도록(은폐되도록) 구성하면 그 만큼 회로 기판의 투명 영역이 넓어지는 효과가 있는 것이다. That is, for example, to implement the same circuit pattern in the same area of the upper circuit board and the lower circuit board, the circuit patterns overlap each other, so that when viewed from the top visually, the lower circuit pattern is completely invisible (hidden) If it constitutes, the transparent area of a circuit board will increase by that much.
다만, 상하 회로 기판의 동일한 영역에 동일한 패턴이 반드시 구현되어야 하는 것은 아니다. 즉, 동일한 패턴이 형성된 상부 회로 기판과 하부 회로 기판의 영역이 다소간 불일치하더라도 이는 상하 회로기판의 중첩 위치를 조정하여 동일 패턴이 상하로 중첩되도록 구성할 수도 있으므로, 위와 같이 한정되지는 않는다. However, the same pattern is not necessarily implemented in the same region of the upper and lower circuit boards. That is, even if the regions of the upper circuit board and the lower circuit board on which the same pattern is formed are somewhat inconsistent, this may be configured to adjust the overlapping positions of the upper and lower circuit boards so that the same patterns overlap the upper and lower sides, but are not limited thereto.
도 9는 본 발명의 실시예에 따른 투명 디스플레이 장치를 제조하는 공정을 도시한 순서도이다.9 is a flowchart illustrating a process of manufacturing a transparent display device according to an embodiment of the present invention.
도 9를 참조하면, 1층 회로 기판(101-1)과 2층 회로 기판(101-3)에 스루홀을 가공(S101)하고, 3층 회로 기판(101-5)과 4층 회로 기판(101-7)에 스루홀을 가공한다(S103).Referring to FIG. 9, through-holes are processed (S101) in the one-layer circuit board 101-1 and the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board ( 101-7) through holes are processed (S103).
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)의 각 스루홀이 통전되도록 동도금으로 도금층을 형성한다(S105).Plating layer made of copper plating so that each through hole of the one-layer circuit board 101-1 and the two-layer circuit board 101-3 and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 is energized. To form (S105).
2층 회로 기판(101-3) 과 3층 회로 기판(101-5)에 각각의 인쇄회로패턴(105-3, 105-5)를 형성한다(S107). Printed circuit patterns 105-3 and 105-5 are formed on the two-layer circuit board 101-3 and the three-layer circuit board 101-5 (S107).
1층 회로 기판(101-1)과 2층 회로 기판(101-3)이 결합된 회로 기판의 한쪽면또는 3층 회로 기판(101-5)과 4층 회로 기판(101-7)이 결합된 회로 기판의 한쪽면을 OCA 또는 OCR로 라미네이팅(Laminating)하여, 결합한다(S109). 이때, 접착층은 패턴 높이의 2~3배 두께가 될 수 있다. 그리고 50~80도, 압력 5~20kg/cm2로 압력을 가하여 결합을 견고히할 수 있다.One side of the circuit board on which the one-layer circuit board 101-1 and the two-layer circuit board 101-3 are coupled or the three-layer circuit board 101-5 and the four-layer circuit board 101-7 are coupled. One side of the circuit board is laminated by laminating with OCA or OCR and bonded (S109). At this time, the adhesive layer may be two to three times the thickness of the pattern height. And 50 to 80 degrees, pressure 5 ~ 20kg / cm2 can be applied to strengthen the bond.
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)을 전체적으로 관통하는 스루홀을 가공(S111)한후, 전 회로층이 도통이 될 수 있도록 각 스루홀에 전도성 페이스트로 홀플러깅후 경화를 한다(S113). The through-holes penetrating through the one-layer circuit board 101-1 and the two-layer circuit board 101-3 and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 are processed (S111). ), And then hardened after hole plugging with conductive paste in each through hole so that the entire circuit layer can be conductive (S113).
기존의 1층 및 4층의 동박면과 홀플러깅 경계면의 접지력을 향상 시키기 위해 전체적인 동도금을 실시한다(S115). 이 순서는 선택적으로 시행할 수 있다.Overall copper plating is performed to improve the grounding force of the existing copper foil surface and hole plugging interface of the first and fourth layers (S115). This order can be implemented optionally.
가장 바깥층에 위치한 1층 회로 기판(101-1)과 4층 회로 기판(101-7)에 각각의 인쇄회로패턴(105-1, 105-7)을 형성한다(S117).Each of the printed circuit patterns 105-1 and 105-7 is formed on the one-layer circuit board 101-1 and the four-layer circuit board 101-7 positioned at the outermost layer (S117).
1층 회로 패턴(105-1)과 4층 회로 패턴(107-7)에 TIN 도금을 실시한다(S119)TIN plating is performed on the one-layer circuit pattern 105-1 and the four-layer circuit pattern 107-7 (S119).
그리고 가장 바깥층에 위치한 1층 회로 기판(101-1)과 4층 회로 기판(101-7)의 외부면에 투명 솔더 레지스트를 인쇄한 후 경화한다(S121). 이 순서는 선택적으로 시행할 수 있다. Then, the transparent solder resist is printed on the outer surfaces of the one-layer circuit board 101-1 and the four-layer circuit board 101-7 positioned at the outermost layer and then cured (S121). This order can be implemented optionally.
전체 회로의 도통검사 후 외형을 가공(S123)한다. After the conduction test of the entire circuit to process the appearance (S123).
이상에서 설명한 본 발명의 실시예는 장치 및 방법을 통해서만 구현이 되는 것은 아니며, 본 발명의 실시예의 구성에 대응하는 기능을 실현하는 프로그램 또는 그 프로그램이 기록된 기록 매체를 통해 구현될 수도 있다. The embodiments of the present invention described above are not only implemented through the apparatus and the method, but may also be implemented through a program for realizing a function corresponding to the configuration of the embodiments of the present invention or a recording medium on which the program is recorded.
이상에서 본 발명의 실시예에 대하여 상세하게 설명하였지만 본 발명의 권리범위는 이에 한정되는 것은 아니고 다음의 청구범위에서 정의하고 있는 본 발명의 기본 개념을 이용한 당업자의 여러 변형 및 개량 형태 또한 본 발명의 권리범위에 속하는 것이다.Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.
Claims (10)
1층 회로 기판(101-1)과 2층 회로 기판(101-3)에 스루홀을 가공(S101)하고, 3층 회로 기판(101-5)과 4층 회로 기판(101-7)에 스루홀을 가공하는 제1단계;Through-holes are processed in the one-layer circuit board 101-1 and the two-layer circuit board 101-3 (S101), and through-through the three-layer circuit board 101-5 and the four-layer circuit board 101-7. A first step of processing holes;
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)의 각 스루홀을 동도금(S105)하여 각 스루홀이 통전되도록하는 제2단계;Each through hole of the one-layer circuit board 101-1, the two-layer circuit board 101-3, and the three-layer circuit board 101-5 and the four-layer circuit board 101-7 is copper plated (S105). A second step of allowing each through hole to be energized;
2층 회로 기판(101-3) 과 3층 회로 기판(101-5)에 각각의 인쇄회로패턴(105-3, 105-5)를 형성하는 제3단계;A third step of forming respective printed circuit patterns 105-3 and 105-5 on the two-layer circuit board 101-3 and the three-layer circuit board 101-5;
1층 회로 기판(101-1)과 2층 회로 기판(101-3)이 결합된 회로 기판의 한쪽면 또는 3층 회로 기판(101-5)과 4층 회로 기판(101-7)이 결합된 회로 기판의 한쪽면을 라미네이팅(Laminating)하여, 결합하는 제4단계;One side of the circuit board on which the one-layer circuit board 101-1 and the two-layer circuit board 101-3 are coupled or the three-layer circuit board 101-5 and the four-layer circuit board 101-7 are coupled. A fourth step of laminating and bonding one side of the circuit board;
1층 회로 기판(101-1)과 2층 회로 기판(101-3), 그리고 3층 회로 기판(101-5)과 4층 회로 기판(101-7)을 전체적으로 관통하는 스루홀을 가공하는 제5단계;The agent which processes through-hole which penetrates the 1-layer circuit board 101-1 and the 2-layer circuit board 101-3, and the 3-layer circuit board 101-5 and the 4-layer circuit board 101-7 as a whole. Step 5;
전 회로층이 도통이 될 수 있도록 각 스루홀에 전도성 페이스트로 홀플러깅후 경화를 하는 제6단계;A sixth step of hardening after hole plugging with a conductive paste in each through hole so that the entire circuit layer is conductive;
1층 회로 기판(101-1)과 4층 회로 기판(101-7)에 각각의 인쇄회로패턴(105-1, 105-7)을 형성하는 제7단계;A seventh step of forming printed circuit patterns 105-1 and 105-7 on the one-layer circuit board 101-1 and the four-layer circuit board 101-7;
1층 회로 패턴(105-1)과 4층 회로 패턴(107-7)에 TIN 도금을 실시하는 제8단계;An eighth step of applying TIN plating to the one-layer circuit pattern 105-1 and the four-layer circuit pattern 107-7;
전체 회로의 도통검사 후 외형을 가공하는 제9단계;A ninth step of processing the appearance after the conduction inspection of the entire circuit;
를 포함하되,Including but not limited to:
각 층의 인쇄회로패턴을 선폭 및 패턴상 서로 동일하게 구현하여 각 회로 기판이 상하로 중첩되었을 때, 하부 회로기판의 인쇄회로패턴 전체가 상부 회로기판의 인쇄회로패턴에 의하여 시각적으로 은폐되도록 배치 및 구성되고,The printed circuit patterns of each layer are implemented in the same width and pattern, so that when each circuit board is overlapped up and down, the entire printed circuit pattern of the lower circuit board is visually concealed by the printed circuit pattern of the upper circuit board. Composed,
복수의 회로 기판 각각의 인쇄회로패턴의 총 면적과 동일한 총 면적의 인쇄회로패턴을 복수의 회로 기판에 형성함으로써 상대적으로 더 넓은 투명영역이 확보되도록 하며, 상기 인쇄회로패턴의 회로 폭은 다층을 이루는 회로 기판의 숫자가 많아질수록 감소되는 것을 특징으로 하는 투명 디스플레이 장치의 제조방법.By forming a printed circuit pattern having a total area equal to the total area of each printed circuit pattern of the plurality of circuit boards on the plurality of circuit boards, a relatively wider transparent area is ensured, and the circuit width of the printed circuit pattern forms a multilayer. A method of manufacturing a transparent display device, characterized in that it decreases as the number of circuit boards increases.
제1항에서,In claim 1,
제6단계 이후에 After step six
기존의 1층 및 4층의 동박면과 홀플러깅 경계면의 접지력을 향상 시키기 위해 전체적인 동도금을 실시하는 단계;Performing overall copper plating to improve the grounding force of the existing copper foil surface and hole plugging interface of the first and fourth layers;
를 더 포함하는, 투명 디스플레이 장치의 제조방법.Further comprising, a method of manufacturing a transparent display device.
제1항에서,In claim 1,
제8단계 이후에After step 8
1층 회로 기판(101-1)과 4층 회로 기판(101-7)의 외부면에 투명 솔더 레지스트를 인쇄한 후 경화하는 제9단계;A ninth step of printing the transparent solder resist on the outer surfaces of the one-layer circuit board 101-1 and the four-layer circuit board 101-7 and curing the printed circuit board;
를 더 포함하는, 투명 디스플레이 장치의 제조방법.Further comprising, a method of manufacturing a transparent display device.
제1항에서,In claim 1,
제4단계는, OCA 또는 OCR로 라미네이팅하는, 투명 디스플레이 장치의 제조방법.The fourth step is a method of manufacturing a transparent display device, laminating with OCA or OCR.
적어도 일측면에 회로 패턴이 형성되고 플렉시블 합성수지 재질로 형성된 다층 구조의 복수의 회로 기판, A plurality of circuit boards having a multilayered pattern formed on at least one side thereof and formed of a flexible synthetic resin material;
상기 복수의 회로 기판 중 가장 최상위 계층의 회로 기판에 탑재되는 발광 소자, 그리고A light emitting element mounted on a circuit board of the highest layer among the plurality of circuit boards, and
상기 회로 기판과 연결되어 상기 발광 소자를 구동하는 제어부를 포함하고,A control unit connected to the circuit board to drive the light emitting device;
상기 복수의 회로 기판은,The plurality of circuit boards,
접착 소재를 통해 접합되어 하나의 기판으로 형성되고, Bonded through an adhesive material to form a single substrate,
상기 회로 패턴은,The circuit pattern,
층 별로 서로 도통하도록 형성되며,Each layer is formed to be in contact with each other,
상기 복수의 회로 기판에 각각 형성된 회로 패턴 중 적어도 일부의 회로패턴은 각 회로 기판이 상하로 중첩되었을 때, 하부 회로기판의 적어도 일부의 회로패턴이 상부 회로기판의 적어도 일부의 회로패턴에 의하여 시각적으로 은폐되도록 배치 및 구성되고,The circuit patterns of at least some of the circuit patterns respectively formed on the plurality of circuit boards are visually displayed by at least a portion of the circuit patterns of the upper circuit board when the circuit boards overlap each other. Arranged and configured to conceal,
복수의 회로 기판 각각의 회로 패턴의 총 면적과 동일하거나 유사한 총 면적의 회로 패턴을 단일의 회로 기판에 형성하였을 때와 비교하여 복수의 회로 기판에 회로패턴을 형성함으로써 상대적으로 더 넓은 투명영역이 확보되는, 투명 디스플레이 장치.A relatively wider transparent area is secured by forming circuit patterns on a plurality of circuit boards as compared to when a circuit pattern having a total area equal to or similar to the total area of each circuit pattern on a plurality of circuit boards is formed on a single circuit board. , Transparent display device.
제1항에서,In claim 1,
상기 회로 패턴은,The circuit pattern,
각 층 별 기판에 형성된 스루홀(thru-hole)을 통해 전기적으로 연결되는, 투명 디스플레이 장치.A transparent display device electrically connected through a through-hole formed in a substrate for each layer.
제6항에서,In claim 6,
상기 회로 패턴은,The circuit pattern,
1층 회로 기판, 2층 회로 기판, 3층 회로 기판, 4층 회로 기판으로 구성되고,상기 1층 회로 기판과 2층 회로 기판에 형성된 스루홀에는 동도금이 이루어지고, 3층 회로 기판과 4층 회로 기판에 형성된 스루홀에도 동도금이 이루어지며, 동도금이 이루어진 모든 회로기판을 전체적으로 관통하는 스루홀을 가공한후, 전 회로층이 도통이 될 수 있도록 각 스루홀에 전도성 페이스트로 홀플러깅후 경화를하여 형성되는, 투명 디스플레이 장치.Comprising a one-layer circuit board, a two-layer circuit board, a three-layer circuit board, a four-layer circuit board, copper plating is performed in the through holes formed in the one-layer circuit board and the two-layer circuit board, and the three-layer circuit board and the four-layer Copper plating is also applied to the through-holes formed in the circuit board. After through-holes are processed through all the circuit boards formed with copper plating, hardening is performed after hole plugging with conductive paste in each through-hole so that all circuit layers can be conducted. And a transparent display device.
제5항에서,In claim 5,
상기 회로 패턴은,The circuit pattern,
투명 필름 소재에 증착 방식으로 형성된 동박면을 노광 및 에칭하여 형성되는, 투명 디스플레이 장치.A transparent display device, formed by exposing and etching a copper foil surface formed by a vapor deposition method on a transparent film material.
제5항에서,In claim 5,
상기 복수의 회로 기판은,The plurality of circuit boards,
투명한 양면 테이프 타입의 OCA(optically clear adhesive)와 투명한 액체 타입의 OCR(optically clear resin) 중에서 선택된 라미네이션(lamination) 방식을 사용하여 서로 결합되는, 투명 디스플레이 장치.A transparent display device coupled to each other using a lamination method selected from an optically clear adhesive (OCA) of a transparent double-sided tape type and an optically clear resin (OCR) of a transparent liquid type.
제5항에서,In claim 5,
상기 회로 패턴의 회로 폭은 다층을 이루는 회로 기판의 숫자가 많아질수록 감소되는, 투명 디스플레이 장치.The circuit width of the circuit pattern decreases as the number of circuit boards forming a multilayer increases.
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| KR20080077423A (en) * | 2007-02-20 | 2008-08-25 | 삼성테크윈 주식회사 | Build-up printed-circuit board and method for producing thereof |
| KR102523482B1 (en) | 2016-06-15 | 2023-04-19 | 에스케이플래닛 주식회사 | Digital signage apparatus for, and control method thereof |
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| JP2002169490A (en) * | 2000-12-01 | 2002-06-14 | Minolta Co Ltd | Laminated display panel and display device |
| KR20030097665A (en) * | 2002-06-21 | 2003-12-31 | 아스라브 쏘시에떼 아노님 | Method for manufacturing a batch of multi-layered cells, such as liquid crystal display, or electrochemical photovoltaic cells |
| JP2012000771A (en) * | 2010-06-14 | 2012-01-05 | Fuji Xerox Co Ltd | Light emitting device, print head, and image forming apparatus |
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