WO2020024151A1 - 信息处理方法及装置、设备、*** - Google Patents
信息处理方法及装置、设备、*** Download PDFInfo
- Publication number
- WO2020024151A1 WO2020024151A1 PCT/CN2018/098040 CN2018098040W WO2020024151A1 WO 2020024151 A1 WO2020024151 A1 WO 2020024151A1 CN 2018098040 W CN2018098040 W CN 2018098040W WO 2020024151 A1 WO2020024151 A1 WO 2020024151A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- logical address
- physical address
- address set
- field
- physical
- Prior art date
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7201—Logical to physical mapping or translation of blocks or pages
Definitions
- the present application relates to the field of chip technology, and in particular, to an information processing method and device, device, and system.
- Memory chips generally include a controller and a flash array.
- static random access memory (SRAM) in the controller can be used to store the mapping relationship between logical addresses and physical addresses, also known as logical addresses. And physical address mapping table.
- SRAM static random access memory
- a universal flash storage (UFS) integrated on the system chip (SOC) side can be used to issue a UFS protocol information unit (UFS protocol).
- UFS protocol UFS protocol information unit
- UPIU information unit
- the request may include a read request, a write request, an erase request, and so on.
- SRAM has limited resources and often cannot store the full mapping table. Therefore, every time you look up the logical address and physical address mapping table, there is a high probability that it will fail to hit, and a multi-level lookup process will be required. For example, when performing a read request to find the logical address and physical address mapping table, if there is a miss, you need to download the logical address and physical address mapping table from flash to SRAM, and if the entry in SRAM is not enough, It will download other entries to the flash, so the low hit rate will lead to table overhead and table entry flash operations, which will seriously affect the response speed of read requests.
- the present application discloses an information processing method, device, device, and system, which can effectively improve the response speed of a read request.
- an embodiment of the present application provides an information processing method.
- the method is applied to a main chip connected to a universal flash memory UFS protocol information unit UPIU.
- the method includes:
- the main chip determines a first logical address set; the main chip generates first indication information; the main chip sends a first request to a memory chip connected to the main chip; wherein the first indication information includes all The first logical address set and the first physical address set corresponding to the first logical address set determined according to the mapping relationship between the logical address and the physical address, the first physical address set includes N physical addresses, and the N One physical address corresponds one-to-one with N logical addresses included in the first logical address set, where N is an integer greater than or equal to 2; the first request includes the first indication information.
- the response speed of the read request can be effectively improved;
- the first An indication information may be used to indicate a first physical address set, and the first physical address set includes at least two physical addresses. For example, in a case where a physical address corresponds to a 4KB read request, the implementation of the embodiment of the present application can implement 8KB, 16KB or even 32KB read requests, thus effectively realizing the efficiency of real-time information interaction between the main chip and the memory chip.
- the logical address may include a logical block address (LBA), and the physical address may include a physical page number (PPN).
- LBA logical block address
- PPN physical page number
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the storage chip by indicating the number of physical addresses in the first physical address set to the storage chip, the storage chip can clearly know the number of physical addresses included in the first physical address set, thereby obtaining To data, which further improves the efficiency of information interaction.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the main chip when the access chip granularity is not agreed in advance between the main chip and the storage chip, the main chip can indicate the access granularity to the storage chip, so that the storage chip can obtain how many physical addresses are in the first physical address set. byte.
- the method further includes: the main chip allocates an extension header field EHS extension field;
- the EHS extension domain is used to carry the first indication information.
- the main chip may include a UFS driver and a UFS controller, and the UFS driver is connected to the UFS controller; before the main chip sends a first request to a memory chip connected to the main chip, the The method further includes: the UFS driver allocates an extension header field EHS extension domain; the UFS driver sends the EHS extension domain to the UFS controller; wherein the EHS extension domain is used to carry the first indication information .
- an extension header field (EHS) extension field may include at least 2016B space, and the EHS extension field may be used to carry a UPIU request (command UPIU), that is, first indication information in the first request.
- UPIU request command UPIU
- the first instruction information sent by the main chip to the memory chip includes N physical addresses, thereby avoiding sending one physical address at a time, which results in inefficient information exchange. Therefore, by implementing the embodiment of the present application, the efficiency of information interaction between the main chip and the storage chip is effectively improved by using the EHS extension domain.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the method further includes: the main chip receives the first response message from the memory chip; wherein the first response message includes second indication information, and the first The two indication information include the first logical address set and the second physical address set; the second physical address set is a physical address corresponding to the first logical address set after the mapping relationship between the logical address and the physical address is updated Set; the second set of physical addresses includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the master chip receives the first logical address set and the second physical address set with the mapping relationship sent by the memory chip, so that the master chip can be updated in time.
- the mapping relationship between the logical address and the physical address stored in the master chip effectively improves the efficiency of the master chip in finding the physical address according to the logical address.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the second indication information is carried in the EHS extension domain.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- an embodiment of the present application further provides an information processing method.
- the method is applied to a storage chip connected to a universal flash memory UFS protocol information unit UPIU.
- the method includes:
- the memory chip receives a first request from a master chip connected to the memory chip; the memory chip obtains first data according to a first physical address set; the memory chip sends the first data to the master chip ;
- the first request includes first indication information
- the first indication information includes a first logical address set and a first physical address corresponding to the first logical address set determined according to a mapping relationship between a logical address and a physical address Address set
- the first physical address set includes N physical addresses
- the N physical addresses correspond to the N logical addresses included in the first logical address set, and the N is greater than or equal to 2 An integer
- the first data includes data stored in the first physical address set.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the method further includes: after the memory chip determines the logical address and physical address mapping When the relationship changes, a first response message is sent to the main chip; wherein the first response message includes second instruction information, and the second instruction information includes the first logical address set and a second physical information.
- An address set; the second physical address set is a physical address set corresponding to the first logical address set after a mapping relationship between a logical address and a physical address is changed; the second physical address set includes N physical addresses, and The N physical addresses are in one-to-one correspondence with the N logical addresses.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the second indication information is carried in the EHS extension domain.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- an embodiment of the present application further provides an information processing method, which is characterized in that the method is applied to a storage chip connected to a universal flash memory UFS protocol information unit UPIU, and the method includes:
- the memory chip receives a second request from a master chip connected to the memory chip; after the memory chip writes second data to the memory chip, a third request is generated according to the changed mapping relationship between the logical address and the physical address. Indication information; the memory chip sends a second response message of the second request to the main chip; wherein the second request includes a second logical address set and the second data; the second data Including data to be written into the memory chip; wherein the third indication information includes the second logical address set and a third physical address set corresponding to the second logical address set, and the third physical address
- the set includes M physical addresses, and the M physical addresses are in one-to-one correspondence with the M logical addresses included in the second logical address set, and the third physical address set is used to store the second data, so M is an integer greater than or equal to 3; wherein the second response message includes the third indication information, and the second response message is used to instruct to update the main chip Logical address and physical address mappings.
- the memory chip indicates at least three physical addresses to the main chip, so that when a large number of mapping relationships are updated in the memory chip, the main chip can be instructed to update the mapping relationships stored in the main chip in time, thereby improving The efficiency of updating the mapping relationship is improved, and the efficiency of real-time information exchange is improved.
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the third control information is carried in a third reserved field of a UPIU protocol frame.
- an embodiment of the present application further provides an information processing method.
- the method is applied to a main chip connected to a universal flash memory UFS protocol information unit UPIU.
- the method includes:
- the main chip receives a second response message from a memory chip connected to the main chip; the main chip updates a mapping relationship between a logical address and a physical address in the main chip according to the third instruction information;
- the second response message includes third indication information, the third indication information includes the second logical address set and a third physical address set corresponding to the second logical address set, and the third physical address set Including M physical addresses, and the M physical addresses are in one-to-one correspondence with the M logical addresses included in the second logical address set, and the third physical address set is used to store the second data, the M is an integer greater than or equal to 3.
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the third control information is carried in a third reserved field of a UPIU protocol frame.
- the method further includes: the main chip sends a second request to the storage chip ; Wherein the second request includes a second logical address set and second data, and the second data includes data to be written into the memory chip.
- an embodiment of the present application further provides an information processing method.
- the method is applied to a main chip connected to a universal flash memory UFS protocol information unit UPIU.
- the method includes:
- the main chip determines a first logical address set; the main chip generates first indication information; the main chip sends a first request to a memory chip connected to the main chip; wherein the first indication information includes all The first logical address set and the first physical address set corresponding to the first logical address set determined according to the mapping relationship between the logical address and the physical address, the first physical address set includes N physical addresses, and the N The one physical address corresponds to the N logical addresses included in the first logical address set, where N is an integer greater than or equal to 2; wherein the first request includes the first indication information.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first request includes a read request.
- the method further includes: the main chip receives a first response message from the storage chip; wherein The first response message includes second indication information, and the second indication information includes the first logical address set and the second physical address set; and the second physical address set is an update of the mapping relationship between the logical address and the physical address.
- a physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field
- the fourth field is used to indicate an access granularity of each physical address in the second physical address set
- the fourth field is used to indicate an access granularity of each logical address in the first logical address
- the fourth field is used to indicate a sum of an access granularity of each physical address in the second physical address set and an access granularity of each logical address in the first logical address; wherein the second physical address
- the access granularity of each physical address in the address set is the same as the access granularity of each logical address in the first logical address.
- the method further includes: the main chip sends a second request to the memory chip; and the main chip receives a second response message from the memory chip; the main chip Update the mapping relationship between the logical address and the physical address in the main chip according to the third instruction information; wherein the second request includes a second logical address set and second data, and the second data includes the data to be written into the Data of a memory chip; wherein the second response message includes third indication information, and the third indication information includes a second logical address set and a third physical address set corresponding to the second logical address set, so
- the third physical address set includes M physical addresses, and the M physical addresses are in one-to-one correspondence with the M logical addresses included in the second logical address set, and the third physical address set is used to store the In the second data, M is an integer greater than or equal to 3.
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the second request includes a write request.
- the method further includes: the main chip allocates an extension header field EHS extension field;
- the EHS extension domain is used to carry the first indication information.
- the EHS extension domain is further configured to carry the second indication information.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- the main chip includes a UFS driver and a UFS controller, and the UFS driver is connected to the UFS controller; before the main chip sends a first request to a storage chip connected to the main chip, the method It also includes: the UFS driver allocates an extension header field EHS extension domain; the UFS driver sends the EHS extension domain to the UFS controller.
- an embodiment of the present application further provides an information processing method.
- the method is applied to a universal flash memory storage chip connected to a UFS protocol information unit UPIU.
- the method includes:
- the memory chip receives a first request from a master chip connected to the memory chip; the memory chip obtains first data according to the first physical address set; the memory chip sends the first data to the master chip.
- Data wherein the first request includes first indication information, and the first indication information includes a first logical address set and a first logical address set corresponding to the first logical address set determined according to a mapping relationship between the logical address and the physical address.
- a physical address set, and the first physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses included in the first logical address set, and the N is greater than or equal to An integer of 2; wherein the first data includes data stored in the first physical address set.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the first request includes a read request.
- the method further includes: after the memory chip determines the logical address and physical address mapping When the relationship changes, a first response message is sent to the main chip; wherein the first response message includes second instruction information, and the second instruction information includes the first logical address set and a second physical information.
- An address set; the second physical address set is a physical address set corresponding to the first logical address set after a mapping relationship between a logical address and a physical address is changed; the second physical address set includes N physical addresses, and The N physical addresses are in one-to-one correspondence with the N logical addresses.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the method further includes: the memory chip receives a second request from a master chip connected to the memory chip; after the memory chip writes second data to the memory chip Generating third indication information according to the changed mapping relationship between the logical address and the physical address; the storage chip sends a second response message of the second request to the main chip;
- the second request includes a second logical address set and the second data; the second data includes data to be written into the memory chip; and the third indication information includes the second A logical address set and a third physical address set corresponding to the second logical address set, the third physical address set includes M physical addresses, and the M physical addresses and the second logical address set include M logical addresses correspond one-to-one, and the third physical address set is used to store the second data, where M is an integer greater than or equal to 3; wherein the second response message includes the third indication Information, and the second response message is used to instruct to update a mapping relationship between a logical address and a physical address in the master chip.
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the second request includes a write request.
- the third indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the third control information is carried in a third reserved field of the UPIU protocol frame.
- an embodiment of the present application provides a main chip that can be used to execute the method described in the first aspect.
- the main chip is connected to a universal flash memory UFS protocol information unit UPIU.
- the main chip includes:
- a determining unit is configured to determine a first logical address set; a generating unit is configured to generate first instruction information; wherein the first instruction information includes the first logical address set and a value determined according to a mapping relationship between a logical address and a physical address A first physical address set corresponding to the first logical address set, the first physical address set includes N physical addresses, and the N physical addresses and the N logical addresses included in the first logical address set One-to-one correspondence, the N is an integer greater than or equal to 2; the sending unit is configured to send a first request to a memory chip connected to the main chip; wherein the first request includes the first indication information.
- the first indication information further includes a mapping relationship between the N logical addresses and the N physical addresses, where one logical address corresponds to one physical address.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the main chip further includes: an allocation unit configured to allocate an extension header field EHS extension domain; wherein the EHS extension domain is used to carry the first indication information.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the main chip further includes: a receiving unit, configured to receive the first response message from the memory chip; wherein the first response message includes second indication information, and The second instruction information includes the first logical address set and the second physical address set; the second physical address set is a physical address corresponding to the first logical address set after the mapping relationship between the logical address and the physical address is updated; Set; the second set of physical addresses includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the second indication information is carried in the EHS extension domain.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- an embodiment of the present application provides a memory chip that can be used to implement the implementation manner described in the second aspect.
- the memory chip is connected to a universal flash memory UFS protocol information unit UPIU.
- the memory chip includes a receiving unit For receiving a first request from a master chip connected to the memory chip; wherein the first request includes first instruction information, and the first instruction information includes a first logical address set and a logical address and a physical address according to the logical address and the physical address; A first physical address set corresponding to the first logical address set determined by an address mapping relationship, and the first physical address set includes N physical addresses, and the N physical addresses and the first logical address set include The N logical addresses correspond one-to-one, where N is an integer greater than or equal to 2; an obtaining unit is configured to obtain first data according to the first physical address set; wherein the first data includes the first Data stored in a physical address set; a sending unit, configured to send the first data to the main chip.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first request is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the sending unit is further configured to send a first response message to the main chip when it is determined that the mapping relationship between the logical address and the physical address has changed; wherein the first A response message includes second indication information, and the second indication information includes the first logical address set and the second physical address set; the second physical address set is a change between the mapping relationship between the logical address and the physical address, and A physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the second indication information is carried in the EHS extension domain.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- an embodiment of the present application further provides a memory chip for implementing the implementation manner described in the third aspect, the memory chip is connected to a universal flash memory UFS protocol information unit UPIU, and the memory chip includes:
- a receiving unit configured to receive a second request from a master chip connected to the storage chip; wherein the second request includes a second logical address set and a second data, and the second data includes data to be written to The data of the memory chip; a generating unit, configured to generate the third instruction information according to the mapping relationship between the changed logical address and the physical address after the second data is written into the memory chip; wherein the third instruction information Including the second logical address set and a third physical address set corresponding to the second logical address set, the third physical address set including M physical addresses, and the M physical addresses and the second physical address set The logical address set includes M logical addresses in a one-to-one correspondence, and the third physical address set is used to store the second data, where M is an integer greater than or equal to 3; and a sending unit is configured to send to the master The chip sends a second response message of the second request; wherein the second response message includes the third indication information, and the second response message is used to instruct to update the Logical addresses and physical addresses in the chip mapping
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the third control information is carried in a third reserved field of a UPIU protocol frame.
- an embodiment of the present application further provides a main chip for implementing the implementation manner described in the fourth aspect, the main chip is connected to a universal flash memory UFS protocol information unit UPIU, and the main chip includes:
- a receiving unit configured to receive a second response message from a memory chip connected to the main chip; wherein the second response message includes third instruction information, and the third instruction information includes a second logical address set and A third physical address set corresponding to the second logical address set, the third physical address set includes M physical addresses, and the M physical addresses and the M logical addresses included in the second logical address set One-to-one correspondence, and the third physical address set is used to store the second data, the M is an integer greater than or equal to 3, and the update unit is used to update the main chip according to the third instruction information Mapping between logical addresses and physical addresses.
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the third control information is carried in a third reserved field of a UPIU protocol frame.
- the main chip further includes: a sending unit, configured to send a second request to the storage chip; wherein the second request includes a second logical address set and second data, The second data includes data to be written into the memory chip.
- an embodiment of the present application further provides a main chip for implementing the implementation manner described in the fifth aspect, the main chip is connected to a universal flash memory UFS protocol information unit UPIU, and the main chip includes:
- a determining unit is configured to determine a first logical address set; a generating unit is configured to generate first instruction information; wherein the first instruction information includes the first logical address set and a value determined according to a mapping relationship between a logical address and a physical address A first physical address set corresponding to the first logical address set, the first physical address set includes N physical addresses, and the N physical addresses and the N logical addresses included in the first logical address set One-to-one correspondence, the N is an integer greater than or equal to 2; the sending unit is configured to send a first request to a memory chip connected to the main chip; wherein the first request includes the first indication information.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the main chip further includes: an allocation unit configured to allocate an extension header field EHS extension domain; wherein the EHS extension domain is used to carry the first indication information.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the main chip further includes: a receiving unit, configured to receive a first response message from the storage chip; wherein the first response message includes second indication information, and the first The two indication information include the first logical address set and the second physical address set; the second physical address set is a physical address corresponding to the first logical address set after the mapping relationship between the logical address and the physical address is updated Set; the second set of physical addresses includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address; or the fourth field is used to indicate the access granularity of each physical address in the second physical address set and the The sum of the access granularity of each logical address in the first logical address; wherein the access granularity of each physical address in the second physical address set is the same as the access granularity of each logical address in the first logical address.
- the EHS extension domain is further configured to carry the second indication information.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- the sending unit is further configured to send a second request to the storage chip;
- the main chip further includes: a receiving unit configured to receive a second response message from the main chip An update unit, configured to update the mapping relationship between the logical address and the physical address in the main chip according to the third instruction information; wherein the second request includes a second logical address set and second data, and the second data Including data to be written into the memory chip; wherein the second response message includes third instruction information, and the third instruction information includes the second logical address set and corresponds to the second logical address set A third physical address set, the third physical address set includes M physical addresses, and the M physical addresses are in one-to-one correspondence with the M logical addresses included in the second logical address set, and the third The physical address set is used to store the second data, and M is an integer greater than or equal to 3.
- the second response message further includes third control information, where the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the EHS extension domain is further configured to carry the third indication information.
- the third control information is carried in a third reserved field of the UPIU protocol frame.
- an embodiment of the present application further provides a memory chip for implementing the implementation manner described in the sixth aspect, the memory chip is connected to a universal flash memory UFS protocol information unit UPIU, and the memory chip includes:
- a receiving unit configured to receive a first request from a master chip connected to the memory chip; wherein the first request includes first instruction information, and the first instruction information includes a first logical address set and a logical address according to the logical address
- the set includes N logical addresses in a one-to-one correspondence, where N is an integer greater than or equal to 2; an obtaining unit is configured to obtain first data according to the first physical address set; wherein the first data includes the first data Data stored in a first physical address set; a sending unit, configured to send the first data to the master chip.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or The second field is used to indicate the access granularity of each logical address in the first logical address set; or, the second field is used to indicate the access granularity and relative address of each physical address in the first physical address set.
- the sum of the access granularity of each logical address in the first logical address set; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first indication information is carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the master chip.
- the first control information is carried in a first reserved field of a UPIU protocol frame.
- the sending unit is further configured to send a first response message to the main chip when it is determined that the mapping relationship between the logical address and the physical address has changed; wherein the first A response message includes second indication information, and the second indication information includes the first logical address set and the second physical address set; the second physical address set is a change between the mapping relationship between the logical address and the physical address, and A physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses on a one-to-one basis.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or The fourth field is used to indicate the access granularity of each logical address in the first logical address set; or, the fourth field is used to indicate the access granularity and relative address of each physical address in the second physical address set.
- the second indication information is carried in the EHS extension domain.
- the second control information is carried in a second reserved field of the UPIU protocol frame.
- the receiving unit is further configured to receive a second request from a master chip connected to the storage chip; wherein the second request includes a second logical address set and a second Data, the second data includes data to be written into the memory chip;
- the storage chip further includes: a generating unit, configured to generate the third instruction information according to the mapping relationship between the changed logical address and the physical address after the second data is written into the storage chip; and the sending unit further uses A second response message for sending the second request to the main chip; wherein the second request includes a second logical address set and the second data; and the second data includes the to-be-written Data of a memory chip; wherein the third indication information includes the second logical address set and a third physical address set corresponding to the second logical address set, and the third physical address set includes M physical addresses And the M physical addresses correspond one-to-one with the M logical addresses included in the second logical address set, and the third physical address set is used to store the second data, and M is greater than or equal to An integer of 3; wherein the second response message includes the third indication information, and the second response message is used to instruct to update the mapping between the logical address and the physical address in the main chip Relations.
- a generating unit configured to generate the third instruction information according to the mapping relationship between
- the second response message further includes third control information; wherein the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or The sixth field is used to indicate the access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity and address of each physical address in the third physical address set.
- the sum of the access granularity of each logical address in the second logical address set; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information is carried in the EHS extension domain.
- the third control information is carried in a third reserved field of the UPIU protocol frame.
- an embodiment of the present application further provides a main chip, where the main chip includes a processor, a memory, and a communication interface, and the processor is connected to the memory and the communication interface through a line; the memory For storing a program; the processor for executing a program stored in the memory, so that the processor executes a corresponding function in an implementation manner described in the first aspect, the fourth aspect, and the fifth aspect;
- the communication interface is used to support communication between the main chip and other networks.
- an embodiment of the present application further provides a memory chip, where the memory chip includes a processor, a memory, and a communication interface, and the processor is connected to the memory and the communication interface through a line; the memory For storing a program; the processor for executing a program stored in the memory, so that the processor executes a corresponding function in an implementation manner described in the second aspect, the third aspect, and the sixth aspect;
- the communication interface is used to support communication between the memory chip and other networks.
- an embodiment of the present application provides a terminal device.
- the terminal device includes a main chip and a memory chip, and the main chip includes one or more of the seventh aspect, the tenth aspect, and the eleventh aspect.
- an embodiment of the present application provides a chip system.
- the chip system includes a main chip and a memory chip, and the main chip includes one or more of the seventh aspect, the tenth aspect, and the eleventh aspect.
- an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores instructions, and when the instructions are run on a computer, the computer is caused to execute the first aspect, The flow of the method described in any one or more of the second aspect, the third aspect, the fourth aspect, the fifth aspect, and the sixth aspect.
- an embodiment of the present application provides a computer program, where the computer program includes instructions, so that when the computer program is executed by the computer, the computer can execute the first aspect, the second aspect, The flow of the method described in any one or more of the third aspect, the fourth aspect, the fifth aspect, and the sixth aspect.
- FIG. 1a is a schematic flowchart of processing a read request according to an embodiment of the present application.
- FIG. 1b is a schematic flowchart of processing a write request according to an embodiment of the present application
- FIG. 2 is a schematic structural diagram of a main chip according to an embodiment of the present application.
- FIG. 3 is a schematic structural diagram of a memory chip according to an embodiment of the present application.
- FIG. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
- FIG. 5 is a schematic structural diagram of a chip system according to an embodiment of the present application.
- FIG. 6 is a schematic flowchart of an allocation method according to an embodiment of the present application.
- FIG. 7 is a schematic flowchart of an information processing method according to an embodiment of the present application.
- FIG. 8 is a schematic flowchart of another information processing method according to an embodiment of the present application.
- FIG. 9a is a schematic diagram of an EHS extended domain according to an embodiment of the present application.
- FIG. 9b is a schematic diagram of another EHS extension domain according to an embodiment of the present application.
- FIG. 10 is a schematic structural diagram of another main chip according to an embodiment of the present application.
- FIG. 11 is a schematic structural diagram of still another main chip according to an embodiment of the present application.
- FIG. 12 is a schematic structural diagram of another memory chip according to an embodiment of the present application.
- FIG. 13 is a schematic structural diagram of still another memory chip according to an embodiment of the present application.
- Logical address a relative address used in the user program.
- the logical address may include an LBA and the like.
- the physical address may include a PPN, a physical block address (physics address, PBA), an address smaller than a page, and the like.
- PPN physical block address
- an address smaller than a page may include an address with an access granularity of 4 KB, etc., which is not limited in the embodiment of the present application.
- the storage unit may include a storage unit in a memory chip and the like.
- mapping relationship between logical address and physical address In specific applications, the mapping relationship between logical address and physical address is stored in the memory chip.
- the main chip needs to read the data in the memory chip, the main chip sends to the memory chip including logic Address read request; after receiving the read request, the storage chip determines the physical address of the logical address according to the mapping relationship between the logical address and the physical address; then the storage chip sends the data stored in the physical address to the main chip, as shown in the figure 1a.
- the main chip When the main chip needs to write data, the main chip sends a write request including the logical address and the data to be written to the memory chip; after receiving the write request, the memory chip stores the data to be written to the storage In the chip, the mapping relationship between the logical address and the physical address stored in the memory chip is updated, as shown in FIG. 1b.
- mapping relationship between the logical address and the physical address can also be called a logical address and physical address mapping table; or, it can also be called an LBA and PPN mapping table; or, it can also be called an LBA and PBA mapping table, etc.
- LBA and PPN mapping table or, it can also be called an LBA and PBA mapping table, etc.
- the specific names of the embodiments of the present application are not limited.
- the mapping relationship between the logical address and the physical address can be stored in both the main chip and the storage chip.
- the mapping relationship between the logical address and the physical address is stored in the main chip, which can effectively avoid the situation that the memory chip cannot be hit, and avoid the process of multi-level search of the memory chip, etc., which improves the search efficiency and the response speed.
- the mapping relationship between the logical address and the physical address stored in the main chip may also be referred to as a copy of the mapping relationship between the logical address and the physical address, or may be referred to as a copy of the mapping table between the logical address and the physical address. .
- FIG. 2 is a schematic structural diagram of a main chip provided in an embodiment of the present application, and the main chip may be connected to a universal flash storage (UFS) protocol information unit (UFS) protocol information unit (UPIU).
- UFS universal flash storage
- UFS universal flash storage
- the main chip may include a main central processing unit (CPU), a multimedia application processor (MAP), a UFS main controller, and a double-rate synchronous dynamic random access memory (double data). rate, dynamic, random, random access, memory (DDR, SDRAM) controller, DDR SDRAM memory, peripheral device controller, and peripherals.
- DDR SDRAM dynamic, random, random access, memory
- peripheral device controller and peripherals.
- DDR SDRAM dynamic, random, random access memory
- the main CPU and the MAP can be used for coupling with the memory, so as to execute program instructions stored in the memory and the like.
- Such as the main CPU and MAP can be used to run the operating system, applications, drivers and other software running on the main chip.
- the memory may also be used to store a mapping relationship between a logical address and a physical address. It can be understood that, in the embodiment of the present application, the memory includes DDR.
- the UFS master controller can be used to issue one or more of a read request and a write request in accordance with the UPIU protocol frame.
- the UFS main controller may be further configured to cause the instruction information (such as the first instruction information in the following embodiments, etc.) included in the read request to be carried on the EHS allocated by the UFS driver (not shown in the figure).
- the EHS extension domain may include at least 2016B space.
- the read request sent by the UFS main controller may occupy at least 2KB of space, such as a 32IU UPIU frame header (UPIU frame header) and a 2016B EHS extension field.
- the main chip can carry more physical address information, such as first indication information, when sending a UPIU request to the memory chip.
- the DDR controller can be used to control the DDR.
- the DDR controller can be used to control and update the mapping relationship between the logical address and the physical address in the DDR.
- Peripheral devices can include input and output interfaces, external memory, analog-to-digital converters, digital-to-analog converters, peripheral processors, and so on.
- the peripheral device may include a touch screen, a camera, fingerprint collection, a near-field communication element, various sensors, and the like, and the embodiment of the present application does not limit the peripheral device.
- the peripheral device controller may be used to control the peripheral device.
- the main chip may be various forms of chips, for example, the main chip may be integrated on the SOC.
- the main chip may be applied to various terminal devices, such as the main chip may be applied to a mobile phone or a notebook computer, etc., which are not limited in the embodiment of the present application.
- main chip shown in FIG. 2 is only an example provided in the embodiment of the present application, and the main chip may have more or fewer parts than those shown, and two or more parts may be combined. Or it may have different configuration implementations with different components and so on.
- FIG. 3 is a schematic structural diagram of a memory chip provided by an embodiment of the present application, and the memory chip can be connected to a UPIU.
- the memory chip includes a controller and a cache array (ie, a flash array).
- the controller and the flash array can be connected to each other through a line.
- the controller is the core device of the memory chip, which can be used to reasonably allocate the load of data on each flash array, and the controller can also be used for data transfer, connecting the flash array and an external serial interface.
- the controller may further include a hardware chip, for example, the hardware chip may be an application-specific integrated circuit (ASIC), or the hardware chip may be a field programmable logic gate array (field programmable logic array). gate array, FPGA, etc., which are not limited in the embodiments of the present application.
- ASIC application-specific integrated circuit
- FPGA field programmable logic gate array
- the controller may include a static random access memory (static random access memory, SRAM).
- SRAM static random access memory
- the SRAM may be used to store a mapping relationship between a logical address and a physical address.
- the memory chip may be a chip of various forms.
- the storage chip may be applied to various storage devices, such as the storage chip may be applied to a solid state disk (SSD), etc., which is not limited in the embodiment of the present application.
- the memory chip can also be applied to various terminal devices, for example, the memory chip can be applied to a mobile phone or a notebook computer.
- the memory chip may receive the information including the EHS extension domain sent by the main chip, and thus use the EHS extension domain to send more information to the main chip including the updated mapping relationship between the physical address and the logical address.
- the memory chip shown in FIG. 3 is only an example provided in the embodiment of the present application, and the memory chip may have more or fewer parts than those shown, and two or more parts may be combined. Or it may have different configuration implementations with different components and so on.
- FIG. 4 is a schematic structural diagram of a terminal device according to an embodiment of the present application.
- the terminal device may include a screen, a screen controller, a main chip, and a UFS storage device.
- the main chip may be the main chip shown in FIG. 2.
- the main chip may include a peripheral device, a peripheral device controller, a DDR, a DDR controller, a UFS host controller, and a main CPU.
- the UFS storage device may be a memory chip shown in FIG. 3, wherein components included in the UFS storage device are not shown in FIG. 4.
- the UFS main controller is connected to the UFS storage device, and the UFS main controller can be used to interact with the UFS storage device, so that the terminal device can read data in the UFS storage device through the UFS main controller, and
- the UFS storage device may also be used to send information for instructing the UFS main controller to update the mapping relationship when the data storage in the UFS storage device changes, so that the main CPU controls the DDR controller to update the DDR in time. Mapping relationship between stored logical addresses and physical addresses.
- the main CPU may include a RISC microprocessor (advanced RISC machines, ARM), and the like.
- RISC microprocessor advanced RISC machines, ARM
- the embodiment of the present application does not limit the specific type or model of the main CPU.
- terminal device shown in FIG. 4 is only an example, and it should not be construed as limiting the embodiments of the present application.
- FIG. 5 is a schematic diagram of a specific scenario of a chip system according to an embodiment of the present application.
- the chip system may include a main chip and a memory chip.
- the main chip may be the main chip shown in FIG. 2, and the memory chip may be the memory chip shown in FIG. 3.
- the main chip may further include an application (APP), a UFS driver, a UFS main controller, and a mobile industry processor interface (MIPI) transport layer and MIPI physics. Layers and so on.
- the memory chip may further include a storage unit, a logical unit (LU) unit, and a device-level management unit, and has a MIPI physical layer, a MIPI transport layer, and a cache descriptor.
- the main chip obtains a logical address from the APP, and the logical address is issued by the UFS driver to carry a read request carrying the logical address; the read request is controlled by the UFS master
- the device sends a read request that conforms to the UPIU protocol frame; then it passes through the transport layer. If the read request can go through the MIPI unified protocol (MIPI Unipro); finally after the MIPI physical layer (PHY), the master chip sends the read request Send to the memory chip.
- MIPI Unipro MIPI unified protocol
- PHY MIPI physical layer
- the memory chip may sequentially pass through the MIPI physical layer and the MIPI transport layer, and then pass the buffer descriptor, the read request passes through the LU unit, and after the read request is calculated by the LU, the memory chip is readable Take the data stored in the storage unit.
- the data stream sent from the buffer descriptor can pass through the LU; and the control stream sent from the buffer descriptor can pass through the device-level management unit.
- the device-level management unit may be used to receive a control flow sent from the buffer descriptor.
- the control flow may be used to control the configuration of the LU unit, and the like is not limited in the embodiment of the present application.
- the chip system shown in FIG. 5 is only an example provided by the embodiment of the present application, and the chip system may have more or fewer parts than those shown, and two or more parts may be combined. Or it may have different configuration implementations with different components and so on.
- the main CPU included in the main chip is not shown, but should not be construed as limiting the embodiments of the present application.
- the master chip when the master chip sends a read request including a logical address to the memory chip, the master chip can indicate the logical address by the first address + length of the logical address. That is, the main chip can send a UPIU request (commandUPIU, CMD @ UPIU) that conforms to the UPIU protocol frame through the UFS controller.
- UPIU request commandUPIU, CMD @ UPIU
- the main chip when the mapping relationship between the logical address and the physical address is stored on the main chip and the storage chip, the main chip sends a read request to the storage chip.
- the read request may include a 4KB read request, an 8KB read request, and a 16KB read request. Read requests, 32KB read requests, etc.
- READ_10 can be used, that is, the main chip can send a read request including a mapping relationship between a logical address and a physical address to the storage chip; wherein the pair can include 8 bytes, that is, 4 bytes Logical address, 4-byte physical address.
- the first address + length of the logical address and the first address + length of the physical address can be used to indicate to the memory chip the mapping relationship between the pair of logical addresses and the physical address. That is, a 4-byte logical address and a 4-byte physical address (one-to-one correspondence) can express a 4KB read request.
- mapping relationship between the logical address and the physical address is stored on the main chip and the storage chip
- the storage chip updates the mapping relationship between the logical address and the physical address, such as after the writing of the storage chip is completed
- the memory chip needs to send the updated mapping relationship between the logical address and the physical address to the master chip, so that the master chip updates the mapping relationship between the logical address and the physical address stored in the master chip.
- the standard UPIU uses 20 bytes of Sense Data, and can only put down a maximum of two pairs (16 bytes) of mapping. As a result, it may not be possible to update the mapping relationship change of the write request in a timely manner. That is to say, due to the native available space of the response UPIU response (UPIU, RESP @ UPIU), when the storage chip indicates the updated mapping relationship to the main chip, it cannot fill in multiple mapping relationships. Further, when the mapping relationship between the logical address and the physical address is updated in a large amount, adopting the foregoing method may seriously affect system performance.
- the embodiments of the present application provide a method that not only enables the main chip to fill in multiple pairs of discrete physical addresses, but also enables the memory chip to fill in multiple pairs or even a large number of mapping relationships.
- FIG. 6 is a schematic flowchart of an allocation method provided by an embodiment of the present application.
- the method can be applied to the main chip shown in FIG. 2 above.
- the UFS main controller of FIG. 2 can be used to support and execute FIG. Shown method flow 602.
- the method can also be applied to the main chip shown in FIG. 5.
- the UFS driver shown in FIG. 5 can be used to support and execute the method flow 601 shown in FIG. 6, and the UFS main controller can be used to support and execute The method flow 602 shown in FIG. 6.
- the allocation method includes:
- the UFS driver allocates an EHS extension domain.
- the EHS extension domain may also be referred to as an EHS extension space.
- the EHS extension domain may also include other names, etc., which are not limited in the embodiment of the present application.
- the EHS extension domain may include at least 2016B extension space.
- the EHS extension domain can be allocated by the UFS driver software of the main chip.
- the driver software can include the Kirin UFS driver of the Huawei Kirin platform and so on.
- the UFS driver sends the EHS extension domain to the UFS controller.
- the EHS extension domain is used to carry one or more of a read request and a write request issued by the master chip. That is, the EHS extension field may be used to instruct the UFS controller to carry a UPIU request conforming to the UPIU protocol frame, such as first indication information included in a read request, and so on.
- the embodiment of the present application also provides two implementation manners, as shown below:
- the UFS driver sends the first address of the EHS extended domain to the UFS controller.
- the main chip can set or plan the length of the EHS extension domain in advance. Further, the main chip may further negotiate (or negotiate) the length of the EHS extension domain with the memory chip in advance. For example, the main chip can increase the protocol with the memory chip.
- the length of the EHS extension field is 2016B.
- the UFS driver sends the first address and length of the EHS extended domain to the UFS controller.
- the length of the EHS extension domain can be changed, that is, the main chip can set the length of the EHS extension domain according to needs.
- the memory chip can also return a response message, such as the first response message and the second response message in the following embodiments.
- the second indication information in the first response message and the third indication information in the second response message may also be carried in the EHS extension domain.
- the first indication information in the read request is carried in the EHS extension domain, and the memory chip may return the second indication information in the first response message (or the second indication message in the second response message).
- the third indication information bears the same EHS extension domain, or may be different, which is not limited in the embodiment of the present application. It can be understood that the same EHS extension field can indicate the same format, but it does not mean that the content filled in the EHS extension field is the same.
- the first control information in the read request (such as the first request) may be carried in the first reserved field of the UPIU protocol frame, and the first The second control information in a response message may be carried in the second reserved field of the UPIU protocol frame, and the third control information in the second response message returned by the storage chip may be carried in the third UPIU protocol frame. In the reserved field.
- the second reserved field and the third reserved field may be the same field or different fields, which are not limited in the embodiment of the present application.
- the UPIU protocol frame carried in the first control information may be the same UPIU protocol frame as the UPIU protocol frame carried in the second control information, or may be different UPIU protocol frames, etc., which is not limited in the embodiment of the present application .
- the UPIU protocol frame carried by the first control information may be the same UPIU protocol frame as the UPIU protocol frame carried by the third control information, or may be different UPIU protocol frames, etc., which are not limited in the embodiment of the present application. . Therefore, the first reserved field and the second reserved field (or the third reserved field) may be the same field or different fields, which are not limited in the embodiment of the present application.
- the UFS controller in the embodiment of the present application may be the UFS main controller shown in FIG. 2, FIG. 4, and FIG. 5. Therefore, the UFS controller should not be construed as limiting the embodiments of the present application.
- FIG. 7 is a schematic flowchart of an information processing method provided by an embodiment of the present application.
- the information processing method can be applied to the main processing method shown in FIG. 2 to FIG. 5. Chips and memory chips. If the method can be applied to the main chip shown in FIG. 2 described above, the main CPU of FIG. 2 can be used to support and execute the method flows 701, 702, and 706 shown in FIG.
- the controller shown in FIG. 3 can be used to support and execute the method flow 704 shown in FIG. 7.
- the information processing method includes:
- the main chip determines a first logical address set.
- the first logical address set determined by the main chip may correspond to at least an 8 KB read request. It can be understood that the logical addresses included in the first logical address set may be continuous, or the logical addresses included in the first logical address set may also be discontinuous, which is not limited in the embodiment of the present application.
- the main chip generates first indication information, where the first indication information includes a first logical address set and a first physical address set corresponding to the first logical address set determined according to a mapping relationship between the logical address and the physical address.
- the first physical address set includes N physical addresses, and the N physical addresses are in one-to-one correspondence with the N logical addresses included in the first logical address set.
- the first physical address set may include N discrete physical addresses. Specifically, how many physical addresses are included in the first physical address set, the master chip can divide the first logical address set into how many logical addresses. For example, if the first physical address set includes N physical addresses, and each physical address in the N physical addresses corresponds to a logical address, then the first logical address set (such as the first logical address set The logical addresses included are continuous) and can be divided into N logical addresses, and the N logical addresses correspond to the N physical addresses, respectively. That is, one physical address corresponds to one logical address. Understandably, N is an integer greater than or equal to two.
- the main chip sends a first request to a storage chip connected to the main chip, where the first request includes first indication information.
- the first request may be used to request to read data corresponding to the first logical address set. That is, the first request may be used to request first data, and the first data includes data stored in the first physical address set.
- the first request may further include first control information, and the first control information includes a first field, where the first field is used to indicate N.
- N may represent the number of discrete physical addresses in the first physical address set, or the number of logical addresses in the first logical address set after the first logical address set is divided. Specifically, N is an integer greater than or equal to two.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or the second field is used to indicate the first The access granularity of each logical address in a logical address set; or, the second field is used to indicate the access granularity of each physical address in the first physical address set and the access of each logical address in the first logical address set Sum of granularity; the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the access granularity may indicate a unit storing each address in the first instruction information. More generally, the access granularity can indicate how many bytes are stored in each logical address or each physical address. As described above, the mapping relationship between a pair of logical addresses and physical addresses may include 8 bytes, that is, a 4-byte logical address and a 4-byte physical address. Among them, the access granularity can be expressed by 4 bytes, or the access granularity can also be expressed by 8 bytes.
- the first physical address set includes N physical addresses
- the first logical address set includes N logical addresses, which means that there are N mapping relationships, and 8 bytes can be used to express N respectively.
- Each pair of mappings in a mapping is a mapping.
- access granularity is only an example, and more or less bytes than 4 bytes (access granularity of each physical address or access granularity of each logical address) may be used to express the access granularity Alternatively, more or less bytes than 8 bytes (that is, the sum of the access granularity of each physical address and the access granularity of each logical address) may be used to express the access granularity, which is not described in this embodiment of the present application. limited.
- the first indication information can be carried in the EHS extension domain allocated by the main chip, and the first control information can be carried in the first reserved field of the UPIU protocol frame.
- the storage chip receives a first request from the main chip, and obtains first data according to a first physical address set, where the first data includes data stored in the first physical address set.
- the storage chip may return the first data to the main chip, that is, the storage The chip sends the first data to the main chip.
- the memory chip may carry the first data in a space other than the UPIU protocol frame and the EHS extension domain.
- the memory chip may send the first data
- the data stored in the N physical addresses may be N data or less than N data
- the response speed of the read request can be effectively improved; on the other hand, by generating the first instruction information, the first An indication information can be used to indicate the first physical address set.
- the first physical address set includes at least two physical addresses, so that 8KB, 16KB, and even 32KB read requests can be realized, thereby realizing real-time between the main chip and the memory chip. The efficiency of information interaction.
- the physical address of data stored in the memory chip may change due to operations such as wear leveling (WL) or garbage collection (GC). Therefore, after the memory chip determines the mapping relationship between the logical address and the physical address after the change, it also needs to inform the main chip of the change to improve the efficiency of information interaction. Refer to the following steps for the above situation.
- the storage chip determines that the mapping relationship between the logical address and the physical address has changed, send a first response message to the main chip.
- the first response message includes second indication information, and the second indication information includes a first logical address set and a second physical address set; the second physical address set is an update of the mapping relationship between the logical address and the physical address, and A physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses one-to-one.
- the second instruction information may also be used to instruct the main chip to update a mapping relationship between a logical address and a physical address in the main chip.
- the first response message further includes second control information; wherein the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or the fourth field is used to indicate the first The access granularity of each logical address in a logical address set; or, the fourth field is used to indicate the access granularity of each physical address in the second physical address set and the access of each logical address in the first logical address set The sum of granularity; wherein the access granularity of each physical address in the second physical address set is the same as the access granularity of each logical address in the first logical address set. 706.
- the main chip receives the first response message, and updates the mapping relationship between the logical address and the physical address in the main chip according to the second instruction information.
- the second indication information can be carried in the EHS extension domain, and the second control information can be carried in the second reserved field of the UPIU protocol frame.
- the mapping relationship between the logical address and the physical address stored in the memory chip can also be prevented from changing, and the memory chip cannot be based on only the physical Address to determine the corresponding data (first data); thereby further improving the efficiency of information exchange between the main chip and the memory chip.
- FIG. 8 is a schematic flowchart of another information processing method according to an embodiment of the present application.
- the information processing method may be applied to a main chip and a memory chip shown in FIGS. 2 to 5.
- the information processing method includes:
- the main chip sends a second request to a memory chip connected to the main chip.
- the second request includes a second logical address set and second data, and the second data includes data to be written to the memory chip.
- the second logical address set is the logical address of the second data.
- the second data includes data to be written into the memory chip. It can be understood that the embodiment of the present application does not limit the size or type of the second data.
- the storage chip receives a second request from the main chip, and writes the second data into the storage chip.
- the storage chip generates third instruction information according to the changed mapping relationship between the logical address and the physical address.
- the memory chip can generate the third instruction information according to the physical address of the second data and the logical address of the second data.
- the third indication information includes a second logical address set and a third physical address set corresponding to the second logical address set.
- the third physical address set includes M physical addresses, and the M physical addresses and the first The two logical address sets include one-to-one correspondence of M logical addresses, and the third physical address set is used to store second data, and M is an integer greater than or equal to 3.
- the third physical address set may include at least three discrete physical addresses. Specifically, how many (such as M) physical addresses are included in the third physical address set, the memory chip may divide the second logical address set into how many (such as M) logical addresses. It can be understood that one physical address corresponds to one logical address. Therefore, the third indication information includes a third physical address set and a second logical address set having a mapping relationship.
- the memory chip sends a second response message of the second request to the main chip; wherein the second response message includes third instruction information, and the second response message is used to instruct to update the mapping between the logical address and the physical address in the main chip. relationship.
- the second response message further includes third control information
- the third control information includes a fifth field, and the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or the sixth field is used to indicate the third control address.
- Access granularity of each logical address in the second logical address set; or, the sixth field is used to indicate the access granularity of each physical address in the third physical address set and the access of each logical address in the second logical address set Sum of granularity; the access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the main chip receives a second response message from the memory chip, and updates the mapping relationship between the logical address and the physical address according to the third instruction information in the second response message.
- mapping relationship between the logical address and the physical address can be stored in the DDR space.
- the master chip After the master chip receives the second response message, it can parse the updated mapping relationship from the UPIU to synchronize the updated mapping relationship. Update the mapping relationship between logical address and physical address in the DDR space of the main chip.
- the third indication information may be carried in the EHS extension domain, and the third control information may be carried in the third reserved field of the UPIU protocol frame.
- the storage chip when a large number of mapping relationships are updated in the storage chip, the storage chip can indicate the updated mapping relationship to the main chip in time, which improves the efficiency of real-time interaction of information.
- first indication information, the second indication information, and the third indication information shown in FIG. 7 and FIG. 8 may be carried in the EHS extension domain shown in FIG. 6. More specific first indication information may be carried in the EHS extension domain carrying the UPIU request. And the second indication information and the third indication information may be carried in an EHS extension domain carrying a UPIU response.
- FIG. 9a is a schematic structural diagram of an EHS extension domain provided by an embodiment of the present application.
- the EHS extension domain may be used to carry first indication information.
- reference numeral 32 is an EHS extension domain provided by an embodiment of the present application, and may be used to carry first indication information.
- label 5, label 6, or label 7 can be the first reserved field in the UPIU protocol frame.
- label 5 is used as an example, and label 5 can be used to carry the access granularity and label. 8 can be used to carry the number. That is, reference numeral 5 is the second field provided in the embodiment of the present application.
- the reference numeral 5 can be used to carry the access granularity of each physical address in the first physical address set, or each of the first logical address set.
- the access granularity of the logical address or the sum of the access granularity of each physical address in the first physical address set and the access granularity of each logical address in the first logical address set.
- the reference number 8 is the first field provided in the embodiment of the present application, and the reference number 8 may be used to carry the number N.
- Reference numeral 32 may be used to carry the first logical address set and the first physical address set in the embodiment of the present application, as shown in FIG. 9a.
- FIG. 9b is a schematic structural diagram of another EHS extension domain provided by an embodiment of the present application.
- the EHS extension domain may be used to carry the second indication information or the third indication information.
- reference numeral 32 is an EHS extension domain provided in the embodiment of the present application, and may be used to carry the second indication information or the third indication information. Further, one or more of the number 5 or the number 6 may be the second reserved field or the third reserved field in the UPIU protocol frame. For example, if the EHS extension domain carries the second indication information, the number 5 is The second reserved field in the UPIU protocol frame is taken as an example. The number 5 can be used to carry the access granularity, and the number 8 can be used to carry the number. That is, reference numeral 5 is the fourth field in the embodiment of the present application.
- Reference numeral 5 may be used to carry the access granularity of each physical address in the second physical address set in the embodiment of the present application, or the access granularity of each logical address in the first logical address set, or each second physical address set The sum of the access granularity of each physical address in each and the access granularity of each logical address in each first logical address set.
- the EHS extended domain carries the third indication information
- the number 5 is the third reserved field in the UPIU protocol frame as an example.
- the number 5 is the sixth field in the embodiment of the present application.
- the number 5 can be used for It carries the access granularity of each physical address in the third physical address set in the embodiment of the present application, or the access granularity of each logical address in the second logical address set, or the physical granularity of each physical address in the third physical address set. The sum of the access granularity and the access granularity of each logical address in the second logical address set.
- the reference number 8 is the third field or the fifth field in the embodiment of the present application, and the reference number 8 may be used to bear N or M.
- Reference numeral 32 may be used to carry the second indication information or the third indication information. That is, the reference number 32 can be used to carry a first logical address set and a second physical address set having a mapping relationship, or can also be used to carry a second logical address set and a third physical address set having a mapping relationship, as shown in FIG. 9b. .
- FIG. 10 is a schematic structural diagram of a main chip according to an embodiment of the present application, and the main chip may be used to execute the methods shown in FIGS. As shown in FIG. 10, the main chip includes:
- the generating unit 1002 is configured to generate first indication information, where the first indication information includes a first logical address set and a first physical address set corresponding to the first logical address set and determined according to a mapping relationship between the logical address and the physical address.
- the first physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses included in the first logical address set one by one, where N is an integer greater than or equal to 2;
- the sending unit 1003 is configured to send a first request to a memory chip connected to the main chip; wherein the first request includes first indication information.
- the main CPU shown in FIG. 2 can be used to execute the implementation manner shown in the determining unit 1001 and the generating unit 1002. And in a possible implementation manner, the main CPU can also be used to control the UFS main controller to execute the implementation manner shown in the sending unit 1003.
- the response speed of the read request can be effectively improved; on the other hand, by generating the first instruction information, the first An indication information can be used to indicate the first physical address set.
- the first physical address set includes at least two physical addresses, so that 8KB, 16KB, and even 32KB read requests can be realized, thereby realizing real-time between the main chip and the memory chip. The efficiency of information interaction.
- the first request further includes first control information.
- the first control information includes a first field, and the first field is used to indicate N.
- the first control information further includes a second field
- the second field is used to indicate the access granularity of each physical address in the first physical address set
- the second field is used to indicate the access granularity of each logical address in the first logical address set
- the second field is used to indicate the sum of the access granularity of each physical address in the first physical address set and the access granularity of each logical address in the first logical address set; the access of each physical address in the first physical address set
- the granularity is the same as the access granularity of each logical address in the first logical address set.
- the main chip further includes:
- the allocating unit 1104 is configured to allocate an extended header field EHS extended domain; wherein the EHS extended domain is used to carry the first indication information.
- the first control information may be carried in a first reserved field of the UPIU protocol frame.
- the main chip further includes:
- a receiving unit 1105 configured to receive a first response message from the memory chip
- the first response message includes second indication information, and the second indication information includes a first logical address set and a second physical address set.
- the second physical address set is updated after the mapping relationship between the logical address and the physical address is updated.
- the physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses one-to-one.
- the first response message further includes second control information.
- the second control information includes a third field, and the third field is used to indicate the N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate an access granularity of each physical address in the second physical address set; or the fourth field is used to indicate the first physical address The access granularity of each logical address in the logical address; or, the fourth field is used to indicate the sum of the access granularity of each physical address in the second physical address set and the access granularity of each logical address in the first logical address Wherein, the access granularity of each physical address in the second physical address set is the same as the access granularity of each logical address in the first logical address.
- the second indication information may be carried in an EHS extension domain, and the second control information may be carried in a second reserved field of a UPIU protocol frame.
- the sending unit 1103 is further configured to send a second request to the memory chip, where the second request includes a second logical address set and second data, and the second data includes data to be written to the memory chip. .
- the second request may be used to request that the second data be written into the memory chip.
- the receiving unit 1105 may be further configured to receive a second response message from a memory chip connected to the main chip; wherein the second response message includes third instruction information, and the third instruction information includes a second logical address set and A third physical address set corresponding to the second logical address set, the third physical address set includes M physical addresses, and the M physical addresses are in one-to-one correspondence with the M logical addresses included in the second logical address set, And the third physical address set is used to store the second data, and M is an integer greater than or equal to 3;
- the main chip also includes:
- the updating unit 1106 is configured to update the mapping relationship between the logical address and the physical address in the main chip according to the third instruction information.
- the second response message further includes third control information, and the third control information includes a fifth field, where the fifth field is used to indicate the M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or the sixth field is used to indicate the second physical address The access granularity of each logical address in the logical address set; or, the sixth field is used to indicate the access granularity of each physical address in the third physical address set and the access granularity of each logical address in the second logical address set The access granularity of each physical address in the third physical address set is the same as the access granularity of each logical address in the second logical address set.
- the third indication information can also be carried in the EHS extension domain, and the third control information can also be carried in the third reserved field of the UPIU protocol frame.
- the main CPU shown in FIG. 2 can also be used to execute the implementation manner shown in the update unit 1106, etc., and in a possible implementation manner, the main CPU can also be used to control the UFS main controller to execute the receiving unit 1105.
- the implementation manners shown and the like are not limited in the embodiments of the present application.
- FIG. 12 is a schematic structural diagram of a memory chip according to an embodiment of the present application.
- the memory chip may be used to execute the methods shown in FIGS. 6 to 8.
- the memory chip includes:
- the receiving unit 1201 is configured to receive a first request from a master chip connected to the storage chip; wherein the first request includes first instruction information, and the first instruction information includes a first logical address set and a logical address and a physical address according to the logical address and the physical address.
- the obtaining unit 1202 is configured to obtain first data according to a first physical address set, where the first data includes data stored in the first physical address set;
- the sending unit 1203 is configured to send the first data to the main chip.
- controller in the memory chip shown in FIG. 3 may be used to execute the method performed by the obtaining unit 1202.
- the external serial interface in the memory chip and the like (not shown in FIG. 3) can be used to execute the method performed by the receiving unit 1201 and the transmitting unit 1203.
- the first request further includes first control information; wherein the first control information includes a first field, and the first field is used to indicate the N.
- the first control information further includes a second field; wherein the second field is used to indicate an access granularity of each physical address in the first physical address set; or the second field is used to indicate the first physical address Access granularity of each logical address in the logical address set; or, the second field is used to indicate the access granularity of each physical address in the first physical address set and the access granularity of each logical address in the first logical address set And the access granularity of each physical address in the first physical address set is the same as the access granularity of each logical address in the first logical address set.
- the first indication information may be carried in an extension header field EHS extension domain, and the EHS extension domain is allocated by the main chip.
- the first control information may be carried in a first reserved field of a UPIU protocol frame.
- the sending unit 1203 is further configured to send a first response message to the main chip when it is determined that the mapping relationship between the logical address and the physical address has changed;
- the first response message includes second instruction information, and the second instruction information includes a first logical address set and a second physical address set.
- the second physical address set is a mapping relationship between the logical address and the physical address, and A physical address set corresponding to the first logical address set; the second physical address set includes N physical addresses, and the N physical addresses correspond to the N logical addresses one to one.
- the first response message further includes second control information.
- the second control information includes a third field, and the third field is used to indicate N.
- the second control information further includes a fourth field; wherein the fourth field is used to indicate the access granularity of each physical address in the second physical address set; or the fourth field is used to indicate each of the physical addresses in the first logical address set.
- the granularity of access to each logical address; or, the fourth field is used to indicate the sum of the granularity of access to each physical address in the second physical address set and the granularity of access to each logical address in the first logical address set;
- the access granularity of each physical address in the address set is the same as the access granularity of each logical address in the first logical address set.
- the receiving unit 1201 is further configured to receive a second request from a master chip connected to the memory chip; wherein the second request includes a second logical address set and second data, and the second data includes a memory to be written into the memory.
- Chip data includes a second logical address set and second data, and the second data includes a memory to be written into the memory.
- the memory chip also includes:
- the generating unit 1204 is configured to generate the third instruction information according to the mapping relationship between the changed logical address and the physical address after writing the second data into the memory chip, where the third instruction information includes the second logical address set and the second logical address set.
- the sending unit 1203 is configured to send a second request second response message to the main chip; wherein the second response message includes third indication information, and the second response message is used to instruct to update the mapping relationship between the logical address and the physical address in the main chip. .
- the second response message further includes third control information.
- the third control information includes a fifth field, and the fifth field is used to indicate M.
- the third control information further includes a sixth field; wherein the sixth field is used to indicate an access granularity of each physical address in the third physical address set; or the sixth field is used to indicate each of the physical addresses in the second logical address set.
- the granularity of access of each logical address; or, the sixth field is used to indicate the sum of the granularity of access of each physical address in the third physical address set and the granularity of access of each logical address in the second logical address set; the third physical address set
- the access granularity of each physical address in the same as the access granularity of each logical address in the second logical address set.
- the third indication information may also be carried in the EHS extension domain.
- the third control information may be carried in a third reserved field of the UPIU protocol frame.
- the processes may be completed by a computer program instructing related hardware.
- the program may be stored in a computer-readable storage medium.
- When the program is executed, Can include the processes of the method embodiments described above.
- the foregoing storage media include: ROM or random storage memory RAM, magnetic disks, or optical discs, which can store various program code media.
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Memory System (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Abstract
一种信息处理方法及装置、设备、***;其中,该信息处理方法包括:主芯片确定第一信息,该第一信息中包括第一逻辑地址集合;该主芯片生成第一指示信息,该第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与该第一逻辑地址集合对应的第一物理地址集合,该第一物理地址集合包括N个物理地址,该N个物理地址与第一逻辑地址集合中包括的N个逻辑地址一一对应,该N为大于或等于2的整数;该主芯片向与该主芯片连接的存储芯片发送第一请求,该第一请求包括该第一指示信息。该方法,以及对应的装置、设备和***可有效提高读请求的响应速度。
Description
本申请涉及芯片技术领域,尤其涉及一种信息处理方法及装置、设备、***。
存储芯片中一般都包括控制器以及缓存(flash)阵列,其中,控制器中的静态随机存取存储器(static random access memory,SRAM)可用来存储逻辑地址与物理地址映射关系,也称为逻辑地址与物理地址映射表。
如对于终端设备来说,在需要向存储芯片发送请求时,可由集成在***芯片(system on chip,SOC)侧的通用闪存存储(universal flash storage,UFS),发出符合UFS协议信息单元(UFS protocol information unit,UPIU)的请求,然后存储芯片在接收到该请求后,在SRAM中查找逻辑地址与物理地址映射表,从而操作flash阵列来实现该请求所需要执行的操作。其中,该请求可包括读请求或写请求或擦除请求等等。
然而,在实际应用中,SRAM的资源有限,往往无法存储全量映射表,因此每次查找逻辑地址与物理地址映射表时,很有可能没法命中,从而需要多级查找等过程。举例来说,在执行读请求,查找逻辑地址与物理地址映射表时,如果未命中,则需要从flash中下载该逻辑地址与物理地址映射表到SRAM中,同时如果SRAM中表项空位不足,则会下刷其他表项到该flash中,由此命中率低会导致导表开销以及表项下刷等操作,从而严重影响读请求的响应速度。
因此,如何提高读请求的响应速度是亟待解决的问题。
发明内容
本申请公开了一种信息处理方法及装置、设备、***,能够有效提高读请求的响应速度。
第一方面,本申请实施例提供了一种信息处理方法,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的主芯片,所述方法包括:
所述主芯片确定第一逻辑地址集合;所述主芯片生成第一指示信息;所述主芯片向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;所述第一请求包括所述第一指示信息。
本申请实施例中,一方面,通过将逻辑地址与物理地址映射关系存储于空间较大的主芯片中,可有效提高读请求的响应速度;另一方面,通过生成第一指示信息,该第一指示信息可用于指示第一物理地址集合,该第一物理地址集合中包括至少两个物理地址,如在一个物理地址对应4KB的读请求的情况下,实施本申请实施例便可以实现8KB、16KB甚 至32KB的读请求,从而有效实现了主芯片和存储芯片之间实时信息交互的效率。
本申请实施例中,通过向存储芯片指示具有映射关系的N个逻辑地址与N个物理地址,还可避免存储芯片中存储的逻辑地址与物理地址映射关系发生变化,而导致存储芯片无法仅仅根据物理地址而确定相应的数据(第一数据);从而进一步提高了主芯片与存储芯片之间信息交互的效率。
可选的,逻辑地址可包括逻辑区块地址(logical block address,LBA),物理地址可包括物理页号(physical page number,PPN)。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
本申请实施例中,通过向存储芯片指示第一物理地址集合中物理地址的个数,可使得存储芯片能够清楚得知第一物理地址集合中所包含的物理地址的个数是多少,从而获取到数据,进而进一步提高了信息交互的效率。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
本申请实施例中,在主芯片与存储芯片未预先约定访问粒度的情况下,主芯片通过向存储芯片指示访问粒度,可使得存储芯片得到第一物理地址集合中每个物理地址具体为多少个字节。
在一种可能的实现方式中,所述主芯片向与所述主芯片连接的存储芯片发送第一请求之前,所述方法还包括:所述主芯片分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述第一指示信息。
具体的,所述主芯片可包括UFS驱动器和UFS控制器,所述UFS驱动器与所述UFS控制器连接;所述主芯片向与所述主芯片连接的存储芯片发送第一请求之前,所述方法还包括:所述UFS驱动器分配扩展头字段EHS扩展域;所述UFS驱动器将所述EHS扩展域发送给所述UFS控制器;其中,所述EHS扩展域用于承载所述第一指示信息。
本申请实施例中,扩展头字段(extend header segment,EHS)扩展域至少可包括2016B的空间,该EHS扩展域可用于承载UPIU请求(command UPIU)即第一请求中的第一指示信息。具体的,通过该EHS扩展域可使得主芯片向存储芯片发送的第一指示信息中包括N个物理地址,从而避免了每次发送一个物理地址,而导致信息交互的效率低下。因此,实施本申请实施例,通过该EHS扩展域有效提高了主芯片与存储芯片之间信息交互的效率。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述方法还包括:所述主芯片接收来自所述存储芯片的所述第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为所述逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址 集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
本申请实施例中,在逻辑地址与物理地址映射关系发生变化之后,主芯片通过接收存储芯片发送的包括具有映射关系的第一逻辑地址集合与第二物理地址集合,可使得主芯片能够及时更新该主芯片中存储的逻辑地址与物理地址映射关系,从而有效提高了主芯片根据逻辑地址查找物理地址的效率。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
第二方面,本申请实施例还提供了一种信息处理方法,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的存储芯片,所述方法包括:
所述存储芯片接收来自与所述存储芯片连接的主芯片的第一请求;所述存储芯片根据第一物理地址集合获取第一数据;所述存储芯片向所述主芯片发送所述第一数据;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;其中,所述第一数据包括所述第一物理地址集合中存储的数据。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第一指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述存储芯片接收来自与所述存储芯片连接的主芯片的第 一请求之后,所述方法还包括;在所述存储芯片确定所述逻辑地址与物理地址映射关系发生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
第三方面,本申请实施例还提供了一种信息处理方法,其特征在于,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的存储芯片,所述方法包括:
所述存储芯片接收来自与所述存储芯片连接的主芯片的第二请求;所述存储芯片将第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;所述存储芯片向所述主芯片发送所述第二请求的第二响应消息;其中,所述第二请求中包括第二逻辑地址集合以及所述第二数据;所述第二数据包括待写入所述存储芯片的数据;其中,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
本申请实施例中,存储芯片通过向主芯片指示至少三个物理地址,从而在存储芯片中更新了大量映射关系的情况下,可以及时指示主芯片更新该主芯片中存储的映射关系,进而提高了映射关系更新的效率,提高了信息实时互通的效率。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三 物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
第四方面,本申请实施例还提供了一种信息处理方法,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的主芯片,所述方法包括:
所述主芯片接收来自与所述主芯片连接的存储芯片的第二响应消息;所述主芯片根据所述第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
在一种可能的实现方式中,所述主芯片接收来自与所述主芯片连接的存储芯片的第二响应消息之前,所述方法还包括:所述主芯片向所述存储芯片发送第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据。
第五方面,本申请实施例还提供了一种信息处理方法,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的主芯片,所述方法包括:
所述主芯片确定第一逻辑地址集合;所述主芯片生成第一指示信息;所述主芯片向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;其中,所 述第一请求包括所述第一指示信息。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第一请求包括读请求。
在一种可能的实现方式中,所述主芯片向与所述主芯片连接的存储芯片发送第一请求之后,方法还包括:所述主芯片接收来自所述存储芯片的第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;
其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;
或,所述第四字段用于指示所述第一逻辑地址中每个逻辑地址的访问粒度;
或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述方法还包括:所述主芯片向所述存储芯片发送第二请求;以及所述主芯片接收来自所述存储芯片的第二响应消息;所述主芯片根据第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系;其中,所述第二请求中包括第二逻辑地址集合和第二数据,所述第二数据包括待写入所述存储芯片的数据;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问 粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二请求包括写请求。
在一种可能的实现方式中,所述主芯片向与所述主芯片连接的存储芯片发送第一请求之前,所述方法还包括:所述主芯片分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述第一指示信息。
在一种可能的实现方式中,所述EHS扩展域还用于承载所述第二指示信息。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
具体的,所述主芯片包括UFS驱动器和UFS控制器,所述UFS驱动器与所述UFS控制器连接;所述主芯片向与所述主芯片连接的存储芯片发送第一请求之前,所述方法还包括:所述UFS驱动器分配扩展头字段EHS扩展域;所述UFS驱动器将所述EHS扩展域发送给所述UFS控制器。
第六方面,本申请实施例还提供了一种信息处理方法,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的存储芯片,所述方法包括:
所述存储芯片接收来自与所述存储芯片连接的主芯片的第一请求;所述存储芯片根据所述第一物理地址集合获取第一数据;所述存储芯片向所述主芯片发送所述第一数据;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;其中,所述第一数据包括所述第一物理地址集合中存储的数据。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第一指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述第一请求包括读请求。
在一种可能的实现方式中,所述存储芯片接收来自与所述存储芯片连接的主芯片的第一请求之后,所述方法还包括;在所述存储芯片确定所述逻辑地址与物理地址映射关系发 生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述方法还包括:所述存储芯片接收来自与所述存储芯片连接的主芯片的第二请求;所述存储芯片将第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;所述存储芯片向所述主芯片发送所述第二请求的第二响应消息;
其中,所述第二请求中包括第二逻辑地址集合以及所述第二数据;所述第二数据包括待写入所述存储芯片的数据;其中,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二请求包括写请求。
在一种可能的实现方式中,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第三控制信息承载于所述UPIU协议帧的第三预留字段中。
第七方面,本申请实施例提供了一种主芯片,可用于执行第一方面所述的方法,所述主芯片与通用闪存存储UFS协议信息单元UPIU连接,所述主芯片包括:
确定单元,用于确定第一逻辑地址集合;生成单元,用于生成第一指示信息;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;发送单元,用于向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一请求包括所述第一指示信息。
在一种可能的实现方式中,所述第一指示信息还包括所述N个逻辑地址与所述N个物理地址的映射关系,其中,一个逻辑地址对应一个物理地址。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述主芯片还包括:分配单元,用于分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述第一指示信息。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述主芯片还包括:接收单元,用于接收来自所述存储芯片的所述第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
第八方面,本申请实施例提供了一种存储芯片,可用于执行第二方面所述的实现方式,所述存储芯片与通用闪存存储UFS协议信息单元UPIU连接,所述存储芯片包括:接收单元,用于接收来自与所述存储芯片连接的主芯片的第一请求;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;获取单元,用于根据所述第一物理地址集合获取第一数据;其中,所述第一数据包括所述第一物理地址集合中存储的数据;发送单元,用于向所述主芯片发送所述第一数据。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第一请求承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述发送单元,还用于在确定所述逻辑地址与物理地址映射关系发生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
第九方面,本申请实施例还提供了一种存储芯片,用于执行第三方面所述的实现方式,所述存储芯片与通用闪存存储UFS协议信息单元UPIU连接,所述存储芯片包括:
接收单元,用于接收来自与所述存储芯片连接的主芯片的第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据;生成单元,用于将所述第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;其中,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;发送单元,用于向所述主芯片发送所述第二请求的第二响应消息;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
第十方面,本申请实施例还提供了一种主芯片,用于执行第四方面所述的实现方式,所述主芯片与通用闪存存储UFS协议信息单元UPIU连接,所述主芯片包括:
接收单元,用于接收来自与所述主芯片连接的存储芯片的第二响应消息;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;更新单元,用于根据所述第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问 粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
在一种可能的实现方式中,所述主芯片还包括:发送单元,用于向所述存储芯片发送第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据。
第十一方面,本申请实施例还提供了一种主芯片,用于执行第五方面所述的实现方式,所述主芯片与通用闪存存储UFS协议信息单元UPIU连接,所述主芯片包括:
确定单元,用于确定第一逻辑地址集合;生成单元,用于生成第一指示信息;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;发送单元,用于向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一请求包括所述第一指示信息。
在一种可能的实现方式中,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述主芯片还包括:分配单元,用于分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述第一指示信息。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述主芯片还包括:接收单元,用于接收来自所述存储芯片的第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为所述逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理 地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述EHS扩展域还用于承载所述第二指示信息。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
在一种可能的实现方式中,所述发送单元,还用于向所述存储芯片发送第二请求;所述主芯片还包括:接收单元,用于接收来自所述主芯片的第二响应消息;更新单元,用于根据第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系;其中,所述第二请求中包括第二逻辑地址集合和第二数据,所述第二数据包括待写入所述存储芯片的数据;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数。
在一种可能的实现方式中,所述第二响应消息中还包括第三控制信息,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述EHS扩展域还用于承载所述第三指示信息。
在一种可能的实现方式中,所述第三控制信息承载于所述UPIU协议帧的第三预留字段中。
第十二方面,本申请实施例还提供了一种存储芯片,用于执行第六方面所述的实现方式,所述存储芯片与通用闪存存储UFS协议信息单元UPIU连接,所述存储芯片包括:
接收单元,用于接收来自与所述存储芯片连接的主芯片的第一请求;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;获取单元,用于根据所述第一物理地址集合获取第一数据;其中,所述第一数据包括所述第一物理地址集合中存储的数据;发送单元,用于向所述主芯片发送所述第一数据。
在一种可能的实现方式中,所述第一请求中还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
在一种可能的实现方式中,所述第一控制信息还包括第二字段;其中,所述第二字段 用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第一指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
在一种可能的实现方式中,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
在一种可能的实现方式中,所述发送单元,还用于在确定所述逻辑地址与物理地址映射关系发生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
在一种可能的实现方式中,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
在一种可能的实现方式中,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第二指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
在一种可能的实现方式中,所述接收单元,还用于接收来自与所述存储芯片连接的主芯片的第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据;
所述存储芯片还包括:生成单元,用于将所述第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;所述发送单元,还用于向所述主芯片发送所述第二请求的第二响应消息;其中,所述第二请求中包括第二逻辑地址集合以及所述第二数据;所述第二数据包括待写入所述存储芯片的数据;其中,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
在一种可能的实现方式中,所述第二响应消息还包括第三控制信息;其中,所述第三 控制信息包括第五字段,所述第五字段用于指示所述M。
在一种可能的实现方式中,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
在一种可能的实现方式中,所述第三指示信息承载于所述EHS扩展域中。
在一种可能的实现方式中,所述第三控制信息承载于所述UPIU协议帧的第三预留字段中。
第十三方面,本申请实施例还提供了一种主芯片,所述主芯片包括处理器、存储器和通信接口,所述处理器与所述存储器、所述通信接口通过线路连接;所述存储器,用于存储程序;所述处理器,用于执行所述存储器中存储的程序,使所述处理器执行第一方面、第四方面和第五方面所描述的实现方式中相应的功能;所述通信接口用于支持所述主芯片与其他网络之间的通信。
第十四方面,本申请实施例还提供了一种存储芯片,所述存储芯片包括处理器、存储器和通信接口,所述处理器与所述存储器、所述通信接口通过线路连接;所述存储器,用于存储程序;所述处理器,用于执行所述存储器中存储的程序,使所述处理器执行第二方面、第三方面和第六方面所描述的实现方式中相应的功能;所述通信接口用于支持所述存储芯片与其他网络之间的通信。
第十五方面,本申请实施例提供了一种终端设备,所述终端设备包括主芯片和存储芯片,所述主芯片包括第七方面、第十方面和第十一方面中的一项或多项所述的主芯片;所述存储芯片包括第八方面、第九方面和第十二方面中的一项或多项所述的存储芯片。
第十六方面,本申请实施例提供了一种芯片***,所述芯片***包括主芯片和存储芯片,所述主芯片包括第七方面、第十方面和第十一方面中的一项或多项所述的主芯片;所述存储芯片包括第八方面、第九方面和第十二方面中的一项或多项所述的存储芯片。
第十七方面,本申请实施例提供一种计算机可读存储介质,所述计算机可读存储介质中存储有指令,当所述指令在计算机上运行时,使得所述计算机执行上述第一方面、第二方面、第三方面、第四方面、第五方面和第六方面中的任意一项或多项所述的方法的流程。
第十八方面,本申请实施例提供了一种计算机程序,所述计算机程序包括指令,当所述计算机程序被所述计算机执行时,使得所述计算机可以执行上述第一方面、第二方面、第三方面、第四方面、第五方面和第六方面中的任意一项或多项所述的方法的流程。
图1a是本申请实施例提供的一种处理读请求的流程示意图;
图1b是本申请实施例提供的一种处理写请求的流程示意图
图2是本申请实施例提供的一种主芯片的结构示意图;
图3是本申请实施例提供的一种存储芯片的结构示意图;
图4是本申请实施例提供的一种终端设备的结构示意图;
图5是本申请实施例提供的一种芯片***的架构示意图;
图6是本申请实施例提供的一种分配方法的流程示意图;
图7是本申请实施例提供的一种信息处理方法的流程示意图;
图8是本申请实施例提供的另一种信息处理方法的流程示意图;
图9a是本申请实施例提供的一种EHS扩展域的示意图;
图9b是本申请实施例提供的另一种EHS扩展域的示意图;
图10是本申请实施例提供的另一种主芯片的结构示意图;
图11是本申请实施例提供的又一种主芯片的结构示意图;
图12是本申请实施例提供的另一种存储芯片的结构示意图;
图13是本申请实施例提供的又一种存储芯片的结构示意图。
下面结合本申请实施例中的附图对本申请实施例进行描述。
本申请的说明书、权利要求书及附图中的术语“第一”和“第二”等是用于区别不同对象,而不是用于描述特定顺序。此外,术语“包括”和“具有”以及它们任何变形,意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、***、产品或设备没有限定于已列出的步骤或单元,而是可选地还包括没有列出的步骤或单元,或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
首先,介绍本申请涉及到的技术术语。
逻辑地址,用户程序中使用的相对地址。本申请实施例中,该逻辑地址可以包括LBA等等。
物理地址,实际存储单元的绝对地址。本申请实施例中,该物理地址可以包括PPN,也可以包括物理区块地址(physics block address,PBA),也可以包括比页(page)更小的地址等等。如比页更小的地址可以包括访问粒度为4KB的地址等等,本申请实施例不作限定。可理解,该存储单元可以包括存储芯片中的存储单元等等。
逻辑地址与物理地址映射关系,在具体应用中,该逻辑地址与物理地址映射关系存储于存储芯片中,在主芯片需要读取存储芯片中的数据时,该主芯片向该存储芯片发送包括逻辑地址的读请求;存储芯片在接收到该读请求后,根据该逻辑地址与物理地址映射关系确定该逻辑地址的物理地址;然后存储芯片将该物理地址中存储的数据发送给主芯片,如图1a所示。在主芯片需要写入数据时,该主芯片向该存储芯片发送包括逻辑地址以及待写 入的数据的写请求;存储芯片接收到该写请求之后,将该待写入的数据存储至该存储芯片中,并更新该存储芯片中存储的逻辑地址与物理地址映射关系,如图1b所示。
可选的,该逻辑地址与物理地址映射关系,也可称为逻辑地址与物理地址映射表;或者,也可称为LBA与PPN映射表;或者,也可称为LBA与PBA映射表等等,本申请实施例对于其具体名称不作限定。
本申请实施例中,该逻辑地址与物理地址映射关系既可存储于主芯片中,又可存储于存储芯片中。将该逻辑地址与物理地址映射关系存储于主芯片中,可有效避免存储芯片无法命中的情况,以及避免了存储芯片多级查找的过程等等,提高了查找效率,还提高了响应速度。可选的,存储于主芯片中的逻辑地址与物理地址映射关系也可称为逻辑地址与物理地址映射关系副本,或者也可称为逻辑地址与物理地址映射表副本等等,本申请不作限定。
以下将具体描述本申请实施例中的主芯片和存储芯片。
参见图2,图2是本申请实施例提供的一种主芯片的结构示意图,该主芯片可与通用闪存存储(universal flash storage,UFS)协议信息单元(UFS protocol information unit,UPIU)连接。如图2所示,该主芯片可包括主中央处理器(central processing unit,CPU),多媒体应用处理器(multimedia application processor,MAP),UFS主控制器,双倍速率同步动态随机存储器(double data rate synchronous dynamic random access memory,DDR SDRAM)控制器,DDR SDRAM内存,***设备控制器和***设备(peripherals)。可理解,本申请实施例中,DDR SDRAM也可简称为DDR。
其中,主CPU和MAP可用于与存储器耦合,从而执行存储器中存储的程序指令等等。如主CPU和MAP可用于运行操作***、应用、驱动等主芯片上运行的软件。本申请实施例中,该存储器还可用于存储逻辑地址与物理地址映射关系。可理解,本申请实施例中,存储器包括DDR。
UFS主控制器可用于发出符合UPIU协议帧的读请求和写请求中的一项或多项。本申请实施例中,UFS主控制器还可用于使读请求中包括的指示信息(如以下实施例中的第一指示信息等等)等承载于UFS驱动器(图中未示出)分配的EHS扩展域中,该EHS扩展域至少可包括2016B的空间。也就是说,本申请实施例中UFS主控制器发出的读请求可至少占用2KB的空间,如包括32B的UPIU帧头(UPIU frame header)和2016B的EHS扩展域。通过该EHS扩展域可使得主芯片在向存储芯片发送UPIU请求时,携带更多的物理地址信息如第一指示信息等等。
DDR控制器可用于控制DDR,如该DDR控制器可用于控制更新DDR中的逻辑地址与物理地址映射关系等等。
***设备可包括输入和输出接口、外存储器、模数转换器、数模装换器和***处理器等等。如该***设备可包括触摸屏、摄像头、指纹采集、近场通信元件和各种传感器等等,本申请实施例对于该***设备不作限定。其中,***设备控制器可用于控制该***设备。
可理解,该主芯片可以为各种形式的芯片,如该主芯片可以集成于SOC上。可选的,该主芯片可应用于各种终端设备中,如该主芯片可应用于手机或笔记本电脑中等等,本申 请实施例不作限定。
可理解,图2所示的主芯片仅为本申请实施例提供的一个例子,且该主芯片可具有比示出的部件更多或更少的部件,可以组合两个或更多个部件,或者可具有不同部件的不同配置实现等等。
参见图3,图3是本申请实施例提供的一种存储芯片的结构示意图,该存储芯片可与UPIU连接。如图3所示,该存储芯片包括控制器和缓存阵列(即flash阵列)。该控制器和该flash阵列可通过线路相互连接。
具体的,该控制器为该存储芯片的核心器件,可用于合理调配数据在各个flash阵列上的负荷,以及该控制器还可用于数据中转,连接flash阵列和外部串行接口。
可选的,该控制器还可进一步包括硬件芯片,如该硬件芯片可以是专用集成电路(application-specific integrated circuit,ASIC),或者,该硬件芯片还可以是现场可编程逻辑门阵列(field programmable gate array,FPGA)等等,本申请实施例不作限定。
进一步地,该控制器中可包括静态随机存取存储器(static random access memory,SRAM)。本申请实施例中,该SRAM可用于存储逻辑地址与物理地址映射关系。
可选的,该存储芯片可以为各种形式的芯片。可选的,该存储芯片可应用于各种存储装置中,如该存储芯片可应用于固态硬盘(solid state disk,SSD)中等等,本申请实施例不作限定。可选的,该存储芯片还可应用于各种终端设备中,如该存储芯片可应用于手机或笔记本电脑中等。
本申请实施例中,该存储芯片可接收主芯片发送的包括EHS扩展域的信息,从而利用该EHS扩展域向主芯片发送更多的包括更新的物理地址与逻辑地址映射关系的信息。
可理解,图3所示的存储芯片仅为本申请实施例提供的一个例子,且该存储芯片可具有比示出的部件更多或更少的部件,可以组合两个或更多个部件,或者可具有不同部件的不同配置实现等等。
参见图4,图4是本申请实施例提供的一种终端设备的结构示意图。如图4所示,该终端设备可包括屏幕、屏幕控制器、主芯片和UFS存储设备。其中,该主芯片可为图2所示的主芯片,如该主芯片可包括***设备、***设备控制器、DDR、DDR控制器、UFS主(host)控制器和主CPU。该UFS存储设备可为图3所示的存储芯片,其中,该UFS存储设备中包含的部件在图4中未示出。
具体的,该UFS主控制器与该UFS存储设备连接,该UFS主控制器可用于与UFS存储设备交互,从而使得该终端设备能够通过UFS主控制器读取该UFS存储设备中的数据,以及该UFS存储设备还可用于在该UFS存储设备中的数据存储发生变化的情况下,向该UFS主控制器发送用于指示更新映射关系的信息,从而使得主CPU控制DDR控制器及时更新DDR中存储的逻辑地址与物理地址映射关系。
具体的,该主CPU可以包括RISC微处理器(advanced RISC machines,ARM)等等,本申请实施例对于该主CPU的具体类型或型号不作限定。
可理解,图4所示的终端设备仅为一个示例,不应将其理解为对本申请实施例的限定。
参见图5,图5是本申请实施例提供的一种芯片***的具体场景示意图,该芯片***可包括主芯片和存储芯片。该主芯片可为图2所示的主芯片,该存储芯片可为图3所示的存储芯片。
在一种可能的实现方式中,该主芯片还可包括应用(application,APP)、UFS驱动、UFS主控制器,以及具有移动行业处理器接口(mobile industry processor interface,MIPI)传输层和MIPI物理层等等。该存储芯片还可包括存储单元、逻辑(logical units,LU)单元和设备级管理单元,以及具有MIPI物理层、MIPI传输层和缓存描述符。
如图5所示,在主芯片需要读取第一数据的情况下,主芯片从APP中获取逻辑地址,该逻辑地址经过UFS驱动发出携带该逻辑地址的读请求;该读请求通过UFS主控制器后发出符合UPIU协议帧的读请求;然后再经过传输层,如该读请求可经过MIPI统一协议(MIPI Unipro);最后经过MIPI物理层(physical layer,PHY)后,主芯片将该读请求发送给存储芯片。
该存储芯片在接收到该读请求后,可依次通过MIPI物理层和MIPI传输层,然后经过缓冲描述符之后,该读请求经过LU单元,该读请求经过LU的计算之后,存储芯片便可读取存储在存储单元中的数据。
其中,从缓冲描述符中发出的数据流,可经过LU;而从该缓存描述符中发出的控制流,可经过设备级管理单元。具体的,设备级管理单元可用于接收来自缓冲描述符发出的控制流,如该控制流可用于控制LU单元的配置等等,本申请实施例不作限定。
可理解,图5所示的芯片***仅为本申请实施例提供的一个例子,且该芯片***可具有比示出的部件更多或更少的部件,可以组合两个或更多个部件,或者可具有不同部件的不同配置实现等等。举例来说,主芯片中包括的主CPU未示出,但是不应理解为对本申请实施例的限定。
以下将具体描述本申请实施例中的信息处理方法。
在实际应用中,主芯片向存储芯片发送包括逻辑地址的读请求时,该主芯片可通过该逻辑地址的首地址+长度来指示该逻辑地址。即该主芯片可通过UFS控制器发出符合UPIU协议帧的UPIU请求(commandUPIU,CMD@UPIU)。
在一个实施例中,在将逻辑地址与物理地址映射关系存储于主芯片以及存储芯片的情况下,主芯片向存储芯片发送读请求,如该读请求可以包括4KB读请求、8KB读请求、16KB读请求和32KB读请求等等。其中,对于4KB读请求,可使用READ_10,即主芯片可向存储芯片发送包括一对逻辑地址和物理地址映射关系的读请求;其中,该一对可以包括8个字节,即4个字节的逻辑地址,4个字节的物理地址。具体的,如可以通过逻辑地址的首地址+长度,以及物理地址的首地址+长度向存储芯片指示该一对逻辑地址和物理地址映射关系。即4个字节的逻辑地址和4个字节的物理地址(一一对应)可表达4KB大小的读请求。
然而,对于8KB读请求来说,逻辑上连续的8KB的读请求,由于存储芯片不断发生垃圾回收以及磨损均衡,因此该8KB的读请求在物理上极大概率是不连续的。由此受限 CMD@UPIU原生可用空间,主芯片无法填写多对离散的物理地址。也就是说,无法支持8KB以上的读请求。
同时,在另一个实施例中,在将逻辑地址与物理地址映射关系存储于主芯片和存储芯片的情况下,在存储芯片更新该逻辑地址与物理地址映射关系之后,如存储芯片写完成之后,该存储芯片就需要将更新的逻辑地址与物理地址映射关系发送给主芯片,从而使得主芯片更新该主芯片中存储的逻辑地址与物理地址映射关系。
标准的UPIU用20个字节的Sense Data,只能最多放下两对(16字节)映射关系。由此就可能无法及时更新写请求千万的映射(mapping)关系的变更。也就是说,受限于UPIU响应(response UPIU,RESP@UPIU)原生可用空间,存储芯片向主芯片指示更新的映射关系时,无法填写多对映射关系。进一步地,在逻辑地址与物理地址映射关系大量更新时,采用上述方式可能会严重影响***性能。
因此,本申请实施例提供了一种方法,不仅可使得主芯片能够填写多对离散的物理地址,而且还可使得存储芯片能够填写多对甚至大量的映射关系。
参见图6,图6是本申请实施例提供的一种分配方法的流程示意图,该方法可应用于上述图2中所示的主芯片,图2的UFS主控制器可用于支持并执行图6所示的方法流程602。可选的,该方法还可应用于图5中所示的主芯片,如图5中的UFS驱动可用于支持并执行图6所示的方法流程601,以及UFS主控制器可用于支持并执行图6所示的方法流程602。如图6所示,该分配方法包括:
601、UFS驱动器分配EHS扩展域。
本申请实施例中,该EHS扩展域也可称为EHS扩展空间。或者该EHS扩展域还可包括其他名称等等,本申请实施例不作限定。具体的,该EHS扩展域至少可包括2016B的扩展空间。更具体的,该EHS扩展域可以通过主芯片的UFS驱动软件来分配,如该驱动软件可包括华为麒麟平台的kirin UFS驱动等等。
602、UFS驱动器将EHS扩展域发送给UFS控制器。
其中,该EHS扩展域用于承载主芯片发出的读请求和写请求中的一项或多项。也就是说,该EHS扩展域可用于指示UFS控制器承载符合UPIU协议帧的UPIU请求如读请求中包括的第一指示信息等等。
可选的,对于UFS驱动器如何将EHS扩展域发送给UFS控制器,本申请实施例还提供了两种实现方式,分别如下所示:
实现方式一、
UFS驱动器将该EHS扩展域的首地址发送给该UFS控制器。
该实现方式中,主芯片可提前设置或规划好EHS扩展域的长度。进一步地,主芯片还可与存储芯片提前协议(或协商)该EHS扩展域的长度。举例来说,主芯片可与存储芯片提高协议该EHS扩展域的长度为2016B。
实现方式二、
UFS驱动器将该EHS扩展域的首地址以及长度发送给该UFS控制器。
该实现方式中,该EHS扩展域的长度可以发生变化,即主芯片可根据需要来设置该EHS扩展域的长度。
可理解,在主芯片向存储芯片发送读请求或写请求后,该存储芯片还可返回响应消息,如以下实施例中的第一响应消息和第二响应消息。其中,该第一响应消息中的第二指示信息和第二响应消息中的第三指示信息还可承载于该EHS扩展域中。
具体的,在主芯片发出读请求时,该读请求中的第一指示信息承载在的EHS扩展域,可与存储芯片返回第一响应消息中的第二指示信息(或第二响应消息中的第三指示信息)承载在的EHS扩展域相同,或者,也可不同等,本申请实施例不作限定。可理解,EHS扩展域相同可表示格式相同,并不表示该EHS扩展域中填写的内容相同。
进一步地,在主芯片向存储芯片发送读请求时,该读请求(如第一请求)中的第一控制信息可承载于UPIU协议帧的第一预留字段中,以及该存储芯片返回的第一响应消息中的第二控制信息可承载于该UPIU协议帧的第二预留字段中,以及该存储芯片返回的第二响应消息中的第三控制信息可承载于该UPIU协议帧的第三预留字段中。
可理解,其中,第二预留字段和第三预留字段可为同一个字段,也可为不同的字段等,本申请实施例不作限定。以及第一控制信息所承载在的UPIU协议帧可以与第二控制信息所承载在的UPIU协议帧为同一个UPIU协议帧,或者,也可为不同的UPIU协议帧等,本申请实施例不作限定。以及第一控制信息所承载在的UPIU协议帧可以与第三控制信息所承载在的UPIU协议帧为同一个UPIU协议帧,或者,也可为不同的UPIU协议帧等,本申请实施例不作限定。因此,第一预留字段与第二预留字段(或第三预留字段)也可为同一个字段,也可为不同的字段等,本申请实施例不作限定。
可理解,本申请实施例中的UFS控制器可以为图2、图4和图5所示的UFS主控制器,因此,不应将该UFS控制器理解为对本申请实施例的限定。
在图6所示的分配方法的基础上,参见图7,图7是本申请实施例提供的一种信息处理方法的流程示意图,该信息处理方法可应用于图2至图5所示的主芯片和存储芯片。如该方法可应用于上述图2中所示的主芯片,图2的主CPU可用于支持并执行图7所示的方法流程701、702和706。又如图3的控制器可用于支持并执行图7所示的方法流程704。如图7所示,该信息处理方法包括:
701、主芯片确定第一逻辑地址集合。
本申请实施例中,该主芯片确定的第一逻辑地址集合至少可对应8KB的读请求。可理解,该第一逻辑地址集合中包含的逻辑地址可以是连续的,或者,该第一逻辑地址集合中包含的逻辑地址还可是不连续的,本申请实施例不作限定。
702、主芯片生成第一指示信息;其中,该第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与该第一逻辑地址集合对应的第一物理地址集合,该第一物理地址集合包括N个物理地址,且该N个物理地址与该第一逻辑地址集合包括的N个逻辑地址一一对应。
本申请实施例中,该第一物理地址集合可包括N个离散的物理地址。具体的,该第一物理地址集合中包括多少个物理地址,该主芯片便可将该第一逻辑地址集合划分为多少个逻辑地址。举例来说,该第一物理地址集合中包括N个物理地址,则与该N个物理地址中每个物理地址都对应一个逻辑地址,则该第一逻辑地址集合(如该第一逻辑地址集合中包 括的逻辑地址是连续的)可分为N个逻辑地址,且该N个逻辑地址分别与该N个物理地址对应。即一个物理地址对应一个逻辑地址。可理解,N为大于或等于2的整数。
703、主芯片向与该主芯片连接的存储芯片发送第一请求,该第一请求包括第一指示信息。
本申请实施例中,该第一请求可用于请求读与第一逻辑地址集合对应的数据。即该第一请求可用于请求第一数据,该第一数据包括第一物理地址集合中存储的数据。
进一步地,该第一请求中还可包括第一控制信息,该第一控制信息中包括第一字段,该第一字段用于指示N。其中,该N既可以表示第一物理地址集合中离散的物理地址的个数,还可以表示划分第一逻辑地址集合后该第一逻辑地址集合中的逻辑地址的个数。具体的,该N为大于或等于2的整数。
更进一步地,该第一控制信息还包括第二字段;其中,该第二字段用于指示该第一物理地址集合中每个物理地址的访问粒度;或,该第二字段用于指示该第一逻辑地址集合中每个逻辑地址的访问粒度;或,该第二字段用于指示该第一物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度的和;该第一物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度相同。
本申请实施例中,该访问粒度即可表示第一指示信息中存放每个地址的单位。更通俗的说,该访问粒度可表示存放每个逻辑地址或存放每个物理地址的字节数是多少。如前述实施,一对逻辑地址与物理地址的映射关系,可包括8个字节,即4个字节的逻辑地址和4个字节的物理地址。其中,访问粒度即可用4个字节来表示,或者,访问粒度也可用8个字节来表示。
本申请实施例中,第一物理地址集合中包括N个物理地址,第一逻辑地址集合中包括N个逻辑地址,即表示有N个映射关系,则可使用8个字节来分别表达N个映射关系中的每对映射关系。
可理解,以上访问粒度仅为一种示例,还可使用比4个字节(每个物理地址的访问粒度或每个逻辑地址的访问粒度)更多或更少的字节来表达该访问粒度,或者,还可使用比8个字节(即每个物理地址的访问粒度与每个逻辑地址的访问粒度的和)更多或更少的字节来表达该访问粒度,本申请实施例不作限定。
可理解,第一指示信息可承载于主芯片分配的EHS扩展域中,以及第一控制信息可承载于UPIU协议帧的第一预留字段中。
704、存储芯片接收来自主芯片的第一请求,根据第一物理地址集合获取第一数据,该第一数据包括该第一物理地址集合中存储的数据。
本申请实施例中,在存储芯片接收到该第一请求后,若该存储芯片中的逻辑地址与物理地址映射关系未发生变化,则该存储芯片可向主芯片返回第一数据,即该存储芯片向该主芯片发送该第一数据。具体的,在存储芯片向主芯片发送该第一数据的情况下,该存储芯片可以将该第一数据承载在UPIU协议帧以及EHS扩展域之外的其他空间中,如该存储芯片可将该N个物理地址中存储的数据(可能为N个数据,也可能为小于N个的数据)整合为一份数据,从而承载在数据空间中发送给主芯片。可理解,第一数据承载在的数据空间仅为一种示例,在具体实现中,可能还包括其他实现方式等等,本申请实施例不作限定。
本申请实施例中,一方面,通过将逻辑地址与物理地址映射关系存储于空间较大的主芯片中,可有效提高读请求的响应速度;另一方面,通过生成第一指示信息,该第一指示信息可用于指示第一物理地址集合,该第一物理地址集合中至少包括两个物理地址,从而可以实现8KB、16KB甚至32KB的读请求,进而有效实现了主芯片和存储芯片之间实时信息交互的效率。
然而,在实际应用中,由于磨损均衡(wear leveling,WL),又或者,垃圾回收(garbage collection,GC)等操作,存储芯片中存储的数据的物理地址可能会发生变化。因此,存储芯片在确定发生变化后的逻辑地址与物理地址映射关系后,还需要将该变化告诉主芯片,以提高信息交互的效率。对于上述情况参考以下步骤。
705、存储芯片确定逻辑地址与物理地址映射关系发生变化的情况下,向主芯片发送第一响应消息。
其中,该该第一响应消息包括第二指示信息,该第二指示信息包括第一逻辑地址集合与第二物理地址集合;该第二物理地址集合为逻辑地址与物理地址映射关系更新后,与该第一逻辑地址集合对应的物理地址集合;该第二物理地址集合包括N个物理地址,且该N个物理地址与该N个逻辑地址一一对应。且该第二指示信息还可用于指示主芯片更新该主芯片中的逻辑地址与物理地址映射关系。
进一步的,该第一响应消息还包括第二控制信息;其中,该第二控制信息中包括第三字段,该第三字段用于指示该N。
更进一步的,该第二控制信息还包括第四字段;其中,该第四字段用于指示该第二物理地址集合中每个物理地址的访问粒度;或,该第四字段用于指示该第一逻辑地址集合中每个逻辑地址的访问粒度;或,该第四字段用于指示该第二物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,该第二物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度相同。706、主芯片接收第一响应消息,根据该第二指示信息更新该主芯片中的逻辑地址与物理地址映射关系。
可理解,第二指示信息可承载于EHS扩展域中,第二控制信息可承载于UPIU协议帧的第二预留字段中。
本申请实施例中,通过向存储芯片指示N个逻辑地址与N个物理地址的映射关系,还可避免存储芯片中存储的逻辑地址与物理地址映射关系发生变化,而导致存储芯片无法仅仅根据物理地址而确定相应的数据(第一数据);从而进一步提高了主芯片与存储芯片之间信息交互的效率。
以上重点介绍了读请求的具体实现方式,以下将重点介绍写请求的具体实现方式。
参见图8,图8是本申请实施例提供的另一种信息处理方法的流程示意图,该信息处理方法可应用于图2至图5所示的主芯片和存储芯片。如图8所示,该信息处理方法包括:
801、主芯片向与该主芯片连接的存储芯片发送第二请求;其中,该第二请求中包括第二逻辑地址集合和第二数据,该第二数据包括待写入该存储芯片的数据。
本申请实施例中,第二逻辑地址集合即为第二数据的逻辑地址。该第二数据包括待写 入存储芯片中的数据。可理解,本申请实施例对于该第二数据的大小或类型不作限定。
802、存储芯片接收来自主芯片的第二请求,将第二数据写入该存储芯片。
803、存储芯片根据变化后的逻辑地址与物理地址映射关系生成第三指示信息。
本申请实施例中,在存储芯片将第二数据写入到该存储芯片后,该存储芯片便可以根据第二数据的物理地址以及该第二数据的逻辑地址生成第三指示信息。其中,该第三指示信息包括第二逻辑地址集合以及与该第二逻辑地址集合对应的第三物理地址集合,该第三物理地址集合包括M个物理地址,且该M个物理地址与该第二逻辑地址集合包括的M个逻辑地址一一对应,以及该第三物理地址集合用于存储第二数据,M为大于或等于3的整数。
其中,第三物理地址集合中至少可包括三个离散的物理地址。具体的,该第三物理地址集合中包括多少(如M)个物理地址,该存储芯片便可将该第二逻辑地址集合划分为多少(如M)个逻辑地址。可理解,一个物理地址对应一个逻辑地址,由此,第三指示信息中包括了具有映射关系的第三物理地址集合与第二逻辑地址集合。
804、存储芯片向主芯片发送第二请求的第二响应消息;其中,该第二响应消息中包括第三指示信息,该第二响应消息用于指示更新主芯片中的逻辑地址与物理地址映射关系。
进一步的,该第二响应消息还包括第三控制信息;
其中,该第三控制信息包括第五字段,该第五字段用于指示该M。
更进一步的,该第三控制信息还包括第六字段;其中,该第六字段用于指示该第三物理地址集合中每个物理地址的访问粒度;或,该第六字段用于指示该第二逻辑地址集合中每个逻辑地址的访问粒度;或,该第六字段用于指示该第三物理地址集合中每个物理地址的访问粒度与该第二逻辑地址集合中每个逻辑地址的访问粒度之和;该第三物理地址集合中每个物理地址的访问粒度与该第二逻辑地址集合中每个逻辑地址的访问粒度相同。
可理解,对于访问粒度的具体描述可参考图7所示的实现方式,这里不再一一详述。
805、主芯片接收来自存储芯片的第二响应消息,根据该第二响应消息中的第三指示信息更新逻辑地址与物理地址映射关系。
举例来说,逻辑地址与物理地址映射关系可存储在DDR空间中,主芯片接收到该第二响应消息之后,可以从UPIU中解析出更新后的映射关系,从而将该更新后的映射关系同步更新到主芯片的DDR空间中的逻辑地址与物理地址映射关系。
其中,第三指示信息可承载于EHS扩展域中,以及第三控制信息可承载于UPIU协议帧的第三预留字段中。
实施本申请实施例,在存储芯片中更新了大量映射关系的情况下,该存储芯片可及时向主芯片指示更新的映射关系,提高了信息实时交互的效率。
可理解,以上所示的实施例中的方法各有侧重,其中一个实施例中未详尽描述的实现方式,还可参考其他实施例,这里不再一一详述。
可理解,图7和图8所示的第一指示信息、第二指示信息和第三指示信息可承载于图6所示的EHS扩展域中。更具体的第一指示信息可承载于承载UPIU请求的EHS扩展域中。以及第二指示信息和第三指示信息可承载于承载UPIU响应的EHS扩展域中。
为更形象的理解本申请实施例所提供的方法,以下将结合具体场景来说明。
参见图9a,图9a是本申请实施例提供的一种EHS扩展域的结构示意图,该EHS扩展域可用于承载第一指示信息。
如图9a所示,标号32即为本申请实施例所提供的EHS扩展域,可用于承载第一指示信息。进一步地,标号5、标号6或标号7中的一项或多项即可为UPIU协议帧中的第一预留字段,如以标号5为例,该标号5可用于承载访问粒度,以及标号8可用于承载个数。也就是说,标号5即为本申请实施例所提供的第二字段,该标号5中中可用于承载第一物理地址集合中每个物理地址的访问粒度,或第一逻辑地址集合中每个逻辑地址的访问粒度,或第一物理地址集合中每个物理地址的访问粒度与第一逻辑地址集合中每个逻辑地址的访问粒度的和。该标号8即为本申请实施例所提供的第一字段,该标号8可用于承载个数N。标号32中可用于承载本申请实施例中的第一逻辑地址集合和第一物理地址集合,如图9a所示。
可理解,本申请实施例对于图9a所示的UPIU协议帧的其他字段或标号所指示或承载的内容不作限定。
参见图9b,图9b是本申请实施例提供的另一种EHS扩展域的结构示意图,该EHS扩展域可用于承载第二指示信息或第三指示信息。
如图9b所示,标号32即为本申请实施例所提供的EHS扩展域,可用于承载第二指示信息或第三指示信息。进一步地,标号5或标号6中的一项或多项即可为UPIU协议帧中的第二预留字段或第三预留字段,如以该EHS扩展域承载第二指示信息,标号5为UPIU协议帧中的第二预留字段为例,该标号5可用于承载访问粒度,标号8可用于承载个数。也就是说,标号5即为本申请实施例中的第四字段。标号5中可用于承载本申请实施例中的第二物理地址集合中每个物理地址的访问粒度,或第一逻辑地址集合中每个逻辑地址的访问粒度,或,每个第二物理地址集合中每个物理地址的访问粒度与每个第一逻辑地址集合中每个逻辑地址的访问粒度的和。又如以该EHS扩展域承载第三指示信息,以标号5为UPIU协议帧中的第三预留字段为例,该标号5即为本申请实施例中的第六字段,标号5中可用于承载本申请实施例中的第三物理地址集合中每个物理地址的访问粒度,或者,第二逻辑地址集合中每个逻辑地址的访问粒度,或者,第三物理地址集合中每个物理地址的访问粒度与第二逻辑地址集合中每个逻辑地址的访问粒度的和。
标号8即为本申请实施例中的第三字段或第五字段,该标号8可用于承载N或M。
标号32中可用于承载第二指示信息或第三指示信息。即该标号32中可用于承载具有映射关系的第一逻辑地址集合与第二物理地址集合,或者还可用于承载具有映射关系的第二逻辑地址集合与第三物理地址集合,如图9b所示。
可理解,本申请实施例对于该UPIU协议帧中的其他字段或标号所指示或承载的内容不作限定。
上述详细阐述了本申请实施例的方法,下面提供了本申请实施例的装置。
参见图10,图10是本申请实施例提供的一种主芯片的结构示意图,该主芯片可用于 执行图6至图8所示的方法。如图10所示,该主芯片包括:
确定单元1001,用于确定第一逻辑地址集合;
生成单元1002,用于生成第一指示信息;其中,该第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与该第一逻辑地址集合对应的第一物理地址集合,该第一物理地址集合包括N个物理地址,且该N个物理地址与该第一逻辑地址集合包括的N个逻辑地址一一对应,该N为大于或等于2的整数;
发送单元1003,用于向与主芯片连接的存储芯片发送第一请求;其中,该第一请求包括第一指示信息。
可理解,图2所示的主CPU可用于执行该确定单元1001以及生成单元1002所示的实现方式。以及在一种可能的实现方式中,主CPU还可用于控制UFS主控制器,从而来执行发送单元1003所示的实现方式。
实施本申请实施例,一方面,通过将逻辑地址与物理地址映射关系存储于空间较大的主芯片中,可有效提高读请求的响应速度;另一方面,通过生成第一指示信息,该第一指示信息可用于指示第一物理地址集合,该第一物理地址集合中至少包括两个物理地址,从而可以实现8KB、16KB甚至32KB的读请求,进而有效实现了主芯片和存储芯片之间实时信息交互的效率。
具体的,该第一请求还包括第一控制信息;其中,该第一控制信息中包括第一字段,第一字段用于指示N。
具体的,第一控制信息还包括第二字段;
其中,第二字段用于指示第一物理地址集合中每个物理地址的访问粒度;
或,第二字段用于指示第一逻辑地址集合中每个逻辑地址的访问粒度;
或,第二字段用于指示第一物理地址集合中每个物理地址的访问粒度与第一逻辑地址集合中每个逻辑地址的访问粒度的和;第一物理地址集合中每个物理地址的访问粒度与第一逻辑地址集合中每个逻辑地址的访问粒度相同。
具体的,如图11所示,该主芯片还包括:
分配单元1104,用于分配扩展头字段EHS扩展域;其中,EHS扩展域用于承载第一指示信息。
具体的,第一控制信息可承载于UPIU协议帧的第一预留字段中。
可选的,如图11所示,该主芯片还包括:
接收单元1105,用于接收来自存储芯片的第一响应消息;
其中,该第一响应消息包括第二指示信息,该第二指示信息包括第一逻辑地址集合与第二物理地址集合;该第二物理地址集合为逻辑地址与物理地址映射关系更新后,与该第一逻辑地址集合对应的物理地址集合;该第二物理地址集合包括N个物理地址,且N个物理地址与N个逻辑地址一一对应。
具体的,该第一响应消息还包括第二控制信息;其中,该第二控制信息中包括第三字段,该第三字段用于指示该N。
具体的,该第二控制信息还包括第四字段;其中,该第四字段用于指示该第二物理地址集合中每个物理地址的访问粒度;或,该第四字段用于指示该第一逻辑地址中每个逻辑 地址的访问粒度;或,该第四字段用于指示该第二物理地址集合中每个物理地址的访问粒度与该第一逻辑地址中每个逻辑地址的访问粒度的和;其中,该第二物理地址集合中每个物理地址的访问粒度与该第一逻辑地址中每个逻辑地址的访问粒度相同。
具体的,该第二指示信息可承载于EHS扩展域中,以及该第二控制信息可承载于UPIU协议帧的第二预留字段中。
可选的,发送单元1103,还用于向存储芯片发送第二请求;其中,该第二请求中包括第二逻辑地址集合以及第二数据,该第二数据包括待写入该存储芯片的数据。
具体的,该第二请求可用于请求将第二数据写入存储芯片。
可选的,接收单元1105,还可用于接收来自与主芯片连接的存储芯片的第二响应消息;其中,第二响应消息中包括第三指示信息,第三指示信息包括第二逻辑地址集合以及与该第二逻辑地址集合对应的第三物理地址集合,该第三物理地址集合包括M个物理地址,且该M个物理地址与该第二逻辑地址集合包括的M个逻辑地址一一对应,以及该第三物理地址集合用于存储该第二数据,M为大于或等于3的整数;
如图11所示,该主芯片还包括:
更新单元1106,用于根据第三指示信息更新主芯片中的逻辑地址与物理地址映射关系。
具体的,该第二响应消息中还包括第三控制信息,该第三控制信息包括第五字段,该第五字段用于指示该M。
具体的,该第三控制信息还包括第六字段;其中,该第六字段用于指示该第三物理地址集合中每个物理地址的访问粒度;或,该第六字段用于指示该第二逻辑地址集合中每个逻辑地址的访问粒度;或,该第六字段用于指示该第三物理地址集合中每个物理地址的访问粒度与该第二逻辑地址集合中每个逻辑地址的访问粒度之和;该第三物理地址集合中每个物理地址的访问粒度与该第二逻辑地址集合中每个逻辑地址的访问粒度相同。
具体的,第三指示信息还可承载于EHS扩展域中,以及第三控制信息还可承载于UPIU协议帧的第三预留字段中。
具体的,图2所示的主CPU还可用于执行该更新单元1106所示的实现方式等等,以及在一种可能的实现方式中,主CPU还可用于控制UFS主控制器执行接收单元1105所示的实现方式等等,本申请实施例不作限定。
可理解,图10和图11所示的主芯片的具体实现方式,还可对应参考前述实施例中的具体实现方式,这里不再一一详述。
参见图12,图12是本申请实施例提供的一种存储芯片的结构示意图,该存储芯片可用于执行图6至图8所示的方法。如图12所示,该存储芯片包括:
接收单元1201,用于接收来自与存储芯片连接的主芯片的第一请求;其中,该第一请求包括第一指示信息,该第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与该第一逻辑地址集合对应的第一物理地址集合,且该第一物理地址集合包括N个物理地址,该N个物理地址与该第一逻辑地址集合包括的N个逻辑地址一一对应,该N为大于或等于2的整数;
获取单元1202,用于根据第一物理地址集合获取第一数据;其中,该第一数据包括第 一物理地址集合中存储的数据;
发送单元1203,用于向主芯片发送第一数据。
可理解,图3所示的存储芯片中的控制器可用于执行获取单元1202所执行的方法。以及该存储芯片中的外部串行接口等(图3中未示出)可用于执行接收单元1201和发送单元1203所执行的方法。
具体的,该第一请求中还包括第一控制信息;其中,该第一控制信息中包括第一字段,该第一字段用于指示该N。
具体的,该第一控制信息还包括第二字段;其中,该第二字段用于指示该第一物理地址集合中每个物理地址的访问粒度;或,该第二字段用于指示该第一逻辑地址集合中每个逻辑地址的访问粒度;或,该第二字段用于指示该第一物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度的和;该第一物理地址集合中每个物理地址的访问粒度与该第一逻辑地址集合中每个逻辑地址的访问粒度相同。
具体的,该第一指示信息可承载于扩展头字段EHS扩展域中,该EHS扩展域由主芯片分配。以及该第一控制信息可承载于UPIU协议帧的第一预留字段中。
可选的,发送单元1203,还用于在确定逻辑地址与物理地址映射关系发生变化的情况下,向主芯片发送第一响应消息;
其中,该第一响应消息包括第二指示信息,该第二指示信息包括第一逻辑地址集合与第二物理地址集合;该第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与该第一逻辑地址集合对应的物理地址集合;该第二物理地址集合包括N个物理地址,且N个物理地址与N个逻辑地址一一对应。
具体的,第一响应消息还包括第二控制信息;其中,第二控制信息中包括第三字段,第三字段用于指示N。
具体的,第二控制信息还包括第四字段;其中,第四字段用于指示第二物理地址集合中每个物理地址的访问粒度;或,第四字段用于指示第一逻辑地址集合中每个逻辑地址的访问粒度;或,第四字段用于指示第二物理地址集合中每个物理地址的访问粒度与第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,第二物理地址集合中每个物理地址的访问粒度与第一逻辑地址集合中每个逻辑地址的访问粒度相同。
可选的,接收单元1201,还用于接收来自与存储芯片连接的主芯片的第二请求;其中,第二请求中包括第二逻辑地址集合以及第二数据,第二数据包括待写入存储芯片的数据;
如图13所示,该存储芯片还包括:
生成单元1204,用于将第二数据写入存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;其中,第三指示信息包括第二逻辑地址集合以及与该第二逻辑地址集合对应的第三物理地址集合,该第三物理地址集合包括M个物理地址,且该M个物理地址与该第二逻辑地址集合包括的M个逻辑地址一一对应,以及该第三物理地址集合用于存储该第二数据,该M为大于或等于3的整数;
发送单元1203,用于向主芯片发送第二请求的第二响应消息;其中,第二响应消息包括第三指示信息,第二响应消息用于指示更新主芯片中的逻辑地址与物理地址映射关系。
具体的,第二响应消息还包括第三控制信息;其中,第三控制信息包括第五字段,第 五字段用于指示M。
具体的,第三控制信息还包括第六字段;其中,第六字段用于指示第三物理地址集合中每个物理地址的访问粒度;或,第六字段用于指示第二逻辑地址集合中每个逻辑地址的访问粒度;或,第六字段用于指示第三物理地址集合中每个物理地址的访问粒度与第二逻辑地址集合中每个逻辑地址的访问粒度之和;第三物理地址集合中每个物理地址的访问粒度与第二逻辑地址集合中每个逻辑地址的访问粒度相同。
具体的,该第三指示信息也可承载于EHS扩展域中。以及该第三控制信息可承载于UPIU协议帧的第三预留字段中。
可理解,图12和图13所示的存储芯片的具体实现方式,还可对应参考前述实施例中的具体实现方式,这里不再一一详述。
本领域普通技术人员可以理解实现上述实施例方法中的全部或部分流程,该流程可以由计算机程序来指令相关的硬件完成,该程序可存储于计算机可读取存储介质中,该程序在执行时,可包括如上述各方法实施例的流程。而前述的存储介质包括:ROM或随机存储记忆体RAM、磁碟或者光盘等各种可存储程序代码的介质。
Claims (62)
- 一种信息处理方法,其特征在于,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的主芯片,所述方法包括:所述主芯片确定第一逻辑地址集合;所述主芯片生成第一指示信息;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;所述主芯片向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一请求包括所述第一指示信息。
- 根据权利要求1所述的方法,其特征在于,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
- 根据权利要求2所述的方法,其特征在于,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求1至3任意一项所述的方法,其特征在于,所述主芯片向与所述主芯片连接的存储芯片发送第一请求之前,所述方法还包括:所述主芯片分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述第一指示信息。
- 根据权利要求2至4任意一项所述的方法,其特征在于,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
- 根据权利要求5所述的方法,其特征在于,所述主芯片向与所述主芯片连接的存储芯片发送第一请求之后,所述方法还包括:所述主芯片接收来自所述存储芯片的第一响应消息,所述第一响应消息为所述第一请求的响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为所述逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
- 根据权利要求6所述的方法,其特征在于,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
- 根据权利要求7所述的方法,其特征在于,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度相同。
- 根据权利要求6至8任意一项所述的方法,其特征在于,所述第二指示信息承载于所述EHS扩展域中。
- 根据权利要求7至9任意一项所述的方法,其特征在于,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
- 一种信息处理方法,其特征在于,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的存储芯片,所述方法包括:所述存储芯片接收来自与所述存储芯片连接的主芯片的第一请求;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;所述存储芯片根据所述第一物理地址集合获取第一数据;其中,所述第一数据包括所述第一物理地址集合中存储的数据;所述存储芯片向所述主芯片发送所述第一数据。
- 根据权利要求11所述的方法,其特征在于,所述第一请求中还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
- 根据权利要求12所述的方法,其特征在于,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求11至13任意一项所述的方法,其特征在于,所述第一指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求12至14任意一项所述的方法,其特征在于,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
- 根据权利要求15所述的方法,其特征在于,所述存储芯片接收来自与所述存储芯片连接的主芯片的第一请求之后,所述方法还包括:在所述存储芯片确定所述逻辑地址与物理地址映射关系发生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
- 根据权利要求16所述的方法,其特征在于,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
- 根据权利要求17所述的方法,其特征在于,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求16至18任意一项所述的方法,其特征在于,所述第二指示信息承载于所述EHS扩展域中。
- 根据权利要求17至19任意一项所述的方法,其特征在于,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
- 一种信息处理方法,其特征在于,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的存储芯片,所述方法包括:所述存储芯片接收来自与所述存储芯片连接的主芯片的第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据;所述存储芯片将所述第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;其中,所述第三指示信息包括所述第二逻辑地址集合以 及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;所述存储芯片向所述主芯片发送所述第二请求的第二响应消息;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
- 根据权利要求21所述的方法,其特征在于,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
- 根据权利要求22所述的方法,其特征在于,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求21至23任意一项所述的方法,其特征在于,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求22至24任意一项所述的方法,其特征在于,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
- 一种信息处理方法,其特征在于,所述方法应用于通用闪存存储UFS协议信息单元UPIU连接的主芯片,所述方法包括:所述主芯片接收来自与所述主芯片连接的存储芯片的第二响应消息;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;所述主芯片根据所述第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系。
- 根据权利要求26所述的方法,其特征在于,所述第二响应消息中还包括第三控制信息,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
- 根据权利要求27所述的方法,其特征在于,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求26至28任意一项所述的方法,其特征在于,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求27至29任意一项所述的方法,其特征在于,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
- 根据权利要求26至30任意一项所述的方法,其特征在于,所述主芯片接收来自与所述主芯片连接的存储芯片的第二响应消息之前,所述方法还包括:所述主芯片向所述存储芯片发送第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据。
- 一种主芯片,其特征在于,所述主芯片与通用闪存存储UFS协议信息单元UPIU连接,所述主芯片包括:确定单元,用于确定第一逻辑地址集合;生成单元,用于生成第一指示信息;其中,所述第一指示信息包括所述第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,所述第一物理地址集合包括N个物理地址,且所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;发送单元,用于向与所述主芯片连接的存储芯片发送第一请求;其中,所述第一请求包括所述第一指示信息。
- 根据权利要求32所述的主芯片,其特征在于,所述第一请求还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
- 根据权利要求33所述的主芯片,其特征在于,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求32至34任意一项所述的主芯片,其特征在于,所述主芯片还包括:分配单元,用于分配扩展头字段EHS扩展域;其中,所述EHS扩展域用于承载所述 第一指示信息。
- 根据权利要求33至35任意一项所述的方法,其特征在于,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
- 根据权利要求36所述的主芯片,其特征在于,所述主芯片还包括:接收单元,用于接收来自所述存储芯片的所述第一响应消息,所述第一响应消息为所述第一请求的响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为所述逻辑地址与物理地址映射关系更新后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
- 根据权利要求37所述的主芯片,其特征在于,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
- 根据权利要求38所述的主芯片,其特征在于,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址中每个逻辑地址的访问粒度相同。
- 根据权利要求37至39任意一项所述的方法,其特征在于,所述第二指示信息承载于所述EHS扩展域中。
- 根据权利要求38至40任意一项所述的方法,其特征在于,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
- 一种存储芯片,其特征在于,所述存储芯片与通用闪存存储UFS协议信息单元UPIU连接,所述存储芯片包括:接收单元,用于接收来自与所述存储芯片连接的主芯片的第一请求;其中,所述第一请求包括第一指示信息,所述第一指示信息包括第一逻辑地址集合以及根据逻辑地址与物理地址映射关系确定的与所述第一逻辑地址集合对应的第一物理地址集合,且所述第一物理地址集合包括N个物理地址,所述N个物理地址与所述第一逻辑地址集合包括的N个逻辑地址一一对应,所述N为大于或等于2的整数;获取单元,用于根据所述第一物理地址集合获取第一数据;其中,所述第一数据包括所述第一物理地址集合中存储的数据;发送单元,用于向所述主芯片发送所述第一数据。
- 根据权利要求42所述的存储芯片,其特征在于,所述第一请求中还包括第一控制信息;其中,所述第一控制信息中包括第一字段,所述第一字段用于指示所述N。
- 根据权利要求43所述的存储芯片,其特征在于,所述第一控制信息还包括第二字段;其中,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度;或,所述第二字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第二字段用于指示所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;所述第一物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求42至44任意一项所述的存储芯片,其特征在于,所述第一指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求43至45任意一项所述的存储芯片,其特征在于,所述第一控制信息承载于UPIU协议帧的第一预留字段中。
- 根据权利要求46所述的存储芯片,其特征在于,所述发送单元,还用于在确定所述逻辑地址与物理地址映射关系发生变化的情况下,向所述主芯片发送第一响应消息;其中,所述第一响应消息包括第二指示信息,所述第二指示信息包括所述第一逻辑地址集合与第二物理地址集合;所述第二物理地址集合为逻辑地址与物理地址映射关系发生变化后,与所述第一逻辑地址集合对应的物理地址集合;所述第二物理地址集合包括N个物理地址,且所述N个物理地址与所述N个逻辑地址一一对应。
- 根据权利要求47所述的存储芯片,其特征在于,所述第一响应消息还包括第二控制信息;其中,所述第二控制信息中包括第三字段,所述第三字段用于指示所述N。
- 根据权利要求48所述的存储芯片,其特征在于,所述第二控制信息还包括第四字段;其中,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度;或,所述第四字段用于指示所述第一逻辑地址集合中每个逻辑地址的访问粒度;或,所述第四字段用于指示所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度的和;其中,所述第二物理地址集合中每个物理地址的访问粒度与所述第一逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求47至49任意一项所述的存储芯片,其特征在于,所述第二指示信息承载于所述EHS扩展域中。
- 根据权利要求48至50任意一项所述的存储芯片,其特征在于,所述第二控制信息承载于所述UPIU协议帧的第二预留字段中。
- 一种存储芯片,其特征在于,所述存储芯片与通用闪存存储UFS协议信息单元UPIU连接,所述存储芯片包括:接收单元,用于接收来自与所述存储芯片连接的主芯片的第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据;生成单元,用于将所述第二数据写入所述存储芯片之后,根据变化后的逻辑地址与物理地址映射关系生成第三指示信息;其中,所述第三指示信息包括所述第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;发送单元,用于向所述主芯片发送所述第二请求的第二响应消息;其中,所述第二响应消息包括所述第三指示信息,所述第二响应消息用于指示更新所述主芯片中的逻辑地址与物理地址映射关系。
- 根据权利要求52所述的存储芯片,其特征在于,所述第二响应消息还包括第三控制信息;其中,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
- 根据权利要求53所述的存储芯片,其特征在于,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求52至54任意一项所述的存储芯片,其特征在于,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求53至55任意一项所述的存储芯片,其特征在于,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
- 一种主芯片,其特征在于,所述主芯片与通用闪存存储UFS协议信息单元UPIU连接,所述主芯片包括:接收单元,用于接收来自与所述主芯片连接的存储芯片的第二响应消息;其中,所述第二响应消息中包括第三指示信息,所述第三指示信息包括第二逻辑地址集合以及与所述第二逻辑地址集合对应的第三物理地址集合,所述第三物理地址集合包括M个物理地址,且所述M个物理地址与所述第二逻辑地址集合包括的M个逻辑地址一一对应,以及所述第三物理地址集合用于存储所述第二数据,所述M为大于或等于3的整数;更新单元,用于根据所述第三指示信息更新所述主芯片中的逻辑地址与物理地址映射关系。
- 根据权利要求57所述的主芯片,其特征在于,所述第二响应消息中还包括第三控制信息,所述第三控制信息包括第五字段,所述第五字段用于指示所述M。
- 根据权利要求58所述的主芯片,其特征在于,所述第三控制信息还包括第六字段;其中,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度;或,所述第六字段用于指示所述第二逻辑地址集合中每个逻辑地址的访问粒度;或,所述第六字段用于指示所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度之和;所述第三物理地址集合中每个物理地址的访问粒度与所述第二逻辑地址集合中每个逻辑地址的访问粒度相同。
- 根据权利要求57至59任意一项所述的主芯片,其特征在于,所述第三指示信息承载于扩展头字段EHS扩展域中,所述EHS扩展域由所述主芯片分配。
- 根据权利要求58至60任意一项所述的主芯片,其特征在于,所述第三控制信息承载于UPIU协议帧的第三预留字段中。
- 根据权利要求57至61任意一项所述的主芯片,其特征在于,所述主芯片还包括:发送单元,用于向所述存储芯片发送第二请求;其中,所述第二请求中包括第二逻辑地址集合以及第二数据,所述第二数据包括待写入所述存储芯片的数据。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201880096230.9A CN112513822B (zh) | 2018-08-01 | 2018-08-01 | 信息处理方法及装置、设备、*** |
EP18928761.8A EP3819771B1 (en) | 2018-08-01 | 2018-08-01 | Data processing method and device, apparatus, and system |
PCT/CN2018/098040 WO2020024151A1 (zh) | 2018-08-01 | 2018-08-01 | 信息处理方法及装置、设备、*** |
US17/162,232 US11467766B2 (en) | 2018-08-01 | 2021-01-29 | Information processing method, apparatus, device, and system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2018/098040 WO2020024151A1 (zh) | 2018-08-01 | 2018-08-01 | 信息处理方法及装置、设备、*** |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/162,232 Continuation US11467766B2 (en) | 2018-08-01 | 2021-01-29 | Information processing method, apparatus, device, and system |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2020024151A1 true WO2020024151A1 (zh) | 2020-02-06 |
Family
ID=69232147
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2018/098040 WO2020024151A1 (zh) | 2018-08-01 | 2018-08-01 | 信息处理方法及装置、设备、*** |
Country Status (4)
Country | Link |
---|---|
US (1) | US11467766B2 (zh) |
EP (1) | EP3819771B1 (zh) |
CN (1) | CN112513822B (zh) |
WO (1) | WO2020024151A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4283455A4 (en) * | 2021-03-18 | 2024-03-13 | Huawei Technologies Co., Ltd. | METHOD AND DEVICE FOR PERFORMING A STORAGE OPERATION |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105159622A (zh) * | 2015-10-22 | 2015-12-16 | 湖南国科微电子股份有限公司 | 一种减小ssd读写io时延的方法与*** |
CN106775466A (zh) * | 2016-12-05 | 2017-05-31 | 深圳市金泰克半导体有限公司 | 一种无dram的ftl读缓存管理方法及装置 |
US20170300422A1 (en) * | 2016-04-14 | 2017-10-19 | Micron Technology, Inc. | Memory device with direct read access |
CN108062280A (zh) * | 2016-11-07 | 2018-05-22 | 三星电子株式会社 | 存储器控制器以及包括该存储器控制器的存储器*** |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102145420B1 (ko) * | 2013-07-25 | 2020-08-18 | 삼성전자주식회사 | 데이터 전송 속도를 변경하는 스토리지 시스템 및 그것의 데이터 전송 속도 변경 방법 |
US20160011790A1 (en) * | 2014-07-14 | 2016-01-14 | Sandisk Technologies Inc. | Systems and methods to enable access to a host memory associated with a unified memory architecture (uma) |
US10229051B2 (en) * | 2015-12-30 | 2019-03-12 | Samsung Electronics Co., Ltd. | Storage device including nonvolatile memory device and controller, operating method of storage device, and method for accessing storage device |
KR20170081118A (ko) * | 2015-12-30 | 2017-07-11 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 컨트롤러를 포함하는 스토리지 장치, 스토리지 장치의 동작 방법, 그리고 스토리지 장치를 액세스하는 액세스 방법 |
-
2018
- 2018-08-01 CN CN201880096230.9A patent/CN112513822B/zh active Active
- 2018-08-01 WO PCT/CN2018/098040 patent/WO2020024151A1/zh unknown
- 2018-08-01 EP EP18928761.8A patent/EP3819771B1/en active Active
-
2021
- 2021-01-29 US US17/162,232 patent/US11467766B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105159622A (zh) * | 2015-10-22 | 2015-12-16 | 湖南国科微电子股份有限公司 | 一种减小ssd读写io时延的方法与*** |
US20170300422A1 (en) * | 2016-04-14 | 2017-10-19 | Micron Technology, Inc. | Memory device with direct read access |
CN108062280A (zh) * | 2016-11-07 | 2018-05-22 | 三星电子株式会社 | 存储器控制器以及包括该存储器控制器的存储器*** |
CN106775466A (zh) * | 2016-12-05 | 2017-05-31 | 深圳市金泰克半导体有限公司 | 一种无dram的ftl读缓存管理方法及装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP4283455A4 (en) * | 2021-03-18 | 2024-03-13 | Huawei Technologies Co., Ltd. | METHOD AND DEVICE FOR PERFORMING A STORAGE OPERATION |
Also Published As
Publication number | Publication date |
---|---|
US20210149588A1 (en) | 2021-05-20 |
US11467766B2 (en) | 2022-10-11 |
CN112513822B (zh) | 2024-05-10 |
EP3819771A1 (en) | 2021-05-12 |
CN112513822A (zh) | 2021-03-16 |
EP3819771B1 (en) | 2023-10-04 |
EP3819771A4 (en) | 2021-07-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10067684B2 (en) | File access method and apparatus, and storage device | |
JP6913481B2 (ja) | 大容量格納装置、システム、及び方法 | |
US9395921B2 (en) | Writing data using DMA by specifying a buffer address and a flash memory address | |
US9734085B2 (en) | DMA transmission method and system thereof | |
US10452562B2 (en) | File access method and related device | |
US9785545B2 (en) | Method and apparatus for providing dual memory access to non-volatile memory | |
WO2017000658A1 (zh) | 存储***、存储管理装置、存储器、混合存储装置及存储管理方法 | |
JP5384576B2 (ja) | 複数の異種のソリッドステート・ストレージ・ロケーションの選択的利用 | |
JP2020046963A (ja) | メモリシステムおよび制御方法 | |
TW201915741A (zh) | 記憶體系統及控制非揮發性記憶體之控制方法 | |
JP6785204B2 (ja) | メモリシステムおよび制御方法 | |
TW201818249A (zh) | 操作對多重名稱空間進行管理的儲存裝置的方法 | |
US20200257620A1 (en) | Memory Block Reclamation Method and Apparatus | |
CN108959127A (zh) | 地址转换方法、装置及*** | |
WO2015180598A1 (zh) | 对存储设备的访问信息处理方法和装置、*** | |
CN113032293A (zh) | 缓存管理器及控制部件 | |
WO2020024151A1 (zh) | 信息处理方法及装置、设备、*** | |
US11835992B2 (en) | Hybrid memory system interface | |
US10572382B2 (en) | Method of operating data storage device and method of operating data processing system including the same | |
WO2023241655A1 (zh) | 数据处理方法、装置、电子设备以及计算机可读存储介质 | |
CN117389685A (zh) | 虚拟机热迁移标脏方法及其装置、后端设备、芯片 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 18928761 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |