WO2020015088A1 - 一种oled像素驱动电路及oled显示装置 - Google Patents

一种oled像素驱动电路及oled显示装置 Download PDF

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Publication number
WO2020015088A1
WO2020015088A1 PCT/CN2018/104746 CN2018104746W WO2020015088A1 WO 2020015088 A1 WO2020015088 A1 WO 2020015088A1 CN 2018104746 W CN2018104746 W CN 2018104746W WO 2020015088 A1 WO2020015088 A1 WO 2020015088A1
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Prior art keywords
film transistor
switch
thin film
switch tube
node
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PCT/CN2018/104746
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English (en)
French (fr)
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陈小龙
温亦谦
周明忠
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/331,153 priority Critical patent/US10685602B2/en
Publication of WO2020015088A1 publication Critical patent/WO2020015088A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G09G3/3283—Details of drivers for data electrodes in which the data driver supplies a variable data current for setting the current through, or the voltage across, the light-emitting elements
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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Definitions

  • the present invention relates to the field of display technology, and in particular, to an OLED pixel driving circuit and an OLED display device.
  • OLED Organic Light Emitting Diode
  • OLED display devices have many advantages such as self-emission, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180 ° viewing angle, wide operating temperature range, flexible display and large-area full-color display. It is recognized by the industry as the most promising display device.
  • OLED is a current-driven device. When a current flows, the OLED emits light, and the brightness of the OLED is determined by the current flowing through the OLED itself. Most existing ICs (Integrated Circuits) only transmit voltage signals, so the pixel driving circuit of the OLED needs to complete the task of converting voltage signals into current signals.
  • the OLED pixel driving circuit in the prior art is usually 2T1C (2transistor1capacitance, that is, a structure of two thin film transistors plus a capacitor) to convert a voltage into a current.
  • the existing 2T1C pixel driving circuit includes a first thin film transistor T1, a second thin film transistor T2, and a capacitor Cs.
  • the first thin film transistor T1 is a driving TFT
  • the second thin film transistor T2 is a switching TFT
  • a capacitor is the storage capacitor.
  • the source of the first thin film transistor T1 is electrically connected to the anode of the organic light emitting diode D0, the drain is connected to the power supply voltage OVDD, and the gate is electrically connected to the first node G; the cathode of the organic light emitting diode D0 is connected to the common ground. Voltage OVSS; the source of the second thin film transistor T2 is electrically connected to the first node G, the gate is connected to the scan signal Scan, and the drain is connected to the data signal Data; one end of the capacitor Cs is electrically connected to the gate of the first thin film transistor T1 The other end is electrically connected to the source of the first thin film transistor T1.
  • the scan signal Scan controls T2 to turn on, the data signal Data enters the gate of T1 and the capacitor Cs through T2, and then T2 turns off. Due to the storage effect of capacitor Cs, the gate voltage of T1 can still maintain the data signal The voltage makes T1 in a conducting state, the driving current enters the organic light emitting diode D0 through T1, and the organic light emitting diode D0 is driven to emit light.
  • K is an intrinsic conductivity factor
  • the magnitude of I ds and sat is related to the threshold voltage Vth of the driving TFT, that is, T1.
  • the threshold voltage Vth of the driving TFT of each sub-pixel in the panel will be different. Therefore, even if the voltage Vdata of the data signal Data is applied equally to the driving TFTs of each pixel, the current flowing into the organic light emitting diode may be inconsistent, which makes it difficult to achieve uniformity of the display image quality.
  • the TFT material will be aged and mutated, which will cause the threshold voltage Vth of the driving TFT to drift.
  • the aging degree of the TFT material in the panel is different, which causes the threshold voltage Vth drift of each driving TFT in the panel to be different, which may also cause uneven display of the panel, and the aging of the TFT material becomes more serious with the driving time. . Even if the driving voltage is the same, the light emitting current flowing through the organic light emitting diode is likely to be different, resulting in uneven brightness.
  • the aging of the light-emitting transistor device will cause the turn-on voltage of the light-emitting transistor to increase, and the current flowing into the organic light-emitting diode will gradually decrease, resulting in problems such as a decrease in panel brightness and a decrease in light-emitting efficiency. .
  • the existing 3T1C pixel driving circuit includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a capacitor Cs, a capacitor C OLED, and a capacitor Cp.
  • the first thin film transistor T1 is a driver. TFT. Compared with the 2T1C pixel driving circuit shown in FIG.
  • the existing 3T1C pixel driving circuit adds the following components: a capacitor C OLED electrically connected between the anode and the cathode of the organic light emitting diode D0, and the source is electrically connected to the first film
  • the source and the drain of the transistor T1 are connected to the sensing control signal Sense, the gate is connected to the third thin film transistor T3 of the scan signal Scan, one end is connected to the capacitor Cp connected to the drain of the third thin film transistor T3 and the other end is connected to the sense.
  • Measure the reference voltage Vref of the control signal Sense and access the analog-to-digital converter ADC0 of the control signal Sense through the switch SW0.
  • the existing 3T1C pixel driving circuit compensates the threshold voltage Vth by sensing the threshold voltage Vth of the driving thin film transistor, that is, T1, but it can only compensate the threshold voltage Vth of the driving thin film transistor, and cannot compensate for the influence of OLED aging on brightness. As the OLED ages, the value of k will drift, and the aging degree of the OLED device of each sub-pixel will not be consistent with the drift of time, resulting in problems such as decreased brightness, luminous efficiency and uneven brightness of the panel display.
  • the purpose of the present invention is to provide an OLED pixel driving circuit and an OLED display device, which can compensate the threshold voltage Vth of the driving thin film transistor and compensate the drift of the k value after the OLED is aged, thereby improving the uniformity of the brightness of the OLED panel.
  • the present invention provides an OLED pixel driving circuit.
  • the working state of the driving circuit includes a display mode and a sensing mode.
  • the driving circuit includes a first thin film transistor, and a gate is electrically connected to a first node.
  • the source is electrically connected to the second node, the drain is connected to the data current through the first switch, and the power voltage is also connected to the second switch; the second thin film transistor, the gate is connected to the scanning signal, and the source is electrically connected to the source.
  • the drain is connected to the data signal, the data voltage is connected in the display mode through the fifth switch and the initialization voltage is connected in the sensing mode, and the first analog-to-digital conversion is connected through the sixth switch.
  • the third thin film transistor the gate is connected to the scanning signal, the source is electrically connected to the second node, the drain is connected to the reference voltage through the third switch, and the second analog-to-digital conversion is connected to the drain through the fourth switch Capacitor; one end is electrically connected to the first node, and the other end is electrically connected to the second node; an organic light emitting diode, an anode is electrically connected to the second node, and a cathode is connected to the public Ground voltage; the first to sixth switching tubes, the first analog-to-digital converter, and the second analog-to-digital converter are all set in the driving IC; the display mode is divided into a data writing phase and a light-emitting phase, and in the display mode Data writing stage: the scan signal is high so that the second thin film transistor and the third thin film transistor are turned on, and the second switch, the fifth switch, and the third switch are in the corresponding It is turned on under the control of a level control signal, the first node writes the data
  • the third switch writes the reference voltage; in the light-emitting stage of the display mode: the scan signal is at a low level so that the second thin film transistor and the third thin film transistor are turned off, and the charge stored in the capacitor is The difference between the data voltage and the reference voltage, the organic light emitting diode emits light; the sensing mode is divided into a level initialization stage and a sensing stage, and in the potential initialization stage of the sensing mode: the scanning signal The high level causes the second thin film transistor and the third thin film transistor to be turned on, the fifth switch tube and the third switch tube are turned on under the control of a corresponding level control signal, and the first node passes The second thin film transistor and the fifth switching transistor write the initialization voltage, and the second node writes the reference voltage through the third thin film transistor and the third switching transistor; in a sensing mode Sensing stage: the scan signal is at a high level, the fifth switch tube and the third switch tube are turned off under the control of corresponding level control signals, the first switch tube, the sixth switch tube,
  • the first analog-to-digital converter passes the A second thin film transistor and the sixth switch tube sense the potential of the first node, and the second analog-to-digital converter senses the second node potential through the third thin film transistor and the fourth switch tube To sense everything
  • the threshold voltage and the intrinsic conductivity factor of the first thin film transistor are described.
  • the present invention also provides an OLED pixel driving circuit.
  • the working state of the driving circuit includes a display mode and a sensing mode.
  • the driving circuit includes a first thin film transistor, and a gate is electrically connected to the first node.
  • the source is electrically connected to the second node, the drain is connected to the data current through the first switch, and the power voltage is connected to the second switch; the second thin film transistor, the gate is connected to the scanning signal, and the source is electrically connected
  • the drain of the first node is connected to the data signal, the data voltage is connected to the display mode and the initialization voltage in the sensing mode through the fifth switch, and the first modulus is connected to the drain through the sixth switch.
  • the third thin film transistor the gate of which is connected to the scanning signal, the source of which is electrically connected to the second node, the drain of which is connected to the reference voltage through the third switch, and the second module to the second through the fourth switch A converter; a capacitor, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the second node; an organic light emitting diode, an anode of which is electrically connected to the second node, and a cathode of which is connected to the public Common ground voltage; in the display mode, the second switch tube, the fifth switch tube, and the third switch tube are turned on under the control of corresponding level control signals; the display mode is divided into a data writing phase and a light emitting phase.
  • the scanning signal is at a high level during the data writing phase, so that the second thin film transistor and the third thin film transistor are turned on, the data voltage is connected to the reference voltage, and the scanning signal is The low level causes the second thin film transistor and the third thin film transistor to be turned off, and the charge stored in the capacitor causes the organic light emitting diode to emit light; in a sensing mode, the fifth switch tube and the third switch The tubes are first turned on under the control of the corresponding level control signals, and then the fifth switch tube and the third switch tube are turned off under the control of the corresponding level control signals, and at the same time, the first switch tube and the sixth switch tube are turned off.
  • the fourth switch is turned on under the control of the corresponding level control signal; the sensing mode is divided into a level initialization stage and a sensing stage, and the scanning signal is always high level, and the
  • the second thin film transistor is in conduction with the third thin film transistor, the initialization voltage and the reference voltage are connected to the circuit, and the data current is connected to the circuit during the sensing stage, and the first mode is input by different data currents.
  • the digital-to-digital converter and the second analog-to-digital converter sense the threshold voltage of the first thin film transistor and the intrinsic conductivity factor value.
  • the present invention also provides an OLED display device, including an OLED pixel driving circuit, the driving circuit working state includes a display mode and a sensing mode; the driving circuit includes: a first thin film transistor, a gate electrode The first node is electrically connected to the second node, the source is electrically connected to the second node, the drain is connected to the data current through the first switch, and the power supply voltage is connected to the second switch through the second switch; The source is electrically connected to the first node, the drain is connected to the data signal, the data voltage is connected in the display mode through the fifth switch, the initialization voltage is connected in the sensing mode, and the sixth switch is connected to the drain.
  • the third thin-film transistor the gate is connected to the scanning signal, the source is electrically connected to the second node, the drain is connected to the reference voltage through the third switch, and at the same time connected to the fourth switch
  • a second analog-to-digital converter a capacitor, one end of which is electrically connected to the first node, and the other end of which is electrically connected to the second node; an organic light emitting diode, and the anode is electrically connected to the first node Node, the cathode is connected to the common ground voltage;
  • the first to sixth switching tubes, the first analog-to-digital converter and the second analog-to-digital converter are all set in the driving IC;
  • the display mode is divided into a data writing stage and In the light-emitting stage, in the data writing stage of the display mode: the scan signal is at a high level so that the second thin film transistor and the third thin film transistor are turned on, the second switch tube, the fifth switch tube, the first The three
  • the first node writes the data voltage through the second thin film transistor and the fifth switch, and the second node passes the first Three thin-film transistors and the third switch write the reference voltage; in the light-emitting stage of the display mode: the scan signal is at a low level so that the second thin-film transistor and the third thin-film transistor are turned off, so The charge stored in the capacitor is the difference between the data voltage and the reference voltage, and the organic light emitting diode emits light; the sensing mode is divided into a level initialization stage and a sensing stage, and the potential in the sensing mode is initialized.
  • the first node writes the initialization voltage through the second thin film transistor and the fifth switch
  • the second node writes the reference through the third thin film transistor and the third switch Voltage
  • the scan signal is at a high level
  • the fifth switch tube and the third switch tube are turned off under the control of a corresponding level control signal
  • the first switch tube
  • the sixth switch tube and the fourth switch tube are turned on under the control of the corresponding level control signals
  • the second node is charged and discharged through the first thin film transistor by inputting different data currents.
  • a digital-to-digital converter senses the potential of the first node through the second thin-film transistor and the sixth switching transistor, and the second analog-to-digital converter senses through the third thin-film transistor and the fourth switching transistor.
  • the second section Potential thereby sensing the threshold voltage of the first thin film transistor and the intrinsic conductivity factor values.
  • the OLED pixel driving circuit and the OLED display device provided by the present invention adopt a 3T1C structure.
  • the normal display mode and the sensing mode of the pixel driving circuit include two stages; at the same time, the thin film transistor is driven according to the sensing.
  • the threshold voltage Vth and the intrinsic conductivity factor value k of the OLED after aging, and corresponding data compensation in the display mode can improve the uniformity of the display and the luminous efficiency.
  • FIG. 1 is a structural diagram of a 2T1C pixel driving circuit for an OLED in the prior art
  • FIG. 2 is a structural diagram of a 3T1C pixel driving circuit for an OLED in the prior art
  • FIG. 3 is a structural diagram of an OLED pixel driving circuit according to a first embodiment of the present invention.
  • FIG. 4 is a timing diagram of a display mode of the OLED pixel driving circuit described in FIG. 3;
  • FIG. 5 is a timing diagram of a sensing mode of the OLED pixel driving circuit described in FIG. 3;
  • FIG. 6 is a structural diagram showing a second embodiment of an OLED pixel driving circuit according to the present invention.
  • FIG. 7 is a timing chart of a display mode of the OLED pixel driving circuit described in FIG. 6;
  • FIG. 8 is a timing diagram of a sensing mode of the OLED pixel driving circuit described in FIG. 6.
  • the "first" or “down” of the second feature may include the first and second features in direct contact, and may also include the first and second features. Not directly, but through another characteristic contact between them.
  • the first feature is “above”, “above”, and “above” the second feature, including that the first feature is directly above and obliquely above the second feature, or merely indicates that the first feature is higher in level than the second feature.
  • the first feature is “below”, “below”, and “below” of the second feature, including the fact that the first feature is directly below and obliquely below the second feature, or merely indicates that the first feature is less horizontal than the second feature.
  • FIG. 3 is a structural diagram shown in the first embodiment of the OLED pixel driving circuit according to the present invention
  • FIG. 4 is a timing chart of the display mode of the OLED pixel driving circuit described in FIG. 3
  • FIG. 5 is FIG.
  • the driving circuit includes: first to third thin film transistors T1 to T3, first to sixth switching transistors S1 to S6, a capacitor Cs, an organic light emitting diode D0, and first and second analog-to-digital converters ADC1 and ADC2;
  • the working state of the driving circuit includes a display mode and a sensing mode.
  • the first to sixth switching transistors S1 to S6, the first analog-to-digital converter ADC1, and the second analog-to-digital converter ADC2 are all disposed in the driving IC 30 to improve the integration of the circuit.
  • the above-mentioned components may be directly disposed on the panel.
  • the first thin film transistor T1 has a gate electrically connected to the first node g and a source electrically connected to the second node s. The drain is connected to the data current Idata through the first switch S1 and is simultaneously connected to the power through the second switch S1. Voltage OVDD.
  • the first thin film transistor T1 is a driving thin film transistor that drives the organic light emitting diode D0.
  • the second thin film transistor T2 has a gate connected to the scan signal Scan, a source electrically connected to the first node g, a drain connected to the data signal Data, a data voltage Vdata in the display mode through the fifth switch S5, and In the sensing mode, the initialization voltage Vini is connected, and the first analog-to-digital converter ADC1 is connected through the sixth switch S6.
  • the third thin film transistor T3 has the gate connected to the scan signal Scan, the source is electrically connected to the second node s, the drain is connected to the reference voltage Vref through the third switch S3 and the second mode is connected to the second mode through the fourth switch S4. Digit converter ADC2.
  • One end of the capacitor Cs is electrically connected to the first node g, and the other end is electrically connected to the second node s.
  • the anode is electrically connected to the second node s, and the cathode is connected to the common ground voltage OVSS.
  • the second switch S2, the fifth switch S5, and the third switch S3 are turned on under the control of the corresponding level control signal SW.
  • the display mode is divided into a data writing stage t1 and a light-emitting stage t2.
  • the scan signal Scan is at a high level during the data writing stage t1 so that the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the data voltage Vdata and the reference voltage Vref is connected to the circuit, and the scan signal Scan is at a low level during the light-emitting stage t2 to turn off the second thin film transistor T2 and the third thin film transistor T3, and the charge stored in the capacitor Cs causes the organic light emitting diode D0 to emit light.
  • the scan signal Scan is at a high level so that the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the second switching transistor S2, the fifth switching transistor S5, and the first The three switches S3 are turned on under the control of the corresponding level control signal SW, and the first node g writes the data voltage Vdata through the second thin film transistor T2 and the fifth switch S5 (after obtaining the compensation data, the data after compensation is written) Voltage), the second node s writes the reference voltage Vref through the third thin film transistor T3 and the third switch S3, and the OLED does not emit light at this stage.
  • the scan signal Scan is at a low level so that the second thin film transistor T2 and the third thin film transistor T3 are turned off, and the charge stored in the capacitor Cs is the difference between the data voltage Vdata and the reference voltage Vref (that is, The charge stored by Cs is consistent with the previous stage), and the organic light emitting diode D0 emits light.
  • the fifth switch S5 and the third switch S3 are first turned on under the control of the corresponding level control signal SW, and then the fifth switch S5 and the third switch S3 are controlled at the corresponding level.
  • the switch is turned off under the control of SW, and the first switch S1, the sixth switch S6, and the fourth switch S4 are turned on under the control of the corresponding level control signal SW.
  • the sensing mode is divided into a potential initialization phase t1 and a sensing phase t2.
  • the scan signal Scan is always high. During the potential initialization phase t1, the second thin film transistor T2 and the third thin film transistor T3 are turned on.
  • the initialization voltage Vini and the reference The voltage Vref is connected to the circuit, and the data current Idata is connected to the circuit at the sensing stage t2.
  • the first analog-to-digital converter ADC1 and the second analog-to-digital converter ADC2 sense the threshold value of the first thin film transistor T1.
  • the voltage Vth and the intrinsic conductivity factor k According to the sensed threshold voltage Vth of the driving thin film transistor (ie, the first thin film transistor T1) and the intrinsic conductivity factor value k, corresponding data compensation can be performed in the display mode.
  • the scan signal Scan is at a high level so that the second thin film transistor T2 and the third thin film transistor T3 are turned on, and the fifth switch S5 and the third switch S3 are correspondingly
  • the level control signal SW is turned on, the first node g writes the initialization voltage Vini through the second thin film transistor T2 and the fifth switch S5, and the second node s writes through the third thin film transistor T3 and the third switch S3.
  • the reference voltage Vref Into the reference voltage Vref.
  • the scan signal Scan is at a high level
  • the fifth switch S5 and the third switch S3 are turned off under the control of the corresponding level control signal SW
  • the first switch S1 The sixth switch S6 and the fourth switch S4 are turned on under the control of the corresponding level control signal SW, and input different data currents Idata to charge and discharge the second node s through the first thin film transistor T1.
  • the first mode The digital converter ADC1 senses the potential of the first node g through the second thin film transistor T2 and the sixth switch S6, and the second analog digital converter ADC2 senses the potential of the second node s through the third thin film transistor T3 and the fourth switch S4. , Thereby sensing the threshold voltage Vth of the first thin film transistor T1 and the intrinsic conductivity factor value k.
  • the first data current Idata1 is input to the second node s through the first thin film transistor T1, and after the current is stabilized, the first analog-to-digital converter ADC1 passes the second thin film transistor T2
  • the sixth switching transistor S6 senses the potential of the first node g
  • the second analog-to-digital converter ADC2 senses the potential of the second node s through the third thin film transistor T3 and the fourth switching transistor S4 to obtain the gate of the first thin film transistor and The first voltage difference Vgs1 between the sources; the input second data current Idata2 charges and discharges the second node s through the first thin film transistor T1.
  • the first analog-to-digital converter ADC1 passes the second thin film transistor T2 and the first Six switching transistors S6 sense the potential of the first node g, and the second analog-to-digital converter ADC2 senses the potential of the second node s through the third thin film transistor T3 and the fourth switching transistor S4 to obtain the gate and source of the first thin film transistor.
  • Idata1 is the first data current
  • Vgs1 is the first voltage difference between the gate and the source of the first thin film transistor
  • Idata2 is the second data current
  • Vgs2 is between the gate and the source of the first thin film transistor
  • the second voltage difference is the threshold voltage of the first thin film transistor
  • k is the intrinsic conductivity factor value.
  • the data current Idata is charged and discharged to the s point through T1, and the current flowing through the OLED after stabilization is Idata.
  • the OLED pixel driving circuit of the present invention adopts a 3T1C structure.
  • the normal display mode and the sensing mode of the pixel driving circuit both include two phases; at the same time, the threshold voltage of the driving thin film transistor is driven according to the sensing.
  • Vth and the intrinsic conductivity factor k of the OLED after aging corresponding data compensation is performed in the display mode. That is, in the display mode, both the threshold voltage Vth of the driving thin film transistor and the drift of the intrinsic conductivity factor value k after the OLED is aged can be compensated, which can improve the uniformity of the display and the luminous efficiency.
  • the first to sixth switching transistors S1 to S6 are all switching elements.
  • the control terminals of the first switch S1 and the second switch S2 are used to receive the corresponding level control signals SW1 and SW2, respectively.
  • the first access point of the first switch S1 and the second switch S2 are electrically connected after short-circuiting.
  • the second access point of the first switch S1 is connected to the data current Idata
  • the second access point of the second switch S2 is connected to the power supply voltage OVDD.
  • the control terminals of the third switch tube S3 and the fourth switch tube S4 are used to receive the corresponding level control signals SW3 and SW4, respectively.
  • the third switch tube S3 and the first access point of the fourth switch tube S4 are electrically short-circuited.
  • the drain of the third thin film transistor T3 is connected, the second access point of the third switch S3 is connected to the reference voltage Vref, and the second access point of the fourth switch S4 is connected to the second analog-to-digital converter ADC2.
  • the control terminals of the fifth switch S5 and the sixth switch S6 are used to receive the corresponding level control signals SW5 and SW6, respectively.
  • the fifth switch S5 and the first access point of the sixth switch S6 are short-circuited.
  • the second access point of the fifth switching transistor S5 is connected to the data voltage Vdata in the display mode
  • the initialization voltage Vini is connected to the sensing mode
  • the second switching point of the sixth switching transistor S6 is The access point is connected to the first analog-to-digital converter ADC1.
  • the scan signal Scan is at a high level
  • the control terminals of the first, fourth, and sixth switches S1, S4, and S6 receive a low level (ie, SW1, SW4, SW6 is a low-level signal)
  • the control ends of the second, third, and fifth switch transistors S2, S3, and S5 receive a high-level (ie, SW2, SW3, and SW5 are high-level signals).
  • the scan signal Scan is at a low level
  • the control terminals of the first, fourth, and sixth switching transistors S1, S4, and S6 receive the low level
  • the second, third, and fifth switches receive a high level. That is, in the display mode, the second, third, and fifth switches S2, S3, and S5 are always turned on, and the first, fourth, and sixth switches S1, S4, and S6 are always turned off.
  • the scan signal Scan is at a high level, and the control terminals of the first, second, fourth, and sixth switching transistors S1, S2, S4, and S6 receive a low level, The control terminals of the third and fifth switches S3 and S5 receive a high level.
  • the sensing phase t2 of the sensing mode the scan signal Scan is at a high level, and the control terminals of the first, fourth, and sixth switching transistors S1, S4, and S6 receive the high level, and the second, third, and sixth The control terminals of the five switches S2, S3, and S5 receive a low level.
  • FIG. 6 is an architectural diagram shown in the second embodiment of the OLED pixel driving circuit according to the present invention
  • FIG. 7 is a timing chart of the display mode of the OLED pixel driving circuit described in FIG. 6,
  • FIG. 8 is FIG.
  • the first to sixth switching transistors S1 to S6 are all MOS transistors.
  • the gates of the first switch S1 and the second switch S2 are short-circuited to receive the corresponding level control signal SW1 / 2.
  • the first switch S1 and the source of the second switch S2 are short-circuited and electrically connected to the first The drain of a thin film transistor T1, the source of the first switch S1 is connected to the data current Idata, and the source of the second switch S2 is connected to the power supply voltage OVDD.
  • the gates of the third switch S3 and the fourth switch S4 are short-circuited to receive corresponding level control signals SW3 / 4.
  • the third switch S3 and the source of the fourth switch S4 are short-circuited and electrically connected to the first The drain of the three thin film transistors T3, the drain of the third switch S3 is connected to the reference voltage Vref, and the drain of the fourth switch S4 is connected to the second analog-to-digital converter ADC2.
  • the fifth switch S5 and the gate of the sixth switch S6 are short-circuited to receive the corresponding level control signal SW5 / 6.
  • the fifth switch S5 and the source of the sixth switch S6 are short-circuited and electrically connected to the first.
  • the drain of the two thin-film transistors T2 the drain of the fifth switch S5 is connected to the data voltage Vdata in the display mode, the initialization voltage Vini is connected to the sensing mode, and the drain of the sixth switch S6 is connected to the first mode Digit converter ADC1.
  • the scan signal Scan is at a high level, and the gates of the first and second switches S1 and S2 receive a low level (that is, SW1 / 2 is a low level signal).
  • the gates of the third, fourth, fifth, and sixth switches S3, S4, S5, and S6 receive a high level (ie, SW3 / 4, SW5 / 6 are high-level signals).
  • the scan signal Scan is at a low level, the gates of the first and second switching transistors S1 and S2 receive a low level, and the third, fourth, fifth, and sixth switching transistors S3
  • the gates of, S4, S5, and S6 receive a high level. That is, in the display mode, the second, third, and fifth switches S2, S3, and S5 are always turned on, and the first, fourth, and sixth switches S1, S4, and S6 are always turned off.
  • the scan signal Scan is at a high level, and the gates of the first and second switching transistors S1 and S2 receive a low level, and the third, fourth, fifth, and third The gates of the six switches S3, S4, S5, and S6 receive a high level; in the sensing phase t2 of the sensing mode: the scan signal Scan is high, and the gates of the first and second switches S1 and S2 are high.
  • the pole receives a high level, and the gates of the third, fourth, fifth, and sixth switches S3, S4, S5, and S6 receive a low level.
  • the present invention also provides an OLED display device including the above-mentioned OLED pixel driving circuit, and the structure and function of the OLED pixel driving circuit will not be described repeatedly here.
  • the OLED pixel driving circuit and the OLED display device provided by the present invention adopt a 3T1C structure.
  • the normal display mode and the sensing mode of the pixel driving circuit include two stages; at the same time, the thin film transistor is driven according to the sensing
  • the threshold voltage Vth and the intrinsic conductivity factor value k of the OLED after aging, and corresponding data compensation in the display mode can improve the uniformity of the display and the luminous efficiency.

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Abstract

一种OLED像素驱动电路及OLED显示装置，采用3T1C结构，通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段；同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k，在显示模式下进行相应的数据补偿，能够提高显示的均匀性，提高发光效率。

Description

一种OLED像素驱动电路及OLED显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种OLED像素驱动电路及OLED显示装置。
背景技术
近年来OLED(Organic Light Emitting Diode，有机发光二极管)显示技术的快速发展，推动曲面和柔性显示触控产品迅速进入市场，相关领域技术更新也是日新月异。OLED是指利用有机半导体材料和发光材料在电场驱动下，通过载流子注入和复合导致发光的二极管。OLED显示装置具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽，可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。
OLED是电流驱动器件，当有电流流经时OLED发光，且发光亮度由流经OLED自身的电流决定。大部分已有的IC(Integrated Circuit，集成电路)都只传输电压信号，故OLED的像素驱动电路需要完成将电压信号转变为电流信号的任务。现有技术中的OLED像素驱动电路通常为2T1C(2 transistor 1 capacitance，即两个薄膜晶体管加一个电容的结构)，以将电压变换为电流。
参考图1，现有技术中的用于OLED的2T1C像素驱动电路架构图。如图1所示，现有2T1C像素驱动电路包括：第一薄膜晶体管T1、第二薄膜晶体管T2、及电容Cs，其中第一薄膜晶体管T1为驱动TFT，第二薄膜晶体管T2为开关TFT，电容Cs为存储电容。具体地，第一薄膜晶体管T1的源极电性连接有机发光二极管D0的阳极、漏极接入电源电压OVDD、栅极电性连接于第一节点G；有机发光二极管D0的阴极接入公共接地电压OVSS；第二薄膜晶体管T2的源极电性连接于第一节点G、栅极接入扫描信号Scan，漏极接入数据信号Data；电容Cs的一端电性连接第一薄膜晶体管T1的栅极，另一端电性连接第一薄膜晶体管T1的源极。OLED显示时，扫描信号Scan控制T2导通，数据信号Data经过T2进入到T1的栅极及电容Cs，然后T2关断，由于电容Cs的存储作用，T1的栅极电压仍可继续保持数据信号电压，使得T1处于导通状态，驱动电流通过T1进入有机发光二极管D0，驱动有机发光二极管D0发光。
晶体管I‐V方程：
I ds,sat＝k·(V GS-V th,T1) 2＝k·(V G-V S-V th,T1) 2
式中K为本征导电因子，I ds,sat的大小与驱动TFT即T1的阈值电压Vth有关。
由于面板制程的不稳定性等原因，使得面板内每个子像素的驱动TFT的阈值电压Vth会有差别。因此，即使数据信号Data的电压Vdata相等的施加到各像素的驱动TFT，也会出现流入有机发光二极管的电流不一致的情况，导致显示图像质量的均一性难以实现。
另外，随着驱动TFT驱动时间的推移，会造成TFT材料老化、变异，导致驱动TFT的阈值电压Vth会漂移等问题。并且面板内TFT材料的老化程度不同，导致面板内各驱动TFT的阈值电压Vth漂移量不同，也会造成面板显示的不均匀现象，并且随着驱动时间的推移，TFT材料的老化变得更严重。即使驱动电压相同，流经有机发光二极管的发光电流也很可能不同，造成亮度不均匀。加之发光晶体管器件的老化，会使发光晶体管的开启电压上升，流入有机发光二极管的电流逐渐减小，导致面板亮度降低、发光效率下降等问题。。
技术问题
参考图2，现有技术中的用于OLED的3T1C像素驱动电路架构图。如图2所示，现有3T1C像素驱动电路包括：第一薄膜晶体管T1、第二薄膜晶体管T2、第三薄膜晶体管T3、电容Cs、电容C OLED及电容Cp，其中第一薄膜晶体管T1为驱动TFT。与图1所示2T1C像素驱动电路相比，现有3T1C像素驱动电路增设了如下组件：电性连接于有机发光二极管D0的阳极与阴极之间的电容C OLED，源极电性连接第一薄膜晶体管T1的源极、漏极接入感测控制信号Sense，栅极接入扫描信号Scan的第三薄膜晶体管T3，一端接入第三薄膜晶体管T3漏极另一端接地的电容Cp，接入感测控制信号Sense的参考电压Vref，通过开关SW0接入感测控制信号Sense的模数转换器ADC0。现有3T1C像素驱动电路通过感测到驱动薄膜晶体管即T1的阈值电压Vth，以对阈值电压Vth进行补偿，但其只能补偿驱动薄膜晶体管的阈值电压Vth，无法补偿OLED老化对 亮度的影响。当OLED老化时k值会漂移，且各子像素的OLED器件随时间的漂移老化程度不一致，导致面板显示的亮度、发光效率下降，亮度不均匀等问题。
因此，可补偿驱动薄膜晶体管的阈值电压Vth漂移以及补偿OLED老化后k值的漂移，提升OLED面板亮度的均匀性成为亟待解决的技术问题。
技术解决方案
本发明的目的在于，提供一种OLED像素驱动电路及OLED显示装置，可补偿驱动薄膜晶体管的阈值电压Vth漂移以及补偿OLED老化后k值的漂移，提升OLED面板亮度的均匀性。
为实现上述目的，本发明提供了一种OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式，所述驱动电路包括：第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压；第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内；显示模式分为数据写入阶段与发光阶段，在显示模式的数据写入阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在显示模式的发光阶段：所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷为所述数据电压与所述参考电压的差值，所述有机发光二极管发光；感测模式分为电平初始化阶段与感测阶段，在感测模式的电位初始化阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在感测模式的感测阶段：所述扫描信号为高电平，所述第五开关管、第三开关管在相应的电平控制信号控制下关断，所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通，通过输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
为实现上述目的，本发明还提供了一种OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式，所述驱动电路包括：第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压；第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；在显示模式下，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通；显示模式分为数据写入阶段与发光阶段，所述扫描信号在数据写入阶段为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述数据电压与所述参考电压接入电路，所述扫描信号在发光阶段为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷使得所述有机发光二极管发光；在感测模式下，所述第五开关管、第三开关管先在相应的电平控制信号控制下导通，然后所述第五开关管、第三开关管在相应的电平控制信号控制下关断，同时所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通；感测模式分为电平初始化阶段与感测阶段，所述扫描信号始终为高电平，在电位初始化阶段所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述初 始化电压与所述参考电压接入电路，在感测阶段所述数据电流接入电路，通过输入不同数据电流使得所述第一模数转换器与所述第二模数转换器感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
为实现上述目的，本发明还提供了一种OLED显示装置，包括OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式；所述驱动电路包括：第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压；第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内；显示模式分为数据写入阶段与发光阶段，在显示模式的数据写入阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在显示模式的发光阶段：所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷为所述数据电压与所述参考电压的差值，所述有机发光二极管发光；感测模式分为电平初始化阶段与感测阶段，在感测模式的电位初始化阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在感测模式的感测阶段：所述扫描信号为高电平，所述第五开关管、第三开关管在相应的电平控制信号控制下关断，所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通，通过输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
有益效果
本发明提供的OLED像素驱动电路及OLED显示装置，采用3T1C结构，通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段；同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k，在显示模式下进行相应的数据补偿，能够提高显示的均匀性，提高发光效率。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1，现有技术中的用于OLED的2T1C像素驱动电路架构图；
图2，现有技术中的用于OLED的3T1C像素驱动电路架构图；
图3，本发明所述的OLED像素驱动电路第一实施例所示架构图；
图4为图3所述的OLED像素驱动电路显示模式时序图；
图5为图3所述的OLED像素驱动电路感测模式时序图；
图6，本发明所述的OLED像素驱动电路第二实施例所示架构图；
图7为图6所述的OLED像素驱动电路显示模式时序图；
图8为图6所述的OLED像素驱动电路感测模式时序图。
本发明的最佳实施方式
下面详细描述本发明的实施方式，所述实施方式的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施方式是示例性的，仅用于解释本发明，而不能理解为对本发明的限制。
在本发明中，除非另有明确的规定和限定，第一特征在第二特征之“上”或之“下”可以包括第一和第二特征直接接触，也可以包括第一和第二特征不是直接接触而是通过它们之间的另外的特征接触。而且，第一特征在第二特征“之上”、“上方”和“上面”包括第一特征在第二特征正上方和斜上方，或仅仅表示第一特征水平高度高于第二特征。第一特征在第二特征“之下”、“下方”和“下面”包括第一特征在第二特征正下方和斜下方，或仅仅表示第一特征水平高度小于第二特征。
下文的公开提供了许多不同的实施方式或例子用来实现本发明的不同结构。为了简化本发明的公开，下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本发明。此外，本发明可以在不同例子中重复参考数字和/或参考字母，这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施方式和/或设置之间的关系。此外，本发明提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的应用和/或其他材料的使用。
参考图3‐5，其中图3为本发明所述的OLED像素驱动电路第一实施例所示架构图，图4为图3所述的OLED像素驱动电路显示模式时序图，图5为图3所述的OLED像素驱动电路感测模式时序图。所述驱动电路包括：第一至第三薄膜晶体管T1‐T3、第一至第六开关管S1‐S6、电容Cs、有机发光二极管D0、以及第一、第二模数转换器ADC1、ADC2；所述驱动电路工作状态包括显示模式和感测模式。
本实施例中，第一至第六开关管S1‐S6、第一模数转换器ADC1以及第二模数转换器ADC2均设置在驱动IC30内，以提高电路的集成度。其它实施例中，上述元件也可以直接设置在面板上。
第一薄膜晶体管T1，栅极电性连接第一节点g，源极电性连接第二节点s，漏极通过第一开关管S1接入数据电流Idata、同时通过第二开关管S1接入电源电压OVDD。其中第一薄膜晶体管T1为对有机发光二极管D0进行驱动的驱动薄膜晶体管。
第二薄膜晶体管T2，栅极接入扫描信号Scan，源极电性连接第一节点g，漏极分别接入数据信号Data、通过第五开关管S5在显示模式下接入数据电压Vdata及在感测模式下接入初始化电压Vini、以及通过第六开关管S6接入第一模数转换器ADC1。
第三薄膜晶体管T3，栅极接入扫描信号Scan，源极电性连接第二节点s，漏极通过第三开关管S3接入参考电压Vref、同时通过第四开关管S4接入第二模数转换器ADC2。
电容Cs，一端电性连接第一节点g，另一端电性连接第二节点s。
有机发光二极管D0，阳极电性连接第二节点s，阴极接入公共接地电压OVSS。
在显示模式下，第二开关管S2、第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通。显示模式分为数据写入阶段t1与发光阶段t2，所述扫描信号Scan在数据写入阶段t1为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通，数据电压Vdata与参考电压Vref接入电路，扫描信号Scan在发光阶段t2为低电平使得第二薄膜晶体管T2与第三薄膜晶体管T3关断，电容Cs存储的电荷使得有机发光二极管D0发光。
具体的，在显示模式的数据写入阶段t1：所述扫描信号Scan为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通，第二开关管S2、第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通，第一节点g通过第二薄膜晶体管T2与第五开关管S5写入数据电压Vdata(获取补偿数据后则写入补偿后的数据电压)，第二节点s通过第三薄膜晶体管T3与第三开关管S3写入参考电压Vref，此阶段OLED不发光。在显示模式的发光阶段t2：所述扫描信号Scan为低电平使得第二薄膜晶体管T2与第三薄膜晶体管T3关断，电容Cs存储的电荷为数据电压Vdata与参考电压Vref的差值(即Cs存储的电荷与上一阶段保持一致)，有机发光二极管D0发光。
在感测模式下，第五开关管S5、第三开关管S3先在相应的电平控制信号SW控制下导通，然后第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下关断，同时第一开关管S1、第六开关管S6、第四开关管S4在相应的电平控制信号SW控制下导通。感测模式分为电位初始化阶段t1与感测阶段t2，所述扫描信号Scan始终为高电平，在电位初始化阶段t1第二薄膜晶体管T2与第三薄膜晶体管T3导通，初始化电压Vini与参考电压Vref接入电路，在感测阶段t2数据电流Idata接入电路，通过输入不同数据电流Idata 使得第一模数转换器ADC1与第二模数转换器ADC2感测到第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。根据感测的驱动薄膜晶体管(即第一薄膜晶体管T1)的阈值电压Vth以及本征导电因子值k，即可在显示模式下进行相应的数据补偿。
具体的，在感测模式的电位初始化阶段t1：所述扫描信号Scan为高电平使得第二薄膜晶体管T2与第三薄膜晶体管T3导通，第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下导通，第一节点g通过第二薄膜晶体管T2与第五开关管S5写入初始化电压Vini，第二节点s通过第三薄膜晶体管T3与第三开关管S3写入参考电压Vref。在感测模式的感测阶段t2：所述扫描信号Scan为高电平，第五开关管S5、第三开关管S3在相应的电平控制信号SW控制下关断，同时第一开关管S1、第六开关管S6、第四开关管S4在相应的电平控制信号SW控制下导通，输入不同数据电流Idata通过第一薄膜晶体管T1对第二节点s充放电，电流稳定后第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位，第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位，从而感测到第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。
优选的，在感测模式的感测阶段t2：输入第一数据电流Idata1通过第一薄膜晶体管T1对第二节点s充放电，电流稳定后，第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位，第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位，获取第一薄膜晶体管的栅极与源极之间的第一电压差Vgs1；输入第二数据电流Idata2通过第一薄膜晶体管T1对第二节点s充放电，电流稳定后，第一模数转换器ADC1通过第二薄膜晶体管T2与第六开关管S6感测第一节点g电位，第二模数转换器ADC2通过第三薄膜晶体管T3与第四开关管S4感测第二节点s电位，获取第一薄膜晶体管的栅极与源极之间的第二电压差Vgs2。联立方程组Idata1＝k(Vgs1‐Vth)和Idata2＝k(Vgs2‐Vth)，获取第一薄膜晶体管T1的阈值电压Vth以及本征导电因子值k。其中，Idata1为第一数据电流、Vgs1为第一薄膜晶体管的栅极与源极之间的第一电压差、Idata2为第二数据电流、Vgs2为第一薄膜晶体管的栅极与源极之间的第二电压差、Vth为第一薄膜晶体管的阈值电压、k为本征导电因子值。
也即，S1打开后，数据电流Idata通过T1对s点充放电，稳定后流经OLED的电流为Idata。此时ADC1通过T2、S6感测g点电位，ADC2通过T3、S4感测s点电位。改变Idata的值再次感测g、s点电位，并联立方程组I1＝k(Vgs1‐Vth)和I2＝k(Vgs2‐Vth)，即可获取k和Vth值。根据k和Vth值，即可在显示模式下进行相应的数据补偿。
本发明所述的OLED像素驱动电路，采用3T1C结构，通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段；同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k，在显示模式下进行相应的数据补偿。即，在显示模式下，驱动薄膜晶体管的阈值电压Vth以及OLED老化后本征导电因子值k的漂移均可以得到补偿，能够提高显示的均匀性，提高发光效率。在本实施例中，第一至第六开关管S1‐S6均为开关元件。第一开关管S1与第二开关管S2的控制端用于分别接收相应的电平控制信号SW1、SW2，第一开关管S1与第二开关管S2的第一接入点短接后电性连接第一薄膜晶体管T1的漏极，第一开关管S1的第二接入点接入数据电流Idata，第二开关管S2的第二接入点接入电源电压OVDD。第三开关管S3与第四开关管S4的控制端用于分别接收相应的电平控制信号SW3、SW4，第三开关管S3与第四开关管S4的第一接入点短接后电性连接第三薄膜晶体管T3的漏极，第三开关管S3的第二接入点接入参考电压Vref，第四开关管S4的第二接入点接入第二模数转换器ADC2。第五开关管S5与第六开关管S6的控制端用于分别接收相应的电平控制信号SW5、SW6，第五开关管S5与第六开关管S6的第一接入点短接后电性连接第二薄膜晶体管T2的漏极，第五开关管S5的第二接入点在显示模式下接入数据电压Vdata、在感测模式下接入初始化电压Vini，第六开关管S6的第二接入点接入第一模数转换器ADC1。
进一步，在显示模式的数据写入阶段t1：所述扫描信号Scan为高电平，第一、第四、第六开关管S1、S4、S6的控制端接收低电平(即SW1、SW4、SW6为低电平信号)，第二、第三、第五开关管S2、S3、S5的控制端接收高电平(即SW2、SW3、SW5为高电平信号)。在显示模式的发光阶段t2：所述扫描信号Scan为低电平，第一、第四、第六开关管S1、S4、S6的控制端接收低电平，第二、第三、第五开关管S2、S3、S5的控制端接收高电平。也即，在显示模式下，第二、第三、第五开关管S2、S3、S5始终导通，第一、第四、第六开关管S1、S4、S6始终关断。
进一步，在感测模式的电位初始化阶段t1：所述扫描信号Scan为高电平，第一、第二、第四、第六开关管S1、S2、S4、S6的控制端接收低电平，第三、第五开关管S3、S5的控制端接收高电平。在感测模式的感测阶段t2：所述扫描信号Scan为高电平，第一、第四、第六开关管S1、S4、S6的控制端接收高电平，第二、第三、第五开关管S2、S3、S5的控制端接收低电平。
本发明的实施方式
参考图6‐8，其中图6为本发明所述的OLED像素驱动电路第二实施例所示架构图，图7为图6所述的OLED像素驱动电路显示模式时序图，图8为图6所述的OLED像素驱动电路感测模式时序图。与图3所示实施例的不同之处在于，本实施例中第一至第六开关管S1‐S6均为MOS管。第一开关管S1与第二开关管S2的栅极短接用于接收相应的电平控制信号SW1/2，第一开关管S1与第二开关管S2的源极短接后电性连接第一薄膜晶体管T1的漏极，第一开关管S1的源极接入数据电流Idata，第二开关管S2的源极接入电源电压OVDD。第三开关管S3与第四开关管S4的栅极短接用于接收相应的电平控制信号SW3/4，第三开关管S3与第四开关管S4的源极短接后电性连接第三薄膜晶体管T3的漏极，第三开关管S3的漏极接入参考电压Vref，第四开关管S4的漏极接入第二模数转换器ADC2。第五开关管S5与第六开关管S6的栅极短接用于接收相应的电平控制信号SW5/6，第五开关管S5与第六开关管S6的源极短接后电性连接第二薄膜晶体管T2的漏极，第五开关管S5的漏极在显示模式下接入数据电压Vdata、在感测模式下接入初始化电压Vini，第六开关管S6的漏极接入第一模数转换器ADC1。
进一步，在显示模式的数据写入阶段t1：所述扫描信号Scan为高电平，第一、第二开关管S1、S2的栅极接收低电平(即SW1/2为低电平信号)，第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平(即SW3/4、SW5/6均为高电平信号)。在显示模式的发光阶段t2：所述扫描信号Scan为低电平，第一、第二开关管S1、S2的栅极接收低电平，第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平。也即，在显示模式下，第二、第三、第五开关管S2、S3、S5始终导通，第一、第四、第六开关管S1、S4、S6始终关断。
进一步，在感测模式的电位初始化阶段t1：所述扫描信号Scan为高电平，第一、第二开关管S1、S2的栅极接收低电平，第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收高电平；在感测模式的感测阶段t2：所述扫描信号Scan为高电平，第一、第二开关管S1、S2的栅极接收高电平，第三、第四、第五、第六开关管S3、S4、S5、S6的栅极接收低电平。
本发明还提供一种OLED显示装置，包括上述的OLED像素驱动电路，此处不再对该OLED像素驱动电路的结构及功能进行重复性描述。
本发明提供的OLED像素驱动电路及OLED显示装置，采用3T1C结构，通过控制不同开关管导通使得像素驱动电路的正常显示模式和感测模式都包含两个阶段；同时根据感测的驱动薄膜晶体管的阈值电压Vth以及OLED老化后的本征导电因子值k，在显示模式下进行相应的数据补偿，能够提高显示的均匀性，提高发光效率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (20)

  1. 一种OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式，其中，所述驱动电路包括：
    第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压；
    第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；
    第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；
    电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；
    有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；
    第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内；
    显示模式分为数据写入阶段与发光阶段，在显示模式的数据写入阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在显示模式的发光阶段：所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷为所述数据电压与所述参考电压的差值，所述有机发光二极管发光；
    感测模式分为电平初始化阶段与感测阶段，在感测模式的电位初始化阶段：
    所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在感测模式的感测阶段：所述扫描信号为高电平，所述第五开关管、第三开关管在相应的电平控制信号控制下关断，所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通，通过输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
  2. 如权利要求1所述的电路，其中，在感测模式的感测阶段：输入第一数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第一电压差；输入第二数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第二电压差；联立方程组Idata1＝k(Vgs1-Vth)和Idata2＝k(Vgs2-Vth)，获取所述第一薄膜晶体管的阈值电压以及本征导电因子 值；其中，Idata1为所述第一数据电流、Vgs1为所述第一电压差、Idata2为所述第二数据电流、Vgs2为所述第二电压差、Vth为所述第一薄膜晶体管的阈值电压、k为本征导电因子值。
  3. 如权利要求1所述的电路，其中，第一至第六开关管均为开关元件；
    所述第一开关管与所述第二开关管的控制端用于分别接收相应的电平控制信号，所述第一开关管与所述第二开关管的第一接入点短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的第二接入点接入所述数据电流，所述第二开关管的第二接入点接入所述电源电压；
    所述第三开关管与所述第四开关管的控制端用于分别接收相应的电平控制信号，所述第三开关管与所述第四开关管的第一接入点短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的第二接入点接入所述参考电压，所述第四开关管的第二接入点接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的控制端用于分别接收相应的电平控制信号，所述第五开关管与所述第六开关管的第一接入点短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的第二接入点在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的第二接入点接入所述第一模数转换器。
  4. 如权利要求3所述的电路，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；
    在感测模式的电平初始化阶段：所述扫描信号为高电平，第一、第二、第四、 第六开关管的控制端接收低电平，第三、第五开关管的控制端接收高电平；在感测模式的感测阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收高电平，第二、第三、第五开关管的控制端接收低电平。
  5. 如权利要求1所述的电路，其中，第一至第六开关管均为MOS管；
    所述第一开关管与所述第二开关管的栅极短接用于接收相应的电平控制信号，所述第一开关管与所述第二开关管的源极短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的源极接入所述数据电流，所述第二开关管的源极接入所述电源电压；
    所述第三开关管与所述第四开关管的栅极短接用于接收相应的电平控制信号，所述第三开关管与所述第四开关管的源极短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的漏极接入所述参考电压，所述第四开关管的漏极接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的栅极短接用于接收相应的电平控制信号，所述第五开关管与所述第六开关管的源极短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的漏极在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的漏极接入所述第一模数转换器。
  6. 如权利要求5所述的电路，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；
    在感测模式的电位初始化阶段：所述扫描信号为高电平，第一、第二开关管 的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在感测模式的感测阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收高电平，第三、第四、第五、第六开关管的栅极接收低电平。
  7. 一种OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式，其中，所述驱动电路包括：
    第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压；
    第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；
    第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；
    电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；
    有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；
    在显示模式下，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通；显示模式分为数据写入阶段与发光阶段，所述扫描信号在数据写入阶段为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述数据电压与所述参考电压接入电路，所述扫描信号在发光阶段为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷使得所述有机发光二极管发光；
    在感测模式下，所述第五开关管、第三开关管先在相应的电平控制信号控制下导通，然后所述第五开关管、第三开关管在相应的电平控制信号控制下关断，同时所述第一开关管、第六开关管、第四开关管在相应的电平控制信号 控制下导通；感测模式分为电平初始化阶段与感测阶段，所述扫描信号始终为高电平，在电位初始化阶段所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述初始化电压与所述参考电压接入电路，在感测阶段所述数据电流接入电路，通过输入不同数据电流使得所述第一模数转换器与所述第二模数转换器感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
  8. 如权利要求7所述的电路，其中，
    在显示模式的数据写入阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在显示模式的发光阶段：所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷为所述数据电压与所述参考电压的差值，所述有机发光二极管发光；
    在感测模式的电位初始化阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在感测模式的感测阶段：所述扫描信号为高电平，所述第五开关管、第三开关管在相应的电平控制信号控制下关断，所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通，输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测 所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
  9. 如权利要求8所述的电路，其中，在感测模式的感测阶段：输入第一数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第一电压差；输入第二数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第二电压差；联立方程组Idata1＝k(Vgs1-Vth)和Idata2＝k(Vgs2-Vth)，获取所述第一薄膜晶体管的阈值电压以及本征导电因子值；其中，Idata1为所述第一数据电流、Vgs1为所述第一电压差、Idata2为所述第二数据电流、Vgs2为所述第二电压差、Vth为所述第一薄膜晶体管的阈值电压、k为本征导电因子值。
  10. 如权利要求7所述的电路，其中，第一至第六开关管均为开关元件；
    所述第一开关管与所述第二开关管的控制端用于分别接收相应的电平控制信号，所述第一开关管与所述第二开关管的第一接入点短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的第二接入点接入所述数据电流，所述第二开关管的第二接入点接入所述电源电压；
    所述第三开关管与所述第四开关管的控制端用于分别接收相应的电平控制 信号，所述第三开关管与所述第四开关管的第一接入点短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的第二接入点接入所述参考电压，所述第四开关管的第二接入点接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的控制端用于分别接收相应的电平控制信号，所述第五开关管与所述第六开关管的第一接入点短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的第二接入点在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的第二接入点接入所述第一模数转换器。
  11. 如权利要求10所述的电路，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；
    在感测模式的电平初始化阶段：所述扫描信号为高电平，第一、第二、第四、第六开关管的控制端接收低电平，第三、第五开关管的控制端接收高电平；
    在感测模式的感测阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收高电平，第二、第三、第五开关管的控制端接收低电平。
  12. 如权利要求7所述的电路，其中，第一至第六开关管均为MOS管；
    所述第一开关管与所述第二开关管的栅极短接用于接收相应的电平控制信号，所述第一开关管与所述第二开关管的源极短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的源极接入所述数据电流，所述第二开关管的源极接入所述电源电压；
    所述第三开关管与所述第四开关管的栅极短接用于接收相应的电平控制信 号，所述第三开关管与所述第四开关管的源极短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的漏极接入所述参考电压，所述第四开关管的漏极接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的栅极短接用于接收相应的电平控制信号，所述第五开关管与所述第六开关管的源极短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的漏极在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的漏极接入所述第一模数转换器。
  13. 如权利要求12所述的电路，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；
    在感测模式的电位初始化阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在感测模式的感测阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收高电平，第三、第四、第五、第六开关管的栅极接收低电平。
  14. 如权利要求7所述的电路，其中，第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内。
  15. 一种OLED显示装置，包括OLED像素驱动电路，所述驱动电路工作状态包括显示模式和感测模式；其中，所述驱动电路包括：
    第一薄膜晶体管，栅极电性连接第一节点，源极电性连接第二节点，漏极通过第一开关管接入数据电流、同时通过第二开关管接入电源电压； 第二薄膜晶体管，栅极接入扫描信号，源极电性连接所述第一节点，漏极分别接入数据信号、通过第五开关管在显示模式下接入数据电压及在感测模式下接入初始化电压、以及通过第六开关管接入第一模数转换器；
    第三薄膜晶体管，栅极接入扫描信号，源极电性连接所述第二节点，漏极通过第三开关管接入参考电压、同时通过第四开关管接入第二模数转换器；电容，一端电性连接所述第一节点，另一端电性连接所述第二节点；
    有机发光二极管，阳极电性连接所述第二节点，阴极接入公共接地电压；第一至第六开关管、所述第一模数转换器以及所述第二模数转换器均设置在驱动IC内；
    显示模式分为数据写入阶段与发光阶段，在显示模式的数据写入阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第二开关管、第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述数据电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在显示模式的发光阶段：所述扫描信号为低电平使得所述第二薄膜晶体管与所述第三薄膜晶体管关断，所述电容存储的电荷为所述数据电压与所述参考电压的差值，所述有机发光二极管发光；
    感测模式分为电平初始化阶段与感测阶段，在感测模式的电位初始化阶段：所述扫描信号为高电平使得所述第二薄膜晶体管与所述第三薄膜晶体管导通，所述第五开关管、第三开关管在相应的电平控制信号控制下导通，所述第一节点通过所述第二薄膜晶体管与所述第五开关管写入所述初始化电压，所述第二节点通过所述第三薄膜晶体管与所述第三开关管写入所述参考电压；在感测模式的感测阶段：所述扫描信号为高电平，所述第五开关管、第 三开关管在相应的电平控制信号控制下关断，所述第一开关管、第六开关管、第四开关管在相应的电平控制信号控制下导通，通过输入不同数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而感测到所述第一薄膜晶体管的阈值电压以及本征导电因子值。
  16. 如权利要求15所述的装置，其中，在感测模式的感测阶段：输入第一数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测所述第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第一电压差；输入第二数据电流通过所述第一薄膜晶体管对所述第二节点充放电，电流稳定后，所述第一模数转换器通过所述第二薄膜晶体管与所述第六开关管感测第一节点电位，所述第二模数转换器通过所述第三薄膜晶体管与所述第四开关管感测所述第二节点电位，从而获取所述第一薄膜晶体管的栅极与源极之间的第二电压差；联立方程组Idata1＝k(Vgs1-Vth)和Idata2＝k(Vgs2-Vth)，获取所述第一薄膜晶体管的阈值电压以及本征导电因子值；其中，Idata1为所述第一数据电流、Vgs1为所述第一电压差、Idata2为所述第二数据电流、Vgs2为所述第二电压差、Vth为所述第一薄膜晶体管的阈值电压、k为本征导电因子值。
  17. 如权利要求15所述的装置，其中，第一至第六开关管均为开关元件；
    所述第一开关管与所述第二开关管的控制端用于分别接收相应的电平控制 信号，所述第一开关管与所述第二开关管的第一接入点短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的第二接入点接入所述数据电流，所述第二开关管的第二接入点接入所述电源电压；
    所述第三开关管与所述第四开关管的控制端用于分别接收相应的电平控制信号，所述第三开关管与所述第四开关管的第一接入点短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的第二接入点接入所述参考电压，所述第四开关管的第二接入点接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的控制端用于分别接收相应的电平控制信号，所述第五开关管与所述第六开关管的第一接入点短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的第二接入点在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的第二接入点接入所述第一模数转换器。
  18. 如权利要求17所述的装置，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第四、第六开关管的控制端接收低电平，第二、第三、第五开关管的控制端接收高电平；
    在感测模式的电平初始化阶段：所述扫描信号为高电平，第一、第二、第四、第六开关管的控制端接收低电平，第三、第五开关管的控制端接收高电平；
    在感测模式的感测阶段：所述扫描信号为高电平，第一、第四、第六开关管的控制端接收高电平，第二、第三、第五开关管的控制端接收低电平。
  19. 如权利要求15所述的装置，其中，第一至第六开关管均为MOS管；
    所述第一开关管与所述第二开关管的栅极短接用于接收相应的电平控制信 号，所述第一开关管与所述第二开关管的源极短接后电性连接所述第一薄膜晶体管的漏极，所述第一开关管的源极接入所述数据电流，所述第二开关管的源极接入所述电源电压；
    所述第三开关管与所述第四开关管的栅极短接用于接收相应的电平控制信号，所述第三开关管与所述第四开关管的源极短接后电性连接所述第三薄膜晶体管的漏极，所述第三开关管的漏极接入所述参考电压，所述第四开关管的漏极接入所述第二模数转换器；
    所述第五开关管与所述第六开关管的栅极短接用于接收相应的电平控制信号，所述第五开关管与所述第六开关管的源极短接后电性连接所述第二薄膜晶体管的漏极，所述第五开关管的漏极在显示模式下接入所述数据电压、在感测模式下接入所述初始化电压，所述第六开关管的漏极接入所述第一模数转换器。
  20. 如权利要求19所述的装置，其中，在显示模式的数据写入阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在显示模式的发光阶段：所述扫描信号为低电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；
    在感测模式的电位初始化阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收低电平，第三、第四、第五、第六开关管的栅极接收高电平；在感测模式的感测阶段：所述扫描信号为高电平，第一、第二开关管的栅极接收高电平，第三、第四、第五、第六开关管的栅极接收低电平。
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