WO2020006848A1 - 集成肖特基二极管的u型源槽vdmosfet器件 - Google Patents

集成肖特基二极管的u型源槽vdmosfet器件 Download PDF

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Publication number
WO2020006848A1
WO2020006848A1 PCT/CN2018/102830 CN2018102830W WO2020006848A1 WO 2020006848 A1 WO2020006848 A1 WO 2020006848A1 CN 2018102830 W CN2018102830 W CN 2018102830W WO 2020006848 A1 WO2020006848 A1 WO 2020006848A1
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source
region
schottky diode
gate
drift region
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PCT/CN2018/102830
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English (en)
French (fr)
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汤晓燕
陈辉
张玉明
宋庆文
张艺蒙
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西安电子科技大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

Definitions

  • the invention relates to the field of microelectronic technology, and in particular to a U-shaped source-slot VDMOSFET device with integrated Schottky diode.
  • the wide band gap semiconductor material silicon carbide has a large forbidden band width, a high critical breakdown electric field, and excellent physical and chemical characteristics such as high thermal conductivity and high electron saturation drift speed.
  • a P + ohmic contact region is usually introduced on the surface of the P-type base region to short-circuit the P-type base region and the N + source region.
  • the VDMOSFET acts as a power switch in the converter.
  • the phenomenon of "power degradation” occurs, which increases the on-resistance and forward voltage drop of the diode. And cause reliability problems.
  • a Schottky diode with a turn-on voltage lower than the body diode is usually used in parallel across the source and drain of the device to provide a freewheeling path and ensure that the body diode does not conduct. This method greatly increases The complexity and cost of circuit design.
  • the present invention provides a U-shaped source-slot VDMOSFET device with an integrated Schottky diode.
  • the technical problem to be solved by the present invention is achieved through the following technical solutions:
  • the application provides a U-shaped source-slot VDMOSFET device with an integrated Schottky diode, including: a substrate; and
  • a drain disposed below the substrate
  • N-drift region disposed above the substrate
  • N + source region located in N-drift regions on both sides of the source
  • P-type base regions which are arranged in N-drift regions on both sides of the source;
  • a gate-source isolation layer disposed above the N + source region
  • a gate dielectric disposed above the N-drift region
  • a gate disposed above the gate dielectric
  • the interface between the source and the N-drift region is Schottky contact.
  • the interface between the source and the N + source region is an ohmic contact.
  • the interface between the source and the P-type base region is an ohmic contact.
  • the gate is polysilicon.
  • a gate metal is further included, which is disposed above the gate.
  • the doping concentration of the P-type base region near the surface is 1 ⁇ 10 17 cm -3 .
  • the doping concentration of the P-type base region below the N + source region is 5 ⁇ 10 18 cm - 3 .
  • the depth of the source trench where the source is located is greater than the junction depth of the N + source region and smaller than the junction depth of the P-type base region.
  • the substrate is an N-type SiC material
  • the thickness is 200 ⁇ m to 500 ⁇ m
  • the doping concentration is 5 ⁇ 10 18 cm -3 to 1 ⁇ 10 20 cm -3
  • the doping ion is a nitrogen ion.
  • the N + source region is an N-type SiC material with a thickness of 0.3 to 0.5 ⁇ m, a doping concentration of 5 ⁇ 10 18 cm -3 , and a doping ion is a nitrogen ion.
  • the invention provides a U-shaped source-slot VDMOSFET device with integrated Schottky diode.
  • the device forms a Schottky diode through Schottky contact at the U-shaped source slot position (the interface where the source contacts the N-drift region).
  • the external Schottky diode instead of the external Schottky diode as a freewheeling path, it does not cause the "dielectric degradation" of the body diode, while reducing the extra Schottky diode, reducing the area of the device, improving the reliability of the device and reducing Complexity and cost of device design.
  • the device does not need to introduce a surface P + ohmic contact region by forming a U-shaped source trench at the source electrode. While reducing the area and cost, the surface is lightly doped in the P-type base region through multiple ion implantations. The concentration distribution of heavy doping at the bottom, so as to achieve an ohmic contact at the interface between the source and the P-type base region, and inhibit the parasitic NPN transistor from turning on.
  • a U-shaped source trench is formed at the source electrode through a shallower etching depth. This process step can be completed in the etching mark step in the traditional process without adding a new etching process step.
  • FIG. 1 is a schematic diagram of a U-shaped source trench VDMOSFET device with an integrated Schottky diode according to an embodiment of the present invention.
  • VDMOSFET vertical double-diffused MOSFET
  • vertical double-diffused metal oxide semiconductor field effect transistor Vertical double-diffused metal oxide semiconductor field effect transistor
  • a first embodiment of the present application relates to a U-shaped source trench VDMOSFET device with an integrated Schottky diode. As shown in Figure 1, the device includes:
  • the drain 9 is disposed below the substrate 8;
  • N-drift region 7 is disposed above the substrate 8;
  • the source electrode 4 is disposed above the N-drift region 7;
  • N + source region 5 is disposed in N-drift region 7 on both sides of source electrode 4;
  • the P-type base region 6 is disposed in the N-drift region 7 on both sides of the source electrode 4 and is located below the N + source region 5;
  • the gate-source isolation layer 3 is disposed above the N + source region 5;
  • the gate dielectric 2 is disposed above the N-drift region 7;
  • the gate 10 is disposed above the gate dielectric 2;
  • the interface between the source electrode 4 and the N-drift region 7 is a Schottky contact.
  • the interface between the source electrode 4 and the N + source region 5 is an ohmic contact.
  • the interface between the source electrode 4 and the P-type base region 6 is an ohmic contact.
  • the gate 10 is polysilicon.
  • the device further includes a gate metal 1 disposed above the gate 10 for metal interconnection between the gate and other circuits.
  • the gate metal 1 is a Ti or Ni or Au material.
  • the surface of the P-type base region 6 (that is, the region where the P-type base region 6 is close to the gate dielectric 2 and has the same thickness as the N + source region 5) has a lower doping concentration and a higher doping concentration at the bottom;
  • the impurity concentration is 1 ⁇ 10 17 cm -3
  • the doping concentration of the P-type base region 6 located below the N + source region 5 is 5 ⁇ 10 18 cm - 3 .
  • the depth of the U-shaped source groove (ie, the distance between the bottom surface of the U-shaped source groove and the upper surface of the N + source region 5) is greater than the junction depth of the N + source region 5 and smaller than the junction depth of the P-type base region 6.
  • the source electrode 4 is made of Ti or Ni or Au material
  • the drain electrode 9 is made of Ti or Ni or Au material.
  • the substrate 8 is an N-type SiC material with a thickness of 200 ⁇ m to 500 ⁇ m, a doping concentration of 5 ⁇ 10 18 cm -3 to 1 ⁇ 10 20 cm -3 , and the doping ion is a nitrogen ion.
  • the N + source region 5 is an N-type SiC material with a thickness of 0.3 to 0.5 ⁇ m, a doping concentration of 5 ⁇ 10 18 cm -3 , and a doping ion is a nitrogen ion.
  • the N-drift region 7 is an N-type SiC material with a thickness of 10 ⁇ m to 20 ⁇ m, a doping concentration of 1 ⁇ 10 15 cm -3 to 8 ⁇ 10 15 cm -3 , and the doping ion is a nitrogen ion. .
  • the MOS switch In the operation of the device, when the device's gate voltage is low, the MOS switch is turned off.
  • the anode of the Schottky diode is the source of the MOS switch and the cathode is the drain of the MOS switch. Between them, the Schottky diode is turned on, and the load current flows from the source to the drain through the Schottky diode.
  • the MOS switch When the device's gate voltage is high, the MOS switch is on, the Schottky diode is off, and the source and drain are turned on through the MOS switch.
  • an action is performed according to an element, it means that the action is performed at least according to the element, which includes two cases: performing the action based on the element only, and according to the element and Other elements perform the action.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

本发明涉及集成电路领域，公开了一种集成肖特基二极管的U型源槽VDMOSFET器件，包括：衬底(8)；漏极(9)，设置在所述衬底(8)下方；N-漂移区(7)，设置在所述衬底(8)上方；源极(4)，设置在所述N-漂移区(7)上方；N+源区(5)，设置在所述源极(4)两侧的所述N-漂移区(7)中；P型基区(6)，设置在所述N-漂移区(7)内部；栅源隔离层(3)，设置在所述N+源区(5)上方；栅介质(2)，栅极(10)；所述源极(4)与所述N-漂移区(7)的界面为肖特基接触。所述器件能够提高器件性能的可靠性，并降低设计的复杂性和成本。

Description

集成肖特基二极管的U型源槽VDMOSFET器件 技术领域
本发明涉及微电子技术领域，具体涉及一种集成肖特基二极管的U型源槽VDMOSFET器件。
背景技术
宽带隙半导体材料碳化硅具有较大的禁带宽度，较高的临界击穿电场，以及高热导率、高电子饱和漂移速度等优良物理和化学特性，适合制作高温、高压、大功率、抗辐照的半导体器件。在功率电子领域中，功率MOSFET已被广泛应用，它具有栅极驱动简单，开关时间短等特点。
现有的VDMOSFET结构中，为避免寄生NPN晶体管开启，通常会通过在P型基区表面引入P+欧姆接触区，使P型基区和N+源区短路。同时VDMOSFET在变流器中作为功率开关，当其体二极管作为续流通路持续流过正向电流时，会发生“通电劣化”现象，使导通电阻和二极管的正向导通压降增大，并引起可靠性问题。因此在实际的应用中，通常采用在器件源漏极两端并联一个开启电压小于体二极管的肖特基二极管的方法来提供续流通路并保证体二极管不会导通，这种方法极大地增加了电路设计的复杂性和成本费用。
发明内容
为了解决现有技术中存在的上述问题，本发明提供了一种集成肖特基二极管的U型源槽VDMOSFET器件。本发明要解决的技术问题通过以下 技术方案实现：
本申请提供了一种集成肖特基二极管的U型源槽VDMOSFET器件，包括：衬底；以及
漏极，设置在衬底下方；
N-漂移区，设置在衬底上方；
源极，设置在N-漂移区上方；
N+源区，设置在源极两侧的N-漂移区中；
P型基区，设置在源极两侧的N-漂移区中；
栅源隔离层，设置在N+源区上方；
栅介质，设置在N-漂移区上方；
栅极，设置在栅介质上方；
源极与N-漂移区的界面为肖特基接触。
在一个优选例中，源极与N+源区的界面为欧姆接触。
在一个优选例中，源极与P型基区的界面为欧姆接触。
在一个优选例中，栅极是多晶硅。
在一个优选例中，还包括栅金属，设置在栅极上方。
在一个优选例中，P型基区靠近表面的掺杂浓度为1×10 17cm -3。
在一个优选例中,位于N+源区下方的P型基区的掺杂浓度为5×10 18cm - 3。
在一个优选例中，源极所在的源槽的深度大于N+源区的结深，且小于P型基区的结深。
在一个优选例中，衬底为N型SiC材料，厚度为200μm～500μm，掺杂浓度为5×10 18cm -3～1×10 20cm -3，掺杂离子为氮离子。
在一个优选例中，N+源区为N型SiC材料，厚度为0.3～0.5μm，掺杂浓度为5×10 18cm -3，掺杂离子为氮离子。
与现有技术相比，本发明的有益效果：
本发明提供了一种集成肖特基二极管的U型源槽VDMOSFET器件，该器件在U型源槽位置(源极与N-漂移区接触的界面)通过肖特基接触形成肖特基二极管，替代外接的肖特基二极管作为续流通路，在不引起体二极管的“通电劣化”的同时，减少了额外的肖特基二极管，减小了器件的面积，提高了器件的可靠性并降低了器件设计的复杂性和成本。
进一步地，该器件通过在源极形成U型源槽，不需要引入表面P+欧姆接触区，在减小面积，降低成本的同时，通过多次离子注入在P型基区形成表面轻掺杂、底部重掺杂的浓度分布，从而实现源极与P型基区交界面的欧姆接触，抑制寄生NPN晶体管开启。
进一步地，本发明通过较浅的刻蚀深度在源极刻蚀形成U型源槽，这一步工艺步骤可以在传统工艺中的刻蚀标记这一步完成，无需增加新的刻蚀工艺步骤。
可以理解，在本发明范围内中，本发明的上述各技术特征和在下文(如实施方式和例子)中具体描述的各技术特征之间都可以互相组合，从而构成新的或优选的技术方案。限于篇幅，在此不再一一累述。
附图说明
图1为本发明实施方式中一种集成肖特基二极管的U型源槽VDMOSFET器件的示意图。
具体实施方式
在以下的叙述中，为了使读者更好地理解本申请而提出了许多技术细 节。但是，本领域的普通技术人员可以理解，即使没有这些技术细节和基于以下各实施方式的种种变化和修改，也可以实现本申请所要求保护的技术方案。
本申请涉及的术语解释：
VDMOSFET，(vertical double-diffused MOSFET)：垂直双扩散金属氧化物半导体场效应管。
为使本发明的目的、技术方案和优点更加清楚，下面结合具体实施例对本发明做进一步详细的描述，但本发明的实施方式不限于此。
本申请的第一实施方式涉及一种集成肖特基二极管的U型源槽VDMOSFET器件。如图1所示，该器件包括：
衬底8；以及
漏极9，设置在衬底8下方；
N-漂移区7，设置在衬底8上方；
源极4，设置在N-漂移区7上方；
N+源区5，设置在源极4两侧的N-漂移区7中；
P型基区6，设置在源极4两侧的N-漂移区7中，且位于N+源区5下方；
栅源隔离层3，设置在N+源区5上方；
栅介质2，设置在N-漂移区7上方；
栅极10，设置在栅介质2上方；
源极4与N-漂移区7的界面为肖特基接触。
在一个实施例中，源极4与N+源区5的界面为欧姆接触。
在一个实施例中，源极4与P型基区6的界面为欧姆接触。
在一个实施例中，栅极10是多晶硅。
在一个实施例中，该器件还包括栅金属1，设置在栅极10上方，用于栅极与其他电路之间的金属互联。优选地，栅金属1为Ti或Ni或Au材料。
在一个实施例中，P型基区6的表面(即P型基区6靠近栅介质2，与N+源区5厚度相同的区域)掺杂浓度较低，底部掺杂浓度较高；表面掺杂浓度为1×10 17cm -3，位于N+源区5下方的P型基区6的掺杂浓度为5×10 18cm - 3。
在一个实施例中，U型源槽深度(即U型源槽的底面与N+源区5的上表面的距离)大于N+源区5的结深，小于P型基区6的结深。
在一个实施例中，源极4为Ti或Ni或Au材料，漏极9为Ti或Ni或Au材料。
在一个实施例中，衬底8为N型SiC材料，厚度为200μm～500μm，掺杂浓度为5×10 18cm -3～1×10 20cm -3，掺杂离子为氮离子。
在一个实施例中，N+源区5为N型SiC材料，厚度为0.3～0.5μm，掺杂浓度为5×10 18cm -3，掺杂离子为氮离子。
在一个实施例中，N-漂移区7为N型SiC材料，其厚度为10μm～20μm，掺杂浓度为1×10 15cm -3～8×10 15cm -3，掺杂离子为氮离子。
在该器件工作中，当器件的栅压为低电平时，MOS开关处于关断状态，肖特基二极管的阳极为MOS开关的源极，阴极为MOS开关的漏极，此时源漏极之间通过肖特基二极管导通，负载电流从源极经肖特基二极管流向漏极；
当器件的栅压为高电平时，MOS开关处于导通状态，肖特基二极管处 于关断状态，源漏之间通过MOS开关导通。
需要说明的是，在本申请文件中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。本专利的申请文件中，如果提到根据某要素执行某行为，则是指至少根据该要素执行该行为的意思，其中包括了两种情况：仅根据该要素执行该行为、和根据该要素和其它要素执行该行为。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (10)

  1. 一种集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，包括：衬底(8)；以及
    漏极(9)，设置在所述衬底(8)下方；
    N-漂移区(7)，设置在所述衬底(8)上方；
    源极(4)，设置在所述N-漂移区(7)上方；
    N+源区(5)，设置在所述源极(4)两侧的所述N-漂移区(7)中；
    P型基区(6)，设置在所述源极(4)两侧的所述N-漂移区(7)中；
    栅源隔离层(3)，设置在所述N+源区(5)上方；
    栅介质(2)，设置在所述N-漂移区(7)上方；
    栅极(10)，设置在所述栅介质(2)上方；
    所述源极(4)与所述N-漂移区(7)的界面为肖特基接触。
  2. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述源极(4)与所述N+源区(5)的界面为欧姆接触。
  3. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述源极(4)与所述P型基区(6)的界面为欧姆接触。
  4. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述栅极(10)是多晶硅。
  5. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，还包括栅金属(1)，设置在所述栅极(10)上方。
  6. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述P型基区(6)靠近表面的掺杂浓度为1×10 17cm -3。
  7. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，位于所述N+源区(5)下方的P型基区(6)的掺杂浓度 为5×10 18cm -3。
  8. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述源极(4)所在的源槽的深度大于所述N+源区(5)的结深，且小于所述P型基区(6)的结深。
  9. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述衬底(8)为N型SiC材料，厚度为200μm～500μm，掺杂浓度为5×10 18cm -3～1×10 20cm -3，掺杂离子为氮离子。
  10. 根据权利要求1所述的集成肖特基二极管的U型源槽VDMOSFET器件，其特征在于，所述N+源区(5)为N型SiC材料，厚度为0.3～0.5μm，掺杂浓度为5×10 18cm -3，掺杂离子为氮离子。
PCT/CN2018/102830 2018-07-04 2018-08-29 集成肖特基二极管的u型源槽vdmosfet器件 WO2020006848A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101950759A (zh) * 2010-08-27 2011-01-19 电子科技大学 一种Super Junction VDMOS器件
CN102723363A (zh) * 2011-03-29 2012-10-10 比亚迪股份有限公司 一种vdmos器件及其制作方法
US9530880B2 (en) * 2015-03-03 2016-12-27 Micrel, Inc. DMOS transistor with trench schottky diode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101950759A (zh) * 2010-08-27 2011-01-19 电子科技大学 一种Super Junction VDMOS器件
CN102723363A (zh) * 2011-03-29 2012-10-10 比亚迪股份有限公司 一种vdmos器件及其制作方法
US9530880B2 (en) * 2015-03-03 2016-12-27 Micrel, Inc. DMOS transistor with trench schottky diode

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