WO2020006749A1 - 芯片阻抗测试方法及*** - Google Patents

芯片阻抗测试方法及*** Download PDF

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Publication number
WO2020006749A1
WO2020006749A1 PCT/CN2018/094815 CN2018094815W WO2020006749A1 WO 2020006749 A1 WO2020006749 A1 WO 2020006749A1 CN 2018094815 W CN2018094815 W CN 2018094815W WO 2020006749 A1 WO2020006749 A1 WO 2020006749A1
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Prior art keywords
test
voltage value
power supply
terminal
port
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PCT/CN2018/094815
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English (en)
French (fr)
Inventor
沈丹禹
童天涯
宋海宏
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深圳市汇顶科技股份有限公司
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Priority to CN201880000935.6A priority Critical patent/CN109073689A/zh
Priority to PCT/CN2018/094815 priority patent/WO2020006749A1/zh
Publication of WO2020006749A1 publication Critical patent/WO2020006749A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant

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  • the embodiments of the present application relate to the technical field of electronic devices, and in particular, to a chip impedance test method and system.
  • one of the technical problems solved by the embodiments of the present application is to provide a chip impedance test method and system to overcome the problem that the impedance test within a chip in the prior art is affected by external factors and has poor accuracy.
  • An embodiment of the present application provides a chip impedance test system, including: a tester, the tester includes a device power source, the device power source is connected to a ground pin and an I / O port of a chip to be tested, and the tester adjusts the ground pin through the device power source.
  • the voltage value so that the voltage value of the ground pin is the same as the voltage value of the ground terminal of the test machine; the test machine outputs a test current to the I / O port through the device power supply, and tests the voltage value at the I / O port, according to the I / O port
  • the voltage value at, the voltage value at the ground pin, and the current value of the test current determine the resistance value between the I / O port and the ground pin.
  • the test system further includes a LB board for testing, and a ground pin of the chip to be tested is connected to a ground terminal of the test machine through a first connection path of the LB board for testing.
  • the voltage of the ground pin and the ground terminal of the tester is 0V.
  • the device power supply includes a first power supply unit, and the first power supply unit is configured to be connected to a ground pin of a chip to be tested.
  • the first power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal. Both the positive output terminal and the positive test terminal are connected to the ground pin, and the negative output terminal and the negative test terminal are both connected to the test machine. Ground connection.
  • the device power supply includes a second power supply unit, and the second power supply unit is configured to be connected to the I / O port of the chip under test.
  • the second power supply unit includes a positive output terminal, a negative output terminal, a positive test terminal, and a negative test terminal. Both the positive output terminal and the positive test terminal are connected to the I / O port, and the negative output terminal and the negative test terminal are connected to the test machine. The ground terminal is connected.
  • a test method for a chip under test is provided.
  • the tester adjusts the voltage value of the ground pin of the chip under test through the power supply of the device, so that the voltage value of the ground pin and the voltage value of the ground terminal in the test machine Equal; the tester outputs the test current from the I / O port of the chip to be tested through the power supply of the device, and tests the voltage value at the I / O port; the tester is based on the current value of the test current, the voltage value at the I / O port, and the test The voltage value of the ground pin of the chip determines the resistance value between the I / O port of the chip under test and the ground pin.
  • the tester includes a first power supply unit, and the tester adjusts the voltage value of the ground pin of the chip under test through the device power supply, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the test machine, including:
  • the first power supply unit supplies power to the ground pin of the chip under test, so that the voltage value of the ground pin is equal to the voltage value of the ground terminal in the tester.
  • the tester includes a second power supply unit, and the tester outputs a test current through an equipment power supply to the I / O port of the chip to be tested, and tests the voltage value at the I / O port, including: the second power supply unit of the tester passes The I / O port outputs a test current to the chip under test and tests the voltage value at the I / O port.
  • the voltage value of the ground pin of the chip under test is adjusted by using the equipment power in the test machine to make the voltage between the ground pin of the test machine and the ground terminal of the test machine.
  • the values are consistent, so that during the test, there is no voltage drop between the ground pin of the chip under test and the ground terminal of the test machine, thereby avoiding the ground pin of the chip under test and the ground terminal of the test machine in the prior art.
  • the voltage of the ground pin of the chip under test is not an ideal value due to the existence of the environmental resistance between the two, and the internal resistance test of the chip under test is inaccurate.
  • FIG. 1 is a schematic structural diagram of a chip impedance test system according to an embodiment of the present application.
  • FIG. 2 is a schematic flowchart of a chip impedance test method according to an embodiment of the present application.
  • Chip to be tested 20. Test machine; 30. LB board for testing.
  • a chip impedance test system includes: a tester 20, the tester 20 includes a device power source, and the device power source and a ground pin of the chip under test 10 (the test target shown in FIG. 1) GND at the chip 10) and I / O port connection, the tester 20 adjusts the voltage of the ground pin GND through the device power supply, so that the voltage of the ground pin GND is the same as the voltage of the ground terminal of the tester 20; the tester 20 Output the test current to the I / O port through the device power supply, and test the voltage value at the I / O port. Determine the I / O based on the voltage value at the I / O port, the voltage value at the ground pin GND, and the current value of the test current. The resistance value between the O port and the ground pin GND.
  • the equipment power of the testing machine 20 is used to force adjust the voltage value of the ground pin GND of the chip under test 10 so that the voltage value is equal to the voltage value of the ground terminal of the testing machine 20, so as to ensure that the chip is tested.
  • the equipment power of the testing machine 20 is used to force adjust the voltage value of the ground pin GND of the chip under test 10 so that the voltage value is equal to the voltage value of the ground terminal of the testing machine 20, so as to ensure that the chip is tested.
  • the test system further includes a test LB board 30, and the chip under test 10 and the tester 20 are connected through the test LB board 30 to improve the convenience of the connection and further improve the test efficiency.
  • the ground pin GND of the chip under test 10 passes the first connection path of the LB board 30 for testing (ie, the path formed from point J to point I shown in FIG. 1), and the environmental resistance on it is equivalent to the resistances RG1 and The resistor RG2) is connected to the ground terminal of the tester 20.
  • the ground pin GND of the chip under test 10 passes through the second connection path of the test LB (Load Board) board 30 (that is, the path formed by the points A to E and B to F shown in FIG. 1, A
  • the environmental resistance between point E and point E is equivalent to resistance RA1 and resistance RA2, and the environmental resistance between point B and point F is equivalent to RB1 and resistance RB2) and is connected to the equipment power supply of the tester 20.
  • the second connection path is used to enable the power source of the device to supply power to the ground pin GND of the chip under test 10 to adjust its voltage value.
  • the I / O port of the chip under test 10 passes through the third connection path of the test LB board 30 (that is, the path formed from point C to point G and point D to point H shown in FIG. 1, where point C to point G
  • the environmental resistance is equivalent to the resistance RC1 and the resistance RC2, and the environmental resistance from point D to the point H is equivalent to the resistance RD1 and the resistance RD2) and is connected to the equipment power source of the testing machine 20.
  • the third connection path is used for powering the device power supply to the I / O port of the chip under test 10 to output a test current.
  • the power supply of the device includes a first power supply unit (ie, DPS1 shown in FIG. 1), and the first power supply unit DPS1 is configured to be connected to the ground pin GND of the chip under test 10 to adjust the ground The voltage value of pin GND.
  • DPS1 a first power supply unit
  • the first power supply unit includes a positive output terminal (the F + port of DPS1 shown in FIG. 1, that is, the positive output terminal of the device power supply), and a negative output terminal (the F- port of DPS1 shown in FIG. 1, that is, The negative output terminal of the device power supply), the positive test terminal (the S + port of DPS1 shown in Figure 1, that is, the positive sampling terminal of the device power supply), and the negative test terminal (the S-port of DPS1 shown in Figure 1) , That is, the negative sampling terminal of the device power supply), the positive output terminal F + and the positive test terminal S + are connected to the ground pin GND, and the negative output terminal F- and the negative test terminal S- are connected to the ground terminal of the tester 20.
  • the negative output terminal F- and the negative test terminal S- of the first power supply unit DSP1 are both connected to the ground terminal of the testing machine 20, its potential value is equal to the potential value of the ground terminal of the testing machine 20.
  • the potential value of the ground terminal of the testing machine 20 is 0V. Therefore, in this embodiment, the potential value of the ground terminal is 0V for example, that is, the first power supply unit DPS1 adjusts the voltage value of the ground pin GND to 0V.
  • the potential value may be other values.
  • the ground pin GND output of the chip 10 to be tested can be adjusted to 0V, so that the voltage value of the ground pin GND is equal to the voltage value of the ground terminal, thereby ensuring that During the test, there was no voltage drop between the two, thereby shielding the environmental resistance between the ground pin GND and the ground terminal (resistors RG1 and RG2 shown in Figure 1).
  • the positive test terminal S + of the first power supply unit DPS1 is used to accurately test the voltage value of the ground pin GND, so as to provide feedback data for the testing machine 20 so that it can adjust the positive output terminal F + of the first power supply unit DPS1 through the feedback data.
  • the testing machine further includes a control unit, which is connected to the first power supply unit DPS1 and adjusts the output of the positive output terminal F + according to the voltage value detected by the positive test terminal S +.
  • the device power supply includes a second power supply unit DPS2, and the second power supply unit DPS2 is used to connect to the I / O port of the chip under test 10 to output a test current to the I / O port and measure the I / O port The voltage value.
  • the second power supply unit DPS2 includes a positive output terminal F +, a negative output terminal F-, a positive test terminal S +, and a negative test terminal S-.
  • the positive output terminal F + and the positive test terminal S + are connected to the I / O port, and the negative output terminal. Both F- and the negative test terminal S- are connected to the ground terminal of the tester 20.
  • the negative output terminal and the negative test terminal of the second power supply unit DPS2 are also connected to the ground terminal of the testing machine 20. Its function is similar to the negative output terminal and the negative test terminal of the first power supply unit DPS1, which will not be repeated here.
  • the positive output terminal F + of the second power supply unit DPS2 is used to output a test current to the I / O port.
  • the positive test terminal S + of the second power supply unit DPS2 is used to test the voltage value of the I / O port. Because the internal resistance of the positive test terminal S + is close to infinite, the positive test terminal S + and the I / O port are further increased. The environmental resistance value does not affect the test of the voltage value of the I / O port, thereby avoiding the impact of the environmental resistance on the I / O port side on the test accuracy.
  • the tester can be an ATE (Automatic Test Equipment) tester.
  • the device power supply can be a self-provided power supply (DPS, device power supply) inside the ATE tester.
  • the chip impedance test system uses the DPS resources of the ATE tester to accurately measure Rdson (internal resistance) or other impedance methods. Compared with the previous impedance test, this application uses a Kelvin four wire formed between the DPS that comes with the test machine and the ground pin of the chip under test 10 instead of the original one-way (F +, S +) solution. This makes it possible to accurately measure impedances such as Rdson without adding external resources.
  • the test is performed by using the positive output terminal and the positive test terminal of the two power supply units in the equipment power supply.
  • the existing negative output terminal and negative test terminal of the power supply unit are used to connect to the ground terminal of the test machine, so the environment of the ground terminal cannot be offset. Problems with impedance.
  • a method for testing a chip under test which includes the following steps:
  • Step S102 The testing machine 20 adjusts the voltage value of the ground pin GND of the chip under test 10 through the device power source, so that the voltage value of the ground pin GND is equal to the voltage value of the ground terminal in the testing machine 20.
  • the device power is output to the ground pin GND to forcibly adjust its voltage value to be equal to the voltage of the ground terminal.
  • the tester 20 includes a first power supply unit.
  • the first power supply unit is connected to the ground pin GND, and power is supplied to the ground pin GND of the chip 10 to be tested through the first power supply unit, so that the ground lead The voltage value of the pin GND is equal to the voltage value of the ground terminal in the testing machine 20.
  • Step S104 The tester 20 outputs a test current to the I / O port of the chip under test 10 through the device power source, and tests the voltage value at the I / O port.
  • an I / O port of the chip under test 10 outputs a current of 10 mA through a device power source.
  • the current value may be any appropriate current value, and is not limited to the exemplified 10 mA.
  • the tester 20 includes a second power supply unit.
  • the second power supply unit is connected to the I / O port.
  • the second power supply unit outputs a test current to the chip under test 10 through the I / O port, and tests.
  • Step S106 Determine the distance between the I / O port of the chip under test 10 and the ground pin GND according to the current value of the test current, the voltage value at the I / O port, and the voltage value of the ground pin GND of the chip under test 10. resistance.
  • the internal resistance value between the I / O port of the chip under test and the ground pin GND (denoted as R) is equal to the voltage value of the I / O port minus the voltage value of the ground pin GND, divided by the test current. Current value.
  • the voltage value of the ground pin GND is forcibly adjusted by the power supply of the device, so that there is no voltage difference between the ground pin and the ground terminal, thereby ensuring that the environmental resistance between the ground pin and the ground terminal of the test machine is not.
  • Will affect the test of the internal resistance R. Use the equipment power supply to detect the voltage value at the I / O port and calculate the internal resistance R based on the voltage value to ensure that the environmental resistance between the I / O port and the tester will not affect the test of the internal resistance R, thereby ensuring the internal resistance Test accuracy.
  • the environmental resistance existing in the existing testing process is avoided, for example, the resistance on the LB board 30 for testing, the impedance of the wire (including the on-resistance of the relay on the line, etc.), The contact impedance and the like, and the wiring or contact impedance and the like between the test LB board 30 and the tester.
  • the voltage across the internal resistance R and the current through the internal resistance R can be accurately obtained through the second power supply unit, so that the impedance of the internal resistance R can be accurately calculated.
  • the voltage value of the first power supply unit DPS1 is forcibly output (Force) 0V, that is, the potential of the point A in FIG. 1 is 0V through the first power supply unit DPS1.
  • the ground terminal of the testing machine 20 is connected to the negative output terminal F-, the negative test terminal S- of the first power supply unit DPS1, the negative output terminal F- and the negative test terminal S- of the second power supply unit DPS2. Therefore, when the first power supply unit DPS1 makes the voltage value of point A 0V, its positive output terminal F + will make the E potential point lower than that of the ground terminal of the testing machine, so that the current flows back from the positive output terminal F + path of the first power supply unit DPS1. .
  • the ground terminal of the testing machine, the negative output terminal F- of the first power supply unit DPS1, the negative output terminal F- of the second power supply unit DPS2, and the ground pin GND of the chip under test 10 are at the same potential point.
  • the second power supply unit DPS2 forcibly outputs (Force) 10 mA (denoted as I1) (specifically adjusted according to the actual situation), and the second power supply unit DPS2 can measure the voltage at point D (denoted as V1).
  • Internal resistance R V1 / I1 Calculate the resistance value of internal resistance R.
  • the ground pin GND is equal to 0V.
  • the ground pin of the chip under test 10 is directly connected to the ground terminal of the test machine, and then the I / O port of the chip under test is output and an internal resistance test is performed.
  • the voltage value of the default ground pin is equal to the voltage value of the ground terminal, which is 0V.
  • RG is RG1 + RG2, and RA, RB, RC, and RD are the same.

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  • General Physics & Mathematics (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种芯片阻抗测试***和方法，该芯片阻抗测试***包括：测试机（20），测试机（20）包括设备电源，设备电源与待测芯片（10）的接地引脚以及I/O端口连接，测试机（20）通过设备电源调节接地引脚的电压值，使接地引脚的电压值与测试机（20）的接地端的电压值相同；测试机（20）通过设备电源对I/O端口输出测试电流，并测试I/O端口处的电压值，根据I/O端口处的电压值、接地引脚处的电压值和测试电流的电流值确定I/O端口与接地引脚之间的电阻值。该芯片阻抗测试***能够准确测量芯片内阻。

Description

芯片阻抗测试方法及*** 技术领域
本申请实施例涉及电子设备技术领域，尤其涉及一种芯片阻抗测试方法及***。
背景技术
在IC芯片(Integrated Circuit集成电路)测试领域中，经常会测试Rdson(在芯片内的mos管导通的时候，与之等效的导通电阻)及其他阻抗。在现有测试过程中，因导线的阻抗、继电器的导通阻抗、针卡的接触阻抗、以及接触和脏污影响的阻抗等因素的影响，导致对IC芯片内阻抗测试的准确性不高。
因此，如何避免环境因素对测试的影响，成为亟待解决的问题。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种芯片阻抗测试方法及***，用以克服现有技术中芯片内阻抗测试受外部因素影响而准确性不好的问题。
本申请实施例提供一种芯片阻抗测试***，包括：测试机，测试机包括设备电源，设备电源与待测芯片的接地引脚以及I/O端口连接，测试机通过设备电源调节接地引脚的电压值，使接地引脚的电压值与测试机的接地端的电压值相同；测试机通过设备电源对I/O端口输出测试电流，并测试I/O端口处的电压值，根据I/O端口处的电压值、接地引脚处的电压值和测试电流的电流值确定I/O端口与接地引脚之间的电阻值。
可选地，测试***还包括测试用LB板，待测芯片的接地引脚通过测试用LB板的第一连接通路与测试机的接地端连接。
可选地，接地引脚和测试机的接地端的电压值为0V。
可选地，设备电源包括第一电源单元，第一电源单元用于与待测芯片的接地引脚连接。
可选地，第一电源单元包括正输出端、负输出端、正测试端和负测试端，正输出端和正测试端均与接地引脚连接，负输出端和负测试端均与测试机的 接地端连接。
可选地，设备电源包括第二电源单元，第二电源单元用于与待测芯片的I/O端口连接。
可选地，第二电源单元包括正输出端、负输出端、正测试端和负测试端，正输出端和正测试端均与I/O端口连接，负输出端和负测试端均与测试机的接地端连接。
根据本申请的另一方面，提供一种待测芯片测试方法，测试机通过设备电源调节待测芯片的接地引脚的电压值，使接地引脚的电压值与测试机中的接地端的电压值相等；测试机通过设备电源对待测芯片的I/O端口输出测试电流，并测试I/O端口处的电压值；测试机根据测试电流的电流值、I/O端口处的电压值和待测芯片的接地引脚的电压值，确定待测芯片的I/O端口与接地引脚之间的电阻值。
可选地，测试机包括第一电源单元，测试机通过设备电源调节待测芯片的接地引脚的电压值，使接地引脚的电压值与测试机中的接地端的电压值相等，包括：通过第一电源单元对待测芯片的接地引脚供电，使接地引脚的电压值与测试机中的接地端的电压值相等。
可选地，测试机包括第二电源单元，测试机通过设备电源对待测芯片的I/O端口输出测试电流，并测试I/O端口处的电压值，包括：测试机的第二电源单元通过I/O端口对待测芯片输出测试电流，并测试I/O端口处的电压值。
由以上技术方案可见，本申请实施例芯片阻抗测试***中，利用测试机中自有的设备电源对待测芯片的接地引脚的电压值进行调节，使其与测试机的接地端之间的电压值一致，从而使得在测试过程中，待测芯片的接地引脚与测试机的接地端之间无压降，从而避免了现有技术中将待测芯片的接地引脚与测试机的接地端连接后，两者之间由于存在环境电阻而导致待测芯片的接地引脚的电压值不为理想值而造成的待测芯片的内阻测试不准的问题。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面 描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本申请的实施例的芯片阻抗测试***的结构示意图；
图2为本申请的实施例的芯片阻抗测试方法的流程示意图。
附图标记说明：
10、待测芯片；20、测试机；30、测试用LB板。
具体实施方式
为使得本申请实施例的发明目的、特征、优点能够更加的明显和易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请实施例一部分实施例，而非全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请实施例保护的范围。
下面结合本申请实施例附图进一步说明本申请实施例具体实现。
如图1所示，根据本申请的实施例，芯片阻抗测试***包括：测试机20，测试机20包括设备电源，设备电源与待测芯片10的接地引脚(图1中所示的待测芯片10处的GND)以及I/O端口连接，测试机20通过设备电源调节接地引脚GND的电压值，使接地引脚GND的电压值与测试机20的接地端的电压值相同；测试机20通过设备电源对I/O端口输出测试电流，并测试I/O端口处的电压值，根据I/O端口处的电压值、接地引脚GND处的电压值和测试电流的电流值确定I/O端口与接地引脚GND之间的电阻值。
该芯片阻抗测试***中，利用测试机20的设备电源强制调节待测芯片10的接地引脚GND的电压值，使其电压值与测试机20的接地端的电压值相等，这样保证在对芯片进行测试的过程中，待测芯片10的接地引脚GND与测试机20的接地端之间无压差，从而使待测芯片10的接地引脚GND与接地端之间的环境电阻无效化，进而保证对待测芯片10的内阻测试的准确性。利用设备电源对待测芯片10的I/O端口进行供电，控制通过的电流值为测试电流，确保测试时的电流的准确性，进而保证测试的准确性，避免了环境电阻对测试准确性的影响。
在本实施例中，测试***还包括测试用LB板30，待测芯片10与测试机20之间通过该测试用LB板30连接，以提升连接的便捷性，进而使测试效率更高。
例如，待测芯片10的接地引脚GND通过测试用LB板30的第一连接通路(即图1中所示的J点到I点形成的通路，其上的环境电阻等效为电阻RG1和电阻RG2)与测试机20的接地端连接。
待测芯片10的接地引脚GND通过测试用LB(Load Board)板30的第二连接通路(即图1中所示的A点到E点、B点到F点的通路形成的通路，A点与E点之间的环境电阻等效为电阻RA1和电阻RA2，B点到F点之间的环境电阻等效为RB1和电阻RB2)与测试机20的设备电源连接。该第二连接通路用于使设备电源能够对待测芯片10的接地引脚GND供电，以调节其电压值。
待测芯片10的I/O端口通过测试用LB板30的第三连接通路(即图1中所示的C点到G点、D点到H点形成的通路，其中，C点到G点的环境电阻等效为电阻RC1和电阻RC2，D点到H点的环境电阻等效为电阻RD1和电阻RD2)与测试机20的设备电源连接。该第三连接通路用于使设备电源对待测芯片10的I/O端口供电，以输出测试电流。
可选地，在本实施例中，设备电源包括第一电源单元(即图1中所示的DPS1)，第一电源单元DPS1用于与待测芯片10的接地引脚GND连接，以调节接地引脚GND的电压值。
具体地，第一电源单元包括正输出端(图1中所示的DPS1的F+端口，即设备电源正向的输出端)、负输出端(图1中所示的DPS1的F-端口，即设备电源负向的输出端)、正测试端(图1中所示的的DPS1的S+端口，即设备电源正向的采样端)和负测试端(图1中所示的DPS1的S-端口，即设备电源负向的采样端)，正输出端F+和正测试端S+均与接地引脚GND连接，负输出端F-和负测试端S-均与测试机20的接地端连接。
由于第一电源单元DSP1的负输出端F-和负测试端S-均与测试机20的接地端连接，因此其电位值与测试机20的接地端的电位值相等。通常情况下，测试机20的接地端的电位值为0V。故而本实施例中，以接地端的电位值为0V进行举例说明，即第一电源单元DPS1调节接地引脚GND的电压值为0V；当然，在其他实施例中，该电位值可以是其他值。
通过第一电源单元DPS1的正输出端F+可以对待测芯片10的接地引脚GND输出，以调节其电压值到0V，从而使接地引脚GND的电压值与接地端的电压值相等，进而保证在测试过程中，这两者之间不存在压降，从而屏蔽接地引脚GND与接地端之间的环境电阻(图1中所示的电阻RG1和RG2)。
第一电源单元DPS1的正测试端S+用于准确测试接地引脚GND的电压值，从而为测试机20提供反馈数据，使其能够通过该反馈数据调节第一电源单元DPS1的正输出端F+的输出。例如，测试机还包括控制单元，控制单元与第一电源单元DPS1连接，根据正测试端S+检测的电压值调节正输出端F+的输出。
在本实施例中，设备电源包括第二电源单元DPS2，第二电源单元DPS2用于与待测芯片10的I/O端口连接，以对I/O端口输出测试电流，并测量I/O端口的电压值。
具体地，第二电源单元DPS2包括正输出端F+、负输出端F-、正测试端S+和负测试端S-，正输出端F+和正测试端S+均与I/O端口连接，负输出端F-和负测试端S-均与测试机20的接地端连接。
与第一电源单元DPS1的负输出端和负测试端类似的，第二电源单元DPS2的负输出端和负测试端也与测试机20的接地端连接。其作用与第一电源单元DPS1的负输出端和负测试端类似，在此不再赘述。
第二电源单元DPS2的正输出端F+用于对I/O端口输出测试电流。第二电源单元DPS2的正测试端S+用于测试I/O端口的电压值，由于该正测试端S+的内阻接近于无限大，进而使得该正测试端S+与I/O端口之间的环境电阻值不会影响对I/O端口的电压值的测试，从而避免了I/O端口侧的环境电阻对测试准确性的影响。
该测试机可以ATE(Automatic Test Equipment，自动化测试设备)测试机。设备电源可以是ATE测试机内部的自备电源(DPS，device power supply)。
该芯片阻抗测试***利用ATE测试机自身的DPS资源，能够精确测Rdson(内阻)或其他阻抗的方法。和以往的阻抗测试相比，本申请利用测试机自带的DPS与待测芯片10的接地引脚之间形成一组凯尔文四线，代替原本的只有一路(F+，S+)的方案，使在不添加外部资源的情况下，准确测量Rdson等阻抗。
利用设备电源中的两个电源单元的正输出端和正测试端进行测试，解决 了现有的电源单元负输出端和负测试端用来与测试机的接地端连接，所以不能抵消掉地端环境阻抗的问题。
利用该***，即便是低配ATE测试机，也可以利用自身的设备电源精准测量内阻(Rdson)或其他阻抗。解决了现有技术中的随着测试机的配置变高，测试成本也越高，如果单单因为一个导通阻抗测试需求来更换资源丰富的测试机成本会变的很高的问题。
利用测试机自身的DPS单元与待测芯片10的接地引脚GND连接，使其修正待测芯片10的接地引脚GND与测试机的接地端之间的电位差，使其电位差为0，以达到精准测量内阻(Rdson)的目的。
如图2所示，根据本申请的另一方面，提供一种待测芯片测试方法，其包括以下步骤：
步骤S102：测试机20通过设备电源调节待测芯片10的接地引脚GND的电压值，使接地引脚GND的电压值与测试机20中的接地端的电压值相等。
例如，在一种可行方式中，通过将设备电源与待测芯片10的接地引脚GND连接，使设备电源对接地引脚GND输出，以强制调节其电压值与接地端的电压值相等。
可选地，测试机20包括第一电源单元，在步骤102中，使第一电源单元与接地引脚GND连接，并通过第一电源单元对待测芯片10的接地引脚GND供电，使接地引脚GND的电压值与测试机20中的接地端的电压值相等。
步骤S104：测试机20通过设备电源对待测芯片10的I/O端口输出测试电流，并测试I/O端口处的电压值。
例如，在一种可行方式中，通过设备电源对待测芯片10的I/O端口输出10mA的电流。当然，该电流值可以是任意适当的电流值，并不限于例举的10mA。
可选地，测试机20包括第二电源单元，在步骤S104中包括：使第二电源单元与I/O端口连接，第二电源单元通过I/O端口对待测芯片10输出测试电流，并测试I/O端口处的电压值。
步骤S106：根据测试电流的电流值、I/O端口处的电压值和待测芯片10的接地引脚GND的电压值，确定待测芯片10的I/O端口与接地引脚GND之间的电阻值。
待测芯片的I/O端口与接地引脚GND之间的内阻值(记作R)等于I/O 端口的电压值减去接地引脚GND的电压值的差值，除以测试电流的电流值。
该方法中，由于通过设备电源强制调节了接地引脚GND的电压值，使接地引脚与接地端之间无压差，从而保证了接地引脚与测试机的接地端之间的环境电阻不会对内阻R的测试产生影响。利用设备电源检测I/O端口处的电压值，根据该电压值计算内阻R，确保I/O端口与测试机之间的环境电阻不会对内阻R的测试产生影响从而保证了内阻测试的准确性。
通过该方法，避免了现有测试过程中存在的环境电阻，例如，测试用LB板30上的电阻、导线阻抗(包括在线上的继电器等导通电阻)、测试探针、探针与芯片的接触阻抗等、以及测试用LB板30与测试机之间的排线或接触阻抗等。通过第二电源单元可以正确得到内阻R两端的电压和通过内阻R的电流，以此可以准确地计算出内阻R的阻抗。
该测试的具体过程为：
如图1所示，将第一电源单元DPS1的电压值强制输出(Force)0V,也就是通过第一电源单元DPS1使得图1中A点电位为0V。由于测试机20的接地端与第一电源单元DPS1的负输出端F-、负测试端S-、第二电源单元的DPS2的负输出端F-和负测试端S-连接。所以，第一电源单元DPS1使A点的电压值为0V时，其正输出端F+会使E电位点低于测试机接地端的电位，使得电流从第一电源单元DPS1的正输出端F+通路回流。此时测试机的接地端、第一电源单元DPS1的负输出端F-、第二电源单元DPS2的负输出端F-和待测芯片10的接地引脚GND在同一电位点上。
将第二电源单元DPS2强制输出(Force)10mA(记作I1)(具体根据实际情况调整)，可通过第二电源单元DPS2测量D点的电压(记作V1)。
内阻R＝V1/I1计算出内阻R的阻值。此种情况是接地引脚GND等于0V的情况。
通过本方法在测试机不具备DPS-使用的情况下，通过DPS+精准调节待测芯片10的接地引脚GND的电位点，使得测量阻抗更精准，不必更换高端测试机，电路实现简单。
下面例举一种现有技术的测量方法，以进行效果对比。
在现有技术中，直接将待测芯片10的接地引脚与测试机的接地端连接，之后对待测芯片的I/O端口输出，并进行内阻测试。在此过程中，默认接地 引脚的电压值等于接地端的电压值，即为0V。
这种情况下，在计算阻抗R时为：设备电源DPS强制输出(Force)10mA(记作I2),可测量D点的电位(记作V2),则R值实际上为V2/I2，由于环境电阻的存在计算出的R＝R0(待测芯片的实际内阻)+RG1+RG2。计算结果R与实际内阻R0间存在一定误差。
假设：实际内阻R0＝5，RG＝6，RA＝7，RB＝8，RC＝9，RD＝10，单位(欧姆)。RG为RG1+RG2，RA、RB、RC和RD同理。
现有技术方案中：DPS强制输出(Force)10mA,则测试台的接地端电位点为0V，J点电位为RG*10mA＝60mV，测量D点电压为110mV,计算内阻R为：110mV除以10mA＝11欧姆。
本申请的方案：第一电源单元DPS1强制输出(Force)0V,第二电源单元DPS2强制输出(Force)10mA,则测试机的接地端电位点为0V，待测芯片10的接地引脚GND也为0V，E点电位为-70mV。测量D点电压为50mV，计算内阻R为50mV除以10mA＝5欧姆。由此可见，本申请的方案测量更为准确。
最后应说明的是：以上实施例仅用以说明本申请实施例的技术方案，而非对其限制；尽管参照前述实施例对本申请实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (10)

  1. 一种芯片阻抗测试***，包括：测试机，所述测试机包括设备电源，所述设备电源与待测芯片的接地引脚以及I/O端口连接，
    所述测试机通过所述设备电源调节所述接地引脚的电压值，使所述接地引脚的电压值与所述测试机的接地端的电压值相同；
    所述测试机通过所述设备电源对所述I/O端口输出测试电流，并测试所述I/O端口处的电压值，根据所述I/O端口处的电压值、所述接地引脚处的电压值和所述测试电流的电流值确定所述I/O端口与所述接地引脚之间的电阻值。
  2. 根据权利要求1所述的芯片开短路测试装置，其中，所述测试***还包括测试用LB板，所述待测芯片的接地引脚通过所述测试用LB板的第一连接通路与所述测试机的接地端连接。
  3. 根据权利要求1或2所述的芯片阻抗测试***，其特征在于，所述接地引脚和所述测试机的接地端的电压值为0V。
  4. 根据权利要求1所述的芯片阻抗测试***，其特征在于，所述设备电源包括第一电源单元，所述第一电源单元用于与所述待测芯片的接地引脚连接。
  5. 根据权利要求4所述的芯片阻抗测试***，其特征在于，所述第一电源单元包括正输出端、负输出端、正测试端和负测试端，所述正输出端和正测试端均与所述接地引脚连接，所述负输出端和负测试端均与所述测试机的接地端连接。
  6. 根据权利要求1-5中任一项所述的芯片阻抗测试***，其特征在于，所述设备电源包括第二电源单元，所述第二电源单元用于与所述待测芯片的I/O端口连接。
  7. 根据权利要求6所述的芯片阻抗测试***，其特征在于，所述第二电源单元包括正输出端、负输出端、正测试端和负测试端，所述正输出端和正测试端均与所述I/O端口连接，所述负输出端和负测试端均与所述测试机的接地端连接。
  8. 一种待测芯片测试方法，其特征在于，
    测试机通过设备电源调节所述待测芯片的接地引脚的电压值，使所述 接地引脚的电压值与所述测试机中的接地端的电压值相等；
    测试机通过设备电源对所述待测芯片的I/O端口输出测试电流，并测试所述I/O端口处的电压值；
    测试机根据所述测试电流的电流值、所述I/O端口处的电压值和所述待测芯片的接地引脚的电压值，确定所述待测芯片的所述I/O端口与所述接地引脚之间的电阻值。
  9. 根据权利要求8所述的方法，其特征在于，所述测试机包括第一电源单元，所述测试机通过设备电源调节所述待测芯片的接地引脚的电压值，使所述接地引脚的电压值与所述测试机中的接地端的电压值相等，包括：
    通过所述第一电源单元对所述待测芯片的接地引脚供电，使所述接地引脚的电压值与所述测试机中的接地端的电压值相等。
  10. 根据权利要求8所述的方法，其特征在于，所述测试机包括第二电源单元，所述测试机通过设备电源对所述待测芯片的I/O端口输出测试电流，并测试所述I/O端口处的电压值，包括：
    测试机的第二电源单元通过所述I/O端口对所述待测芯片输出测试电流，并测试所述I/O端口处的电压值。
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