WO2019242369A1 - 像素电路及其驱动方法、阵列基板、显示面板 - Google Patents

像素电路及其驱动方法、阵列基板、显示面板 Download PDF

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Publication number
WO2019242369A1
WO2019242369A1 PCT/CN2019/080113 CN2019080113W WO2019242369A1 WO 2019242369 A1 WO2019242369 A1 WO 2019242369A1 CN 2019080113 W CN2019080113 W CN 2019080113W WO 2019242369 A1 WO2019242369 A1 WO 2019242369A1
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signal
circuit
voltage
control signal
node
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PCT/CN2019/080113
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English (en)
French (fr)
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殷新社
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京东方科技集团股份有限公司
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Priority to US16/611,290 priority Critical patent/US11282452B2/en
Publication of WO2019242369A1 publication Critical patent/WO2019242369A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3618—Control of matrices with row and column drivers with automatic refresh of the display panel using sense/write circuits
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G09G2300/0866—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes by means of changes in the pixel supply voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/029—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • G09G2320/0295—Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel by monitoring each display pixel

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a driving method thereof, an array substrate, and a display panel.
  • OLED Organic Light Emitting Diode
  • the current mainstream development direction of OLEDs is to control the magnitude of the current between the source and the drain of the driving transistor by changing the gate voltage of the driving transistor that directly drives the OLED to emit light to achieve a change in light emission brightness.
  • the threshold voltages of the driving transistors in different positions may be different due to process variations. And with long-term use and the use environment changes, the threshold voltage of the driving transistor will drift.
  • the different positions of the pixels may also cause the IR drop of the power supply to be different, thereby affecting the current driving the OLED.
  • Embodiments of the present disclosure provide a pixel circuit and a driving method thereof, an array substrate, and a display panel.
  • a pixel circuit may include a data writing circuit, an initialization circuit, a sensing circuit, a first capacitor, a second capacitor, a driving transistor, and a data signal providing circuit.
  • the data writing circuit is configured to provide a data signal from a data line to a first node according to a first control signal from a first control signal terminal.
  • the initialization circuit is configured to provide an initialization signal to the sensing line according to a second control signal from the second control signal terminal.
  • the sensing circuit is configured to couple the second node to the sensing line according to the first control signal, so that the voltage at the second node is equal to the voltage on the sensing line.
  • the first capacitor is configured to store a voltage difference between the first node and the second node.
  • the second capacitor is configured to store a voltage on the sensing line.
  • the control electrode of the driving transistor is coupled to the first node, the first electrode is coupled to the first voltage signal terminal, and the second electrode is coupled to the second node, and is configured to provide a driving current to the light emitting device.
  • the data signal providing circuit is configured to read the voltage on the sensing line according to the third control signal from the third control signal terminal, determine the threshold voltage of the driving transistor according to the read voltage, and modify the original signal from the data signal terminal according to the threshold voltage. Data signal to provide to the data line.
  • the data signal providing circuit may include a reading circuit, a determining circuit, and a providing circuit.
  • the reading circuit is configured to read the voltage on the sensing line according to the third control signal.
  • the determination circuit is configured to determine a threshold voltage of the driving transistor based on the read voltage.
  • the providing circuit is configured to modify the original data signal according to a threshold voltage to provide to the data line.
  • the data signal providing circuit may further include an analog-to-digital conversion circuit and a storage circuit.
  • the analog-to-digital conversion circuit is configured to convert a threshold voltage into a digital signal form.
  • the memory circuit is configured to store a threshold voltage in the form of a digital signal
  • the data writing circuit may include a first transistor.
  • the control electrode of the first transistor is coupled to the first control signal terminal, the first electrode is coupled to the data line, and the second electrode is coupled to the first node.
  • the initialization circuit may include a second transistor.
  • the control electrode of the second transistor is coupled to the second control signal terminal, the first electrode is coupled to the initialization signal, and the second electrode is coupled to the sensing line.
  • the sensing circuit may include a third transistor.
  • the control electrode of the third transistor is coupled to the first control signal, the first electrode is coupled to the sensing line, and the second electrode is coupled to the second node.
  • the pixel circuit may further include a first reference circuit.
  • the first reference circuit is configured to provide a first reference signal to the data line based on a fourth control signal from a fourth control signal terminal.
  • the first reference circuit may include a fourth transistor.
  • the control electrode of the fourth transistor is coupled to the fourth control signal terminal, the first electrode is coupled to the first reference signal, and the second electrode is coupled to the data line.
  • the pixel circuit may further include a second reference circuit.
  • the second reference circuit is configured to provide a second reference signal to the sensing line according to a fifth control signal from the fifth control signal terminal.
  • the second reference circuit may include a fifth transistor.
  • the control electrode of the fifth transistor is coupled to the fifth control signal terminal, the first electrode is coupled to the second reference signal, and the second electrode is coupled to the sensing line.
  • a method for driving a pixel circuit of the first aspect of the present disclosure includes a non-display phase and a display phase.
  • the non-display stage under the control of the first control signal and the second control signal, the data signal from the data line is provided to the first node, the initialization signal is provided to the sensing line, and the voltage and The voltage of the second node is equal; under the control of the first control signal, the data signal is provided to the first node, and under the control of the voltage of the first node, the driving current of the driving transistor charges the first capacitor and the second capacitor; Under the control of the third control signal, the voltage on the sensing line is read, and the threshold voltage of the driving transistor is determined according to the read voltage.
  • the original data signal from the data signal terminal is modified according to the threshold voltage to provide to the data line.
  • the driving transistor provides the driving current
  • the method further includes: providing a first reference signal to the data line under the control of the fourth control signal in a non-display phase.
  • the method further includes: providing a second reference signal to the sensing line under the control of the fifth control signal in the display phase.
  • the scanning frequency in the non-display phase is lower than the scanning frequency in the display phase.
  • an array substrate may include a plurality of pixel circuits according to the first aspect of the present disclosure.
  • the driving transistor, the data writing circuit, the sensing circuit, and the first capacitor of each pixel circuit are located in an effective display area of the array substrate.
  • the second capacitor, the initialization circuit, and the data signal supply circuit of each pixel circuit are located in a peripheral region of the array substrate.
  • a display panel includes an array substrate of a third aspect of the present disclosure.
  • FIG. 1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic block diagram of a pixel circuit according to another embodiment of the present disclosure
  • FIG. 3 shows an exemplary circuit diagram of the pixel circuit shown in FIG. 1;
  • FIG. 4 shows an exemplary circuit diagram of the pixel circuit shown in FIG. 2;
  • FIG. 5 shows an exemplary schematic diagram of a display system in a non-display phase and a display phase according to an embodiment of the present disclosure
  • FIG. 6a shows a timing diagram of signals in the pixel circuit shown in FIG. 3 in a non-display phase
  • FIG. 6b shows a timing diagram of signals in the pixel circuit shown in FIG. 3 during a display phase
  • FIG. 7a shows a timing diagram of signals in the pixel circuit shown in FIG. 4 in a non-display phase
  • FIG. 7b shows a timing diagram of signals in the pixel circuit shown in FIG. 4 during a display phase
  • FIG. 8 illustrates a flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • FIG. 10 illustrates an exemplary timing diagram of signals in an array substrate according to an embodiment of the present disclosure.
  • connection should be understood in a broad sense unless otherwise specified and limited.
  • it may be a fixed connection or a connection.
  • Disassembly connection, or integral connection it can be mechanical or electrical connection; it can be directly connected or indirectly connected through an intermediate medium.
  • FIG. 1 shows a schematic block diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 100 may include a data writing circuit 110, an initialization circuit 120, a sensing circuit 130, a first capacitor 140, a second capacitor 150, a data signal providing circuit 160, and a driving transistor TD.
  • the data writing circuit 110 may be coupled to the data line DL, the first control signal terminal S1 and the first node A. As shown in FIG. 1, the data writing circuit 110 may be coupled to a control electrode (eg, a gate) of the driving transistor TD via a first node A. The data writing circuit 110 may provide the data signal V D from the data line DL to the first node A according to the first control signal G from the first control signal terminal S1 to control the voltage V A of the first node A.
  • a control electrode eg, a gate
  • the initialization circuit 120 may be coupled to the sensing line SL, the second control signal terminal S2 and the initialization signal Ini. Initializing circuit 120 according to a second control signal R from the end of the second control signal S2, the initialization signal Ini provided to the sensing line SL, the voltage V SL to initialize the control voltage V ini sensing line SL.
  • the sensing circuit 130 may be coupled to the sensing line SL, the first control signal terminal S1 and the second node B. As shown in FIG. 1, the sensing circuit 130 may be coupled to a second electrode (for example, a source) of the driving transistor TD via a second node B.
  • the sensing circuit 130 may be configured in accordance with a first control signal G, the second node B is coupled to the sense line SL, SL V so that the voltage V B and the voltage on the sense line SL is equal to the second node B.
  • the first capacitor 140 may be coupled between the first node A and the second node B.
  • the first capacitor 140 can store the amount of charge between the first node A and the second node B, that is, the voltage difference between the first node A and the second node B.
  • One end of the second capacitor 150 can be coupled to the sensing line SL, and the other end is grounded.
  • the second capacitor 150 can store the amount of charge on the sensing line SL, that is, the voltage V SL on the sensing line SL .
  • the control electrode of the driving transistor TD is coupled to the first node A, the first electrode is coupled to the first voltage signal terminal V1, and the second electrode is coupled to the second node B.
  • the driving transistor TD voltage V A and the voltage V B of the second node B to node A, to provide drive current to the light emitting device.
  • the driving transistor TD is an N-type transistor.
  • the control electrode (ie, the first node A) of the driving transistor TD is the gate
  • the first electrode is the drain
  • the second electrode (the second node B) is the source.
  • TD drive transistor gate-source voltage V gs is the voltage between the voltage V B V A voltage of the second node B and node A difference.
  • the driving transistor TD When the gate-source voltage V gs (that is, V A -V B ) of the driving transistor TD is above its threshold voltage V th , the driving transistor TD is turned on. When the gate-source voltage V gs (ie, V A -V B ) of the driving transistor TD is lower than its threshold voltage V th , the driving transistor TD is turned off. In the embodiment of the present disclosure, in the non-display stage, when the driving transistor TD is turned on, the current in the driving transistor TD charges the first capacitor C1 and the second capacitor C2, so that the voltage V B of the second node B rises. .
  • the data signal providing circuit 160 may be coupled to the sensing line SL, the data line DL, the third control signal terminal S3 and the data signal terminal DT.
  • the data signal providing circuit 160 can read the voltage V SL on the sensing line SL under the control of the third control signal P from the third control signal terminal S3. According to the data signal V D on the data line DL and the read The voltage V SL is used to calculate the threshold voltage V th of the driving transistor TD. Then, the data signal providing circuit 160 may modify the original data signal V D0 from the data signal terminal DT according to the threshold voltage V th of the driving transistor TD, and provide the corrected data signal V D1 to the data line DL as the next A data signal on the data line DL of the frame.
  • the data signal providing circuit 160 may be disconnected from the data line DL (for example, in a high-impedance state) during the non-display stage to avoid affecting the data signal on the data line DL.
  • the data signal providing circuit 160 may be disconnected from the sensing line SL (for example, in a high-impedance state) during the display stage to avoid affecting the voltage on the sensing line SL.
  • the voltage read by the data signal providing circuit 160 from the sensing line SL is V A -V th .
  • the voltage V A of the first node A is under the control of the data writing circuit 110.
  • the driving transistor DT may provide a driving current according to the modified data signal V D1 from the data line DL.
  • the pixel circuit 100 may further include a light emitting device D (shown by a dotted frame).
  • the anode of the light-emitting device D is coupled to the second pole of the driving transistor TD, and the cathode is coupled to the second voltage signal terminal V2.
  • the light emitting device D may emit light according to a driving current provided by the driving transistor TD.
  • the light emitting device D is, for example, an OLED or the like.
  • the pixel circuit 100 may determine a threshold voltage of the driving transistor TD and compensate the original data signal V D0 provided by the data signal terminal DT.
  • the driving current provided by the driving transistor TD is related to the difference between the gate-source voltage V gs and the threshold voltage V th (V gs -V th ).
  • the driving current provided by the driving transistor TD is only related to the original data signal V D0 provided by the data signal terminal DT and the voltage V SL on the sensing line SL, and is not subject to threshold voltage deviation or IR.
  • the influence of the power supply voltage caused by the drop causes the brightness of the pixels to be inconsistent.
  • an original data signal at a data signal end is compensated by determining an electrical characteristic (e.g., a threshold voltage) of a driving transistor in a pixel circuit, and according to the determined electrical characteristic when displaying. Therefore, the driving current provided by the driving transistor has nothing to do with its electrical characteristics, thereby eliminating the difference in brightness caused by the difference in characteristics of the driving transistor between different pixel circuits.
  • an electrical characteristic e.g., a threshold voltage
  • FIG. 2 shows a schematic block diagram of a pixel circuit according to another embodiment of the present disclosure.
  • the pixel circuit 200 may include a data writing circuit 110, an initialization circuit 120, a sensing circuit 130, a first capacitor 140, a second capacitor 150, a data signal providing circuit 160, a driving transistor TD, and a first reference circuit. 270 and second reference circuit 280.
  • the first reference circuit 270 may be coupled to the fourth control signal terminal S4, the data line DL, and the first reference signal REF1.
  • the first reference circuit 270 may provide the first reference signal REF1 to the data line DL according to the fourth control signal S from the fourth control signal terminal S4 as the data signal V D on the data line DL.
  • the second reference circuit 280 may be coupled to the fifth control signal terminal S5, the sensing line SL, and the second reference signal REF2.
  • the second reference circuit 280 may provide the second reference signal REF2 to the sensing line SL according to the fifth control signal EM from the fifth control signal terminal S5 to control the voltage V SL on the sensing line SL .
  • the first reference circuit 270 and the second reference circuit 280 may be provided separately from other parts of the pixel circuit 200.
  • the first reference circuit 270 and the second reference circuit 280 may be provided in separate driver circuits.
  • the driver circuit may include a processor and a memory, and the computer program instructions are stored in the memory. When the computer program instructions are executed by the processor, The first reference signal REF1 is provided to the data line DL according to the fourth control signal S from the fourth control signal terminal S4, and the second reference signal is provided to the sensing line SL according to the fifth control signal EM from the fifth control signal terminal S5 REF2.
  • the pixel circuit according to the embodiment of the present disclosure may provide a stable voltage to the data line DL and the sensing line SL at a specific time, and a driving method of the pixel circuit will be described in detail below.
  • the pixel circuit 200 in FIG. 2 has the same structure as the pixel circuit 100 in FIG. 1, and will not be described in detail.
  • first reference signal REF1 provided by the first reference circuit 270 may be provided to the first node A through the data writing circuit 110 to control the voltage V A of the first node A.
  • the second reference signal REF2 provided by the second reference circuit 280 may be provided to the second node B through the sensing circuit 130 to control the voltage V B of the second node B.
  • FIG. 3 illustrates an exemplary circuit diagram of a pixel circuit according to an embodiment of the present disclosure
  • the pixel circuit 300 is, for example, the pixel circuit 100 shown in FIG. 1.
  • the transistor used may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • a gate of a transistor is referred to as a gate. Because the source and drain of a transistor are symmetrical, no distinction is made between source and drain, that is, the source of a transistor can be the first (or second) and the drain can be the second (or first) One pole).
  • NMOS N-type field effect transistor
  • the data writing circuit 110 may include a first transistor T1.
  • the control electrode of the first transistor T1 is coupled to the first control signal terminal S1, the first electrode is coupled to the data line DL, and the second electrode is coupled to the first node A.
  • the first transistor T1 may supply the data signal V D from the data line DL to the first node A under the control of the first control signal G from the first control signal terminal S1.
  • the initialization circuit 120 may include a second transistor T2.
  • the control electrode of the second transistor T2 is coupled to the second control signal terminal S2, the first electrode is coupled to the initialization signal Ini, and the second electrode is coupled to the sensing line SL.
  • the second transistor T2 can provide the initialization signal Ini to the sensing line SL under the control of the second control signal R from the second control signal terminal S2 as the initialization voltage V SL of the sensing line SL .
  • the sensing circuit 130 may include a third transistor T3.
  • the control electrode of the third transistor T3 is coupled to the first control signal terminal S1, the first electrode is coupled to the sensing line SL, and the second electrode is coupled to the second node B.
  • the third transistor T3 may be under control of a first control signal G, the second node B is coupled to the sense line SL, SL V so that the voltage V B and the voltage on the sense line SL is equal to the second node B.
  • the voltage V SL ie, the initialization signal Ini
  • the voltage V B of the second node B is transmitted to the sensing line SL as the voltage V SL on the sensing line SL .
  • the initialization phase and the establishment phase will be described in detail later.
  • the first capacitor 140 may include a capacitor C1
  • the second capacitor 150 may include a capacitor C2.
  • the structure of the driving transistor TD has been described above, and will not be described in detail here.
  • the data signal providing circuit 160 may include a reading circuit M1, a determining circuit M2, and a providing circuit M3.
  • the reading circuit M1 can read the voltage V SL on the sensing line SL according to the third control signal P from the third control signal terminal S3, and provide the read voltage V SL to the first input of the determining circuit M2. end.
  • the read circuit M1 is, for example, a fifth transistor, and its control electrode is coupled to the third control signal terminal S3, the first electrode is coupled to the sensing line SL, and the second electrode is coupled to the first of the determination circuit M2. Input.
  • the determination circuit M2 may determine the threshold voltage V th of the driving transistor TD according to the data signal D on the data line DL and the read voltage V SL , and provide the determined threshold voltage V th to the supply circuit M 3.
  • the determining circuit M2 may include a subtractor. A first input terminal thereof is coupled to the reading circuit M1 to receive the read voltage V SL , a second input terminal is coupled to the data line DL, and an output terminal is coupled to the providing circuit. M3.
  • the threshold voltage V th can be determined by calculating a voltage difference between the data signal V D and the read voltage V SL .
  • the data signal providing circuit 160 may further include an analog-to-digital conversion circuit (not shown), such as an analog-to-digital converter ADC, which converts the threshold voltage V th determined by the determination circuit M2 into a digital signal.
  • the data signal providing circuit 160 may further include a memory circuit (not shown).
  • the storage circuit may store a threshold voltage V th in the form of a digital signal.
  • the storage circuit may be any memory having a storage function, and a threshold voltage V th in the form of a digital signal is stored on its address.
  • the providing circuit M3 may modify the data signal on the data line DL according to the determined (or stored) threshold voltage V th and the original data signal V D0 from the data signal terminal DT, and provide the modified data line to the data line DL.
  • Data signal V D1 may be implemented by an adder.
  • the first input terminal is coupled to the data signal terminal DT, and the second input terminal is coupled to the determination circuit M2 (optionally, a storage circuit) to receive the threshold voltage V th and output.
  • the terminal is coupled to the data line DL.
  • the adder sums the threshold voltage V th and the original data signal V D0 to obtain a modified data signal V D1 and outputs it to the data line DL.
  • the data signal providing circuit 160 may also be implemented by a combination of software and hardware such as a processor.
  • the data signal providing circuit 160 may include a memory and a processor, and the computer program instructions stored in the memory cause the data signal providing circuit 160 to execute the reading of the sensing line according to the third control signal P when executed by the processor.
  • Voltage V SL on the basis of the data signal D and the read voltage V SL to determine the threshold voltage V th of the driving transistor (which can be converted into a digital signal and stored in the memory), and according to the threshold voltage V th and the data
  • the original data signal V D0 of the signal terminal DT provides a modified data signal V D1 to the data line DL.
  • FIG. 4 illustrates an exemplary circuit diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 400 is, for example, the pixel circuit 200 shown in FIG. 2.
  • the transistor used may be an N-type transistor or a P-type transistor.
  • the transistor may be an N-type or P-type field effect transistor (MOSFET), or an N-type or P-type bipolar transistor (BJT).
  • MOSFET N-type or P-type field effect transistor
  • BJT N-type or P-type bipolar transistor
  • a gate of a transistor is referred to as a gate. Because the source and drain of a transistor are symmetrical, no distinction is made between source and drain, that is, the source of a transistor can be the first (or second) and the drain can be the second (or first) One pole).
  • NMOS N-type field effect transistor
  • the pixel circuit 400 may further include a first reference circuit 270 and a second reference circuit 280.
  • the first reference circuit 270 may include a fourth transistor T4.
  • the control electrode of the fourth transistor T4 is coupled to the fourth control signal terminal S4.
  • the first electrode is coupled to the first reference signal REF1.
  • the second electrode is coupled to the data line DL.
  • the first reference signal REF1 is provided to the data line DL under the control of the fourth control signal S from the fourth control signal terminal S4.
  • the second reference circuit 280 may include a fifth transistor T5, a control electrode of the fifth transistor T5 is coupled to the fifth control signal terminal S5, a first electrode is coupled to the second reference signal REF2, and a second electrode is coupled to the sensing line SL, and The second reference signal REF2 may be provided to the sensing line SL under the control of the fifth control signal EM from the fifth control signal terminal S5.
  • reading the characteristics of the driving transistor of the pixel circuit that is, determining the threshold voltage
  • displaying the normal screen are divided into two different phases, namely a non-display phase and a display phase.
  • the order of the non-display phase and the display phase is not specifically limited.
  • the characteristic reading can be performed before the first few frames to several hundred frames of the normal display of the display device, or after the display is completed to the non-display phase of shutdown, or performed before and after the display phase.
  • FIG. 5 illustrates an exemplary timing diagram of a non-display phase and a display phase according to an embodiment of the present disclosure.
  • the power-off is performed, and three phases including a non-display phase, a display phase, and a non-display phase are passed.
  • the non-display phase from when the power is turned on until the display device displays a normal screen may include a display device system setting phase and an electrical characteristic reading (and saving) phase.
  • the display device system setting stage sets the power supply voltage to a set value, and sets the control signal and timing of the display system.
  • the value of the threshold voltage Vth of the driving transistor in the pixel is read line by line for each pixel, and the detected value is stored in the control device.
  • the data signal provided by the data signal end is compensated according to the determined threshold voltage, and the display system is sequentially displayed in accordance with the normal timing, so as to compensate the pixel voltage.
  • FIGS. 6 a and 6 b respectively show timing charts of signals in a pixel circuit according to an embodiment of the present disclosure in a non-display phase and a display phase.
  • the pixel circuit is, for example, the pixel circuit 300 shown in FIG. 3.
  • the first voltage signal Vdd is a high-level signal
  • the second voltage signal Vss is a low-level signal.
  • the non-display phase may include an initialization phase P1, a setup phase P2, and a read phase P3 accordingly.
  • the first control signal G and the second control signal R are both at a high level, so that the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on.
  • the data signal V D is provided to the data line DL, for example, it can be directly provided to the data line DL through the data signal terminal DT (for example, other reference signals can also be provided).
  • the data signal V D on the data line DL is provided to the first node A through the first transistor T1 so that the voltage (V A ) of the first node is V D.
  • the initialization signal Ini (for example, a low-level signal, and the voltage value may be represented as V ini ) is provided to the sensing line SL via the second transistor T2, and further provided to the second node B via the third transistor T3. Therefore, during the initialization phase T1, the voltage V B of the second node B is V ini . In this manner, the voltages of the gate (ie, the first node A) and the source (ie, the second node B) of the driving transistor TD are initialized by the data signal V D and the initialization signal Ini, respectively.
  • the first capacitor C1 can store the voltage difference between the first node A and the second node B, that is, V D -V ini , that is, the gate-source voltage V gs of the driving transistor TD.
  • the first control signal G is kept at a high level, and the second control signal R is at a low level.
  • the first transistor T1 and the third transistor T3 remain on, and the second transistor T2 is turned off.
  • the voltage V A of the first node A is kept at V D.
  • the current in the driving transistor TD charges the first capacitor C1 and the second capacitor C2, so that the voltage V B of the second node B and the voltage of the sensing line SL gradually increase. Accordingly, the gate-source voltage V gs (ie, V A -V B ) of the driving transistor is reduced, and the current in the driving transistor TD is correspondingly reduced.
  • the driving transistor TD is turned off.
  • the voltage on the sense line SL can be approximately regarded as V D -V th .
  • the longer the period of the establishment phase T2 the closer the voltage on the sensing line SL approaches V D -V th .
  • the first control signal G is maintained at a high level, the first transistor T1 and the third transistor T3 are kept on, and the voltage V A of the first node A is maintained at V D.
  • the voltage on the sensing line is approximately V D -V th .
  • the third control signal P is at a high level, and the voltage (V D -V th ) on the sensing line SL is read by the reading circuit M1.
  • the analog-to-digital conversion circuit may convert the determined threshold voltage V th into a digital signal, and the storage circuit may store the threshold voltage V th .
  • the data signal providing circuit 160 may be disconnected from the data line DL in the non-display stage.
  • the second control signal R is kept at a high level, and the second transistor T2 is kept on.
  • the first transistor T1 and the third transistor T3 are all turned on.
  • the initialization signal Ini is provided to the sensing line SL through the second transistor T2 (for example, other reference signals may also be provided), and then the initialization signal Ini is transmitted to the second node B through the third transistor T3, so that the voltage V of the second node B is B is an initialization voltage V ini of the initialization signal Ini.
  • the providing circuit M3 receives the original data signal V D0 from the data signal terminal DT and the threshold voltage V th of the determined (and stored) driving transistor TD, and provides a modified data signal V D1 to the data line DL.
  • the current provided by the driving transistor TD is expressed as follows:
  • ⁇ , Cox, W, and L are related to the material and size of the driving transistor. Therefore, the current provided by the driving transistor TD is only related to the original data signal V D0 and the initialization signal Ini provided by the data signal terminal DT.
  • the light emitting device D may emit light according to a current provided by the driving transistor TD.
  • the data signal providing circuit 160 may be disconnected from the sensing line SL in the display stage.
  • the pixel circuit according to the embodiment of the present disclosure can be prevented from being affected by the threshold voltage and the power supply voltage of the driving transistor.
  • the first control signal is, for example, a line scan signal, so the time of one line is related to the frame rate of the signal. Therefore, the scanning frequency in the non-display phase can be set lower than the scanning frequency in the display phase. For example, the scanning frequency of the display phase can be set to 60 Hz, and the scanning frequency of the non-display phase can be set to 10 Hz, or even 1 Hz.
  • the pixel circuit is, for example, the pixel circuit 400 shown in FIG. 4.
  • the first voltage signal Vdd is a high-level signal
  • the second voltage signal Vss is a low-level signal
  • the initialization signal Vini is a low-level signal.
  • the non-display phase may also include an initialization phase P1, a setup phase P2, and a read phase P3.
  • a high-level fourth control signal S is provided, and a first reference signal REF1 is provided to the data line DL through the fourth transistor T4. Similar to the timing of the signal shown in FIG. 6a, the first reference signal REF1 on the data line DL is provided to the first node A through the first transistor T1, so that the voltage V A of the first node A is equal to that of the first reference signal. Voltage V ref1 .
  • An initialization signal Ini is provided to the second node B through the second transistor T2 and the third transistor T3, so that the voltage V B of the second node B is V ini
  • the voltage V A of the first node A is maintained at V ref1 , and the voltage V B of the second node B and the voltage V SL on the sensing line SL gradually increase.
  • the timing of the signals shown in FIG. 6a is similar, and will not be described in detail here.
  • the voltage V SL on the sensing line SL is read by the reading circuit M1, that is, V ref1 -V th .
  • the determination circuit M2 determines a threshold voltage V th based on the first reference signal (V ref1 ) and the read voltage (V ref1 -V th ). Optionally, it is converted into a digital signal and stored in a memory circuit.
  • a high-level fifth control signal EM is provided.
  • the fifth transistor T5 is turned on and provides a second reference signal REF2 to the sensing line SL, the voltage of which is represented by V ref2 .
  • the second control signal R and the fourth control signal S remain at a low level.
  • the driving current in the pixel circuit 400 is only related to the original data signal and the second reference signal.
  • the light emitting device emits light according to the driving current.
  • FIG. 8 shows a schematic flowchart of a method for driving a pixel circuit according to an embodiment of the present disclosure.
  • step S810 under the control of the first control signal and the second control signal, the data signal from the data line is provided to the first node, the initialization signal is provided to the sensing line, and the second The node is coupled to the sensing line so that the voltage on the sensing line is equal to the voltage of the second node.
  • step S820 the data signal is provided to the first node under the control of the first control signal, and the driving current of the driving transistor is coupled between the first node and the second node under the control of the voltage of the first node.
  • the first capacitor and the second capacitor coupled to the sensing line are charged.
  • step S830 under the control of the third control signal, the voltage on the sensing line is read, and the threshold voltage of the driving transistor is determined according to the data signal and the read voltage.
  • the determined threshold voltage can also be converted into a digital signal and stored.
  • steps S810, S820, and S830 may be performed in a non-display stage.
  • the first reference signal may be provided to the data line under the control of the fourth control signal.
  • step S840 the original data signal from the data signal terminal is modified to be provided to the data line according to the threshold voltage, and the data signal from the data line is provided to the first node under the control of the first control signal.
  • the light emitting device provides a driving current.
  • step S840 may be performed in a display stage.
  • a second reference signal may also be provided to the sensing line under the control of the fifth control signal.
  • the scanning frequency in the non-display phase is lower than the scanning frequency in the display phase.
  • non-display phase (S810, S820, S830) may be performed before and / or after the display phase (S840).
  • FIG. 9 shows a schematic diagram of an array substrate according to an embodiment of the present disclosure.
  • the array substrate 900 may include a plurality of pixel circuits according to an embodiment of the present disclosure, and only one pixel circuit 910 is schematically illustrated in FIG. 9, such as the pixel circuit 100 or the pixel circuit 200.
  • the driving transistor TD, the data writing circuit 110, the sensing circuit 130, and the first capacitor 140 of each pixel circuit are disposed in the effective display area AA of the array substrate.
  • the second capacitor 150, The initialization circuit 120 and the data signal supply circuit 160 are provided in a peripheral area of the array substrate.
  • the first reference circuit 270 and the second reference circuit 280 may be provided in a peripheral region of the array substrate.
  • the data signal providing circuit 160 may also be provided on a backplane circuit other than the array substrate and connected to other parts of the pixel circuit through a corresponding interface.
  • a plurality of pixel circuit portions within the effective display area AA may be arranged in a matrix shape.
  • the array substrate 900 may further include a cascaded shift register unit (GOA), and the shift register unit provides a first control signal to the pixel circuits in the same row.
  • the pixel circuits in the same column are coupled to the same data line DL and the same scan line SL.
  • GOA cascaded shift register unit
  • the pixel circuit since the pixel circuit has only three transistors and one capacitor in the portion of the effective display area, it can be wired at a higher resolution.
  • FIG. 10 An exemplary timing diagram of signals in the array substrate according to an embodiment of the present disclosure is shown in FIG. 10.
  • a first control signal G of a high level is provided to the pixel circuits line by line, for example, the first control signal G1 of the pixel circuits of the first line and the first control signal G2 of the pixel circuits of the second line.
  • the timing of the signal of the pixel circuit in the non-display phase and the display phase has been described above, and will not be repeated here.
  • embodiments of the present disclosure also provide a display panel including the above array substrate, and a display device including the display panel.
  • the display device may be, for example, a display screen, a mobile phone, a tablet computer, a camera, a wearable device, and the like.

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Abstract

本公开的实施例提供了像素电路及其驱动方法、阵列基板和显示面板。像素电路包括数据写入电路、初始化电路、感测电路、第一电容、第二电容、驱动晶体管和数据信号提供电路。数据写入电路根据第一控制信号将来自数据线的数据信号提供至第一节点。初始化电路根据第二控制信号将初始化信号提供至感测线。感测电路根据第一控制信号将第二节点耦接到感测线，使得第二节点的电压和感测线上的电压相等。第一电容存储第一节点和第二节点之间的电压差。第二电容存储感测线上的电压。驱动晶体管提供驱动电流。数据信号提供电路根据第三控制信号读取感测线上的电压，根据所读取的电压确定驱动晶体管的阈值电压，以及根据阈值电压修正来自数据信号端的原始数据信号，以提供至数据线。

Description

像素电路及其驱动方法、阵列基板、显示面板
相关申请的交叉引用
本申请要求于2018年6月19日递交的申请号为201810627050.0的中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，具体地，涉及像素电路及其驱动方法、阵列基板和显示面板。
背景技术
随着显示技术的进步，相对于传统的液晶显示(Liquid Crystal Display，LCD)装置，新一代的有机发光二极管(Organic Light Emitting Diode，OLED)显示装置具有更低的制造成本，更快的反应速度，更高的对比度，更广的视角，更大的工作温度范围，不需要背光单元，色彩鲜艳及轻薄等优点，因此OLED显示技术成为当前发展最快的显示技术。
当前OLED的主流发展方向是通过改变直接驱动OLED发光的驱动晶体管的栅极电压，来控制驱动晶体管的源极与漏极之间电流的大小以实现发光亮度的变化。然而在制作驱动晶体管的过程中，由于工艺偏差会导致不同位置的驱动晶体管的阈值电压存在差异。并且随着长时间使用及使用环境改变，驱动晶体管的阈值电压会发生漂移。另一方面，在显示器件中，各像素所处的位置不同也可能导致电源的压降(IR Drop)不同，从而对驱动OLED的电流产生影响。
发明内容
本公开的实施例提供了像素电路及其驱动方法、阵列基板和显示面板。
根据本公开的第一方面，提供了一种像素电路。像素电路可包括数据 写入电路、初始化电路、感测电路、第一电容、第二电容、驱动晶体管和数据信号提供电路。数据写入电路被配置为根据来自第一控制信号端的第一控制信号，将来自数据线的数据信号提供至第一节点。初始化电路被配置为根据来自第二控制信号端的第二控制信号，将初始化信号提供至感测线。感测电路被配置为根据第一控制信号，将第二节点耦接到感测线，使得第二节点的电压和感测线上的电压相等。第一电容被配置为存储第一节点和第二节点之间的电压差。第二电容被配置为存储感测线上的电压。驱动晶体管的控制极耦接第一节点，第一极耦接第一电压信号端，第二极耦接第二节点，并被配置为向发光器件提供驱动电流。数据信号提供电路被配置为根据来自第三控制信号端的第三控制信号读取感测线上的电压，根据所读取的电压确定驱动晶体管的阈值电压，以及根据阈值电压修正来自数据信号端的原始数据信号，以提供至数据线。
在本公开的实施例中，数据信号提供电路可包括读取电路、确定电路和提供电路。读取电路被配置为根据第三控制信号，读取感测线上的电压。确定电路被配置为根据所读取的电压，确定驱动晶体管的阈值电压。提供电路被配置为根据阈值电压修正原始数据信号，以提供至数据线。
在本公开的实施例中，数据信号提供电路还可包括模数转换电路和存储电路。模数转换电路被配置为将阈值电压转换为数字信号形式。存储电路被配置为存储数字信号形式的阈值电压
在本公开的实施例中，数据写入电路可包括第一晶体管。第一晶体管的控制极耦接第一控制信号端，第一极耦接数据线，以及第二极耦接第一节点。
在本公开的实施例中，初始化电路可包括第二晶体管。第二晶体管的控制极耦接第二控制信号端，第一极耦接初始化信号，以及第二极耦接感测线。
在本公开的实施例中，感测电路可包括第三晶体管。第三晶体管的控制极耦接第一控制信号，第一极耦接感测线，以及第二极耦接第二节点。
在本公开的实施例中，像素电路还可包括第一参考电路。第一参考电 路被配置为根据来自第四控制信号端的第四控制信号，向数据线提供第一参考信号。
在本公开的实施例中，第一参考电路可包括第四晶体管。第四晶体管的控制极耦接第四控制信号端，第一极耦接第一参考信号，以及第二极耦接数据线。
在本公开的实施例中，像素电路还可包括第二参考电路。第二参考电路被配置为根据来自第五控制信号端的第五控制信号，向感测线提供第二参考信号。
在本公开的实施例中，第二参考电路可包括第五晶体管。第五晶体管的控制极耦接第五控制信号端，第一极耦接第二参考信号，以及第二极耦接感测线。
根据本公开的第二方面，提供了一种用于驱动本公开的第一方面的像素电路的方法。方法包括非显示阶段和显示阶段。在非显示阶段，在第一控制信号和第二控制信号的控制下，将来自数据线的数据信号提供至第一节点，将初始化信号提供至感测线，以及使得感测线上的电压和第二节点的电压相等；在第一控制信号的控制下，保持向第一节点提供数据信号，在第一节点的电压的控制下，驱动晶体管的驱动电流对第一电容和第二电容充电；在第三控制信号的控制下，读取感测线上的电压，根据所读取的电压，确定驱动晶体管的阈值电压。在显示阶段，根据阈值电压修正来自数据信号端的原始数据信号，以提供至数据线，在第一控制信号的控制下，将来自数据线的数据信号提供至第一节点，驱动晶体管提供驱动电流。
在本公开的实施例中，该方法还包括：在非显示阶段，在第四控制信号的控制下，向数据线提供第一参考信号。
在本公开的实施例中，该方法还包括：在显示阶段，在第五控制信号的控制下，向感测线提供第二参考信号。
在本公开的实施例中，非显示阶段的扫描频率低于显示阶段的扫描频率。
根据本公开的第三方面，提供了一种阵列基板。阵列基板可包括多个 根据本公开的第一方面的像素电路。各个像素电路的驱动晶体管、数据写入电路、感测电路和第一电容位于阵列基板的有效显示区。各个像素电路的第二电容、初始化电路和数据信号提供电路位于阵列基板的周边区域。
根据本公开的第四方面，提供了一种显示面板。显示面板包括本公开的第三方面的阵列基板。
附图说明
为了更清楚地说明本公开的技术方案，下面将对实施例的附图进行简单说明。应当知道，以下描述的附图仅仅是本公开的一些实施例，而非对本公开的限制，其中相同的附图标记指示相同的元件或信号。在附图中：
图1示出了根据本公开的实施例的像素电路的示意性框图；
图2示出了根据本公开的另一实施例的像素电路的示意性框图；
图3示出了如图1所示的像素电路的示例性电路图；
图4示出了如图2所示的像素电路的示例性电路图；
图5示出了根据本公开的实施例的显示***在非显示阶段和显示阶段的示例性示意图；
图6a示出了如图3所示的像素电路中的信号在非显示阶段的时序图；
图6b示出了如图3所示的像素电路中的信号在显示阶段的时序图；
图7a示出了如图4所示的像素电路中的信号在非显示阶段的时序图；
图7b示出了如图4所示的像素电路中的信号在显示阶段的时序图；
图8示出了根据本公开的实施例的用于驱动像素电路的方法的流程图；
图9示出了根据本公开的实施例的阵列基板的示意图；
图10示出了根据本公开的实施例的阵列基板中的信号的示例性时序图。
具体实施方式
为了使本公开的实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开的实施例的技术方案进行清楚、完整的描述。显然，所 描述的实施例仅仅是本公开的一部分实施例，而并非全部的实施例。基于所描述的实施例，本领域的普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例，也都属于本公开的范围。
在本公开的描述中，除非另有说明，“多个”的含义是两个或两个以上；术语“上”、“下”、“左”、“右”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的机或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开的描述中，需要说明的是，除非另有明确的规定和限定，术语“安装”、“连接”、“耦接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
图1示出了根据本公开的实施例的像素电路的示意性框图。如图1所示，像素电路100可包括数据写入电路110、初始化电路120、感测电路130、第一电容140、第二电容150、数据信号提供电路160和驱动晶体管TD。
在本公开的实施例中，数据写入电路110可耦接数据线DL、第一控制信号端S1和第一节点A。如图1所示，可经由第一节点A将数据写入电路110耦接到驱动晶体管TD的控制极(例如，栅极)。数据写入电路110可根据来自第一控制信号端S1的第一控制信号G，将来自数据线DL的数据信号V D提供至第一节点A，以控制第一节点A的电压V A。
初始化电路120可耦接感测线SL、第二控制信号端S2和初始化信号Ini。初始化电路120可根据来自第二控制信号端S2的第二控制信号R，将初始化信号Ini提供至感测线SL，以通过初始化电压V ini控制感测线SL上的电压V SL。
感测电路130可耦接感测线SL、第一控制信号端S1和第二节点B。如图1所示，可经由第二节点B将感测电路130耦接到驱动晶体管TD的 第二极(例如，源极)。感测电路130可被配置为根据第一控制信号G，将第二节点B耦接到感测线SL，使得第二节点B的电压V B和感测线SL上的电压V SL相等。
第一电容140可被耦接第一节点A和第二节点B之间。第一电容140可存储第一节点A和第二节点B之间的电荷量，即存储第一节点A和第二节点B之间的电压差。
第二电容150的一端可耦接感测线SL，另一端接地。第二电容150可存储感测线SL上的电荷量，即存储感测线SL上的电压V SL。
驱动晶体管TD的控制极耦接第一节点A，第一极耦接第一电压信号端V1，第二极耦接第二节点B。驱动晶体管TD可根据第一节点A的电压V A和第二节点B的电压V B，向发光器件提供驱动电流。在本公开的实施例中，驱动晶体管TD是N型晶体管。如图1所示，驱动晶体管TD的控制极(即第一节点A)是栅极，第一极是漏极，第二极(即第二节点B)是源极。驱动晶体管TD的栅源电压V gs是第一节点A的电压V A和第二节点B的电压V B之间的电压差。在驱动晶体管TD的栅源电压V gs(即V A-V B)在其阈值电压V th以上时，驱动晶体管TD导通。在驱动晶体管TD的栅源电压V gs(即V A-V B)低于其阈值电压V th时，驱动晶体管TD关断。在本公开的实施例中，在非显示阶段，当驱动晶体管TD导通时，驱动晶体管TD中的电流对第一电容C1和第二电容C2充电，使得第二节点B的电压V B升高。当第二节点B的电压V B升高到V A-V th时，栅源电压V gs等于阈值电压Vth(即VA-VB＝V A-V A+V th＝V th)，驱动晶体管TD关断，此时感测线SL上的电压V SL等于第二节点B的电压V B，即V A-V th。
数据信号提供电路160可耦接感测线SL、数据线DL、第三控制信号端S3和数据信号端DT。数据信号提供电路160可在来自第三控制信号端S3的第三控制信号P的控制下读取感测线SL上的电压V SL，根据数据线DL上的数据信号V D和所读取的电压V SL，计算驱动晶体管TD的阈值电压V th。然后，数据信号提供电路160可根据驱动晶体管TD的阈值电压V th对来自数据信号端DT的原始数据信号V D0进行修正，并将经修正的数 据信号V D1提供至数据线DL，作为下一帧的数据线DL上的数据信号。在本公开的实施例中，数据信号提供电路160可在非显示阶段与数据线DL断开连接(例如，呈高阻状态)，以避免影响数据线DL上的数据信号。此外，数据信号提供电路160可在显示阶段与感测线SL断开连接(例如，呈高阻状态)，以避免影响感测线SL上的电压。
在本公开的实施例中，数据信号提供电路160从感测线SL上读取的电压为V A-V th，而此时第一节点A的电压V A在数据写入电路110的控制下等于数据线DL的数据信号的电压V D，因此驱动晶体管TD的阈值电压V th可通过计算数据线的数据信号V D和所读取的电压V SL之间的电压差(即V th＝V D-V SL)来确定。另外，可通过对原始数据信号V D0加上阈值电压V th，来修正原始数据信号V D0，以得到修正的数据信号V D1(即V D1＝V D0+V th)，并将其提供至数据线DL。进一步地，驱动晶体管DT可根据来自数据线DL的修正的数据信号V D1提供驱动电流。
此外，像素电路100还可包括发光器件D(以虚线框示出)。发光器件D的阳极耦接驱动晶体管TD的第二极，阴极耦接第二电压信号端V2。发光器件D可根据驱动晶体管TD所提供的驱动电流发光。发光器件D例如是OLED等。
根据本公开的实施例，像素电路100可确定驱动晶体管TD的阈值电压，并对数据信号端DT提供的原始数据信号V D0进行补偿。驱动晶体管TD所提供的驱动电流与栅源电压V gs与阈值电压V th的差(V gs-V th)相关，根据计算，V gs-V th＝V A-V B-V th＝V D1-V SL-V th＝V D0+V th-V SL-V th＝V D0-V SL。因此，在进行显示时，驱动晶体管TD所提供的驱动电流仅与数据信号端DT提供的原始数据信号V D0和感测线SL上的电压V SL相关，而不会受到阈值电压偏差或由IR drop引起的电源电压(例如第一电压信号端V1的第一电压信号VDD和第二电压信号端V2的第二电压信号VSS)的影响而产生像素点的亮度不一致的情况。
根据本公开的实施例，通过确定像素电路中驱动晶体管的电学特性(例如，阈值电压)，并在显示时根据所确定的电学特性来补偿数据信号端的原 始数据信号。由此，驱动晶体管所提供的驱动电流与其电学特性无关，从而消除了不同像素电路之间由于驱动晶体管的特性差异引起的亮度差异。
图2示出了根据本公开的另一实施例的像素电路的示意性框图。如图2所示，像素电路200可包括数据写入电路110、初始化电路120、感测电路130、第一电容140、第二电容150、数据信号提供电路160、驱动晶体管TD、第一参考电路270和第二参考电路280。
在本公开的实施例中，第一参考电路270可耦接第四控制信号端S4、数据线DL和第一参考信号REF1。第一参考电路270可根据来自第四控制信号端S4的第四控制信号S向数据线DL提供第一参考信号REF1，以作为数据线DL上的数据信号V D。
第二参考电路280可耦接第五控制信号端S5、感测线SL和第二参考信号REF2。第二参考电路280可根据来自第五控制信号端S5的第五控制信号EM向感测线SL提供第二参考信号REF2，以控制感测线SL上的电压V SL。
在本公开的另一实施例中，第一参考电路270和第二参考电路280也可与像素电路200的其它部分分开设置。例如，第一参考电路270和第二参考电路280可被设置在独立的驱动器电路中，驱动器电路可包括处理器和存储器，存储器内存储有计算机程序指令，该计算机程序指令在由处理器执行时根据来自第四控制信号端S4的第四控制信号S向数据线DL提供第一参考信号REF1，以及根据来自第五控制信号端S5的第五控制信号EM向感测线SL提供第二参考信号REF2。
因此，根据本公开实施例的像素电路可在特定时间对数据线DL和感测线SL提供稳定的电压，像素电路的驱动方法将在下文中详细描述。
除此之外，图2中的像素电路200与图1中的像素电路100的结构相同，不再详细描述。
此外，可通过数据写入电路110将第一参考电路270所提供的第一参考信号REF1提供至第一节点A，以控制第一节点A的电压V A。可通过感测电路130将第二参考电路280所提供的第二参考信号REF2提供至第二 节点B，以控制第二节点B的电压V B。
图3示出了根据本公开的实施例的像素电路的示例性电路图，像素电路300例如是图1中所示的像素电路100。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。
在本公开的实施例中，以N型场效应晶体管(NMOS)为例进行详细的描述。
如图3所示，数据写入电路110可包括第一晶体管T1。第一晶体管T1的控制极耦接第一控制信号端S1，第一极耦接数据线DL，以及第二极耦接第一节点A。第一晶体管T1可在来自第一控制信号端S1的第一控制信号G的控制下，将来自数据线DL的数据信号V D提供至第一节点A。
初始化电路120可包括第二晶体管T2。第二晶体管T2的控制极耦接第二控制信号端S2，第一极耦接初始化信号Ini，第二极耦接感测线SL。第二晶体管T2可在来自第二控制信号端S2的第二控制信号R的控制下，将初始化信号Ini提供至感测线SL，以作为感测线SL的初始化的电压V SL。
感测电路130可包括第三晶体管T3。第三晶体管T3的控制极耦接第一控制信号端S1，第一极耦接感测线SL，第二极耦接第二节点B。第三晶体管T3可在第一控制信号G的控制下，将第二节点B耦接到感测线SL，使得第二节点B的电压V B和感测线SL上的电压V SL相等。在实施例中，在初始化阶段，感测线SL的电压V SL(即初始化信号Ini)被提供至第二节点B，以作为第二节点B的电压V B。在建立阶段，第二节点B的电压V B被传递至感测线SL上，以作为感测线SL上的电压V SL。后文将对初始化阶段和建立阶段进行详细描述。
第一电容140可包括电容C1，第二电容150可包括电容C2。
驱动晶体管TD的结构已在上文中描述，在此不再详细描述。
在本公开的实施例中，数据信号提供电路160可包括读取电路M1、确定电路M2和提供电路M3。
读取电路M1可根据来自第三控制信号端S3的第三控制信号P，读取感测线SL上的电压V SL，并将所读取的电压V SL提供至确定电路M2的第一输入端。如图3所示，读取电路M1例如是第五晶体管，其控制极耦接第三控制信号端S3，第一极耦接感测线SL，以及第二极耦接确定电路M2的第一输入端。
确定电路M2可根据数据线DL上的数据信号D和所读取的电压V SL，确定驱动晶体管TD的阈值电压V th，并将所确定的阈值电压V th提供给提供电路M3。在实施例中，确定电路M2可包括减法器，其第一输入端耦接读取电路M1以接收所读取的电压V SL、第二输入端耦接数据线DL、输出端耦接提供电路M3。阈值电压V th可通过计算数据信号V D和所读取的电压V SL之间的电压差来确定。
在本公开的实施例中，数据信号提供电路160还可包括模数转换电路(未示出)，例如是模数转换器ADC，其将确定电路M2所确定的阈值电压V th转换成数字信号。可选地，数据信号提供电路160还可包括存储电路(未示出)。存储电路可存储数字信号形式的阈值电压V th。在实施例中，存储电路可以是任何具有存储功能的存储器，在其地址上存储数字信号形式的阈值电压V th。
提供电路M3可根据所确定的(或所存储的)阈值电压V th和来自数据信号端DT的原始数据信号V D0，对数据线DL上的数据信号进行修正，并向数据线DL提供修正的数据信号V D1。在示例中，提供电路M3可通过加法器实现，其第一输入端耦接数据信号端DT、第二输入端耦接确定电路M2(可选地，存储电路)以接收阈值电压V th，输出端耦接数据线DL。加法器对阈值电压V th和原始数据信号V D0进行求和，以得到修正的数据信号V D1，并将其输出至数据线DL。
在本公开的实施例中，数据信号提供电路160还可以由处理器等软硬件结合的形式实现。例如，数据信号提供电路160可包括存储器和处理器， 存储器内存储有计算机程序指令，该计算机程序指令在由处理器执行时使数据信号提供电路160执行根据第三控制信号P读取感测线上的电压V SL，根据数据信号D和所读取的电压V SL确定驱动晶体管的阈值电压V th(其可被转换为数字信号并存储在存储器中)，以及根据阈值电压V th和来自数据信号端DT的原始数据信号V D0，向数据线DL提供修正的数据信号V D1。
图4示出了根据本公开的实施例的像素电路的示例性电路图，像素电路400例如是如图2所示的像素电路200。在实施例中，所采用的晶体管可以是N型晶体管或者P型晶体管。具体地，晶体管可以是N型或P型场效应晶体管(MOSFET)，或者N型或P型双极性晶体管(BJT)。在本公开的实施例中，晶体管的栅极被称为控制极。由于晶体管的源极和漏极是对称的，因此对源极和漏极不做区分，即晶体管的源极可以为第一极(或第二极)，漏极可以为第二极(或第一极)。
在本公开的实施例中，以N型场效应晶体管(NMOS)为例进行详细的描述。
如图4所示，在本公开的实施例中，除图3所示的像素电路300的电路结构外，像素电路400还可包括第一参考电路270和第二参考电路280。第一参考电路270可包括第四晶体管T4，第四晶体管T4的控制极耦接第四控制信号端S4，第一极耦接第一参考信号REF1，第二极耦接数据线DL，并可在来自第四控制信号端S4的第四控制信号S的控制下，将第一参考信号REF1提供至数据线DL。第二参考电路280可包括第五晶体管T5，第五晶体管T5的控制极耦接第五控制信号端S5，第一极耦接第二参考信号REF2，第二极耦接感测线SL，并可在来自第五控制信号端S5的第五控制信号EM的控制下，将第二参考信号REF2提供至感测线SL。
在本公开的实施例中，将像素电路的驱动晶体管的特性读取(即确定阈值电压)以及显示正常画面分为两个不同阶段进行，即非显示阶段和显示阶段。对于非显示阶段和显示阶段的顺序不做具体限定。例如，特性读取可以在显示器件正常显示的前几帧到几百帧的时间之前进行，或者在显示完成后到关机的非显示阶段进行，或者在显示阶段的前后均执行。
图5示出根据本公开的实施例的非显示阶段和显示阶段的示例性时序图。在示例中，如图5所示，从电源开启到显示结束后电源关闭，经过非显示阶段、显示阶段和非显示阶段三个阶段。
从电源开启到显示器件显示正常的画面的非显示阶段可包括显示器件***设置阶段和电学特性读取(及保存)阶段。显示器件***设置阶段将电源电压设定到设定值，并设定显示***的控制信号和时序。在电学特性读取保存阶段，对像素点逐行读取像素点内驱动晶体管的阈值电压Vth的值，并将检测的值保存在控制器件中。
在显示阶段，根据确定的阈值电压对数据信号端提供的数据信号进行补偿，并使显示***根据正常的时序依次显示画面，从而实现对像素点像素电压进行补偿。
在显示器件显示正常画面后进入关机的非显示阶段，还可以再一次设置电学特性读取保存阶段以及***复位阶段，然后再关断电源。
以下分别对本公开的实施例提供的像素电路300和像素电路400在非显示阶段和显示阶段的操作过程进行详细描述。
图6a和6b分别示出了根据本公开的实施例的像素电路中的信号在非显示阶段和显示阶段的时序图，像素电路例如是图3所示的像素电路300。在实施例中，第一电压信号Vdd为高电平信号，第二电压信号Vss为低电平信号。
如图6a所示，非显示阶段可相应地包括初始化阶段P1、建立阶段P2和读取阶段P3。
在初始化阶段P1，第一控制信号G和第二控制信号R均处于高电平，以使得第一晶体管T1、第二晶体管T2和第三晶体管T3均导通。向数据线DL提供数据信号V D，例如可直接通过数据信号端DT向数据线DL提供(例如也可提供其它参考信号)。通过第一晶体管T1将数据线DL上的数据信号V D提供至第一节点A，以使得第一节点的电压(V A)为V D。初始化信号Ini(例如为低电平信号，电压值可表示为V ini)经由第二晶体管T2而被提供至感测线SL，进而经由第三晶体管T3被提供至第二节点B。因 此，在初始化阶段T1期间，第二节点B的电压V B为V ini。以这种方式，通过数据信号V D和初始化信号Ini分别对驱动晶体管TD的栅极(即第一节点A)和源极(即第二节点B)的电压进行初始化。此外，第一电容C1可存储第一节点A和第二节点B之间的电压差，即V D-V ini，即保持驱动晶体管TD的栅源电压V gs。
在建立阶段P2，第一控制信号G保持为高电平，第二控制信号R处于低电平。第一晶体管T1和第三晶体管T3保持导通，而第二晶体管T2关断。第一节点A的电压V A保持为V D。驱动晶体管TD中的电流对第一电容C1和第二电容C2充电，使得第二节点B的电压V B和感测线SL的电压逐渐升高。相应地，驱动晶体管的栅源电压V gs(即V A-V B)减小，驱动晶体管TD中的电流也对应减小。直到感测线SL上的电压达到数据信号V D与驱动晶体管TD的阈值电压V th的电压差时，驱动晶体管TD关断。此时，可近似认为感测线SL上的电压为V D-V th。在本公开的实施例中，建立阶段T2的时段越长，感测线SL上的电压越接近V D-V th。
在读取阶段P3，第一控制信号G保持为高电平，第一晶体管T1和第三晶体管T3保持导通，维持第一节点A的电压V A为V D。如上可理解的，感测线上的电压近似为V D-V th。第三控制信号P处于高电平，通过读取电路M1读取感测线SL上的电压(V D-V th)。然后，确定电路M2确定驱动晶体管TD的阈值电压V th，例如通过计算数据信号V D和所读取的感测线上的电压V SL之间的电压差确定，即V D-(V D-V th)＝V th。可选地，模数转换电路可将所确定的阈值电压V th转换为数字信号，存储电路可对阈值电压V th进行存储。
在本公开的实施例中，为了保证数据线DL上的数据信号的稳定性，在非显示阶段可将数据信号提供电路160与数据线DL断开连接。
如图6b所示，在显示阶段，第二控制信号R保持为高电平，第二晶体管T2保持导通。在第一控制信号G为高电平的写入数据阶段，第一晶体管T1、和第三晶体管T3均导通。通过第二晶体管T2向感测线SL提供初始化信号Ini(例如也可提供其它参考信号)，进而通过第三晶体管T3将 初始化信号Ini传递至第二节点B，使得电压第二节点B的电压V B为初始化信号Ini的初始化电压V ini。提供电路M3接收来自数据信号端DT的原始数据信号V D0和所确定(及存储的)驱动晶体管TD的阈值电压V th，并向数据线DL提供修正的数据信号V D1。例如，通过对原始数据信号V D0和阈值电压V th相加来获得修正的数据信号V D1，即V D1＝V D0+V th。进一步地，第一晶体管T1将数据线DL上的数据信号(即经修正的数据信号V D1)提供至第一节点A，即驱动晶体管TD的控制极，以控制驱动晶体管提供驱动电流。因此，第一节点的电压V A为V D1＝V D0+V th。驱动晶体管TD所提供的电流表示如下：
Figure PCTCN2019080113-appb-000001
其中，μ、Cox、W和L与驱动晶体管的材料、尺寸相关。因此，驱动晶体管TD所提供的电流仅与数据信号端DT提供的原始数据信号V D0和初始化信号Ini相关。
然后，发光器件D可根据驱动晶体管TD提供的电流发光。
在本公开的实施例中，为了保证感测线SL上的电压的稳定性，在显示阶段可将数据信号提供电路160与感测线SL断开连接。
由上，根据本公开的实施例的像素电路可避免受到驱动晶体管的阈值电压和电源电压的影响。
本领域的技术人员可理解的是，非显示阶段的建立阶段的时间越充足，则读取到的阈值电压就越准确。第一控制信号例如是行扫描信号，所以一行的时间和信号的帧频相关。因此，可将非显示阶段的扫描频率设定为低于显示阶段的扫描频率。例如，可将显示阶段的扫描频率设定为60Hz，而将非显示阶段的扫描频率设定为10Hz，甚至1Hz。
图7a和7b分别示出了根据本公开的实施例的像素电路中的信号在非显示阶段和显示阶段的时序图。像素电路例如是图4所示的像素电路400。 其中，第一电压信号Vdd为高电平信号，第二电压信号Vss为低电平信号，初始化信号Vini为低电平信号。
如图7a所示，非显示阶段也可包括初始化阶段P1、建立阶段P2和读取阶段P3。
在初始化阶段P1，提供高电平的第四控制信号S，通过第四晶体管T4向数据线DL提供第一参考信号REF1。与图6a所示的信号的时序类似地，通过第一晶体管T1将数据线DL上的第一参考信号REF1提供至第一节点A，使得第一节点A的电压V A为第一参考信号的电压V ref1。通过第二晶体管T2和第三晶体管T3向第二节点B提供初始化信号Ini，以使得第二节点B的电压V B为V ini
在建立阶段P2，第一节点A的电压V A保持为V ref1，第二节点B的电压V B和感测线SL上的电压V SL逐渐升高。与图6a所示的信号的时序类似，在此不再详细描述。
在读取阶段P3，通过读取电路M1读取感测线SL上的电压V SL，即V ref1-V th。然后，确定电路M2根据第一参考信号(V ref1)和所读取的电压(V ref1-V th)，确定阈值电压V th。可选地，将其转换为数字信号并存储到存储电路中。
此外，如图7b所示，在显示阶段期间，提供高电平的第五控制信号EM。第五晶体管T5导通，并向感测线SL提供第二参考信号REF2，其电压由V ref2表示。第二控制信号R和第四控制信号S保持处于低电平。与图6b所示的信号的时序图类似，驱动晶体管的驱动电流与其栅源电压V gs和阈值电压V th的差相关，即V gs-V th＝V D1-V ref2-V th＝V D0+V th-V ref2-V th＝V D0-V ref2。
由此，根据本公开的实施例的像素电路400中的驱动电流仅与原始数据信号和第二参考信号相关。
然后，发光器件根据驱动电流发光。
图8示出了根据本公开实施例的用于驱动像素电路的方法的示意性流程图。
如图8所示，在步骤S810，在第一控制信号和第二控制信号的控制下， 将来自数据线的数据信号提供至第一节点，将初始化信号提供至感测线，以及将第二节点耦接到感测线，使得感测线上的电压和第二节点的电压相等。
在步骤S820，在第一控制信号的控制下，保持向第一节点提供数据信号，在第一节点的电压的控制下，驱动晶体管的驱动电流对耦接在第一节点和第二节点之间的第一电容和与感测线耦接的第二电容充电。
在步骤S830，在第三控制信号的控制下，读取感测线上的电压，根据数据信号和所读取的电压，确定驱动晶体管的阈值电压。可选地，还可将所确定的阈值电压转换成数字信号以及进行存储。
在本公开的实施例中，步骤S810、步骤S820和步骤S830可在非显示阶段进行。可选地，在非显示阶段，还可在第四控制信号的控制下，向数据线提供第一参考信号。
在步骤S840，根据阈值电压修正来自数据信号端的原始数据信号，以提供至数据线，在第一控制信号的控制下，将来自数据线的数据信号提供至第一节点，驱动晶体管导通并向发光器件提供驱动电流。
在本公开的实施例中，步骤S840可在显示阶段进行。可选地，在显示阶段期间，还可在第五控制信号的控制下，向感测线提供第二参考信号。
在本公开的实施例中，非显示阶段的扫描频率低于显示阶段的扫描频率。
本领域的技术人员可理解的是，虽然在本公开的实施例中以步骤S810、S820、S830和S840表示驱动像素电路的方法的顺序，但并不构成对本公开的实施例的限制。非显示阶段(S810、S820、S830)可在显示阶段(S840)的之前和/或之后执行。
图9示出了根据本公开实施例的阵列基板的示意图。阵列基板900可包括根据本公开的实施例的多个像素电路，图9中仅示意性地示出一个像素电路910，例如是像素电路100或像素电路200。如图9所示，各个像素电路的驱动晶体管TD、数据写入电路110、感测电路130和第一电容140被设置在阵列基板的有效显示区AA中，各个像素电路的第二电容150、 初始化电路120和数据信号提供电路160被设置在阵列基板的周边区域。此外，第一参考电路270和第二参考电路280也可被设置在阵列基板的周边区域。
在本公开的实施例中，数据信号提供电路160也可以被设置在阵列基板之外的背板电路上，并通过相应的接口连接到像素电路的其它部分。
在实施例中，在有效显示区AA内的多个像素电路部分可被布置为矩阵状。
在本公开的实施例中，阵列基板900还可包括级联的移位寄存器单元(GOA)，移位寄存器单元向同一行的像素电路提供第一控制信号。同一列的像素电路耦接同一条数据线DL和同一条扫描线SL。
在本公开的实施例中，由于像素电路在有效显示区的部分只有3个晶体管和一个电容，因此可以在更高分辨率下布线。
根据本公开的实施例，可补偿多个像素电路中的驱动晶体管的阈值电压的偏差和漂移，以及补偿IR drop引起的电源远端与近端的亮度差异，从而可以提高显示的均一性和显示品质。
以阵列基板上的像素电路为图4中的像素电路400为例，在图10中示出了根据本公开的实施例的阵列基板中的信号的示例性时序图。
如图10所示，逐行对像素电路提供高电平的第一控制信号G，例如，第一行像素电路的第一控制信号G1，第二行像素电路的第一控制信号G2。以上已经分别对像素电路的信号在非显示阶段和显示阶段的时序的进行了描述，在此不再赘述。
另一方面，本公开的实施例还提供了一种包括以上阵列基板的显示面板，以及包括该显示面板的显示装置。显示装置例如可以是显示屏、移动电话、平板计算机、照相机、可穿戴式设备等。
以上对本公开的若干实施方式进行了详细描述，但本公开的保护范围并不限于此。显然，对于本领域的普通技术人员来说，在不脱离本公开的精神和范围的情况下，可以对本公开的实施例进行各种修改、替换或变形。本公开的保护范围由所附权利要求限定。

Claims (16)

  1. 一种像素电路，包括：
    数据写入电路，其被配置为根据来自第一控制信号端的第一控制信号，将来自数据线的数据信号提供至第一节点；
    初始化电路，其被配置为根据来自第二控制信号端的第二控制信号，将初始化信号提供至感测线；
    感测电路，其被配置为根据所述第一控制信号，将第二节点耦接到所述感测线，使得所述第二节点的电压和所述感测线上的电压相等；
    第一电容，其被配置为存储所述第一节点和所述第二节点之间的电压差；
    第二电容，其被配置为存储所述感测线上的电压；
    驱动晶体管，其控制极耦接所述第一节点，第一极耦接第一电压信号端，第二极耦接所述第二节点，并被配置为向发光器件提供驱动电流；以及
    数据信号提供电路，其被配置为根据来自第三控制信号端的第三控制信号读取所述感测线上的电压，根据所读取的电压确定所述驱动晶体管的阈值电压，以及根据所述阈值电压修正来自数据信号端的原始数据信号，以提供至所述数据线。
  2. 根据权利要求1所述的像素电路，其中，所述数据信号提供电路包括：
    读取电路，其被配置为根据所述第三控制信号，读取所述感测线上的电压；
    确定电路，其被配置为根据所读取的电压，确定所述驱动晶体管的阈值电压；
    提供电路，其被配置为根据所述阈值电压修正所述原始数据信号，以提供至所述数据线。
  3. 根据权利要求2所述的像素电路，其中，所述数据信号提供电路还 包括：
    模数转换电路，其被配置为将所述阈值电压转换为数字信号形式；以及
    存储电路，其被配置为存储所述数字信号形式的阈值电压。
  4. 根据权利要求1所述的像素电路，其中，所述数据写入电路包括：
    第一晶体管，所述第一晶体管的控制极耦接所述第一控制信号端，第一极耦接所述数据线，第二极耦接所述第一节点。
  5. 根据权利要求1所述的像素电路，其中，所述初始化电路包括：
    第二晶体管，所述第二晶体管的控制极耦接所述第二控制信号端，第一极耦接所述初始化信号，第二极耦接所述感测线。
  6. 根据权利要求1所述的像素电路，其中，所述感测电路包括：
    第三晶体管，所述第三晶体管的控制极耦接所述第一控制信号，第一极耦接所述感测线，第二极耦接所述第二节点。
  7. 根据权利要求1至6中任一项所述的像素电路，还包括：
    第一参考电路，其被配置为根据来自第四控制信号端的第四控制信号，向所述数据线提供第一参考信号。
  8. 根据权利要求7所述的像素电路，其中，所述第一参考电路包括：
    第四晶体管，所述第四晶体管的控制极耦接所述第四控制信号端，第一极耦接所述第一参考信号，第二极耦接所述数据线。
  9. 根据权利要求1至6中任一项所述的像素电路，还包括:
    第二参考电路，其被配置为根据来自第五控制信号端的第五控制信号，向所述感测线提供第二参考信号。
  10. 根据权利要求9所述的像素电路，其中，所述第二参考电路包括:
    第五晶体管，所述第五晶体管的控制极耦接所述第五控制信号端，第一极耦接所述第二参考信号，第二极耦接所述感测线。
  11. 一种用于驱动如权利要求1至6中任一项所述的像素电路的方法，包括:
    在非显示阶段：
    在第一控制信号和第二控制信号的控制下，将来自数据线的数据信号提供至第一节点，将初始化信号提供至感测线，以及使得所述感测线上的电压和所述第二节点的电压相等；
    在第一控制信号的控制下，保持向所述第一节点提供所述数据信号，在所述第一节点的电压的控制下，驱动晶体管的驱动电流对第一电容和第二电容充电；
    在第三控制信号的控制下，读取所述感测线上的电压，根据所读取的电压，确定所述驱动晶体管的阈值电压；
    在显示阶段，根据所述阈值电压修正来自数据信号端的原始数据信号，以提供至所述数据线，在第一控制信号的控制下，将来自所述数据线的数据信号提供至所述第一节点，驱动晶体管提供驱动电流。
  12. 根据权利要求11所述的方法，其中，像素电路包括第一参考电路，其被配置为根据来自第四控制信号端的第四控制信号，向所述数据线提供第一参考信号，所述方法还包括：
    在非显示阶段，在第四控制信号的控制下，向所述数据线提供第一参考信号。
  13. 根据权利要求11所述的方法，其中，像素电路包括第二参考电路，其被配置为根据来自第五控制信号端的第五控制信号，向所示感测线提供第二参考信号，所述方法还包括：
    在显示阶段，在第五控制信号的控制下，向所述感测线提供第二参考信号。
  14. 根据权利要求11至13中任一项所述的方法，其中，
    所述非显示阶段的扫描频率低于所述显示阶段的扫描频率。
  15. 一种阵列基板，包括多个如权利要求1至10中任一项所述的像素电路，其中，
    各个所述像素电路的驱动晶体管、数据写入电路、感测电路和第一电容位于所述阵列基板的有效显示区，
    各个所述像素电路的第二电容、初始化电路和数据信号提供电路位于 所述阵列基板的周边区域。
  16. 一种显示面板，包括如权利要求15所述的阵列基板。
PCT/CN2019/080113 2018-06-19 2019-03-28 像素电路及其驱动方法、阵列基板、显示面板 WO2019242369A1 (zh)

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