WO2019233198A1 - 显示面板、显示面板的制造方法和显示装置 - Google Patents

显示面板、显示面板的制造方法和显示装置 Download PDF

Info

Publication number
WO2019233198A1
WO2019233198A1 PCT/CN2019/083277 CN2019083277W WO2019233198A1 WO 2019233198 A1 WO2019233198 A1 WO 2019233198A1 CN 2019083277 W CN2019083277 W CN 2019083277W WO 2019233198 A1 WO2019233198 A1 WO 2019233198A1
Authority
WO
WIPO (PCT)
Prior art keywords
base substrate
terminal
layer
pattern
orthographic projection
Prior art date
Application number
PCT/CN2019/083277
Other languages
English (en)
French (fr)
Inventor
王大伟
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/610,202 priority Critical patent/US11562973B2/en
Publication of WO2019233198A1 publication Critical patent/WO2019233198A1/zh

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/84Passivation; Containers; Encapsulations
    • H10K50/844Encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80Constructional details
    • H10K59/87Passivation; Containers; Encapsulations
    • H10K59/873Encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022Protective coating, i.e. protective bond-through coating
    • H01L2224/02205Structure of the protective coating
    • H01L2224/02206Multilayer protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/022Protective coating, i.e. protective bond-through coating
    • H01L2224/0221Shape of the protective coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/03011Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/03019Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for protecting parts during the process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05075Plural internal layers
    • H01L2224/0508Plural internal layers being stacked
    • H01L2224/05083Three-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/0518Molybdenum [Mo] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666Titanium [Ti] as principal constituent
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/1201Manufacture or treatment

Definitions

  • Embodiments of the present disclosure relate to a display panel, a method of manufacturing the display panel, and a display device.
  • a display panel generally includes a base substrate, and terminals are provided on the base substrate. After the manufacturing of the display panel is completed, it is generally necessary to connect the terminals in the display panel with an external control component to control the display function of the display panel through the control component.
  • At least one embodiment of the present disclosure provides a display panel, a method for manufacturing the display panel, and a display device, which can prevent the sides of the internal film layers of the terminals on the display panel from being exposed to the external environment and being eroded by external water and oxygen, thereby avoiding Degradation of electrical performance of the terminal.
  • an embodiment of the present disclosure provides a display panel including a base substrate on which a terminal and a terminal protection layer pattern are provided; wherein the terminal protection layer pattern includes A first shielding area and a first opening area, and the orthographic projection of the first shielding area on the base substrate and the orthographic projection of the terminal on the base substrate have overlapping areas, and the overlapping areas are located at An edge of an orthographic projection of the terminal on the base substrate, and an orthographic projection of the first opening region on the base substrate is located in an orthographic projection of the terminal on the base substrate.
  • a display structure and a barrier layer pattern are further provided on the base substrate, the barrier layer pattern is configured to protect the display structure, and the terminal protection layer pattern is disposed on the same layer as the barrier layer pattern.
  • an opening area is provided between the terminal protection layer pattern and the barrier layer pattern.
  • a flat layer protection pattern is further provided on the base substrate, and the flat layer protection pattern includes a second shielding area and a second opening area, and the second shielding area is positive on the base substrate.
  • the flat layer protection pattern includes a second shielding area and a second opening area, and the second shielding area is positive on the base substrate.
  • the material of the terminal protection layer pattern includes one of silicon nitride, silicon oxide, and silicon oxynitride.
  • a material of the terminal protection layer includes an organic material.
  • the terminal has a multilayer structure.
  • the terminal includes a titanium structure, an aluminum structure, and a titanium structure that are sequentially disposed in a direction away from the base substrate.
  • a buffer layer, a first gate insulating layer, a gate, a second gate insulating layer, and an intermediate dielectric layer are sequentially disposed on the base substrate, and the intermediate dielectric layer and the second gate insulating layer are sequentially disposed on the base substrate.
  • a through hole is provided in the terminal; the terminal is in contact with the gate through the through hole.
  • an embodiment of the present disclosure further provides a method for manufacturing a display panel, the method comprising: forming a terminal on a base substrate; and forming a terminal protection layer pattern on the base substrate on which the terminal is formed
  • forming the terminal protection layer pattern includes: forming a first shielding area and a first opening area, so that the orthographic projection of the first shielding area on the base substrate and the terminal on the base substrate There is an overlapping area on the orthographic projection on the base, and the overlapping area is located at an edge of the orthographic projection of the terminal on the base substrate, and the orthographic projection of the first opening area on the base substrate is located in the The terminals are in an orthographic projection on the base substrate.
  • the method further includes: forming a display structure on the base substrate.
  • the forming a terminal protection layer pattern on the base substrate on which the terminals are formed includes: forming a barrier layer on the base substrate on which the display structure and the terminals are formed; and processing the barrier layer into a barrier layer. A pattern and the terminal protection layer pattern, wherein the blocking layer pattern is configured to protect the display structure.
  • the processing the barrier layer into a barrier layer pattern and the terminal protection layer pattern includes: forming a photoresist layer on a base substrate on which the barrier layer is formed; Performing exposure and development to process the photoresist layer into a photoresist pattern; processing the barrier layer into the barrier layer pattern and the terminal protection layer pattern by an etching process; and removing the remaining the Photoresist pattern.
  • the method further includes: forming a flat layer protective pattern on the base substrate on which the terminals are formed, the The flat layer protection pattern includes a second shielding area and a second opening area.
  • the orthographic projection of the second shielding area on the base substrate and the orthographic projection of the terminal on the base substrate have overlapping areas.
  • the orthographic projection of the second opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate.
  • the forming a terminal protection layer pattern on a base substrate on which the terminals are formed includes: forming the terminal protection layer pattern on a base substrate on which the flat layer protection pattern is formed.
  • the method further includes: sequentially forming a buffer layer, a first gate insulating layer, a gate, a second gate insulating layer, and an intermediate on the base substrate.
  • a dielectric layer, a through hole is provided in the intermediate dielectric layer and the second gate insulating layer.
  • the forming a terminal on a base substrate includes forming the terminal on a base substrate on which the intermediate dielectric layer is formed, and the terminal is in contact with the gate through the through hole.
  • an embodiment of the present disclosure further provides a display device, the display device including the display panel described in the first aspect.
  • FIG. 1 is a schematic structural diagram of an array substrate
  • FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 4 is a plan view of the display panel shown in FIG. 3;
  • FIG. 5 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • FIG. 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure.
  • FIG. 8 is a flowchart of a method for manufacturing a display panel according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic structural diagram of an example of a base substrate in the embodiment shown in FIG. 8;
  • FIG. 10 is a schematic structural diagram of another example of a base substrate in the embodiment shown in FIG. 8;
  • FIG. 11 is a schematic diagram of forming a barrier layer pattern and a terminal protection layer pattern in the embodiment shown in FIG. 8;
  • FIG. 12 is a schematic structural diagram of still another example of a base substrate in the embodiment shown in FIG. 8.
  • FIG. 1 is a schematic structural diagram of an array substrate.
  • the array substrate includes a base substrate 11 on which terminals 12 are disposed.
  • the terminal 12 includes a film layer structure 122 and a terminal protection layer 121.
  • the terminal protection layer 121 is disposed on the side c1 of the film layer structure 122 away from the substrate substrate.
  • the protection layer 121 can prevent the side c1 of the film layer structure 122 away from the substrate substrate 11 from being directly exposed to the external environment and oxidizing. .
  • the side c2 of the film layer structure 122 in the terminal 12 is still exposed to the external environment. After the side c2 is corroded by the external water and oxygen, the electrical performance of the terminal 12 is reduced.
  • At least one embodiment of the present disclosure provides a display panel, a method of manufacturing the display panel, and a display device, which can solve the problems existing in the above-mentioned array substrate.
  • FIG. 2 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure.
  • the display panel may include a base substrate 21. Terminals 22 are provided on the base substrate 21.
  • a terminal protection layer pattern 23 is provided on the base substrate 21 provided with the terminals 22.
  • the terminal protection layer pattern 23 includes a first shielding area a1 and a first opening area a2.
  • the orthographic projection (not shown in FIG. 2) of the first shielding area a1 on the substrate 21 and the orthography of the terminal 22 on the substrate There is an overlap area in the projection (not shown in FIG. 2), and the overlap area is located at the edge of the orthographic projection of the terminal 22 on the base substrate 21.
  • the orthographic projection (not shown in FIG. 2) of the first opening region a2 on the base substrate 21 is located in the orthographic projection (not shown in FIG. 2) of the terminal 22 on the base substrate 21.
  • both the terminals are exposed to enable the terminals to be electrically connected to the outside, and
  • the side of the terminal is prevented from being directly exposed to the external environment, and the side of the terminal is prevented from being corroded by water and oxygen in the external environment. Therefore, the problem that the side of the internal film layer of the terminal is still exposed to the external environment and is easily eroded by external water and oxygen, which causes the electrical performance of the terminal to decrease, is achieved, and the effect of avoiding the decrease of the electrical performance of the terminal is achieved.
  • FIG. 3 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure. Different from the embodiment shown in FIG. 2, the display panel in the embodiment shown in FIG. 3 further includes a display structure and a barrier layer pattern.
  • a display structure 24 is further provided on the base substrate 11.
  • the display structure may be a structure configured to implement a display function.
  • the display structure may be different according to the type of the display panel. For example, when the display panel is an organic light emitting diode (English: Organic Light-Emitting Diode; OLED for short) display panel, the display structure may be a display structure including an organic light emitting structure.
  • OLED Organic Light-Emitting Diode
  • the base substrate 21 provided with the display structure 24 and the terminals 22 may further be provided with a barrier layer pattern 25 configured to protect the display structure 24.
  • the blocking layer pattern 25 can be disposed on the same layer as the terminal protection layer pattern 23.
  • the barrier layer pattern 25 may be a protection structure formed by a thin film encapsulation (English: Thin Film Encapsulation; TFE for short) technology.
  • the protection structure may include a single-layer inorganic film, or a multilayer composite inorganic film, or include multiple layers. Composite inorganic and organic films.
  • the terminal protection layer pattern 23 configured to protect the terminal 22 may be disposed on the same layer as the barrier layer pattern 25 configured to protect the display structure 24, so that the thickness of the entire display panel can be reduced.
  • the material of the terminal protection layer pattern 23 may include silicon nitride, silicon oxide, or silicon oxynitride. These three inorganic substances have a strong barrier to water and oxygen, and can prevent external water and oxygen from eroding the terminals through the terminal protection layer pattern 23.
  • the material of the terminal protection layer pattern 23 may also include an organic material, which is not specifically limited in the embodiments of the present disclosure.
  • the terminal 22 may be provided in a peripheral area of the display panel, and the display structure 24 may be provided in a display area of the display panel.
  • the terminal 22 may be configured to be connected to a flip-chip film (English: Chip On Film; COF for short), and the COF may be provided with a control integrated circuit (English: integrated circuit; Abbreviation: IC).
  • an opening area k may be provided between the terminal protection layer pattern 23 and the barrier layer pattern 25.
  • the opening area k can separate the terminal protection layer pattern 23 from the barrier layer pattern 25, reduce the film layer stress, and improve the flexibility of the display panel to a certain extent.
  • the terminal 22 may include a titanium structure 223, an aluminum structure 222, and a titanium structure 221 disposed in this order.
  • the aluminum structure 222 is relatively easy to be attacked by external water and oxygen (the erosion may cause various problems such as galvanic cell corrosion, short circuit, and open circuit).
  • the two titanium structures have high stability and strong resistance to erosion, and are difficult to be affected by external water and Oxygen attack.
  • the titanium structures provided on the upper and lower sides of the aluminum structure 222 can protect the upper and lower sides of the aluminum structure 222 from being affected by other films or water and oxygen in the external environment, but the titanium structure is difficult to protect the aluminum structure 222 from being parallel to the substrate 21 Direction of side c2.
  • the side surface c2 of the aluminum structure 222 in the terminal 22 may be protected by the terminal protection layer pattern 23 covering the terminal 22.
  • the terminal 22 may be provided at the same layer as the source and drain, that is, the terminal 22 may be formed by processing the source and drain metal layers.
  • FIG. 4 is a plan view of the display panel shown in FIG. 3.
  • the terminal protection layer pattern 23 covers the edges of the terminals 22 and exposes a part of the terminals 22.
  • An opening area k is provided between the terminal protection layer pattern 23 and the barrier layer pattern 25.
  • FIG. 4 shows a case where there is an acute angle between the longitudinal direction of the first opening area a2 and the edge of the substrate 21, but an obtuse angle may exist between the longitudinal direction of the first opening area a2 and the edge of the substrate 21 , Vertical, or even parallel, the embodiments of the present disclosure are not specifically limited herein.
  • FIG. 5 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • the display panel includes three terminals 22, and the edges of each terminal 22 are covered and protected by a terminal protection layer pattern 23.
  • the number of terminals in the display panel can also be other values.
  • FIG. 6 is a schematic structural diagram of a display panel according to another embodiment of the present disclosure.
  • the base substrate 21 provided with the terminals 22 may further be provided with a flat layer protection pattern 26.
  • the flat layer protection pattern 26 may be disposed on the same layer as the flat layer pattern 27 provided on the display structure 24.
  • the flat layer protection pattern 26 includes a second shielding area a3 and a second opening area a4.
  • the orthographic projection of the second opening area a4 on the base substrate 21 is located in the orthographic projection of the terminal 22 on the base substrate 21.
  • the terminal protection layer pattern 23 is provided on the base substrate provided with the flat layer protection pattern 26.
  • the display structure 24, and the terminal protection layer pattern 23 in this embodiment reference may be made to the description of FIG. 2-5 above, and details are not described herein.
  • the flat layer protection pattern 26 is provided between the terminal protection layer pattern 23 and the terminal 22, which can further improve the protection of the side surface of the film structure of the terminal, and further avoid the electrical performance of the terminal 22. decline.
  • ILD inter-layer Dielectric
  • the terminal 22 is in contact with the gate electrode 273 through a via hole in the intermediate dielectric layer 275 and the second gate insulating layer 274.
  • the material of the gate electrode 273 may include metal molybdenum.
  • the gate electrode 273 may also be used as a part of the terminal 22.
  • both the terminals are exposed to enable the terminals to be electrically connected to the outside, and
  • the side of the terminal is prevented from being directly exposed to the external environment, and the side of the terminal is prevented from being corroded by water and oxygen in the external environment.
  • the effect of preventing a decrease in the electrical performance of the terminal is achieved.
  • FIG. 7 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present disclosure. As shown in FIG. 7, the method may include the following steps.
  • Step 701 Form a terminal on a base substrate.
  • Step 702 Form a terminal protection layer pattern on the base substrate on which the terminals are formed.
  • forming the terminal protection layer pattern may include forming a first shielding region and a first opening region, and making: the orthographic projection of the first shielding region on the substrate and the terminal on the substrate
  • the orthographic projection on the substrate has an overlapping area, and the orthographic projection of the first opening region on the base substrate is located in the orthographic projection of the terminal on the base substrate.
  • terminal and the terminal protection layer pattern in this embodiment reference may be made to the relevant details of the terminal 22 and the terminal protection layer pattern 23 described above with reference to FIGS. 2-6, and details are not described herein.
  • the manufacturing method of the display panel provided by the embodiment of the present disclosure, by forming a terminal protection layer pattern covering the edge of the terminal on the base substrate on which the terminal is formed, a part of the terminal is exposed to enable the terminal to communicate with the outside.
  • the connection prevents the side of the terminal from being directly exposed to the external environment, and prevents the side of the terminal from being attacked by water and oxygen in the external environment. Thereby, the effect of preventing the electrical performance of the terminal from being reduced is achieved.
  • FIG. 8 is a flowchart of a method for manufacturing a display panel according to another embodiment of the present disclosure. As shown in Figure 8, the method may include the following steps S801-807.
  • Step 801 A buffer layer, a first gate insulating layer, a gate, a second gate insulating layer, and an intermediate dielectric layer are sequentially formed on a base substrate, and a through hole is provided in the intermediate dielectric layer and the second gate insulating layer.
  • the buffer layer, the first gate insulating layer, the gate, the second gate insulating layer, and the intermediate dielectric layer are all conventional film layer structures in the art.
  • Step 802 Form a display structure on a base substrate.
  • the display structure is a structure for realizing a display function in a display panel.
  • the display structure may include an organic light emitting material and positive and negative electrodes disposed on both sides of the organic light emitting material.
  • the display structure can be set in a display area of a display panel.
  • Step 803 Form a terminal composed of a multilayer structure on the base substrate on which the intermediate dielectric layer is formed, and the terminal is in contact with the gate through a through hole.
  • each layer of the multilayer structure may be sequentially formed on the base substrate on which the intermediate dielectric layer is formed by a process such as a sputtering process to form a terminal, and the terminal is passed through the intermediate dielectric layer and A through hole provided in the second gate insulating layer is in contact with the gate.
  • the terminal may be provided at the same layer as the source and drain, that is, the terminal may be formed by processing the source and drain metal layers.
  • the structure of the base substrate can be as shown in FIG.
  • a buffer layer 271, a first gate insulating layer 272, a gate 273, a second gate insulating layer 274, and an intermediate dielectric layer 275 are sequentially formed.
  • the intermediate dielectric layer 275 and the second gate insulating layer 274 are disposed in There are through holes.
  • the terminal 22 is in contact with the gate electrode 237 through a through hole provided in the intermediate dielectric layer 275 and the second gate insulating layer 274.
  • a display structure may be formed first, and then a terminal may be formed; a terminal may be formed first, and then a display structure may be formed; and a terminal and a display structure may be formed at the same time.
  • Step 804 Form a flat layer on the base substrate on which the terminals and the display structure are formed.
  • the flat layer can improve the flatness of the film layer in the region where the display structure is located, so as to facilitate the subsequent formation of the film layer structure.
  • Step 805 Process the flat layer into a flat layer pattern and a flat layer protection pattern.
  • the flat layer pattern is located in the display area, and the flat layer protection pattern is configured to protect the terminals.
  • the flat layer protection pattern includes a second shielding area and a second opening area.
  • the orthographic projection of the second shielding area on the base substrate and the orthographic projection of the terminal on the base substrate overlap.
  • the second opening area is on the base substrate.
  • the orthographic projection on is located in the orthographic projection of the terminal on the base substrate.
  • the planarization layer may be processed into a planarization layer pattern and a planarization layer protection pattern through a patterning process.
  • the patterning process may include operations such as coating a photoresist, exposing the photoresist, developing the photoresist, etching, and stripping the photoresist.
  • specific implementation of the patterning process reference may be made to known related technologies, and details are not described herein again.
  • the flat layer pattern is a conventional film layer usually provided in a display panel. Therefore, in step 805, the manufacturing method of forming the flat layer pattern and the flat layer protection pattern through a single patterning process not only reduces the manufacturing process of the display panel, but also saves additional Material for making a flat layer protection pattern.
  • the structure of the substrate can be as shown in FIG.
  • a flat layer pattern 27 and a flat layer protection pattern 26 are formed on the base substrate on which the terminals 22 and the display structure 24 are formed.
  • FIG. 10 reference may be made to the related description in FIG. 9, and details are not described herein again.
  • Step 806 Form a barrier layer on the base substrate on which the protection pattern of the flat layer is formed.
  • a barrier layer may be formed on a base substrate formed with a flat-layer protection pattern by a thin film encapsulation technology.
  • a thin film encapsulation technology For the material of the barrier layer, reference may be made to the foregoing embodiments, and details are not described herein again.
  • Step 807 Process the barrier layer into a terminal protection layer pattern and a barrier layer pattern configured to protect the display structure.
  • a barrier layer may be formed on a base substrate having a flat layer protective pattern formed by a patterning process.
  • step 807 may include the following sub-steps 8071-8074.
  • Sub-step 8071 forming a photoresist layer on the base substrate on which the protective layer is formed.
  • a photoresist layer may be formed on the base substrate on which the protective layer is formed by a coating process.
  • Sub-step 8072 exposing and developing the photoresist layer to process the photoresist layer into a photoresist pattern.
  • the structure of the base substrate can be as shown in FIG.
  • a barrier layer 31 is formed on the base substrate 21 on which the flat layer pattern 27 and the flat layer protection pattern 26 are formed, and a photoresist pattern 32 is formed on the base substrate 21 on which the barrier layer 31 is formed.
  • FIG. 12 reference may be made to the related description in FIG. 9, and details are not described herein again.
  • the protective layer is processed into a barrier layer pattern and a terminal protective layer pattern by an etching process.
  • the protective layer may be processed into a barrier layer pattern and a terminal protective layer pattern by a wet-etching process or a dry-etching process.
  • Sub-step 8074 Remove the remaining photoresist pattern.
  • the remaining photoresist pattern can be peeled from the base substrate by a stripping solution.
  • the structure of the base substrate can be as shown in FIG. 6, for example.
  • the barrier layer pattern is a conventional film layer usually provided in a display panel. Therefore, in step 807, the manufacturing method of forming the barrier layer pattern and the terminal protection layer pattern through a single patterning process not only reduces the manufacturing process of the display panel, but also saves additional Material for making terminal protection layer pattern.
  • the step of manufacturing the flat layer protection pattern is an optional step, that is, the flat layer protection pattern may not be formed between the terminal and the terminal protection layer pattern.
  • the structure of the display panel formed without a flat layer protection pattern may be as shown in FIG. 3.
  • the manufacturing method of the display panel provided by the embodiment of the present disclosure, by forming a terminal protection layer pattern covering the edge of the terminal on the base substrate on which the terminal is formed, a part of the terminal is exposed to enable the terminal to communicate with the outside.
  • the connection prevents the side of the terminal from being directly exposed to the external environment, and prevents the side of the terminal from being attacked by water and oxygen in the external environment. Thereby, the effect of avoiding a decrease in the electrical performance of the terminal is achieved.
  • an embodiment of the present disclosure further provides a display device, which may include a display panel described in any one of the foregoing embodiments or examples.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种显示面板、显示面板的制造方法和显示装置。显示面板包括:衬底基板(21),衬底基板(21)上设置有端子(22)和端子保护层图案(23);端子保护层图案(23)包括第一遮挡区(a1)和第一开口区(a2),第一遮挡区(a1)在衬底基板(21)上的正投影与端子(22)在衬底基板(21)上的正投影存在重叠区域,重叠区域位于端子(22)在衬底基板(21)上的正投影的边缘,第一开口区(a2)在衬底基板(21)上的正投影位于端子(22)在衬底基板(21)上的正投影中。

Description

显示面板、显示面板的制造方法和显示装置 技术领域
本公开的实施例涉及显示面板、显示面板的制造方法和显示装置。
背景技术
显示面板通常包括衬底基板,在衬底基板上设置有端子。在显示面板制造完成后,一般需要将显示面板中的端子与外部的控制组件进行连接,以通过该控制组件对显示面板的显示功能进行控制。
发明内容
本公开的至少一个实施例提供了一种显示面板、显示面板的制造方法和显示装置,能够避免显示面板上端子内部膜层的侧面暴露在外界环境中而被外界的水氧侵蚀,因此避免了端子的电学性能的下降。
为了实现上述目的,本公开的实施例采取以下技术方案。
第一方面,本公开的实施例提供了一种显示面板,所述显示面板包括:衬底基板,所述衬底基板上设置有端子和端子保护层图案;其中,所述端子保护层图案包括第一遮挡区和第一开口区,所述第一遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述重叠区域位于所述端子在所述衬底基板上的正投影的边缘,并且所述第一开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
可选地,所述衬底基板上还设置有显示结构和阻挡层图案,所述阻挡层图案被配置为保护所述显示结构,并且所述端子保护层图案与所述阻挡层图案同层设置。
可选地,所述端子保护层图案与所述阻挡层图案之间设置有开口区域。
可选地,所述衬底基板上还设置有平坦层保护图案,所述平坦层保护图案包括第二遮挡区和第二开口区,所述第二遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,并且所述第二开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
可选地,所述端子保护层图案的材料包括氮化硅、氧化硅和氮氧化硅中的一个。
可选地,所述端子保护层的材料包括有机材料。
可选地,所述端子为多层结构。
可选地,所述端子包括沿远离所述衬底基板的方向依次设置的钛结构、铝结构和钛结构。
可选地,所述衬底基板上依次设置有缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层,所述中间介电层和所述第二栅绝缘层中设置有通孔;所述端子通过所述通孔与所述栅极接触。
第二方面,本公开的实施例还提供了一种显示面板的制造方法,所述方法包括:在衬底基板上形成端子;以及在形成有所述端子的衬底基板上形成端子保护层图案,其中,形成所述端子保护层图案包括:形成第一遮挡区和第一开口区,使得所述第一遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述重叠区域位于所述端子在所述衬底基板上的正投影的边缘,并且使得所述第一开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
可选地,所述在形成有所述端子的衬底基板上形成端子保护层图案之前,所述方法还包括:在所述衬底基板上形成显示结构。所述在形成有所述端子的衬底基板上形成端子保护层图案包括:在形成有所述显示结构和所述端子的衬底基板上形成阻挡层;以及将所述阻挡层加工为阻挡层图案和所述端子保护层图案,其中,所述阻挡层图案被配置为保护所述显示结构。
可选地,所述将所述阻挡层加工为阻挡层图案和所述端子保护层图案包括:在形成有所述阻挡层的衬底基板上形成光刻胶层;对所述光刻胶层进行曝光与显影,以将所述光刻胶层加工为光刻胶图案;通过刻蚀工艺将所述阻挡层加工为所述阻挡层图案和所述端子保护层图案;以及去除剩余的所述光刻胶图案。
可选地,在所述在形成有所述端子的衬底基板上形成端子保护层图案之前,所述方法还包括:在形成有所述端子的衬底基板上形成平坦层保护图案,所述平坦层保护图案包括第二遮挡区和第二开口区,所述第二遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述第二开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。所述在形成有所述端子的衬底基板上形成端子保护层图案包括:在形成有所述平坦层保护图案的衬底基板上形成所述端子保护层图案。
可选地,在所述在衬底基板上形成端子之前,所述方法还包括:在所述衬底基板上依次形成缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层,所述中间介电层和所述第二栅绝缘层中设置有通孔。所述在衬底基板上形成端子包括:在形成有所述中间介电层的衬底基板上形成所述端子,所述端子通过所述通孔与所述栅极接触。
第三方面,本公开的实施例还提供了一种显示装置,所述显示装置包括第一方面所述的显示面板。
附图说明
为了更清楚地说明本发明实施例中的技术方案,下面将对实施例描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。附图中:
图1是一种阵列基板的结构示意图;
图2是本公开一实施例提供的一种显示面板的结构示意图;
图3是本公开另一实施例提供的一种显示面板的结构示意图;
图4是图3所示的显示面板的俯视图;
图5是本公开又一实施例提供的一种显示面板的结构示意图;
图6是本公开再一实施例提供的一种显示面板的结构示意图;
图7是本公开一实施例提供的一种显示面板的制造方法的流程图;
图8是本公开另一实施例提供的一种显示面板的制造方法的流程图;
图9是图8所示实施例中衬底基板的一个示例的结构示意图;
图10是图8所示实施例中衬底基板的另一个示例的结构示意图;
图11是图8所示实施例中形成阻挡层图案和端子保护层图案的示意图;以及
图12是图8所示实施例中衬底基板的再一个示例的结构示意图。
具体实施方式
为使本发明的实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例的附图对本发明的实施例的技术方案进行清楚、完整的描述。显然,所描述的实施例仅是本发明的一部分示例性实施例,而不是全部的实施 例。基于所描述的本发明的示例性实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其它实施例都属于本发明的保护范围。
除非另作定义,此处使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。同样,“一个”、“一”或者“该”等类似词语也不表示数量限制,而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
图1是一种阵列基板的结构示意图。如图1所示,该阵列基板包括衬底基板11,该衬底基板11上设置有端子12。端子12包括膜层结构122和端子保护层121。端子保护层121设置在该膜层结构122远离衬底基板的一侧c1,该保护层121能够避免膜层结构122远离衬底基板11的一侧c1直接暴露在外界环境中而发生氧化等问题。
但是,端子12中膜层结构122的侧面c2仍会暴露在外界环境中。该侧面c2被外界的水氧侵蚀后会导致端子12的电学性能的下降。
本公开的至少一个实施例提供了一种显示面板、显示面板的制造方法和显示装置,能够解决上述阵列基板中存在的问题。
图2是本公开一实施例提供的一种显示面板的结构示意图。如图2所示,该显示面板可以包括衬底基板21。衬底基板21上设置有端子22。设置有端子22的衬底基板21上设置有端子保护层图案23。端子保护层图案23包括第一遮挡区a1和第一开口区a2,第一遮挡区a1在衬底基板21上的正投影(图2中未标出)与端子22在衬底基板上的正投影(图2中未标出)存在重叠区域,该重叠区域位于端子22在衬底基板21上的正投影的边缘。第一开口区a2在衬底基板21上的正投影(图2中未标出)位于端子22在衬底基板21上的正投影(图2中未标出)中。
综上所述,本公开实施例提供的显示面板中,通过在设置有端子的衬底基板上设置覆盖端子边缘的端子保护层图案,既露出了部分端子以使端子能够与外部电连接,又防止了端子的侧面直接暴露在外部环境中,避免了端子 的侧面被外部环境中的水氧侵蚀。由此,解决了端子内部膜层的侧面仍会暴露在外界环境中并容易被外界的水氧侵蚀后从而导致端子的电学性能下降的问题,实现了避免端子的电学性能下降的效果。
图3为本公开另一实施例提供的一种显示面板的结构示意图。与图2所示实施例不同的是,图3所示实施例中的该显示面板还包括显示结构和阻挡层图案。
如图3所示,可选地,衬底基板11上还设置有显示结构24。该显示结构可以是被配置为实现显示功能的结构。根据显示面板的种类的不同,该显示结构也可以不同。示例性地,当显示面板为有机发光二级管(英文:Organic Light-Emitting Diode;简称:OLED)显示面板时,该显示结构可以是包括有机发光结构的显示结构。
如图3所示,可选地,设置有显示结构24和端子22的衬底基板21上还可设置有阻挡层图案25,其被配置为保护该显示结构24。该阻挡层图案25可与前述端子保护层图案23同层设置。该阻挡层图案25可以是通过薄膜封装(英文:Thin Film Encapsulation;简称:TFE)技术形成的保护结构,该保护结构可以包括单层无机膜,或包括多层复合的无机膜,或包括多层复合的无机膜和有机膜。
可选地,被配置为保护端子22的端子保护层图案23可以和被配置为保护显示结构24的阻挡层图案25同层设置,如此能够降低整个显示面板的厚度。
可选地,端子保护层图案23的材料可包括氮化硅、氧化硅或氮氧化硅。这三种无机物对于水和氧的阻挡能力较强,能够避免外部的水和氧透过端子保护层图案23侵蚀端子。此外,端子保护层图案23的材料也可以包括有机材料,本公开的实施例对此不进行具体限制。
可选地,端子22可以设置在显示面板中的***区域,而显示结构24可以设置在显示面板的显示区域中。端子22可以被配置为与覆晶薄膜(英文:Chip On Film;简称:COF)连接,该COF上可以设置有控制集成电路(英文:integrated circuit;简称:IC)。
如图3所示,可选地,端子保护层图案23与阻挡层图案25之间可设置有开口区域k。该开口区域k能够使端子保护层图案23与阻挡层图案25分离,降低膜层应力,且在一定程度上提高显示面板的柔韧性。
如图3所示,可选地,端子22可以包括依次设置的钛结构223、铝结构222和钛结构221。铝结构222较容易被外界的水和氧侵蚀(该侵蚀可能造成原电池腐蚀、短路和断路等各种问题),两个钛结构的稳定性高,抗侵蚀能力强,难以被外界的水和氧侵蚀。设置在铝结构222上下两侧的钛结构能够保护铝结构222的上下两侧不被其他膜层或外界环境中的水和氧影响,但是钛结构难以保护铝结构222在平行于衬底基板21的方向上的侧面c2。在本公开的实施例中,端子22中铝结构222的该侧面c2可以由覆盖在端子22上的端子保护层图案23来保护。
可选地,端子22可以与源漏极同层设置,即:端子22可以由源漏极金属层加工形成。
图4为图3所示的显示面板的俯视图。如图4所示,端子保护层图案23覆盖在端子22的边缘,且使部分端子22露出。端子保护层图案23和阻挡层图案25之间设置有开口区域k。图4示出的是第一开口区域a2的长度方向与衬底基板21的边缘存在锐角夹角的情况,但第一开口区域a2的长度方向还可以与衬底基板21的边缘存在钝角夹角、垂直甚或平行,本公开的实施例在此不做具体限制。
可选地,显示面板中可以包括多个端子。图5为本公开又一实施例提供的一种显示面板的结构示意图。在本实施例中,显示面板中包括3个端子22,并且每个端子22的边缘均由端子保护层图案23进行覆盖保护。本领域技术人员应理解的是,显示面板中端子的数量也可为其他数值。
图6为本公开再一实施例提供的一种显示面板的结构示意图。如图6所示,设置有端子22的衬底基板21上还可设置有平坦层保护图案26。可选地,该平坦层保护图案26可以和设置在显示结构24上的平坦层图案27同层设置。
如图6所示,可选地,平坦层保护图案26包括第二遮挡区a3和第二开口区a4,第二遮挡区a3在衬底基板21上的正投影与端子22在衬底基板21上的正投影存在重叠区域,第二开口区a4在衬底基板21上的正投影位于端子22在衬底基板21上的正投影中。
在此情况下,端子保护层图案23设置在设置有平坦层保护图案26的衬底基板上。本实施例中的端子22、显示结构24和端子保护层图案23可参照上文中关于图2-5的描述,在此不做赘述。
如上所述,本公开的实施例在端子保护层图案23和端子22之间设置平坦层保护图案26,能够进一步提高对端子内膜层结构的侧面的保护,进一步避免了端子22的电学性能的下降。
如图6所示,可选地,衬底基板21上可依次设置有缓冲层(buffer layer)271、第一栅绝缘层272、栅极273、第二栅绝缘层274和中间介电层(英文:inter-layer Dielectric;简称:ILD)275;中间介电层275和第二栅绝缘层274上可设置有通孔。
在此情况下,端子22通过中间介电层275和第二栅绝缘层274中的通孔与栅极273接触。栅极273的材料可以包括金属钼。可选地,栅极273也可以作为端子22的一部分。
综上所述,在本公开实施例提供的显示面板中,通过在设置有端子的衬底基板上设置覆盖端子边缘的端子保护层图案,既露出了部分端子使端子能够与外部电连接,又防止了端子的侧面直接暴露在外部环境中,避免了端子的侧面被外部环境中的水氧侵蚀。由此,实现了防止端子电学性能下降的效果。
图7是本公开一实施例提供的一种显示面板的制造方法的流程图。如图7所示,该方法可以包括以下步骤。
步骤701、在衬底基板上形成端子。
步骤702、在形成有端子的衬底基板上形成端子保护层图案。
根据本公开的实施例,在步骤702中,形成端子保护层图案可包括形成第一遮挡区和第一开口区,并且使得:第一遮挡区在衬底基板上的正投影与端子在衬底基板上的正投影存在重叠区域,第一开口区在衬底基板上的正投影位于端子在衬底基板上的正投影中。
本实施例中的端子和端子保护层图案可参照上文中关于图2-6描述的端子22和端子保护层图案23的相关细节,在此不做赘述。
综上所述,在本公开实施例提供的显示面板的制造方法中,通过在形成有端子的衬底基板上形成覆盖端子边缘的端子保护层图案,既露出了部分端子使端子能够与外部电连接,又防止了端子的侧面直接暴露在外部环境中,避免了端子的侧面被外部环境中的水氧侵蚀。由此,实现了防止端子的电学性能下降的效果。
图8是本公开另一实施例提供的一种显示面板的制造方法的流程图。如 图8所示,该方法可以包括以下步骤S801-807。
步骤801、在衬底基板上依次形成缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层,并且在中间介电层和第二栅绝缘层中设置有通孔。
缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层均为本领域的常规膜层结构,这些膜层结构的形成方式以及材料可以参考已知相关技术,在此不再赘述。
步骤802、在衬底基板上形成显示结构。
该显示结构为显示面板中用于实现显示功能的结构。示例性地,当显示面板为OLED显示面板时,该显示结构可以包括有机发光材料以及设置在该有机发光材料两侧的正负电极。该显示结构可以设置在显示面板的显示区域。显示结构的材料和形成工艺可以参考已知相关技术,在此不再赘述。
步骤803、在形成有中间介电层的衬底基板上形成由多层结构构成的端子,端子通过通孔与栅极接触。
可选地,可以通过溅镀工艺等工艺、在形成有中间介电层的衬底基板上依次形成多层结构中的每一层结构,以构成端子,并且使该端子通过中间介电层和第二栅绝缘层中设置的通孔与栅极接触。
可选地,端子可以与源漏极同层设置,即:端子可以由源漏极金属层加工形成。
步骤803结束时,衬底基板的结构可以如图9所示。衬底基板21上依次形成有缓冲层271、第一栅绝缘层272、栅极273、第二栅绝缘层274和中间介电层275,中间介电层275和第二栅绝缘层274中设置有通孔。端子22通过中间介电层275和第二栅绝缘层274中设置的通孔与栅极237接触。
本公开的实施例不对显示结构和端子的形成顺序进行限定。例如,可以先形成显示结构,再形成端子;也可以先形成端子,再形成显示结构;还可以同时形成端子和显示结构。
步骤804、在形成有端子和显示结构的衬底基板上形成平坦层。
该平坦层可提高显示结构所在区域膜层的平整程度,以便于后续膜层结构的形成。
步骤805、将平坦层加工为平坦层图案和平坦层保护图案。
平坦层图案位于显示区域,而平坦层保护图案被配置为保护端子。该平坦层保护图案包括第二遮挡区和第二开口区,第二遮挡区在衬底基板上的正 投影与端子在衬底基板上的正投影存在重叠区域,第二开口区在衬底基板上的正投影位于端子在衬底基板上的正投影中。
例如,可以通过构图工艺将平坦层加工为平坦层图案和平坦层保护图案。构图工艺可以包括涂覆光刻胶、曝光光刻胶、对光刻胶显影、刻蚀和剥离光刻胶等操作。构图工艺的具体实施可以参考已知相关技术,在此不再赘述。
平坦层图案为显示面板中通常设置的常规膜层,因而在步骤805中,通过一次构图工艺形成平坦层图案和平坦层保护图案的制造方式不但减少了显示面板的制造工序,而且还节省了额外制造平坦层保护图案的材料。
步骤805结束时,衬底基板的结构可以如图10所示。形成有端子22和显示结构24的衬底基板上形成有平坦层图案27和平坦层保护图案26。图10中的其他结构可以参考图9的相关描述,在此不再赘述。
步骤806、在形成有平坦层保护图案的衬底基板上形成阻挡层。
例如,可以通过薄膜封装技术在形成有平坦层保护图案的衬底基板上形成阻挡层。该阻挡层的材料可以参考前述实施例,在此不再赘述。
步骤807、将阻挡层加工为端子保护层图案和被配置为保护显示结构的阻挡层图案。
例如,可以通过构图工艺在形成有平坦层保护图案的衬底基板上形成阻挡层。
例如,如图11所示,步骤807可以包括以下子步骤8071-8074。
子步骤8071、在形成有保护层的衬底基板上形成光刻胶层。
例如,可以通过涂覆工艺在形成有保护层的衬底基板上形成光刻胶层。
子步骤8072、对光刻胶层进行曝光与显影,以将光刻胶层加工为光刻胶图案。
子步骤8072结束时,衬底基板的结构可以如图12所示。形成有平坦层图案27以及平坦层保护图案26的衬底基板21上形成有阻挡层31,形成有阻挡层31的衬底基板21上形成有光刻胶图案32。图12中的其他结构可以参考图9的相关描述,在此不再赘述。
子步骤8073、通过刻蚀工艺将保护层加工为阻挡层图案和端子保护层图案。
例如,可以通过湿刻工艺或干刻工艺将保护层加工为阻挡层图案和端 子保护层图案。
子步骤8074、去除剩余的光刻胶图案。
例如,可以通过剥离液来将剩余的光刻胶图案从衬底基板上剥离。
子步骤8074结束时,衬底基板的结构例如可以如图6所示。
阻挡层图案为显示面板中通常设置的常规膜层,因而在步骤807中,通过一次构图工艺形成阻挡层图案和端子保护层图案的制造方式不但减少了显示面板的制造工序,而且还节省了额外制造端子保护层图案的材料。
本公开实施例提供的显示面板的制造方法中,制造平坦层保护图案的步骤为可选的步骤,即:可以不在端子和端子保护层图案之间形成该平坦层保护图案。相应地,形成的不包含平坦层保护图案的显示面板的结构可以如图3所示。
综上所述,在本公开实施例提供的显示面板的制造方法中,通过在形成有端子的衬底基板上形成覆盖端子边缘的端子保护层图案,既露出了部分端子使端子能够与外部电连接,又防止了端子的侧面直接暴露在外部环境中,避免了端子的侧面被外部环境中的水氧侵蚀。由此,实现了避免端子的电学性能下降的效果。
此外,本公开一实施例还提供一种显示装置,该显示装置可包括前述任一实施例或示例中描述的显示面板。
以上所述,仅为本公开的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。
本申请要求于2018年6月8日递交的中国专利申请第201810585220.3号的优先权,在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。

Claims (15)

  1. 一种显示面板,包括:
    衬底基板,所述衬底基板上设置有端子和端子保护层图案;
    其中,所述端子保护层图案包括第一遮挡区和第一开口区,所述第一遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述重叠区域位于所述端子在所述衬底基板上的正投影的边缘,并且所述第一开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
  2. 根据权利要求1所述的显示面板,其中,所述衬底基板上还设置有显示结构和阻挡层图案,
    所述阻挡层图案被配置为保护所述显示结构,并且所述端子保护层图案与所述阻挡层图案同层设置。
  3. 根据权利要求2所述的显示面板,其中,所述端子保护层图案与所述阻挡层图案之间设置有开口区域。
  4. 根据权利要求1所述的显示面板,其中,所述衬底基板上还设置有平坦层保护图案,
    所述平坦层保护图案包括第二遮挡区和第二开口区,所述第二遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,并且所述第二开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
  5. 根据权利要求1所述的显示面板,其中,所述端子保护层图案的材料包括氮化硅、氧化硅和氮氧化硅中的一个。
  6. 根据权利要求1所述的显示面板,其中,所述端子保护层的材料包括有机材料。
  7. 根据权利要求1所述的显示面板,其中,所述端子为多层结构。
  8. 根据权利要求7所述的显示面板,其中,所述端子包括沿远离所述衬底基板的方向依次设置的钛结构、铝结构和钛结构。
  9. 根据权利要求1-8中任一项所述的显示面板,其中,所述衬底基板上依次设置有缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层,所述中间介电层和所述第二栅绝缘层中设置有通孔;
    所述端子通过所述通孔与所述栅极接触。
  10. 一种显示面板的制造方法,包括:
    在衬底基板上形成端子;以及
    在形成有所述端子的衬底基板上形成端子保护层图案,
    其中,形成所述端子保护层图案包括:形成第一遮挡区和第一开口区,使得所述第一遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述重叠区域位于所述端子在所述衬底基板上的正投影的边缘,并且使得所述第一开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中。
  11. 根据权利要求10所述的制造方法,其中,所述在形成有所述端子的衬底基板上形成端子保护层图案之前,所述方法还包括:
    在所述衬底基板上形成显示结构;
    所述在形成有所述端子的衬底基板上形成端子保护层图案包括:
    在形成有所述显示结构和所述端子的衬底基板上形成阻挡层;以及
    将所述阻挡层加工为阻挡层图案和所述端子保护层图案,
    其中,所述阻挡层图案被配置为保护所述显示结构。
  12. 根据权利要求11所述的制造方法,其中,所述将所述阻挡层加工为阻挡层图案和所述端子保护层图案包括:
    在形成有所述阻挡层的衬底基板上形成光刻胶层;
    对所述光刻胶层进行曝光与显影,以将所述光刻胶层加工为光刻胶图 案;
    通过刻蚀工艺将所述阻挡层加工为所述阻挡层图案和所述端子保护层图案;以及
    去除剩余的所述光刻胶图案。
  13. 根据权利要求10所述的制造方法,其中,在所述在形成有所述端子的衬底基板上形成端子保护层图案之前,所述方法还包括:
    在形成有所述端子的衬底基板上形成平坦层保护图案,所述平坦层保护图案包括第二遮挡区和第二开口区,所述第二遮挡区在所述衬底基板上的正投影与所述端子在所述衬底基板上的正投影存在重叠区域,所述第二开口区在所述衬底基板上的正投影位于所述端子在所述衬底基板上的正投影中;
    所述在形成有所述端子的衬底基板上形成端子保护层图案包括:
    在形成有所述平坦层保护图案的衬底基板上形成所述端子保护层图案。
  14. 根据权利要求10-13中任一项所述的制造方法,其中,在所述在衬底基板上形成端子之前,所述方法还包括:
    在所述衬底基板上依次形成缓冲层、第一栅绝缘层、栅极、第二栅绝缘层和中间介电层,所述中间介电层和所述第二栅绝缘层中设置有通孔;
    所述在衬底基板上形成端子包括:
    在形成有所述中间介电层的衬底基板上形成所述端子,所述端子通过所述通孔与所述栅极接触。
  15. 一种显示装置,包括如权利要求1-9中任一项所述的显示面板。
PCT/CN2019/083277 2018-06-08 2019-04-18 显示面板、显示面板的制造方法和显示装置 WO2019233198A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/610,202 US11562973B2 (en) 2018-06-08 2019-04-18 Display panel, manufacturing method of display panel, and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810585220.3A CN108550588B (zh) 2018-06-08 2018-06-08 显示面板、显示面板的制造方法和显示装置
CN201810585220.3 2018-06-08

Publications (1)

Publication Number Publication Date
WO2019233198A1 true WO2019233198A1 (zh) 2019-12-12

Family

ID=63492468

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2019/083277 WO2019233198A1 (zh) 2018-06-08 2019-04-18 显示面板、显示面板的制造方法和显示装置

Country Status (3)

Country Link
US (1) US11562973B2 (zh)
CN (1) CN108550588B (zh)
WO (1) WO2019233198A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970484A (zh) * 2019-12-20 2020-04-07 京东方科技集团股份有限公司 显示基板及显示装置

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108550588B (zh) 2018-06-08 2021-03-30 京东方科技集团股份有限公司 显示面板、显示面板的制造方法和显示装置
CN110676217B (zh) 2019-10-09 2021-12-10 京东方科技集团股份有限公司 显示面板及其制造方法、显示装置
KR20210052741A (ko) * 2019-10-31 2021-05-11 삼성디스플레이 주식회사 표시장치
EP4095920A4 (en) * 2020-01-22 2023-01-25 BOE Technology Group Co., Ltd. DISPLAY PANEL AND DISPLAY DEVICE
CN112864340B (zh) * 2021-01-26 2022-10-28 苏州清越光电科技股份有限公司 一种显示面板、显示面板制备方法及显示装置
CN113161396B (zh) * 2021-03-19 2023-05-02 京东方科技集团股份有限公司 一种显示基板、其制作方法及显示装置
CN113725231B (zh) * 2021-08-20 2024-06-21 京东方科技集团股份有限公司 一种显示面板及其制备方法、掩模板及显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1504818A (zh) * 2002-11-15 2004-06-16 Nec液晶技术株式会社 液晶显示装置的制造方法
JP2007036006A (ja) * 2005-07-28 2007-02-08 Hitachi Ltd 有機薄膜トランジスタ及びその製造方法
CN103137630A (zh) * 2011-11-30 2013-06-05 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN107910365A (zh) * 2017-10-25 2018-04-13 南京中电熊猫液晶显示科技有限公司 一种薄膜晶体管及其制造方法
CN108550588A (zh) * 2018-06-08 2018-09-18 京东方科技集团股份有限公司 显示面板、显示面板的制造方法和显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI450653B (zh) * 2012-12-06 2014-08-21 Wintek Corp 接墊結構
CN107579040B (zh) * 2017-09-07 2020-04-21 京东方科技集团股份有限公司 一种掩膜版、阵列基板及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1504818A (zh) * 2002-11-15 2004-06-16 Nec液晶技术株式会社 液晶显示装置的制造方法
JP2007036006A (ja) * 2005-07-28 2007-02-08 Hitachi Ltd 有機薄膜トランジスタ及びその製造方法
CN103137630A (zh) * 2011-11-30 2013-06-05 三星显示有限公司 薄膜晶体管阵列基板、其制造方法以及有机发光显示设备
CN107910365A (zh) * 2017-10-25 2018-04-13 南京中电熊猫液晶显示科技有限公司 一种薄膜晶体管及其制造方法
CN108550588A (zh) * 2018-06-08 2018-09-18 京东方科技集团股份有限公司 显示面板、显示面板的制造方法和显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110970484A (zh) * 2019-12-20 2020-04-07 京东方科技集团股份有限公司 显示基板及显示装置

Also Published As

Publication number Publication date
CN108550588A (zh) 2018-09-18
CN108550588B (zh) 2021-03-30
US11562973B2 (en) 2023-01-24
US20210366850A1 (en) 2021-11-25

Similar Documents

Publication Publication Date Title
WO2019233198A1 (zh) 显示面板、显示面板的制造方法和显示装置
WO2017054384A1 (zh) 一种阵列基板及其制作方法、显示面板
US10916568B2 (en) Manufacturing method of display substrate, array substrate and display device
WO2016119324A1 (zh) 阵列基板及其制作方法、显示装置
US8748320B2 (en) Connection to first metal layer in thin film transistor process
US20140091390A1 (en) Protection Layer for Halftone Process of Third Metal
WO2015149482A1 (zh) 阵列基板及其制作方法、显示装置
US20230317826A1 (en) Method for manufacturing thin film transistor, and thin film transistor
US9905592B2 (en) Method for manufacturing TFT, array substrate and display device
WO2016078169A1 (zh) 薄膜晶体管的制造方法
JP5991668B2 (ja) 表示装置及びその製造方法
US9978777B2 (en) Display device including thin film transistor array panel and manufacturing method thereof
US11710747B2 (en) Array substrate, manufacturing method thereof, and display device
WO2018058522A1 (zh) 薄膜晶体管制造方法及阵列基板
US10818798B2 (en) Display panel, array substrate, thin film transistor and method for manufacturing the same
WO2019210776A1 (zh) 阵列基板、显示装置、薄膜晶体管及阵列基板的制作方法
US11139324B2 (en) Method of manufacturing array substrate and display panel
US9142654B2 (en) Manufacturing method of oxide semiconductor thin film transistor
US9673228B2 (en) Display panel
WO2018094598A1 (zh) 阵列基板的制造方法
WO2016145758A1 (zh) 显示基板及其制备方法
JP6255452B2 (ja) 表示装置及びその製造方法
TWI550725B (zh) 薄膜電晶體基板製作方法
KR20160017868A (ko) 표시장치와 그 제조 방법
JP2002334885A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 19814799

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 26.04.2021)

122 Ep: pct application non-entry in european phase

Ref document number: 19814799

Country of ref document: EP

Kind code of ref document: A1