WO2015149482A1 - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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WO2015149482A1
WO2015149482A1 PCT/CN2014/086301 CN2014086301W WO2015149482A1 WO 2015149482 A1 WO2015149482 A1 WO 2015149482A1 CN 2014086301 W CN2014086301 W CN 2014086301W WO 2015149482 A1 WO2015149482 A1 WO 2015149482A1
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Prior art keywords
transparent electrode
pattern
photoresist
drain
insulating spacer
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PCT/CN2014/086301
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English (en)
French (fr)
Inventor
白金超
丁向前
刘耀
李梁梁
郭总杰
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US14/436,843 priority Critical patent/US10014329B2/en
Publication of WO2015149482A1 publication Critical patent/WO2015149482A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • Embodiments of the present invention relate to an array substrate, a method of fabricating the same, and a display device.
  • the advanced Super Dimension Switch (ADS) display mode has been widely developed due to its superior display quality, and has become an important technical standard in the world.
  • the H-ADS (High Open Rate ADS) mode is the most advanced technology. One.
  • At least one embodiment of the present invention provides a method of fabricating an array substrate, comprising: forming a pattern including a gate electrode, a gate line, a common electrode line, and a gate insulating layer on a base substrate; forming a data line, a source, and a drain a pattern of the electrode and the active layer; forming a pattern including an insulating spacer layer on the pattern of the source, the drain, and the active layer; forming a pattern including the first transparent electrode on the insulating spacer layer; Forming a pattern including a passivation layer over the first transparent electrode; and forming a pattern including the second transparent electrode over the passivation layer.
  • forming the pattern of the insulating spacer layer and the pattern of the first transparent electrode include: applying a photoresist on the insulating spacer layer; exposing and developing the photoresist by using a double-tuned mask The photoresist corresponding to the region where the drain pattern is located partially retains the photoresist corresponding to the region where the first transparent electrode pattern is located, completely retains the photoresist of other regions; and etches the exposed insulating spacer layer to form the a first via hole for exposing the drain; activating the photoresist to remove a photoresist corresponding to a region where the first transparent electrode pattern is located, and retaining light other than the first transparent electrode and the first via region The first transparent conductive film is formed, and the remaining photoresist and the first transparent conductive film thereon are peeled off to form a first transparent electrode, and the drain is connected through the first via.
  • a second via hole is formed on a region of the passivation layer corresponding to a pattern of a common electrode line; And a transparent electrode, wherein the second transparent electrode is connected to the common electrode line through the second via.
  • forming the pattern of the insulating spacer layer and the pattern of the first transparent electrode include: applying a photoresist on the insulating spacer layer; exposing and developing the photoresist by using a double-tuned mask to remove the common The photoresist corresponding to the region where the electrode line pattern is located, and the first transparent electrode pattern portion is retained a photoresist corresponding to the region, completely retaining photoresist of other regions; etching the exposed insulating spacer layer to form the first via hole to expose the common electrode line; ashing the photoresist, Removing the photoresist corresponding to the region where the first transparent electrode pattern is located, leaving the photoresist other than the first transparent electrode and the first via region; and forming the first transparent conductive film, and stripping the remaining photoresist and being located thereon a first transparent conductive film thereon to form a first transparent electrode, and the common electrode line is connected through the first via.
  • the method further includes: performing a hydrogen plasma process to process the source and drain before forming a pattern including an insulating spacer layer over the pattern of the source, drain, and active layers. The channel region formed between.
  • forming the pattern of the insulating spacer layer and the pattern of the first transparent electrode includes: applying a photoresist on the insulating spacer layer; exposing and developing the photoresist using a mask, removing part of the a photoresist corresponding to a region where the drain pattern is located and a region where the first transparent electrode pattern is located, completely retaining photoresist of other regions; etching away all of the exposed insulating spacer layers; forming a first transparent conductive film, and stripping The remaining photoresist and the first transparent conductive film thereon are formed to form the first transparent electrode.
  • a via hole is formed through the passivation layer and the insulating spacer layer in a region corresponding to the pattern of the common electrode line; and the second transparent electrode is connected to the common electrode through the via hole line.
  • the first transparent electrode is between the gate insulating layer, the drain, and the passivation layer.
  • performing a hydrogen plasma process to process a channel region formed between the source and the drain .
  • At least one embodiment of the present invention also provides an array substrate comprising: a gate line formed on a base substrate, a data line, a common electrode line, a thin film transistor including a source, a drain, and an active layer, a transparent electrode, a passivation layer formed on the first transparent electrode, and a second transparent electrode, forming an insulation interval between the active layer of the thin film transistor and a layer where the first transparent electrode is located a layer, the insulating spacer layer is formed with a first via hole, and a second via hole is formed on the passivation layer; Wherein the first transparent electrode is connected to the drain of the thin film transistor through the first via, and the second transparent electrode is connected to the common electrode line through the second via; or the first The transparent electrode is connected to the common electrode line through the first via, and the second transparent electrode is connected to a drain of the thin film transistor through the second via.
  • the material of the insulating spacer layer is silicon nitride.
  • the thickness of the insulating spacer layer is
  • At least one embodiment of the present invention also provides an array substrate comprising: a gate line formed on a base substrate, a data line, a common electrode line, a thin film transistor including a source, a drain, and an active layer, a transparent electrode, a passivation layer formed on the first transparent electrode, and a second transparent electrode, forming an insulation interval between the active layer of the thin film transistor and a layer where the first transparent electrode is located a via, and a via formed over the common electrode line through the insulating spacer layer and the passivation layer; the first transparent electrode being located at the gate insulating layer and the drain and the blunt Between the layers, and connected to the drain, the second transparent electrode is connected to the common electrode line through the via.
  • the material of the insulating spacer layer is silicon nitride, and the thickness of the insulating spacer layer is
  • a display device including any of the array substrates described above is provided.
  • 1a-1e are schematic flow diagrams showing respective structures for forming an array substrate in an array substrate manufacturing method
  • FIG. 2a is a schematic structural view of a substrate for forming a TFT in an array substrate manufacturing method according to an embodiment of the present invention
  • FIG. 2b is a schematic structural view of a substrate on which an insulating spacer layer is formed on the basis of FIG. 2a;
  • FIG. 2c is a schematic structural view of a substrate after forming a photoresist on the basis of FIG. 2b and exposing and developing;
  • FIG. 2d is a schematic structural view of a substrate after forming a first via hole on the insulating spacer layer and aashing the photoresist on the basis of FIG. 2c;
  • FIG. 2e is a schematic structural view of a substrate on which a first transparent conductive film is formed on the basis of FIG. 2d;
  • FIG. 2f is a schematic structural view of a substrate on which a first transparent electrode is formed on the basis of FIG. 2e;
  • 2g is a schematic structural view of an array substrate fabricated by using the array substrate manufacturing method of the embodiment of the invention.
  • FIG. 3 is a schematic structural view of another array substrate fabricated by the method for fabricating an array substrate according to another embodiment of the present invention.
  • FIGS. 4a-4h are schematic structural views of still another array substrate fabricated by the method of fabricating an array substrate according to a third embodiment of the present invention.
  • FIG. 1a-1e The process flow for the preparation of the H-ADS display mode thin film transistor (TFT) array substrate is shown in Figures 1a-1e.
  • a gate electrode 120, a gate line (not shown), and a common electrode line 130 (first mask process) are formed on the base substrate 110; a gate insulating layer 140 is formed; an active layer 150 is formed; and a data line is formed (Fig. Not shown), source 161 and drain 162 (1 mask process); forming first transparent electrode 170 (1 mask process); forming passivation layer 180 and vias thereon (1 time mask) Mold process); forming a second transparent electrode 190 (1 mask process).
  • the inventors have noticed the following problems. As shown in FIGS. 1a-1e, in the process of forming the first transparent electrode 170, the source 161 and the drain 162 are completed, and the TFT channel is as shown in FIG. 1c. All shown in the dashed box) will be exposed to the outside.
  • the material of the first transparent electrode 170 is usually ITO (indium tin oxide), which will introduce impurities into the TFT channel during deposition, causing channel contamination of the TFT.
  • the residual ITO etching solution and the residual ITO in the channel may also cause TFT channel contamination.
  • the TFT channel determines the characteristics of the TFT, and the TFT channel contamination causes abnormal TFT characteristics and affects product performance.
  • the passivation layer 180 deposition (PVX Dep) is generally not processed by H 2 Plasma, thereby causing a high I off of the TFT, which affects product quality.
  • the method for fabricating an array substrate according to an embodiment of the present invention includes:
  • Step 1 as shown in FIG. 2a, a pattern including a gate line (not shown), a gate electrode 220, a common electrode line 230, and a gate insulating layer 240 is formed on the base substrate 210, wherein the gate electrode 220 and the gate line are formed.
  • the common electrode line 230 is formed in the same patterning process, requiring only one mask.
  • a gate insulating layer 240 is formed over the gate lines, the gate electrodes 220, and the common electrode lines 230.
  • a pattern including the active layer 250, the data lines (not shown), the source 261, and the drain 262 is formed.
  • a pattern of the active layer 250, the data lines (not shown), the source 261, and the drain 262 is formed over the gate insulating layer 240.
  • the gate 220, the gate insulating layer 240, the active layer 250, the source 261, and the drain 262 form a thin film transistor (TFT), and the source 261 and the drain 262 are between the channel regions of the TFT.
  • TFT thin film transistor
  • the data line, source 261 and drain 262 are formed in the same patterning process.
  • an insulating spacer layer 300 is formed over the pattern of the source electrode 261, the drain electrode 262, and the active layer 250, and may be formed by deposition, sputtering, or coating. Since the insulating spacer 300 is intended to protect the first transparent electrode from being formed by the residual influence on the channel, the insulating spacer 300 may cover only the region where the TFT is located, or may cover the entire substrate surface, thereby covering the channel of the TFT. It is protected in a later process.
  • the insulating spacer 300 may be made of a silicon nitride material, and the thickness may be Such a thickness can protect the channel of the TFT, and the thickness of the entire array substrate is not too thick, thereby ensuring the lightness and thinness of the display device.
  • a pattern including the first transparent electrode is formed on the insulating spacer 300.
  • the first transparent electrode is connected to the drain of the thin film transistor through the first via, that is, the first transparent electrode is a pixel electrode.
  • a photoresist 400 is applied over the insulating spacer 300.
  • the photoresist 400 is exposed and developed by using a double-adjusting mask (half-tone mask or gray-tone mask), and the photoresist of the corresponding region A of the drain 262 of the thin film transistor is removed, and the first transparent electrode is partially retained.
  • the photoresist of the region B completely retains the photoresist of other regions, that is, the thickness of the photoresist of the corresponding region B of the first transparent electrode is small. The thickness of the photoresist in other areas.
  • the exposed insulating spacer 300 that is, the insulating spacer 300 corresponding to the region A, is etched to form the first via 500 to expose the drain 262 of the thin film transistor; the ashing photoresist 400
  • the photoresist corresponding to the first transparent electrode region B is removed, and the photoresist other than the first transparent electrode and the first via region is retained.
  • a first transparent conductive film 270' is formed.
  • the remaining photoresist 400 and the first transparent conductive film 270' located thereon are stripped by a lift-off technique to form a first transparent electrode 270.
  • the first transparent electrode 270 is connected to the drain 262 of the thin film transistor through the first via 500.
  • Step five as shown in FIG. 2g, a pattern including a passivation layer 280 is formed over the first transparent electrode 270.
  • Step six forming a pattern including the second transparent electrode over the passivation layer. Since the first transparent electrode in the above example is a pixel electrode, the second electrode is a common electrode. A method of forming the second electrode is as follows:
  • a second via is formed on the passivation layer 280 corresponding to the common electrode line 230, and a second transparent electrode is formed, and the second transparent electrode 290 is connected to the common electrode line 230 through the second via.
  • the insulating spacer layer 300 is formed in a region corresponding to the TFT before the first transparent electrode is formed, thereby protecting the TFT channel from being contaminated by the first transparent electrode material ITO process, preventing deterioration of TFT characteristics, and ensuring product performance.
  • a dual-mask mask exposure process and a lift off process are employed in forming the first via 500 and the first transparent electrode 270 on the insulating spacer layer 300 without adding a mask. The TFT channel is prevented from being contaminated by the first transparent electrode material ITO process.
  • a step is further included between the second step and the third step: performing a H 2 Plasma process on the channel of the TFT.
  • the first transparent electrode 270 is a pixel electrode
  • the second transparent electrode 290 is a common electrode
  • the first transparent electrode 270 can be a common electrode and the second transparent electrode can be a pixel electrode.
  • the schematic diagram of the structure of the formed TFT array substrate is as shown in FIG. 3, and the preparation process is the same as the steps 1 to 3 corresponding to the first embodiment, and the steps 4 to 6 are as follows:
  • Step 4 forming a photoresist on the insulating spacer layer 300; exposing and developing the photoresist by using a double-adjusting mask to remove the photoresist in the corresponding region of the common electrode line, and partially retaining the first transparent electrode The photoresist of the region completely retains the photoresist of the other regions; etching the exposed insulating spacer layer to form the first via hole to expose the common electrode line; ashing the photoresist, removing the first a photoresist corresponding to a region of the transparent electrode, retaining a photoresist other than the first transparent electrode and the first via region; forming a first transparent conductive film, and peeling off the remaining photoresist and being located by a ground lift-off technique a first transparent conductive film thereon to form a first transparent electrode, and the common electrode line is connected through the first via.
  • step five a passivation layer is formed on the first transparent electrode.
  • step six a second via hole is formed on a region of the passivation layer corresponding to a drain of the thin film transistor to form a second transparent electrode, and the drain is connected through the second via.
  • the manufacturing process is similar to the process of manufacturing the first transparent electrode 270 as a pixel electrode and the second transparent electrode 290 as a common electrode, and details are not described herein again.
  • the above embodiment is described by taking a bottom gate type TFT structure as an example, and is also applicable to the top gate type TFT structure as long as the active layer of the TFT and the first transparent electrode (ITO) are formed when the first transparent electrode (ITO) is formed. Add an insulating spacer between them.
  • a method of fabricating an array substrate is provided, as shown in Figures 4a-4h.
  • the method for fabricating an array substrate of this embodiment includes:
  • Step 1 referring to FIG. 4 a , performing a gate mask patterning process on the base substrate 210 to form a gate metal layer, and forming a gate line (not shown) and a gate 220 by using a single patterning process and a primary mask process.
  • the pattern of the common electrode line 230 is not shown.
  • Step 2 referring to FIG. 4b, a source-drain mask patterning process is performed to form a pattern including a gate insulating layer 240, an active layer 250, an ohmic contact layer (eg, N+a-Si), and a source 261 and a drain 262.
  • a pattern of the active layer 250, the data lines, the source electrodes 261, the drain electrodes 262, and the like is formed over the gate insulating layer 240.
  • the gate 220, the gate insulating layer 240, the active layer 250, the source 261, and the drain 262 form a thin film transistor (TFT), and the source 261 and the drain 262 are between the channel regions of the TFT.
  • TFT thin film transistor
  • the data line, source 261 and drain 262 are formed in the same patterning process.
  • Step 3 referring to Figures 4b-4c, a hydrogen plasma process is performed to process the TFT channel; then an insulating spacer layer 300 is formed over the pattern of source 261, drain 262, and active layer 250.
  • the insulating spacer 300 may be formed using a material of silicon nitride (SiNx) by deposition, sputtering, or coating. Thickness can be
  • Step 4 referring to FIG. 4d, a photoresist 400 is applied over the insulating spacer 300.
  • the photoresist 400 is subjected to exposure development by a normal exposure process to remove the photoresist 400 corresponding to the common electrode region and the region B' corresponding to the partial drain region of the active layer, completely retaining the photoresist of the other regions.
  • Step 5 referring to Figures 4d-4e, the exposed SiNx material layer is etched by a dry etching process to remove the silicon nitride insulating spacer layer of the region B'.
  • Step 6 referring to Figures 4e-4f, depositing a first transparent conductive film (ITO) 270' over portions of step five, and stripping the remaining photoresist 400 along with the first layer thereon by a lift-off technique
  • a transparent conductive film portion 270' is formed to form a first transparent electrode 270 on a portion of the drain and the gate insulating layer.
  • the first transparent electrode 270 is directly connected to the drain 262.
  • Step 7 referring to FIG. 4g, a passivation layer is formed over portions of the step six, and a via is formed in the passivation layer 28 and the region of the insulating spacer 300 corresponding to the common electrode 230 by using a mask.
  • Step 8 referring to FIG. 4h, a second transparent electrode 290 is formed by a mask patterning process, and the second transparent electrode 290 is connected to the common electrode through the via.
  • the fourth embodiment of the present invention it is also conceivable to provide the first transparent electrode in the above third embodiment as a common electrode, and The two transparent electrodes are provided as pixel electrodes, and thus the structure of the formed TFT array substrate and the preparation process thereof can be easily obtained by changing the third embodiment.
  • the contradiction between the hydrogen plasma treatment and the haze defect is solved without increasing the number of process steps. It can be achieved that both the hydrogen plasma treatment and the I off of the TFT can be reduced, and the first time that the ITO is reduced by the hydrogen plasma treatment can be avoided, and the haze defect is generated.
  • An embodiment of the present invention further provides an array substrate fabricated by the above method, comprising: a gate line formed on a base substrate, a data line, a common electrode line, a thin film transistor, a first transparent electrode, formed in the a passivation layer over the first transparent electrode and a second transparent electrode.
  • the array substrate further includes: an insulating spacer layer between the active layer of the thin film transistor and the first transparent electrode, through the insulation The spacer layer and the passivation layer are formed with a via, the first transparent electrode is connected to the drain of the thin film transistor, and the second transparent electrode is connected to the common electrode through the via.
  • An embodiment of the present invention further provides an array substrate fabricated by the above method, comprising: a gate line formed on a base substrate, a data line, a common electrode line, a thin film transistor, a first transparent electrode, formed in the a passivation layer over the first transparent electrode and a second transparent electrode.
  • the array substrate further includes: an insulating spacer layer between the active layer of the thin film transistor and the first transparent electrode, wherein the insulating spacer layer is formed A via hole is formed with a second via hole formed on the passivation layer.
  • the first transparent electrode is connected to a drain of the thin film transistor through the first via, the second transparent electrode is connected to the common electrode line through the second via; or the first transparent electrode passes The first via is connected to the common electrode line, and the second transparent electrode is connected to the drain of the thin film transistor through the second via.
  • ITO first transparent electrode
  • the insulating spacer layer is made of silicon nitride and has a thickness of
  • Embodiments of the present invention also provide a display device including any of the above array substrates.
  • the display device may be a product or a component having any display function such as a liquid crystal panel, an electronic paper, a liquid crystal television, a liquid crystal display, a digital photo frame, a mobile phone, or a tablet computer.
  • the method for fabricating the array substrate of the embodiment of the invention can effectively avoid the pollution caused by the first transparent electrode (ITO) process on the TFT channel, avoid deterioration of the TFT characteristics, and improve product quality.
  • ITO first transparent electrode

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Abstract

一种阵列基板制作方法及制作的阵列基板及显示装置。所述阵列基板制作方法包括：在衬底基板（210）上形成包括栅极（230）、栅线、公共电极线（230）及栅绝缘层（240）的图形；形成包括数据线、源极（261）、漏极（262）及有源层（250）的图形；在所述源极（261）、漏极（262）及有源层（250）的图形之上形成包括绝缘间隔层（300）的图形；在所述绝缘间隔层（300）上形成包括第一透明电极（270）的图形；在所述第一透明电极（270）之上形成包括钝化层（280）的图形；以及在所述钝化层（280）之上形成包括第二透明电极（290）的图形。可以有效避免ITO工艺对TFT沟道造成的污染。

Description

阵列基板及其制作方法、显示装置 技术领域
本发明的实施例涉及一种阵列基板及其制作方法、显示装置。
背景技术
高级超维场转换技术(ADvanced Super Dimension Switch，ADS)显示模式由于优越的显示品质得到广泛发展，已成为全球业内重要技术标准，而H-ADS(高开口率ADS)模式是最先进的工艺之一。
发明内容
本发明的至少一个实施例提供了一种阵列基板制作方法，包括：在衬底基板上形成包括栅极、栅线、公共电极线及栅绝缘层的图形；形成包括数据线、源极、漏极及有源层的图形；在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形；在所述绝缘间隔层上形成包括第一透明电极的图形；在所述第一透明电极之上形成包括钝化层的图形；以及在所述钝化层之上形成包括第二透明电极的图形。
在一示例中，形成绝缘间隔层的图形以及第一透明电极的图形包括：，在所述绝缘间隔层上施加光刻胶；采用双调掩膜板对所述光刻胶进行曝光显影，去除所述漏极图形所在区域对应的光刻胶，部分保留第一透明电极图形所在区域对应的光刻胶，完全保留其它区域的光刻胶；刻蚀暴露出的绝缘间隔层，以形成所述第一过孔，使暴露出所述漏极；灰化所述光刻胶，去除第一透明电极图形所在区域对应的光刻胶，保留除第一透明电极和第一过孔区域以外的光刻胶；形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的第一透明导电薄膜，以形成第一透明电极，且通过所述第一过孔连接所述漏极。
在一示例中，所述在所述钝化层之上形成包括第二透明电极的图形的过程中，在所述钝化层上对应公共电极线的图形所在区域形成第二过孔；形成第二透明电极，使所述第二透明电极通过所述第二过孔连接所述公共电极线。
在一示例中，形成绝缘间隔层的图形以及第一透明电极的图形包括：在所述绝缘间隔层上施加光刻胶；采用双调掩膜板对所述光刻胶进行曝光显影，去除公共电极线图形所在区域对应的光刻胶，部分保留第一透明电极图形所 在区域对应的光刻胶，完全保留其它区域的光刻胶；刻蚀暴露出的绝缘间隔层，以形成所述第一过孔，使暴露出公共电极线；灰化所述光刻胶，去除第一透明电极图形所在区域对应的光刻胶，保留除第一透明电极和第一过孔区域以外的光刻胶；以及形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的第一透明导电薄膜，以形成第一透明电极，且通过所述第一过孔连接所述公共电极线。
在一示例中，所述在所述钝化层之上形成包括第二透明电极的图形的过程中，在所述钝化层上对应所述漏极所在区域形成第二过孔；形成第二透明电极，使所述第二透明电极通过所述第二过孔连接所述漏极。
在一示例中，所述方法还包括：在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形之前，进行氢气等离子体工艺处理所述源极和漏极之间形成的沟道区域。
在一示例中，形成绝缘间隔层的图形以及第一透明电极的图形包括：在所述绝缘间隔层上施加光刻胶；采用掩膜板对所述光刻胶进行曝光显影，去除部分所述漏极图形所在区域和第一透明电极图形所在区域对应的光刻胶，完全保留其它区域的光刻胶；刻蚀掉暴露出的全部所述绝缘间隔层；形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的所述第一透明导电薄膜，以形成所述第一透明电极。
在一示例中，在对应所述公共电极线的图形所在区域，通过所述钝化层和绝缘间隔层，形成一过孔；以及所述第二透明电极通过所述过孔连接所述公共电极线。
在一示例中，所述第一透明电极位于所述栅极绝缘层、漏极以及所述钝化层之间。
在一示例中，在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形之前，进行氢等离子体工艺处理所述源极和漏极之间形成的沟道区域。
本发明的至少一个实施例还提供了一种阵列基板，包括：形成在衬底基板之上的栅线、数据线、公共电极线、包括源极、漏极和有源层的薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极，形成在所述薄膜晶体管的所述有源层和所述第一透明电极所在层之间的绝缘间隔层，所述绝缘间隔层形成有第一过孔，所述钝化层上形成有第二过孔； 其中所述第一透明电极通过所述第一过孔连接所述薄膜晶体管的所述漏极，所述第二透明电极通过所述第二过孔连接所述公共电极线；或所述第一透明电极通过所述第一过孔连接所述公共电极线，所述第二透明电极通过所述第二过孔连接所述薄膜晶体管的漏极。
在一示例中，所述绝缘间隔层的材料为氮化硅。
在一示例中，所述绝缘间隔层的厚度为
Figure PCTCN2014086301-appb-000001
本发明的至少一个实施例还提供了一种阵列基板、包括：形成在衬底基板之上的栅线、数据线、公共电极线、包括源极、漏极和有源层的薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极，形成在所述薄膜晶体管的所述有源层和所述第一透明电极所在层之间的绝缘间隔层，以及通过所述绝缘间隔层和所述钝化层形成在所述公共电极线之上的过孔；所述第一透明电极位于所述栅极绝缘层和所述漏极以及所述钝化层之间，并与所述漏极相连，所述第二透明电极通过所述过孔连接所述公共电极线。
在一示例中，所述绝缘间隔层的材料为氮化硅，并且所述绝缘间隔层的厚度为
Figure PCTCN2014086301-appb-000002
根据本发明的至少一个实施例提供一种显示装置，包括所述任一所述的阵列基板。
附图说明
以下将结合附图对本发明的实施例进行更详细的说明，以使本领域普通技术人员更加清楚地理解本发明，其中：
图1a-1e是阵列基板制作方法中形成阵列基板的各结构的流程示意图；
图2a是根据采用本发明的一个实施例的阵列基板制作方法中形成TFT的基板结构示意图；
图2b是在图2a的基础上形成绝缘间隔层的基板结构示意图；
图2c是在图2b的基础上形成光刻胶并曝光显影后的基板结构示意图；
图2d是在图2c的基础上在绝缘间隔层上形成第一过孔并灰化光刻胶后的基板结构示意图；
图2e是在图2d的基础上形成第一透明导电薄膜的基板结构示意图；
图2f是在图2e的基础上形成第一透明电极的基板结构示意图；
图2g是采用本发明实施例的阵列基板制作方法制作的一种阵列基板结构示意图；
图3是根据本发明的另一个实施例的阵列基板制作方法制作的另一种阵列基板的结构示意图；
图4a-4h是根据本发明的第三实施例的阵列基板制作方法制作的又一种阵列基板的结构示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在无需创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
除非另作定义，本文使用的技术术语或者科学术语应当为本发明所属领域内具有一般技能的人士所理解的通常意义。本发明专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“上”、“下”、等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
H-ADS显示模式薄膜晶体管(TFT)阵列基板制备工艺流程如图1a-1e所示。在衬底基板110上形成栅极120、栅线(图中未示出)和公共电极线130(1次掩模工艺)；形成栅绝缘层140；形成有源层150；形成数据线(图中未示出)、源极161及漏极162(1次掩模工艺)；形成第一透明电极170(1次掩模工艺)；形成钝化层180及其上的过孔(1次掩模工艺)；形成第二透明电极190(1次掩模工艺)。
在上述阵列基板制备工艺中，发明人注意到如下问题，参照1a-1e所示，在形成第一透明电极170工艺时，源极161和漏极162工艺已完成，TFT沟道(如图1c在虚线框所示)会全部裸露在外部。第一透明电极170的材料通常为ITO(氧化铟锡)，沉积时会给TFT沟道引入杂质，造成TFT沟道污染。 同时ITO刻蚀液残留、沟道内ITO残留也会造成TFT沟道污染。TFT沟道决定着TFT的特性，TFT沟道污染会造成TFT特性异常，影响产品性能。
此外，在沉积钝化层180之前，虽然采用氢等离子体(H2Plasma)处理TFT沟道，可以降低TFT的关态漏电流Ioff，提高产品品质，但是氢等离子体会造成第一透明电极ITO被还原，而产生雾状不良。故H-ADS显示模式TFT阵列基板制备工艺中钝化层180沉积(PVX Dep)前一般不能采用H2Plasma处理，因此造成TFT的Ioff较高，影响产品品质。
如图2a-2g所示，本发明的一个实施例的阵列基板制作方法包括：
步骤一，如图2a所示，在衬底基板210上形成包括栅线(图中未示出)、栅极220、公共电极线230及栅绝缘层240的图形，其中栅极220、栅线和公共电极线230在同一次构图工艺中形成，仅需要一次掩模。栅绝缘层240形成在栅线、栅极220和公共电极线230之上。
步骤二，形成包括有源层250、数据线(图中未示出)、源极261和漏极262的图形。有源层250、数据线(图中未示出)、源极261和漏极262的图形形成在所述栅绝缘层240之上。该步骤之后，栅极220、栅绝缘层240、有源层250、源极261和漏极262形成薄膜晶体管(TFT)，源极261和漏极262之间为TFT的沟道区域。数据线、源极261和漏极262在同一次构图工艺中形成。
步骤三，如图2b所示，在源极261、漏极262及有源层250的图形之上形成绝缘间隔层300，可以采用沉积、溅射或涂覆等方式形成。由于绝缘间隔层300旨在保护第一透明电极形成时不会因残留影响沟道，绝缘间隔层300可以只覆盖TFT所在区域，也可以覆盖在整个基板表面，由此覆盖TFT的沟道而使其在后面的工序中得到保护。例如，绝缘间隔层300可以采用氮化硅材料，厚度可以为
Figure PCTCN2014086301-appb-000003
这样的厚度既能保护TFT的沟道，又能使整个阵列基板的厚度不至于太厚，保证显示装置的轻薄性。
步骤四，在绝缘间隔层300上形成包括第一透明电极的图形。本发明的实施例的一个示例中以第一透明电极通过第一过孔连接薄膜晶体管的漏极，即第一透明电极为像素电极为例进行说明。
如图2c所示，在绝缘间隔层300上施加光刻胶400。采用双调掩膜板(半调掩膜板或灰调掩膜板)对光刻胶400进行曝光显影，去除薄膜晶体管的漏极262对应区域A的光刻胶，部分保留第一透明电极对应区域B的光刻胶，完全保留其它区域的光刻胶，即第一透明电极对应区域B的光刻胶的厚度小 于其它区域的光刻胶厚度。
如图2d所示，刻蚀暴露出的绝缘间隔层300，即区域A对应的绝缘间隔层300，以形成第一过孔500，使暴露出薄膜晶体管的漏极262；灰化光刻胶400，去除第一透明电极区域B对应的光刻胶，保留除第一透明电极和第一过孔区域以外的光刻胶。
如图2e所示，形成第一透明导电薄膜270＇。
如图2f所示，通过离地剥离技术，剥离剩余的光刻胶400及位于其上的第一透明导电薄膜270＇，以形成第一透明电极270。第一透明电极270通过第一过孔500连接薄膜晶体管的漏极262。
步骤五，如图2g所示，在第一透明电极270之上形成包括钝化层280的图形。
步骤六，在所述钝化层之上形成包括第二透明电极的图形。由于上述示例中第一透明电极为像素电极，则此第二电极为公共电极。形成第二电极的方法例如如下所述：
如图2g所示，在钝化层280上对应公共电极线230的区域形成第二过孔，并形成第二透明电极，第二透明电极290通过第二过孔连接公共电极线230。
本实施例中，在形成第一透明电极之前在TFT对应的区域形成绝缘间隔层300，从而保护了TFT沟道不被第一透明电极材料ITO工艺污染，避免TFT特性恶化，保证产品性能。另外，在形成绝缘间隔层300上的第一过孔500和第一透明电极270时采用了双调掩膜板曝光工艺和离地剥离(lift off)工艺，在不增加掩模的前提下，避免了TFT沟道被第一透明电极材料ITO工艺污染。
由于本实施例中第一透明电极270和TFT间隔有绝缘间隔层300，氢等离子体处理不再会造成ITO被还原。因此，为了降低TFT的Ioff，提高产品品质，在步骤二和步骤三之间还包括步骤：对TFT的沟道进行H2Plasma工艺处理。
上述实施例的示例中，第一透明电极270为像素电极，第二透明电极290为公共电极。
在根据本发明的另一个实施例中，第一透明电极270可以为公共电极，而第二透明电极为像素电极。在此实施例中，形成的TFT阵列基板的结构示意图如图3所示，其制备过程除了对应于实施例一中的步骤一到三相同之外，步骤四到步骤六的制作过程如下：
步骤四，在所述绝缘间隔层300上形成光刻胶；采用双调掩膜板对所述光刻胶进行曝光显影，去除公共电极线对应区域的光刻胶，部分保留第一透明电极对应区域的光刻胶，完全保留其它区域的光刻胶；刻蚀暴露出的绝缘间隔层，以形成所述第一过孔，使暴露出公共电极线；灰化所述光刻胶，去除第一透明电极对应区域的光刻胶，保留除第一透明电极和第一过孔区域以外的光刻胶；形成第一透明导电薄膜，并通过离地剥离技术，剥离剩余的光刻胶及位于其上的第一透明导电薄膜，以形成第一透明电极，且通过所述第一过孔连接所述公共电极线。
步骤五，在所述第一透明电极之上形成钝化层。
步骤六，在所述钝化层上对应薄膜晶体管的漏极的区域形成第二过孔，形成第二透明电极，通过所述第二过孔连接所述漏极。
制作工艺过程与第一透明电极270为像素电极，第二透明电极290为公共电极的制作工艺过程类似，此处不再赘述。
以上实施例是以底栅型TFT结构为例进行说明的，对于顶栅型TFT结构同样适用，只要在形成第一透明电极(ITO)时在TFT的有源层和第一透明电极(ITO)之间增加绝缘间隔层即可。
根据本发明的第三实施例，提供了一种阵列基板的制备方法，如图4a-4h所示。该实施例的阵列基板制作方法包括：
步骤一，参见图4a，在衬底基板210上进行栅极掩模构图工艺，形成栅极金属层，利用一次构图工艺和一次掩模形成包括栅线(图中未示出)、栅极220、公共电极线230的图形。
步骤二，参见图4b，进行源漏掩模构图工艺，形成包括栅绝缘层240，有源层250、欧姆接触层(例如N+a-Si)以及源极261和漏极262的图形。有源层250、数据线、源极261和漏极262等的图形形成在所述栅绝缘层240之上。该步骤之后，栅极220、栅绝缘层240、有源层250、源极261和漏极262形成薄膜晶体管(TFT)，源极261和漏极262之间为TFT的沟道区域。数据线、源极261和漏极262在同一次构图工艺中形成。
步骤三，参见图4b-4c，执行氢等离子体工艺来处理TFT沟道；然后在源极261、漏极262及有源层250的图形之上形成绝缘间隔层300。绝缘间隔层300可以采用沉积、溅射或涂覆等方式，利用氮化硅(SiNx)的材料形成。厚度可以为
Figure PCTCN2014086301-appb-000004
步骤四，参见图4d，在绝缘间隔层300上施加光刻胶400。采用普通曝光工艺对光刻胶400进行曝光显影，去除对应于公共电极区和对应于有源层的部分漏极区的区域B’的光刻胶400，完全保留其它区域的光刻胶。
步骤五，参见图4d-4e，采用干蚀刻工艺对暴露出的SiNx材料层进行刻蚀，去除区域B’的氮化硅绝缘间隔层。
步骤六，参见图4e-4f，在经过步骤五的各部分之上沉积第一透明导电薄膜(ITO)270’，并通过离地剥离技术，剥离剩余的光刻胶400连同位于其上的第一透明导电薄膜部分270’，以在部分漏极和栅极绝缘层上形成第一透明电极270。该第一透明电极270与漏极262直接相连。
步骤七，参见图4g，在经过步骤六的各部分之上形成钝化层，并利用掩模在所述钝化层28和绝缘间隔层300上对应公共电极230的区域形成一过孔。
步骤八，参见图4h，利用掩模构图工艺形成第二透明电极290，该第二透明电极290通过所述过孔与所述公共电极相连。
类似于上面关于第一实施例和第二实施例的情形，在本发明的第四实施例中，也可以容易地想到将上述第三实施例中的第一透明电极设置为公共电极，而第二透明电极设置为像素电极，因此形成的TFT阵列基板的结构和其制备过程可以通过变化第三实施例而容易地得到。
本发明实施例的上述阵列基板制作方法，在不增加工艺步骤的前提下，解决了氢等离子体处理和雾状不良之间的矛盾。可以做到既保留氢等离子体处理，又能够降低TFT的Ioff，能够避免氢等离子体处理造成的第一次ITO被还原，产生雾状不良的缺陷。
本发明的实施例还提供了一种利用上述方法制作的阵列基板，包括：形成在衬底基板之上的栅线、数据线、公共电极线、薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极。为了避免第一透明电极对TFT的沟道产生污染，该阵列基板还包括：绝缘间隔层，所述绝缘间隔层位于薄膜晶体管的有源层和所述第一透明电极之间，通过所述绝缘间隔层和钝化层形成有一过孔，所述第一透明电极与薄膜晶体管的漏极相连，所述第二透明电极通过所述过孔与公共电极相连。
本发明的实施例还提供了一种利用上述方法制作的阵列基板，包括：形成在衬底基板之上的栅线、数据线、公共电极线、薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极。为了避免第一 透明电极对TFT的沟道产生污染，该阵列基板还包括：绝缘间隔层，所述绝缘间隔层位于薄膜晶体管的有源层和所述第一透明电极之间，所述绝缘间隔层形成有第一过孔，钝化层上形成有第二过孔。
所述第一透明电极通过所述第一过孔连接所述薄膜晶体管的漏极，所述第二透明电极通过所述第二过孔连接所述公共电极线；或所述第一透明电极通过第一过孔连接所述公共电极线，所述第二透明电极通过所述第二过孔连接所述薄膜晶体管的漏极。如此可以有效地避免第一透明电极(ITO)工艺对TFT沟道造成的污染，避免TFT特性恶化，提高了产品质量。
例如，所述绝缘间隔层的材料为氮化硅，厚度为
Figure PCTCN2014086301-appb-000005
本发明的实施例还提供了一种显示装置，包括上述任一的阵列基板。该显示装置可以为：液晶面板、电子纸、液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
本发明实施例的阵列基板制作方法可以有效地避免第一透明电极(ITO)工艺对TFT沟道造成的污染，避免TFT特性恶化，提高了产品质量。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有这样的变化和变形以及等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。
本申请要求于2014年03月31日提交的名称为“阵列基板及其制作方法、显示装置”的中国专利申请No.201410126538.7的优先权，其全文以引用方式合并于本文。

Claims (16)

  1. 一种阵列基板制作方法，包括：
    在衬底基板上形成包括栅极、栅线、公共电极线及栅绝缘层的图形；
    形成包括数据线、源极、漏极及有源层的图形；
    在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形；
    在所述绝缘间隔层上形成包括第一透明电极的图形；
    在所述第一透明电极之上形成包括钝化层的图形；以及
    在所述钝化层之上形成包括第二透明电极的图形。
  2. 如权利要求1所述的阵列基板制作方法，其中，形成绝缘间隔层的图形以及第一透明电极的图形包括：
    在所述绝缘间隔层上施加光刻胶；
    采用双调掩膜板对所述光刻胶进行曝光显影，去除所述漏极图形所在区域对应的光刻胶，部分保留第一透明电极图形所在区域对应的光刻胶，完全保留其它区域的光刻胶；
    刻蚀暴露出的所述绝缘间隔层，以形成所述第一过孔，使暴露出所述漏极；
    灰化所述光刻胶，去除所述第一透明电极图形所在区域对应的光刻胶，保留除所述第一透明电极和第一过孔区域以外的光刻胶；以及
    形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的所述第一透明导电薄膜，以形成所述第一透明电极，且通过所述第一过孔连接所述漏极。
  3. 如权利要求1或2所述的阵列基板制作方法，其中，
    在所述钝化层上对应所述公共电极线的图形所在区域形成第二过孔；形成所述第二透明电极，使所述第二透明电极通过所述第二过孔连接所述公共电极线。
  4. 如权利要求1所述的阵列基板制作方法，其中，形成绝缘间隔层的图形以及第一透明电极的图形包括：
    在所述绝缘间隔层上施加光刻胶；
    采用双调掩膜板对所述光刻胶进行曝光显影，去除所述公共电极线的图形所在区域对应的光刻胶，部分保留所述第一透明电极的图形所在区域对应的光刻胶，完全保留其它区域的光刻胶；
    刻蚀暴露出的所述绝缘间隔层，以形成所述第一过孔，使暴露出所述公共电极线；
    灰化所述光刻胶，去除所述第一透明电极的图形所在区域对应的光刻胶，保留除所述第一透明电极和所述第一过孔区域以外的光刻胶；以及
    形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的第一透明导电薄膜，以形成所述第一透明电极，且通过所述第一过孔连接所述公共电极线。
  5. 如权利要求1或4所述的阵列基板制作方法，其中，
    在所述钝化层上对应所述漏极所在区域形成第二过孔；形成所述第二透明电极，使所述第二透明电极通过所述第二过孔连接所述漏极。
  6. 如权利要求1-5中任一项所述的阵列基板制作方法，还包括：在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形之前，进行氢等离子体工艺处理所述源极和漏极之间形成的沟道区域。
  7. 如权利要求1所述的阵列基板制作方法，其中，形成绝缘间隔层的图形以及第一透明电极的图形包括：
    在所述绝缘间隔层上施加光刻胶；
    采用掩膜板对所述光刻胶进行曝光显影，去除部分所述漏极图形所在区域和所述第一透明电极图形所在区域对应的光刻胶，完全保留其它区域的光刻胶；
    刻蚀掉暴露出的全部所述绝缘间隔层；以及
    形成第一透明导电薄膜，并剥离剩余的光刻胶及位于其上的所述第一透明导电薄膜，以形成所述第一透明电极。
  8. 如权利要求7所述的阵列基板制作方法，其中，
    在对应所述公共电极线的图形所在区域，通过所述钝化层和绝缘间隔层，形成一过孔；以及所述第二透明电极通过所述过孔连接所述公共电极线。
  9. 如权利要求7或8所述的阵列基板制作方法，其中，所述第一透明电极位于所述栅极绝缘层、漏极以及所述钝化层之间。
  10. 如权利要求7-9中任一项所述的阵列基板制作方法，还包括：在所述源极、漏极及有源层的图形之上形成包括绝缘间隔层的图形之前，进行氢等离子体工艺处理所述源极和漏极之间形成的沟道区域。
  11. 一种阵列基板，包括：形成在衬底基板之上的栅线、数据线、公共电极线、包括源极、漏极和有源层的薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极，形成在所述薄膜晶体管的所述有源层和所述第一透明电极所在层之间的绝缘间隔层，所述绝缘间隔层形成有第一过孔，所述钝化层上形成有第二过孔；
    其中所述第一透明电极通过所述第一过孔连接所述薄膜晶体管的所述漏极，所述第二透明电极通过所述第二过孔连接所述公共电极线；或所述第一透明电极通过所述第一过孔连接所述公共电极线，所述第二透明电极通过所述第二过孔连接所述薄膜晶体管的所述漏极。
  12. 如权利要求11所述的阵列基板，其中，所述绝缘间隔层的材料为氮化硅。
  13. 如权利要求11或12所述的阵列基板，其中，所述绝缘间隔层的厚度为
    Figure PCTCN2014086301-appb-100001
  14. 一种阵列基板，包括：形成在衬底基板之上的栅线、数据线、公共电极线、包括源极、漏极和有源层的薄膜晶体管、第一透明电极、形成在所述第一透明电极之上的钝化层和第二透明电极，形成在所述薄膜晶体管的所述有源层和所述第一透明电极所在层之间的绝缘间隔层，以及通过所述绝缘间隔层和所述钝化层形成在所述公共电极线之上的过孔；
    其中所述第一透明电极位于所述栅极绝缘层和所述漏极以及所述钝化层之间，并与所述漏极相连，所述第二透明电极通过所述过孔连接所述公共电极线。
  15. 如权利要求14所述的阵列基板，其中，所述绝缘间隔层的材料为氮化硅，并且所述绝缘间隔层的厚度为
    Figure PCTCN2014086301-appb-100002
  16. 一种显示装置，包括如权利要求11-15中任一项所述的阵列基板。
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