WO2019227964A1 - 阵列基板、显示装置以及形成阵列基板的方法 - Google Patents

阵列基板、显示装置以及形成阵列基板的方法 Download PDF

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WO2019227964A1
WO2019227964A1 PCT/CN2019/074200 CN2019074200W WO2019227964A1 WO 2019227964 A1 WO2019227964 A1 WO 2019227964A1 CN 2019074200 W CN2019074200 W CN 2019074200W WO 2019227964 A1 WO2019227964 A1 WO 2019227964A1
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layer
array substrate
detection line
substrate
display area
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PCT/CN2019/074200
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English (en)
French (fr)
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张陶然
周炟
莫再隆
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to US16/491,737 priority Critical patent/US11569274B2/en
Publication of WO2019227964A1 publication Critical patent/WO2019227964A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • Embodiments of the present disclosure relate to an array substrate, a display device, and a method of forming an array substrate.
  • Flexible organic light-emitting diode Organic Light-Emitting Diode, OLED
  • OLED Organic Light-Emitting Diode
  • film cracks ie, film cracks
  • TFE thin film encapsulation
  • At least one embodiment of the present disclosure provides an array substrate including a substrate and a display region provided on the substrate and a non-display region surrounding the display region; the non-display region includes a substrate disposed on the substrate.
  • a detection line is provided on the surface of the detection line far from the substrate in an undulating manner.
  • the non-display area further includes an adjustment layer; the adjustment layer is disposed between the substrate and the detection line, and the adjustment layer and an active layer in the display area The layer is made using the same patterning process; the surface of the adjustment layer away from the substrate is set to be undulating, and the surface of the detection line near and away from the substrate is set to be undulating.
  • the non-display area further includes a first buffer layer; the first buffer layer is disposed between the adjustment layer and the substrate, and the first buffer layer and the The second buffer layer in the display area is made by the same patterning process.
  • the detection line and the gate layer in the display region are made by a same patterning process.
  • the detection line and the pixel electrode layer in the display area are made by a same patterning process.
  • the array substrate further includes a fan-out area; the fan-out area includes a substrate, a first buffer layer, an adjustment layer, and a detection line; the first buffer layer is disposed on the substrate The adjustment layer is disposed on the first buffer layer, and a surface remote from the substrate is undulated, and a surface of the detection line near and far from the substrate is undulated.
  • the undulating shape is wavy.
  • the detection line is made of metal molybdenum.
  • At least one embodiment of the present disclosure provides a display device including any one of the above array substrates.
  • FIG. 1 is a schematic diagram of detection line routing in a non-display area in the technology known by the inventors;
  • FIG. 2 is a schematic cross-sectional view in the direction A-A 'shown in FIG. 1;
  • 3A is a schematic diagram of detecting line routing in a non-display area according to an embodiment of the present disclosure
  • FIG. 3B is a schematic cross-sectional view taken along line B-B 'in FIG. 3A;
  • FIG. 3C is a schematic diagram of a force on a section taken along line B-B 'in FIG. 3A;
  • 3D is a schematic diagram of detecting a line crack according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic flowchart illustrating a process for forming a detection line and a gate layer in a display region by using the same patterning process according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a pickled film board in a detection line area according to an embodiment of the present disclosure.
  • Fig. 6 is a schematic cross-sectional view taken along a line C-C 'in Fig. 2.
  • flexible OLED products often use flexible packaging. If the flexible packaging loses airtightness, water vapor may enter the electroluminescent device, causing the electroluminescent material to fail, resulting in black spots in the display screen. In order to improve the yield of OLED products, it is necessary to detect film cracks as early as possible.
  • PCD Panel, Crack, Detect
  • the array substrate known by the inventors includes at least a display area (also referred to as AA area) 101 and a non-display area 102 (also referred to as a non-AA area, a thick dashed line and a thick solid line) surrounding the display area. Area).
  • the detection line 103 is disposed in the non-display area 102 and is connected to a data line in the display area.
  • the detection principle of the PCD trace detection method is:
  • the detection line If the detection line is intact, the corresponding column of pixels displays the set color, such as green; if the detection line is broken or cracked, its resistance will increase, and then the detection line and data The series resistance of the line becomes larger. According to the principle of resistance voltage division, the pixel voltage written to the corresponding column of pixels becomes smaller, so that the corresponding column of pixels no longer displays a set color, such as purple. When the pixels in the corresponding column do not display the set color, it can be determined that a Crack area exists. Since the crack area of the PCD trace detection film layer is not the focus of this application, only the basic principle is described. For a more detailed description, reference may be made to related documents, which does not constitute a limitation on the present disclosure.
  • the PCD traces and the source and drain layers in the display region are formed using the same patterning process, that is, the PCD traces in the non-display region 102 and the source and drain layers in the display region 101 are disposed on the same layer.
  • the source / drain layer in the display region 101 usually adopts a Ti / Al / Ti structure. Therefore, the PCD trace also uses the Ti / Al / Ti structure (as shown in Figure 2). Its good ductility can buffer the stress of the film crack, which causes the PCD trace to be cracked under the same force. Slight, resistance change is small, Crack is more difficult to detect.
  • At least one embodiment of the present disclosure provides an array substrate, as shown in FIGS. 3A, 3B, and 3C, including a substrate 304 and a display region 301 formed on the substrate 304 and a non-display region 302 surrounding the display region 301.
  • the array substrate further includes detection lines 305 disposed in the non-display area 302, and the detection lines 305 are disposed on the substrate 304.
  • the surface of the detection line 305 remote from the substrate 304 is provided with an undulation 306.
  • FIG. 3C shows a metallographic diagram in the direction of B-B 'in FIG. 3A.
  • the surface of the detection line 305 is set as a undulation 306, the ductility of different parts of the detection line 305 is different.
  • the weaker ductile portion of the detection line near the external force is more likely to generate cracks (the area inside the dotted frame), thereby significantly changing the resistance value of the detection line.
  • the problem of TFE cracks caused when the film crack is slight is more easily detected, the sensitivity of detecting the film crack is improved, and the rate of missed detection can be reduced.
  • the undulating shape 306 may be wavy, stepped (high-step and low-step spaced), and the like. In one embodiment of the present disclosure, the undulations 306 are provided in a wave shape.
  • the array substrate further includes an adjustment layer 307.
  • the adjustment layer 307 is disposed on the substrate 304, and the detection line 305 is disposed on the adjustment layer 307.
  • the adjustment layer 307 can be made of polycrystalline silicon (P-Si), so the adjustment layer 307 can be formed using the same patterning process as the active layer (not shown) in the display area 301.
  • P-Si polycrystalline silicon
  • the surface of the adjustment layer 307 away from the substrate 304 is undulated, so that the surface of the detection line 305 near and away from the substrate has undulations.
  • the adjustment layer 307 is set to be undulated, so that when the detection line 305 is formed on the adjustment layer 307, the surfaces of the detection line 305 near and away from the substrate 304 are undulated.
  • the array substrate further includes a first buffer layer 308.
  • the first buffer layer 308 may be disposed between the adjustment layer 307 and the substrate 304, and the first buffer layer 308 may be formed using the same patterning process as a second buffer layer buffer (not shown in the figure) in the display area 304. In this way, the first buffer layer 308 can increase the adhesion between the adjustment layer 307 and the substrate 304 and prevent the adjustment layer 307 from falling off.
  • the detection line 305 is undulated, even if the detection line 305 still adopts a Ti / Al / Ti structure, the sensitivity of the crack of the detection film layer can also be improved.
  • the detection line 305 is made of metal molybdenum. At this time, the detection line 305 and a gate layer (not shown in the figure) or a pixel electrode layer in the display area 301 Formed using the same patterning process.
  • the detection line 305 and the gate layer in the display area 301 are made by the same patterning process. As shown in FIGS. 4 (a) to (e), the process of forming the detection line 305 includes :
  • a first buffer layer is formed on the substrate by using a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the first buffer layer and the second buffer layer in the display area are formed by the same patterning process.
  • the substrate may be made of a material such as polyester fiber, and the first buffer layer and the second buffer layer may be made of a silicon oxide (SiOx) and / or a silicon nitride (SiNx) material.
  • Step 2 Referring to FIG. 4 (b), a PECVD method is used to form an adjustment layer on the first buffer layer.
  • the adjustment layer and the active layer in the display area are formed by the same patterning process.
  • the adjustment layer may be made of polysilicon (P-Si) material.
  • Step three referring to FIG. 4 (c), forming an undulating shape on the side of the adjustment layer away from the substrate.
  • a halftone (Halftone) process is used, that is, during the ACT Mask process, the detection line area in the non-display area is alternately half-exposed.
  • the composition is shown in FIG. 5.
  • ACT Dry Etch Dry Etch
  • the surface of the P-Si will form undulations.
  • a gate insulating layer is formed on the adjustment layer by using a PECVD method.
  • the gate insulating layer and the gate insulating layer in the display region are formed by the same patterning process.
  • the gate insulating layer may be made of silicon oxide (SiOx) and / or silicon nitride (SiNx) materials.
  • Step 5 Referring to 4 (e), a sputter method is used to form a detection line on the gate insulation layer. At this time, the bottom of the detection line (the surface close to the substrate) will form an undulating shape.
  • the detection line 305 and the pixel electrode layer in the display area 301 are made by the same patterning process.
  • the detection line 305 and the pixel electrode layer in the display area 301 are made by the same patterning process, and the detection line 305 and the gate layer in the display area 301 are made of the same patterning process. The differences are:
  • step 5 when the detection line 2 is formed on the gate insulating layer by a sputtering method, the patterning process of the pixel electrode layer in the display area is corresponding.
  • the detection line 305 and the gate layer in the display area 301 are made by using the same patterning process to realize that the detection line 305 and the gate layer in the display area 301 are made by using the same patterning process, which will not be repeated here.
  • the array substrate further includes a fan-out area 308.
  • the fan-out area 308 includes a substrate 701, a first buffer layer 702, an adjustment layer 703, and a detection line 704.
  • the first buffer layer 702 may be formed using the same patterning process as the gate insulating layer in the display region, and the adjustment layer 703 may be formed using the same patterning process as the active layer in the display region.
  • the first buffer layer 702 is disposed on the substrate 701; the adjustment layer 703 is disposed on the first buffer layer 702, and the surface away from the substrate 701 is undulated, and accordingly, the detection line 704 approaches and leaves the surface of the first buffer layer 702 Set to undulating.
  • the process of forming the fan-out area includes:
  • EBA Mask Edge Bending Mask
  • the Halftone process is performed in the EBA Mask.
  • the configuration is shown in Figure 5 to keep the active layer away from the substrate. The surface of the surface is undulating, and the bottom of the detection line 704 is undulating.
  • the detection line 704 can also be made by using the same patterning process as the pixel electrode layer in the display area.
  • the adjustment layer 703 may be formed using the same patterning process as the interlayer dielectric layer ILD (dielectric material between the pixel electrodes) in the display region.
  • ILD interlayer dielectric layer
  • the thin film transistor (TFT) in the display area of the array substrate adopts a top gate structure, and the detection line routing in the non-display area also corresponds to it.
  • the detection line routing in the non-display area also changes accordingly.
  • At least one embodiment of the present disclosure also provides a display panel including an array substrate.
  • the array substrate is the above-mentioned array substrate.
  • the display panel can be used in display devices such as mobile phones, computers, tablet computers, and televisions.
  • first and second are used for descriptive purposes only, and should not be interpreted to indicate or imply relative importance.
  • plurality refers to two or more, unless explicitly defined otherwise.
  • the two components connected by dashed lines are in an electrical connection or contact relationship. The use of dashed lines is only to make the drawings clearer and easier to understand the solutions of the embodiments of the present disclosure.

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Abstract

一种阵列基板，包括基底(304)和形成在所述基底上的显示区域(301)和围绕所述显示区域的非显示区域(302)；所述非显示区域(302)包括设置在所述基底上的检测线(305)，所述检测线(305)远离所述基底(304)的表面设置为起伏状(306)。还公开了一种显示装置。

Description

阵列基板、显示装置以及形成阵列基板的方法
本申请要求于2018年5月31日递交的中国专利申请第201820843207.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种阵列基板、显示装置以及形成阵列基板的方法。
背景技术
柔性有机发光二极管(Organic Light-Emitting Diode，OLED)产品常采用柔性封装。若柔性封装漏气，则电致发光器件会接触到外界水汽，使电致发光器件中的电致发光材料遇水失效，导致显示画面中会出现黑点(Growing Dark Spot，GDS)。
柔性封装漏气的基本原因是膜层裂纹(即膜层Crack)，膜层裂纹进一步引起薄膜封装(Thin Film Encapsulation，TFE)破裂。为提升OLED产品良率，需要尽可能早的检测出膜层裂纹。
发明内容
本公开的至少一个实施例提供了一种阵列基板，包括基底和设置在所述基底上的显示区域以及围绕所述显示区域的非显示区域；所述非显示区域包括设置在所述基底上的检测线，所述检测线远离所述基底的表面设置为起伏状。
在本公开的一个实施例中，所述非显示区域还包括调整层；所述调整层设置在所述基底和所述检测线之间，且所述调整层与所述显示区域内的有源层采用同一构图工艺制成；所述调整层远离所述基底的表面设置为起伏状，所述检测线靠近和远离所述基底的表面设置为起伏状。
在本公开的一个实施例中，所述非显示区域还包括第一缓冲层；所述第一缓冲层设置在所述调整层和所述基底之间，且所述第一缓冲层与所述显示 区域内的第二缓冲层采用同一构图工艺制成。
在本公开的一个实施例中，所述检测线与所述显示区域内栅极层采用同一构图工艺制成。
在本公开的一个实施例中，所述检测线与所述显示区域内的像素电极层采用同一构图工艺制成。
在本公开的一个实施例中，所述阵列基板还包括扇出区域；所述扇出区域包括基底、第一缓冲层、调整层和检测线；所述第一缓冲层设置在所述基底上，所述调整层设置在所述第一缓冲层上，且远离所述基底的表面设置为起伏状，所述检测线靠近和远离所述基底的表面设置为起伏状。
在本公开的一个实施例中，所述起伏状为波浪形。
在本公开的一个实施例中，所述检测线采用金属钼制成。
本公开的至少一个实施例提供了一种显示装置，包括上述任一阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1是发明人已知的技术中非显示区域内检测线走线示意图；
图2是图1所示A-A’方向上剖面示意图；
图3A是根据本公开的一个实施例的非显示区域内检测线走线示意图；
图3B是沿图3A中的线B-B’截取的剖面示意图；
图3C是沿图3A中的线B-B’截取的剖面上的受力示意图；
图3D是根据本公开的一个实施例的检测线裂缝示意图；
图4是示出了根据本公开一个实施例的采用同一构图工艺形成检测线与显示区域内栅极层的工艺流程示意图；
图5是根据本公开实施例的检测线区域的腌膜板示意图；以及
图6是沿图2中的线C-C’得到的剖面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公 开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
目前，柔性OLED产品常采用柔性封装，如果柔性封装丧失气密性，则水蒸气可能会进入电致发光器件中，使电致发光材料失效，导致显示画面中会出现黑点。为提升OLED产品良率，需要尽可能早的检测出膜层裂纹。
实际应用中，若膜层裂纹较轻微引起的TFE薄膜裂缝不太明显，发明人已知的技术中涡流检测(Eddy Current Testing，ET)无法检测出TFE裂缝，并且后续点亮阶段也不会出现明显不良。这样，OLED产品在高温信赖性试验中或在后续的使用中，膜层裂纹会恶化，会引起阵列基板不良，使阵列基板存在报废风险。
发明人已知的技术提供了一种检测方式，PCD(Panel Crack Detect)走线检测法。下文将对PCD走线检测法进行简单的描述。
参见图1，发明人已知的阵列基板至少包括显示区域(也称之为AA区)101和围绕在显示区域的非显示区域102(也称之为非AA区，粗虚线和粗实线之间的区域)。其中，检测线103设置在非显示区域102内，与显示区域内的数据线连接。该PCD走线检测法的检测原理为：
通过检测线向数据线写入预设的像素电压，若检测线完好，则对应列像素显示设定颜色，例如绿色；若检测线折断或者有裂纹，其电阻会增大，进而检测线和数据线的串联电阻变大，根据电阻分压原理，写入到对应列像素的像素电压变小，从而使对应列像素不再显示设定颜色，例如紫色。在相应列像素不显示设定颜色时，可以确定存在Crack区域。由于PCD走线检测膜层Crack区域不是本申请的重点，因此仅描述了基本原理，更详细的描述可以参考相关文献，在此不构成对本公开的限定。
以经典7T1C构成的OLED电路为例，参见表1，当膜层裂纹较轻微时TFE薄膜裂缝不明显，此时，PCD走线103和数据线的电阻变化不明显(序号4～9)，对应列像素单元的颜色变化不明显，检测人员认为该阵列基板为良品。
表1 膜层Crack对PCD走线的电阻值的影响
Figure PCTCN2019074200-appb-000001
这样，OLED产品在高温信赖性试验中或在后续的使用中，膜层裂纹恶化会引起基板Panel不良，使基板Panel存在报废风险。
在发明人已知的技术中，PCD走线与显示区域中源漏极层采用同一构图工艺形成，即非显示区域102内的PCD走线与显示区域101内源漏极层同层设置。为有更好的导电性能和延展性能，显示区域101内源漏极层通常采用Ti/Al/Ti结构。从而，PCD走线同样采用了Ti/Al/Ti结构(如图2所示)，其良好的延展性能能够缓冲膜层Crack时的受力，导致PCD走线在受到相同的力作用下Crack比较轻微，电阻变化较小，Crack较难被检出。
本公开的至少一个实施例提供了一种阵列基板，参见图3A、图3B和图3C，包括：基底304以及形成在所述基底304上的显示区域301和围绕显示区域301的非显示区域302。参见图3A和图3B，该阵列基板还包括设置在非显示区域302中的检测线305，所述检测线305设置在所述基底304上。检测线305中远离基底304的表面设置为起伏状306。参见图3C，图3C示出了在图3A中B-B’方向上的金相图，由于检测线305的表面设置为起伏状306，导致该检测线305不同部位的延展性不同。在受到外力时，参见图3D，检测线的位于外力附近的延展性较弱的部分更易产生裂缝(虚线框内部区域)，从而使检测线的电阻值发生显著变化。换言之，在根据本公开实施例 的阵列基板中，更容易检测出膜层Crack较轻微时引起的TFE裂缝的问题，提高了检测膜层Crack的灵敏度，能够降低漏检率。
上述起伏状306可以为波浪形、台阶型(高台阶和低台阶间隔设置)等。在本公开的一个实施例中，起伏状306设置为波浪形。
在本公开的一个实施例中，继续参见图3B，阵列基板还包括调整层307。该调整层307设置在基底304之上，检测线305设置在调整层307之上。其中，调整层307可以采用多晶硅P-Si(Polycrystalline Silicon)制成，因此该调整层307可以与显示区域301内的有源层(图中未示出)采用同一构图工艺形成。参见图3B，调整层307远离基底304的表面设置为起伏状，这样检测线305靠近和远离基底的表面都有起伏状。本实施例中通过设置调整层307为起伏状态，从而在调整层307上形成检测线305时，可以使检测线305靠近和远离基底304的表面均为起伏状。
在本公开的一个实施例中，继续参见图3B，阵列基板还包括第一缓冲层308。该第一缓冲层308可以设置在调整层307和基底304之间，并且该第一缓冲层308可以与显示区域304内的第二缓冲层buffer(图中未示出)采用同一构图工艺形成。这样第一缓冲层308可以增加调整层307和基底304之间的粘合力，防止调整层307脱落。
可理解的是，由于检测线305采用了起伏状设置，即使检测线305仍然采用Ti/Al/Ti结构，同样可以提高检测膜层Crack的灵敏度。
为进一步提升检测灵敏度，在本公开的一个实施例中，检测线305由金属钼制成，此时，检测线305与显示区域301内的栅极层(图中未示出)或者像素电极层采用同一构图工艺形成。
在本公开的一个实施例中，检测线305与显示区域301内的栅极层采用同一构图工艺制成，如图4(a)～(e)所示，形成所述检测线305的过程包括：
步骤一，参见图4(a)，采用等离子增强化学气相沉积法(Plasma Enhanced Chemical Vapor Deposition，PECVD)在基底上形成第一缓冲层。该第一缓冲层与显示区域内的第二缓冲层采用同一构图工艺形成。其中，基底可以采用聚酯纤维等材料制成，第一缓冲层和第二缓冲层可以采用氧化硅(SiOx)和/或氮化硅(SiNx)材料制成。
步骤二，参见图4(b)，采用PECVD方法在第一缓冲层上形成调整层。该调整层与显示区域内有源层由同一构图工艺形成。其中，调整层可以采用多晶硅(P-Si)材料制成。
步骤三，参见图4(c)，在调整层远离基底的一面形成起伏状。例如，使用半色调(Halftone)工艺，即在ACT Mask工艺时对非显示区域内检测线区域交替形半曝光，构图如图5所示。在进行ACT Dry Etch(干法刻蚀)时，由于Halftone工艺，P-Si表面会形成高低起伏状。
步骤四，参见4(d)，采用PECVD方法在调整层上形成栅绝缘层。该栅绝缘层与显示区域内栅绝缘层采用同一构图工艺形成。其中，栅绝缘层可以采用氧化硅(SiOx)和/或氮化硅(SiNx)材料制成。
步骤五，参见4(e)，采用溅射方法(Sputter)在栅绝缘层上形成检测线，此时检测线底部(靠近基底的表面)会形成高低起伏状。
在本公开的一个实施例中，检测线305与显示区域301内的像素电极层采用同一构图工艺制成。检测线305与显示区域301内的像素电极层采用同一构图工艺制成与检测线305与显示区域301内的栅极层采用同一构图工艺制成的区别在于：
步骤五中，采用溅射方法(Sputter)在栅绝缘层上形成检测线2时，对应显示区域内的像素电极层的构图工艺。可以参考检测线305与显示区域301内的栅极层采用同一构图工艺制成的实施例实现检测线305与显示区域301内的栅极层采用同一构图工艺制成，在此不再赘述。
在本公开的另一个实施例中，继续参见图3A，阵列基板还包括扇出区域308。参见图6，扇出区域308包括基底701、第一缓冲层702、调整层703和检测线704。其中，第一缓冲层702可以与显示区域内的栅绝缘层采用同一构图工艺形成，调整层703可以与显示区域内的有源层采用同一构图工艺形成。第一缓冲层702设置在基底701上；调整层703设置在第一缓冲层702上，且远离基底701的表面设置为起伏状，相应地，检测线704靠近和远离第一缓冲层702的表面设置为起伏状态。形成所述扇出区域的工艺包括：
在Pad bending工艺中，增加EBA Mask(Edge Bending A Mask)对非显示区域内的有源层钻孔，即在EBA Mask中进行Halftone工艺，构型如图5所示，使有源层远离基底的表面形成起伏状，进而使检测线704底部为高低 起伏状的效果。
可理解的是，上述检测线704还可以与显示区域内的像素电极层采用同一构图工艺制成。相应地，调整层703可以与显示区域内的层间介电层ILD(像素电极间的介电材料)采用同一构图工艺形成。制成工艺参见调整层703对应显示区域内有源层的实施例，在此不再赘述。
需要说明的是，本实施例中阵列基板显示区域内的薄膜晶体管(TFT)采用顶栅结构，非显示区域内检测线走线也与之相对应。当然，在TFT晶体管的结构改变时，非显示区域内检测线走线也随之变化。
本公开的至少一个实施例还提供了一种显示面板，该显示面板包括阵列基板。其中，阵列基板为上述阵列基板。该显示面板可以用于手机、电脑、平板电脑、电视机等显示装置中。
在本公开中，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性。术语“多个”指两个或两个以上，除非另有明确的限定。在本公开中，虚线连接的两个部件是存在电连接或者接触关系的，采用虚线仅是为了使附图更清楚，更易理解本公开实施例的方案。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

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  1. 一种阵列基板，包括基底以及形成在所述基底上的显示区域和围绕所述显示区域的非显示区域；其中，所述非显示区域包括设置在所述基底上的检测线，所述检测线远离所述基底的表面设置为起伏状。
  2. 根据权利要求1所述的阵列基板，其中，所述非显示区域还包括调整层；所述调整层设置在所述基底之上，且所述调整层与所述显示区域内的有源层采用同一构图工艺制成；所述检测线设置在所述调整层之上；
    所述调整层远离所述基底的表面设置为起伏状，所述检测线靠近和远离所述基底的表面均设置为起伏状。
  3. 根据权利要求1或2所述的阵列基板，其中，所述非显示区域还包括第一缓冲层；所述第一缓冲层设置在所述调整层和所述基底之间，且所述第一缓冲层与所述显示区域内的第二缓冲层采用同一构图工艺制成。
  4. 根据权利要求1至3中任何一项所述的阵列基板，其中，所述检测线与所述显示区域内栅极层采用同一构图工艺制成。
  5. 根据权利要求1至3中任何一项所述的阵列基板，其中，所述检测线与所述显示区域内的像素电极层采用同一构图工艺制成。
  6. 根据权利要求1至5中任何一项所述的阵列基板，其中，所述阵列基板还包括扇出区域；所述扇出区域包括基底、第一缓冲层、调整层和检测线；所述第一缓冲层设置在所述基底上，所述调整层设置在所述第一缓冲层上，且远离所述基底的表面设置为起伏状，所述检测线靠近和远离所述基底的表面均设置为起伏状。
  7. 根据权利要求1至6中任何一项所述的阵列基板，其中，所述起伏状为波浪形。
  8. 根据权利要求1至7中任何一项所述的阵列基板，其中，所述检测线采用金属钼制成。
  9. 一种显示装置，其包括权利要求1～8任一项所述的阵列基板。
  10. 一种形成阵列基板的方法，所述阵列基板包括基底以及形成在所述基底上的显示区域和围绕所述显示区域的非显示区域；其中，所述非显示区域包括设置在所述基底上的检测线；所述方法包括：
    在所述基底的位于非显示区域的部分上形成第一缓冲层；
    在所述第一缓冲层上形成调整层；
    在所述调整层的远离所述基底的表面上形成起伏状；
    在所述调整层上形成绝缘层；以及
    在所述绝缘层上形成所述检测线，其中所述检测线远离所述基底的表面设置为起伏状。
  11. 根据权利要求10所述的形成阵列基板的方法，其中，采用等离子增强化学气相沉积法形成第一缓冲层，所述第一缓冲层和位于所述显示区域内的第二缓冲层采用同一构图工艺形成。
  12. 根据权利要求10或11所述的形成阵列基板的方法，其中，采用PECVD方法在第一缓冲层上形成调整层，所述调整层和位于所述显示区域内的有源层通过同一构图工艺形成。
  13. 根据权利要求10至12中任何一项所述的形成阵列基板的方法，其中，使用半色调工艺在所述调整层远离基底的一面形成起伏状。
  14. 根据权利要求10至13中任何一项所述的形成阵列基板的方法，其中，采用PECVD方法在调整层上形成绝缘层，所述绝缘层与显示区域内的栅绝缘层采用同一构图工艺形成。
  15. 根据权利要求10至14中任何一项所述的形成阵列基板的方法，其中，采用溅射方法在绝缘层上形成检测线，所述检测线与所述显示区域内的栅极层通过同一构图工艺形成。
  16. 根据权利要求10至15中任何一项所述的形成阵列基板的方法，其中，所述检测线由金属钼制成。
  17. 根据权利要求10至16中任何一项所述的形成阵列基板的方法，其中，所述起伏状为波浪形。
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