WO2019227946A1 - 显示面板及其驱动方法、显示装置 - Google Patents

显示面板及其驱动方法、显示装置 Download PDF

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Publication number
WO2019227946A1
WO2019227946A1 PCT/CN2019/071806 CN2019071806W WO2019227946A1 WO 2019227946 A1 WO2019227946 A1 WO 2019227946A1 CN 2019071806 W CN2019071806 W CN 2019071806W WO 2019227946 A1 WO2019227946 A1 WO 2019227946A1
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Prior art keywords
sub
light
transistor
circuit
emitting
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PCT/CN2019/071806
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English (en)
French (fr)
Inventor
陈亮
王磊
刘冬妮
肖丽
陈小川
玄明花
杨盛际
卢鹏程
赵德涛
丛宁
Original Assignee
京东方科技集团股份有限公司
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Priority to US16/484,983 priority Critical patent/US11508298B2/en
Publication of WO2019227946A1 publication Critical patent/WO2019227946A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
    • G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
    • G09G3/204—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames being organized in consecutive sub-frame groups
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0814—Several active elements per pixel in active matrix panels used for selection purposes, e.g. logical AND for partial update
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes

Definitions

  • Embodiments of the present disclosure relate to a display panel, a driving method thereof, and a display device.
  • OLED display devices have gradually received people's attention due to their advantages such as wide viewing angles, high contrast, fast response speed, and higher luminous brightness and lower driving voltage than inorganic light-emitting display devices. extensive attention. Due to the above characteristics, organic light emitting diodes (OLEDs) can be applied to devices with display functions such as mobile phones, displays, notebook computers, digital cameras, instruments and meters.
  • the pixel driving circuit in the OLED display device generally adopts a matrix driving method, and is divided into an active matrix (AM) drive and a passive matrix (PM) drive according to whether a switching element is introduced in each pixel unit.
  • AM active matrix
  • PM passive matrix
  • AMOLED integrates a set of thin-film transistors and storage capacitors in the pixel drive circuit of each pixel unit. By driving and controlling the thin-film transistors and storage capacitors, the control of the current flowing through the OLED is achieved, so that the OLED Glow as needed.
  • AMOLED Compared with PMOLED, AMOLED requires less driving current, lower power consumption, and longer life, which can meet the large-scale display requirements of high resolution and multi-gray scale. At the same time, AMOLED has obvious advantages in terms of viewing angle, color reduction, power consumption, and response time. It is suitable for high information content and high resolution display devices.
  • At least one embodiment of the present disclosure provides a display panel including a plurality of sub-pixel unit groups arranged in an array, the array including multiple rows and columns, and each of the sub-pixel unit groups including N sub-pixels arranged along a column direction.
  • a pixel unit and a pixel driving circuit each of the sub-pixel units including a light-emitting circuit, the pixel-driving circuit being electrically connected to the light-emitting circuits in the N sub-pixel units, and configured to be connected to the N sub-pixel units
  • the light-emitting circuit provides a light-emitting driving current;
  • the display panel further includes a gating circuit and a light-emitting control line correspondingly provided for each row of the sub-pixel unit group, and the gate circuit is electrically connected to the light-emitting control line and is corresponding to the corresponding row.
  • the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group are electrically connected, and are configured to control the corresponding rows of the corresponding rows under the control of a gating control signal and a light-emitting control signal provided by the light-emitting control line.
  • the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group are driven by the pixel driving circuit to emit light in a time-sharing manner; N is an integer equal to or greater than 2 .
  • the gate circuits are respectively electrically connected to the light-emitting control terminals of the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group of the corresponding row, and are configured.
  • the light-emitting control signal is applied to the light-emitting control terminals of the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group in a time-sharing manner.
  • the display panel provided by an embodiment of the present disclosure further includes a gate driving circuit.
  • the gate driving circuit includes a plurality of cascaded gate driving sub-circuits. Each row of the sub-pixel unit group is correspondingly provided with one of the gate driving sub-circuits, and the gate driving sub-circuits are configured to provide corresponding rows.
  • a gating circuit corresponding to the sub-pixel unit group provides the gating control signal.
  • the display panel provided by an embodiment of the present disclosure further includes a light emission control driving circuit.
  • the light emission control driving circuit includes a plurality of cascaded light emission control driving sub-circuits. Each row of the sub-pixel unit group is correspondingly provided with one of the light emission control driving sub-circuits, and the light emission control driving sub-circuits correspond to the corresponding rows of the sub-pixel unit.
  • the light emission control line corresponding to the sub-pixel unit group is electrically connected, and is configured to provide the light emission control signal to the light emission control line.
  • a display panel provided by an embodiment of the present disclosure further includes a gate driving circuit.
  • the gate driving circuit includes a plurality of cascaded shift register units, and each row of the sub-pixel unit group is correspondingly provided with one of the shift register units, and the shift register units are configured to provide the shift register units to the corresponding rows.
  • the pixel driving circuit in the sub-pixel unit group provides a gate scan signal.
  • the pixel driving circuit includes a light-emitting driving circuit, a data writing circuit, a compensation circuit, a reset circuit, and a light-emitting control circuit;
  • the light-emitting driving circuit includes a driving control terminal, a first One end and a second end, and configured to control the light emission driving current flowing through the first end and the second end;
  • the data writing circuit is configured to write a data signal in response to a gate scan signal Into the driving control terminal of the light-emitting driving circuit;
  • the compensation circuit is configured to store the written data signal and compensate the light-emitting driving circuit in response to the gate scan signal;
  • the reset circuit is configured Applying a reset voltage to a drive control terminal of the light emitting drive circuit in response to a reset signal; and the light emitting control circuit configured to apply a first voltage to a first of the light emitting drive circuit in response to the light emitting control signal end.
  • the light-emitting driving circuit includes a first transistor, and a gate of the first transistor is connected as a driving control terminal of the light-emitting driving circuit to a first node.
  • a first pole of a first transistor is connected as a first end of the light emitting driving circuit and a second node, and a second pole of the first transistor is connected as a second end of the light emitting driving circuit and a third node;
  • the data writing circuit includes a second transistor, the gate of the second transistor is configured to be connected to the scanning signal terminal to receive the gate scanning signal, and the first electrode of the second transistor is configured to be connected to the data signal terminal.
  • the compensation circuit includes a third transistor and a storage capacitor, the gate of the third transistor is configured to scan A signal terminal is connected to receive the gate scanning signal, a first pole of the third transistor is connected to the third node, and a second pole of the third transistor is connected to the storage capacitor.
  • the reset circuit includes a fourth transistor, and the gate of the fourth transistor is configured to be connected to the reset control terminal to receive all The reset signal, a first pole of the fourth transistor is connected to a first node, and a second pole of the fourth transistor is configured to be connected to a reset voltage terminal to receive the reset voltage; and the light emitting control circuit includes A fifth transistor, a gate of the fifth transistor is configured to be connected to the light emission control line to receive the light emission control signal, and a first electrode of the fifth transistor is configured to be connected to the first voltage terminal To receive the first voltage, a second pole of the fifth transistor is connected to a second node.
  • N 2
  • two sub-pixel units in each of the sub-pixel unit groups include a first light-emitting sub-circuit and a second light-emitting sub-circuit, respectively.
  • the light-emitting sub-circuit includes a first switching circuit and a first light-emitting element.
  • the second light-emitting sub-circuit includes a second switching circuit and a second light-emitting element. The first switching circuit and the second switching circuit and the light-emitting drive. The second end of the circuit is electrically connected.
  • the first switching circuit includes a sixth transistor, and a gate of the sixth transistor is configured to receive the light emission control signal.
  • One pole is connected to the second end of the light-emitting driving circuit, the second pole of the sixth transistor is connected to the first pole of the first light-emitting element, and the second pole of the first light-emitting element and the second voltage Terminal is connected to receive a second voltage;
  • the second switching circuit includes a seventh transistor, a gate of the seventh transistor is configured to receive the light emission control signal, a first pole of the seventh transistor and the light emission The second terminal of the driving circuit is connected, the second electrode of the seventh transistor is connected to the first electrode of the second light emitting element, and the second electrode of the second light emitting element is connected to the second voltage terminal to receive the second Voltage.
  • the gating circuit includes a first gating sub-circuit and a second gating sub-circuit, the first gating sub-circuit and the light emitting control line, and all The first switch circuit is electrically connected, and the second gating sub-circuit is electrically connected to the light emitting control line and the second switch circuit.
  • the gating control signal includes a first gating control signal
  • the first gating subcircuit includes an eighth transistor, and a gate of the eighth transistor is Configured to receive the first gating control signal, a first pole of the eighth transistor is electrically connected to the light emitting control line, and a second pole of the eighth transistor is electrically connected to the first switching circuit
  • the second gating sub-circuit includes a ninth transistor, a gate of the ninth transistor is configured to receive the first gating control signal, and the first pole of the ninth transistor is electrically connected to the light emission control line.
  • the second pole of the ninth transistor is electrically connected to the second switching circuit; wherein one of the eighth transistor and the ninth transistor is a P-type transistor, and the other is an N-type transistor.
  • the gating control signal includes a first gating control signal and a second gating control signal;
  • the first gating sub-circuit includes an eighth transistor, and the The gate of the eighth transistor is configured to receive the first gating control signal, the first pole of the eighth transistor is electrically connected to the light emission control line, and the second pole of the eighth transistor is connected to the first gate.
  • a switch circuit is electrically connected;
  • the second gating sub-circuit includes a ninth transistor, a gate of the ninth transistor is configured to receive the second gating control signal, a first pole of the ninth transistor and The light emitting control line is electrically connected, and the second pole of the ninth transistor is electrically connected to the second switching circuit.
  • the first gating sub-circuit further includes a tenth transistor, and a gate of the tenth transistor is configured to receive the second gating control signal, so The first pole of the tenth transistor is connected to the second pole of the eighth transistor, and the second pole of the tenth transistor is connected to a third voltage terminal to receive a third voltage;
  • the second gating sub-circuit is also Comprising an eleventh transistor, a gate of the eleventh transistor is configured to receive the first gating control signal, a first pole of the eleventh transistor is connected to a second pole of the ninth transistor, A second pole of the eleventh transistor is connected to the third voltage terminal to receive the third voltage.
  • At least one embodiment of the present disclosure also provides a display device including any display panel described in the embodiments of the present disclosure.
  • At least one embodiment of the present disclosure also provides a method for driving a display panel, which includes: dividing a frame display scan into N sub-frames; and in the N sub-frames, a pixel driving circuit of each of the sub-pixel unit groups Providing the light-emitting driving current to the light-emitting circuits of the N sub-pixel units in each of the sub-pixel unit groups according to the provided data signals, and the gating circuit is controlled by a gating control signal and the light-emitting control signal, The light-emitting circuits controlling the N sub-pixel units in the sub-pixel unit group of the corresponding row are driven by the pixel driving circuit to emit light in a time-sharing manner.
  • N 2
  • the light-emitting circuits in the sub-pixel units in the odd-numbered rows and the light-emitting circuits in the sub-pixel units in the even-numbered rows are in two different sub-pixels, respectively. Light is emitted within the frame.
  • FIG. 1 is a schematic diagram of a display panel
  • FIG. 2 is a circuit diagram of a pixel driving circuit
  • FIG. 3 is a schematic diagram of a display panel provided by some embodiments of the present disclosure.
  • FIG. 4 is a schematic diagram of another display panel provided by some embodiments of the present disclosure.
  • FIG. 5 is a schematic diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 6 is a schematic diagram of a light emitting control driving circuit provided by some embodiments of the present disclosure.
  • FIG. 7 is a schematic diagram of a gate driving circuit provided by some embodiments of the present disclosure.
  • FIG. 8 is a schematic block diagram of a pixel driving circuit provided by some embodiments of the present disclosure.
  • FIG. 9 is a schematic block diagram of a gating circuit provided by some embodiments of the present disclosure.
  • FIG. 10 is a circuit diagram of an implementation example of a pixel driving circuit, a gating circuit, and a light emitting circuit in a display panel provided by some embodiments of the present disclosure
  • FIG. 11 is a circuit diagram of an implementation example of a pixel driving circuit, a gating circuit, and a light emitting circuit in another display panel provided by some embodiments of the present disclosure
  • FIG. 12A is a timing diagram of signals corresponding to FIG. 10 and FIG. 11; FIG.
  • FIG. 12B is a signal timing chart of the gate control signals output by the two-stage gate driving sub-circuits
  • FIG. 13 is a circuit diagram of an implementation example of a pixel driving circuit, a gating circuit, and a light emitting circuit in a display panel according to some embodiments of the present disclosure
  • FIG. 14 is a signal timing diagram corresponding to FIG. 13;
  • FIG. 15 is a schematic diagram of a display device provided by some embodiments of the present disclosure.
  • FIG. 16 is a schematic diagram of a driving method provided by some embodiments of the present disclosure.
  • AMOLED uses thin-film transistors (TFTs) to construct light-emitting drive circuits to provide corresponding light-emitting drive currents to OLED devices.
  • TFTs thin-film transistors
  • LTPS TFTs and Oxide TFTs have higher mobility and more stable characteristics, so they are more suitable for application in AMOLED displays.
  • the threshold voltage may also drift, which may cause poor display. For example, a mura phenomenon (uneven display brightness) or an afterimage phenomenon occurs.
  • a pixel driving circuit needs to be provided for each sub-pixel unit to eliminate the non-uniformity of the transistor or the drift of the threshold voltage of the transistor to a certain extent.
  • R1, R2, R3, and R4 represent the sub-pixel units of the first, second, third, and fourth rows in the display panel, respectively.
  • the sub-pixel unit in the first row and the two sub-pixel units in the same row in the second row can share a pixel driving circuit.
  • the sub-pixel unit in the third row and the sub-pixel unit in the fourth row can share a pixel driving circuit, and so on, that is, the pixel driving circuit is reused between every two adjacent rows of sub-pixel units.
  • the above pixel driving circuit may adopt the circuit structure shown in FIG. 2.
  • the pixel driving circuit is composed of seven transistors (first transistor T1 to seventh transistor T7) and a storage capacitor C1, where the first transistor T1 to the The five transistors T5 and the storage capacitor C1 are common to the two sub-pixel units.
  • the sixth transistor and the seventh transistor control the two light emitting elements (D1 and D2) to emit light in a time-sharing manner.
  • EM3 light emission control signal
  • Lighting control signals EM1 and EM2 are provided.
  • the light emission control driving sub-circuit EOA1 and the control terminal (ie, the gate) of the sixth transistor T6 can be electrically connected to provide the light emission control signal EM1.
  • the control terminals (ie, gates) of the second transistor T2 and the third transistor T3 need to be connected to the scan signal terminal GATE to receive the gate scan signal. Accordingly, as shown in FIG. 1, a shift register unit GOA needs to be provided for every two rows of sub-pixel units, and the shift register unit GOA provides a gate scan signal to the pixel driving circuit.
  • At least one embodiment of the present disclosure provides a display panel.
  • the display panel includes a plurality of sub-pixel unit groups arranged in an array.
  • the array includes multiple rows and columns.
  • Each sub-pixel unit group includes N sub-pixel units and pixel driving circuits arranged along the column direction.
  • Each sub-pixel unit includes a light-emitting circuit.
  • the pixel driving circuit is electrically connected to the light-emitting circuits in the N sub-pixel units, and is configured to provide the light-emitting driving current to the light-emitting circuits in the N sub-pixel units.
  • the display panel further includes a gating circuit and a light emitting control line correspondingly provided for each row of the sub-pixel unit group, the gating circuit is electrically connected to the light-emitting control line, and is electrically connected to the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group of the corresponding row. And is configured to control the light-emitting circuits of the N sub-pixel units in the sub-pixel unit group of the corresponding row to be driven by the pixel driving circuit to emit light under the control of the gating control signal and the light-emitting control signal provided by the light-emitting control line; N is an integer of 2 or more.
  • Embodiments of the present disclosure also provide a display device and a driving method corresponding to the above display panel.
  • the display panel, the driving method and the display device provided by the embodiments of the present disclosure can reduce the number of light emission control driving sub-circuits provided when the pixel driving circuit is multiplexed, so that the frame of the display panel is narrower, and the display panel can be improved. Resolution.
  • At least one embodiment of the present disclosure provides a display panel 10.
  • the display panel 10 includes a plurality of sub-pixel unit groups 100 arranged in an array, and the array includes a plurality of rows and a plurality of columns.
  • FIG. 3 only schematically shows two rows and two columns of the sub-pixel unit groups 100.
  • the embodiment of the present disclosure does not limit the number of the sub-pixel unit groups 100, for example, the sub-pixel units in the display panel 10
  • the number of groups 100 can be set according to the requirements of resolution.
  • each sub-pixel unit group 100 includes N sub-pixel units 110 and pixel driving circuits 120 arranged along the column direction.
  • Each sub-pixel unit 110 includes a light-emitting circuit 130, and the pixel driving circuit 120 and the light-emitting circuits 130 of the N sub-pixel units 110. It is electrically connected and configured to provide a light emitting driving current to the light emitting circuit 130 in the N sub-pixel units 110.
  • N is an integer of 2 or more.
  • the display panel 10 further includes a gate circuit 200 and a light-emitting control line EL correspondingly provided for each row of the sub-pixel unit group 100.
  • the gate circuit 200 is electrically connected to the light-emission control line EL and is connected to N
  • the light-emitting circuits 130 of the pixel units 110 are electrically connected, and are configured to control the light emission of the N sub-pixel units 110 in the sub-pixel unit group 100 of the corresponding row under the control of the gating control signal and the light-emitting control signal provided by the light-emitting control line EL.
  • the circuit 130 is driven by the pixel driving circuit 120 in time division to emit light.
  • N is an integer of 2 or more.
  • the pixel driving circuit 120 and the two sub-pixel units 110 The light-emitting circuit 130 is electrically connected, that is, two sub-pixel units 110 in each sub-pixel unit group 100 share one pixel driving circuit 120.
  • the gate circuit 200 is electrically connected to the light-emitting circuits 130 in the two sub-pixel units 110 in the sub-pixel unit group 100 of the corresponding row.
  • FIG. 3 only shows that the gate circuit 200 is electrically connected to the light-emitting circuits 130 in the first column of the sub-pixel unit group 100 in the corresponding row of the sub-pixel unit group 100.
  • the gate circuit 200 is also It is electrically connected to the light-emitting circuits 130 in the sub-pixel unit group 100 in other rows in the row.
  • the embodiment of the present disclosure does not limit the setting position of the gating circuit 200, and the gating circuit 200 may be disposed at any one end (for example, the start end or the end) of each row of the sub-pixel unit group 100. The following embodiments and This is the same and will not be described again.
  • the gate circuit 200 is electrically connected to the light-emission control terminals ET of the light-emitting circuits 130 in the two sub-pixel units 110 in the corresponding sub-pixel unit group 100 of the corresponding row, and is configured to divide the light-emission control signals. Is applied to the light-emitting control terminals ET of the light-emitting circuits 130 in the two sub-pixel units 110 in the row of the sub-pixel unit groups 100 at this time.
  • a frame display scan may be divided into two sub-frames, such as a first sub-frame and a second sub-frame, such as a first sub-frame and The second sub-frame may be alternated in timing.
  • the gating circuit 200 may apply the light-emission control signal provided on the light-emission control line EL to the sub-pixel unit in the first sub-frame.
  • the light emitting control signal provided on the light emitting control line EL may be applied to the light emitting control terminal ET of another light emitting circuit 130 in the sub-pixel unit group 100, so that the The light emitting circuit 130 is turned on, so that the pixel driving circuit 120 can provide a light emitting driving current to the light emitting circuit 130 to emit light.
  • the gate circuit 200 controls the light-emitting circuit 130 in the same manner as described above, and details are not described again.
  • the sub-pixel units 110 in the first row of the display panel 10 in the first sub-frame can be light-emitting displayed, and then the sub-pixel units 110 in the second row in the display panel 10 are made in the second sub-frame.
  • the pixel unit 110 performs light-emitting display, and then causes the sub-pixel unit 110 in the third row in the display panel 10 to perform light-emitting display in the first sub-frame, and then causes the sub-pixel in the fourth row in the display panel 10 in the second sub-frame.
  • the pixel unit 110 performs light-emitting display, and so on, that is to say, in the first sub-frame, the sub-pixel units 110 in the odd-numbered rows of the display panel 10 can be light-emitting displayed, and in the second sub-frame, the display panel 10
  • the sub-pixel units 110 located in the even-numbered rows perform light emission display, thereby completing one frame display scan.
  • the gating circuit 200 is electrically connected to the light-emitting control terminals ET of the light-emitting circuits 130 in the three sub-pixel units 110 in the corresponding sub-pixel unit group 100 of the corresponding row, and is configured to divide the light-emitting control signals. It is applied to the light-emitting control terminals ET of the light-emitting circuits 130 in the three sub-pixel units 110 in the row of the sub-pixel unit groups 100 at a time.
  • one frame of the display scan may be divided into three sub-frames, such as a first sub-frame, a second sub-frame, and a third sub-frame, respectively.
  • the first subframe, the second subframe, and the third subframe may be alternated in time.
  • the gating circuit 200 may apply the gating control signal to the light-emitting control line EL.
  • the provided light-emitting control signals are respectively applied to the light-emitting control terminals ET of the three light-emitting circuits 130 in the sub-pixel unit group 100, so that the corresponding light-emitting circuits 130 are turned on, so that the pixel driving circuit 120 can connect the turned-on light-emitting circuits 130.
  • a light emission driving current is provided to emit light.
  • the gate circuit 200 controls the light-emitting circuit 130 in the same manner as described above, and details are not described herein again.
  • the sub-pixel units 110 in the 3n-2th row of the display panel 10 in the first sub-frame can be light-emitting displayed, and the 3n-1 in the display panel 10 can be positioned in the second sub-frame.
  • the sub-pixel units 110 in the row perform light-emitting display, and the sub-pixel units 110 in the 3nth row of the display panel 10 are caused to perform light-emitting display in the third sub-frame, thereby completing one frame display scan, where n is an integer greater than zero.
  • each sub-pixel unit group 100 may further include four, five, or more sub-pixel units 110.
  • a plurality of light-emitting circuits in the sub-pixel unit group can be provided with light-emitting control signals in a time-sharing manner, so that the multiple light-emitting circuits can Light is emitted in different sub-frames, so that when the number of pixel driving circuits provided on the display panel is constant, more sub-pixel units can be set corresponding to each pixel driving circuit, thereby improving the resolution of the display panel. rate.
  • a gating circuit may be provided for each row of sub-pixel unit groups in the display panel, thereby improving the resolution of all areas of the entire display panel.
  • the embodiments of the present disclosure include: Not limited to this, for example, a gating circuit may be provided only for a sub-pixel unit group in a partial region of the display panel, so that the resolution of only the partial region may be improved.
  • the display panel 10 provided by the embodiment of the present disclosure further includes a gate driving circuit 300.
  • the gate driving circuit includes a plurality of cascaded gate driving sub-circuits 310.
  • each row of sub-pixel unit groups 100 is provided with a gate driving sub-circuit 310, and the gate-driving sub-circuit 310 is configured to correspond to the gate circuit 200 of the corresponding sub-pixel unit group 100.
  • the gate control signals provided by two gate driving sub-circuits 310 in adjacent cascades are staggered from each other by a fixed time interval.
  • the display panel 10 provided by the embodiment of the present disclosure further includes a light emission control driving circuit 400.
  • the light emission control driving circuit 400 includes a plurality of cascaded light emission control driving sub-circuits 410. As shown in FIG. 3 and FIG. 4, each row of the sub-pixel unit group 100 is correspondingly provided with a light-emitting control driving sub-circuit 410, and the light-emitting control driving sub-circuit 410 is electrically connected to the light-emitting control line EL corresponding to the corresponding sub-pixel unit group 100. And it is configured to provide a light emission control signal to the light emission control line EL.
  • the light emission control signal transmitted through the light emission control line EL is provided to the pixel driving circuit 120 in each row of the sub-pixel unit group 100 in addition to the gate circuit 200, for example, to turn on the pixel driving circuit 120 during the light-emitting stage.
  • each row of the sub-pixel unit groups only needs to be provided with one light-emitting control driving sub-circuit 410, which can further reduce the frame width of the display panel, thereby further improving the resolution.
  • the display panel 10 provided by the embodiment of the present disclosure further includes a gate driving circuit 500.
  • the gate driving circuit 500 includes a plurality of cascaded shift register units 510. As shown in FIG. 3 and FIG. 4, each row of the sub-pixel unit group 100 is correspondingly provided with a shift register unit 510.
  • the shift register unit 510 is configured to provide a gate to the pixel driving circuit 120 in the sub-pixel unit group 100 of the corresponding row. Scan signal.
  • the gate scan signal provided by the cascaded shift register unit 510 is shifted step by step, so that the multi-row sub-pixel unit group of the display panel can perform light-emitting display row by row.
  • the gate driving circuit 500 in the embodiment of the present disclosure may adopt a conventional design, as long as it is a gate scanning signal that can provide stepwise shift.
  • the pixel driving circuit 120 is a pixel driving circuit having a compensation function.
  • the compensation function may be implemented by voltage compensation, current compensation, or hybrid compensation.
  • the pixel circuit having the compensation function may be, for example, 4T1C or 4T2C.
  • the pixel driving circuit 120 includes a light-emitting driving circuit 121, a data writing circuit 122, a compensation circuit 123, a reset circuit 124, and a light-emitting control circuit 125.
  • the light emitting driving circuit 121 includes a driving control terminal 1210, a first terminal 1211, and a second terminal 1212, and is configured to control a light emitting driving current flowing through the first terminal 1211 and the second terminal 1212.
  • the light-emitting driving circuit 121 may provide a light-emitting driving current to the light-emitting element in the light-emitting circuit 130 to drive the light-emitting element to emit light, and may emit light according to a required "gray scale".
  • the data writing circuit 122 is configured to write a data signal to the driving control terminal 1210 of the light emitting driving circuit 121 in response to a gate scan signal.
  • the data writing circuit 122 is connected to the scanning signal terminal GATE and the data signal terminal DATA.
  • the data writing circuit 122 is turned on in response to the gate scanning signal input from the scanning signal terminal GATE, so that The data signal input from the data signal terminal DATA is written into the driving control terminal 1210 of the light-emitting driving circuit 121 and stored in the compensation circuit 123 to generate a light-emitting driving current that drives the light-emitting circuit 130 to emit light according to the data signal during the light-emitting stage, for example.
  • the compensation circuit 123 is configured to store the written data signal and compensate the light emitting driving circuit 121 in response to the gate scan signal.
  • the compensation circuit 123 may be turned on in response to a gate scan signal inputted from the scan signal terminal GATE, so that the data write circuit 122
  • the written data signal is stored in a storage capacitor.
  • the compensation circuit 123 can electrically connect the driving control terminal 1210 and the second terminal 1212 of the light-emitting driving circuit 121, so that the information about the threshold voltage of the light-emitting driving circuit 121 can be stored accordingly.
  • the light-emitting driving circuit 121 can be controlled by using the stored data signal and the threshold voltage in the light-emitting stage, so that the light-emitting driving circuit 121 is compensated.
  • the reset circuit 124 is configured to apply a reset voltage to the driving control terminal 1210 of the light emitting driving circuit 121 in response to a reset signal.
  • the reset circuit 124 is connected to the reset control terminal RST and the reset voltage terminal VINT.
  • the reset circuit 124 can be turned on in response to a reset signal input from the reset control terminal RST, so that the reset input of the reset voltage terminal VINT can be reset.
  • a voltage is applied to the driving control terminal 1210 of the light-emitting driving circuit 121.
  • the reset circuit 124 in the pixel driving circuit 120 in the sub-pixel unit group 100 in this row may not be connected to the reset control terminal RST, but may be connected to the sub-pixel unit in the previous row.
  • the scanning signal terminal GATE in the pixel driving circuit 120 in the group 100 is connected, that is, the gate scanning signal corresponding to the sub-pixel unit group 100 in the previous row is used as the reset signal.
  • the embodiment of the present disclosure does not limit the manner in which the reset signal is applied.
  • the light emission control circuit 125 is configured to apply a first voltage to the first terminal 1211 of the light emission driving circuit 121 in response to a light emission control signal.
  • the light-emission control circuit 125 is electrically connected to the light-emission control line EL so that it can receive the light-emission control signal provided on the light-emission control line EL.
  • the light-emission control circuit 125 is also connected to the first voltage terminal VDD to receive the first voltage.
  • the light-emitting control circuit 125 may be turned on in response to the light-emitting control signal, so that a first voltage may be applied to the first terminal 1211 of the light-emitting driving circuit 121.
  • the potential of the second terminal 1212 is also the first voltage. Then, the light emitting driving circuit 121 applies this first voltage to the light emitting element in the light emitting circuit 130 to provide a driving voltage, thereby driving the light emitting element to emit light.
  • the first voltage may be a driving voltage, such as a high voltage.
  • the pixel driving circuit 120 provided by the embodiment of the present disclosure is not limited to the example in FIG. 8.
  • the pixel driving circuit 120 may also adopt other conventional pixel driving circuits, as long as the description in the embodiments of the present disclosure can be implemented accordingly. Function.
  • the light emitting circuit 130 is connected between the pixel driving circuit 120 and the second voltage terminal VSS, and the voltage input terminal of the pixel driving circuit 120 is connected to the first voltage terminal VDD, so that the light emitting circuit 130 can be driven to emit light.
  • the light emitting circuit 130 may be connected between the pixel driving circuit 120 and the first voltage terminal VDD, and the voltage input terminal of the pixel driving circuit 120 is connected to the second voltage terminal VSS, thereby driving light emission.
  • the circuit 130 emits light.
  • the pixel driving circuit 120 shown in FIG. 8 may be implemented as the circuit structure shown in FIG. 10.
  • the pixel driving circuit 120 includes first to fifth transistors T1, T2, T3, T4, T5, and a storage capacitor C1.
  • the first transistor T1 is used as a driving transistor, and the other second to fifth transistors are used as switching transistors.
  • the light emitting driving circuit 121 may be implemented as the first transistor T1.
  • the gate of the first transistor T1 is connected as the driving control terminal 1210 of the light-emitting driving circuit 121 and the first node N1, and the first electrode of the first transistor T1 is connected as the first terminal 1211 of the light-emitting driving circuit 121 and the second node N2.
  • a second electrode of a transistor T1 is connected to the third node N3 as the second terminal 1212 of the light-emitting driving circuit 121.
  • the data writing circuit 122 may be implemented as a second transistor T2.
  • the gate of the second transistor T2 is configured to be connected to the scan signal terminal GATE to receive the gate scan signal
  • the first transistor of the second transistor T2 is configured to be connected to the data signal terminal DATA to receive the data signal.
  • the second pole is connected to the second node N2.
  • the compensation circuit 123 may be implemented to include a third transistor T3 and a storage capacitor C1.
  • the gate of the third transistor T3 is configured to be connected to the scan signal terminal GATE to receive the gate scan signal
  • the first pole of the third transistor T3 is connected to the third node N3
  • the second pole of the third transistor T3 and the storage capacitor C1 Is connected to the first pole (that is, connected to the first node N1)
  • the second pole of the storage capacitor C1 is configured to be connected to the first voltage terminal VDD to receive the first voltage.
  • the reset circuit 124 may be implemented as a fourth transistor T4.
  • the gate of the fourth transistor T4 is configured to be connected to the reset control terminal RST to receive a reset signal
  • the first pole of the fourth transistor T4 is connected to the first node N1
  • the second pole of the fourth transistor T4 is configured to be connected to the reset voltage.
  • Terminal VINT is connected to receive the reset voltage.
  • the gate of the fourth transistor T4 may be connected to the scan signal terminal GATE in the pixel driving circuit 120 in the sub-pixel unit group 100 in the previous row, that is, the corresponding signal corresponding to GATE is used.
  • the gate scan signal of the sub-pixel unit group 100 in the previous row serves as a reset signal.
  • the embodiment of the present disclosure does not limit the manner in which the reset signal is applied.
  • the light emission control circuit 125 may be implemented as a fifth transistor T5.
  • the gate of the fifth transistor T5 is configured to be connected to the light-emission control line EL to receive the light-emission control signal.
  • the first electrode of the fifth transistor T5 is configured to be connected to the first voltage terminal VDD to receive the first voltage.
  • the fifth transistor T5 is The second pole is connected to the second node N2.
  • each sub-pixel unit group 100 includes two sub-pixel units 110.
  • the light-emitting circuits 130 included in the two sub-pixel units 110 in the sub-pixel unit group 100 are referred to as a first light-emitting sub-circuit 131 and a second Luminescent subcircuit 132.
  • the first light-emitting sub-circuit 131 includes a first switching circuit 1311 and a first light-emitting element D1.
  • the second light-emitting sub-circuit 132 includes a second switching circuit 1322 and a second light-emitting element D2.
  • the first switching circuit 1311 and the second switching circuit 1322 and The second terminal 1212 of the light-emitting driving circuit 121 is electrically connected.
  • the light-emitting elements (for example, the first light-emitting element D1 and the second light-emitting element D2) in the embodiments of the present disclosure may adopt an OLED.
  • the embodiments of the present disclosure include, but are not limited to, the following embodiments are described by taking the OLED as an example. ,No longer.
  • the OLED may be of various types, such as top emission, bottom emission, etc., and may emit red light, green light, blue light, or white light, which is not limited in the embodiments of the present disclosure.
  • the first switching circuit 1311 may be implemented as a sixth transistor T6.
  • the gate of the sixth transistor T6 is configured to receive a light emission control signal.
  • the gate of the sixth transistor T6 is connected to a gate circuit, so that the gate can receive a light emission control signal provided by the light emission control line EL when the gate circuit is turned on.
  • the first electrode of the sixth transistor T6 is connected to the second terminal 1212 of the light-emitting driving circuit 121 (that is, connected to the third node N3), and the second electrode of the sixth transistor T6 is connected to the first electrode of the first light-emitting element D1 (that is, the anode).
  • the second electrode (ie, the cathode) of the first light-emitting element D1 is connected to the second voltage terminal VSS to receive the second voltage.
  • the second voltage terminal VSS may be grounded, that is, the second voltage is 0V.
  • the second switching circuit 1322 may be implemented as a seventh transistor T7.
  • the gate of the seventh transistor T7 is configured to receive a light emission control signal.
  • the gate of the seventh transistor T7 is connected to a gate circuit, so that the gate can receive a light emission control signal provided by the light emission control line EL when the gate circuit is turned on.
  • the first pole of the seventh transistor T7 is connected to the second end of the light-emitting driving circuit 121 (that is, connected to the third node N3), and the second pole of the seventh transistor T7 and the first pole (that is, the anode) of the second light-emitting element D2 are connected.
  • the second electrode (ie, the cathode) of the second light-emitting element D2 is connected to the second voltage terminal VSS to receive the second voltage.
  • the gating circuit 200 includes a first gating sub-circuit 210 and a second gating sub-circuit 220.
  • the first gating sub-circuit 210 is electrically connected to the light-emitting control line EL and the first switching circuit 1311, so that when the first gating sub-circuit 210 is turned on, the light-emitting control signal provided by the light-emitting control line EL can be applied to the first switch.
  • the circuit 1311 turns on the first switching circuit 1311, so that the pixel driving circuit 120 can provide a light emitting driving current to the first light emitting element D1.
  • the second gating sub-circuit 220 is electrically connected to the light-emitting control line EL and the second switching circuit 1322, so that when the second gating sub-circuit 220 is turned on, the light-emitting control signal provided by the light-emitting control line EL can be applied to the second switch.
  • the circuit 1322 turns on the second switching circuit 1322, so that the pixel driving circuit 120 can provide a light emitting driving current to the second light emitting element D2.
  • the first gating sub-circuit 210 may be implemented as an eighth transistor T8, and the gate of the eighth transistor T8 is configured to receive the first gating control signal CK.
  • the first pole of the transistor T8 is electrically connected to the light emitting control line EL to receive the light emitting control signal
  • the second pole of the eighth transistor T8 is electrically connected to the first switching circuit 1311, for example, in the case where the first switching circuit 1311 is implemented as a sixth transistor.
  • the second electrode of the eighth transistor T8 and the gate of the sixth transistor T6 are connected.
  • the eighth transistor T8 is a P-type transistor.
  • the second gating sub-circuit 220 may be implemented as a ninth transistor T9.
  • the gate of the ninth transistor T9 is configured to receive the first gating control signal CK.
  • the first pole of the ninth transistor T9 is electrically connected to the light emitting control line EL.
  • the second pole of the ninth transistor T9 and the second switching circuit 1322 are electrically connected.
  • the ninth transistor T9 is an N-type transistor.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other switching devices with the same characteristics.
  • the thin film transistors are used as an example for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so there can be no difference in structure of the source and drain of the transistor.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • the transistors can be divided into N-type and P-type transistors according to the characteristics of the transistors.
  • the on-voltage is a low-level voltage (for example, 0V, -5V, -10V, or other suitable voltage), and the off-voltage is a high-level voltage (for example, 5V, 10V, or other suitable voltage) Voltage);
  • the on-voltage is a high-level voltage (for example, 5V, 10V or other suitable voltage)
  • the cut-off voltage is a low-level voltage (for example, 0V, -5V, -10V or Other suitable voltages).
  • the transistors used in the pixel driving circuit 120 provided in the embodiments of the present disclosure are all described by taking a P-type transistor as an example.
  • the embodiments of the present disclosure include, but are not limited to, for example, pixel driving circuits. Some or all of the transistors in 120 may also be N-type transistors.
  • FIG. 12A illustrates a timing of signals provided by each signal terminal of the pixel driving circuit 120 shown in FIG. 10 and a timing of a gating control signal controlling the gating circuit 200, for example, driving a first light emission in a first subframe
  • the element D1 emits light
  • the second light-emitting element D2 is driven to emit light in the second subframe.
  • the eighth transistor T8 P-type transistor
  • the ninth transistor T9 N-type transistor
  • a low-level signal is input to the reset control terminal RST, and the fourth transistor T4 is turned on.
  • the reset voltage input from the reset voltage terminal VINT may be applied to the gate of the first transistor T1, so that the first transistor T1 is processed. Reset.
  • a low-level signal is input to the scan signal terminal GATE, and the second transistor T2 and the third transistor T3 are turned on.
  • the first transistor T1 also remains turned on due to the reset in the previous stage, thereby the data signal
  • the data signal input from the terminal DATA passes through the second transistor T2, the first transistor T1, and the third transistor T3 to charge the storage capacitor C1 until the charging process ends when the first transistor T1 is turned off.
  • the information including the data signal and the threshold voltage of the first transistor T1 can be stored in the storage capacitor C1 for providing gray-scale display data and The threshold voltage of the transistor T1 is compensated.
  • the light-emitting control signal provided by the light-emitting control line EL is a low-level signal. Since the eighth transistor T8 remains on in the first subframe, the low-level signal is applied to the eighth transistor T8.
  • the first voltage input from the first voltage terminal VDD may be applied to the first light-emitting element D1 through the fifth transistor T5, the first transistor T1, and the sixth transistor T6, so that the first transistor T1 can provide an operation based on the first voltage and the data signal.
  • the light-emitting control signal provided by the light-emitting control line EL becomes a high-level signal. Since the eighth transistor T8 remains on in the first subframe, the high-level signal is applied after passing through the eighth transistor T8. To the gate of the sixth transistor T6, so that the sixth transistor T6 is turned off. At this stage, the sixth transistor T6 is turned off to prevent the first light-emitting element D1 from emitting light in the second sub-frame, thereby avoiding display failure.
  • the eighth transistor T8 is a P-type transistor
  • the ninth transistor T9 is an N-type crystal
  • the gates of both are receiving the first gating control signal at the same time.
  • CK so that the eighth transistor T8 and the ninth transistor T9 can be turned on in two different subframes, respectively.
  • Embodiments of the present disclosure include, but are not limited to, for example, in some other embodiments, the eighth transistor T8 may also be an N-type transistor, and the ninth transistor T9 may also be a P-type transistor. Accordingly, at this time, the eighth The gates of the transistor T8 and the ninth transistor T9 simultaneously receive the second gating control signal CB (shown as CB in FIG. 12A).
  • the eighth transistor T8 and the ninth transistor T9 can also be in two different subframes. Turn on separately to complete the corresponding functions.
  • the difference between this embodiment and the embodiment shown in FIG. 10 includes: the eighth transistor T8 and the ninth transistor T9 both adopt P-type transistors, and the eighth transistor The gate of T8 is configured to receive the first gating control signal CK, and the gate of the ninth transistor T9 is configured to receive the second gating control signal CB.
  • the eighth transistor T8 remains on in the first sub-frame; because the second gating control signal CB has been kept high Level, so the ninth transistor T9 remains off in the first subframe.
  • the eighth transistor T8 is kept off in the second subframe; because the second gating control signal CB is always maintained at a low level, The ninth transistor T9 remains on in the second subframe.
  • the eighth transistor T8 and the ninth transistor T9 can be turned on in two subframes respectively, thereby completing the corresponding time-sharing display function. It should be noted that the working principle of the pixel driving circuit 120 in each sub-frame is the same as the corresponding description in the embodiment shown in FIG. 10, which is not repeated here.
  • the eighth transistor T8 and the ninth transistor T9 may both adopt N-type transistors. Accordingly, the gate of the eighth transistor T8 is configured to receive the second gate. The control signal CB, and the gate of the ninth transistor T9 is configured to receive the first gate control signal CK.
  • FIG. 12A shows only the first gating control signal CK and the second gating control signal CB applied to the gating circuit 200 of the sub-pixel unit group 100 in one row
  • FIG. 12B shows the application to the two adjacent rows of sub-pixels.
  • the relationship between the first gating control signal and the second gating control signal of the gating circuit 200 of the pixel unit group 100 As shown in FIG.
  • CK (n) represents the first gating control signal provided by the n-th gate driving sub-circuit 310 of the n-th sub-pixel unit group 100
  • CK (n + 1) represents the first The first gating control signal provided by the n + 1th-level gating driving sub-circuit 310 of the n + 1-row sub-pixel unit group 100, for example, CK (n) and CK (n + 1) can be staggered from each other by a fixed time interval T1 This time interval may be, for example, the on-time T2 of the gate scan signal provided by the gate driving circuit 500.
  • CB (n) represents the second gating control signal provided by the n-th gate driving driver circuit 310 of the n-th row of the sub-pixel unit group 100
  • CB (n + 1) represents the sub-pixel corresponding to the n + 1th row
  • the second gating control signal provided by the n + 1th-level gating driving sub-circuit 310 of the unit group 100, for example, CB (n) and CB (n + 1) can be staggered from each other by a fixed time interval T1.
  • the time interval can be The on-time T2 of the gate scan signal provided to the gate driving circuit 500.
  • the difference between this embodiment and the embodiment shown in FIG. 11 includes that the first gating sub-circuit 210 further includes a tenth transistor T10.
  • the gate is configured to receive the second gate control signal CB, the first pole of the tenth transistor T10 and the second pole of the eighth transistor T8 are connected, and the second pole of the tenth transistor T10 and the third voltage terminal VGH are connected to receive Third voltage;
  • the second gating sub-circuit 220 further includes an eleventh transistor T11, the gate of the eleventh transistor T11 is configured to receive the first gating control signal CK, the first pole of the eleventh transistor T11, and the first The second pole of the nine transistor T9 is connected, and the second pole of the eleventh transistor T11 is connected to the third voltage terminal VGH to receive the third voltage.
  • the third voltage is a high voltage, which may keep the sixth transistor T6 and the seventh transistor T7 off.
  • the eighth transistor T8 and the eleventh transistor T11 are kept on in the first sub-frame.
  • the light emission control signal may be applied to the gate of the sixth transistor T6 through the eighth transistor T8, so that the sixth transistor T6 is turned on during the light emitting stage.
  • the third voltage (high voltage) provided by the third voltage terminal VGH can be applied to the gate of the seventh transistor T7 through the eleventh transistor T11, so that the seventh transistor T7 remains off in the first subframe, which can prevent the first The two light-emitting elements D2 emit light in the first sub-frame, thereby preventing display defects from occurring.
  • the ninth transistor T9 and the tenth transistor T10 are kept off in the first subframe.
  • the ninth transistor T9 and the tenth transistor T10 remain on in the second sub-frame, and the light emission provided by the light emission control line EL
  • the control signal may be applied to the gate of the seventh transistor T7 through the ninth transistor T9, so that the seventh transistor T7 is turned on during the light emitting stage.
  • the third voltage (high voltage) provided by the third voltage terminal VGH can be applied to the gate of the sixth transistor T6 through the tenth transistor T10, so that the sixth transistor T6 remains off in the second subframe, which can prevent the first The light emitting element D1 emits light in the second sub-frame, thereby preventing display defects from occurring.
  • the eighth transistor T8 and the eleventh transistor T11 remain off in the second subframe because the first gating control signal CK is always maintained at a high level.
  • the working principle of the pixel driving circuit 120 shown in FIG. 13 in the reset phase 1, the data writing and compensation phase 2 and the light emitting phase 3 in the first subframe is the same as that in the embodiment shown in FIG. 10
  • the corresponding descriptions are the same; similarly, the operation principle of the pixel driving circuit 120 shown in FIG. 13 in the reset phase 4, the data writing and compensation phase 5, and the light emitting phase 6 in the second subframe is the same as that shown in FIG. 10
  • the corresponding descriptions in the embodiments are the same;
  • a plurality of light-emitting circuits in the sub-pixel unit group can be provided with light-emitting control signals in a time-sharing manner, so that the multiple light-emitting circuits can Light is emitted in different sub-frames, so that when the number of pixel driving circuits provided on the display panel is constant, more sub-pixel units can be set corresponding to each pixel driving circuit, thereby improving the resolution of the display panel. rate.
  • the display device 1 includes any display panel 10 provided by an embodiment of the present disclosure.
  • the display device 1 provided in the embodiment of the present disclosure may be any product or component having a display function, such as a display, an OLED panel, an OLED TV, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, and the like.
  • the display device provided by the embodiments of the present disclosure can improve the display resolution.
  • An embodiment of the present disclosure further provides a driving method that can be used to drive the display panel 10 and the display device 1 using the display panel 10 provided by the embodiments of the present disclosure.
  • the driving method includes the following operations.
  • Step S100 Divide a frame display scan into N subframes.
  • Step S200 In N sub-frames, the pixel driving circuit 120 of each sub-pixel unit 100 is configured to provide the light-emitting driving current to the light-emitting circuit 130 of the N sub-pixel units 110 in each sub-pixel unit group 100 according to the provided data signal, and the gate is selected.
  • the circuit 200 controls the light-emitting circuits 130 of the N sub-pixel units 110 in the sub-pixel unit group 100 of the corresponding row under the control of the gating control signal and the light-emission control signal, and is driven by the pixel driving circuit 120 to emit light.
  • a light emission control signal is provided to the gate circuit 200 and the pixel driving circuit 120 through the light emission control line EL; the gate driving sub-circuit 310 provides a gate control signal (for example, the first gate control signal CK and the first Two gating control signals CB) to the gating circuit 200; the gating circuit 200 controls the light-emitting circuits 130 of the two sub-pixel units 110 in the sub-pixel unit group 100 respectively under the control of the gating control signal and the light-emitting control signal at the first The sub-frame and the second sub-frame are driven by the pixel driving circuit 120 to emit light.
  • a gate control signal for example, the first gate control signal CK and the first Two gating control signals CB
  • the light-emitting circuits 130 in the sub-pixel units 110 in the odd-numbered rows and the light-emitting circuits 130 in the sub-pixel units 110 in the even-numbered rows are respectively in two different Light emission is performed in a sub-frame.

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Abstract

一种显示面板及其驱动方法、显示装置。该显示面板(10)包括呈阵列排布的多个子像素单元组(100)，阵列包括多行和多列，每个子像素单元组(100)包括沿列方向设置的N个子像素单元(110)和像素驱动电路(120)，每个子像素单元(110)包括发光电路(130)，像素驱动电路(120)与N个子像素单元(110)中的发光电路(130)电连接，且被配置为向N个子像素单元(110)中的发光电路(130)提供发光驱动电流；显示面板(10)还包括为每行子像素单元组(100)对应设置的选通电路(200)以及发光控制线(EL)，选通电路(200)被配置为在选通控制信号以及发光控制线(EL)提供的发光控制信号的控制下，控制对应行的子像素单元组(100)中N个子像素单元(110)的发光电路(130)分时被像素驱动电路(120)驱动以进行发光；N为大于等于2的整数。该显示面板可以提高显示的分辨率。

Description

显示面板及其驱动方法、显示装置
本申请要求于2018年5月31日递交的中国专利申请第201810552445.9号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开实施例涉及一种显示面板及其驱动方法、显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示装置由于具有视角宽、对比度高、响应速度快以及相比于无机发光显示器件更高的发光亮度、更低的驱动电压等优势而逐渐受到人们的广泛关注。由于上述特点，有机发光二极管(OLED)可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。
OLED显示装置中的像素驱动电路一般采用矩阵驱动方式，根据每个像素单元中是否引入开关元器件分为有源矩阵(Active Matrix，AM)驱动和无源矩阵(Passive Matrix，PM)驱动。PMOLED虽然工艺简单、成本较低，但因存在交叉串扰、高功耗、低寿命等缺点，不能满足高分辨率大尺寸显示的需求。相比之下，AMOLED在每一个像素单元的像素驱动电路中都集成了一组薄膜晶体管和存储电容，通过对薄膜晶体管和存储电容的驱动控制，实现对流过OLED的电流的控制，从而使OLED根据需要发光。相比PMOLED，AMOLED所需驱动电流小、功耗低、寿命更长，可以满足高分辨率多灰度的大尺寸显示需求。同时，AMOLED在可视角度、色彩的还原、功耗以及响应时间等方面具有明显的优势，适用于高信息含量、高分辨率的显示装置。
发明内容
本公开至少一实施例提供一种显示面板，包括呈阵列排布的多个子像素单元组，所述阵列包括多行和多列，每个所述子像素单元组包括沿列方 向设置的N个子像素单元和像素驱动电路，每个所述子像素单元包括发光电路，所述像素驱动电路与所述N个子像素单元中的发光电路电连接，且被配置为向所述N个子像素单元中的发光电路提供发光驱动电流；所述显示面板还包括为每行所述子像素单元组对应设置的选通电路以及发光控制线，所述选通电路与所述发光控制线电连接以及与对应行的所述子像素单元组中所述N个子像素单元的发光电路电连接，且被配置为在选通控制信号以及所述发光控制线提供的发光控制信号的控制下，控制所述对应行的所述子像素单元组中所述N个子像素单元的发光电路分时被所述像素驱动电路驱动以进行发光；N为大于等于2的整数。
例如，在本公开一实施例提供的显示面板中，所述选通电路与对应行的所述子像素单元组中所述N个子像素单元的发光电路的发光控制端分别电连接，且被配置为将所述发光控制信号分时施加至所述子像素单元组中所述N个子像素单元的发光电路的发光控制端。
例如，本公开一实施例提供的显示面板还包括选通驱动电路。所述选通驱动电路包括多个级联的选通驱动子电路，每行所述子像素单元组对应设置一个所述选通驱动子电路，所述选通驱动子电路被配置为向对应行的所述子像素单元组对应的选通电路提供所述选通控制信号。
例如，本公开一实施例提供的显示面板还包括发光控制驱动电路。所述发光控制驱动电路包括多个级联的发光控制驱动子电路，每行所述子像素单元组对应设置一个所述发光控制驱动子电路，所述发光控制驱动子电路与对应行的所述子像素单元组对应的发光控制线电连接，且被配置为向所述发光控制线提供所述发光控制信号。
例如，本公开一实施例提供的显示面板还包括栅极驱动电路。所述栅极驱动电路包括多个级联的移位寄存器单元，每行所述子像素单元组对应设置一个所述移位寄存器单元，所述移位寄存器单元被配置为向对应行的所述子像素单元组中的像素驱动电路提供栅极扫描信号。
例如，在本公开一实施例提供的显示面板中，所述像素驱动电路包括发光驱动电路、数据写入电路、补偿电路、复位电路和发光控制电路；所述发光驱动电路包括驱动控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的所述发光驱动电流；所述数据写入电路被配置为响应于栅极扫描信号将数据信号写入所述发光驱动电路的驱动控制端； 所述补偿电路被配置为存储写入的所述数据信号且响应于所述栅极扫描信号对所述发光驱动电路进行补偿；所述复位电路被配置为响应于复位信号将复位电压施加至所述发光驱动电路的驱动控制端；以及所述发光控制电路被配置为响应于所述发光控制信号将第一电压施加至所述发光驱动电路的第一端。
例如，在本公开一实施例提供的显示面板中，所述发光驱动电路包括第一晶体管，所述第一晶体管的栅极作为所述发光驱动电路的驱动控制端和第一节点连接，所述第一晶体管的第一极作为所述发光驱动电路的第一端和第二节点连接，所述第一晶体管的第二极作为所述发光驱动电路的第二端和第三节点连接；所述数据写入电路包括第二晶体管，所述第二晶体管的栅极被配置为和扫描信号端连接以接收所述栅极扫描信号，所述第二晶体管的第一极被配置为和数据信号端连接以接收所述数据信号，所述第二晶体管的第二极与所述第二节点连接；所述补偿电路包括第三晶体管和存储电容，所述第三晶体管的栅极被配置为和扫描信号端连接以接收所述栅极扫描信号，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极连接，所述存储电容的第二极被配置为和第一电压端连接；所述复位电路包括第四晶体管，所述第四晶体管的栅极被配置为和复位控制端连接以接收所述复位信号，所述第四晶体管的第一极和第一节点连接，所述第四晶体管的第二极被配置为和复位电压端连接以接收所述复位电压；以及所述发光控制电路包括第五晶体管，所述第五晶体管的栅极被配置为和所述发光控制线连接以接收所述发光控制信号，所述第五晶体管的第一极被配置为和所述第一电压端连接以接收所述第一电压，所述第五晶体管的第二极和第二节点连接。
例如，在本公开一实施例提供的显示面板中，N＝2，每个所述子像素单元组中的两个子像素单元分别包括第一发光子电路和第二发光子电路，所述第一发光子电路包括第一开关电路和第一发光元件，所述第二发光子电路包括第二开关电路和第二发光元件，所述第一开关电路以及所述第二开关电路与所述发光驱动电路的第二端电连接。
例如，在本公开一实施例提供的显示面板中，所述第一开关电路包括第六晶体管，所述第六晶体管的栅极被配置为接收所述发光控制信号，所述第六晶体管的第一极和所述发光驱动电路的第二端连接，所述第六晶体 管的第二极和所述第一发光元件的第一极连接，所述第一发光元件的第二极和第二电压端连接以接收第二电压；所述第二开关电路包括第七晶体管，所述第七晶体管的栅极被配置为接收所述发光控制信号，所述第七晶体管的第一极和所述发光驱动电路的第二端连接，所述第七晶体管的第二极和所述第二发光元件的第一极连接，所述第二发光元件的第二极和第二电压端连接以接收第二电压。
例如，在本公开一实施例提供的显示面板中，所述选通电路包括第一选通子电路和第二选通子电路，所述第一选通子电路和所述发光控制线以及所述第一开关电路电连接，所述第二选通子电路和所述发光控制线以及所述第二开关电路电连接。
例如，在本公开一实施例提供的显示面板中，所述选通控制信号包括第一选通控制信号；所述第一选通子电路包括第八晶体管，所述第八晶体管的栅极被配置为接收所述第一选通控制信号，所述第八晶体管的第一极和所述发光控制线电连接，所述第八晶体管的第二极和所述第一开关电路电连接；所述第二选通子电路包括第九晶体管，所述第九晶体管的栅极被配置为接收所述第一选通控制信号，所述第九晶体管的第一极和所述发光控制线电连接，所述第九晶体管的第二极和所述第二开关电路电连接；其中，所述第八晶体管和第九晶体管中的一个为P型晶体管，另外一个为N型晶体管。
例如，在本公开一实施例提供的显示面板中，所述选通控制信号包括第一选通控制信号和第二选通控制信号；所述第一选通子电路包括第八晶体管，所述第八晶体管的栅极被配置为接收所述第一选通控制信号，所述第八晶体管的第一极和所述发光控制线电连接，所述第八晶体管的第二极和所述第一开关电路电连接；所述第二选通子电路包括第九晶体管，所述第九晶体管的栅极被配置为接收所述第二选通控制信号，所述第九晶体管的第一极和所述发光控制线电连接，所述第九晶体管的第二极和所述第二开关电路电连接。
例如，在本公开一实施例提供的显示面板中，所述第一选通子电路还包括第十晶体管，所述第十晶体管的栅极被配置为接收所述第二选通控制信号，所述第十晶体管的第一极和所述第八晶体管的第二极连接，所述第十晶体管的第二极和第三电压端连接以接收第三电压；所述第二选通子电 路还包括第十一晶体管，所述第十一晶体管的栅极被配置为接收所述第一选通控制信号，所述第十一晶体管的第一极和所述第九晶体管的第二极连接，所述第十一晶体管的第二极和所述第三电压端连接以接收所述第三电压。
本公开至少一实施例还提供一种显示装置，包括本公开的实施例所述的任一显示面板。
本公开至少一实施例还提供一种显示面板的驱动方法，包括：将一帧显示扫描划分为N个子帧；在所述N个子帧中，使得每个所述子像素单元组的像素驱动电路根据提供的数据信号分别向每个所述子像素单元组中N个子像素单元的发光电路提供所述发光驱动电流，所述选通电路在选通控制信号以及所述发光控制信号的控制下，控制所述对应行的子像素单元组中所述N个子像素单元的发光电路分时被所述像素驱动电路驱动以进行发光。
例如，在本公开一实施例提供的显示面板中，N＝2，位于奇数行的子像素单元中的发光电路和位于偶数行的子像素单元中的发光电路分别在两个不同的所述子帧内进行发光。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种显示面板的示意图；
图2为一种像素驱动电路的电路图；
图3为本公开一些实施例提供的一种显示面板的示意图；
图4为本公开一些实施例提供的另一种显示面板的示意图；
图5为本公开一些实施例提供的一种选通驱动电路的示意图；
图6为本公开一些实施例提供的一种发光控制驱动电路的示意图；
图7为本公开一些实施例提供的一种栅极驱动电路的示意图；
图8为本公开一些实施例提供的一种像素驱动电路的示意框图；
图9为本公开一些实施例提供的选通电路的示意框图；
图10为本公开一些实施例提供的一种显示面板中像素驱动电路、选 通电路以及发光电路的实现示例的电路图；
图11为本公开一些实施例提供的另一种显示面板中像素驱动电路、选通电路以及发光电路的实现示例的电路图；
图12A为对应于图10和图11的信号时序图；
图12B为相邻两级选通驱动子电路输出的选通控制信号的信号时序图；
图13为本公开一些实施例提供的又一种显示面板中像素驱动电路、选通电路以及发光电路的实现示例的电路图；
图14为对应于图13的信号时序图；
图15为本公开一些实施例提供的一种显示装置的示意图；以及
图16为本公开的一些实施例提供的一种驱动方法的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
AMOLED采用薄膜晶体管(TFT)构建发光驱动电路为OLED器件提供相应的发光驱动电流，例如采用低温多晶硅薄膜晶体管(LTPS TFT)或氧化物薄膜晶体管(Oxide TFT)，与一般的非晶硅薄膜晶体管(amorphous-Si TFT)相比，LTPS TFT和Oxide TFT具有更高的迁移率和更稳定的特性，因此更 适合应用于AMOLED显示中。但是由于晶体管制作工艺的局限性造成的例如阈值电压、迁移率等电学参数上的非均匀性，或者在长时间加压和高温下，阈值电压还可能会出现漂移，从而有可能造成显示不良，例如出现姆拉(mura)现象(显示亮度不均匀)或残影现象。针对上述问题，需要为每个子像素单元设置像素驱动电路，以在一定程度上消除晶体管的非均匀性或者晶体管阈值电压的漂移。
在每个子像素单元中都设置像素驱动电路会制约显示面板分辨率的提高，在一种提高OLED显示屏分辨率的显示面板中，可以通过复用像素驱动电路来提高显示面板的分辨率。例如，如图1所示，R1、R2、R3和R4分别表示显示面板中第一行、第二行、第三行和第四行的子像素单元。第一行的子像素单元和第二行的子像素单元中位于同一列的两个子像素单元可以共用一个像素驱动电路，类似地，第三行的子像素单元和第四行的子像素单元中位于同一列的两个子像素单元可以共用一个像素驱动电路，依次类推，即每相邻的两行子像素单元之间复用像素驱动电路。
例如，上述像素驱动电路可以采用图2中所示的电路结构，该像素驱动电路由七个晶体管(第一晶体管T1至第七晶体管T7)和一个存储电容C1构成，其中第一晶体管T1至第五晶体管T5以及存储电容C1是两个子像素单元共用的部分，第六晶体管和第七晶体管分别控制两个发光元件(D1和D2)分时进行发光。该像素驱动电路工作时，除了需要向第五晶体管T5提供发光控制信号(EM3)外，还需要在不同的时间段(例如在不同的子帧中)分别向第六晶体管T6和第七晶体管T7提供发光控制信号(EM1和EM2)。继续回到图1，为了提供发光控制信号，每两行子像素单元就需要设置三个发光控制驱动子电路(EOA1、EOA2和EOA3)以分别提供三个发光控制信号(EM1、EM2和EM3)。对于图2的电路结构，可以使发光控制驱动子电路EOA1和第六晶体管T6的控制端(即栅极)电连接以提供发光控制信号EM1，类似地，使发光控制驱动子电路EOA2和第七晶体管T7的控制端(即栅极)电连接以提供发光控制信号EM2，使发光控制驱动子电路EOA3和第五晶体管T5的控制端(即栅极)电连接以提供发光控制信号EM3。如图2所示，第二晶体管T2和第三晶体管T3的控制端(即栅极)需要和扫描信号端GATE连接以接收栅极扫描信号。相应地，如图1所示，每两行子像素单元需要设置一个移位寄存器单元GOA，该移位寄存器单元GOA向像素驱动 电路提供栅极扫描信号。
在上述复用像素驱动电路的显示面板中，对于每相邻的两行子像素单元需要对应设置三个发光控制驱动子电路(EOA1、EOA2和EOA3)以及一个移位寄存器单元GOA，这些电路会占用较大的背板布局空间，不利于实现窄边框，从而会制约显示面板分辨率的提高。
本公开至少一实施例提供一种显示面板。该显示面板包括呈阵列排布的多个子像素单元组，阵列包括多行和多列，每个子像素单元组包括沿列方向设置的N个子像素单元和像素驱动电路，每个子像素单元包括发光电路，像素驱动电路与N个子像素单元中的发光电路电连接，且被配置为向N个子像素单元中的发光电路提供发光驱动电流。显示面板还包括为每行子像素单元组对应设置的选通电路以及发光控制线，选通电路与发光控制线电连接以及与对应行的子像素单元组中N个子像素单元的发光电路电连接，且被配置为在选通控制信号以及发光控制线提供的发光控制信号的控制下，控制对应行的子像素单元组中N个子像素单元的发光电路分时被像素驱动电路驱动以进行发光；N为大于等于2的整数。本公开的实施例还提供对应于上述显示面板的显示装置以及驱动方法。
本公开的实施例提供的显示面板及其驱动方法、显示装置，可以减少在复用像素驱动电路时设置的发光控制驱动子电路的个数，使得显示面板的边框更窄，从而可以提高显示面板分辨率。
下面结合附图对本公开的实施例进行详细说明。
本公开的至少一个实施例提供一种显示面板10，如图3所示，该显示面板10包括呈阵列排布的多个子像素单元组100，该阵列包括多行和多列。需要说明的是，图3中仅示意性的示出了两行两列子像素单元组100，本公开的实施例对子像素单元组100的个数不作限定，例如，显示面板10中子像素单元组100的个数可以根据分辨率的要求进行设置。
例如，每个子像素单元组100包括沿列方向设置的N个子像素单元110和像素驱动电路120，每个子像素单元110包括发光电路130，像素驱动电路120与N个子像素单元110中的发光电路130电连接，且被配置为向N个子像素单元110中的发光电路130提供发光驱动电流。这里N为大于等于2的整数。
显示面板10还包括为每行子像素单元组100对应设置的选通电路200 以及发光控制线EL，选通电路200与发光控制线EL电连接以及与对应行的子像素单元组100中N个子像素单元110的发光电路130电连接，且被配置为在选通控制信号以及发光控制线EL提供的发光控制信号的控制下，控制对应行的子像素单元组100中N个子像素单元110的发光电路130分时被像素驱动电路120驱动以进行发光。N为大于等于2的整数。
例如，在一些实施例中，如图3所示，每个子像素单元组100包括沿列方向设置的两个子像素单元110(即N＝2)，像素驱动电路120与该两个子像素单元110中的发光电路130电连接，也就是说，每个子像素单元组100中的两个子像素单元110共用一个像素驱动电路120。相应地，选通电路200与对应行的子像素单元组100中两个子像素单元110中的发光电路130电连接。需要说明的是，在图3中仅示出了选通电路200与对应行子像素单元组100中的第一列子像素单元组100中的发光电路130电连接，容易理解，选通电路200还与该行子像素单元组100中的其它列子像素单元组100中的发光电路130电连接。另外，本公开的实施例对选通电路200的设置位置不作限定，选通电路200可以设置在每行子像素单元组100的任一一端(例如起始端或末端)，以下各实施例与此相同，不再赘述。
例如，如图3所示，选通电路200与对应行的子像素单元组100中两个子像素单元110中的发光电路130的发光控制端ET分别电连接，且被配置为将发光控制信号分时施加至该行子像素单元组100中两个子像素单元110中的发光电路130的发光控制端ET。
例如，对于图3中所示的显示面板10，在进行显示扫描时，可以将一帧显示扫描划分为两个子帧，例如分别为第一子帧和第二子帧，例如第一子帧和第二子帧在时序上可以是交替进行的。例如，对于第一行的子像素单元组100，在第一子帧中，选通电路200在选通控制信号的作用下，可以将发光控制线EL上提供的发光控制信号施加至子像素单元组100中的其中一个发光电路130的发光控制端ET，以使得该发光电路130导通，从而使得像素驱动电路120可以向该发光电路130提供发光驱动电流以进行发光；然后在第二子帧中，选通电路200在选通控制信号的作用下，可以将发光控制线EL上提供的发光控制信号施加至子像素单元组100中的另外一个发光电路130的发光控制端ET，以使得该发光电路130导通，从而使得像素驱动电路120可以向该发光电路130提供发光驱动电流以进行发光。对于其它行的子像素 单元组100，选通电路200对发光电路130的控制方式与上述相同，不再赘述。
例如，通过上述设置，可以实现在第一子帧中使得显示面板10中位于第一行的子像素单元110进行发光显示，然后在第二子帧中使得显示面板10中位于第二行的子像素单元110进行发光显示，然后在第一子帧中使得显示面板10中位于第三行的子像素单元110进行发光显示，然后在第二子帧中使得显示面板10中位于第四行的子像素单元110进行发光显示，依次类推，也就是说，可以实现在第一子帧中使得显示面板10中位于奇数行的子像素单元110进行发光显示，在第二子帧中使得显示面板10中位于偶数行的子像素单元110进行发光显示，从而完成一帧显示扫描。
例如，在另一些实施例中，如图4所示(图中仅示意性地示出了一行子像素单元组100)，每个子像素单元组100包括沿列方向设置的三个子像素单元110(即N＝3)，像素驱动电路120与该三个子像素单元110中的发光电路130电连接，也就是说，每个子像素单元组100中的三个子像素单元110共用一个像素驱动电路120。相应地，选通电路200与对应行的子像素单元组100中三个子像素单元110的发光电路130电连接。
例如，如图4所示，选通电路200与对应行的子像素单元组100中三个子像素单元110中的发光电路130的发光控制端ET分别电连接，且被配置为将发光控制信号分时施加至该行子像素单元组100中三个子像素单元110中的发光电路130的发光控制端ET。
例如，对于图4中所示的显示面板10，在进行显示扫描时，可以将一帧显示扫描划分为三个子帧，例如分别为第一子帧、第二子帧和第三子帧，例如第一子帧、第二子帧和第三子帧在时序上可以是交替进行的。例如，对于第一行的子像素单元组100，在第一子帧、第二子帧和第三子帧中，选通电路200在选通控制信号的作用下，可以将发光控制线EL上提供的发光控制信号分别施加至子像素单元组100中的三个发光电路130的发光控制端ET，以使得对应的发光电路130导通，从而使得像素驱动电路120可以对导通的发光电路130提供发光驱动电流以进行发光。对于其它行的子像素单元组100，选通电路200对发光电路130的控制方式与上述相同，不再赘述。例如，通过上述设置，可以实现在第一子帧中使得显示面板10中位于第3n-2行的子像素单元110进行发光显示，在第二子帧中使得显示面板10中位于 第3n-1行的子像素单元110进行发光显示，在第三子帧中使得显示面板10中位于第3n行的子像素单元110进行发光显示，从而完成一帧显示扫描，n为大于零的整数。
需要说明的是，图3和图4仅示意性示出了N＝2和N＝3的实施例，但本公开的实施例对N的值不作限定，N只要为大于等于2的整数即可。例如，在本公开的实施例中，每个子像素单元组100还可以包括四个、五个、或更多个子像素单元110。
在本公开的实施例提供的显示面板中，通过复用像素驱动电路以及设置选通电路，可以为子像素单元组中的多个发光电路分时提供发光控制信号，使得该多个发光电路可以在不同的子帧中进行发光，从而在显示面板设置的像素驱动电路的个数不变的情形下，对应于每一个像素驱动电路，可以设置更多个子像素单元，从而可以提高显示面板的分辨率。
需要说明的是，在本公开的实施例中，可以对显示面板中的每行子像素单元组均设置选通电路，从而提高整个显示面板的全部区域的分辨率，本公开的实施例包括但不限于此，例如还可以只对显示面板的部分区域中的子像素单元组设置选通电路，从而可以仅提高该部分区域的分辨率。
例如，本公开的实施例提供的显示面板10还包括选通驱动电路300，如图5所示，该选通驱动电路包括多个级联的选通驱动子电路310。如图3和图4所示，每行子像素单元组100对应设置一个选通驱动子电路310，选通驱动子电路310被配置为向对应行的子像素单元组100对应的选通电路200提供选通控制信号。例如，相邻级联的两个选通驱动子电路310提供的选通控制信号彼此错开一个固定的时间间隔。
例如，本公开的实施例提供的显示面板10还包括发光控制驱动电路400，如图6所示，该发光控制驱动电路400包括多个级联的发光控制驱动子电路410。如图3和图4所示，每行子像素单元组100对应设置一个发光控制驱动子电路410，发光控制驱动子电路410与对应行的子像素单元组100对应的发光控制线EL电连接，且被配置为向发光控制线EL提供发光控制信号。例如，通过发光控制线EL传输的发光控制信号除了提供至选通电路200外，还提供至每行子像素单元组100中的像素驱动电路120，例如用于在发光阶段导通像素驱动电路120中的薄膜晶体管。
在本公开的实施例提供的显示面板中，每行子像素单元组只需要对应设 置一个发光控制驱动子电路410，可以进一步减小显示面板的边框宽度，从而可以进一步提高分辨率。
例如，本公开的实施例提供的显示面板10还包括栅极驱动电路500，如图7所示，该栅极驱动电路500包括多个级联的移位寄存器单元510。如图3和图4所示，每行子像素单元组100对应设置一个移位寄存器单元510，移位寄存器单元510被配置为向对应行的子像素单元组100中的像素驱动电路120提供栅极扫描信号。级联的移位寄存器单元510提供的栅极扫描信号是逐级移位的，从而可以使得显示面板的多行子像素单元组可以逐行进行发光显示。需要说明的是，本公开的实施例中的栅极驱动电路500可以采用常规设计，只要是可以提供逐级移位的栅极扫描信号即可。
在本公开的实施例中，像素驱动电路120为具有补偿功能的像素驱动电路，该补偿功能可以通过电压补偿、电流补偿或混合补偿来实现，具有补偿功能的像素电路例如可以为4T1C或4T2C等。在本公开的一些实施例中，如图8所示，像素驱动电路120包括发光驱动电路121、数据写入电路122、补偿电路123、复位电路124和发光控制电路125。
该发光驱动电路121包括驱动控制端1210、第一端1211和第二端1212，且被配置为控制流经第一端1211和第二端1212的发光驱动电流。例如，在发光阶段，发光驱动电路121可以向发光电路130中的发光元件提供发光驱动电流以驱动发光元件进行发光，且可以根据需要的“灰度”发光。
该数据写入电路122被配置为响应于栅极扫描信号将数据信号写入发光驱动电路121的驱动控制端1210。例如，数据写入电路122和扫描信号端GATE以及数据信号端DATA连接，例如在数据写入和补偿阶段，数据写入电路122响应于扫描信号端GATE输入的栅极扫描信号而导通，从而将数据信号端DATA输入的数据信号写入发光驱动电路121的驱动控制端1210，并存储在补偿电路123中，以在例如发光阶段时根据该数据信号生成驱动发光电路130发光的发光驱动电流。
该补偿电路123被配置为存储写入的数据信号且响应于栅极扫描信号对发光驱动电路121进行补偿。例如，在补偿电路123包括存储电容的情形下，例如在数据写入和补偿阶段，补偿电路123可以响应于扫描信号端GATE输入的栅极扫描信号而导通，从而可以将数据写入电路122写入的数据信号存储在存储电容中。例如，同时在数据写入和补偿阶段，补偿电路123可以将 发光驱动电路121的驱动控制端1210和第二端1212电连接，从而可以使发光驱动电路121的阈值电压的相关信息也相应地存储在存储电容中，从而例如在发光阶段可以利用存储的数据信号以及阈值电压对发光驱动电路121进行控制，使得发光驱动电路121得到补偿。
该复位电路124被配置为响应于复位信号将复位电压施加至发光驱动电路121的驱动控制端1210。例如，复位电路124和复位控制端RST以及复位电压端VINT连接，例如在复位阶段，复位电路124可以响应于复位控制端RST输入的复位信号而导通，从而可以将复位电压端VINT输入的复位电压施加至发光驱动电路121的驱动控制端1210。需要说明的是，在本公开的一些实施例中，本行的子像素单元组100中的像素驱动电路120中的复位电路124还可以不与复位控制端RST连接，而与上一行子像素单元组100中的像素驱动电路120中的扫描信号端GATE连接，即利用对应于上一行子像素单元组100的栅极扫描信号作为复位信号。本公开的实施例对复位信号的施加方式不作限定。
该发光控制电路125被配置为响应于发光控制信号将第一电压施加至发光驱动电路121的第一端1211。例如，发光控制电路125和发光控制线EL电连接，从而可以接收发光控制线EL上提供的发光控制信号，发光控制电路125还和第一电压端VDD连接以接收第一电压。例如，在发光阶段，发光控制电路125可以响应于发光控制信号而导通，从而可以将第一电压施加至发光驱动电路121的第一端1211，在发光驱动电路121导通时，容易理解，其第二端1212的电位也为第一电压。然后，发光驱动电路121将此第一电压施加至发光电路130中的发光元件以提供驱动电压，从而驱动发光元件发光。例如，第一电压可以是驱动电压，例如为高电压。
如上所述，本公开的实施例提供的像素驱动电路120不限于图8中的示例，像素驱动电路120还可以采用其它常规的像素驱动电路，只要相应地可以实现本公开的实施例中所描述的功能即可。
在图8中，发光电路130连接在像素驱动电路120和第二电压端VSS之间，而像素驱动电路120的电压输入端连接到第一电压端VDD，由此可以驱动发光电路130发光。与此对应，在其他示例中，发光电路130可以连接在像素驱动电路120和第一电压端VDD之间，且像素驱动电路120的电压输入端连接到第二电压端VSS，由此可以驱动发光电路130发光。
例如，在一些实施例中，图8中所示的像素驱动电路120可以实现为图10中所示的电路结构。如图10所示，该像素驱动电路120包括：第一至第五晶体管T1、T2、T3、T4、T5以及存储电容C1。例如，第一晶体管T1被用作驱动晶体管，其他的第二至第五晶体管被用作开关晶体管。
例如，如图10所示，更详细地，发光驱动电路121可以实现为第一晶体管T1。第一晶体管T1的栅极作为发光驱动电路121的驱动控制端1210和第一节点N1连接，第一晶体管T1的第一极作为发光驱动电路121的第一端1211和第二节点N2连接，第一晶体管T1的第二极作为发光驱动电路121的第二端1212和第三节点N3连接。
数据写入电路122可以实现为第二晶体管T2。第二晶体管T2的栅极被配置为和扫描信号端GATE连接以接收栅极扫描信号，第二晶体管T2的第一极被配置为和数据信号端DATA连接以接收数据信号，第二晶体管T2的第二极与第二节点N2连接。
补偿电路123可以实现为包括第三晶体管T3和存储电容C1。第三晶体管T3的栅极被配置为和扫描信号端GATE连接以接收栅极扫描信号，第三晶体管T3的第一极和第三节点N3连接，第三晶体管T3的第二极和存储电容C1的第一极连接(即与第一节点N1连接)，存储电容C1的第二极被配置为和第一电压端VDD连接以接收第一电压。
复位电路124可以实现为第四晶体管T4。第四晶体管T4的栅极被配置为和复位控制端RST连接以接收复位信号，第四晶体管T4的第一极和第一节点N1连接，第四晶体管T4的第二极被配置为和复位电压端VINT连接以接收复位电压。需要说明的是，在不设置复位电压端VINT的情形下，第四晶体管T4的栅极可以与上一行子像素单元组100中的像素驱动电路120中的扫描信号端GATE连接，即利用对应于上一行子像素单元组100的栅极扫描信号作为复位信号。本公开的实施例对复位信号的施加方式不作限定。
发光控制电路125可以实现为第五晶体管T5。第五晶体管T5的栅极被配置为和发光控制线EL连接以接收发光控制信号，第五晶体管T5的第一极被配置为和第一电压端VDD连接以接收第一电压，第五晶体管T5的第二极和第二节点N2连接。
在本公开的一些实施例中，例如N＝2，即每个子像素单元组100中包括两个子像素单元110。如图9所示，在一个子像素单元组100中，为了描述 清楚，把该子像素单元组100中的两个子像素单元110包括的发光电路130分别称为第一发光子电路131和第二发光子电路132。第一发光子电路131包括第一开关电路1311和第一发光元件D1，第二发光子电路132包括第二开关电路1322和第二发光元件D2，第一开关电路1311以及第二开关电路1322与发光驱动电路121的第二端1212电连接。
本公开的实施例中的发光元件(例如，第一发光元件D1和第二发光元件D2)可以采用OLED，本公开的实施例包括但不限于此，以下各实施例均以OLED为例进行说明，不再赘述。该OLED可以为各种类型，例如顶发射、底发射等，可以发红光、绿光、蓝光或白光等，本公开的实施例对此不作限制。
例如，在本公开的一些实施例中，如图10所示，第一开关电路1311可以实现为第六晶体管T6。第六晶体管T6的栅极被配置为接收发光控制信号，例如，第六晶体管T6的栅极和选通电路连接，从而在选通电路导通时可以接收发光控制线EL提供的发光控制信号。第六晶体管T6的第一极和发光驱动电路121的第二端1212连接(即与第三节点N3连接)，第六晶体管T6的第二极和第一发光元件D1的第一极(即阳极)连接，第一发光元件D1的第二极(即阴极)和第二电压端VSS连接以接收第二电压。例如，第二电压端VSS可以接地，即第二电压为0V。
如图10所示，第二开关电路1322可以实现为第七晶体管T7。第七晶体管T7的栅极被配置为接收发光控制信号，例如，第七晶体管T7的栅极和选通电路连接，从而在选通电路导通时可以接收发光控制线EL提供的发光控制信号。第七晶体管T7的第一极和发光驱动电路121的第二端连接(即与第三节点N3连接)，第七晶体管T7的第二极和第二发光元件D2的第一极(即阳极)连接，第二发光元件D2的第二极(即阴极)和第二电压端VSS连接以接收第二电压。
在一些实施例中，如图9所示，选通电路200包括第一选通子电路210和第二选通子电路220。第一选通子电路210和发光控制线EL以及第一开关电路1311电连接，从而在第一选通子电路210导通时，可以将发光控制线EL提供的发光控制信号施加至第一开关电路1311，使得第一开关电路1311导通，从而使得像素驱动电路120可以将发光驱动电流提供至第一发光元件D1。第二选通子电路220和发光控制线EL以及第二开关电路1322电 连接，从而在第二选通子电路220导通时，可以将发光控制线EL提供的发光控制信号施加至第二开关电路1322，使得第二开关电路1322导通，从而使得像素驱动电路120可以将发光驱动电流提供至第二发光元件D2。
例如，在一些实施例中，如图10所示，第一选通子电路210可以实现为第八晶体管T8，第八晶体管T8的栅极被配置为接收第一选通控制信号CK，第八晶体管T8的第一极和发光控制线EL电连接以接收发光控制信号，第八晶体管T8的第二极和第一开关电路1311电连接，例如在第一开关电路1311实现为第六晶体管的情形下，第八晶体管T8的第二极和第六晶体管T6的栅极连接。例如，第八晶体管T8为P型晶体管。
第二选通子电路220可以实现为第九晶体管T9，第九晶体管T9的栅极被配置为接收第一选通控制信号CK，第九晶体管T9的第一极和发光控制线EL电连接以接收发光控制信号，第九晶体管T9的第二极和第二开关电路1322电连接，例如在第二开关电路1322实现为第七晶体管T7的情形下，第九晶体管T9的第二极和第七晶体管T7的栅极连接。例如，第九晶体管T9为N型晶体管。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，导通电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)，截止电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，导通电压为高电平电压(例如，5V、10V或其他合适的电压)，截止电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，需要说明的是，本公开的实施例中提供的像素驱动电路120中采用的晶体管均是以P型晶体管为例进行说明的，本公开的实施例包括但不限于此，例如像素驱动电路120中的部分或全部晶体管也可以采用N型晶体管。
下面结合图12A所示的信号时序图，对图10中所示的电路结构的工作原理进行说明。例如，如图12A所示，将一帧显示扫描分为第一子帧和第二 子帧。图12A示出了图10中所示的像素驱动电路120的各个信号端提供的信号的时序以及控制选通电路200的选通控制信号的时序，例如，在第一子帧中驱动第一发光元件D1发光，在第二子帧中驱动第二发光元件D2发光。
在第一子帧中，由于第一选通控制信号CK一直保持低电平，所以在第一子帧中第八晶体管T8(P型晶体管)保持导通，第九晶体管T9(N型晶体管)保持截止。
在复位阶段1中，复位控制端RST输入低电平信号，第四晶体管T4导通，可以将复位电压端VINT输入的复位电压施加至第一晶体管T1的栅极，从而对第一晶体管T1进行复位。
在数据写入和补偿阶段2中，扫描信号端GATE输入低电平信号，第二晶体管T2和第三晶体管T3导通，第一晶体管T1由于上个阶段的复位也保持导通，从而数据信号端DATA输入的数据信号经过第二晶体管T2、第一晶体管T1和第三晶体管T3后对存储电容C1进行充电，直到第一晶体管T1截止时充电过程结束。经过数据写入和补偿阶段2后，可以将包括数据信号和第一晶体管T1的阈值电压的信息存储在存储电容C1中，以用于在后续发光阶段时，提供灰度显示数据和对第一晶体管T1的阈值电压进行补偿。
在发光阶段3中，发光控制线EL提供的发光控制信号为低电平信号，由于第八晶体管T8在第一子帧中保持导通，所以该低电平信号通过第八晶体管T8后施加至第六晶体管T6的栅极，从而使得第六晶体管T6导通，同时第五晶体管T5也导通。第一电压端VDD输入的第一电压可以通过第五晶体管T5、第一晶体管T1以及第六晶体管T6施加至第一发光元件D1，从而使得第一晶体管T1可以根据第一电压以及数据信号提供使第一发光元件D1发光的发光驱动电流。
在关闭阶段4中，发光控制线EL提供的发光控制信号变为高电平信号，由于第八晶体管T8在第一子帧中保持导通，所以该高电平信号通过第八晶体管T8后施加至第六晶体管T6的栅极，从而使得第六晶体管T6截止。在此阶段，将第六晶体管T6截止是为了防止第一发光元件D1在第二子帧中发光，从而避免发生显示不良。
在第二子帧中，由于第一选通控制信号CK一直保持高电平，所以在第二子帧中第九晶体管T9保持导通，第八晶体管T8保持截止。关于第二子帧中的复位阶段5、数据写入和补偿阶段6、发光阶段7以及关闭阶段8的描 述可以分别参考第一子帧中的复位阶段1、数据写入和补偿阶段2、发光阶段3以及关闭阶段4中的相应描述，这里不再赘述。
需要说明的是，在图10所示的电路结构中，其中第八晶体管T8采用P型晶体管，且第九晶体管T9采用N型晶体，且使得两者的栅极同时接收第一选通控制信号CK，从而使得第八晶体管T8和第九晶体管T9可以在两个不同的子帧中分别导通。本公开的实施例包括但不限于此，例如在其它的一些实施例中，第八晶体管T8还可以采用N型晶体管，且第九晶体管T9还可以采用P型晶体管，相应地，此时第八晶体管T8和第九晶体管T9的栅极同时接收第二选通控制信号CB(如图12A中的CB所示)，也可以使得第八晶体管T8和第九晶体管T9在两个不同的子帧中分别导通，从而完成相应的功能。
在本公开的另一些实施例中，如图11所示，该实施例与图10所示的实施例的区别包括：第八晶体管T8和第九晶体管T9均采用P型晶体管，且第八晶体管T8的栅极被配置为接收第一选通控制信号CK，而第九晶体管T9的栅极被配置为接收第二选通控制信号CB。
下面结合图12A所示的信号时序图，对图11中所示的电路结构的工作原理进行说明。例如，在第一子帧中，由于第一选通控制信号CK一直保持低电平，所以在第一子帧中第八晶体管T8保持导通；由于第二选通控制信号CB一直保持高电平，所以在第一子帧中第九晶体管T9保持截止。在第二子帧中，由于第一选通控制信号CK一直保持高电平，所以在第二子帧中第八晶体管T8保持截止；由于第二选通控制信号CB一直保持低电平，所以在第二子帧中第九晶体管T9保持导通。采用上述方式可以实现第八晶体管T8和第九晶体管T9分别在两个子帧中导通，从而完成相应的分时显示功能。需要说明的是，像素驱动电路120在每一个子帧中的工作原理和图10中所示的实施例中的相应描述相同，这里不再赘述。
需要说明的是，在图11所示的电路结构中，第八晶体管T8和第九晶体管T9还可以均采用N型晶体管，相应地，第八晶体管T8的栅极被配置为接收第二选通控制信号CB，而第九晶体管T9的栅极被配置为接收第一选通控制信号CK。
图12A中仅示出了施加于一行子像素单元组100的选通电路200的第一选通控制信号CK和第二选通控制信号CB，图12B中示出了施加于相邻两 行子像素单元组100的选通电路200的第一选通控制信号和第二选通控制信号之间的关系。如图12B所示，CK(n)表示对应于第n行子像素单元组100的第n级选通驱动子电路310提供的第一选通控制信号，CK(n+1)表示对应于第n+1行子像素单元组100的第n+1级选通驱动子电路310提供的第一选通控制信号，例如CK(n)和CK(n+1)彼此可以错开一个固定时间间隔T1，该时间间隔例如可以为栅极驱动电路500提供的栅极扫描信号的导通时间T2。CB(n)表示对应于第n行子像素单元组100的第n级选通驱动子电路310提供的第二选通控制信号，CB(n+1)表示对应于第n+1行子像素单元组100的第n+1级选通驱动子电路310提供的第二选通控制信号，例如CB(n)和CB(n+1)彼此可以错开一个固定时间间隔T1，该时间间隔例如可以为栅极驱动电路500提供的栅极扫描信号的导通时间T2。以下各实施例与此相同，不再赘述。
在本公开的又一些实施例中，如图13所示，该实施例与图11所示的实施例的区别包括：第一选通子电路210还包括第十晶体管T10，第十晶体管T10的栅极被配置为接收第二选通控制信号CB，第十晶体管T10的第一极和第八晶体管T8的第二极连接，第十晶体管T10的第二极和第三电压端VGH连接以接收第三电压；第二选通子电路220还包括第十一晶体管T11，第十一晶体管T11的栅极被配置为接收第一选通控制信号CK，第十一晶体管T11的第一极和第九晶体管T9的第二极连接，第十一晶体管T11的第二极和第三电压端VGH连接以接收第三电压。例如，第三电压为高电压，该高电压可以使得第六晶体管T6和第七晶体管T7保持截止。
下面结合图14所示的信号时序图，对图13中所示的电路结构的工作原理进行说明。例如，在第一子帧中，由于第一选通控制信号CK一直保持低电平，所以在第一子帧中第八晶体管T8和第十一晶体管T11保持导通，发光控制线EL提供的发光控制信号可以通过第八晶体管T8施加至第六晶体管T6的栅极，从而使得第六晶体管T6在发光阶段导通。同时第三电压端VGH提供的第三电压(高电压)可以通过第十一晶体管T11施加中第七晶体管T7的栅极，从而使得第七晶体管T7在第一子帧中保持截止，可以防止第二发光元件D2在第一子帧中发光，从而避免发生显示不良。另外在第一子帧中，由于第二选通控制信号CB一直保持高电平，所以在第一子帧中第九晶体管T9和第十晶体管T10保持截止。
例如，在第二子帧中，由于第二选通控制信号CB一直保持低电平，所以在第二子帧中第九晶体管T9和第十晶体管T10保持导通，发光控制线EL提供的发光控制信号可以通过第九晶体管T9施加至第七晶体管T7的栅极，从而使得第七晶体管T7在发光阶段导通。同时第三电压端VGH提供的第三电压(高电压)可以通过第十晶体管T10施加中第六晶体管T6的栅极，从而使得第六晶体管T6在第二子帧中保持截止，可以防止第一发光元件D1在第二子帧中发光，从而避免发生显示不良。另外在第二子帧中，由于第一选通控制信号CK一直保持高电平，所以在第二子帧中第八晶体管T8和第十一晶体管T11保持截止。
需要说明的是，图13所示的像素驱动电路120在第一子帧中的复位阶段1、数据写入和补偿阶段2以及发光阶段3中的工作原理和图10中所示的实施例中的相应描述相同；类似地，图13所示的像素驱动电路120在第二子帧中的复位阶段4、数据写入和补偿阶段5以及发光阶段6中的工作原理和图10中所示的实施例中的相应描述相同；这里不再赘述。
在本公开的实施例提供的显示面板中，通过复用像素驱动电路以及设置选通电路，可以为子像素单元组中的多个发光电路分时提供发光控制信号，使得该多个发光电路可以在不同的子帧中进行发光，从而在显示面板设置的像素驱动电路的个数不变的情形下，对应于每一个像素驱动电路，可以设置更多个子像素单元，从而可以提高显示面板的分辨率。
本公开的实施例还提供一种显示装置1，如图15所示，该显示装置1包括本公开的实施例提供的任一显示面板10。例如，本公开的实施例提供的显示装置1可以为显示器、OLED面板、OLED电视、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。本公开的实施例提供的显示装置可以提高显示的分辨率。
本公开的实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的显示面板10以及采用该显示面板10的显示装置1。例如，该驱动方法包括如下操作。
步骤S100：将一帧显示扫描划分为N个子帧；以及
步骤S200：在N个子帧中，使得每个子像素单元100的像素驱动电路120根据提供的数据信号分别向每个子像素单元组100中N个子像素单元110的发光电路130提供发光驱动电流，选通电路200在选通控制信号以及发光 控制信号的控制下，控制对应行的子像素单元组100中的N个子像素单元110的发光电路130分时被像素驱动电路120驱动以进行发光。
例如，对于图3所示的显示面板，在步骤S100中，可以将一帧显示扫描划分为两个子帧(例如第一子帧和第二子帧)，即N＝2。相应地，在步骤S200中，通过发光控制线EL提供发光控制信号至选通电路200和像素驱动电路120；选通驱动子电路310提供选通控制信号(例如第一选通控制信号CK和第二选通控制信号CB)至选通电路200；选通电路200在选通控制信号和发光控制信号的控制下，控制子像素单元组100中两个子像素单元110的发光电路130分别在第一子帧和第二子帧中被像素驱动电路120驱动以进行发光。
例如，在将一帧显示扫描划分为两个子帧的情形中，位于奇数行的子像素单元110中的发光电路130和位于偶数行的子像素单元110中的发光电路130分别在两个不同的子帧内进行发光。
需要说明的是，关于该驱动方法的详细描述和技术效果可以参考本公开的实施例中对于显示面板10的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种显示面板，包括呈阵列排布的多个子像素单元组，所述阵列包括多行和多列，每个所述子像素单元组包括沿列方向设置的N个子像素单元和像素驱动电路，每个所述子像素单元包括发光电路，所述像素驱动电路与所述N个子像素单元中的发光电路电连接，且被配置为向所述N个子像素单元中的发光电路提供发光驱动电流；
    所述显示面板还包括为每行所述子像素单元组对应设置的选通电路以及发光控制线，所述选通电路与所述发光控制线电连接以及与对应行的所述子像素单元组中所述N个子像素单元的发光电路电连接，且被配置为在选通控制信号以及所述发光控制线提供的发光控制信号的控制下，控制所述对应行的所述子像素单元组中所述N个子像素单元的发光电路分时被所述像素驱动电路驱动以进行发光；
    N为大于等于2的整数。
  2. 根据权利要求1所述的显示面板，其中，所述选通电路与对应行的所述子像素单元组中所述N个子像素单元的发光电路的发光控制端分别电连接，且被配置为将所述发光控制信号分时施加至所述子像素单元组中所述N个子像素单元的发光电路的发光控制端。
  3. 根据权利要求1或2所述的显示面板，还包括选通驱动电路，其中，
    所述选通驱动电路包括多个级联的选通驱动子电路，每行所述子像素单元组对应设置一个所述选通驱动子电路，
    所述选通驱动子电路被配置为向对应行的所述子像素单元组对应的选通电路提供所述选通控制信号。
  4. 根据权利要求1-3任一所述的显示面板，还包括发光控制驱动电路，其中，
    所述发光控制驱动电路包括多个级联的发光控制驱动子电路，每行所述子像素单元组对应设置一个所述发光控制驱动子电路，
    所述发光控制驱动子电路与对应行的所述子像素单元组对应的发光控制线电连接，且被配置为向所述发光控制线提供所述发光控制信号。
  5. 根据权利要求1-4任一所述的显示面板，还包括栅极驱动电路，其 中，
    所述栅极驱动电路包括多个级联的移位寄存器单元，每行所述子像素单元组对应设置一个所述移位寄存器单元，
    所述移位寄存器单元被配置为向对应行的所述子像素单元组中的像素驱动电路提供栅极扫描信号。
  6. 根据权利要求1-5任一所述的显示面板，其中，所述像素驱动电路包括发光驱动电路、数据写入电路、补偿电路、复位电路和发光控制电路；
    所述发光驱动电路包括驱动控制端、第一端和第二端，且被配置为控制流经所述第一端和所述第二端的所述发光驱动电流；
    所述数据写入电路被配置为响应于栅极扫描信号将数据信号写入所述发光驱动电路的驱动控制端；
    所述补偿电路被配置为存储写入的所述数据信号且响应于所述栅极扫描信号对所述发光驱动电路进行补偿；
    所述复位电路被配置为响应于复位信号将复位电压施加至所述发光驱动电路的驱动控制端；以及
    所述发光控制电路被配置为响应于所述发光控制信号将第一电压施加至所述发光驱动电路的第一端。
  7. 根据权利要求6所述的显示面板，其中，
    所述发光驱动电路包括第一晶体管，所述第一晶体管的栅极作为所述发光驱动电路的驱动控制端和第一节点连接，所述第一晶体管的第一极作为所述发光驱动电路的第一端和第二节点连接，所述第一晶体管的第二极作为所述发光驱动电路的第二端和第三节点连接；
    所述数据写入电路包括第二晶体管，所述第二晶体管的栅极被配置为和扫描信号端连接以接收所述栅极扫描信号，所述第二晶体管的第一极被配置为和数据信号端连接以接收所述数据信号，所述第二晶体管的第二极与所述第二节点连接；
    所述补偿电路包括第三晶体管和存储电容，所述第三晶体管的栅极被配置为和扫描信号端连接以接收所述栅极扫描信号，所述第三晶体管的第一极和所述第三节点连接，所述第三晶体管的第二极和所述存储电容的第一极连接，所述存储电容的第二极被配置为和第一电压端连接；
    所述复位电路包括第四晶体管，所述第四晶体管的栅极被配置为和复 位控制端连接以接收所述复位信号，所述第四晶体管的第一极和第一节点连接，所述第四晶体管的第二极被配置为和复位电压端连接以接收所述复位电压；以及
    所述发光控制电路包括第五晶体管，所述第五晶体管的栅极被配置为和所述发光控制线连接以接收所述发光控制信号，所述第五晶体管的第一极被配置为和所述第一电压端连接以接收所述第一电压，所述第五晶体管的第二极和第二节点连接。
  8. 根据权利要求6所述的显示面板，其中，N＝2，
    每个所述子像素单元组中的两个子像素单元分别包括第一发光子电路和第二发光子电路，
    所述第一发光子电路包括第一开关电路和第一发光元件，
    所述第二发光子电路包括第二开关电路和第二发光元件，
    所述第一开关电路以及所述第二开关电路与所述发光驱动电路的第二端电连接。
  9. 根据权利要求8所述的显示面板，其中，
    所述第一开关电路包括第六晶体管，所述第六晶体管的栅极被配置为接收所述发光控制信号，所述第六晶体管的第一极和所述发光驱动电路的第二端连接，所述第六晶体管的第二极和所述第一发光元件的第一极连接，所述第一发光元件的第二极和第二电压端连接以接收第二电压；
    所述第二开关电路包括第七晶体管，所述第七晶体管的栅极被配置为接收所述发光控制信号，所述第七晶体管的第一极和所述发光驱动电路的第二端连接，所述第七晶体管的第二极和所述第二发光元件的第一极连接，所述第二发光元件的第二极和第二电压端连接以接收第二电压。
  10. 根据权利要求8或9所述的显示面板，其中，所述选通电路包括第一选通子电路和第二选通子电路，
    所述第一选通子电路和所述发光控制线以及所述第一开关电路电连接，
    所述第二选通子电路和所述发光控制线以及所述第二开关电路电连接。
  11. 根据权利要求10所述的显示面板，其中，所述选通控制信号包括第一选通控制信号；
    所述第一选通子电路包括第八晶体管，所述第八晶体管的栅极被配置为接收所述第一选通控制信号，所述第八晶体管的第一极和所述发光控制线电连接，所述第八晶体管的第二极和所述第一开关电路电连接；
    所述第二选通子电路包括第九晶体管，所述第九晶体管的栅极被配置为接收所述第一选通控制信号，所述第九晶体管的第一极和所述发光控制线电连接，所述第九晶体管的第二极和所述第二开关电路电连接；
    其中，所述第八晶体管和第九晶体管中的一个为P型晶体管，另外一个为N型晶体管。
  12. 根据权利要求10所述的显示面板，其中，所述选通控制信号包括第一选通控制信号和第二选通控制信号；
    所述第一选通子电路包括第八晶体管，所述第八晶体管的栅极被配置为接收所述第一选通控制信号，所述第八晶体管的第一极和所述发光控制线电连接，所述第八晶体管的第二极和所述第一开关电路电连接；
    所述第二选通子电路包括第九晶体管，所述第九晶体管的栅极被配置为接收所述第二选通控制信号，所述第九晶体管的第一极和所述发光控制线电连接，所述第九晶体管的第二极和所述第二开关电路电连接。
  13. 根据权利要求12所述的显示面板，其中，
    所述第一选通子电路还包括第十晶体管，所述第十晶体管的栅极被配置为接收所述第二选通控制信号，所述第十晶体管的第一极和所述第八晶体管的第二极连接，所述第十晶体管的第二极和第三电压端连接以接收第三电压；
    所述第二选通子电路还包括第十一晶体管，所述第十一晶体管的栅极被配置为接收所述第一选通控制信号，所述第十一晶体管的第一极和所述第九晶体管的第二极连接，所述第十一晶体管的第二极和所述第三电压端连接以接收所述第三电压。
  14. 一种显示装置，包括权利要求1-13任一项所述的显示面板。
  15. 一种如权利要求1-13任一所述的显示面板的驱动方法，包括：
    将一帧显示扫描划分为N个子帧；
    在所述N个子帧中，使得每个所述子像素单元组的像素驱动电路根据提供的数据信号分别向每个所述子像素单元组中N个子像素单元的发光电路提供所述发光驱动电流，所述选通电路在选通控制信号以及所述发光控 制信号的控制下，控制所述对应行的子像素单元组中所述N个子像素单元的发光电路分时被所述像素驱动电路驱动以进行发光。
  16. 根据权利要求15所述的驱动方法，其中，N＝2，位于奇数行的子像素单元中的发光电路和位于偶数行的子像素单元中的发光电路分别在两个不同的所述子帧内进行发光。
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