WO2019227440A1 - 超高清图像显示驱动方法及装置 - Google Patents

超高清图像显示驱动方法及装置 Download PDF

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Publication number
WO2019227440A1
WO2019227440A1 PCT/CN2018/089381 CN2018089381W WO2019227440A1 WO 2019227440 A1 WO2019227440 A1 WO 2019227440A1 CN 2018089381 W CN2018089381 W CN 2018089381W WO 2019227440 A1 WO2019227440 A1 WO 2019227440A1
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Prior art keywords
video data
lines
ultra
line
definition
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PCT/CN2018/089381
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English (en)
French (fr)
Inventor
黎守新
于军胜
陈珉
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成都晶砂科技有限公司
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Priority to PCT/CN2018/089381 priority Critical patent/WO2019227440A1/zh
Publication of WO2019227440A1 publication Critical patent/WO2019227440A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B26/00—Optical devices or arrangements for the control of light using movable or deformable optical elements
    • G02B26/08—Optical devices or arrangements for the control of light using movable or deformable optical elements for controlling the direction of light
    • G02B26/10—Scanning systems
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems

Definitions

  • the present invention relates to an ultra-high-definition image display driving technology, and in particular, to an ultra-high-definition image display driving method and device.
  • the mainstream high-resolution screen is full high-definition resolution 1920x1080 (FHD).
  • FHD resolutions include 3840x2160 (4K), 7680x4320 (8K), 10240x4320 (10K), 15360x8640 (16K), and even higher resolutions.
  • Adopting a single video interface, such as HDMI2.0 interface or DP1.2 interface can realize the transmission of ultra high-definition video data, but the transmission distance is quite limited, which greatly reduces the ease of use.
  • the traditional scanning method is progressive scanning or interlaced scanning (as shown in Figure 1), and only one row in the pixel array is selected during each scanning.
  • the technical problem to be solved by the present invention is to provide an ultra high-definition image display driving method and device, which can reduce the video data rate and ensure the grayscale accuracy of the displayed image.
  • the present invention adopts the following technical solutions.
  • An ultra high-definition image display driving method includes the following steps:
  • a frame of ultra-high-definition image is divided into several lines of video data by line; during interlaced scanning, a field of ultra-high-definition images is divided into several lines of video data by line;
  • K is a natural number greater than or equal to 2 and K is less than or equal to the number of lines of line video data into which one frame / field of ultra-high-definition image is divided into lines;
  • the K-line video data corresponds to K lines adjacent to each other in the ultra-high-definition display array; when interlaced scanning, the K-line video data corresponds to K lines of one line in the ultra-high-definition display array .
  • step S3 the buffered K lines of video data are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces; said step In S5, the buffered video data of the other K lines is output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the line video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • An ultra high-definition image display driving device includes:
  • a segmentation unit which is used to progressively divide a frame of ultra-high-definition image into several lines of video data during progressive scanning; and a segmentation unit, which is used to deinterleave a field of ultra-high-definition images into several lines of video data during progressive scanning;
  • the buffer unit is configured to buffer K lines of video data in the plurality of lines of video data, and buffer the other K lines of video data in the plurality of lines of video data after the K lines of video data are output in parallel, and so on, Until the last K lines of video data in the plurality of lines of video data are cached;
  • a receiving output driving unit configured to output the received K-line video data output in parallel by the buffer unit to an ultra-high-definition display array and drive the ultra-high-definition display array corresponding to the K-line video data Lines are simultaneously displayed, and then the other K lines of video data output in parallel by the buffer unit are received in parallel to the ultra high definition display array and the lines corresponding to the other K lines of video data are driven in the ultra high definition display array Simultaneous display, and so on, until all the lines corresponding to the several lines of video data of the one frame / field ultra high-definition image of the ultra-high-definition display array are completely displayed.
  • the K-line video data corresponds to K lines adjacent to each other in the ultra-high-definition display array; when interlaced scanning, the K-line video data corresponds to K lines of one line in the ultra-high-definition display array .
  • the buffer unit transmits the K-line video data to the receiving output driving unit in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces. .
  • the line video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • the invention has the following beneficial technical effects.
  • the present invention divides a frame of ultra-high-definition image into several lines of video data line by line during progressive scanning; in an interlaced scan, divides a field of ultra-high-definition image into lines of video data line by line; caches the K in the several lines of video data Line video data; output the buffered K line video data to the UHD display array in parallel and drive the UHD display array corresponding to the K line video data at the same time; wait for the K line video data After parallel output, another K lines of video data in the plurality of lines of video data are buffered; the buffered K lines of video data are output in parallel to the UHD display array and drive the UHD display array with the other K The lines corresponding to the line of video data are displayed simultaneously; and so on, until the lines corresponding to the lines of video data of the one-frame / field ultra-high-definition image of the ultra-high-definition display array are all displayed.
  • FIG. 1 schematically illustrates a conventional progressive scan structure.
  • FIG. 2 schematically illustrates a structural diagram of an ultra-high-definition image display driving device of the present invention.
  • FIG. 3 schematically illustrates a progressive scanning structure of the present invention.
  • FIG. 4 schematically illustrates a structure of an interlaced scan according to the present invention.
  • FIG. 5 schematically illustrates a gate driving timing chart of progressive scanning according to the present invention.
  • FIG. 6 schematically illustrates a gate driving timing chart of interlaced scanning according to the present invention.
  • FIG. 7 is a schematic flowchart of a method of the present invention.
  • the present invention can be applied to, but not limited to, ultra-high-definition display devices and devices such as LCD, OLED, QLCD, QLED, Mini-LED, Micro-LED, Nano-LED, and Micro-OLED.
  • ultra-high-definition display devices and devices such as LCD, OLED, QLCD, QLED, Mini-LED, Micro-LED, Nano-LED, and Micro-OLED.
  • the ultra-high-definition display array 4 includes a plurality of pixel units arranged in a matrix manner to form an M ⁇ N pixel array, where M is the number of rows and N is the number of columns.
  • the value range of the row number m of the M ⁇ N pixel array is 0, 1, 2, ..., M-1, and the value range of the column number n is 0, 1, 2, ..., N-1.
  • an ultra-high-definition image display driving device includes a dividing unit 1, a buffer unit 2, and a receiving output driving unit 3.
  • the segmentation unit 1 is used for segmenting one frame of ultra-high-definition image into several lines of video data during progressive scanning.
  • the segmentation unit 1 is also used to segment a field of ultra-high-definition images into several lines of video data during interlaced scanning.
  • (1) In the progressive scanning mode, the one ultra-high-definition image is divided into several lines of video data line by line: line video data 0, line video data 1, line video data 2, ..., line video data M-1.
  • line 0 of the ultra-high-definition display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the ultra-high-definition display array 4 and the line of video data 0
  • the corresponding line 0 displays the image contained in line video data 0
  • line 1 of the ultra-high-definition display array 4 displays the image contained in the foregoing line video data 1, that is, the image corresponding to line video data 1 of the ultra-high-definition display array 4.
  • line 0 of the ultra-high-definition display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the ultra-high-definition display array 4 and the line of video data 0
  • the corresponding 0 line displays the image contained in the line video data 0
  • the 2 lines of the UHD display array 4 display the image contained in the aforementioned line video data 1, that is, the corresponding image of the UHD display array 4 corresponding to the line video data 1
  • 2 lines display images contained in line video data 1
  • 4 lines of UHD display array 4 display the images contained in the aforementioned line video data 2, that is, 4 lines corresponding to line video data 2 of UHD display array 4
  • the image contained in the line video data 2 is displayed; the others are the same.
  • one line of the UHD display array 4 displays the image contained in the foregoing line of video data 0, that is, the phase of the UHD display array 4 and the line video data 0
  • the corresponding 1 line displays the image contained in the line video data 0
  • the 3 lines of the UHD display array 4 display the images contained in the aforementioned line video data 1, that is, the image corresponding to the line video data 1 of the UHD display array 4 3 lines display the images contained in line video data 1
  • 5 lines of UHD display array 4 display the images contained in the aforementioned line video data 2, that is, 5 lines corresponding to line video data 2 of UHD display array 4
  • the image contained in the line video data 2 is displayed; the others are the same.
  • the buffer unit 2 is configured to buffer K line video data among the foregoing lines of video data.
  • the K line video data is: line video data 0, line video data 1, line video data 2, line video data 3; After the K lines of video data are output in parallel, the other K lines of video data in the lines of video data are cached.
  • the other K lines of video data are: line video data 4, line video data 5, line Video data 6, line video data 7, or the other K lines of video data are: line video data 8, line video data 9, line video data 10, line video data 11; and so on, until the lines of video are cached
  • the last K lines of video data in the data when progressive scanning, the last K lines of video data are: line video data M-4, line video data M-3, line video data M-2, line video data M-1; in interlaced scanning, the last K lines of video data are: line video data (M / 2) -4, line video data (M / 2) -3, line video data (M / 2)- 2.
  • the buffer unit 2 outputs K lines of video data to the receiving output driving unit 3 in parallel, and the control unit in the receiving output driving unit 3 generates digital gate driving signals and digital source driving signals by using the corresponding line video data and sends them to the corresponding gate driving respectively.
  • K gate drive units and K source drive units load K rows of video data into the UHD display array 4 at the same time to display UHD video images with correct and high dynamic range.
  • K is a natural number greater than or equal to 2
  • K is less than or equal to the number of lines of line video data into which one frame / field ultra-high-definition image is divided into lines. For example, in the embodiment shown in FIG.
  • the number of channels for the buffer unit 2 to output K lines of video data to the receiving output driving unit 3 in parallel is K
  • the receiving output driving unit 3 includes K control units and K source driving units.
  • K gate driving units, the channels of the buffer unit 2 and the control unit of the receiving output driving unit 3 are in one-to-one correspondence.
  • channel 0 of buffer unit 2 is connected to control unit 0 of receiving output driving unit 3
  • channel 1 of buffer unit 2 is connected to control unit 1 of receiving output driving unit 3, and so on.
  • the control unit 0 receives the line video data output by the buffer unit 2 from the channel 0 of the buffer unit 2, and the control unit 0 generates a digital source driving signal and a digital gate driving signal according to the line of video data and respectively Corresponding output to the source drive unit 0 and the gate drive unit 0;
  • the control unit 1 receives the line video data output from the buffer unit 2 through the channel 1 of the buffer unit 2, and the control unit 1 generates a digital source drive signal and a digital gate according to the line video data
  • the driving signals are correspondingly output to the source driving unit 1 and the gate driving unit 1 respectively; and so on.
  • the receiving output driving unit 3 is configured to output the received K-line video data output in parallel by the buffer unit 2 to the ultra-high-definition display array 4 in parallel and drive the ultra-high-definition display array 4 with the K-line video data.
  • the corresponding rows are displayed at the same time, and the other K lines of video data output in parallel by the buffer unit 2 are received and output to the UHD display array 4 in parallel and the UHD video data of the UHD display array 4 is driven
  • the corresponding rows are displayed simultaneously, and so on, until all the rows corresponding to the video data of the one frame / field ultra high-definition image of the ultra-high-definition display array 4 are completely displayed.
  • the K lines of video data are: line video data 0, line video data 1, line video data 2, line video data 3, and the other K lines of video data are: Line video data 4, line video data 5, line video data 6, line video data 7, and the last K lines of line video data are: line video data M-4, line video data M-3, line video data M-2, Line video data M-1.
  • the receiving output driving unit 3 outputs the K lines of video data output in parallel from the received buffer unit 2, that is, line video data 0, line video data 1, line video data 2, and line video data 3 in parallel to the UHD display array 4,
  • line video data 0 is output from channel 0 of buffer unit 2 to control unit 0 of receiving output driving unit 3
  • line video data 1 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output driving unit 3
  • line video Data 2 is output from the channel 2 of the buffer unit 2 to the control unit 2 receiving the output driving unit 3
  • line video data 3 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 drives the lines corresponding to the K line of video data of the UHD display array 4 to be displayed simultaneously, that is, the image contained in the 0 line display video data 0 of the UHD display array 4 and the UHD display array
  • the image contained in the 1 line display line 4 of the video data 1 the image contained in the 2 line display of the ultra-high-definition display array 4 includes the image contained in the video data 2
  • the 3 line displayed in the ultra-high-definition display array 4 contains the image included in the video data 3.
  • line video data 1 line video data 1, line video data 2, and line video data 3 are output to the UHD display array 4 in parallel and drive 0-3 lines of display at the same time
  • the receiving output driving unit 3 then outputs the received
  • the other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and are output to the UHD display array 4 in parallel.
  • the line video data 4 is output from the cache unit Channel 0 of 2 is output to control unit 0 of receiving output drive unit 3.
  • Line video data 5 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output drive unit 3.
  • Line video data 6 is from channel 2 of cache unit 2.
  • the output is sent to the control unit 2 receiving the output driving unit 3, and the line video data 7 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display simultaneously, that is, the images contained in the 4 lines of the UHD display array 4 and the video data 4, UHD
  • the last K lines of video data are: line video data M-4, line video data M-3, line video data M-2, and line video data M-1 corresponding to the AND of the UHD display array 4.
  • the lines corresponding to the last K lines of video data are displayed simultaneously. And so on, until the lines corresponding to the several lines of video data of the one frame of ultra-high-definition image of the ultra-high-definition display array 4 are completely displayed.
  • the K-line video data of even / odd field ultra high-definition images are: line video data 0, line video data 1, line video data 2, line video data 3, and the other K lines
  • the line video data is: line video data 4, line video data 5, line video data 6, line video data 7, and the last K line video data is: line video data (M / 2) -4, line video data ( M / 2) -3, line video data (M / 2) -2, line video data (M / 2) -1.
  • the receiving output driving unit 3 outputs the K lines of video data output in parallel from the received buffer unit 2, that is, line video data 0, line video data 1, line video data 2, and line video data 3 in parallel to the UHD display array 4,
  • line video data 0 is output from channel 0 of buffer unit 2 to control unit 0 of receiving output driving unit 3
  • line video data 1 is output from channel 1 of buffer unit 2 to control unit 1 of receiving output driving unit 3
  • line video Data 2 is output from the channel 2 of the buffer unit 2 to the control unit 2 receiving the output driving unit 3
  • line video data 3 is output from the channel 3 of the buffer unit 2 to the control unit 3 receiving the output driving unit 3.
  • the receiving output driving unit 3 drives the ultra-high-definition display array 4 to display lines corresponding to the K-line video data at the same time.
  • 0 lines of the UHD display array 4 display the images contained in the video data
  • 2 lines of the UHD display array 4 display the images contained in the video data 1 and the UHD display
  • the 4 rows of the array 4 display the images contained in the video data 2
  • the 6 rows of the UHD display array 4 display the images contained in the video data 3.
  • the output drive unit 3 receives the The other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and output to the UHD display array 4 in parallel, for example, line video data.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display at the same time, that is, the images contained in the 8 lines of the UHD display array 4 and the video data 4, UHD The image contained in 10 rows of display array video data 5 of display array 4, the image contained in 12 rows of display array video 4 of ultra high definition display array 4 and the image contained in video data 7 of 14 rows of ultra high definition display array 4 image. And so on, until the lines corresponding to the several lines of video data of the even-field ultra-high-definition image driving the ultra-high-definition display array 4 are all displayed.
  • one line of the UHD display array 4 displays the image contained in the video data 0, and the three lines of the UHD display array 4 displays the image contained in the video data 1 and the UHD display
  • the 5 rows of the array 4 display the images contained in the video data 2
  • the 7 rows of the UHD display array 4 display the images contained in the video data 3.
  • line video data 1 line video data 1, line video data 2, and line video data 3 are output to the UHD display array 4 in parallel and drive 1, 3, 5, and 7 lines of display at the same time
  • the receiving output driving unit 3 then outputs all
  • the other K lines of video data output in parallel by the buffer unit 2 are line video data 4, line video data 5, line video data 6, and line video data 7 and output to the UHD display array 4 in parallel, for example, line video data.
  • the receiving output driving unit 3 then drives the lines corresponding to the other K lines of video data of the UHD display array 4 to display at the same time, that is, the 9 lines of the UHD display array 4 display the images contained in the video data 4 and the UHD 11 images of display array 4 include images contained in video data 5, 13 images of UHD display array 4 contain images contained in video data 6, 15 images of UHD display array 4 contain images contained in video data 7 image. And so on, until all the lines corresponding to the several lines of video data of the odd-field ultra-high-definition image driving the ultra-high-definition display array 4 are completely displayed.
  • the foregoing K-line video data should correspond to K lines adjacent to each other in the UHD display array; during interlaced scanning, the K-line video data should correspond to each other in the UHD display array. K lines apart.
  • the buffer unit 2 transmits the K-line video data to the receiver in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the foregoing line of video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • a method for driving an ultra-high-definition image display of the present invention includes the following steps:
  • a frame of ultra-high-definition image is divided into several lines of video data by line; during interlaced scanning, a field of ultra-high-definition images is divided into several lines of video data by line;
  • the K-line video data should correspond to the K lines adjacent to each other in the ultra-high-definition display array; during interlaced scanning, the K-line video data should correspond to the ultra-high-definition display array. K rows separated from each other.
  • step S3 the buffered K lines of video data are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • step S5 the buffered video data of the other K lines are output in parallel through multiple HDMI interfaces, multiple DP interfaces, multiple V-BY-ONE interfaces, multiple LVDS interfaces, or multiple MIPI interfaces.
  • the foregoing line of video data includes video image data Data, a data clock Clock, a data valid signal DE, a line synchronization signal Hsync, and a frame / field synchronization signal Vsync.
  • K 4 that is, the four gate drive units are gate drive unit 0, gate drive unit 1, gate drive unit 2, and gate drive unit 3, and the four source drive units are source drive unit 0, Source drive unit 1, source drive unit 2, source drive unit 3.
  • the progressive video data is taken as an example, and the present invention is further specifically described according to a scanning method (progressive scanning or interlaced scanning).
  • the dividing unit 1 divides one frame of ultra-high-definition image into M lines of video data.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 with the 4 lines of video data.
  • the corresponding lines are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and frame synchronization signal Vsync) are input to the four control units 0, control unit 1, control unit 2, and control unit 3 respectively.
  • the ultra-high-definition display array 4 supports 8K resolution of progressive scanning.
  • the row number satisfies m 4 * i + 3
  • the pixel unit is connected to the gate driving unit 3 and the source driving unit 3.
  • the pixel units with row number 2 and column number 3 are connected to the gate driving unit 2 and the source driving unit 2.
  • the control unit 0 includes a clock, a data valid signal DE, and a line synchronization signal included in the line video data 0 output from the channel 0 of the buffer unit 2 as received by itself.
  • Hsync and frame synchronization signal Vsync generate corresponding digital gate drive signals and digital source drive signals and send them to gate drive unit 0 and source drive unit 0, respectively.
  • Gate drive unit 0 and source drive unit 0 scan the corresponding data Data to the gate drive.
  • the pixel unit with row number 0 of the ultra high-definition display array 4 selected by unit 0 displays the image contained in the video data 0 of the line 0 of the ultra-high-definition display array 4.
  • the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, data valid signal DE, line synchronization signal Hsync, and frame synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1.
  • the digital source driving signals are sent to the gate driving unit 1 and the source driving unit 1, respectively.
  • the gate driving unit 1 and the source driving unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 1 selected by the gate driving unit 1.
  • One line of the ultra-high-definition display array 4 displays the images included in the video data 1.
  • the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the frame synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 2 and the source driving unit 2, respectively.
  • the gate driving unit 2 and the source driving unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 2 selected by the gate driving unit 2.
  • the two lines of the ultra-high-definition display array 4 display the images contained in the video data 2.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the frame synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 3 and the source driving unit 3, respectively.
  • the gate driving unit 3 and the source driving unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 3 selected by the gate driving unit 3.
  • the images contained in the video data 3 of the 3 lines of the ultra high definition display array 4 are displayed.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M lines of video data, such as line video data 4. , Line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received additional four lines of video data output in parallel by the buffer unit 2 to the ultra high definition display array 4 and drive the ultra high definition display array 4 and the other four lines of video.
  • the rows corresponding to the data are displayed at the same time.
  • the 4, 5, 6, and 7 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M lines of video data, such as line video data 8, Line video data 9, line video data 10, line video data 11.
  • the above-mentioned gate driving timing when performing progressive scanning on the ultra high-definition display array is shown in FIG. 5.
  • the gate driving signal corresponding to the four rows is high, it indicates that the four rows are selected and corresponding source driving is performed.
  • the UHD display array 4 supports 8K resolution for interlaced scanning.
  • the pixel units with row number 2 and column number 3 are connected to the gate driving unit 1 and the source
  • the segmenting unit 1 divides a field of ultra-high-definition images into M / 2 lines of video data line by line.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M / 2 lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the 4 lines of video data.
  • the corresponding rows are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and field synchronization signal Vsync) are input to the four control units 0, control unit 1, control unit 2, and control unit 3 respectively.
  • the control unit 0 includes a clock, a data valid signal DE, a line synchronization signal Hsync, and a field included in the line video data 0 output from the channel 0 of the buffer unit 2 received by itself.
  • the synchronization signal Vsync generates corresponding digital gate driving signals and digital source driving signals and sends them to the gate driving unit 0 and the source driving unit 0, respectively.
  • the gate driving unit 0 and the source driving unit 0 scan the corresponding data Data to the gate driving unit 0 and select them.
  • the row number is the corresponding pixel unit on 0, and the row 0 of the ultra high-definition display array 4 displays the image contained in the row video data 0.
  • control unit 1 At the same time, the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1. And digital source drive signals are sent to the gate drive unit 1 and source drive unit 1, respectively.
  • the gate drive unit 1 and source drive unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 2 selected by the gate drive unit 1. The images contained in the video data 1 of the 2 lines of the ultra high definition display array 4 are displayed.
  • the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 2 and the source driving unit 2, respectively.
  • the gate driving unit 2 and the source driving unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 4 selected by the gate driving unit 2.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source driving signals are sent to the gate driving unit 3 and the source driving unit 3, respectively.
  • the gate driving unit 3 and the source driving unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 6 selected by the gate driving unit 3.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M / 2 line video data, such as line video Data 4, line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received four other lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the other 4 lines.
  • the lines corresponding to the video data are displayed simultaneously.
  • the 8, 10, 12, and 14 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the segmenting unit 1 divides a field of ultra-high-definition images into M / 2 lines of video data line by line.
  • the buffer unit 2 buffers 4 lines of video data among the foregoing M / 2 lines of video data, such as line video data 0, line video data 1, line video data 2, line video data 3.
  • the receiving output driving unit 3 is configured to output the received 4 lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the 4 lines of video data.
  • the corresponding rows are displayed at the same time.
  • the 4 lines of line video data output in parallel by 4 channels are line video data 0, line video data 1, line video data 2, line video data 3 (each line of line video data includes corresponding video data Data, data clock Clock, data valid signal DE, line synchronization signal Hsync, and field synchronization signal Vsync) are input to four control units 0, control unit 1, control unit 2, and control unit 3.
  • the control unit 0 includes a clock, a data valid signal DE, a line synchronization signal Hsync, and a field included in the line video data 0 output from the channel 0 of the buffer unit 2 received by itself.
  • the synchronization signal Vsync generates corresponding digital gate driving signals and digital source driving signals and sends them to the gate driving unit 0 and the source driving unit 0, respectively.
  • the gate driving unit 0 and the source driving unit 0 scan the corresponding data Data to the gate driving unit 0 and select them.
  • the row number is 1 corresponding to the pixel unit, and one row of the ultra-high-definition display array 4 displays the image contained in the video data 0.
  • control unit 1 At the same time, the control unit 1 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 1 output from the channel 1 of the buffer unit 2 received by the control unit 1. And digital source drive signals are sent to the gate drive unit 1 and source drive unit 1, respectively.
  • the gate drive unit 1 and source drive unit 1 scan the corresponding data Data to the corresponding pixel unit on the row number 3 selected by the gate drive unit 1. The images contained in the three-line display line video data 1 of the ultra-high-definition display array 4.
  • control unit 2 At the same time, the control unit 2 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 2 output from the channel 2 of the buffer unit 2 received by itself. And digital source drive signals are sent to the gate drive unit 2 and source drive unit 2, respectively.
  • the gate drive unit 2 and source drive unit 2 scan the corresponding data Data to the corresponding pixel unit on the row number 5 selected by the gate drive unit 2. The images contained in the video data 2 of the 5 lines of the UHD display array 4 are displayed.
  • the control unit 3 generates a corresponding digital gate driving signal according to the clock Clock, the data valid signal DE, the line synchronization signal Hsync, and the field synchronization signal Vsync included in the line video data 3 output from the channel 3 of the buffer unit 2 received by itself.
  • the digital source drive signals are sent to the gate drive unit 3 and the source drive unit 3, respectively.
  • the gate drive unit 3 and the source drive unit 3 scan the corresponding data Data to the corresponding pixel unit on the row number 7 selected by the gate drive unit 3.
  • the 7-line display image of the ultra-high-definition display array 4 contains the video data 3.
  • the buffer unit 2 buffers the other four lines of video data in the foregoing M / 2 line video data, such as line video Data 4, line video data 5, line video data 6, line video data 7.
  • the receiving output driving unit 3 is configured to output the received four other lines of video data output in parallel by the buffer unit 2 to the UHD display array 4 in parallel and drive the UHD display array 4 and the other 4 lines.
  • the lines corresponding to the video data are displayed simultaneously.
  • the 9, 11, 13, and 15 lines of the ultra-high-definition display array 4 correspond to the images contained in the video data lines 4, 5, 6, and 7 at the same time.
  • the above-mentioned gate driving timing when the interlace scanning is performed on the ultra high-definition display array is shown in FIG. 6.
  • the gate driving signal corresponding to the 4 rows is high, it indicates that the 4 rows are selected and corresponding source driving is performed.
  • the disclosed apparatus and method may be implemented in other ways.
  • the device embodiments described above are only schematic.
  • the division of the unit is only a logical function division.
  • multiple units or components may be combined or It can be integrated into another device, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, which may be electrical, mechanical or other forms.
  • the units described as separate components may or may not be physically separated, that is, they may be located in one place, or may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the objective of the solution of this embodiment.
  • each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the above integrated unit may be implemented in the form of hardware or in the form of software functional unit.
  • the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium.
  • the technical solution of the present invention essentially or part that contributes to the existing technology or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium , Including a plurality of instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present invention.
  • the foregoing storage medium / unit includes: universal serial bus flash disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), Various media such as magnetic disks or optical disks that can store program codes.

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Abstract

本发明公开一种超高清图像显示驱动方法及装置，包括以下步骤：将一帧/场超高清图像按行分割成若干行视频数据；缓存该若干行视频数据中的K行行视频数据；并行输出所缓存的该K行行视频数据至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示；缓存该若干行视频数据中的另外K行行视频数据；并行输出所缓存的该另外K行行视频数据至该超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示；以此类推，直至驱动该超高清显示阵列的与该一帧超高清图像的该若干行视频数据相对应的行全部完成显示。它能降低视频数据速率及保证显示图像的灰阶准确性。

Description

超高清图像显示驱动方法及装置 技术领域
本发明涉及超高清图像显示驱动技术，具体涉及超高清图像显示驱动方法及装置。
背景技术
目前主流的高分辨率屏为全高清分辨率1920x1080(FHD)，随着科技的发展，生活娱乐，科学工程，医疗行业等对超高分辨率显示屏的需求也越来越强烈。超高清分辨率包括3840x2160(4K)、7680x4320(8K)、10240x4320(10K)、15360x8640(16K)，甚至更高的分辨率。采用单个视频接口，如HDMI2.0接口或者DP1.2接口等可以实现超高清视频数据的传输，但传输距离相当有限，在使用方便性上大打折扣。传统的扫描方式为逐行扫描或隔行扫描(如图1)，每次扫描时只选中像素阵列中的某一行。利用传统的单一行选中的扫描方式对超高清显示阵列进行门驱动时需要更快的扫描频率，这对IC设计提出了更高要求的难题，在成本上难以控制。在如此高的扫描频率下，超高清显示阵列在实际显示图像时具有更多的显示灰阶以及高动态范围亦是个关键。现实中，常用的一种方式是利用多屏手段来实现超高清显示，即采用超高清图像处理装置对超高清视频信息进行块分割，并传输至拼接显示屏中对应的显示屏上。利用分块技术实现了超高清分辨率图像的显示，但需要缓存一帧的超高清视频数据，导致需要超大容量的存储单元，而且在实际显示中，由于多屏的存在导致图像中间有黑边框，影响用户体验。
发明内容
本发明要解决的技术问题是，提供一种超高清图像显示驱动方法及装置，其能降低视频数据速率及保证显示图像的灰阶准确性。
为解决上述技术问题，本发明采用下述技术方案。
一种超高清图像显示驱动方法，包括以下步骤：
S1，逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；隔行扫描时，将一场超高清图像按行分割成若干行视频数据；
S2，缓存该若干行视频数据中K行行视频数据,其中，K为大于或等于2的自然数，且K小于或等于一帧/场超高清图像按行分割成的行视频数据的行数；
S3，并行输出所缓存的该K行行视频数据至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示；
S4，待该K行行视频数据并行输出后，再缓存该若干行视频数据中的另外K行行视频数据；
S5，并行输出所缓存的该另外K行行视频数据至该超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示；
S6，以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
逐行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行 的K行。
所述步骤S3中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该K行行视频数据；所述步骤S5中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该另外K行行视频数据。
所述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
一种超高清图像显示驱动装置，包括：
分割单元，其用于逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；其用于隔行扫描时，将一场超高清图像按行分割成若干行视频数据；
缓存单元，其用于缓存该若干行视频数据中的K行行视频数据，待该K行行视频数据并行输出后再缓存该若干行视频数据中的另外K行行视频数据，以此类推，直至缓存该若干行视频数据中的最后K行行视频数据；
接收输出驱动单元，其用于将所接收到的该缓存单元所并行输出的K行行视频数据并行输出至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示，再将所接收到的该缓存单元所并行输出的另外K行行视频数据并行输出至超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示，以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
逐行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行的K行。
所述缓存单元通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口将所述K行行视频数据并行输送至所述接收输出驱动单元。
所述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
本发明具有下述有益技术效果。
本发明逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；隔行扫描时，将一场超高清图像按行分割成若干行视频数据；缓存该若干行视频数据中的K行行视频数据；并行输出所缓存的该K行行视频数据至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示；待该K行行视频数据并行输出后，再缓存该若干行视频数据中的另外K行行视频数据；并行输出所缓存的该另外K行行视频数据至该超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示；以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。其优点为：1、相比于单通道传输超高清视频，每行的视频数据速率大大降低，有利于超高速视频的传输；2、每次缓存该若干行视频数据中的K行行视频数据，当K小于一帧/场超高清图像行视频数据的行数时能大大降低对存储器容量的需求；3、K行同时驱动显示的方式(比如具有多个门驱动以 及多个源驱动，连接方式由扫描方式决定)使得超高清显示阵列的各个像素单元具有更多的时间充放电，保证了灰阶准确性，有利于实现高对比。
附图说明
图1示意性示出现有的一种逐行扫描结构示意图。
图2示意性示出本发明的超高清图像显示驱动装置的结构示意图。
图3示意性示出本发明的一种逐行扫描结构示意图。
图4示意性示出本发明的一种隔行扫描结构示意图。
图5示意性示出本发明涉及的逐行扫描的门驱动时序图。
图6示意性示出本发明涉及的隔行扫描的门驱动时序图。
图7为本发明的方法的一种流程示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。在不冲突的情况下，本发明中的实施例及实施例中的特征可以相互任意组合。并且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
本发明可以适用于但不限于LCD、OLED、QLCD、QLED、Mini-LED、Micro-LED、Nano-LED和Micro-OLED等超高清显示器件、设备等。
一并参见图1、2、3，本发明涉及的超高清显示阵列4包括若干像素单元，这些像素单元按矩阵方式排列形成M×N像素阵列，其中，M为行数，N为列数。M×N像素阵列的行编号m的取值范围为0、1、2、…、M-1，其列编号n的取值范围为0、1、2、…、N-1。
参见图2，本发明的一种超高清图像显示驱动装置，其包括分割单元1、缓存单元2以及接收输出驱动单元3。
分割单元1用于逐行扫描时，将一帧超高清图像按行分割成若干行视频数据。分割单元1还用于隔行扫描时，将一场超高清图像按行分割成若干行视频数据。(1)在逐行扫描方式时，该一帧超高清图像按行分割为若干行视频数据：行视频数据0，行视频数据1，行视频数据2，……，行视频数据M-1。该一帧超高清图像在超高清显示阵列4上显示时，超高清显示阵列4的0行显示的是前述行视频数据0所包含的图像，即超高清显示阵列4的与行视频数据0相对应的0行显示行视频数据0所包含的图像；超高清显示阵列4的1行显示的是前述行视频数据1所包含的图像，即超高清显示阵列4的与行视频数据1相对应的1行显示行视频数据1所包含的图像；超高清显示阵列4的2行显示的是前述行视频数据2所包含的图像，即超高清显示阵列4的与行视频数据2相对应的2行显示行视频数据2所包含的图像；其他的以此类推。(2)在隔行扫描方式时，分为偶数场扫描与奇数场扫描，偶/奇数场超高清图像按行分割为若干行视频数据：行视频数据0，行视频数据1，行视频数据2，……，行视频数据(M/2)-1。该偶数场超高清图像在超高清显示阵列4上显示时，超高清显示阵列 4的0行显示的是前述行视频数据0所包含的图像，即超高清显示阵列4的与行视频数据0相对应的0行显示行视频数据0所包含的图像；超高清显示阵列4的2行显示的是前述行视频数据1所包含的图像，即超高清显示阵列4的与行视频数据1相对应的2行显示行视频数据1所包含的图像；超高清显示阵列4的4行显示的是前述行视频数据2所包含的图像，即超高清显示阵列4的与行视频数据2相对应的4行显示行视频数据2所包含的图像；其他的以此类推。该奇数场超高清图像在超高清显示阵列4上显示时，超高清显示阵列4的1行显示的是前述行视频数据0所包含的图像，即超高清显示阵列4的与行视频数据0相对应的1行显示行视频数据0所包含的图像；超高清显示阵列4的3行显示的是前述行视频数据1所包含的图像，即超高清显示阵列4的与行视频数据1相对应的3行显示行视频数据1所包含的图像；超高清显示阵列4的5行显示的是前述行视频数据2所包含的图像，即超高清显示阵列4的与行视频数据2相对应的5行显示行视频数据2所包含的图像；其他的以此类推。
缓存单元2用于缓存前述若干行视频数据中的K行行视频数据，比如，该K行行视频数据分别为：行视频数据0、行视频数据1、行视频数据2、行视频数据3；待该K行行视频数据并行输出后，再缓存该若干行视频数据中的另外K行行视频数据，比如，该另外K行行视频数据分别为：行视频数据4、行视频数据5、行视频数据6、行视频数据7，或者该另外K行行视频数据分别为：行视频数据8、行视频数据9、行视频数据10、行视频数据11；以此类推，直至缓存该若干行视频数据中的最后K行行视频数据，在逐行扫描时，该最后K行行视频数据分别为：行视频数据M-4、行视频数据M-3、行视频数据M-2、行视频数据M-1；在隔行扫描时，该最后K行行视频数据分别为：行视频数据(M/2)-4、行视频数据(M/2)-3、行视频数据(M/2)-2、行视频数据(M/2)-1。
缓存单元2并行输出K行行视频数据至接收输出驱动单元3，接收输出驱动单元3中的控制单元利用相应的行视频数据产生数字门驱动信号以及数字源驱动信号并分别输送至对应的门驱动单元以及源驱动单元。K个门驱动单元以及K个源驱动单元将K行行视频数据同时加载至超高清显示阵列4以正确并高动态范围的显示超高清视频图像。其中，K为大于或等于2的自然数，且K小于或等于一帧/场超高清图像按行分割成的行视频数据的行数。比如，如图2所呈现的实施例中，缓存单元2并行输出K行行视频数据至接收输出驱动单元3的通道数为K，接收输出驱动单元3包含K个控制单元、K个源驱动单元以及K个门驱动单元，缓存单元2的通道与接收输出驱动单元3的控制单元一一对应连通。比如，缓存单元2的通道0与接收输出驱动单元3的控制单元0连通，缓存单元2的通道1与接收输出驱动单元3的控制单元1连通，其他的以此类推。图2所呈现的实施例中，控制单元0接收缓存单元2从缓存单元2的通道0所输出的行视频数据，控制单元0根据该行视频数据产生数字源驱动信号与数字门驱动信号并分别对应输出给源驱动单元0以及门驱动单元0；控制单元1接收缓存单元2从缓存单元2的通道1所输出的行视频数据，控制单元1根据该行视频数据产生数字源驱动信号与数字门驱动信号并分别对应输出给源驱动单元1以及门驱动单元1；其他的以此类推。
接收输出驱动单元3用于将所接收到的该缓存单元2所并行输出的K行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该K行行视频数据相对应的行同时显示，再将所接收的该缓存单元2所并行输出的另外K行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该另外K行行视频数据相对应的行同时显示，以此类推，直至驱动该超高清显示阵列4的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
为清晰起见，用前述所举例说明接收输出驱动单元3如何工作。
(1)在逐行扫描时，比如，该K行行视频数据分别为：行视频数据0、行视频数据1、行视频数据2、行视频数据3，该另外K行行视频数据分别为：行视频数据4、行视频数据5、行视频数据6、行视频数据7，最后K行行视频数据分别为：行视频数据M-4、行视频数据M-3、行视频数据M-2、行视频数据M-1。接收输出驱动单元3将所接收到的缓存单元2所并行输出的K行行视频数据即行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出至超高清显示阵列4，比如，行视频数据0从缓存单元2的通道0输出给接收输出驱动单元3的控制单元0，行视频数据1从缓存单元2的通道1输出给接收输出驱动单元3的控制单元1，行视频数据2从缓存单元2的通道2输出给接收输出驱动单元3的控制单元2，行视频数据3从缓存单元2的通道3输出给接收输出驱动单元3的控制单元3。接收输出驱动单元3驱动该超高清显示阵列4的与该K行行视频数据相对应的行同时显示，即超高清显示阵列4的0行显示行视频数据0所包含的图像，超高清显示阵列4的1行显示行视频数据1所包含的图像，超高清显示阵列4的2行显示行视频数据2所包含的图像，超高清显示阵列4的3行显示行视频数据3所包含的图像。待行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出至超高清显示阵列4并同时驱动0-3行显示后，接收输出驱动单元3再将所接收到的该缓存单元2所并行输出的另外K行行视频数据即行视频数据4、行视频数据5、行视频数据6、行视频数据7并行输出至超高清显示阵列4，比如，行视频数据4从缓存单元2的通道0输出给接收输出驱动单元3的控制单元0，行视频数据5从缓存单元2的通道1输出给接收输出驱动单元3的控制单元1，行视频数据6从缓存单元2的通道2输出给接收输出驱动单元3的控制单元2，行视频数据7从缓存单元2的通道3输出给接收输出驱动单元3的控制单元3。接收输出驱动单元3再驱动该超高清显示阵列4的与该另外K行行视频数据相对应的行同时显示，即超高清显示阵列4的4行显示行视频数据4所包含的图像，超高清显示阵列4的5行显示行视频数据5所包含的图像，超高清显示阵列4的6行显示行视频数据6所包含的图像，超高清显示阵列4的7行显示行视频数据7所包含的图像。以此类推，最后K行行视频数据分别为：行视频数据M-4、行视频数据M-3、行视频数据M-2、行视频数据M-1对应在该超高清显示阵列4的与该最后K行行视频数据相对应的行同时显示。以此类推，直至驱动该超高清显示阵列4的与该一帧超高清图像的该若干行视频数据相对应的行全部完成显示。
(2)在隔行扫描时，比如，偶/奇数场超高清图像的K行行视频数据分别 为：行视频数据0、行视频数据1、行视频数据2、行视频数据3，该另外K行行视频数据分别为：行视频数据4、行视频数据5、行视频数据6、行视频数据7，最后K行行视频数据分别为：行视频数据(M/2)-4、行视频数据(M/2)-3、行视频数据(M/2)-2、行视频数据(M/2)-1。接收输出驱动单元3将所接收到的缓存单元2所并行输出的K行行视频数据即行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出至超高清显示阵列4，比如，行视频数据0从缓存单元2的通道0输出给接收输出驱动单元3的控制单元0，行视频数据1从缓存单元2的通道1输出给接收输出驱动单元3的控制单元1，行视频数据2从缓存单元2的通道2输出给接收输出驱动单元3的控制单元2，行视频数据3从缓存单元2的通道3输出给接收输出驱动单元3的控制单元3。接收输出驱动单元3驱动该超高清显示阵列4的与该K行行视频数据相对应的行同时显示。①在隔行扫描方式的偶数场扫描时，超高清显示阵列4的0行显示行视频数据0所包含的图像，超高清显示阵列4的2行显示行视频数据1所包含的图像，超高清显示阵列4的4行显示行视频数据2所包含的图像，超高清显示阵列4的6行显示行视频数据3所包含的图像。待行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出至超高清显示阵列4并同时驱动0、2、4、6行显示后，接收输出驱动单元3再将所接收到的该缓存单元2所并行输出的另外K行行视频数据即行视频数据4、行视频数据5、行视频数据6、行视频数据7并行输出至超高清显示阵列4，比如，行视频数据4从缓存单元2的通道0输出给接收输出驱动单元3的控制单元0，行视频数据5从缓存单元2的通道1输出给接收输出驱动单元3的控制单元1，行视频数据6从缓存单元2的通道2输出给接收输出驱动单元3的控制单元2，行视频数据7从缓存单元2的通道3输出给接收输出驱动单元3的控制单元3。接收输出驱动单元3再驱动该超高清显示阵列4的与该另外K行行视频数据相对应的行同时显示，即超高清显示阵列4的8行显示行视频数据4所包含的图像，超高清显示阵列4的10行显示行视频数据5所包含的图像，超高清显示阵列4的12行显示行视频数据6所包含的图像，超高清显示阵列4的14行显示行视频数据7所包含的图像。以此类推，直至驱动该超高清显示阵列4的与该偶数场超高清图像的该若干行视频数据相对应的行全部完成显示。②在隔行扫描方式的奇数场扫描时，超高清显示阵列4的1行显示行视频数据0所包含的图像，超高清显示阵列4的3行显示行视频数据1所包含的图像，超高清显示阵列4的5行显示行视频数据2所包含的图像，超高清显示阵列4的7行显示行视频数据3所包含的图像。待行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出至超高清显示阵列4并同时驱动1、3、5、7行显示后，接收输出驱动单元3再将所接收到的该缓存单元2所并行输出的另外K行行视频数据即行视频数据4、行视频数据5、行视频数据6、行视频数据7并行输出至超高清显示阵列4，比如，行视频数据4从缓存单元2的通道0输出给接收输出驱动单元3的控制单元0，行视频数据5从缓存单元2的通道1输出给接收输出驱动单元3的控制单元1，行视频数据6从缓存单元2的通道2输出给接收输出驱动单元3的控制单元2，行视频数据7从缓存单元2的通道3输出给接收输出驱动单元3的控制单元3。接收输出驱动单元3再驱动 该超高清显示阵列4的与该另外K行行视频数据相对应的行同时显示，即超高清显示阵列4的9行显示行视频数据4所包含的图像，超高清显示阵列4的11行显示行视频数据5所包含的图像，超高清显示阵列4的13行显示行视频数据6所包含的图像，超高清显示阵列4的15行显示行视频数据7所包含的图像。以此类推，直至驱动该超高清显示阵列4的与该奇数场超高清图像的该若干行视频数据相对应的行全部完成显示。
在一些实施例中，逐行扫描时，前述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行的K行。
在一些实施例中，缓存单元2通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口将所述K行行视频数据并行输送至接收输出驱动单元3。
在一些实施例中，前述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
如图7，本发明的一种超高清图像显示驱动方法，包括以下步骤：
S1，逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；隔行扫描时，将一场超高清图像按行分割成若干行视频数据；
S2，缓存该若干行视频数据中的K行行视频数据；
S3，并行输出所缓存的该K行行视频数据至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示；
S4，待该K行行视频数据并行输出后，再缓存该若干行视频数据中的另外K行行视频数据；
S5，并行输出所缓存的该另外K行行视频数据至该超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示；
S6，以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
在一些实施例中，逐行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行的K行。
在一些实施例中，步骤S3中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该K行行视频数据；所述步骤S5中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该另外K行行视频数据。
在一些实施例中，前述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
如图3、4，K＝4，即4个门驱动单元分别为门驱动单元0、门驱动单元1、门驱动单元2、门驱动单元3，4个源驱动单元分别为源驱动单元0、源驱动单元1、源驱动单元2、源驱动单元3。
下面以8K分辨率(7680x4320)的超高清图像经过分割单元1与缓存单元2 通过4个(即K＝4)通道(通道编号为j，j＝0，1，2，3)分别并行输出4行行视频数据为例，依据扫描方式(逐行扫描或者隔行扫描)对本发明作进一步具体说明。
(1)在对超高清显示阵列4进行逐行扫描时，视频数据来源于通道j的像素单元的行编号m与其列编号n满足：
Figure PCTCN2018089381-appb-000001
j＝0,1,2,...,K-1，K＝4。
参见图2、3，分割单元1将一帧超高清图像按行分割成M行视频数据。
缓存单元2缓存前述M行行视频数据中的4行行视频数据，如行视频数据0、行视频数据1、行视频数据2、行视频数据3。
接收输出驱动单元3用于将所接收的该缓存单元2所并行输出的前述4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该4行行视频数据相对应的行同时显示。具体的，4个通道并行输出的该4行行视频数据即行视频数据0、行视频数据1、行视频数据2、行视频数据3(每行行视频数据均包括对应的视频数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧同步信号Vsync)分别一一对应输入至4个控制单元0、控制单元1、控制单元2、控制单元3。
如图2、3所示，比如，超高清显示阵列4支持逐行扫描的8K分辨率。行编号满足m＝4*i(i为自然数，即0，1，2，…)的像素单元连接到门驱动单元0以及源驱动单元0上，行编号满足m＝4*i+1的像素单元连接到门驱动单元1以及源驱动单元1上，行编号满足m＝4*i+2的像素单元连接到门驱动单元2以及源驱动单元2上，行编号满足m＝4*i+3的像素单元连接到门驱动单元3以及源驱动单元3上。比如，行编号为2、列编号为3的像素单元连接到门驱动单元2以及源驱动单元2上。
具体的，随着4个通道的并行行视频数据输入，控制单元0根据自身所接收的从缓存单元2的通道0所输出的行视频数据0包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及帧同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元0以及源驱动单元0，门驱动单元0以及源驱动单元0将对应的数据Data扫描到门驱动单元0选中的超高清显示阵列4的行编号为0的像素单元，超高清显示阵列4的0行显示行视频数据0所包含的图像。同时，控制单元1根据自身所接收的从缓存单元2的通道1所输出的行视频数据1包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及帧同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元1以及源驱动单元1，门驱动单元1以及源驱动单元1将对应的数据Data扫描到门驱动单元1选中的行编号为1上对应的像素单元，超高清显示阵列4的1行显示行视频数据1所包含的图像。同时，控制单元2根据自身所接收的从缓存单元2的通道2所输出的行视频数据2包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及帧同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元2以及源驱动单元2，门驱动单元2以及源驱动单元2将对应的数据Data扫描到门驱动单元2选中的行编号为2上对应的像素单元，超高清显示阵列4的2行显示行视频数据2所包含的图像。 同时，控制单元3根据自身所接收的从缓存单元2的通道3所输出的行视频数据3包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及帧同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元3以及源驱动单元3，门驱动单元3以及源驱动单元3将对应的数据Data扫描到门驱动单元3选中的行编号为3上对应的像素单元，超高清显示阵列4的3行显示行视频数据3所包含的图像。
待前述行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出后，缓存单元2再缓存前述M行行视频数据中的另外4行行视频数据，如行视频数据4、行视频数据5、行视频数据6、行视频数据7。
接收输出驱动单元3用于将所接收的该缓存单元2所并行输出的前述另外4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该另外4行行视频数据相对应的行同时显示。超高清显示阵列4的4、5、6、7行对应同时显示行视频数据4、5、6、7所包含的图像。
待前述行视频数据4、行视频数据5、行视频数据6、行视频数据7并行输出后，缓存单元2再缓存前述M行视频数据中的另外4行行视频数据，如行视频数据8、行视频数据9、行视频数据10、行视频数据11。
以此类推，当4个通道扫描完8K的超高清像素阵列4，一帧完整的超高清图像便在超高清显示阵列4显现出来。
上述对超高清显示阵列进行逐行扫描时的门驱动时序如图5所示，该4行对应的门驱动信号为高电平时表示选中该4行并进行相应的源驱动。
(2)在对所述超高清显示阵列4进行隔行扫描时，行视频数据来源于通道j的像素单元的行编号m与列编号n满足：
Figure PCTCN2018089381-appb-000002
或
Figure PCTCN2018089381-appb-000003
i＝0,1,2,...，j＝0,1,2,...,K-1，K＝4。
本实施例中，缓存单元2并行输出4行行视频数据，即K＝4。
如图2、4所示，比如，超高清显示阵列4支持隔行扫描的8K分辨率。行编号满足m＝8*i或m＝8*i+1(i为自然数，即0，1，2，…)的像素单元连接到门驱动单元0以及源驱动单元0上，行编号满足m＝8*i+2或m＝8*i+3的像素单元连接到门驱动单元1以及源驱动单元1上，行编号满足m＝8*i+4或m＝8*i+5的像素单元连接到门驱动单元2以及源驱动单元2上，行编号满足m＝8*i+6或m＝8*i+7的像素单元连接到门驱动单元3以及源驱动单元3上。比如，行编号为2、列编号为3的像素单元连接到门驱动单元1以及源驱动单元1上。①在每一偶数场超高清图像扫描时：
参见图2、4，分割单元1将一场超高清图像按行分割成M/2行行视频数据。
缓存单元2缓存前述M/2行行视频数据中的4行行视频数据，如行视频数据0、行视频数据1、行视频数据2、行视频数据3。
接收输出驱动单元3用于将所接收到的该缓存单元2所并行输出的前述4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该4行行视频数据相对应的行同时显示。具体的，4个通道并行输出的该4行行视频数据即行视频数据0、行视频数据1、行视频数据2、行视频数据3(每行行视频数 据均包括对应的视频数据Data，数据时钟Clock，数据有效信号DE，行同步信号Hsync以及场同步信号Vsync)分别一一对应输入至4个控制单元0、控制单元1、控制单元2、控制单元3。
随着4个通道的并行行视频数据输入，控制单元0根据自身所接收的从缓存单元2的通道0所输出的行视频数据0包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元0以及源驱动单元0，门驱动单元0以及源驱动单元0将对应的数据Data扫描到门驱动单元0选中的行编号为0上对应的像素单元，超高清显示阵列4的0行显示行视频数据0所包含的图像。同时，控制单元1根据自身所接收的从缓存单元2的通道1所输出的行视频数据1包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元1以及源驱动单元1，门驱动单元1以及源驱动单元1将对应的数据Data扫描到门驱动单元1选中的行编号为2上对应的像素单元，超高清显示阵列4的2行显示行视频数据1所包含的图像。同时，控制单元2根据自身所接收的从缓存单元2的通道2所输出的行视频数据2包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元2以及源驱动单元2，门驱动单元2以及源驱动单元2将对应的数据Data扫描到门驱动单元2选中的行编号为4上对应的像素单元，超高清显示阵列4的4行显示行视频数据2所包含的图像。同时，控制单元3根据自身所接收的从缓存单元2的通道3所输出的行视频数据3包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元3以及源驱动单元3，门驱动单元3以及源驱动单元3将对应的数据Data扫描到门驱动单元3选中的行编号为6上对应的像素单元，超高清显示阵列4的6行显示行视频数据3所包含的图像。
待前述行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出后，缓存单元2再缓存前述M/2行行视频数据中的另外4行行视频数据，如行视频数据4、行视频数据5、行视频数据6、行视频数据7。
接收输出驱动单元3用于将所接收到的该缓存单元2所并行输出的前述另外4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该另外4行行视频数据相对应的行同时显示。超高清显示阵列4的8、10、12、14行对应同时显示行视频数据4、5、6、7所包含的图像。
以此类推，当4个通道传输一场完整的超高清视频图像的偶数场视频数据，偶数场的超高清图像便在超高清显示阵列4显现出来。
②在每一奇数场超高清图像扫描时：
参见图2、4，分割单元1将一场超高清图像按行分割成M/2行行视频数据。
缓存单元2缓存前述M/2行行视频数据中的4行行视频数据，如行视频数据0、行视频数据1、行视频数据2、行视频数据3。
接收输出驱动单元3用于将所接收到的该缓存单元2所并行输出的前述4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该4行 行视频数据相对应的行同时显示。具体的，4个通道并行输出的该4行行视频数据即行视频数据0、行视频数据1、行视频数据2、行视频数据3(每行行视频数据均包括对应的视频数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync)分别输入至4个控制单元0、控制单元1、控制单元2、控制单元3。
随着4个通道的并行行视频数据输入，控制单元0根据自身所接收的从缓存单元2的通道0所输出的行视频数据0包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元0以及源驱动单元0，门驱动单元0以及源驱动单元0将对应的数据Data扫描到门驱动单元0选中的行编号为1上对应的像素单元，超高清显示阵列4的1行显示行视频数据0所包含的图像。同时，控制单元1根据自身所接收的从缓存单元2的通道1所输出的行视频数据1包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元1以及源驱动单元1，门驱动单元1以及源驱动单元1将对应的数据Data扫描到门驱动单元1选中的行编号为3上对应的像素单元，超高清显示阵列4的3行显示行视频数据1所包含的图像。同时，控制单元2根据自身所接收的从缓存单元2的通道2所输出的行视频数据2包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元2以及源驱动单元2，门驱动单元2以及源驱动单元2将对应的数据Data扫描到门驱动单元2选中的行编号为5上对应的像素单元，超高清显示阵列4的5行显示行视频数据2所包含的图像。同时，控制单元3根据自身所接收的从缓存单元2的通道3所输出的行视频数据3包括的时钟Clock、数据有效信号DE、行同步信号Hsync以及场同步信号Vsync产生对应的数字门驱动信号以及数字源驱动信号并分别送至门驱动单元3以及源驱动单元3，门驱动单元3以及源驱动单元3将对应的数据Data扫描到门驱动单元3选中的行编号为7上对应的像素单元，超高清显示阵列4的7行显示行视频数据3所包含的图像。
待前述行视频数据0、行视频数据1、行视频数据2、行视频数据3并行输出后，缓存单元2再缓存前述M/2行行视频数据中的另外4行行视频数据，如行视频数据4、行视频数据5、行视频数据6、行视频数据7。
接收输出驱动单元3用于将所接收到的该缓存单元2所并行输出的前述另外4行行视频数据并行输出至超高清显示阵列4并驱动该超高清显示阵列4的与该另外4行行视频数据相对应的行同时显示。超高清显示阵列4的9、11、13、15行对应同时显示行视频数据4、5、6、7所包含的图像。
以此类推，当4个通道传输一场完整的超高清视频图像的奇数场视频数据，奇数场对应的超高清图像便在超高清显示阵列4显现出来。
上述对超高清显示阵列进行隔行扫描时的门驱动时序如图6所示，该4行对应的门驱动信号为高电平时表示选中该4行并进行相应的源驱动。
在本发明所提供的实施例中，应该理解到，所揭露的装置和方法，可以通 过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个装置，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本发明的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器(processor)执行本发明各个实施例所述方法的全部或部分步骤。而前述的存储介质/单元包括：通用串行总线闪存盘(Universal Serial Bus flash disk)、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (8)

  1. 一种超高清图像显示驱动方法，其特征在于，包括以下步骤：
    S1，逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；隔行扫描时，将一场超高清图像按行分割成若干行视频数据；
    S2，缓存该若干行视频数据中的K行行视频数据,其中，K为大于或等于2的自然数，且K小于或等于一帧/场超高清图像按行分割成的行视频数据的行数；
    S3，并行输出所缓存的该K行行视频数据至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示；
    S4，待该K行行视频数据并行输出后，再缓存该若干行视频数据中的另外K行行视频数据；
    S5，并行输出所缓存的该另外K行行视频数据至该超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示；
    S6，以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
  2. 根据权利要求1所述的超高清图像显示驱动方法，其特征在于，逐行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行的K行。
  3. 根据权利要求1所述的超高清图像显示驱动方法，其特征在于，所述步骤S3中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该K行行视频数据；所述步骤S5中，通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口并行输出所缓存的该另外K行行视频数据。
  4. 根据权利要求1所述的超高清图像显示驱动方法，其特征在于，所述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
  5. 一种超高清图像显示驱动装置，其特征在于，包括：
    分割单元，其用于逐行扫描时，将一帧超高清图像按行分割成若干行视频数据；其用于隔行扫描时，将一场超高清图像按行分割成若干行视频数据；
    缓存单元，其用于缓存该若干行视频数据中的K行行视频数据，待该K行行视频数据并行输出后再缓存该若干行视频数据中的另外K行行视频数据，以此类推，直至缓存该若干行视频数据中的最后K行行视频数据；
    接收输出驱动单元，其用于将所接收到的该缓存单元所并行输出的K行行视频数据并行输出至超高清显示阵列并驱动该超高清显示阵列的与该K行行视频数据相对应的行同时显示，再将所接收到的该缓存单元所并行输出的另外K行行视频数据并行输出至超高清显示阵列并驱动该超高清显示阵列的与该另外K行行视频数据相对应的行同时显示，以此类推，直至驱动该超高清显示阵列的与该一帧/场超高清图像的该若干行视频数据相对应的行全部完成显示。
  6. 根据权利要求5所述的超高清图像显示驱动装置，其特征在于，逐行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相邻的K行；隔行扫描时，所述K行行视频数据对应该超高清显示阵列中彼此相隔一行的K行。
  7. 根据权利要求5所述的超高清图像显示驱动装置，其特征在于，所述缓存单元通过多个HDMI接口、多个DP接口、多个V-BY-ONE接口、多个LVDS接口或者多个MIPI接口将所述K行行视频数据并行输送至所述接收输出驱动单元。
  8. 根据权利要求5所述的超高清图像显示驱动装置，其特征在于，所述行视频数据包括视频图像数据Data、数据时钟Clock、数据有效信号DE、行同步信号Hsync以及帧/场同步信号Vsync。
PCT/CN2018/089381 2018-05-31 2018-05-31 超高清图像显示驱动方法及装置 WO2019227440A1 (zh)

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
CN102759795A (zh) * 2011-04-29 2012-10-31 上海数字电视国家工程研究中心有限公司 光束并行扫描成像的图像显示***及方法
CN104038719A (zh) * 2014-05-29 2014-09-10 清华大学 一种基于视频帧的超高清视频显示***及方法
CN105719588A (zh) * 2014-12-22 2016-06-29 三星显示有限公司 扫描线驱动器芯片和包括其的显示设备
CN106920499A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 显示装置及其驱动方法和个人沉浸式装置
CN106993150A (zh) * 2017-04-14 2017-07-28 深圳市唯奥视讯技术有限公司 一种兼容超高清视频输入的视频图像处理***及方法
US20170287429A1 (en) * 2016-03-29 2017-10-05 Samsung Electronics Co., Ltd. Display driving circuit and display device comprising the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447156A (zh) * 2007-11-29 2009-06-03 三星电子株式会社 显示设备及其驱动方法
CN102759795A (zh) * 2011-04-29 2012-10-31 上海数字电视国家工程研究中心有限公司 光束并行扫描成像的图像显示***及方法
CN104038719A (zh) * 2014-05-29 2014-09-10 清华大学 一种基于视频帧的超高清视频显示***及方法
CN105719588A (zh) * 2014-12-22 2016-06-29 三星显示有限公司 扫描线驱动器芯片和包括其的显示设备
CN106920499A (zh) * 2015-12-28 2017-07-04 乐金显示有限公司 显示装置及其驱动方法和个人沉浸式装置
US20170287429A1 (en) * 2016-03-29 2017-10-05 Samsung Electronics Co., Ltd. Display driving circuit and display device comprising the same
CN106993150A (zh) * 2017-04-14 2017-07-28 深圳市唯奥视讯技术有限公司 一种兼容超高清视频输入的视频图像处理***及方法

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