WO2019223331A1 - 移位寄存器单元、驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元、驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019223331A1
WO2019223331A1 PCT/CN2019/070179 CN2019070179W WO2019223331A1 WO 2019223331 A1 WO2019223331 A1 WO 2019223331A1 CN 2019070179 W CN2019070179 W CN 2019070179W WO 2019223331 A1 WO2019223331 A1 WO 2019223331A1
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Prior art keywords
pull
node
voltage
input terminal
circuit
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PCT/CN2019/070179
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English (en)
French (fr)
Inventor
王迎
李红敏
王栋
唐锋景
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京东方科技集团股份有限公司
合肥京东方光电科技有限公司
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Priority to US16/479,484 priority Critical patent/US11238769B2/en
Priority to EP19736957.2A priority patent/EP3806079A1/en
Publication of WO2019223331A1 publication Critical patent/WO2019223331A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes

Definitions

  • the present disclosure relates to the technical field of display driving, and in particular, to a shift register unit, a driving method, a gate driving circuit, and a display device.
  • GOA Gate On Array, gate drive circuit provided on the array substrate
  • Gate COF Chip On Flex, or, Chip On On Film
  • the current GOA circuit design is relatively complicated (the number of clock signals used is large and the number of transistors used is large), and the noise is obvious.
  • the existing shift register unit in the existing gate drive circuit directly provides an input signal to an adjacent next-stage shift register unit through its gate drive signal output end, so that the gate drive signal output end needs to be adjacent
  • the next stage shift register unit provides an input signal and causes a problem of insufficient driving capability, which in turn results in low stability of the gate driving signal output.
  • an embodiment of the present disclosure provides a shift register unit, including: an input sub-circuit, a pull-up node control sub-circuit, a pull-down node control sub-circuit, a gate drive output sub-circuit, and a carry signal output sub-circuit.
  • the input sub-circuit is respectively connected to an input terminal, a second clock signal input terminal, and a pull-up node, and is used for input signals to be accessed by the input terminal under the control of the second clock signal input terminal in the input stage. Write the pull-up node;
  • the pull-up node control sub-circuit is respectively connected to the pull-up node, the pull-down node, the first clock signal input terminal and the first voltage input terminal, and is used for resetting the first clock signal input terminal and the Write a first voltage into the pull-up node under the control of the pull-down node; the first voltage input terminal is used to input the first voltage;
  • the pull-down node control sub-circuit is respectively connected to a pull-down node, a pull-up node, a first clock signal input terminal, a first voltage input terminal, and a second voltage input terminal, and is used for inputting and Write the first voltage to the pull-down node under the control of a node, and write a second voltage to the pull-down node under the control of the first clock signal input terminal in the reset phase; the second A voltage input terminal for inputting the second voltage;
  • the gate driving output sub-circuit is connected to the pull-up node, the pull-down node, the gate driving signal output terminal, the third clock signal input terminal, and the third voltage input terminal, respectively, and is used for inputting and In the output stage, under the control of the pull-up node, a third clock signal is output through the gate drive signal output terminal, and in the reset phase, under the control of the pull-down node, output through the gate drive signal
  • the third terminal outputs a third voltage
  • the third clock signal input terminal is used to input the third clock signal
  • the third voltage input terminal is used to input the third voltage
  • the carry signal output sub-circuit is respectively connected to the pull-up node, the pull-down node, the carry signal output terminal, the third clock signal input terminal, and the third voltage input terminal, and is configured to control the pull-up node, the pull-down node, and the third voltage input terminal. Pull up the potential of the node, and in the input phase and the output phase, under the control of the pull-up node, output the third clock signal through the carry signal output terminal, in the reset phase, in the Under the control of the pull-down node, the third voltage is output through the carry signal output terminal.
  • the pull-down node control sub-circuit is further configured to write the second voltage under a control of the first clock signal input terminal in a reset phase before the input phase. Into the drop-down node.
  • the pull-down node control sub-circuit includes a first pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the pull-down node. Said first voltage input terminal connection;
  • a second pull-down node controls the transistor, a gate is connected to the first clock signal input terminal, a first electrode is connected to the second voltage input terminal, and a second electrode is connected to the pull-down node.
  • the pull-down node control sub-circuit is further configured to write a first clock signal to the pull-down node under the control of the pull-up node in the input phase and the output phase.
  • the first clock signal input terminal is used to input the first clock signal.
  • the pull-down node control sub-circuit further includes a third pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the pull-down node.
  • the first clock signal input terminal is connected.
  • the pull-up node control sub-circuit is further configured to change the first voltage under the control of the first clock signal input terminal and the pull-down node in the reset phase. Write the pull-up node.
  • the pull-up node control sub-circuit includes a first pull-up node control transistor, a gate connected to the first clock signal input terminal, and a first pole connected to the pull-up node; as well as,
  • a second pull-up node controls the transistor, a gate is connected to the pull-down node, a first pole is connected to a second pole of the first pull-up node control transistor, and a second pole is connected to the first voltage input terminal.
  • the gate drive output sub-circuit includes: a first gate drive output transistor, a gate connected to the pull-up node, a first pole connected to the third clock signal input terminal, A second electrode is connected to the gate driving signal output terminal; and
  • a second gate drive output transistor a gate connected to the pull-down node, a first pole connected to the gate drive signal output terminal, and a second pole connected to the third voltage input terminal;
  • the carry signal output sub-circuit includes a first carry signal output transistor, a gate connected to the pull-up node, a first pole connected to the third clock signal input terminal, and a second pole connected to the carry signal output terminal. connection;
  • a second carry signal output transistor having a gate connected to the pull-down node, a first pole connected to the carry signal output terminal, a second pole connected to the third voltage input terminal, and,
  • the first end of the storage capacitor is connected to the pull-up node, and the second end is connected to the carry signal output end.
  • the second gate drive output transistor and the second carry signal output transistor are both N-type transistors, and the first voltage inputted by the first voltage input terminal is substantially smaller than the first voltage input terminal.
  • the second gate drive output transistor and the second carry signal output transistor are both P-type transistors, and the first voltage input from the first voltage input terminal is substantially larger than the third voltage input from the third voltage input terminal. Voltage.
  • the input subcircuit includes: an input transistor, a gate connected to the second clock signal input terminal, a first pole connected to the pull-up node, and a second pole connected to the input terminal connection.
  • the first voltage is a first low voltage VGL1
  • the second voltage is a high voltage VGH
  • the third voltage is a second low voltage VGL2.
  • the second terminal of the storage capacitor is only connected to the carry signal output terminal; or,
  • the second end of the storage capacitor is only connected to the gate drive signal output end;
  • a second terminal of the storage capacitor is connected to the gate driving signal output terminal and the carry signal output terminal, respectively.
  • an embodiment of the present disclosure further provides a method for driving a shift register unit, which is applied to the shift register unit described in the first aspect, wherein each display period includes sequentially set In an input phase, an output phase, and a reset phase, the driving method of the shift register unit includes:
  • an input terminal is connected to an input signal, and an input sub-circuit writes the input signal to a pull-up node under the control of a second clock signal input terminal, so that the potential of the pull-up node is an effective level.
  • the carry signal output sub-circuit controls that the potential of the pull-up node is still an effective level
  • the pull-down node control sub-circuit writes a first voltage to the pull-down node under the control of the pull-up node, and the gate drive output sub-circuit is under the control of the pull-up node,
  • the third clock signal is output through the gate drive signal output terminal;
  • the carry signal output sub-circuit outputs the third clock signal through the carry signal output terminal under the control of the pull-up node;
  • a pull-up node control sub-circuit writes a first voltage to the pull-up node under the control of a first clock signal input terminal and the pull-down node; a gate drive output sub-circuit is on the pull-up node.
  • the pull-down node control sub-circuit stops writing the first voltage to the pull-down node under the control of the pull-up node, and the pull-down node control sub-circuit is controlled by the first clock signal
  • a second voltage is written into the pull-down node, and the gate drive output sub-circuit outputs a third voltage through the gate drive signal output terminal under the control of the pull-down node, and the carry signal is output
  • the sub-circuit outputs a third voltage through the carry signal output terminal under the control of the pull-down node.
  • the driving method of the shift register unit further includes:
  • the pull-down node control sub-circuit writes a first clock signal to the pull-down node under the control of the pull-up node;
  • the pull-down node control sub-circuit stops writing the first clock signal to the pull-down node under the control of the pull-up node.
  • the display cycle further includes a reset phase set before the input phase;
  • the driving method of the shift register unit further includes:
  • the pull-down node control sub-circuit In the reset phase, the pull-down node control sub-circuit writes a second voltage to the pull-down node under the control of the first clock signal input terminal, and the pull-up node control sub-circuit is in the first Under the control of a clock signal input terminal and the pull-down node, a first voltage is written into the pull-up node.
  • the gate drive output subcircuit includes a first gate drive output transistor and a second gate drive output transistor;
  • the carry signal output subcircuit includes a first carry signal output transistor, a second Carry signal output transistor and storage capacitor;
  • the second gate drive output transistor and the second carry signal output transistor are both N-type transistors, and the first voltage input from the first voltage input terminal is substantially smaller than the third voltage input from the third voltage input terminal. A voltage so that the second gate drive output transistor and the second carry signal output transistor can be in an off state during the output stage; or,
  • the second gate drive output transistor and the second carry signal output transistor are both P-type transistors, and the first voltage input from the first voltage input terminal is substantially larger than the third voltage input from the third voltage input terminal. A voltage so that in the output stage, the second gate drive output transistor and the second carry signal output transistor can be in an off state.
  • an embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of cascaded shift register units as described in the first aspect;
  • the carry signal output terminal included in the shift register unit of each stage is connected to the input terminal included in the adjacent next stage shift register unit.
  • an embodiment of the present disclosure further provides a display device including the gate driving circuit as described in the first aspect.
  • FIG. 1 is a structural diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 2 is a circuit diagram of a specific embodiment of a shift register unit according to an embodiment of the present disclosure
  • FIG 3 is an operation timing diagram of the specific embodiment of the shift register unit according to the embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a cascade relationship between the first four stages of shift register units included in the gate driving circuit according to the embodiment of the present disclosure.
  • the transistors used in all embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics.
  • one of the poles is referred to as a first pole, and the other pole is referred to as a second pole.
  • the first pole may be a drain
  • the second pole may be a source
  • the first pole may be a source
  • the second pole may be a drain.
  • the shift register unit includes, for example, an input terminal STU, a gate driving signal output terminal GN_OUT, a carry signal output terminal CR, a first clock signal input terminal CLK1, and a second clock signal.
  • the input sub-circuit 11 is respectively connected to the input terminal STU, the second clock signal input terminal CLK2, and the pull-up node Q, and is used for the input stage, and will be controlled by the second clock signal input terminal CLK2.
  • the input signal accessed by the input STU is written into the pull-up node PU.
  • the pull-up node control sub-circuit 12 is connected to the pull-up node Q, the pull-down node QB, the first clock signal input terminal CLK1, and the first voltage input terminal, respectively, and is configured to reset the first clock signal during the reset phase. Under the control of the input terminal CLK1 and the pull-down node QB, a first voltage V1 is written into the pull-up node Q; the first voltage input terminal is used to input the first voltage V1.
  • the pull-down node control sub-circuit 13 is connected to a pull-down node QB, a pull-up node Q, a first clock signal input terminal CLK1, a first voltage input terminal, and a second voltage input terminal, respectively, and is used in the input stage and the output stage. Under the control of the pull-up node Q, write the first voltage V1 into the pull-down node QB, and in the reset phase, write the second voltage V2 under the control of the first clock signal input terminal CLK1. To the pull-down node QB; the second voltage input terminal is used to input the second voltage V2.
  • the gate drive output sub-circuit 15 is respectively connected to the pull-up node Q, the pull-down node QB, the gate drive signal output terminal GN_OUT, the third clock signal input terminal CLK3, and the third voltage input terminal,
  • a third clock signal is output through the gate driving signal output terminal GN_OUT
  • a third voltage V3 is output through the gate driving signal output terminal GN_OUT;
  • the third clock signal input terminal CLK3 is used to input the third clock signal, and the third voltage input terminal is used to input the third voltage V3.
  • the carry signal output sub-circuit 16 is connected to the pull-up node Q, the pull-down node QB, the carry signal output terminal CR, the third clock signal input terminal CLK3, and the third voltage input terminal, respectively. Configured to control the potential of the pull-up node Q, and in the input phase and the output phase, under the control of the pull-up node Q, output the third clock signal through the carry signal output terminal CR In the reset phase, under the control of the pull-down node QB, the third voltage V3 is output through the carry signal output terminal CR.
  • the number of transistors and clock signal lines used by the shift register unit according to the embodiment of the present disclosure is small, the structure is simple, the timing control is simple and convenient, and a narrow frame can be realized.
  • the shift register unit according to the embodiment of the present disclosure uses a carry signal output sub-circuit to provide a carry signal.
  • the carry signal output terminal provides an input signal to an adjacent next-stage shift register unit to avoid a gate drive signal output terminal. It is necessary to provide input signals to adjacent shift register units and cause insufficient driving capability to improve the gate driving signal output stability.
  • each display period includes, for example, a reset phase, an input phase, an output phase, and a reset phase which are sequentially set.
  • the pull-down node control sub-circuit 13 writes a second voltage V2 to the pull-down node QB under the control of the first clock signal input terminal CLK1, and the pull-up node control sub-circuit 12 Under the control of the first clock signal input terminal CLK1 and the pull-down node QB, write a first voltage V1 into the pull-up node Q.
  • the input terminal STU accesses the input signal
  • the input sub-circuit 11 writes the input signal to the pull-up node Q under the control of the second clock signal input terminal CLK2, so that the pull-up node Q Is the active level (the active level is the first gate drive transistor (not shown in FIG. 1) that enables the gate included in the gate drive output sub-circuit 15 to be connected to the pull-up node.
  • the pull-down node control sub-circuit 13 writes the first voltage V1 into the pull-down node QB under the control of the pull-up node Q, and the gate drive output sub-circuit 15 is under the control of the pull-up node Q
  • the third clock signal is output through the gate driving signal output terminal GN_OUT; the carry signal output sub-circuit 16 outputs the third clock signal through the carry signal output terminal CR under the control of the pull-up node Q.
  • the carry signal output sub-circuit 16 controls the potential of the pull-up node Q to be an active level, and the pull-down node control sub-circuit 13 writes the first voltage V1 under the control of the pull-up node QB.
  • the pull-down node, the gate drive output sub-circuit 15 outputs a third clock signal through the gate-drive signal output terminal GN_OUT under the control of the pull-up node Q; the carry signal output sub-circuit 16 controls the pull-up node Q
  • a third clock signal is output through the carry signal output terminal CR.
  • the pull-up node control sub-circuit 12 writes a first voltage V1 to the pull-up node Q under the control of the first clock signal input terminal CLK1 and the pull-down node QB;
  • the circuit 15 stops outputting the third clock signal through the gate driving signal output terminal GN_OUT under the control of the pull-up node Q, and the carry signal output sub-circuit 16 is under the control of the pull-up node Q
  • the pull-down node control sub-circuit 13 stops writing the first voltage V1 to the pull-down node QB under the control of the pull-up node Q
  • the pull-down node control sub-circuit 13 writes a second voltage V2 into the pull-down node QB under the control of the first clock signal input terminal CLK1, and the gate drive output sub-circuit 15 Under control, a third voltage V3 is output through the gate driving signal output terminal GN_OUT, and the carry signal output subcircuit 16 outputs a third
  • V1 may be, for example, a first low level
  • V2 may be, for example, a high level
  • V3 may be, for example, a second low level, but is not limited thereto.
  • a reset stage is also provided before the input stage, and the pull-down node control sub-circuit is further configured to, during the reset stage, control the second clock signal under the control of the first clock signal input terminal.
  • Voltage is written to the pull-down node to reset the potential of the pull-down node, which is convenient for the pull-up node control subcircuit to write the first voltage under the control of the first clock signal input terminal and the pull-down node during the reset phase.
  • Enter the pull-up node (the function of the pull-up node control sub-circuit during the reset phase will be described below) in order to clear the charge remaining in the pull-up node in the previous display period and improve the stability of the gate drive signal output.
  • the pull-down node control sub-circuit may include, for example, a first pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the first Voltage input connection; and,
  • a second pull-down node controls the transistor, a gate is connected to the first clock signal input terminal, a first electrode is connected to the second voltage input terminal, and a second electrode is connected to the pull-down node.
  • the pull-down node control sub-circuit is further configured to write a first clock signal to the pull-down node under the control of the pull-up node in the input phase and the output phase. node;
  • the first clock signal input terminal is used to input the first clock signal.
  • the pull-down node control sub-circuit further writes the first clock signal to the pull-down node in the input phase and the output phase, so that the potential of the pull-down node can be better controlled in the input phase and the output phase as The first level, and even if the potential of the pull-up node cannot be reduced in time during the reset phase, the potential of the pull-down node can be controlled to the second level.
  • the first level may be, for example, a low level
  • the second level may be, for example, a high level, but is not limited thereto.
  • the pull-down node control sub-circuit may further include, for example, a third pull-down node control transistor, a gate connected to the pull-up node, a first pole connected to the pull-down node, and a second pole connected to the first pull-down node.
  • a clock signal input terminal is connected.
  • the pull-up node control sub-circuit is further configured to control the first pull-down node under the control of the first clock signal input terminal and the pull-down node in the reset phase.
  • the voltage is written into the pull-up node in order to clear the charge remaining in the pull-up node in the previous display period, to avoid the influence of the charge remaining in the pull-up node on the gate drive signal output of the current display period, and to ensure that at the beginning of the input phase
  • the potential of the pull-up node is the first voltage, which improves the stability of the gate drive signal output.
  • the first gate-drive output transistor whose gate includes a gate connected to the pull-up node is turned off.
  • the first voltage may be, for example, a first low voltage, but is not limited thereto.
  • the pull-up node control sub-circuit may include: a first pull-up node control transistor, a gate of which is connected to the first clock signal input terminal, and a first pole of which is connected to the pull-up node; and,
  • a second pull-up node controls the transistor, a gate is connected to the pull-down node, a first pole is connected to a second pole of the first pull-up node control transistor, and a second pole is connected to the first voltage input terminal.
  • the gate drive output sub-circuit may include, for example, a first gate drive output transistor, a gate connected to the pull-up node, a first pole connected to the third clock signal input terminal, and a second pole Connected to the gate driving signal output terminal; and
  • a second gate driving output transistor has a gate connected to the pull-down node, a first electrode connected to the gate driving signal output terminal, and a second electrode connected to the third voltage input terminal.
  • the carry signal output sub-circuit may include, for example, a first carry signal output transistor, a gate connected to the pull-up node, a first pole connected to the third clock signal input terminal, and a second pole connected to the carry signal.
  • a second carry signal output transistor having a gate connected to the pull-down node, a first pole connected to the carry signal output terminal, and a second pole connected to the third voltage input terminal;
  • the first end of the storage capacitor is connected to the pull-up node, and the second end is connected to the carry signal output end.
  • the first voltage inputted by the first voltage input terminal is substantially smaller than A third voltage input from the third voltage input terminal, so that in the output stage, the second gate driving transistor and the second carry signal output transistor can be turned off, reducing leakage current, and reducing noise of the gate driving signal ;
  • the first voltage inputted by the first voltage input terminal is substantially larger than the first voltage inputted by the third voltage input terminal.
  • the third voltage so that in the output stage, the second gate driving transistor and the second carry signal output transistor can be turned off, reducing leakage current, and reducing noise of the gate driving signal.
  • the input sub-circuit may include, for example, an input transistor, a gate connected to the second clock signal input terminal, a first pole connected to the pull-up node, and a second pole connected to the input terminal.
  • a specific embodiment of the shift register unit includes, for example, an input terminal STU, a gate driving signal output terminal GN_OUT, a carry signal output terminal CR, an input sub-circuit 11, and a pull-up The node control sub-circuit 12, the pull-down node control sub-circuit 13, the gate drive output sub-circuit 15, and the carry signal output sub-circuit 16.
  • the input sub-circuit 11 includes, for example, an input transistor M1, a gate connected to the second clock signal input terminal CLK2, a drain connected to the pull-up node Q, and a source connected to the input terminal STU.
  • the pull-up node control sub-circuit 12 includes, for example, a first pull-up node control transistor M4, a gate connected to the first clock signal input terminal CLK1, and a drain connected to the pull-up node Q; and,
  • a second pull-up node control transistor M6 has a gate connected to the pull-down node QB, a drain connected to a source of the first pull-up node control transistor M4, and a source connected to the first voltage V1.
  • the pull-down node control sub-circuit 13 includes, for example, a first pull-down node control transistor M5, a gate connected to the pull-up node Q, a drain connected to the pull-down node QB, and a source connected to the first voltage V1; and,
  • the second pull-down node controls the transistor M3, the gate is connected to the first clock signal input terminal CLK1, the drain is connected to the second voltage V2, and the source is connected to the pull-down node QB; and,
  • the third pull-down node controls the transistor M2, a gate is connected to the pull-up node PU, a drain is connected to the pull-down node QB, and a source is connected to the first clock signal input terminal CLK1.
  • the gate driving output sub-circuit 15 includes, for example, a first gate driving output transistor M7_2, a gate connected to the pull-up node Q, a drain connected to the third clock signal input terminal CLK3, and a source connected to all The gate driving signal output terminal GN_OUT is connected; and
  • the second gate driving output transistor M8_2 has a gate connected to the pull-down node QB, a drain connected to the gate driving signal output terminal GN_OUT, and a source connected to the third voltage V3.
  • the carry signal output sub-circuit 16 includes, for example, a first carry signal output transistor M7_1, a gate connected to the pull-up node Q, a drain connected to the third clock signal input terminal CLK3, and a source connected to the carry Signal output terminal CR connection;
  • a second carry signal output transistor M8_1 a gate of which is connected to the pull-down node Q, a drain of which is connected to the carry signal output terminal CR, and a source of which is connected to the third voltage V3;
  • the storage capacitor C1 has a first terminal connected to the pull-up node Q and a second terminal connected to the carry signal output terminal CR.
  • the first voltage V1 is, for example, a first low voltage VGL1
  • the second voltage V2 is, for example, a high voltage VGH
  • the third voltage V3 is, for example, the second low voltage VGL2.
  • the embodiment of the present disclosure uses a three-clock control technology and a two-stage low-voltage design, including a capacitor and 10 transistors, and adopts a two-stage output, which can improve the gate driving signal.
  • CR provides an input signal for the next-stage shift register unit
  • GN_OUT provides a corresponding gate driving signal for the corresponding row gate line.
  • the second end of C1 is only connected to CR.
  • the second end of C1 can also be connected to GN_OUT only, or the second end of C1 can be connected to GN_OUT and CR respectively.
  • all the transistors are N-type transistors, but not limited thereto. In actual operation, the above-mentioned transistors may also be P-type transistors.
  • a display cycle includes a reset phase S1, an input phase S2, an output phase S3, and a reset phase S4, which are sequentially set.
  • the input signal connected to STU is low level
  • CLK1 is input high level
  • CLK2 and CLK3 are both input low level
  • M3 is turned on, so that the potential of QB is VGH
  • M4 and M6 are both turned on.
  • the input signal is high level, CLK2 is high level, CLK1 and CLK3 are both low level, and M1 is both turned on.
  • the input signal is written to the pull-up node Q so that the potential of Q is High level, both M7_1 and M7_2 are turned on, so that CR and GN_OUT both output VGL1; and M2 and M5 are turned on so that the potential of QB is VGL1.
  • VGL1 makes M8_1 and M8_2 completely closed ( Because VGL1 is lower than VGL2, the gate-source voltage of M8_1 is less than the threshold voltage of M8_1, the gate-source voltage of M8_2 is less than the threshold voltage of M8_2, and M8_1 and M8_2 are in the off state), thereby reducing the leakage current flowing through M8_1 and M8_2, Ensure that the GN_OUT output is stable.
  • the input signal is low level
  • CLK3 is input high level
  • CLK1 and CLK2 are both input low level
  • both M7_1 and M7_2 are turned on
  • M8_1 Both M8_2 and M8_2 are turned off so that CR outputs high and GN_OUT outputs high.
  • the input signal is low level
  • CLK1 is input high level
  • CLK2 and CLK3 are both input low level
  • M3 and M4 are both turned on
  • the potential of QB becomes high level
  • M6 is turned on.
  • the potential of Q is reset to VGL1, M7_1 and M7_2 are both off, and M8_1 and M8_2 are both on, so that CR outputs VGL2 and GN_OUT outputs VGL2.
  • the duty ratio of the first clock signal, the duty ratio of the second clock signal, and the duty ratio of the third clock signal are all 1/3, and the period of the first clock signal and the period of the second clock signal
  • the period of the third and third clock signals are both T, CLK2 is delayed by T / 3 from CLK1, and CLK3 is delayed by T / 3 from CLK2.
  • the driving method of the shift register unit according to the embodiment of the present disclosure is applied to the above-mentioned shift register unit.
  • Each display cycle includes an input stage, an output stage, and a reset stage which are sequentially set.
  • the driving method of the shift register unit include:
  • an input terminal is connected to an input signal, and an input sub-circuit writes the input signal to a pull-up node under the control of a second clock signal input terminal, so that the potential of the pull-up node is an effective level.
  • the carry signal output sub-circuit controls that the potential of the pull-up node is still an effective level
  • the pull-down node control sub-circuit writes a first voltage to the pull-down node under the control of the pull-up node, and the gate drive output sub-circuit is under the control of the pull-up node,
  • the third clock signal is output through the gate drive signal output terminal;
  • the carry signal output sub-circuit outputs the third clock signal through the carry signal output terminal under the control of the pull-up node;
  • a pull-up node control sub-circuit writes a first voltage to the pull-up node under the control of a first clock signal input terminal and the pull-down node; a gate drive output sub-circuit is on the pull-up node.
  • the pull-down node control sub-circuit stops writing the first voltage to the pull-down node under the control of the pull-up node, and the pull-down node control sub-circuit is controlled by the first clock signal
  • a second voltage is written into the pull-down node, and the gate drive output sub-circuit outputs a third voltage through the gate drive signal output terminal under the control of the pull-down node, and the carry signal is output
  • the sub-circuit outputs a third voltage through the carry signal output terminal under the control of the pull-down node.
  • the driving method of the shift register unit in the embodiment of the present disclosure uses a carry signal output sub-circuit to provide a carry signal, and an input signal is provided to an adjacent next-stage shift register unit through the carry signal output terminal, so as to avoid the need for a gate drive signal output terminal.
  • the problem of insufficient driving ability is caused by the input signal provided to the adjacent next-stage shift register unit, which improves the output stability of the gate driving signal.
  • the method for driving a shift register unit further includes:
  • the pull-down node control sub-circuit writes a first clock signal to the pull-down node under the control of the pull-up node;
  • the pull-down node control sub-circuit stops writing the first clock signal to the pull-down node under the control of the pull-up node.
  • the display period further includes a reset phase set before the input phase;
  • the driving method of the shift register unit further includes:
  • the pull-down node control sub-circuit In the reset phase, the pull-down node control sub-circuit writes a second voltage to the pull-down node under the control of the first clock signal input terminal, and the pull-up node control sub-circuit is in the first Under the control of a clock signal input terminal and the pull-down node, a first voltage is written into the pull-up node.
  • a reset phase may be provided before the input phase.
  • the potential of the pull-up node is reset to ensure the stability of the gate driving circuit.
  • the gate driving output sub-circuit may include a first gate driving output transistor and a second gate driving output transistor;
  • the carry signal output sub-circuit may include a first carry signal output transistor and a second carry signal output Transistors and storage capacitors.
  • the first voltage inputted by the first voltage input terminal is substantially smaller than the first voltage inputted by the third voltage input terminal.
  • a third voltage so that in the output stage, the second gate drive output transistor and the second carry signal output transistor can be turned off to reduce the noise of the gate drive signal; or,
  • the first voltage inputted by the first voltage input terminal is substantially larger than the first voltage inputted by the third voltage input terminal.
  • the third voltage so that in the output stage, the second gate drive output transistor and the second carry signal output transistor can be in an off state to reduce noise of the gate drive signal.
  • the gate driving circuit according to the embodiment of the present disclosure includes a plurality of cascaded shift register units described above;
  • the carry signal output terminal included in the shift register unit of each stage is connected to the input terminal included in the adjacent next stage shift register unit.
  • FIG. 4 is a schematic diagram of a cascade relationship between the first four stages of shift register units included in the gate driving circuit according to the embodiment of the present disclosure.
  • the GOA1 is a first-stage shift register unit of the gate driving circuit according to the embodiment of the present disclosure
  • the GOA2 is a second-stage shift register unit included in the gate driving circuit
  • the reference numeral GOA3 is a third-stage shift register unit included in the gate driving circuit
  • the reference numeral GOA4 is a fourth-stage shift register unit included in the gate driving circuit.
  • the STV is the start signal
  • the GN_OUT1 is the first stage gate drive signal output
  • the CR1 is the first stage carry signal output
  • the GN_OUT2 is the second stage.
  • Gate drive signal output terminal CR2 is the second stage carry signal output terminal
  • GN_OUT3 is the third stage gate drive signal output terminal
  • CR3 is the third stage carry signal output terminal
  • the code is GN_OUT4 is a fourth-stage gate drive signal output terminal
  • CR4 is a fourth-stage carry signal output terminal.
  • the reference numeral STU is an input terminal
  • the reference numeral CLK1 is a first clock signal input terminal
  • the reference numeral CLK2 is a second clock signal input terminal
  • the reference numeral CLK3 is a third clock signal input terminal.
  • the gate driving signal output terminal is GN_OUT
  • the carry signal output terminal is labeled CR.
  • CR1 is connected to the input terminal included in GOA2
  • CR2 is connected to the input terminal included in GOA3
  • CR3 is connected to the input terminal included in GOA4.
  • CKI1 is the first clock signal line
  • CKI2 is the second clock signal line
  • CKI3 is the third clock signal line
  • the first clock signal input terminal of GOA1 is connected to CKI1
  • the second clock signal input terminal of GOA1 is connected to CKI2 is connected
  • the third clock signal input of GOA1 is connected to CKI3
  • the first clock signal input of GOA2 is connected to CKI2
  • the second clock signal input of GOA2 is connected to CKI3
  • the third clock signal input of GOA2 is connected to CKI1
  • the first clock signal input of GOA3 is connected to CKI3, the second clock signal input of GOA3 is connected to CKI1, and the third clock signal input of GOA3 is connected to CKI2
  • the first clock signal input of GOA4 is connected to CKI1, GOA4
  • the second clock signal input terminal of the connection is connected to CKI2, the third clock signal input terminal of GOA4 is connected to CKI3, and so on.
  • the display device includes the above-mentioned gate driving circuit.
  • the display device may be, for example, an electronic paper, an OLED (Organic Light-Emitting Diode) display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital direction frame, a navigator, or any other device having a display function. Products or parts.
  • OLED Organic Light-Emitting Diode

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Abstract

一种移位寄存器单元包括：输入子电路（11）、上拉节点控制子电路（12）、下拉节点控制子电路（13）、栅极驱动输出子电路（15）和进位信号输出子电路（16）。输入子电路（11）分别与输入端（STU）、第二时钟信号输入端（CLK2）和上拉节点（Q）连接。上拉节点控制子电路（12）分别与上拉节点（Q）、下拉节点（QB）、第一时钟信号输入端（CLK1）和第一电压输入端连接。下拉节点控制子电路（13）分别与下拉节点（QB）、上拉节点（Q）、第一时钟信号输入端（CLK1）、第一电压输入端和第二电压输入端连接。

Description

移位寄存器单元、驱动方法、栅极驱动电路和显示装置
相关申请的交叉引用
本申请主张在2018年5月25日在中国提交的中国专利申请号No.201810516807.9的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示驱动技术领域，尤其涉及一种移位寄存器单元、驱动方法、栅极驱动电路和显示装置。
背景技术
目前显示面板分辨率越来越高，显示器的栅极驱动电路的输出端和源极驱动电路的输出端较多，驱动电路长度的增加会增加绑定(Bonding)。为了解决以上问题，显示面板厂商越来越多采用GOA(Gate On Array，设置于阵列基板上的栅极驱动电路)技术，这样不仅可以省去Gate COF(Chip On Flex,or,Chip On Film覆晶薄膜)Bonding，还可以实现显示面板窄边框设计。然而目前现有GOA电路设计较复杂(采用的时钟信号的个数多，并采用的晶体管的个数多)，噪声明显。并且，现有的栅极驱动电路中的移位寄存器单元直接通过其栅极驱动信号输出端为相邻下一级移位寄存器单元提供输入信号，从而产生栅极驱动信号输出端需要为相邻下一级移位寄存器单元提供输入信号而导致驱动能力不足的问题，进而导致栅极驱动信号输出稳定性低。
发明内容
在第一个方面中，本公开实施例提供了一种移位寄存器单元，包括：输入子电路、上拉节点控制子电路、下拉节点控制子电路、栅极驱动输出子电路和进位信号输出子电路，其中，
所述输入子电路分别与输入端、第二时钟信号输入端和上拉节点连接，用于在输入阶段，在所述第二时钟信号输入端的控制下，将由所述输入端接入的输入信号写入所述上拉节点；
所述上拉节点控制子电路分别与所述上拉节点、下拉节点、第一时钟信号输入端和第一电压输入端连接，用于在复位阶段，在所述第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点；所述第一电压输入端用于输入所述第一电压；
所述下拉节点控制子电路分别与下拉节点、上拉节点、第一时钟信号输入端、第一电压输入端和第二电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，将所述第一电压写入所述下拉节点，并在复位阶段，在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点；所述第二电压输入端用于输入所述第二电压；
所述栅极驱动输出子电路分别与所述上拉节点、所述下拉节点、所述栅极驱动信号输出端、第三时钟信号输入端和第三电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，通过所述栅极驱动信号输出端输出第三时钟信号，并在复位阶段，在所述下拉节点的控制下，通过所述栅极驱动信号输出端输出第三电压；所述第三时钟信号输入端用于输入所述第三时钟信号，所述第三电压输入端用于输入所述第三电压；
所述进位信号输出子电路分别与所述上拉节点、所述下拉节点、所述进位信号输出端、所述第三时钟信号输入端和所述第三电压输入端连接，用于控制所述上拉节点的电位，并在所述输入阶段和所述输出阶段，在所述上拉节点的控制下，通过所述进位信号输出端输出所述第三时钟信号，在所述复位阶段，在所述下拉节点的控制下，通过所述进位信号输出端输出所述第三电压。
根据本公开的一些实施例，所述下拉节点控制子电路还用于在设置于所述输入阶段之前的重置阶段，在所述第一时钟信号输入端的控制下，将所述第二电压写入所述下拉节点。
根据本公开的一些实施例，所述下拉节点控制子电路包括：第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一电压输入端连接；以及，
第二下拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述第二电压输入端连接，第二极与所述下拉节点连接。
根据本公开的一些实施例，所述下拉节点控制子电路还用于在所述输入阶段和所述输出阶段，在所述上拉节点的控制下，将第一时钟信号写入所述下拉节点；
所述第一时钟信号输入端用于输入所述第一时钟信号。
根据本公开的一些实施例，所述下拉节点控制子电路还包括：第三下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一时钟信号输入端连接。
根据本公开的一些实施例，所述上拉节点控制子电路还用于在所述重置阶段，在所述第一时钟信号输入端和所述下拉节点的控制下，将所述第一电压写入所述上拉节点。
根据本公开的一些实施例，所述上拉节点控制子电路包括：第一上拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接；以及，
第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点控制晶体管的第二极连接，第二极与所述第一电压输入端连接。
根据本公开的一些实施例，所述栅极驱动输出子电路包括：第一栅极驱动输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电压输入端连接；
所述进位信号输出子电路包括：第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述进位信号输出端连接；
第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极与所述第三电压输入端连接，以及，
存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端连接。
根据本公开的一些实施例，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管，所述第一电压输入端输入的第一电压实 质上小于所述第三电压输入端输入的第三电压；或者，
所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型晶体管，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压。
根据本公开的一些实施例，所述输入子电路包括：输入晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述输入端连接。
根据本公开的一些实施例，所述第一电压为第一低电压VGL1，所述第二电压为高电压VGH，所述第三电压为第二低电压VGL2。
根据本公开的一些实施例，所述存储电容的第二端仅与所述进位信号输出端连接；或者，
所述存储电容的第二端仅与所述栅极驱动信号输出端连接；或者，
所述存储电容的第二端分别与所述栅极驱动信号输出端和所述进位信号输出端连接。
在第二个方面中，本公开实施例还提供了一种移位寄存器单元的驱动方法，应用于如第一个方面中所述的移位寄存器单元，其中，每一显示周期包括依次设置的输入阶段、输出阶段和复位阶段，所述移位寄存器单元的驱动方法包括：
在所述输入阶段，输入端接入输入信号，输入子电路在第二时钟信号输入端的控制下，将所述输入信号写入上拉节点，以使得所述上拉节点的电位为有效电平；
在所述输出阶段，进位信号输出子电路控制所述上拉节点的电位仍为有效电平；
在所述输入阶段和所述输出阶段，下拉节点控制子电路在所述上拉节点的控制下将第一电压写入下拉节点，栅极驱动输出子电路在所述上拉节点的控制下，通过栅极驱动信号输出端输出第三时钟信号；进位信号输出子电路在所述上拉节点的控制下，通过进位信号输出端输出第三时钟信号；
在所述复位阶段，上拉节点控制子电路在第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点；栅极驱动输出子电路在所 述上拉节点的控制下，停止通过所述栅极驱动信号输出端输出所述第三时钟信号，所述进位信号输出子电路在所述上拉节点的控制下，停止通过所述进位信号输出端输出第三时钟信号；所述下拉节点控制子电路在所述上拉节点的控制下，停止写入所述第一电压至所述下拉节点，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，栅极驱动输出子电路在所述下拉节点的控制下，通过所述栅极驱动信号输出端输出第三电压，所述进位信号输出子电路在所述下拉节点的控制下，通过所述进位信号输出端输出第三电压。
根据本公开的一些实施例，所述移位寄存器单元的驱动方法还包括：
在所述输入阶段和所述输出阶段，所述下拉节点控制子电路在所述上拉节点的控制下，将第一时钟信号写入所述下拉节点；
在所述复位阶段，所述下拉节点控制子电路在所述上拉节点的控制下，停止将所述第一时钟信号写入所述下拉节点。
根据本公开的一些实施例，所述显示周期还包括设置于所述输入阶段之前的重置阶段；所述移位寄存器单元的驱动方法还包括：
在所述重置阶段，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，所述上拉节点控制子电路在所述第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点。
根据本公开的一些实施例，所述栅极驱动输出子电路包括第一栅极驱动输出晶体管和第二栅极驱动输出晶体管；所述进位信号输出子电路包括第一进位信号输出晶体管、第二进位信号输出晶体管和存储电容；
所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管，所述第一电压输入端输入的第一电压实质上小于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管能够处于截止状态；或者，
所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型晶体管，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管 和所述第二进位信号输出晶体管能够处于截止状态。
在第三个方面中，本公开实施例还提供了一种栅极驱动电路，其中，包括多个级联的如第一个方面中所述的移位寄存器单元；
除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元包括的进位信号输出端与相邻下一级移位寄存器单元包括的输入端连接。
在第四个方面中，本公开实施例还提供了一种显示装置，包括如第一个方面中所述的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对本公开实施例的描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本公开实施例所述的移位寄存器单元的结构图；
图2是本公开实施例所述的移位寄存器单元的一具体实施例的电路图；
图3是本公开实施例所述的移位寄存器单元的该具体实施例的工作时序图；以及
图4是本公开实施例所述的栅极驱动电路包括的前四级移位寄存器单元之间的级联关系示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开所有实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。在本公开实施例中，为区分晶体管除栅极之外的两极，将其中一极称为第一极，另一极称为第二极。在实际操作时，所述第一极可以为漏极，所述第二极可以为源极；或者，所述第一极可以为源极，所述第 二极可以为漏极。
如图1所示，本公开实施例所述的移位寄存器单元，例如包括输入端STU、栅极驱动信号输出端GN_OUT、进位信号输出端CR、第一时钟信号输入端CLK1、第二时钟信号输入端CLK2、第三时钟信号输入端CLK3、输入子电路11、上拉节点控制子电路12、下拉节点控制子电路13、栅极驱动输出子电路15和进位信号输出子电路16。
所述输入子电路11分别与所述输入端STU、第二时钟信号输入端CLK2和上拉节点Q连接，用于在输入阶段，在所述第二时钟信号输入端CLK2的控制下，将由所述输入端STU接入的输入信号写入所述上拉节点PU。
所述上拉节点控制子电路12分别与所述上拉节点Q、下拉节点QB、第一时钟信号输入端CLK1和第一电压输入端连接，用于在复位阶段，在所述第一时钟信号输入端CLK1和所述下拉节点QB的控制下，将第一电压V1写入所述上拉节点Q；所述第一电压输入端用于输入所述第一电压V1。
所述下拉节点控制子电路13分别与下拉节点QB、上拉节点Q、第一时钟信号输入端CLK1、第一电压输入端和第二电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点Q的控制下，将所述第一电压V1写入所述下拉节点QB，并在复位阶段，在所述第一时钟信号输入端CLK1的控制下，将第二电压V2写入所述下拉节点QB；所述第二电压输入端用于输入所述第二电压V2。
所述栅极驱动输出子电路15分别与所述上拉节点Q、所述下拉节点QB、所述栅极驱动信号输出端GN_OUT、第三时钟信号输入端CLK3和第三电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点Q的控制下，通过所述栅极驱动信号输出端GN_OUT输出第三时钟信号，并在复位阶段，在所述下拉节点QB的控制下，通过所述栅极驱动信号输出端GN_OUT输出第三电压V3；所述第三时钟信号输入端CLK3用于输入所述第三时钟信号，所述第三电压输入端用于输入所述第三电压V3。
所述进位信号输出子电路16分别与所述上拉节点Q、所述下拉节点QB、所述进位信号输出端CR、所述第三时钟信号输入端CLK3和所述第三电压输入端连接，用于控制所述上拉节点Q的电位，并在所述输入阶段和所述输出 阶段，在所述上拉节点Q的控制下，通过所述进位信号输出端CR输出所述第三时钟信号，在所述复位阶段，在所述下拉节点QB的控制下，通过所述进位信号输出端CR输出所述第三电压V3。
本公开实施例所述的移位寄存器单元采用的晶体管的个数和时钟信号线的个数少，结构简单，使得时序控制简洁方便，并且能够实现窄边框。并且，本公开实施例所述的移位寄存器单元采用进位信号输出子电路提供进位信号，通过进位信号输出端为相邻下一级移位寄存器单元提供输入信号，以避免栅极驱动信号输出端需要为相邻下一级移位寄存器单元提供输入信号而导致驱动能力不足的问题，提升栅极驱动信号输出稳定性。
本公开实施例如图1所示的移位寄存器单元的实施例在工作时，每一显示周期例如包括依次设置的重置阶段、输入阶段、输出阶段和复位阶段。
在所述重置阶段，所述下拉节点控制子电路13在所述第一时钟信号输入端CLK1的控制下，将第二电压V2写入所述下拉节点QB，所述上拉节点控制子电路12在所述第一时钟信号输入端CLK1和所述下拉节点QB的控制下，将第一电压V1写入所述上拉节点Q。
在所述输入阶段，输入端STU接入输入信号，输入子电路11在第二时钟信号输入端CLK2的控制下，将所述输入信号写入上拉节点Q，以使得所述上拉节点Q的电位为有效电平(所述有效电平即为能够使得栅极驱动输出子电路15包括的栅极与所述上拉节点连接的第一栅极驱动晶体管(图1中未示出)导通的电平)，下拉节点控制子电路13在所述上拉节点Q的控制下将第一电压V1写入下拉节点QB，栅极驱动输出子电路15在所述上拉节点Q的控制下，通过栅极驱动信号输出端GN_OUT输出第三时钟信号；进位信号输出子电路16在所述上拉节点Q的控制下，通过进位信号输出端CR输出第三时钟信号。
在所述输出阶段，进位信号输出子电路16控制所述上拉节点Q的电位仍为有效电平，下拉节点控制子电路13在所述上拉节点QB的控制下将第一电压V1写入下拉节点，栅极驱动输出子电路15在所述上拉节点Q的控制下，通过栅极驱动信号输出端GN_OUT输出第三时钟信号；进位信号输出子电路16在所述上拉节点Q的控制下，通过进位信号输出端CR输出第三时钟信号。
在所述复位阶段，上拉节点控制子电路12在第一时钟信号输入端CLK1和所述下拉节点QB的控制下，将第一电压V1写入所述上拉节点Q；栅极驱动输出子电路15在所述上拉节点Q的控制下，停止通过所述栅极驱动信号输出端GN_OUT输出所述第三时钟信号，所述进位信号输出子电路16在所述上拉节点Q的控制下，停止通过所述进位信号输出端CR输出第三时钟信号；所述下拉节点控制子电路13在所述上拉节点Q的控制下，停止写入所述第一电压V1至所述下拉节点QB，所述下拉节点控制子电路13在所述第一时钟信号输入端CLK1的控制下，将第二电压V2写入所述下拉节点QB，栅极驱动输出子电路15在所述下拉节点QB的控制下，通过所述栅极驱动信号输出端GN_OUT输出第三电压V3，所述进位信号输出子电路16在所述下拉节点QB的控制下，通过所述进位信号输出端CR输出第三电压V3。
在具体实施时，V1可以例如为第一低电平，V2可以例如为高电平，V3可以例如为第二低电平，但不以此为限。
在具体实施时，在输入阶段之前还设有重置阶段，所述下拉节点控制子电路还用于在所述重置阶段，在所述第一时钟信号输入端的控制下，将所述第二电压写入所述下拉节点，以对所述下拉节点的电位进行重置，便于在重置阶段上拉节点控制子电路在第一时钟信号输入端和下拉节点的控制下，将第一电压写入所述上拉节点(上拉节点控制子电路在重置阶段的功能将在下面介绍)，以便清除上一显示周期残留于上拉节点的电荷，提升栅极驱动信号输出的稳定性。
具体的，所述下拉节点控制子电路可以例如包括：第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一电压输入端连接；以及，
第二下拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述第二电压输入端连接，第二极与所述下拉节点连接。
在一种可选的情况下，所述下拉节点控制子电路还用于在所述输入阶段和所述输出阶段，在所述上拉节点的控制下，将第一时钟信号写入所述下拉节点；
所述第一时钟信号输入端用于输入所述第一时钟信号。
在一种可选的情况下，下拉节点控制子电路还在输入阶段和所述输出阶段将第一时钟信号写入下拉节点，以能够更好的在输入阶段和输出阶段控制下拉节点的电位为第一电平，并且即使上拉节点的电位在复位阶段不能及时降低，也能够控制下拉节点的电位为第二电平。
在本公开实施例中，所述第一电平可以例如为低电平，所述第二电平可以例如为高电平，但不以此为限。当所述下拉节点的电位为第一电平时，栅极驱动输出子电路包括的栅极与下拉节点连接的第二栅极驱动输出晶体管关断(OFF)，当所述下拉节点的电位为第二电平时，所述第二栅极驱动信号输出端开启(ON)。
可选的，所述下拉节点控制子电路还可以例如包括：第三下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一时钟信号输入端连接。
在一种可选的情况下，所述上拉节点控制子电路还用于在所述重置阶段，在所述第一时钟信号输入端和所述下拉节点的控制下，将所述第一电压写入所述上拉节点，以便清除上一显示周期残留于上拉节点的电荷，避免残留于上拉节点的电荷对当前显示周期的栅极驱动信号输出的影响，保证在输入阶段开始时上拉节点的电位为第一电压，提升栅极驱动信号输出的稳定性。当所述上拉节点的电位为所述第一电压时，所述栅极驱动输出子电路包括的栅极与上拉节点连接的第一栅极驱动输出晶体管关断(OFF)。
在具体实施时，所述第一电压可以例如为第一低电压，但不以此为限。
具体的，所述上拉节点控制子电路可以包括：第一上拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接；以及，
第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点控制晶体管的第二极连接，第二极与所述第一电压输入端连接。
具体的，所述栅极驱动输出子电路可以例如包括：第一栅极驱动输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
第二栅极驱动输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电压输入端连接。
所述进位信号输出子电路可以例如包括：第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述进位信号输出端连接；
第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极与所述第三电压输入端连接；以及，
存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端连接。
在一种可选的情况下，当所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管时，所述第一电压输入端输入的第一电压实质上小于所述第三电压输入端输入的第三电压，以使得在输出阶段，所述第二栅极驱动晶体管和第二进位信号输出晶体管能够截止，减小漏电流，以降低栅极驱动信号的噪声；或者，
当所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型晶体管时，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压，以使得在输出阶段，所述第二栅极驱动晶体管和第二进位信号输出晶体管能够截止，减小漏电流，以降低栅极驱动信号的噪声。
具体的，所述输入子电路可以例如包括：输入晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述输入端连接。
下面通过一具体实施例来说明本公开实施例所述的移位寄存器单元。
如图2所示，本公开实施例所述的移位寄存器单元的一具体实施例，例如包括输入端STU、栅极驱动信号输出端GN_OUT、进位信号输出端CR、输入子电路11、上拉节点控制子电路12、下拉节点控制子电路13、栅极驱动输出子电路15和进位信号输出子电路16。
所述输入子电路11例如包括：输入晶体管M1，栅极与所述第二时钟信号输入端CLK2连接，漏极与上拉节点Q连接，源极与所述输入端STU连接。
所述上拉节点控制子电路12例如包括：第一上拉节点控制晶体管M4，栅极与所述第一时钟信号输入端CLK1连接，漏极与所述上拉节点Q连接；以及，
第二上拉节点控制晶体管M6，栅极与所述下拉节点QB连接，漏极与所述第一上拉节点控制晶体管M4的源极连接，源极接入所述第一电压V1。
所述下拉节点控制子电路13例如包括：第一下拉节点控制晶体管M5，栅极与所述上拉节点Q连接，漏极与下拉节点QB连接，源极接入第一电压V1；以及，
第二下拉节点控制晶体管M3，栅极与所述第一时钟信号输入端CLK1连接，漏极接入第二电压V2，源极与所述下拉节点QB连接；以及，
第三下拉节点控制晶体管M2，栅极与所述上拉节点PU连接，漏极与所述下拉节点QB连接，源极与所述第一时钟信号输入端CLK1连接。
所述栅极驱动输出子电路15例如包括：第一栅极驱动输出晶体管M7_2，栅极与所述上拉节点Q连接，漏极与所述第三时钟信号输入端CLK3连接，源极与所述栅极驱动信号输出端GN_OUT连接；以及，
第二栅极驱动输出晶体管M8_2，栅极与所述下拉节点QB连接，漏极与所述栅极驱动信号输出端GN_OUT连接，源极接入第三电压V3。
所述进位信号输出子电路16例如包括：第一进位信号输出晶体管M7_1，栅极与所述上拉节点Q连接，漏极与所述第三时钟信号输入端CLK3连接，源极与所述进位信号输出端CR连接；
第二进位信号输出晶体管M8_1，栅极与所述下拉节点Q连接，漏极与所述进位信号输出端CR连接，源极接入所述第三电压V3；以及，
存储电容C1，第一端与所述上拉节点Q连接，第二端与所述进位信号输出端CR连接。
在本公开如图2所示的移位寄存器单元的具体实施例中，所述第一电压V1例如为第一低电压VGL1，所述第二电压V2例如为高电压VGH，所述第三电压V3例如为第二低电压VGL2。
本公开实施例如图2所示的移位寄存器单元的具体实施例采用三时钟控制技术以及两阶低电压设计，包括1个电容和10个晶体管，并采用双级输出，能够提高栅极驱动信号输出的稳定性，CR为相邻下一级移位寄存器单元提供输入信号，GN_OUT为相应行栅线提供相应的栅极驱动信号。由此可见，本公开实施例所述的移位寄存器单元的该具体实施例整体结构简单，可以很好 降低所输出的栅极驱动信号的噪声。
在图2所示的移位寄存器单元的具体实施例中，C1的第二端仅与CR连接。但是在实际操作时，C1的第二端也可以改为仅与GN_OUT连接，或者，C1的第二端可以分别与GN_OUT和CR连接。
在图2所示的移位寄存器单元的具体实施例中，所有的晶体管都为N型晶体管，但不以此为限，在实际操作时，如上晶体管也可以为P型晶体管。
本公开如图2所示的移位寄存器单元的具体实施例在工作时，如图3所示，一显示周期包括依次设置的重置阶段S1、输入阶段S2、输出阶段S3和复位阶段S4。
在所述重置阶段S1，STU接入的输入信号为低电平，CLK1输入高电平，CLK2和CLK3都输入低电平，M3打开，以使得QB的电位为VGH，M4和M6都打开，以将Q点的电位重置为VGL1，保证在输入阶段开始之前，这个栅极驱动电路的各级移位寄存器单元中的上拉节点的电位一致，均为低电压，保证栅极驱动电路的稳定性。
在所述输入阶段S2，所述输入信号为高电平，CLK2输入高电平，CLK1和CLK3都输入低电平，M1都打开，输入信号写入上拉节点Q，以使得Q的电位为高电平，M7_1和M7_2都打开，以使得CR和GN_OUT都输出VGL1；并M2和M5都打开，以使得QB的电位为VGL1，将VGL1设置为例如小于VGL2，则使得M8_1和M8_2彻底关闭(由于VGL1低于VGL2，所以M8_1的栅源电压小于M8_1的阈值电压，M8_2的栅源电压小于M8_2的阈值电压，M8_1和M8_2处于截止状态)，从而可以减小流过M8_1和M8_2的漏电流，保证GN_OUT输出稳定。
在所述输出阶段S3，所述输入信号为低电平，CLK3输入高电平，CLK1和CLK2都输入低电平，C1自举拉升上拉节点Q的电位，M7_1和M7_2都开启，M8_1和M8_2都关断，以使得CR输出高电平，GN_OUT输出高电平。
在所述复位阶段S4，所述输入信号为低电平，CLK1输入高电平，CLK2和CLK3都输入低电平，M3和M4都打开，QB的电位变为高电平，M6打开，以将Q的电位复位为VGL1，M7_1和M7_2都关断，M8_1和M8_2都开启，以使得CR输出VGL2，GN_OUT输出VGL2。
由图3可知，第一时钟信号的占空比、第二时钟信号的占空比和第三时钟信号的占空比都为1/3，第一时钟信号的周期、第二时钟信号的周期和第三时钟信号的周期都为T，CLK2比CLK1推迟T/3，CLK3比CLK2推迟T/3。
本公开实施例所述的移位寄存器单元的驱动方法，应用于上述的移位寄存器单元，每一显示周期包括依次设置的输入阶段、输出阶段和复位阶段，所述移位寄存器单元的驱动方法包括：
在所述输入阶段，输入端接入输入信号，输入子电路在第二时钟信号输入端的控制下，将所述输入信号写入上拉节点，以使得所述上拉节点的电位为有效电平；
在所述输出阶段，进位信号输出子电路控制所述上拉节点的电位仍为有效电平；
在所述输入阶段和所述输出阶段，下拉节点控制子电路在所述上拉节点的控制下将第一电压写入下拉节点，栅极驱动输出子电路在所述上拉节点的控制下，通过栅极驱动信号输出端输出第三时钟信号；进位信号输出子电路在所述上拉节点的控制下，通过进位信号输出端输出第三时钟信号；
在所述复位阶段，上拉节点控制子电路在第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点；栅极驱动输出子电路在所述上拉节点的控制下，停止通过所述栅极驱动信号输出端输出所述第三时钟信号，所述进位信号输出子电路在所述上拉节点的控制下，停止通过所述进位信号输出端输出第三时钟信号；所述下拉节点控制子电路在所述上拉节点的控制下，停止写入所述第一电压至所述下拉节点，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，栅极驱动输出子电路在所述下拉节点的控制下，通过所述栅极驱动信号输出端输出第三电压，所述进位信号输出子电路在所述下拉节点的控制下，通过所述进位信号输出端输出第三电压。
本公开实施例的移位寄存器单元的驱动方法采用进位信号输出子电路提供进位信号，通过进位信号输出端为相邻下一级移位寄存器单元提供输入信号，以避免栅极驱动信号输出端需要为相邻下一级移位寄存器单元提供输入信号而导致驱动能力不足的问题，提升栅极驱动信号输出稳定性。
具体的，本公开实施例所述的移位寄存器单元的驱动方法还包括：
在所述输入阶段和所述输出阶段，所述下拉节点控制子电路在所述上拉节点的控制下，将第一时钟信号写入所述下拉节点；
在所述复位阶段，所述下拉节点控制子电路在所述上拉节点的控制下，停止将所述第一时钟信号写入所述下拉节点。
可选的，所述显示周期还包括设置于所述输入阶段之前的重置阶段；所述移位寄存器单元的驱动方法还包括：
在所述重置阶段，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，所述上拉节点控制子电路在所述第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点。
在具体实施时，在输入阶段之前还可以设置有重置阶段，在重置阶段，将上拉节点的电位进行重置，保证栅极驱动电路稳定性。
具体的，所述栅极驱动输出子电路可以包括第一栅极驱动输出晶体管和第二栅极驱动输出晶体管；所述进位信号输出子电路可以包括第一进位信号输出晶体管、第二进位信号输出晶体管和存储电容。
当所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管时，所述第一电压输入端输入的第一电压实质上小于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管能够处于截止状态，以降低栅极驱动信号的噪声；或者，
当所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型晶体管时，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管能够处于截止状态，以降低栅极驱动信号的噪声。
本公开实施例所述的栅极驱动电路，包括多个级联的上述的移位寄存器单元；
除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元包括的 进位信号输出端与相邻下一级移位寄存器单元包括的输入端连接。
图4是本公开实施例所述的栅极驱动电路包括的前四级移位寄存器单元之间的级联关系示意图。
在图4中，标号为GOA1的为本公开实施例所述的栅极驱动电路的第一级移位寄存器单元，标号为GOA2的为所述栅极驱动电路包括的第二级移位寄存器单元，标号为GOA3的为所述栅极驱动电路包括的第三级移位寄存器单元，标号为GOA4的为所述栅极驱动电路包括的第四级移位寄存器单元。
在图4中，标号为STV的为起始信号，标号为GN_OUT1的为第一级栅极驱动信号输出端，标号为CR1的为第一级进位信号输出端，标号为GN_OUT2的为第二级栅极驱动信号输出端，标号为CR2的为第二级进位信号输出端，标号为GN_OUT3的为第三级栅极驱动信号输出端，标号为CR3的为第三级进位信号输出端，标号为GN_OUT4的为第四级栅极驱动信号输出端，标号为CR4的为第四级进位信号输出端。
在图4中，标号为STU的为输入端，标号为CLK1的为第一时钟信号输入端，标号为CLK2的为第二时钟信号输入端，标号为CLK3的为第三时钟信号输入端，标号为GN_OUT的为栅极驱动信号输出端，标号为CR的为进位信号输出端。
如图4所示，CR1与GOA2包括的输入端连接，CR2与GOA3包括的输入端连接，CR3与GOA4包括的输入端连接。
在图4中，CKI1为第一时钟信号线，CKI2为第二时钟信号线，CKI3为第三时钟信号线；GOA1的第一时钟信号输入端与CKI1连接，GOA1的第二时钟信号输入端与CKI2连接，GOA1的第三时钟信号输入端与CKI3连接；GOA2的第一时钟信号输入端与CKI2连接，GOA2的第二时钟信号输入端与CKI3连接，GOA2的第三时钟信号输入端与CKI1连接；GOA3的第一时钟信号输入端与CKI3连接，GOA3的第二时钟信号输入端与CKI1连接，GOA3的第三时钟信号输入端与CKI2连接；GOA4的第一时钟信号输入端与CKI1连接，GOA4的第二时钟信号输入端与CKI2连接，GOA4的第三时钟信号输入端与CKI3连接，依次类推。
经过对本公开实施例所述的栅极驱动电路进行仿真可以得到GN_OUT 几乎全摆幅输出，实现了输出轨到轨。
本公开实施例所述的显示装置，包括上述的栅极驱动电路。
所述显示装置例如可以为：电子纸、OLED(Organic Light-Emitting Diode，有机发光二极管)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑、数码向框、导航仪等任何具有显示功能的产品或部件。
应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (15)

  1. 一种移位寄存器单元，包括：输入子电路、上拉节点控制子电路、下拉节点控制子电路、栅极驱动输出子电路和进位信号输出子电路，其中，
    所述输入子电路分别与输入端、第二时钟信号输入端和上拉节点连接，用于在输入阶段，在所述第二时钟信号输入端的控制下，将由所述输入端接入的输入信号写入所述上拉节点；
    所述上拉节点控制子电路分别与所述上拉节点、下拉节点、第一时钟信号输入端和第一电压输入端连接，用于在复位阶段，在所述第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点；所述第一电压输入端用于输入所述第一电压；
    所述下拉节点控制子电路分别与下拉节点、上拉节点、第一时钟信号输入端、第一电压输入端和第二电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，将所述第一电压写入所述下拉节点，并在复位阶段，在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点；所述第二电压输入端用于输入所述第二电压；
    所述栅极驱动输出子电路分别与所述上拉节点、所述下拉节点、所述栅极驱动信号输出端、第三时钟信号输入端和第三电压输入端连接，用于在输入阶段和输出阶段，在所述上拉节点的控制下，通过所述栅极驱动信号输出端输出第三时钟信号，并在复位阶段，在所述下拉节点的控制下，通过所述栅极驱动信号输出端输出第三电压；所述第三时钟信号输入端用于输入所述第三时钟信号，所述第三电压输入端用于输入所述第三电压；
    所述进位信号输出子电路分别与所述上拉节点、所述下拉节点、所述进位信号输出端、所述第三时钟信号输入端和所述第三电压输入端连接，用于控制所述上拉节点的电位，并在所述输入阶段和所述输出阶段，在所述上拉节点的控制下，通过所述进位信号输出端输出所述第三时钟信号，在所述复位阶段，在所述下拉节点的控制下，通过所述进位信号输出端输出所述第三电压。
  2. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制子电 路包括：第一下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一电压输入端连接；以及，
    第二下拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述第二电压输入端连接，第二极与所述下拉节点连接。
  3. 如权利要求1所述的移位寄存器单元，其中，所述下拉节点控制子电路还包括：第三下拉节点控制晶体管，栅极与所述上拉节点连接，第一极与所述下拉节点连接，第二极与所述第一时钟信号输入端连接。
  4. 如权利要求1至3中任一项所述的移位寄存器单元，其中，所述上拉节点控制子电路包括：第一上拉节点控制晶体管，栅极与所述第一时钟信号输入端连接，第一极与所述上拉节点连接；以及，
    第二上拉节点控制晶体管，栅极与所述下拉节点连接，第一极与所述第一上拉节点控制晶体管的第二极连接，第二极与所述第一电压输入端连接。
  5. 如权利要求1至4中任一项权利要求所述的移位寄存器单元，其中，所述栅极驱动输出子电路包括：第一栅极驱动输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述栅极驱动信号输出端连接；以及，
    第二栅极驱动输出晶体管，栅极与所述下拉节点连接，第一极与所述栅极驱动信号输出端连接，第二极与所述第三电压输入端连接；
    所述进位信号输出子电路包括：第一进位信号输出晶体管，栅极与所述上拉节点连接，第一极与所述第三时钟信号输入端连接，第二极与所述进位信号输出端连接；
    第二进位信号输出晶体管，栅极与所述下拉节点连接，第一极与所述进位信号输出端连接，第二极与所述第三电压输入端连接，以及，
    存储电容，第一端与所述上拉节点连接，第二端与所述进位信号输出端连接。
  6. 如权利要求5所述的移位寄存器单元，其中，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管，所述第一电压输入端输入的第一电压实质上小于所述第三电压输入端输入的第三电压；或者，
    所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型 晶体管，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压。
  7. 如权利要求1至6中任一项权利要求所述的移位寄存器单元，其中，所述输入子电路包括：输入晶体管，栅极与所述第二时钟信号输入端连接，第一极与所述上拉节点连接，第二极与所述输入端连接。
  8. 如权利要求1至7中任一项权利要求所述的移位寄存器单元，其中，所述第一电压为第一低电压VGL1，所述第二电压为高电压VGH，所述第三电压为第二低电压VGL2。
  9. 如权利要求5所述的移位寄存器单元，其中，所述存储电容的第二端仅与所述进位信号输出端连接；或者，
    所述存储电容的第二端仅与所述栅极驱动信号输出端连接；或者，
    所述存储电容的第二端分别与所述栅极驱动信号输出端和所述进位信号输出端连接。
  10. 一种移位寄存器单元的驱动方法，应用于如权利要求1至9中任一项权利要求所述的移位寄存器单元，其中，每一显示周期包括依次设置的输入阶段、输出阶段和复位阶段，所述移位寄存器单元的驱动方法包括：
    在所述输入阶段，输入端接入输入信号，输入子电路在第二时钟信号输入端的控制下，将所述输入信号写入上拉节点，以使得所述上拉节点的电位为有效电平；
    在所述输出阶段，进位信号输出子电路控制所述上拉节点的电位仍为有效电平；
    在所述输入阶段和所述输出阶段，下拉节点控制子电路在所述上拉节点的控制下将第一电压写入下拉节点，栅极驱动输出子电路在所述上拉节点的控制下，通过栅极驱动信号输出端输出第三时钟信号；进位信号输出子电路在所述上拉节点的控制下，通过进位信号输出端输出第三时钟信号；
    在所述复位阶段，上拉节点控制子电路在第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点；栅极驱动输出子电路在所述上拉节点的控制下，停止通过所述栅极驱动信号输出端输出所述第三时钟信号，所述进位信号输出子电路在所述上拉节点的控制下，停止通过所述进 位信号输出端输出第三时钟信号；所述下拉节点控制子电路在所述上拉节点的控制下，停止写入所述第一电压至所述下拉节点，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，栅极驱动输出子电路在所述下拉节点的控制下，通过所述栅极驱动信号输出端输出第三电压，所述进位信号输出子电路在所述下拉节点的控制下，通过所述进位信号输出端输出第三电压。
  11. 如权利要求10所述的移位寄存器单元的驱动方法，还包括：
    在所述输入阶段和所述输出阶段，所述下拉节点控制子电路在所述上拉节点的控制下，将第一时钟信号写入所述下拉节点；
    在所述复位阶段，所述下拉节点控制子电路在所述上拉节点的控制下，停止将所述第一时钟信号写入所述下拉节点。
  12. 如权利要求10所述的移位寄存器单元的驱动方法，其中，所述显示周期还包括设置于所述输入阶段之前的重置阶段；所述移位寄存器单元的驱动方法还包括：
    在所述重置阶段，所述下拉节点控制子电路在所述第一时钟信号输入端的控制下，将第二电压写入所述下拉节点，所述上拉节点控制子电路在所述第一时钟信号输入端和所述下拉节点的控制下，将第一电压写入所述上拉节点。
  13. 如权利要求10至12中任一项权利要求所述的移位寄存器单元的驱动方法，其中，所述栅极驱动输出子电路包括第一栅极驱动输出晶体管和第二栅极驱动输出晶体管；所述进位信号输出子电路包括第一进位信号输出晶体管、第二进位信号输出晶体管和存储电容；
    所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为N型晶体管，所述第一电压输入端输入的第一电压实质上小于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管能够处于截止状态；或者，
    所述第二栅极驱动输出晶体管和所述第二进位信号输出晶体管都为P型晶体管，所述第一电压输入端输入的第一电压实质上大于所述第三电压输入端输入的第三电压，以使得在所述输出阶段，所述第二栅极驱动输出晶体管 和所述第二进位信号输出晶体管能够处于截止状态。
  14. 一种栅极驱动电路，其中，包括多个级联的如权利要求1至9中任一项权利要求所述的移位寄存器单元；
    除了最后一级移位寄存器单元之外，每一级所述移位寄存器单元包括的进位信号输出端与相邻下一级移位寄存器单元包括的输入端连接。
  15. 一种显示装置，包括如权利要求14所述的栅极驱动电路。
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