WO2019208241A1 - Method of forming electrode and device for forming electrode for organic thin film transistor, method of manufacturing organic thin film transistor, and organic thin film transistor - Google Patents

Method of forming electrode and device for forming electrode for organic thin film transistor, method of manufacturing organic thin film transistor, and organic thin film transistor Download PDF

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Publication number
WO2019208241A1
WO2019208241A1 PCT/JP2019/015802 JP2019015802W WO2019208241A1 WO 2019208241 A1 WO2019208241 A1 WO 2019208241A1 JP 2019015802 W JP2019015802 W JP 2019015802W WO 2019208241 A1 WO2019208241 A1 WO 2019208241A1
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Prior art keywords
electrode
base layer
thin film
film transistor
organic thin
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PCT/JP2019/015802
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French (fr)
Japanese (ja)
Inventor
武史 陶山
弥生 芝藤
知玄 木村
毅 関谷
隆文 植村
Original Assignee
株式会社Ｓｃｒｅｅｎホールディングス
国立大学法人大阪大学
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Priority to JP2020516215A priority Critical patent/JP7116962B2/en
Publication of WO2019208241A1 publication Critical patent/WO2019208241A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having a potential-jump barrier or a surface barrier
    • H10K10/40—Organic transistors
    • H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]

Definitions

  • the present invention relates to an electrode manufacturing technique suitable for manufacturing an organic thin film transistor.
  • a technique for forming a thin film semiconductor element such as a thin film transistor on the surface of a substrate such as a glass substrate or a resin substrate has been studied for the purpose of manufacturing a display device or a touch panel device.
  • organic semiconductors have attracted attention as a material for thin film semiconductor elements from the viewpoint that performance and production technology are remarkably improved, and depending on the material, devices can be created using printing technology.
  • Patent Document 1 describes a technique of forming a thin film transistor using an organic semiconductor material on the surface of a substrate such as a glass substrate, a semiconductor substrate, or a resin substrate.
  • a substrate such as a glass substrate, a semiconductor substrate, or a resin substrate.
  • Manufacturing methods are used. That is, in this technique, the electrode material is laminated on the insulating polymer layer in a state where the insulating polymer layer is softened, and after the polymer layer and the electrode layer are flattened by pressurization, the polymer layer is cured. As a result, the electrode is embedded in the polymer layer, and an electrode having no step with the substrate is realized.
  • Patent Document 1 describes that as a method for realizing a softened polymer layer, a polymer precursor before cross-linking, a polymer before curing treatment, softening by heating, or the like can be used.
  • methods for forming electrodes include methods of patterning with conductive ink using printing techniques such as inkjet printing and screen printing.
  • the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of forming an electrode without a step with respect to the surroundings by a simpler manufacturing process.
  • One aspect of the present invention is an electrode forming method for an organic thin film transistor in which an electrode is formed on the surface of a base layer formed of an electrically insulating resin material.
  • the base layer is A step of preparing, a step of applying a coating liquid containing a solvent for softening the resin material constituting the base layer and an electrode material to the surface of the base layer in a pattern corresponding to an electrode shape; A step of pressing a coating solution against the base layer; and a step of volatilizing the solvent and solidifying the coating solution to form the electrode.
  • the coating liquid applied to the base layer contains a solvent that softens the resin material that forms the base layer. For this reason, it is not necessary to soften the base layer in advance. That is, the base layer may have a certain hardness when the coating liquid is applied. Therefore, various coating methods can be applied for coating the coating liquid containing the electrode material. And a coating liquid osmose
  • electrode forming method for organic thin film transistors is simply referred to as “electrode forming method”
  • electrode forming device for organic thin film transistors is simply referred to as “electrode forming device”.
  • the process of applying the coating liquid itself becomes a process of softening the base layer by using the solvent having the property of softening the base layer as the solvent of the coating liquid. ing.
  • an electrode embedded in the base layer that is, having no step at the boundary with the base layer is realized by a relatively simple manufacturing process in which a coating liquid is applied to a base layer having a certain hardness and pressed. It is possible.
  • the softening of the base layer is limited only to the portion where the coating liquid is applied and touched with the solvent, that is, the portion where the electrode is to be formed. For this reason, the other part of the base layer is not affected by the disturbance of the surface shape or the electrical insulation, and the shape of the formed electrode is also prevented from being deformed.
  • the organic semiconductor layer is formed so as to cover the base layer and the electrode without any step, the disorder of the crystallinity of the organic semiconductor due to the step is suppressed. be able to. Therefore, it is possible to manufacture an organic thin film transistor with good performance while suppressing a decrease in electrical characteristics of the semiconductor due to such disorder of crystallinity.
  • Another aspect of the present invention is an electrode forming apparatus for an organic thin film transistor, which forms an electrode on the surface of a base layer formed of an electrically insulating resin material, in order to achieve the above object,
  • a flat plate shape carrying a pattern in which a coating liquid containing a substrate holding portion for holding a substrate having the base layer, a solvent for softening the resin material constituting the base layer, and an electrode material is patterned according to the electrode shape.
  • a carrier holding portion that holds a pattern carrying surface in close proximity to the surface to be coated of the base layer, a surface of the carrier opposite to the pattern carrying surface, or the substrate to be coated.
  • a roller-shaped pressing member that moves along the substrate while pressing a surface opposite to the coating surface.
  • the coating liquid can be applied to the base layer by bringing the carrier patterned with the coating liquid containing the solvent that softens the base layer into close contact with the base layer. Then, the electrode embedded in the base layer can be formed by allowing the coating liquid to permeate the base layer softened by the pressure applied by the roller-shaped pressing member. That is, the electrode forming apparatus having the above configuration is suitable for executing the electrode forming method according to the present invention.
  • a base layer made of an electrically insulating resin material, a coating liquid containing a solvent that softens the resin material constituting the base layer, and an electrode material.
  • a source electrode and a drain electrode embedded in the base layer in a state where they are separated from each other and at least a part of the surface is exposed by being partially applied to the layer and pressed against the base layer and then solidified ,
  • An organic semiconductor layer continuously covering the exposed surface of each of the source electrode and the drain electrode and the surface of the base layer between the source electrode and the drain electrode, an insulating layer covering the organic semiconductor layer,
  • An organic thin film comprising a gate electrode in contact with an insulating layer, facing the organic semiconductor layer through the insulating layer, and electrically insulated from the organic semiconductor layer It is a transistor.
  • the organic thin film transistor to which the present invention is applied becomes a transistor with good electrical performance.
  • a solvent having a property of softening the base layer is used as a solvent for the coating solution.
  • FIG. 1 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device including an electrode forming method according to the present invention.
  • 2A to 2D and FIGS. 3A to 3E are diagrams showing the structure of each step of the semiconductor element manufactured by this manufacturing method.
  • This manufacturing method can be used for forming semiconductor elements on various flat substrates such as a semiconductor substrate, a glass substrate, and a resin substrate.
  • the process in the case of forming the organic thin-film transistor as an example of a semiconductor element on the surface of the glass sheet or polyimide sheet as the substrate S will be described in detail.
  • the following method and apparatus can be used for forming various semiconductor elements.
  • a structure in which various functional layers are laminated on the substrate S is referred to as a “workpiece” that is a processing target in each process, and is denoted by a reference symbol Wk.
  • the structure of such a structure changes sequentially with the progress of the manufacturing process, and both of them are referred to as workpieces Wk.
  • workpieces Wk are referred to as workpieces Wk.
  • the substrate to be processed is cleaned with an appropriate cleaning agent (step S101), and the substrate surface is cleaned.
  • a resin layer that becomes the base layer B is formed on one surface Sa of the substrate S (step S102).
  • the base layer B can be formed, for example, by uniformly applying a solution containing a resin (for example, various polymer resins) that exhibits electrical insulation in a cured state to the substrate surface Sa by, for example, spin coating. it can.
  • the present invention is not limited to this, and the base layer B can be formed by using any formation method capable of forming a uniform layer.
  • a baking process is performed after the application in order to dry and cure the formed coating film (step S103).
  • the coating film is cured, and the base layer B that is in close contact with the substrate surface Sa is formed.
  • a new layer can be formed on the surface of the cured base layer B.
  • the base layer B has a function of covering the surface of the substrate S with a uniform and stable insulating layer and stably maintaining the shape of each layer formed in a subsequent process.
  • the base layer B functions as a primer layer, it is possible to improve the adhesion of the electrode to the substrate S, and to effectively prevent the electrode from collapsing or peeling off in the wet treatment described later.
  • the polymer resin material constituting the base layer B for example, polyurethane, polyimide, polyamideimide, polyvinyl alcohol, polyvinylphenol, polyester, polyethylene, or the like can be used.
  • the baking treatment for curing the polymer can be performed under conditions of, for example, 120 ° C. and about 30 minutes.
  • the baking process can be performed by holding the workpiece Wk for a predetermined time in a heating furnace such as an oven adjusted to a predetermined baking temperature.
  • a resin material that is not highly heat resistant can be used as the substrate.
  • work Wk may be left still in a heating furnace, and the aspect heated while conveying in a heating furnace may be sufficient.
  • a source electrode and a drain electrode constituting the organic semiconductor thin film transistor are formed on the surface of the base layer B thus formed (step S104).
  • Various methods can be employed for forming these electrodes.
  • a method using a printing technique in which an electrode is formed by transferring a previously formed electrode pattern to the base layer B will be described.
  • an electrode pattern PT formed of a conductive material including a conductive material such as metal particles (for example, silver) and a solvent is preliminarily formed on the surface of a blanket BL formed of a glass plate, a resin plate, or the like. It is formed.
  • two electrode patterns PT spaced from each other are carried on the pattern carrying surface (the lower surface in the drawing) of the blanket BL. These two electrode patterns PT finally function as a source electrode and a drain electrode, respectively.
  • the blanket BL is disposed in close proximity to the workpiece Wk with the pattern carrying surface facing the surface of the base layer B. From this state, as shown in FIG. 2C, the roller member RL is brought into contact with the surface of the blanket BL opposite to the pattern carrying surface. The roller member RL rolls along the surface of the blanket BL while pushing the blanket BL toward the workpiece WK. As a result, the electrode pattern PT carried on the blanket BL is pressed against the base layer B and finally transferred onto the surface of the base layer B.
  • the pressing force against the blanket BL by the roller member RL can be set to 0.05 N / mm 2 to 0.3 N / mm 2 , for example.
  • the blanket BL after transfer at the time of transfer is carried out from the vicinity of the workpiece Wk.
  • the workpiece Wk after the transfer is baked (step S105).
  • the firing conditions at this time may be, for example, 120 ° C. and 30 minutes, but it is not essential to have the same conditions as the firing process in step S103.
  • the workpiece Wk at this point is in a state in which the source electrode Es and the drain electrode Ed formed by curing the transferred electrode pattern are embedded in the base layer B. Yes. The principle of such embedding will be described later.
  • a SAM process for forming a self-assembled monolayer (SAM) on the electrode surface is performed (step S106). Since the principle and method of SAM processing are known, an example of a method for forming a SAM film by wet processing will be briefly described here.
  • the workpiece Wk is immersed for at least 2 minutes in a solution in which pentafluorobenzenethiol (PFBT) having a concentration of about 0.01 M is dissolved in isopropyl alcohol (IPA). Thereafter, a SAM film made of PFBT can be formed by rinsing with IPA and drying.
  • PFBT pentafluorobenzenethiol
  • IPA isopropyl alcohol
  • the electrical contact between the organic semiconductor layer and the electrode to be subsequently stacked can be made low resistance and stable.
  • the monomolecular film M made of PFBT is formed on the surface of the work Wk where the electrodes Es and Ed are exposed.
  • an organic semiconductor layer is laminated so as to cover the surface of the workpiece Wk on which the electrodes Es and Ed are thus formed (step S107).
  • the organic semiconductor layer can be formed by using, for example, a known vacuum deposition method. As shown in FIG. 3B, the workpiece Wk at this point is in a state where the monomolecular film M covering the electrodes Es and Ed and the exposed surface of the base layer B are continuously covered with the organic semiconductor layer Sc. ing.
  • a gate insulating layer covering the surface of the organic semiconductor film Sc is formed (step S108).
  • the gate insulating layer is formed, for example, by depositing a material having electrical insulating properties on the surface of the organic semiconductor film Sc by using a known chemical vapor deposition (CVD) method. can do.
  • CVD chemical vapor deposition
  • the workpiece Wk at this time is in a state where the entire surface of the organic semiconductor layer Sc is covered with the continuous gate insulating layer Ig as shown in FIG. 3C.
  • a gate electrode is formed on the surface of the gate insulating layer Ig (step S109).
  • the gate electrode can be formed by a technique similar to the formation of the source electrode Es and the drain electrode Ed. That is, as shown in FIG. 3D, the blanket BL carrying the electrode pattern PT to be a gate electrode is disposed close to the work Wk, and the electrode pattern PT is gated by pressing the blanket BL by the roller member RL (FIG. 2C). Transfer to the surface of the insulating layer Ig. By baking this (step S110), as shown in FIG. 3E, the gate electrode Eg is formed on the surface of the gate insulating layer Ig.
  • the processing conditions in the transfer process and the baking process in this case can also be made equal to the processing conditions at the time of forming the source electrode Es and the drain electrode Ed.
  • the pressing force of the roller member RL during the transfer process can be 0.05 N / mm 2 to 0.3 N / mm 2
  • the baking temperature can be 120 ° C.
  • the baking time can be 30 minutes.
  • the substrate S, the base layer B, the source and drain electrodes Es and Ed, the organic semiconductor layer Sc, the monomolecular film M, the gate insulating layer Ig, and the gate electrode Eg are stacked in this order.
  • the source and drain electrodes Es and Ed, the organic semiconductor layer Sc, the gate insulating layer Ig, and the gate electrode Eg function as an organic thin film transistor Tr.
  • the substrate S and the base layer B function as a base material that supports the organic thin film transistor Tr.
  • a large number of organic thin film transistors Tr having the above-described structure are simultaneously formed in a state where they are arranged on one substrate S.
  • the thickness of each layer is shown, but is not limited to these values.
  • the thickness of the base layer B is, for example, 100 nm.
  • the thickness of the source and drain electrodes Es, Ed is, for example, 70 nm.
  • the thickness of the organic semiconductor layer Sc is 30 nm.
  • the distance between the source electrode Es and the drain electrode Ed, that is, the channel length is, for example, 50 ⁇ m.
  • the thicknesses of the gate insulating layer Ig and the gate electrode Eg are, for example, 100 nm and 200 nm, respectively.
  • the thickness of each layer is set so that the thickness of the base layer B is larger than the thickness of the electrode pattern PT on the blanket BL. May be set.
  • One condition for obtaining good electrical characteristics in the organic thin film transistor Tr is that the crystallinity of the organic semiconductor layer Sc is good. That is, when the organic semiconductor layer Sc is polycrystalline with many crystal grain boundaries, the performance of the organic thin film transistor Tr is limited due to the low carrier mobility in the organic semiconductor layer Sc. In order to obtain high carrier mobility, the organic semiconductor layer Sc is required to have good crystallinity close to a single crystal.
  • the organic semiconductor layer Sc having good crystallinity on the work Wk on which the source and drain electrodes Es and Ed are formed, between the source and drain electrodes Es and Ed on the surface of the work Wk and the surrounding base layer B Therefore, it is desirable that the surface has a smooth surface with few steps.
  • the structure in which the source and drain electrodes Es and Ed are embedded in the base layer B can meet such a requirement.
  • a configuration for realizing such a buried structure in the present embodiment will be described.
  • FIGS. 4A to 4C are schematic diagrams for explaining electrode embedding in the transfer processing step.
  • the source and drain electrodes Es and Ed are formed on the base layer B by transferring the pattern PT formed of the conductive ink containing the electrode material and the solvent to the base layer B.
  • the solvent contained in the conductive ink those having a property of softening the cured polymer resin constituting the base layer B are used. Specifically, a solvent having the property of swelling or dissolving the polymer resin is used.
  • the solvent is an organic solvent that softens the solvent, in particular, a high boiling point solvent used for conductive ink for reverse printing, specifically, for example, butyl carbitol, hexyl carbitol.
  • a high boiling point solvent used for conductive ink for reverse printing specifically, for example, butyl carbitol, hexyl carbitol.
  • Ethyl carbitol acetate, butyl carbitol acetate, 2-ethyl-1,3-hexanediol, 2,4-diethyl-1,5-pentanediol, 1,3-butylene glycol, and octanediol can be used.
  • the process itself of transferring the electrode pattern PT to the base layer B is a process of embedding the electrode pattern PT in the base layer B. For this reason, it is not necessary to embed the electrode pattern PT by pretreatment of the base layer B before transfer, post-processing after transfer, or the like.
  • FIG. 5A, FIG. 5B, FIG. 6A and FIG. 6B are diagrams illustrating the structure of a prototype organic thin film transistor. More specifically, FIG. 5A is a microscope (TEM) photograph showing an example of a cross-sectional structure of the organic thin film transistor manufactured by the above manufacturing method, and FIG. 5B is a diagram schematically showing the shape of the drain electrode. . FIG. 6A is a photomicrograph showing another example of the cross-sectional structure of the organic thin film transistor manufactured by the above manufacturing method, and FIG. 6B is a diagram schematically showing the shape of the drain electrode. The shape of the source electrode is basically the same.
  • the drain electrode Ed has a shape in which the end portion is embedded in the base layer B while the thickness of the drain electrode Ed is kept substantially constant.
  • the drain electrode Ed is embedded in the base layer B in such a manner that the thickness gradually decreases at the end thereof.
  • the drain electrode Ed has a surface shape that gently rises from the surface of the base layer B.
  • the interface with the organic semiconductor layer Sc is a smooth curved surface with no steps. For this reason, it is possible to improve the performance of the organic thin-film transistor Tr by suppressing the disorder of the crystallinity of the organic semiconductor layer Sc caused by a significant step.
  • the gate insulating layer Ig is preferably formed of a material that does not change with respect to the solvent.
  • FIG. 7A and FIG. 7B are diagrams showing examples of electrical characteristics of a prototype organic thin film transistor. More specifically, FIG. 7A is a graph showing an example of actual measurement of electrical characteristics in a prototype organic thin film transistor and a comparative example. FIG. 7B is a diagram schematically showing a cross-sectional structure of a transistor of a comparative example. Note that, in order to facilitate the comparison of the structures, in FIG. 7B, the same reference numerals are given to the configurations having the same functions as the configurations of the transistors Tr illustrated in FIG. 3E.
  • the organic thin film transistor Tr manufactured by the manufacturing method of this embodiment is a so-called top gate type transistor in which the source and drain electrodes Es and Ed are arranged between the layers and the gate electrode Eg appears on the element surface as shown in FIG. 3E. is there.
  • the transistor shown in FIG. 7B as a comparative example is a so-called bottom gate type transistor in which the gate electrode Eg is disposed between the layers and the source and drain electrodes Es and Ed appear on the element surface.
  • a semiconductor layer Sc, and source and drain electrodes Es and Ed (film thickness of 50 nm, channel length of 50 ⁇ m) formed by vacuum deposition of gold are sequentially stacked.
  • a portion of a semiconductor layer that connects a source electrode and a drain electrode functions as a channel through which a current flows.
  • the carrier mobility of the organic semiconductor in the channel portion that electrically connects the source electrode and the drain electrode due to disorder of the crystallinity of the organic semiconductor layer around the source and drain electrodes Is small. For this reason, there exists a tendency for an electrical characteristic to be inferior compared with the bottom gate type transistor which can make an organic-semiconductor layer into a flat layer.
  • the top gate transistor manufactured according to this embodiment has substantially the same electrical characteristics as the bottom gate transistor of the comparative example. More specifically, the carrier mobility (field effect mobility) in the saturation region between the transistor manufactured according to this embodiment and the transistor of the comparative example under the measurement condition where the drain voltage is ( ⁇ 5) V. And the maximum drain current was compared. The result is -This embodiment: Field effect mobility 0.283 [cm 2 / V ⁇ s], Maximum drain current 8.26 ⁇ 10 ⁇ 7 [A] ⁇ Comparative example: Field effect mobility 0.297 [cm 2 / V ⁇ s], Maximum drain current 7.30 ⁇ 10 ⁇ 7 [A] Met. From this, it can be seen that the organic semiconductor thin film transistor Tr manufactured by the manufacturing method of this embodiment has substantially the same electrical characteristics as the bottom gate transistor of the comparative example. Therefore, it can be said that the organic semiconductor layer Sc has good crystallinity.
  • the electrodes (source electrode Es, drain electrode Ed, and gate electrode Eg) are formed by transferring the conductive ink patterned on the surface of the blanket BL to the workpiece Wk.
  • Such an electrode forming process can be subdivided into a patterning process for forming the electrode pattern PT with conductive ink on the blanket BL and a transfer process for transferring the formed electrode pattern PT to the work Wk.
  • the patterning step and the transfer step can be performed using the same processing apparatus.
  • the processing described here can be executed by, for example, the transfer device described in Japanese Patent Application Laid-Open No. 2016-203518 previously disclosed by the applicant of the present application.
  • FIGS. 8A to 8D are diagrams showing a process of electrode formation processing.
  • 9A and 9B are schematic views showing a patterning process and a transfer process.
  • the XY plane represents a horizontal plane.
  • the Z direction represents the vertical direction, and more specifically, the (+ Z) direction represents the vertical upward direction.
  • an upper stage 11 having a vacuum suction surface on the lower surface and a lower stage 12 having a frame shape with a large opening at the center are arranged in close proximity to each other in a horizontal posture. Yes.
  • the opening size of the opening 121 of the lower stage 12 is larger than the planar size of the upper stage 11.
  • a plurality of lifting hands 13 supported by a lifting mechanism (not shown) so as to be lifted and lowered individually are arranged.
  • a columnar or cylindrical pressing roller 14 extending in the Y direction is disposed near the ( ⁇ X) side (left side in the drawing) end of the opening 121.
  • the pressing roller 14 is supported by the support member 15 so as to be rotatable around the central axis in the Y direction.
  • the support member 15 can be moved up and down in the Z direction and traveled in the X direction by a drive mechanism (not shown).
  • the pressing roller 14 has a function corresponding to the roller member RL shown in FIG. 2C.
  • a plate PP having a convex pattern obtained by inverting a desired electrode pattern is carried into the transfer apparatus 1 and set on the upper stage 11.
  • the upper stage 11 sucks and holds the plate PP with the pattern forming surface on which the convex pattern is formed facing downward.
  • the blanket BL on which the conductive ink Ik is uniformly applied in advance is carried into the transfer device 1 and set on the lower stage 12.
  • the lower stage 12 sucks and holds the peripheral edge portion of the blanket BL with the surface coated with the conductive ink Ik facing upward and facing the plate PP.
  • each lifting hand 13 is positioned at such a height that the upper surface thereof is the same as the upper surface of the lower stage 12, so that the center portion of the opened blanket BL is maintained in a horizontal posture.
  • the pressing roller 14 is positioned below the ( ⁇ X) side end of the plate PP in the horizontal direction and at a position where the upper end is separated from the lower surface of the blanket BL in the vertical direction.
  • the supporting member 15 raises the pressing roller 14 so that the pressing roller 14 comes into contact with the lower surface of the blanket BL.
  • the pressing roller 14 continues to rise after contacting the lower surface of the blanket BL, the blanket BL is pushed up by the pressing roller 14, and finally the upper surface of the blanket BL touches the lower surface of the plate PP. Touch.
  • the ink Ik carried on the upper surface of the blanket BL adheres to the plate PP.
  • the pressing roller 14 pushes up the blanket BL, the ink Ik is pressed against the plate PP with a predetermined pressing force.
  • the support member 15 moves the pressing roller 14 in the (+ X) direction, so that the pressing roller 14 contacts the lower surface of the blanket BL and travels in the (+ X) direction while being driven to rotate.
  • a region where the blanket BL and the plate PP are in close contact with each other via the ink Ik expands in the X direction.
  • each of the plurality of elevating hands 13 is sequentially lowered as the support member 15 moves in order to avoid interference with the traveling pressing roller 14.
  • FIG. 8D when the pressing roller 14 reaches the end position immediately below the (+ X) side end of the plate PP, the entire plate PP is in contact with the blanket BL.
  • the plate PP and the blanket BL are peeled in this state, a portion corresponding to the convex pattern of the ink Ik uniformly applied to the blanket BL shifts to the plate PP, and other portions remain on the blanket BL. .
  • the ink Ik is patterned by the convex pattern, and the inverted pattern of the convex pattern is transferred to the blanket BL as the electrode pattern PT.
  • FIG. 9A schematically shows a process in which the ink Ik applied to the blanket BL is patterned by the plate PP to form the electrode pattern PT.
  • the transfer step of transferring the electrode pattern PT formed on the blanket BL to the workpiece Wk in this way can be explained by replacing the plate PP in the above processing with the workpiece Wk and the ink Ik with the electrode pattern PT. That is, the blanket BL carrying the electrode pattern PT is held by the lower stage 12, and the work Wk to which the pattern is transferred is held by the upper stage 11 (FIG. 8A).
  • the pressing roller 14 travels in the X direction while pressing the blanket BL against the workpiece Wk with a predetermined pressing force (FIGS. 8B to 8D)
  • the blanket BL and the workpiece Wk come into close contact via the electrode pattern PT.
  • the electrode pattern PT on the blanket BL is transferred to the work Wk.
  • FIG. 9B is a diagram schematically showing a process (step S104 in FIG. 1) in which the electrode pattern PT is transferred to the workpiece Wk in which the base layer B is formed on the substrate S.
  • the base layer B is already hardened by a prior baking process. For this reason, the base layer B is not plastically deformed by the pressing force from the pressing roller 14.
  • the electrode pattern PT is in an undried state and contains a lot of solvent components. Therefore, the base layer B in contact with the electrode pattern PT is softened by dissolving or swelling, and the electrode pattern PT is strongly pressed against the base layer B and embedded in the base layer B.
  • a parallel plate printing technique is applied in which the electrode pattern PT is transferred from the blanket BL to the workpiece Wk by bringing the blanket BL having a flat plate shape into contact with the workpiece Wk and then peeling off.
  • the method of forming the electrode pattern PT on the workpiece Wk is not limited to this, and various methods can be applied as exemplified below.
  • FIG. 10 is a diagram showing another aspect of the electrode forming process.
  • a blanket 22 is wound around the surface of a cylindrical blanket cylinder 21.
  • the electrode pattern PT is patterned on the intaglio 23.
  • the intaglio 23 moves while contacting the blanket 22 while rotating the blanket cylinder 21 at a predetermined speed, whereby the electrode pattern PT patterned by the intaglio 23 is transferred to the blanket 22.
  • the stage 24 moves while bringing the workpiece Wk placed on the stage 24 into contact with the blanket BL, whereby the electrode pattern PT on the blanket BL is transferred to the workpiece Wk.
  • the solvent component contained in the electrode pattern PT dissolves or swells the base layer B of the workpiece Wk, so that the electrode pattern PT is embedded in the base layer B.
  • This method corresponds to the offset intaglio printing technique.
  • An electrode can be formed on the workpiece Wk also by such a method.
  • pattern formation on a flat plate or a cylindrical blanket may be performed by other methods.
  • the electrode pattern may be formed by partially landing the conductive ink on the blanket surface using a printing technique such as a screen printing method or an ink jet method.
  • a printing technique such as a screen printing method or an ink jet method.
  • ink is directly applied to the surface of the workpiece Wk by these printing techniques.
  • this does not meet the purpose of embedding the electrode pattern PT in the base layer B by applying pressure while bringing the ink into contact with the workpiece Wk.
  • the above embodiment is particularly effective in that pattern transfer and pressing can be performed simultaneously.
  • the base layer B made of an insulating resin material is formed on the substrate S. Then, an ink containing an electrode material and a solvent is partially applied to the surface of the base layer B according to a predetermined pattern.
  • the solvent has a property of softening the resin material constituting the base layer.
  • the electrode pattern PT formed on the surface of the base layer B When the electrode pattern PT formed on the surface of the base layer B is pressed in an unsolidified state, it penetrates into the base layer B softened by the solvent. For this reason, the electrode formed by solidifying the electrode pattern PT is in a state of being embedded in the base layer B. As a result, in the semiconductor element thus formed, the surface of the electrode laminated on the base layer B and the exposed surface of the base layer constitute a smooth curved surface. This avoids the occurrence of a significant step at the boundary between both surfaces.
  • the organic semiconductor layer formed so as to cover these also has a smooth surface. Therefore, it is possible to suppress a decrease in electrical characteristics of the organic semiconductor layer due to the disorder of crystallinity caused by the step. That is, according to the manufacturing method of the present embodiment, it is possible to stably manufacture an organic thin film transistor having good electrical characteristics.
  • roller member is pressed when forming the electrode by transferring the electrode pattern PT, it is possible to simultaneously realize pattern transfer and electrode embedding. For this reason, the process process for eliminating the level
  • the conductive ink Ik corresponds to the “coating liquid” of the present invention.
  • the blanket BL and the roller member RL function as the “carrier” and “roller” of the present invention, respectively.
  • the transfer device 1 shown in FIG. 8A and the transfer device 2 shown in FIG. 10 function as the “electrode forming device” of the present invention.
  • the upper stage 11 functions as a “substrate holding part” of the present invention
  • the lower stage 12 functions as a “supporting body holding part” of the present invention.
  • the pressing roller 14 functions as a “pressing member” of the present invention.
  • the stage 24 functions as the “substrate holding portion” of the present invention
  • the blanket 22 functions as the “supporting body” of the present invention.
  • the blanket cylinder 21 also functions as the “supporting body holding portion” and the “pressing member” of the present invention.
  • the present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention.
  • the above-described embodiment relates to a method for manufacturing a semiconductor element (specifically, an organic thin film transistor) including the electrode forming method of the present invention.
  • the electrode forming method of the present invention can be applied to processes other than the semiconductor element manufacturing process.
  • the present invention can be applied to the manufacture of various semiconductor elements that are not limited to the organic thin film transistors as described above.
  • the semiconductor element manufactured by the above method is a top gate / bottom contact type organic thin film transistor, but the present invention may be applied to, for example, the manufacture of a bottom gate / top contact type organic thin film transistor.
  • the electrode pattern PT is transferred to the upper surface of the workpiece Wk and is pressed by the roller member RL from above.
  • the electrode pattern PT is transferred to the lower surface of the workpiece Wk, and receives the pressing roller by the pressing roller 14 from below.
  • the pressing direction with respect to the workpiece Wk is arbitrary. Since the base layer B that receives the transfer of the electrode pattern PT is cured in advance and has no fluidity, there is no particular difference depending on the pressing direction.
  • the electrode pattern PT is transferred to the workpiece Wk having the base layer B formed on the surface of the substrate S.
  • the substrate S itself has electrical insulating properties and is softened by the solvent of the conductive ink, there is no need to form a base layer again. That is, in this case, the substrate S itself has a function as the “base layer” of the present invention.
  • the solvent may be an organic solvent that swells or dissolves the resin material, as described above by exemplifying specific embodiments.
  • the electrode embedded in the base layer can be formed by allowing the coating liquid to penetrate into the base layer swollen or dissolved by the solvent.
  • the base layer may be formed by applying a resin material or a liquid containing the raw material to the substrate and solidifying it.
  • a resin material or a liquid containing the raw material By applying the coating solution to the already solidified base layer in this manner, unlike the application to the unsolidified base layer, stable coating is possible. Then, by softening the solidified base layer with a solvent, it is possible to effectively realize embedding of the electrode in the base layer.
  • the resin material may be polyurethane and the solvent may be 2,4-diethyl-1,5-pentanediol. It is clear from experiments by the inventors of the present application that the above-described electrode embedding can be realized by such a combination of a resin material and a solvent.
  • the pattern of the coating liquid patterned according to the electrode shape is supported on a carrier, and the carrier is pressed against the base layer, whereby pressing is performed while the coating liquid is transferred to the base layer.
  • the process itself for transferring the coating liquid to the base layer also serves as a process for pressing the coating liquid, it is not necessary to provide these as separate processes, and the time and cost required for manufacturing are reduced. Can be achieved.
  • the pattern carrying surface of the carrier is flat, and the pattern carrying surface is brought close to or in close contact with the surface to be coated of the base layer, and the surface of the carrier opposite to the pattern carrying surface or the base layer
  • the surface opposite to the surface to be coated may be pressed with a roller. According to such a configuration, it is possible to infiltrate the inside of the softened base layer while performing transfer by pressing the pattern carried on the carrier against the base layer.
  • the thickness of the base layer may be larger than the thickness of the electrode. If the base layer is too thin with respect to the thickness of the electrode, the amount of the electrode embedded in the base layer is limited, and as a result, a step between the base layer surface and the electrode surface may not be eliminated. If at least the thickness of the base layer is larger than the thickness of the electrode, this problem can be avoided and the electrode can be reliably embedded.
  • a step of performing a wet treatment for modifying the surface of the electrode after the electrode is formed may be provided.
  • the electrode is directly provided on the substrate, there is a possibility that the electrode already formed in such a wet treatment process may be peeled off from the substrate.
  • Providing the base layer in advance can effectively prevent peeling of the electrode in response to such a problem.
  • a self-assembled monolayer may be provided between the exposed surface of each of the source electrode and the drain electrode and the organic semiconductor layer. According to such a configuration, the electrical contact between the electrode and the organic semiconductor layer can be made low resistance and stable.
  • the present invention can be applied to all electrode forming techniques for forming electrodes on a substrate, but an organic thin film transistor in which disorder of crystallinity caused by a step between the substrate and the electrode causes deterioration of electrical characteristics. It is particularly effective in the production of

Abstract

The purpose of the present invention is to provide a technique with which an electrode that has no level difference with the surrounding area can be formed by a simpler manufacturing process. A method of forming an electrode for an organic thin film transistor and a method of manufacturing an organic thin film transistor according to the present invention include: a step (step S102) of preparing a base layer formed from an electrically insulating resin material; a step (step S104) of partially applying an application liquid that contains a solvent which softens the resin material composing the base layer and a conductive electrode material on a surface of the base layer in a pattern according to the shape of an electrode; a step (step S104) of pressing the unsolidified application liquid against the base layer; and a step (step S105) of solidifying the application liquid by volatilizing the solvent and forming the electrode.

Description

有機薄膜トランジスタ用の電極形成方法および電極形成装置、有機薄膜トランジスタの製造方法ならびに有機薄膜トランジスタElectrode forming method and electrode forming apparatus for organic thin film transistor, method for producing organic thin film transistor, and organic thin film transistor
　この発明は、有機薄膜トランジスタの製造に好適な電極の製造技術に関するものである。 The present invention relates to an electrode manufacturing technique suitable for manufacturing an organic thin film transistor.
　例えば表示装置やタッチパネル装置等を製造する目的で、ガラス基板や樹脂基板等の基板の表面に薄膜トランジスタなどの薄膜半導体素子を形成する技術が研究されている。特に近年では、性能や生産技術の向上が著しく、また材料によっては印刷技術を利用したデバイス作成が可能であるとの観点から、薄膜半導体素子の材料として有機半導体が注目されている。 For example, a technique for forming a thin film semiconductor element such as a thin film transistor on the surface of a substrate such as a glass substrate or a resin substrate has been studied for the purpose of manufacturing a display device or a touch panel device. In particular, in recent years, organic semiconductors have attracted attention as a material for thin film semiconductor elements from the viewpoint that performance and production technology are remarkably improved, and depending on the material, devices can be created using printing technology.
　例えば特許文献１には、ガラス基板、半導体基板、樹脂基板等の基板の表面に有機半導体材料を用いた薄膜トランジスタを形成する技術が記載されている。この技術においては、基板に形成された電極を覆うように有機半導体層を形成する場合に、電極端部における基板との段差が電気抵抗の増大を招くという問題を解決するため、次のような製造方法が用いられている。すなわち、この技術では、絶縁性ポリマー層が軟化した状態で電極材料が絶縁性ポリマー層に積層され、加圧によってポリマー層と電極層とが平坦化された後、ポリマー層が硬化される。これにより、電極はポリマー層に埋め込まれた状態となって基板との段差のない電極が実現される。 For example, Patent Document 1 describes a technique of forming a thin film transistor using an organic semiconductor material on the surface of a substrate such as a glass substrate, a semiconductor substrate, or a resin substrate. In this technique, when an organic semiconductor layer is formed so as to cover an electrode formed on a substrate, in order to solve the problem that a step difference from the substrate at the end portion of the electrode causes an increase in electrical resistance, Manufacturing methods are used. That is, in this technique, the electrode material is laminated on the insulating polymer layer in a state where the insulating polymer layer is softened, and after the polymer layer and the electrode layer are flattened by pressurization, the polymer layer is cured. As a result, the electrode is embedded in the polymer layer, and an electrode having no step with the substrate is realized.
　特許文献１には、軟化したポリマー層を実現する方法として、架橋前のポリマー前駆体、硬化処理前のポリマー、または加熱による軟化等を使用可能であることが記載されている。また電極を形成する方法としては、フォトリソグラフ法、リフトオフ法、エッチング、レーザーアブレーションの他、インクジェット印刷やスクリーン印刷等の印刷技術を用いて導電性インクによるパターニングを行う方法等が列記されている。 Patent Document 1 describes that as a method for realizing a softened polymer layer, a polymer precursor before cross-linking, a polymer before curing treatment, softening by heating, or the like can be used. In addition to the photolithographic method, lift-off method, etching, and laser ablation, methods for forming electrodes include methods of patterning with conductive ink using printing techniques such as inkjet printing and screen printing.
特開２００８－１４７３４６号公報JP 2008-147346 A
　上記従来技術では、ポリマー層（樹脂層）が軟化した状態で電極形成を行う必要がある。しかしながら、工程間での搬送、電極材料の積層、加圧による平坦化等の処理が、ポリマー層（樹脂層）が軟化した状態を維持したまま行われることが必要となる。このことから、実際に適用可能な製造プロセスは限定されると考えられ、また軟化したポリマー層を有する基板の取り扱いにも特別な注意が必要となる。このため、上記従来技術は、実用性および製造コストの点で改良の余地が残されている。 In the above prior art, it is necessary to perform electrode formation with the polymer layer (resin layer) softened. However, it is necessary to carry out processes such as conveyance between processes, lamination of electrode materials, and flattening by pressurization while maintaining the softened state of the polymer layer (resin layer). For this reason, it is considered that the manufacturing processes that can be actually applied are limited, and special care is required for handling a substrate having a softened polymer layer. For this reason, the above prior art still has room for improvement in terms of practicality and manufacturing cost.
　この発明は上記課題に鑑みなされたものであり、周囲との段差のない電極を、より簡単な製造プロセスで形成することのできる技術を提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of forming an electrode without a step with respect to the surroundings by a simpler manufacturing process.
　この発明の一の態様は、電気絶縁性の樹脂材料により形成されたベース層の表面に電極を形成する、有機薄膜トランジスタ用の電極形成方法であって、上記目的を達成するため、前記ベース層を準備する工程と、前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液を、前記ベース層の表面に電極形状に応じたパターンで塗布する工程と、未固化の前記塗布液を前記ベース層に対し押圧する工程と、前記溶剤を揮発させ前記塗布液を固化させて、前記電極を形成する工程とを備えている。 One aspect of the present invention is an electrode forming method for an organic thin film transistor in which an electrode is formed on the surface of a base layer formed of an electrically insulating resin material. In order to achieve the above object, the base layer is A step of preparing, a step of applying a coating liquid containing a solvent for softening the resin material constituting the base layer and an electrode material to the surface of the base layer in a pattern corresponding to an electrode shape; A step of pressing a coating solution against the base layer; and a step of volatilizing the solvent and solidifying the coating solution to form the electrode.
　このように構成された発明では、ベース層に塗布される塗布液が、ベース層を構成する樹脂材料を軟化させる溶剤を含んでいる。このため、事前にベース層を軟化させておく必要はない。つまり、塗布液が塗布される時点でベース層は一定の硬度を有するものであってよい。したがって、電極材料を含む塗布液の塗布については種々の塗布方法を適用することが可能である。そして、溶剤により軟化したベース層に対し、未固化の塗布液を押圧することにより塗布液がベース層の内部に浸透する。この状態で塗布液が固化することにより、ベース層との間の段差が解消された電極を形成することができる。なお、以下では、本発明に係る「有機薄膜トランジスタ用の電極形成方法」を単に「電極形成方法」と、また「有機薄膜トランジスタ用の電極形成装置」を単に「電極形成装置」と、それぞれ略称することがある。 In the invention thus configured, the coating liquid applied to the base layer contains a solvent that softens the resin material that forms the base layer. For this reason, it is not necessary to soften the base layer in advance. That is, the base layer may have a certain hardness when the coating liquid is applied. Therefore, various coating methods can be applied for coating the coating liquid containing the electrode material. And a coating liquid osmose | permeates the inside of a base layer by pressing an unsolidified coating liquid with respect to the base layer softened with the solvent. By solidifying the coating solution in this state, it is possible to form an electrode in which the level difference with the base layer is eliminated. In the following, the “electrode forming method for organic thin film transistors” according to the present invention is simply referred to as “electrode forming method”, and the “electrode forming device for organic thin film transistors” is simply referred to as “electrode forming device”. There is.
　このように、本発明の電極形成方法によれば、塗布液の溶剤としてベース層を軟化させる性質を有するものを使用したことで、塗布液を塗布するプロセス自体がベース層を軟化させるプロセスとなっている。このため、一定の硬度を有するベース層に塗布液を塗布しそれを押圧するという比較的簡素な製造プロセスによって、ベース層に埋め込まれた、つまりベース層との境界において段差のない電極を実現することが可能となっている。また、ベース層のうち軟化するのは塗布液が塗布されて溶剤に触れる部分、つまり電極が形成されるべき部分のみに限定される。このため、ベース層の他の部分に表面形状の乱れや電気絶縁性の低下などの影響を及ぼすことがなく、また形成される電極の形状の崩れも抑制される。 As described above, according to the electrode forming method of the present invention, the process of applying the coating liquid itself becomes a process of softening the base layer by using the solvent having the property of softening the base layer as the solvent of the coating liquid. ing. For this reason, an electrode embedded in the base layer, that is, having no step at the boundary with the base layer is realized by a relatively simple manufacturing process in which a coating liquid is applied to a base layer having a certain hardness and pressed. It is possible. Further, the softening of the base layer is limited only to the portion where the coating liquid is applied and touched with the solvent, that is, the portion where the electrode is to be formed. For this reason, the other part of the base layer is not affected by the disturbance of the surface shape or the electrical insulation, and the shape of the formed electrode is also prevented from being deformed.
　また、この発明に係る有機薄膜トランジスタの製造方法の一の態様は、上記目的を達成するため、上記の電極形成方法により前記ベース層に前記電極を形成する工程と、前記ベース層の表面に、前記電極を覆う有機半導体層を形成する工程とを備えている。このように構成された発明では、ベース層と電極との間で段差のない状態でこれらを覆うように有機半導体層が形成されるので、段差に起因する有機半導体の結晶性の乱れを抑制することができる。そのため、このような結晶性の乱れに起因する半導体の電気的特性の低下を抑えて、性能の良好な有機薄膜トランジスタを製造することが可能となる。 According to one aspect of the method for producing an organic thin film transistor according to the present invention, in order to achieve the above object, the step of forming the electrode on the base layer by the electrode forming method described above, the surface of the base layer, Forming an organic semiconductor layer covering the electrodes. In the invention configured as described above, since the organic semiconductor layer is formed so as to cover the base layer and the electrode without any step, the disorder of the crystallinity of the organic semiconductor due to the step is suppressed. be able to. Therefore, it is possible to manufacture an organic thin film transistor with good performance while suppressing a decrease in electrical characteristics of the semiconductor due to such disorder of crystallinity.
　また、この発明の他の一の態様は、電気絶縁性の樹脂材料により形成されたベース層の表面に電極を形成する、有機薄膜トランジスタ用の電極形成装置であって、上記目的を達成するため、前記ベース層を有する基板を保持する基板保持部と、前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液が電極形状に応じてパターニングされたパターンを担持する平板状の担持体を、パターン担持面を前記ベース層の被塗布面に近接対向させて保持する担持体保持部と、前記担持体の前記パターン担持面とは反対側の面、または前記基板の前記被塗布面とは反対側の面を押圧しながら前記基板に沿って移動するローラ状の押圧部材とを備えている。 Another aspect of the present invention is an electrode forming apparatus for an organic thin film transistor, which forms an electrode on the surface of a base layer formed of an electrically insulating resin material, in order to achieve the above object, A flat plate shape carrying a pattern in which a coating liquid containing a substrate holding portion for holding a substrate having the base layer, a solvent for softening the resin material constituting the base layer, and an electrode material is patterned according to the electrode shape. A carrier holding portion that holds a pattern carrying surface in close proximity to the surface to be coated of the base layer, a surface of the carrier opposite to the pattern carrying surface, or the substrate to be coated. A roller-shaped pressing member that moves along the substrate while pressing a surface opposite to the coating surface.
　このように構成された発明では、ベース層を軟化させる溶剤を含む塗布液がパターニングされた担持体をベース層に密着させることで、塗布液をベース層に塗布することができる。そして、ローラ状の押圧部材による加圧が軟化したベース層に塗布液を浸透させることで、ベース層に埋め込まれた電極を形成することができる。すなわち、上記構成の電極形成装置は、本発明に係る電極形成方法を実行するのに好適なものとなっている。 In the invention thus configured, the coating liquid can be applied to the base layer by bringing the carrier patterned with the coating liquid containing the solvent that softens the base layer into close contact with the base layer. Then, the electrode embedded in the base layer can be formed by allowing the coating liquid to permeate the base layer softened by the pressure applied by the roller-shaped pressing member. That is, the electrode forming apparatus having the above configuration is suitable for executing the electrode forming method according to the present invention.
　また、この発明の他の一の態様は、電気絶縁性の樹脂材料により形成されたベース層と、前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液を前記ベース層に部分的に塗布し前記ベース層に対し押圧した後固化させることにより、互いに離隔して、かつそれぞれ表面の少なくとも一部が露出した状態で前記ベース層に埋め込まれたソース電極およびドレイン電極と、前記ソース電極および前記ドレイン電極それぞれの露出表面ならびに前記ソース電極と前記ドレイン電極との間の前記ベース層の表面を連続的に覆う有機半導体層と、前記有機半導体層を覆う絶縁層と、前記絶縁層に接し前記絶縁層を介して前記有機半導体層と対向し、かつ前記有機半導体層と電気的に絶縁されたゲート電極とを備える有機薄膜トランジスタである。 According to another aspect of the present invention, there is provided a base layer made of an electrically insulating resin material, a coating liquid containing a solvent that softens the resin material constituting the base layer, and an electrode material. A source electrode and a drain electrode embedded in the base layer in a state where they are separated from each other and at least a part of the surface is exposed by being partially applied to the layer and pressed against the base layer and then solidified , An organic semiconductor layer continuously covering the exposed surface of each of the source electrode and the drain electrode and the surface of the base layer between the source electrode and the drain electrode, an insulating layer covering the organic semiconductor layer, An organic thin film comprising a gate electrode in contact with an insulating layer, facing the organic semiconductor layer through the insulating layer, and electrically insulated from the organic semiconductor layer It is a transistor.
　このように構成された発明では、上記原理によりソース電極およびドレイン電極がベース層に埋め込まれているため、有機半導体層との界面における段差が小さく、したがって有機半導体の結晶性の乱れが抑制されている。したがって、本発明を適用した有機薄膜トランジスタは、電気的性能の良好なトランジスタとなる。 In the invention configured as described above, since the source electrode and the drain electrode are embedded in the base layer according to the principle described above, the level difference at the interface with the organic semiconductor layer is small, and thus the disorder of the crystallinity of the organic semiconductor is suppressed. Yes. Therefore, the organic thin film transistor to which the present invention is applied becomes a transistor with good electrical performance.
　上記のように、本発明によれば、塗布液の溶剤としてベース層を軟化させる性質を有するものを使用する。こうすることにより、一定の硬度を有するベース層に塗布液を塗布しそれを押圧するという比較的簡素な製造プロセスによって、ベース層との境界において段差のない電極を実現することが可能である。 As described above, according to the present invention, a solvent having a property of softening the base layer is used as a solvent for the coating solution. By doing so, it is possible to realize an electrode having no step at the boundary with the base layer by a relatively simple manufacturing process in which a coating liquid is applied to a base layer having a certain hardness and pressed.
　この発明の前記ならびにその他の目的と新規な特徴は、添付図面を参照しながら次の詳細な説明を読めば、より完全に明らかとなるであろう。ただし、図面は専ら解説のためのものであって、この発明の範囲を限定するものではない。 The above and other objects and novel features of the present invention will become more fully apparent when the following detailed description is read with reference to the accompanying drawings. However, the drawings are for explanation only and do not limit the scope of the present invention.
半導体素子の製造方法の一実施形態を示すフローチャートである。It is a flowchart which shows one Embodiment of the manufacturing method of a semiconductor element. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 各製造工程における半導体素子の構造を示す図である。It is a figure which shows the structure of the semiconductor element in each manufacturing process. 転写処理工程における電極の埋め込みを説明する模式図である。It is a mimetic diagram explaining embedding of an electrode in a transfer processing process. 転写処理工程における電極の埋め込みを説明する模式図である。It is a mimetic diagram explaining embedding of an electrode in a transfer processing process. 転写処理工程における電極の埋め込みを説明する模式図である。It is a mimetic diagram explaining embedding of an electrode in a transfer processing process. 試作した有機薄膜トランジスタの構造を例示する図である。It is a figure which illustrates the structure of the prototyped organic thin-film transistor. 試作した有機薄膜トランジスタの構造を例示する図である。It is a figure which illustrates the structure of the prototyped organic thin-film transistor. 試作した有機薄膜トランジスタの構造を例示する図である。It is a figure which illustrates the structure of the prototyped organic thin-film transistor. 試作した有機薄膜トランジスタの構造を例示する図である。It is a figure which illustrates the structure of the prototyped organic thin-film transistor. 試作した有機薄膜トランジスタの電気的特性の例を示す図である。It is a figure which shows the example of the electrical property of the prototyped organic thin-film transistor. 比較例のトランジスタの断面構造を模式的に示す図である。It is a figure which shows typically the cross-section of the transistor of a comparative example. 電極形成処理の過程を示す図である。It is a figure which shows the process of an electrode formation process. 電極形成処理の過程を示す図である。It is a figure which shows the process of an electrode formation process. 電極形成処理の過程を示す図である。It is a figure which shows the process of an electrode formation process. 電極形成処理の過程を示す図である。It is a figure which shows the process of an electrode formation process. パターニング工程を示す模式図である。It is a schematic diagram which shows a patterning process. 転写工程を示す模式図である。It is a schematic diagram which shows a transcription | transfer process. 電極形成処理の他の態様を示す図である。It is a figure which shows the other aspect of an electrode formation process.
　図１は本発明に係る電極形成方法を含む半導体素子の製造方法の一実施形態を示すフローチャートである。また、図２Ａないし図２Ｄおよび図３Ａないし図３Ｅは、この製造方法により製造される半導体素子の各工程における構造を示す図である。この製造方法は、例えば半導体基板、ガラス基板、樹脂基板等の種々の平板状の基板に半導体素子を形成するために用いることができる。以下、基板Ｓとしての例えばガラス板またはポリイミド製シートの表面に、半導体素子の一例としての有機薄膜トランジスタを形成する場合の処理について詳しく説明する。しかしながら、これ以外にも種々の半導体素子の形成のために下記の方法および装置を用いることができる。 FIG. 1 is a flowchart showing an embodiment of a method for manufacturing a semiconductor device including an electrode forming method according to the present invention. 2A to 2D and FIGS. 3A to 3E are diagrams showing the structure of each step of the semiconductor element manufactured by this manufacturing method. This manufacturing method can be used for forming semiconductor elements on various flat substrates such as a semiconductor substrate, a glass substrate, and a resin substrate. Hereinafter, the process in the case of forming the organic thin-film transistor as an example of a semiconductor element on the surface of the glass sheet or polyimide sheet as the substrate S will be described in detail. However, in addition to this, the following method and apparatus can be used for forming various semiconductor elements.
　以下の説明では、基板Ｓに対し各種の機能層が積層されてなる構造体を、各工程における処理対象物たる「ワーク」と称し、符号Ｗｋを付す。このような構造体の構造は製造工程の進行に伴って順次変化するが、それらのいずれについてもワークＷｋと称するものとする。また、以下のワーク断面図においては構造上の特徴を明示するため、各層の寸法や相対的な厚さは実際のものと必ずしも一致しない。 In the following description, a structure in which various functional layers are laminated on the substrate S is referred to as a “workpiece” that is a processing target in each process, and is denoted by a reference symbol Wk. The structure of such a structure changes sequentially with the progress of the manufacturing process, and both of them are referred to as workpieces Wk. Further, in the following workpiece cross-sectional views, the structural features are clearly shown, and therefore the dimensions and relative thicknesses of the respective layers do not always coincide with the actual ones.
　最初に、処理対象となる基板が適宜の洗浄剤により洗浄され（ステップＳ１０１）、基板表面が清浄化される。そして、図２Ａに示すように、基板Ｓの一方表面Ｓａにベース層Ｂとなる樹脂層が形成される（ステップＳ１０２）。ベース層Ｂについては、例えば硬化状態で電気絶縁性を示す樹脂（例えば各種のポリマー樹脂）の材料を含む溶液を、例えばスピンコート法によって基板表面Ｓａに一様に塗布することにより形成することができる。なお、これに限定されず、一様な層を形成することのできる任意の形成方法を用いてベース層Ｂを形成することが可能である。 First, the substrate to be processed is cleaned with an appropriate cleaning agent (step S101), and the substrate surface is cleaned. Then, as shown in FIG. 2A, a resin layer that becomes the base layer B is formed on one surface Sa of the substrate S (step S102). The base layer B can be formed, for example, by uniformly applying a solution containing a resin (for example, various polymer resins) that exhibits electrical insulation in a cured state to the substrate surface Sa by, for example, spin coating. it can. Note that the present invention is not limited to this, and the base layer B can be formed by using any formation method capable of forming a uniform layer.
　ベース層Ｂの材料を含む溶液を基板Ｓに塗布する方法が用いられる場合、形成された塗膜を乾燥硬化させるため、塗布後に焼成処理が行われる（ステップＳ１０３）。これにより塗膜が硬化して、基板表面Ｓａに密着したベース層Ｂが形成される。また、硬化したベース層Ｂの表面に、新たな層を形成することが可能となる。ベース層Ｂは、基板Ｓ表面を均一かつ安定した絶縁層で被覆するとともに、後工程で形成される各層の形状を安定的に維持する機能を有する。特に、ベース層Ｂがプライマー層として機能することで、基板Ｓに対する電極の密着性を向上させ、後述するウェット処理において電極の崩れや剥落を効果的に防止することが可能である。 When a method of applying a solution containing the material of the base layer B to the substrate S is used, a baking process is performed after the application in order to dry and cure the formed coating film (step S103). As a result, the coating film is cured, and the base layer B that is in close contact with the substrate surface Sa is formed. In addition, a new layer can be formed on the surface of the cured base layer B. The base layer B has a function of covering the surface of the substrate S with a uniform and stable insulating layer and stably maintaining the shape of each layer formed in a subsequent process. In particular, since the base layer B functions as a primer layer, it is possible to improve the adhesion of the electrode to the substrate S, and to effectively prevent the electrode from collapsing or peeling off in the wet treatment described later.
　ベース層Ｂを構成するポリマー樹脂材料としては、例えば、ポリウレタン、ポリイミド、ポリアミドイミド、ポリビニルアルコール、ポリビニルフェノール、ポリエステル、ポリエチレン等を用いることができる。この場合、ポリマーを硬化させるための焼成処理は、例えば１２０℃、３０分程度の条件で行うことができる。例えば、所定の焼成温度に温度調整されたオーブン等の加熱炉内でワークＷｋを所定時間保持することにより、焼成処理を実行可能である。このような低い焼成温度で硬化するポリマー材料を採用することで、耐熱性の高くない樹脂材料も基板として用いることが可能となる。ワークＷｋは加熱炉内に静置されてもよく、また加熱炉内で搬送されつつ加熱される態様でもよい。 As the polymer resin material constituting the base layer B, for example, polyurethane, polyimide, polyamideimide, polyvinyl alcohol, polyvinylphenol, polyester, polyethylene, or the like can be used. In this case, the baking treatment for curing the polymer can be performed under conditions of, for example, 120 ° C. and about 30 minutes. For example, the baking process can be performed by holding the workpiece Wk for a predetermined time in a heating furnace such as an oven adjusted to a predetermined baking temperature. By employing such a polymer material that cures at a low firing temperature, a resin material that is not highly heat resistant can be used as the substrate. The workpiece | work Wk may be left still in a heating furnace, and the aspect heated while conveying in a heating furnace may be sufficient.
　こうして形成されたベース層Ｂの表面に、有機半導体薄膜トランジスタを構成するソース電極およびドレイン電極が形成される（ステップＳ１０４）。これらの電極の形成方法については種々の方法を採用可能である。ここではその一例として、予め形成された電極パターンをベース層Ｂに転写することで電極を形成する、印刷技術を応用した方法について説明する。 A source electrode and a drain electrode constituting the organic semiconductor thin film transistor are formed on the surface of the base layer B thus formed (step S104). Various methods can be employed for forming these electrodes. Here, as an example, a method using a printing technique in which an electrode is formed by transferring a previously formed electrode pattern to the base layer B will be described.
　図２Ｂに示すように、金属粒子（例えば銀）等の導電性材料および溶剤を含む導電性インクにより形成された電極パターンＰＴが、ガラス板、樹脂板等で形成されたブランケットＢＬの表面に予め形成される。この例では、ブランケットＢＬのパターン担持面（図における下面）に、互いに離隔した２つの電極パターンＰＴが担持されている。これら２つの電極パターンＰＴは、最終的にそれぞれソース電極およびドレイン電極となって機能する。 As shown in FIG. 2B, an electrode pattern PT formed of a conductive material including a conductive material such as metal particles (for example, silver) and a solvent is preliminarily formed on the surface of a blanket BL formed of a glass plate, a resin plate, or the like. It is formed. In this example, two electrode patterns PT spaced from each other are carried on the pattern carrying surface (the lower surface in the drawing) of the blanket BL. These two electrode patterns PT finally function as a source electrode and a drain electrode, respectively.
　ブランケットＢＬは、パターン担持面をベース層Ｂの表面に向けた状態でワークＷｋに近接対向配置される。この状態から、図２Ｃに示すように、パターン担持面とは反対側のブランケットＢＬ表面にローラ部材ＲＬが当接される。ローラ部材ＲＬがブランケットＢＬをワークＷＫ側へ押しやりながらブランケットＢＬ表面に沿って転動する。これにより、ブランケットＢＬに担持された電極パターンＰＴがベース層Ｂに押し付けられ、最終的にベース層Ｂの表面に転写される。ローラ部材ＲＬによるブランケットＢＬに対する押圧力としては、例えば０．０５Ｎ／ｍｍ2ないし０．３Ｎ／ｍｍ2とすることができる。転写時の転写後のブランケットＢＬは、ワークＷｋ近傍から搬出される。 The blanket BL is disposed in close proximity to the workpiece Wk with the pattern carrying surface facing the surface of the base layer B. From this state, as shown in FIG. 2C, the roller member RL is brought into contact with the surface of the blanket BL opposite to the pattern carrying surface. The roller member RL rolls along the surface of the blanket BL while pushing the blanket BL toward the workpiece WK. As a result, the electrode pattern PT carried on the blanket BL is pressed against the base layer B and finally transferred onto the surface of the base layer B. The pressing force against the blanket BL by the roller member RL can be set to 0.05 N / mm 2 to 0.3 N / mm 2 , for example. The blanket BL after transfer at the time of transfer is carried out from the vicinity of the workpiece Wk.
　転写された電極パターンＰＴの導電性を得るために、転写後のワークＷｋに対し焼成処理が行われる（ステップＳ１０５）。このときの焼成条件としては、例えば１２０℃、３０分とすることができるが、ステップＳ１０３における焼成処理と同一条件とすることは必須ではない。この時点でのワークＷｋは、図２Ｄに示すように、転写された電極パターンが硬化することにより形成されるソース電極Ｅｓおよびドレイン電極Ｅｄが、ベース層Ｂの内部に埋め込まれた状態となっている。このような埋め込みが生じる原理については後述する。 In order to obtain the conductivity of the transferred electrode pattern PT, the workpiece Wk after the transfer is baked (step S105). The firing conditions at this time may be, for example, 120 ° C. and 30 minutes, but it is not essential to have the same conditions as the firing process in step S103. As shown in FIG. 2D, the workpiece Wk at this point is in a state in which the source electrode Es and the drain electrode Ed formed by curing the transferred electrode pattern are embedded in the base layer B. Yes. The principle of such embedding will be described later.
　次に、形成された電極の表面を改質するための処理として、電極表面に自己組織化単分子膜（Self-Assembled Monolayer；ＳＡＭ）を形成するＳＡＭ処理が実行される（ステップＳ１０６）。ＳＡＭ処理の原理および方法は公知であるので、ここではウェット処理によりＳＡＭ膜を形成する方法の一例を簡単に説明する。イソプロプルアルコール（Isopropyl alcohol；ＩＰＡ）に濃度０．０１Ｍ程度のペンタフルオロベンゼンチオール（Pentafluorobenzenethiol；ＰＦＢＴ）を溶解させた溶液にワークＷｋを少なくとも２分浸漬する。その後にＩＰＡでリンスし乾燥させることにより、ＰＦＢＴによるＳＡＭ膜を形成することが可能である。このようなＳＡＭ膜を電極表面に形成することで、この後に積層される有機半導体層と電極との間の電気的接触を低抵抗かつ安定したものとすることができる。ＳＡＭ処理後のワークＷｋでは、図３Ａに示すように、ワークＷｋのうち電極Ｅｓ，Ｅｄの露出した表面にＰＦＢＴによる単分子膜Ｍが形成された状態となっている。 Next, as a process for modifying the surface of the formed electrode, a SAM process for forming a self-assembled monolayer (SAM) on the electrode surface is performed (step S106). Since the principle and method of SAM processing are known, an example of a method for forming a SAM film by wet processing will be briefly described here. The workpiece Wk is immersed for at least 2 minutes in a solution in which pentafluorobenzenethiol (PFBT) having a concentration of about 0.01 M is dissolved in isopropyl alcohol (IPA). Thereafter, a SAM film made of PFBT can be formed by rinsing with IPA and drying. By forming such a SAM film on the electrode surface, the electrical contact between the organic semiconductor layer and the electrode to be subsequently stacked can be made low resistance and stable. In the work Wk after the SAM treatment, as shown in FIG. 3A, the monomolecular film M made of PFBT is formed on the surface of the work Wk where the electrodes Es and Ed are exposed.
　次に、こうして電極Ｅｓ，Ｅｄが形成されたワークＷｋの表面を覆うように、有機半導体層が積層される（ステップＳ１０７）。有機半導体層は、例えば公知の真空蒸着法を用いて成膜することができる。この時点でのワークＷｋは、図３Ｂに示すように、電極Ｅｓ，Ｅｄを覆う単分子膜Ｍと露出したベース層Ｂの表面とが、有機半導体層Ｓｃにより連続的に覆われた状態となっている。 Next, an organic semiconductor layer is laminated so as to cover the surface of the workpiece Wk on which the electrodes Es and Ed are thus formed (step S107). The organic semiconductor layer can be formed by using, for example, a known vacuum deposition method. As shown in FIG. 3B, the workpiece Wk at this point is in a state where the monomolecular film M covering the electrodes Es and Ed and the exposed surface of the base layer B are continuously covered with the organic semiconductor layer Sc. ing.
　次に、有機半導体膜Ｓｃの表面を覆うゲート絶縁層が形成される（ステップＳ１０８）。ゲート絶縁層は、例えば、電気絶縁性を有する材料を、公知の化学的気相成長法（Chemical Vapor Deposition；ＣＶＤ）を用いて有機半導体膜Ｓｃの表面に堆積させて成膜することにより、形成することができる。この時点でのワークＷｋは、図３Ｃに示すように、有機半導体層Ｓｃの表面全体が連続的なゲート絶縁層Ｉｇにより覆われた状態となっている。 Next, a gate insulating layer covering the surface of the organic semiconductor film Sc is formed (step S108). The gate insulating layer is formed, for example, by depositing a material having electrical insulating properties on the surface of the organic semiconductor film Sc by using a known chemical vapor deposition (CVD) method. can do. The workpiece Wk at this time is in a state where the entire surface of the organic semiconductor layer Sc is covered with the continuous gate insulating layer Ig as shown in FIG. 3C.
　次に、ゲート絶縁層Ｉｇの表面にゲート電極が形成される（ステップＳ１０９）。例えば、ソース電極Ｅｓ、ドレイン電極Ｅｄの形成と同様の技術でゲート電極を形成することが可能である。すなわち、図３Ｄに示すように、ゲート電極となる電極パターンＰＴを担持するブランケットＢＬをワークＷｋに近接配置し、ローラ部材ＲＬ（図２Ｃ）によりブランケットＢＬを押圧することで、電極パターンＰＴをゲート絶縁層Ｉｇの表面に転写する。これを焼成処理することで（ステップＳ１１０）、図３Ｅに示すように、ゲート絶縁層Ｉｇの表面にゲート電極Ｅｇが形成される。 Next, a gate electrode is formed on the surface of the gate insulating layer Ig (step S109). For example, the gate electrode can be formed by a technique similar to the formation of the source electrode Es and the drain electrode Ed. That is, as shown in FIG. 3D, the blanket BL carrying the electrode pattern PT to be a gate electrode is disposed close to the work Wk, and the electrode pattern PT is gated by pressing the blanket BL by the roller member RL (FIG. 2C). Transfer to the surface of the insulating layer Ig. By baking this (step S110), as shown in FIG. 3E, the gate electrode Eg is formed on the surface of the gate insulating layer Ig.
　この場合の転写処理および焼成処理における処理条件についても、ソース電極Ｅｓおよびドレイン電極Ｅｄ形成時の処理条件と同等とすることができる。例えば、転写処理時のローラ部材ＲＬの押圧力を０．０５Ｎ／ｍｍ2ないし０．３Ｎ／ｍｍ2、焼成処理温度を１２０℃、焼成時間を３０分とすることができる。 The processing conditions in the transfer process and the baking process in this case can also be made equal to the processing conditions at the time of forming the source electrode Es and the drain electrode Ed. For example, the pressing force of the roller member RL during the transfer process can be 0.05 N / mm 2 to 0.3 N / mm 2 , the baking temperature can be 120 ° C., and the baking time can be 30 minutes.
　図示を省略しているが、この他に、各電極を配線による接続する工程や、形成された素子の表面を覆う保護層を形成する工程等の追加工程が適宜付加されることにより、有機薄膜トランジスタＴｒを含む電子デバイスが完成する。 Although not shown in the drawings, in addition to this, additional steps such as a step of connecting each electrode by wiring and a step of forming a protective layer covering the surface of the formed element are added as appropriate, so that the organic thin film transistor An electronic device including Tr is completed.
　以上の一連の処理により、基板Ｓ、ベース層Ｂ、ソースおよびドレイン電極Ｅｓ，Ｅｄ、有機半導体層Ｓｃ、単分子膜Ｍ、ゲート絶縁層Ｉｇ、ゲート電極Ｅｇがこの順番で積層された構造体を形成することができる。このうち、ソースおよびドレイン電極Ｅｓ，Ｅｄ、有機半導体層Ｓｃ、ゲート絶縁層Ｉｇ、ゲート電極Ｅｇが一体として有機薄膜トランジスタＴｒとして機能する。基板Ｓおよびベース層Ｂは、有機薄膜トランジスタＴｒを支持する基材として機能する。なお、実際の製造工程においては、上記した構造の有機薄膜トランジスタＴｒが、１つの基板Ｓに多数並んだ状態で同時に形成される。 Through the above-described series of processes, a structure in which the substrate S, the base layer B, the source and drain electrodes Es and Ed, the organic semiconductor layer Sc, the monomolecular film M, the gate insulating layer Ig, and the gate electrode Eg are stacked in this order is obtained. Can be formed. Among these, the source and drain electrodes Es and Ed, the organic semiconductor layer Sc, the gate insulating layer Ig, and the gate electrode Eg function as an organic thin film transistor Tr. The substrate S and the base layer B function as a base material that supports the organic thin film transistor Tr. In an actual manufacturing process, a large number of organic thin film transistors Tr having the above-described structure are simultaneously formed in a state where they are arranged on one substrate S.
　各層の厚さの一例を示すが、これらの数値に限定されるものではない。ベース層Ｂの厚さは、例えば１００ｎｍである。また、ソースおよびドレイン電極Ｅｓ，Ｅｄの厚さは例えば７０ｎｍである。また、有機半導体層Ｓｃの厚さは３０ｎｍである。また、ソース電極Ｅｓとドレイン電極Ｅｄとの距離、つまりチャネル長は例えば５０μｍである。また、ゲート絶縁層Ｉｇおよびゲート電極Ｅｇの厚さは、それぞれ例えば１００ｎｍ、２００ｎｍである。 An example of the thickness of each layer is shown, but is not limited to these values. The thickness of the base layer B is, for example, 100 nm. Further, the thickness of the source and drain electrodes Es, Ed is, for example, 70 nm. Further, the thickness of the organic semiconductor layer Sc is 30 nm. The distance between the source electrode Es and the drain electrode Ed, that is, the channel length is, for example, 50 μm. The thicknesses of the gate insulating layer Ig and the gate electrode Eg are, for example, 100 nm and 200 nm, respectively.
　なお、ベース層Ｂへのソースおよびドレイン電極Ｅｓ，Ｅｄの埋め込みを確実に行わせるために、ベース層Ｂの厚さがブランケットＢＬ上における電極パターンＰＴの厚さよりも大きくなるように、各層の厚さが設定されてもよい。 In order to ensure that the source and drain electrodes Es and Ed are embedded in the base layer B, the thickness of each layer is set so that the thickness of the base layer B is larger than the thickness of the electrode pattern PT on the blanket BL. May be set.
　有機薄膜トランジスタＴｒにおいて良好な電気的特性を得るための１つの条件として、有機半導体層Ｓｃの結晶性が良好であることが挙げられる。すなわち、有機半導体層Ｓｃが結晶粒界の多い多結晶性のものであるとき、有機半導体層Ｓｃ内におけるキャリア移動度が低いことで有機薄膜トランジスタＴｒの性能が制限される。高いキャリア移動度を得るために、有機半導体層Ｓｃは単結晶に近い良好な結晶性を有することが求められる。 One condition for obtaining good electrical characteristics in the organic thin film transistor Tr is that the crystallinity of the organic semiconductor layer Sc is good. That is, when the organic semiconductor layer Sc is polycrystalline with many crystal grain boundaries, the performance of the organic thin film transistor Tr is limited due to the low carrier mobility in the organic semiconductor layer Sc. In order to obtain high carrier mobility, the organic semiconductor layer Sc is required to have good crystallinity close to a single crystal.
　ソースおよびドレイン電極Ｅｓ，Ｅｄが形成されたワークＷｋに結晶性の良好な有機半導体層Ｓｃを形成するために、ワークＷｋ表面におけるソースおよびドレイン電極Ｅｓ，Ｅｄとその周囲のベース層Ｂとの間で、段差が少なく平滑な表面となっていることが望ましい。図２Ｄに示すように、ベース層Ｂにソースおよびドレイン電極Ｅｓ，Ｅｄが埋め込まれた構造は、このような要求に応えることのできるものである。以下、本実施形態においてこのような埋め込み構造を実現するための構成について説明する。 In order to form the organic semiconductor layer Sc having good crystallinity on the work Wk on which the source and drain electrodes Es and Ed are formed, between the source and drain electrodes Es and Ed on the surface of the work Wk and the surrounding base layer B Therefore, it is desirable that the surface has a smooth surface with few steps. As shown in FIG. 2D, the structure in which the source and drain electrodes Es and Ed are embedded in the base layer B can meet such a requirement. Hereinafter, a configuration for realizing such a buried structure in the present embodiment will be described.
　図４Ａないし図４Ｃは転写処理工程における電極の埋め込みを説明する模式図である。先に説明したように、ベース層Ｂへのソースおよびドレイン電極Ｅｓ，Ｅｄの形成は、電極材料および溶剤を含む導電性インクにより形成されたパターンＰＴをベース層Ｂに転写することによりなされる。導電性インクに含まれる溶剤は、ベース層Ｂを構成する硬化後のポリマー樹脂を軟化させる性質を有するものが用いられる。具体的には、ポリマー樹脂を膨潤させまたは溶解させるような性質を有する溶剤が用いられる。例えばベース層Ｂを構成するポリマーがポリウレタンである場合、溶剤としてはこれを軟化させる有機溶媒、特に反転印刷用導電性インクに用いられる高沸点溶媒、具体的には例えばブチルカルビトール、ヘキシルカルビトール、エチルカルビトールアセテート、ブチルカルビトールアセテート、２‐エチル‐１，３‐ヘキサンジオール、２，４‐ジエチル‐１，５‐ペンタンジオール、１，３‐ブチレングリコール、オクタンジオールを用いることができる。 4A to 4C are schematic diagrams for explaining electrode embedding in the transfer processing step. As described above, the source and drain electrodes Es and Ed are formed on the base layer B by transferring the pattern PT formed of the conductive ink containing the electrode material and the solvent to the base layer B. As the solvent contained in the conductive ink, those having a property of softening the cured polymer resin constituting the base layer B are used. Specifically, a solvent having the property of swelling or dissolving the polymer resin is used. For example, when the polymer constituting the base layer B is polyurethane, the solvent is an organic solvent that softens the solvent, in particular, a high boiling point solvent used for conductive ink for reverse printing, specifically, for example, butyl carbitol, hexyl carbitol. Ethyl carbitol acetate, butyl carbitol acetate, 2-ethyl-1,3-hexanediol, 2,4-diethyl-1,5-pentanediol, 1,3-butylene glycol, and octanediol can be used.
　図４Ａに示すように、ブランケットＢＬに担持された電極パターンＰＴがベース層Ｂの表面に触れたとき、電極パターンＰＴに含まれる溶剤成分がベース層Ｂに浸透する。これにより、ベース層Ｂの上部に溶剤により膨潤または溶解し軟化した領域（軟化領域）ＳＲが生じる。この状態で、図４Ｂに示すように、ローラ部材ＲＬによる押圧力が加えられると、電極パターンＰＴが軟化領域ＳＲの内部に向けて押し込まれることになる。その結果、図４Ｃに示すように、電極パターンＰＴがベース層Ｂに埋め込まれた構造が実現される。また、電極パターンＰＴの表面がベース層Ｂに押し付けられることで、電極パターンＰＴと周囲のベース層Ｂとの界面に段差が生じることが抑制される。 As shown in FIG. 4A, when the electrode pattern PT carried on the blanket BL touches the surface of the base layer B, the solvent component contained in the electrode pattern PT penetrates into the base layer B. Thereby, a region (softened region) SR swollen or dissolved by the solvent and softened is formed on the upper part of the base layer B. In this state, as shown in FIG. 4B, when a pressing force is applied by the roller member RL, the electrode pattern PT is pushed toward the inside of the softened region SR. As a result, as shown in FIG. 4C, a structure in which the electrode pattern PT is embedded in the base layer B is realized. Further, when the surface of the electrode pattern PT is pressed against the base layer B, it is possible to suppress the occurrence of a step at the interface between the electrode pattern PT and the surrounding base layer B.
　つまり、この製造方法においては、電極パターンＰＴをベース層Ｂに転写するプロセスそのものが、電極パターンＰＴをベース層Ｂに埋め込むプロセスにもなっている。このため、転写前のベース層Ｂの下処理や、転写後の後加工等によって電極パターンＰＴの埋め込みを行う必要がない。 That is, in this manufacturing method, the process itself of transferring the electrode pattern PT to the base layer B is a process of embedding the electrode pattern PT in the base layer B. For this reason, it is not necessary to embed the electrode pattern PT by pretreatment of the base layer B before transfer, post-processing after transfer, or the like.
　図５Ａ、図５Ｂ、図６Ａおよび図６Ｂは試作した有機薄膜トランジスタの構造を例示する図である。より具体的には、図５Ａは、上記製造方法によって製造された有機薄膜トランジスタの断面構造の一例を示す顕微鏡（ＴＥＭ）写真であり、図５Ｂはそのうちドレイン電極の形状を模式的に示す図である。また、図６Ａは、上記製造方法によって製造された有機薄膜トランジスタの断面構造の他の一例を示す顕微鏡写真であり、図６Ｂはそのうちドレイン電極の形状を模式的に示す図である。なおソース電極の形状も基本的に同じである。 FIG. 5A, FIG. 5B, FIG. 6A and FIG. 6B are diagrams illustrating the structure of a prototype organic thin film transistor. More specifically, FIG. 5A is a microscope (TEM) photograph showing an example of a cross-sectional structure of the organic thin film transistor manufactured by the above manufacturing method, and FIG. 5B is a diagram schematically showing the shape of the drain electrode. . FIG. 6A is a photomicrograph showing another example of the cross-sectional structure of the organic thin film transistor manufactured by the above manufacturing method, and FIG. 6B is a diagram schematically showing the shape of the drain electrode. The shape of the source electrode is basically the same.
　図５Ａおよび図５Ｂに示す事例では、ドレイン電極Ｅｄの厚みが概ね一定に保たれたまま、その端部がベース層Ｂに埋め込まれた形状となっている。一方、図６Ａおよび図６Ｂに示す事例では、ドレイン電極Ｅｄがその端部において厚みが次第に減少する態様でベース層Ｂに埋め込まれている。このように複数個体の間で電極の断面形状には幾分ばらつきが見られるが、いずれの事例においても、ドレイン電極Ｅｄはベース層Ｂの表面から緩やかに盛り上がるような表面形状となっており、有機半導体層Ｓｃとの界面は段差のない滑らかな曲面となっている。このため、顕著な段差に起因する有機半導体層Ｓｃの結晶性の乱れを抑えて、有機薄膜トランジスタＴｒの性能を良好なものとすることが可能である。 In the example shown in FIGS. 5A and 5B, the drain electrode Ed has a shape in which the end portion is embedded in the base layer B while the thickness of the drain electrode Ed is kept substantially constant. On the other hand, in the case shown in FIGS. 6A and 6B, the drain electrode Ed is embedded in the base layer B in such a manner that the thickness gradually decreases at the end thereof. In this way, there is some variation in the cross-sectional shape of the electrodes among a plurality of individuals, but in any case, the drain electrode Ed has a surface shape that gently rises from the surface of the base layer B. The interface with the organic semiconductor layer Sc is a smooth curved surface with no steps. For this reason, it is possible to improve the performance of the organic thin-film transistor Tr by suppressing the disorder of the crystallinity of the organic semiconductor layer Sc caused by a significant step.
　なお、ゲート電極Ｅｇの形成に際し、電極パターンＰＴがゲート絶縁層Ｉｇに埋め込まれることは、電気的特性に影響を与えないため必要ではない。したがって、ゲート電極Ｅｇの形成工程においては電極パターンＰＴに含まれる溶剤成分とゲート絶縁層Ｉｇの材料との間に特別の関係は必要とされない。むしろ、絶縁性を担保するとの観点からは、ゲート絶縁層Ｉｇは溶剤に対し変化を示さない材料で形成されることが好ましい。 It should be noted that it is not necessary to embed the electrode pattern PT in the gate insulating layer Ig when forming the gate electrode Eg because it does not affect the electrical characteristics. Therefore, no special relationship is required between the solvent component contained in the electrode pattern PT and the material of the gate insulating layer Ig in the step of forming the gate electrode Eg. Rather, from the viewpoint of ensuring insulation, the gate insulating layer Ig is preferably formed of a material that does not change with respect to the solvent.
　図７Ａおよび図７Ｂは試作した有機薄膜トランジスタの電気的特性の例を示す図である。より具体的には、図７Ａは試作した有機薄膜トランジスタおよび比較例における電気的特性の実測例を示すグラフである。また、図７Ｂは比較例のトランジスタの断面構造を模式的に示す図である。なお、構造の対比を容易にするため、図７Ｂでは、図３Ｅに示すトランジスタＴｒの各構成と同一の機能を有する構成に同一の符号を付している。 FIG. 7A and FIG. 7B are diagrams showing examples of electrical characteristics of a prototype organic thin film transistor. More specifically, FIG. 7A is a graph showing an example of actual measurement of electrical characteristics in a prototype organic thin film transistor and a comparative example. FIG. 7B is a diagram schematically showing a cross-sectional structure of a transistor of a comparative example. Note that, in order to facilitate the comparison of the structures, in FIG. 7B, the same reference numerals are given to the configurations having the same functions as the configurations of the transistors Tr illustrated in FIG. 3E.
　本実施形態の製造方法により製造される有機薄膜トランジスタＴｒは、図３Ｅに示すように、ソースおよびドレイン電極Ｅｓ，Ｅｄが層間に配置されゲート電極Ｅｇが素子表面に現れる、いわゆるトップゲート型のトランジスタである。一方、比較例として図７Ｂに示すトランジスタは、ゲート電極Ｅｇが層間に配置されソースおよびドレイン電極Ｅｓ，Ｅｄが素子表面に現れる、いわゆるボトムゲート型のトランジスタである。比較例においては、ガラス基板Ｓにクロム（膜厚３ｎｍ）および金（膜厚５０ｎｍ）を積層したゲート電極Ｅｇ、ＣＶＤ法による膜厚１００ｎｍのゲート絶縁層Ｉｇ、真空蒸着法による膜厚３０ｎｍの有機半導体層Ｓｃ、金の真空蒸着によるソースおよびドレイン電極Ｅｓ，Ｅｄ（膜厚５０ｎｍ、チャネル長５０μｍ）が順に積層されている。 The organic thin film transistor Tr manufactured by the manufacturing method of this embodiment is a so-called top gate type transistor in which the source and drain electrodes Es and Ed are arranged between the layers and the gate electrode Eg appears on the element surface as shown in FIG. 3E. is there. On the other hand, the transistor shown in FIG. 7B as a comparative example is a so-called bottom gate type transistor in which the gate electrode Eg is disposed between the layers and the source and drain electrodes Es and Ed appear on the element surface. In the comparative example, a gate electrode Eg in which chromium (film thickness 3 nm) and gold (film thickness 50 nm) are stacked on a glass substrate S, a gate insulating layer Ig having a film thickness of 100 nm by a CVD method, and an organic film having a film thickness of 30 nm by a vacuum evaporation method. A semiconductor layer Sc, and source and drain electrodes Es and Ed (film thickness of 50 nm, channel length of 50 μm) formed by vacuum deposition of gold are sequentially stacked.
　薄膜トランジスタでは半導体層のうちソース電極とドレイン電極とを接続する部分が電流の流通するチャネルとして機能する。従来のトップゲート型トランジスタでは、ソースおよびドレイン電極の周囲での有機半導体層の結晶性の乱れに起因して、ソース電極とドレイン電極とを電気的に接続するチャネル部分における有機半導体のキャリア移動度が小さい。このため、有機半導体層を平坦な層とすることができるボトムゲート型トランジスタに比べて電気的特性が劣る傾向がある。 In a thin film transistor, a portion of a semiconductor layer that connects a source electrode and a drain electrode functions as a channel through which a current flows. In a conventional top-gate transistor, the carrier mobility of the organic semiconductor in the channel portion that electrically connects the source electrode and the drain electrode due to disorder of the crystallinity of the organic semiconductor layer around the source and drain electrodes Is small. For this reason, there exists a tendency for an electrical characteristic to be inferior compared with the bottom gate type transistor which can make an organic-semiconductor layer into a flat layer.
　しかしながら、図７Ａに示すように、本実施形態により製造されるトップゲート型トランジスタは、比較例のボトムゲート型トランジスタとほぼ同等の電気的特性を有するものとなった。より具体的には、ドレイン電圧が（－５）Ｖの測定条件において、本実施形態により製造されるトランジスタと比較例のトランジスタとの間で、飽和領域でのキャリア移動度（電界効果移動度）および最大ドレイン電流を比較した。その結果は、
・本実施形態：
　　電界効果移動度　０．２８３［ｃｍ2／Ｖ・ｓ］、
　　最大ドレイン電流　８．２６×１０-7［Ａ］
・比較例：
　　電界効果移動度　０．２９７［ｃｍ2／Ｖ・ｓ］、
　　最大ドレイン電流　７．３０×１０-7［Ａ］
であった。このことから、本実施形態の製造方法により製造される有機半導体薄膜トランジスタＴｒが、比較例のボトムゲート型トランジスタとほぼ同等の電気的特性を有することがわかる。したがって有機半導体層Ｓｃが良好な結晶性を有していると言える。 However, as shown in FIG. 7A, the top gate transistor manufactured according to this embodiment has substantially the same electrical characteristics as the bottom gate transistor of the comparative example. More specifically, the carrier mobility (field effect mobility) in the saturation region between the transistor manufactured according to this embodiment and the transistor of the comparative example under the measurement condition where the drain voltage is (−5) V. And the maximum drain current was compared. The result is
-This embodiment:
Field effect mobility 0.283 [cm 2 / V · s],
Maximum drain current 8.26 × 10 −7 [A]
・ Comparative example:
Field effect mobility 0.297 [cm 2 / V · s],
Maximum drain current 7.30 × 10 −7 [A]
Met. From this, it can be seen that the organic semiconductor thin film transistor Tr manufactured by the manufacturing method of this embodiment has substantially the same electrical characteristics as the bottom gate transistor of the comparative example. Therefore, it can be said that the organic semiconductor layer Sc has good crystallinity.
　次に、基板Ｓにベース層Ｂが形成された図２Ａに示すワークＷｋ、あるいはゲート絶縁層Ｉｇが形成された図３Ｃに示すワークＷｋに電極パターンＰＴを転写し電極を形成する方法につき、さらに詳しく説明する。前述のように、この実施形態において電極（ソース電極Ｅｓ、ドレイン電極Ｅｄ、ゲート電極Ｅｇ）は、ブランケットＢＬ表面でパターン化された導電性インクをワークＷｋに転写することにより形成される。 Next, a method for transferring the electrode pattern PT to the workpiece Wk shown in FIG. 2A in which the base layer B is formed on the substrate S or the workpiece Wk shown in FIG. explain in detail. As described above, in this embodiment, the electrodes (source electrode Es, drain electrode Ed, and gate electrode Eg) are formed by transferring the conductive ink patterned on the surface of the blanket BL to the workpiece Wk.
　このような電極形成処理は、ブランケットＢＬ上に導電性インクによる電極パターンＰＴを形成するパターニング工程と、形成された電極パターンＰＴをワークＷｋに転写する転写工程とに細分化することができる。以下に説明するように、パターニング工程と転写工程とは同一の処理装置を用いて実行することが可能である。なお、ここに説明する処理については、例えば本願出願人が先に開示した特開２０１６－２０３５１８号公報に記載された転写装置により実行することが可能である。 Such an electrode forming process can be subdivided into a patterning process for forming the electrode pattern PT with conductive ink on the blanket BL and a transfer process for transferring the formed electrode pattern PT to the work Wk. As will be described below, the patterning step and the transfer step can be performed using the same processing apparatus. The processing described here can be executed by, for example, the transfer device described in Japanese Patent Application Laid-Open No. 2016-203518 previously disclosed by the applicant of the present application.
　図８Ａないし図８Ｄは電極形成処理の過程を示す図である。また、図９Ａおよび図９Ｂはパターニング工程および転写工程を示す模式図である。図８Ａないし図８Ｄに示す直交座標系において、ＸＹ平面が水平面を表す。また、Ｚ方向が鉛直方向を表し、より具体的には、（＋Ｚ）方向が鉛直上向き方向を表す。図８Ａないし図８Ｄを参照しながら、まずパターニング工程について説明する。 8A to 8D are diagrams showing a process of electrode formation processing. 9A and 9B are schematic views showing a patterning process and a transfer process. In the orthogonal coordinate system shown in FIGS. 8A to 8D, the XY plane represents a horizontal plane. Further, the Z direction represents the vertical direction, and more specifically, the (+ Z) direction represents the vertical upward direction. First, the patterning process will be described with reference to FIGS. 8A to 8D.
　電極形成処理を実行する転写装置１では、下面が真空吸着面となった上ステージ１１と、中央部が大きく開口する額縁形状を有する下ステージ１２とが、それぞれ水平姿勢で互いに近接対向配置されている。下ステージ１２の開口１２１の開口サイズは、上ステージ１１の平面サイズよりも大きい。開口１２１の内部には、図示しない昇降機構により個別に昇降可能に支持された複数の昇降ハンド１３が配置されている。 In the transfer apparatus 1 that performs the electrode forming process, an upper stage 11 having a vacuum suction surface on the lower surface and a lower stage 12 having a frame shape with a large opening at the center are arranged in close proximity to each other in a horizontal posture. Yes. The opening size of the opening 121 of the lower stage 12 is larger than the planar size of the upper stage 11. Inside the opening 121, a plurality of lifting hands 13 supported by a lifting mechanism (not shown) so as to be lifted and lowered individually are arranged.
　また、開口１２１の（－Ｘ）側（図において左方）端部付近には、Ｙ方向に延びる円柱状または円筒状の押圧ローラ１４が配置されている。押圧ローラ１４は、支持部材１５によりＹ方向の中心軸回りに回転自在に支持されている。支持部材１５は図示しない駆動機構によりＺ方向への昇降およびＸ方向への走行が可能となっている。押圧ローラ１４は、図２Ｃに示すローラ部材ＲＬに相当する機能を有するものである。 A columnar or cylindrical pressing roller 14 extending in the Y direction is disposed near the (−X) side (left side in the drawing) end of the opening 121. The pressing roller 14 is supported by the support member 15 so as to be rotatable around the central axis in the Y direction. The support member 15 can be moved up and down in the Z direction and traveled in the X direction by a drive mechanism (not shown). The pressing roller 14 has a function corresponding to the roller member RL shown in FIG. 2C.
　パターニング工程では、図８Ａに示すように、最初に、所望の電極パターンを反転させた凸パターンを有する版ＰＰが転写装置１に搬入され、上ステージ１１にセットされる。上ステージ１１は、凸パターンが形成されたパターン形成面を下向きにして版ＰＰを吸着保持する。また、予め導電性インクＩｋが一様に塗布されたブランケットＢＬが転写装置１に搬入され、下ステージ１２にセットされる。下ステージ１２は、導電性インクＩｋが塗布された面を上向きにして版ＰＰに対向させた状態で、ブランケットＢＬの周縁部を吸着保持する。 In the patterning step, as shown in FIG. 8A, first, a plate PP having a convex pattern obtained by inverting a desired electrode pattern is carried into the transfer apparatus 1 and set on the upper stage 11. The upper stage 11 sucks and holds the plate PP with the pattern forming surface on which the convex pattern is formed facing downward. Further, the blanket BL on which the conductive ink Ik is uniformly applied in advance is carried into the transfer device 1 and set on the lower stage 12. The lower stage 12 sucks and holds the peripheral edge portion of the blanket BL with the surface coated with the conductive ink Ik facing upward and facing the plate PP.
　初期状態では、各昇降ハンド１３が、その上面が下ステージ１２の上面と同じ高さとなるような高さに位置決めされることで、開放された状態のブランケットＢＬ中央部が水平姿勢に維持される。また、押圧ローラ１４は、水平方向においては版ＰＰの（－Ｘ）側端部の下方、鉛直方向においては上端がブランケットＢＬ下面から離間した状態となる位置に位置決めされる。 In the initial state, each lifting hand 13 is positioned at such a height that the upper surface thereof is the same as the upper surface of the lower stage 12, so that the center portion of the opened blanket BL is maintained in a horizontal posture. . The pressing roller 14 is positioned below the (−X) side end of the plate PP in the horizontal direction and at a position where the upper end is separated from the lower surface of the blanket BL in the vertical direction.
　この状態から、支持部材１５が押圧ローラ１４を上昇させることで、押圧ローラ１４がブランケットＢＬの下面に当接する。押圧ローラ１４がブランケットＢＬ下面に当接した後も上昇を続けることにより、図８Ｂに示すように、ブランケットＢＬが押圧ローラ１４により押し上げられ、最終的にはブランケットＢＬ上面が版ＰＰの下面に当接する。これにより、ブランケットＢＬ上面に担持されたインクＩｋが版ＰＰに密着する。さらに押圧ローラ１４がブランケットＢＬを押し上げることで、インクＩｋが所定の押圧力で版ＰＰに押し付けられる。 From this state, the supporting member 15 raises the pressing roller 14 so that the pressing roller 14 comes into contact with the lower surface of the blanket BL. As shown in FIG. 8B, as the pressing roller 14 continues to rise after contacting the lower surface of the blanket BL, the blanket BL is pushed up by the pressing roller 14, and finally the upper surface of the blanket BL touches the lower surface of the plate PP. Touch. As a result, the ink Ik carried on the upper surface of the blanket BL adheres to the plate PP. Further, when the pressing roller 14 pushes up the blanket BL, the ink Ik is pressed against the plate PP with a predetermined pressing force.
　この状態で支持部材１５が押圧ローラ１４を（＋Ｘ）方向に移動させることで、押圧ローラ１４がブランケットＢＬの下面に当接して従動回転しながら（＋Ｘ）方向へ走行する。これにより、インクＩｋを介してブランケットＢＬと版ＰＰとが密着する領域がＸ方向に広がってゆく。このとき、複数の昇降ハンド１３のそれぞれは、図８Ｃに示すように、走行する押圧ローラ１４との干渉を避けるために、支持部材１５の移動に伴って順次下降する。 In this state, the support member 15 moves the pressing roller 14 in the (+ X) direction, so that the pressing roller 14 contacts the lower surface of the blanket BL and travels in the (+ X) direction while being driven to rotate. As a result, a region where the blanket BL and the plate PP are in close contact with each other via the ink Ik expands in the X direction. At this time, as shown in FIG. 8C, each of the plurality of elevating hands 13 is sequentially lowered as the support member 15 moves in order to avoid interference with the traveling pressing roller 14.
　図８Ｄに示すように、押圧ローラ１４が版ＰＰの（＋Ｘ）側端部直下の終了位置に到達すると、版ＰＰ全体がブランケットＢＬに当接した状態となる。この状態で版ＰＰとブランケットＢＬとが剥離されると、ブランケットＢＬに一様塗布されたインクＩｋのうち凸パターンに対応する部分が版ＰＰに移行し、他の部分がブランケットＢＬ上に残留する。こうすることで、インクＩｋが凸パターンによりパターニングされ、当該凸パターンの反転パターンが電極パターンＰＴとしてブランケットＢＬに転写される。図９ＡはブランケットＢＬに塗布されたインクＩｋが版ＰＰによりパターニングされ電極パターンＰＴが形成される過程を模式的に示した図である。 As shown in FIG. 8D, when the pressing roller 14 reaches the end position immediately below the (+ X) side end of the plate PP, the entire plate PP is in contact with the blanket BL. When the plate PP and the blanket BL are peeled in this state, a portion corresponding to the convex pattern of the ink Ik uniformly applied to the blanket BL shifts to the plate PP, and other portions remain on the blanket BL. . By doing so, the ink Ik is patterned by the convex pattern, and the inverted pattern of the convex pattern is transferred to the blanket BL as the electrode pattern PT. FIG. 9A schematically shows a process in which the ink Ik applied to the blanket BL is patterned by the plate PP to form the electrode pattern PT.
　一方、こうしてブランケットＢＬに形成された電極パターンＰＴをワークＷｋに転写する転写工程は、上記処理における版ＰＰをワークＷｋに、インクＩｋを電極パターンＰＴに読み替えることで説明可能である。すなわち、電極パターンＰＴが担持されたブランケットＢＬが下ステージ１２により、該パターンを転写されるワークＷｋが上ステージ１１により、それぞれ保持される（図８Ａ）。 On the other hand, the transfer step of transferring the electrode pattern PT formed on the blanket BL to the workpiece Wk in this way can be explained by replacing the plate PP in the above processing with the workpiece Wk and the ink Ik with the electrode pattern PT. That is, the blanket BL carrying the electrode pattern PT is held by the lower stage 12, and the work Wk to which the pattern is transferred is held by the upper stage 11 (FIG. 8A).
　そして、押圧ローラ１４がブランケットＢＬを所定の押圧力でワークＷｋに押し付けながらＸ方向に走行することで（図８Ｂないし図８Ｄ）、ブランケットＢＬとワークＷｋとが電極パターンＰＴを介して密着する。ワークＷｋとブランケットＢＬとを剥離させると、ブランケットＢＬ上の電極パターンＰＴがワークＷｋに転写される。 Then, when the pressing roller 14 travels in the X direction while pressing the blanket BL against the workpiece Wk with a predetermined pressing force (FIGS. 8B to 8D), the blanket BL and the workpiece Wk come into close contact via the electrode pattern PT. When the work Wk and the blanket BL are peeled off, the electrode pattern PT on the blanket BL is transferred to the work Wk.
　図９Ｂは、基板Ｓにベース層Ｂが形成されてなるワークＷｋに電極パターンＰＴが転写される過程（図１のステップＳ１０４）を模式的に示した図である。ベース層Ｂは事前の焼成処理により既に硬化した状態となっている。このため、押圧ローラ１４からの押圧力によってベース層Ｂが塑性変形することはない。一方、電極パターンＰＴは未乾燥の状態であり溶剤成分を多く含んでいる。このため、電極パターンＰＴと接するベース層Ｂが溶解または膨潤することで軟化し、電極パターンＰＴがベース層Ｂに強く押し付けられることでベース層Ｂに埋め込まれる。 FIG. 9B is a diagram schematically showing a process (step S104 in FIG. 1) in which the electrode pattern PT is transferred to the workpiece Wk in which the base layer B is formed on the substrate S. The base layer B is already hardened by a prior baking process. For this reason, the base layer B is not plastically deformed by the pressing force from the pressing roller 14. On the other hand, the electrode pattern PT is in an undried state and contains a lot of solvent components. Therefore, the base layer B in contact with the electrode pattern PT is softened by dissolving or swelling, and the electrode pattern PT is strongly pressed against the base layer B and embedded in the base layer B.
　なお、上記の電極形成処理は、いずれも平板形状を有するブランケットＢＬとワークＷｋとを密着させた後剥離することで電極パターンＰＴをブランケットＢＬからワークＷｋに転写させる、平行平板印刷技術を応用したものである。しかしながら、ワークＷｋに電極パターンＰＴを形成する方法はこれに限定されず、例えば以下に例示するように種々の方法を適用することが可能である。 In addition, in the above electrode forming process, a parallel plate printing technique is applied in which the electrode pattern PT is transferred from the blanket BL to the workpiece Wk by bringing the blanket BL having a flat plate shape into contact with the workpiece Wk and then peeling off. Is. However, the method of forming the electrode pattern PT on the workpiece Wk is not limited to this, and various methods can be applied as exemplified below.
　図１０は電極形成処理の他の態様を示す図である。この態様に用いられる転写装置２では、円筒状のブランケット胴２１の表面にブランケット２２が巻回されている。また、電極パターンＰＴは凹版２３上でパターニングされている。ブランケット胴２１を所定速度で回転させつつ、凹版２３がブランケット２２と当接しながら移動することにより、凹版２３でパターニングされた電極パターンＰＴがブランケット２２に転写される。続いて、ステージ２４に載置されたワークＷｋをブランケットＢＬに当接させながらステージ２４が移動することにより、ブランケットＢＬ上の電極パターンＰＴがワークＷｋに転写される。電極パターンＰＴに含まれる溶剤成分がワークＷｋのベース層Ｂを溶解または膨潤させることにより、電極パターンＰＴはベース層Ｂに埋め込まれる。この方法はオフセット凹版印刷技術に相当するものである。このような方法によっても、ワークＷｋに電極を形成することが可能である。 FIG. 10 is a diagram showing another aspect of the electrode forming process. In the transfer device 2 used in this embodiment, a blanket 22 is wound around the surface of a cylindrical blanket cylinder 21. The electrode pattern PT is patterned on the intaglio 23. The intaglio 23 moves while contacting the blanket 22 while rotating the blanket cylinder 21 at a predetermined speed, whereby the electrode pattern PT patterned by the intaglio 23 is transferred to the blanket 22. Subsequently, the stage 24 moves while bringing the workpiece Wk placed on the stage 24 into contact with the blanket BL, whereby the electrode pattern PT on the blanket BL is transferred to the workpiece Wk. The solvent component contained in the electrode pattern PT dissolves or swells the base layer B of the workpiece Wk, so that the electrode pattern PT is embedded in the base layer B. This method corresponds to the offset intaglio printing technique. An electrode can be formed on the workpiece Wk also by such a method.
　また、平板または円筒状のブランケット上でのパターン形成が他の方法により実行されてもよい。例えば、スクリーン印刷法、インクジェット法等の印刷技術を用いて導電性インクをブランケット表面に部分的に着液させることによって、電極パターンが形成されてもよい。ワークＷｋに電極パターンＰＴを転写するという目的においては、これらの印刷技術によりワークＷｋ表面に直接インクを着液させることも考えられる。しかしながら、インクをワークＷｋに接触させつつ加圧することで電極パターンＰＴをベース層Ｂに埋め込むという目的に合致するものではない。 Further, pattern formation on a flat plate or a cylindrical blanket may be performed by other methods. For example, the electrode pattern may be formed by partially landing the conductive ink on the blanket surface using a printing technique such as a screen printing method or an ink jet method. In order to transfer the electrode pattern PT to the workpiece Wk, it is also conceivable that ink is directly applied to the surface of the workpiece Wk by these printing techniques. However, this does not meet the purpose of embedding the electrode pattern PT in the base layer B by applying pressure while bringing the ink into contact with the workpiece Wk.
　ただし、これらの印刷技術によりワークＷｋ表面にインクを着液させた後、別途押圧のための工程を追加することにより、同様の効果を得ることは可能である。そのような方法と比較したとき、パターン転写と押圧とを同時に実行することができるという点で、上記実施形態は特に有効である。 However, it is possible to obtain the same effect by adding a step for pressing separately after ink is deposited on the surface of the workpiece Wk by these printing techniques. Compared with such a method, the above embodiment is particularly effective in that pattern transfer and pressing can be performed simultaneously.
　以上のように、この実施形態では、半導体素子（有機薄膜トランジスタ）中において有機半導体層の形成に先立つ電極の形成に際し、有機半導体層と接する界面における顕著な段差を生じさせないようにするために、次のような方法が採られている。すなわち、電極の形成に先立ち、基板Ｓに絶縁性樹脂材料によるベース層Ｂが形成される。そして、ベース層Ｂの表面に、電極材料および溶剤を含むインクが定められたパターンに応じて部分的に塗布される。ここで、溶剤はベース層を構成する樹脂材料を軟化させる性質を有するものとされる。 As described above, in this embodiment, when forming an electrode prior to the formation of the organic semiconductor layer in the semiconductor element (organic thin film transistor), in order to prevent a significant step at the interface in contact with the organic semiconductor layer from occurring, The method like this is taken. That is, prior to the formation of the electrodes, the base layer B made of an insulating resin material is formed on the substrate S. Then, an ink containing an electrode material and a solvent is partially applied to the surface of the base layer B according to a predetermined pattern. Here, the solvent has a property of softening the resin material constituting the base layer.
　ベース層Ｂ表面に形成された電極パターンＰＴが未固化の状態で押圧を受けることにより、溶剤により軟化したベース層Ｂの内部に浸透する。このため、電極パターンＰＴを固化させることにより形成される電極は、ベース層Ｂに埋め込まれた状態となる。その結果、こうして形成される半導体素子において、ベース層Ｂに積層された電極の表面とベース層の露出表面とが滑らかな曲面を構成することとなる。これにより、両表面の境界において顕著な段差が生じることが回避される。 When the electrode pattern PT formed on the surface of the base layer B is pressed in an unsolidified state, it penetrates into the base layer B softened by the solvent. For this reason, the electrode formed by solidifying the electrode pattern PT is in a state of being embedded in the base layer B. As a result, in the semiconductor element thus formed, the surface of the electrode laminated on the base layer B and the exposed surface of the base layer constitute a smooth curved surface. This avoids the occurrence of a significant step at the boundary between both surfaces.
　したがって、これらを覆うように形成される有機半導体層も平滑な表面を有することとなる。そのため、段差によって生じる結晶性の乱れに起因する有機半導体層の電気的特性の低下を抑制することができる。すなわち、本実施形態の製造方法によれば、電気的特性の良好な有機薄膜トランジスタを安定的に製造することが可能である。 Therefore, the organic semiconductor layer formed so as to cover these also has a smooth surface. Therefore, it is possible to suppress a decrease in electrical characteristics of the organic semiconductor layer due to the disorder of crystallinity caused by the step. That is, according to the manufacturing method of the present embodiment, it is possible to stably manufacture an organic thin film transistor having good electrical characteristics.
　また、電極パターンＰＴの転写による電極形成時にローラ部材による押圧を行っているので、パターン転写と電極の埋め込みとを同時に実現することが可能である。このため、電極形成により生じる段差を解消するための処理工程が不要であり、製造装置の設備コストおよび製造コストを大きく低減することが可能である。 Further, since the roller member is pressed when forming the electrode by transferring the electrode pattern PT, it is possible to simultaneously realize pattern transfer and electrode embedding. For this reason, the process process for eliminating the level | step difference produced by electrode formation is unnecessary, and it is possible to reduce the installation cost and manufacturing cost of a manufacturing apparatus greatly.
　以上説明したように、上記実施形態の有機薄膜トランジスタ用電極形成方法およびこれを含む有機薄膜トランジスタの製造方法においては、導電性インクＩｋが本発明の「塗布液」に相当している。そして、ブランケットＢＬおよびローラ部材ＲＬが、それぞれ本発明の「担持体」および「ローラ」として機能している。 As described above, in the organic thin film transistor electrode forming method and the organic thin film transistor manufacturing method including the same according to the above embodiment, the conductive ink Ik corresponds to the “coating liquid” of the present invention. The blanket BL and the roller member RL function as the “carrier” and “roller” of the present invention, respectively.
　また、図８Ａに示す転写装置１および図１０に示す転写装置２が本発明の「電極形成装置」として機能している。転写装置１においては、上ステージ１１が本発明の「基板保持部」として機能しており、下ステージ１２が本発明の「担持体保持部」として機能している。また、押圧ローラ１４が本発明の「押圧部材」として機能している。一方、転写装置２においては、ステージ２４が本発明の「基板保持部」として機能しており、ブランケット２２が本発明の「担持体」として機能している。そして、ブランケット胴２１は、本発明の「担持体保持部」および「押圧部材」としての機能を兼備している。 Further, the transfer device 1 shown in FIG. 8A and the transfer device 2 shown in FIG. 10 function as the “electrode forming device” of the present invention. In the transfer apparatus 1, the upper stage 11 functions as a “substrate holding part” of the present invention, and the lower stage 12 functions as a “supporting body holding part” of the present invention. Further, the pressing roller 14 functions as a “pressing member” of the present invention. On the other hand, in the transfer apparatus 2, the stage 24 functions as the “substrate holding portion” of the present invention, and the blanket 22 functions as the “supporting body” of the present invention. The blanket cylinder 21 also functions as the “supporting body holding portion” and the “pressing member” of the present invention.
　なお、本発明は上記した実施形態に限定されるものではなく、その趣旨を逸脱しない限りにおいて上述したもの以外に種々の変更を行うことが可能である。例えば、上記した実施形態は、本発明の電極形成方法を含む半導体素子（具体的には有機薄膜トランジスタ）の製造方法に関するものである。しかしながら、本発明の電極形成方法は、半導体素子の製造プロセス以外にも適用することが可能である。 Note that the present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, the above-described embodiment relates to a method for manufacturing a semiconductor element (specifically, an organic thin film transistor) including the electrode forming method of the present invention. However, the electrode forming method of the present invention can be applied to processes other than the semiconductor element manufacturing process.
　また例えば、本発明は、上記のような有機薄膜トランジスタに限定されない種々の半導体素子の製造に適用することが可能である。上記方法で製造される半導体素子はトップゲート・ボトムコンタクト型の有機薄膜トランジスタであるが、例えばボトムゲート・トップコンタクト型の有機薄膜トランジスタの製造に本発明が適用されてもよい。 Also, for example, the present invention can be applied to the manufacture of various semiconductor elements that are not limited to the organic thin film transistors as described above. The semiconductor element manufactured by the above method is a top gate / bottom contact type organic thin film transistor, but the present invention may be applied to, for example, the manufacture of a bottom gate / top contact type organic thin film transistor.
　また、上記実施形態の原理説明（図２Ｃ）においては、ワークＷｋの上面に電極パターンＰＴが転写され、上方からローラ部材ＲＬによる押圧を受ける。一方、これとは逆に、具体的な転写装置１ではワークＷｋの下面に電極パターンＰＴが転写され、下方から押圧ローラ１４による押圧ローラを受ける。しかしながら、これらは技術的には等価であり、ワークＷｋに対する押圧方向は任意である。電極パターンＰＴの転写を受けるベース層Ｂは予め硬化されて流動性を有していないので、押圧方向による差異は特に生じない。 In the description of the principle of the above-described embodiment (FIG. 2C), the electrode pattern PT is transferred to the upper surface of the workpiece Wk and is pressed by the roller member RL from above. On the other hand, in the specific transfer device 1, the electrode pattern PT is transferred to the lower surface of the workpiece Wk, and receives the pressing roller by the pressing roller 14 from below. However, these are technically equivalent, and the pressing direction with respect to the workpiece Wk is arbitrary. Since the base layer B that receives the transfer of the electrode pattern PT is cured in advance and has no fluidity, there is no particular difference depending on the pressing direction.
　また、上記実施形態では、基板Ｓの表面にベース層Ｂが形成されたワークＷｋに対し電極パターンＰＴが転写される。しかしながら、基板Ｓ自体が電気絶縁性を有し、かつ導電性インクの溶剤により軟化する性質のものであれば、改めてベース層を形成する必要はない。すなわちこの場合、基板Ｓ自体が本発明の「ベース層」としての機能を有することとなる。 In the above embodiment, the electrode pattern PT is transferred to the workpiece Wk having the base layer B formed on the surface of the substrate S. However, if the substrate S itself has electrical insulating properties and is softened by the solvent of the conductive ink, there is no need to form a base layer again. That is, in this case, the substrate S itself has a function as the “base layer” of the present invention.
　以上、具体的な実施形態を例示して説明してきたように、本発明に係る有機薄膜トランジスタ用の電極形成方法において、溶剤は、樹脂材料を膨潤させまたは溶解する有機溶媒であってよい。このような構成によれば、溶剤により膨潤または溶解したベース層に塗布液が浸透することにより、ベース層の内部に埋め込まれた電極を形成することができる。 As described above, in the method for forming an electrode for an organic thin film transistor according to the present invention, the solvent may be an organic solvent that swells or dissolves the resin material, as described above by exemplifying specific embodiments. According to such a configuration, the electrode embedded in the base layer can be formed by allowing the coating liquid to penetrate into the base layer swollen or dissolved by the solvent.
　また例えば、ベース層は、基板に樹脂材料またはその原料物質を含む液体を塗布し固化させることにより形成されるものであってよい。このようにして既に固化した状態のベース層に塗布液が塗布されることにより、未固化のベース層への塗布とは異なり、安定した塗布が可能となる。そして、いったん固化したベース層を溶剤で軟化させることにより、電極のベース層への埋め込みを効果的に実現することができる。 Further, for example, the base layer may be formed by applying a resin material or a liquid containing the raw material to the substrate and solidifying it. By applying the coating solution to the already solidified base layer in this manner, unlike the application to the unsolidified base layer, stable coating is possible. Then, by softening the solidified base layer with a solvent, it is possible to effectively realize embedding of the electrode in the base layer.
　また例えば、樹脂材料がポリウレタンであり、溶剤が２，４‐ジエチル‐１，５‐ペンタンジオールであってよい。このような樹脂材料と溶剤との組み合わせにより上記した電極の埋め込みが実現可能であることが、本願発明者の実験により明らかとなっている。 For example, the resin material may be polyurethane and the solvent may be 2,4-diethyl-1,5-pentanediol. It is clear from experiments by the inventors of the present application that the above-described electrode embedding can be realized by such a combination of a resin material and a solvent.
　また例えば、電極形状に応じてパターニングされた塗布液のパターンを担持体に担持させ、該担持体をベース層に押し当てることで、ベース層へ塗布液を転写しつつ押圧を行う構成であってよい。このような構成によれば、ベース層に塗布液を転写するプロセス自体が塗布液を押圧するプロセスを兼ねることとなるので、これらを別工程として設ける必要がなく、製造に要する時間およびコストの短縮を図ることが可能となる。 In addition, for example, the pattern of the coating liquid patterned according to the electrode shape is supported on a carrier, and the carrier is pressed against the base layer, whereby pressing is performed while the coating liquid is transferred to the base layer. Good. According to such a configuration, since the process itself for transferring the coating liquid to the base layer also serves as a process for pressing the coating liquid, it is not necessary to provide these as separate processes, and the time and cost required for manufacturing are reduced. Can be achieved.
　この場合、担持体のパターン担持面が平坦であり、パターン担持面をベース層の被塗布面に近接対向させまたは密着させて、担持体のパターン担持面とは反対側の面を、またはベース層の被塗布面とは反対側の面を、ローラで押圧する構成であってよい。このような構成によれば、担持体に担持されたパターンをベース層に押し当てることにより転写を行いつつ、同時にパターンを軟化したベース層の内部に浸透させることができる。 In this case, the pattern carrying surface of the carrier is flat, and the pattern carrying surface is brought close to or in close contact with the surface to be coated of the base layer, and the surface of the carrier opposite to the pattern carrying surface or the base layer The surface opposite to the surface to be coated may be pressed with a roller. According to such a configuration, it is possible to infiltrate the inside of the softened base layer while performing transfer by pressing the pattern carried on the carrier against the base layer.
　また例えば、ベース層の厚さが電極の厚さよりも大きくてもよい。電極の厚さに対しベース層が薄すぎると、ベース層に対する電極の埋め込み量が限定され、結果としてベース層表面と電極表面との間の段差を解消することができない場合が生じ得る。少なくともベース層の厚さが電極の厚さよりも大きければ、この問題を回避して、確実に電極の埋め込みを実現することが可能である。 For example, the thickness of the base layer may be larger than the thickness of the electrode. If the base layer is too thin with respect to the thickness of the electrode, the amount of the electrode embedded in the base layer is limited, and as a result, a step between the base layer surface and the electrode surface may not be eliminated. If at least the thickness of the base layer is larger than the thickness of the electrode, this problem can be avoided and the electrode can be reliably embedded.
　また、本発明に係る有機薄膜トランジスタの製造方法においては、例えば、電極の形成後、電極の表面を改質するためのウェット処理を実行する工程を備えてもよい。基板に直接電極を設けた場合、このようなウェット処理工程で形成済みの電極が基板から剥がれ落ちてしまうおそれがある。予めベース層を設けておくことは、このような問題にも対応して、電極の剥落を効果的に防止することのできるものである。 Further, in the method for manufacturing an organic thin film transistor according to the present invention, for example, a step of performing a wet treatment for modifying the surface of the electrode after the electrode is formed may be provided. When the electrode is directly provided on the substrate, there is a possibility that the electrode already formed in such a wet treatment process may be peeled off from the substrate. Providing the base layer in advance can effectively prevent peeling of the electrode in response to such a problem.
　また、本発明に係る有機薄膜トランジスタでは、例えば、ソース電極およびドレイン電極それぞれの露出表面と有機半導体層との間に自己組織化単分子膜が設けられてもよい。このような構成によれば、電極と有機半導体層との間の電気的接触を低抵抗かつ安定したものとすることができる。 In the organic thin film transistor according to the present invention, for example, a self-assembled monolayer may be provided between the exposed surface of each of the source electrode and the drain electrode and the organic semiconductor layer. According to such a configuration, the electrical contact between the electrode and the organic semiconductor layer can be made low resistance and stable.
　以上、特定の実施例に沿って発明を説明したが、この説明は限定的な意味で解釈されることを意図したものではない。発明の説明を参照すれば、本発明のその他の実施形態と同様に、開示された実施形態の様々な変形例が、この技術に精通した者に明らかとなるであろう。故に、添付の特許請求の範囲は、発明の真の範囲を逸脱しない範囲内で、当該変形例または実施形態を含むものと考えられる。 Although the invention has been described with reference to specific embodiments, this description is not intended to be construed in a limiting sense. Reference to the description of the invention, as well as other embodiments of the present invention, various modifications of the disclosed embodiments will become apparent to those skilled in the art. Accordingly, the appended claims are intended to include such modifications or embodiments without departing from the true scope of the invention.
　この発明は、基板に電極を形成する電極形成技術全般に適用することが可能であるが、基板と電極との間の段差に起因する結晶性の乱れが電気的特性の劣化原因となる有機薄膜トランジスタの製造において特に有効なものである。 The present invention can be applied to all electrode forming techniques for forming electrodes on a substrate, but an organic thin film transistor in which disorder of crystallinity caused by a step between the substrate and the electrode causes deterioration of electrical characteristics. It is particularly effective in the production of
　１，２　転写装置（電極形成装置）
　１１　上ステージ（基板保持部）
　１２　下ステージ（担持体保持部）
　１４　押圧ローラ（押圧部材）
　２１　ブランケット胴（担持体保持部、押圧部材）
　２２　ブランケット（担持体）
　２４　ステージ（基板保持部）
　Ｂ　ベース層
　Ｅｄ　ドレイン電極
　Ｅｇ　ゲート電極
　Ｅｓ　ソース電極
　Ｉｇ　ゲート絶縁層
　Ｉｋ　導電性インク（塗布液）
　ＰＴ　電極パターン
　Ｓ　基板
　Ｓｃ　有機半導体層
　Ｔｒ　有機半導体薄膜トランジスタ
　Ｗｋ　ワーク 1, 2 Transfer device (electrode forming device)
11 Upper stage (substrate holder)
12 Lower stage (supporting body holding part)
14 Pressing roller (pressing member)
21 Blanket cylinder (supporting body holding part, pressing member)
22 Blanket (support)
24 stage (substrate holder)
B Base layer Ed Drain electrode Eg Gate electrode Es Source electrode Ig Gate insulating layer Ik Conductive ink (coating liquid)
PT electrode pattern S substrate Sc organic semiconductor layer Tr organic semiconductor thin film transistor Wk work

Claims (12)

  1. 　電気絶縁性の樹脂材料により形成されたベース層の表面に電極を形成する、有機薄膜トランジスタ用の電極形成方法であって、
    　前記ベース層を準備する工程と、
    　前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液を、前記ベース層の表面に電極形状に応じたパターンで塗布する工程と、
    　未固化の前記塗布液を前記ベース層に対し押圧する工程と、
    　前記溶剤を揮発させ前記塗布液を固化させて、前記電極を形成する工程と
    を備える有機薄膜トランジスタ用の電極形成方法。     An electrode forming method for an organic thin film transistor, wherein an electrode is formed on a surface of a base layer formed of an electrically insulating resin material,
    Preparing the base layer;
    Applying a coating liquid containing a solvent for softening the resin material constituting the base layer and an electrode material to the surface of the base layer in a pattern corresponding to an electrode shape;
    Pressing the unsolidified coating solution against the base layer;
    An electrode forming method for an organic thin film transistor, comprising: evaporating the solvent and solidifying the coating solution to form the electrode.
  2. 　前記溶剤は、前記樹脂材料を膨潤させまたは溶解する有機溶媒である請求項１に記載の有機薄膜トランジスタ用の電極形成方法。 2. The electrode forming method for an organic thin film transistor according to claim 1, wherein the solvent is an organic solvent that swells or dissolves the resin material.
  3. 　前記ベース層は、基板に前記樹脂材料またはその原料物質を含む液体を塗布し固化させることにより形成される請求項１または２に記載の有機薄膜トランジスタ用の電極形成方法。 3. The method for forming an electrode for an organic thin film transistor according to claim 1, wherein the base layer is formed by applying and solidifying a liquid containing the resin material or a raw material thereof on a substrate.
  4. 　前記樹脂材料がポリウレタンであり、前記溶剤が高沸点溶剤である請求項１ないし３のいずれかに記載の有機薄膜トランジスタ用の電極形成方法。 The method for forming an electrode for an organic thin film transistor according to any one of claims 1 to 3, wherein the resin material is polyurethane and the solvent is a high boiling point solvent.
  5. 　前記電極形状に応じてパターニングされた前記塗布液のパターンを担持体に担持させ、前記担持体を前記ベース層に押し当てることで、前記ベース層へ前記塗布液を転写しつつ押圧を行う、請求項１ないし４のいずれかに記載の有機薄膜トランジスタ用の電極形成方法。 The pattern of the coating liquid patterned according to the electrode shape is supported on a carrier, and the carrier is pressed against the base layer to perform pressing while transferring the coating liquid to the base layer. Item 5. A method for forming an electrode for an organic thin film transistor according to any one of Items 1 to 4.
  6. 　前記担持体のパターン担持面が平坦であり、前記パターン担持面を前記ベース層の被塗布面に近接対向させまたは密着させて、前記担持体の前記パターン担持面とは反対側の面を、または前記ベース層の前記被塗布面とは反対側の面を、ローラで押圧する請求項５に記載の有機薄膜トランジスタ用の電極形成方法。 The pattern carrying surface of the carrier is flat, and the pattern carrying surface is brought close to or in close contact with the coated surface of the base layer, and the surface of the carrier opposite to the pattern carrying surface, or The method for forming an electrode for an organic thin film transistor according to claim 5, wherein a surface of the base layer opposite to the surface to be coated is pressed with a roller.
  7. 　前記ベース層の厚さが前記電極の厚さよりも大きい請求項１ないし６のいずれかに記載の有機薄膜トランジスタ用の電極形成方法。 The method for forming an electrode for an organic thin film transistor according to any one of claims 1 to 6, wherein a thickness of the base layer is larger than a thickness of the electrode.
  8. 　請求項１ないし７のいずれかに記載の電極形成方法により、前記ベース層に前記電極を形成する工程と、
    　前記ベース層の表面に、前記電極を覆う有機半導体層を形成する工程と
    を備える有機薄膜トランジスタの製造方法。     Forming the electrode on the base layer by the electrode forming method according to claim 1;
    Forming an organic semiconductor layer covering the electrode on the surface of the base layer.
  9. 　前記電極の形成後、前記電極の表面を改質するためのウェット処理を実行する工程を備える請求項８に記載の有機薄膜トランジスタの製造方法。 The method for producing an organic thin film transistor according to claim 8, further comprising a step of performing a wet treatment for modifying the surface of the electrode after the formation of the electrode.
  10. 　電気絶縁性の樹脂材料により形成されたベース層の表面に電極を形成する、有機薄膜トランジスタ用の電極形成装置であって、
    　前記ベース層を有する基板を保持する基板保持部と、
    　前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液が電極形状に応じてパターニングされたパターンを担持する平板状の担持体を、パターン担持面を前記ベース層の被塗布面に近接対向させて保持する担持体保持部と、
    　前記担持体の前記パターン担持面とは反対側の面、または前記基板の前記被塗布面とは反対側の面を押圧しながら前記基板に沿って移動するローラ状の押圧部材と
    を備える有機薄膜トランジスタ用の電極形成装置。     An electrode forming apparatus for an organic thin film transistor, which forms an electrode on the surface of a base layer formed of an electrically insulating resin material,
    A substrate holding unit for holding a substrate having the base layer;
    A plate-like carrier carrying a pattern in which a coating liquid containing a solvent for softening the resin material constituting the base layer and an electrode material is patterned according to the shape of the electrode, and the pattern carrying surface of the base layer being covered. A carrier holding part that holds the application surface in close proximity to each other;
    An organic thin film transistor comprising: a roller-like pressing member that moves along the substrate while pressing the surface of the carrier opposite to the pattern carrying surface or the surface of the substrate opposite to the coated surface Electrode forming apparatus.
  11. 　電気絶縁性の樹脂材料により形成されたベース層と、
    　前記ベース層を構成する前記樹脂材料を軟化させる溶剤と電極材料とを含む塗布液を前記ベース層に部分的に塗布し前記ベース層に対し押圧した後固化させることにより、互いに離隔して、かつそれぞれ表面の少なくとも一部が露出した状態で前記ベース層に埋め込まれたソース電極およびドレイン電極と、
    　前記ソース電極および前記ドレイン電極それぞれの露出表面ならびに前記ソース電極と前記ドレイン電極との間の前記ベース層の表面を連続的に覆う有機半導体層と、
    　前記有機半導体層を覆う絶縁層と、
    　前記絶縁層に接し前記絶縁層を介して前記有機半導体層と対向し、かつ前記有機半導体層と電気的に絶縁されたゲート電極と
    を備える有機薄膜トランジスタ。     A base layer formed of an electrically insulating resin material;
    A coating liquid containing a solvent for softening the resin material constituting the base layer and an electrode material is partially applied to the base layer, pressed against the base layer, and then solidified, and separated from each other, and A source electrode and a drain electrode embedded in the base layer with at least a part of the surface exposed,
    An organic semiconductor layer continuously covering an exposed surface of each of the source electrode and the drain electrode and a surface of the base layer between the source electrode and the drain electrode;
    An insulating layer covering the organic semiconductor layer;
    An organic thin film transistor comprising a gate electrode that is in contact with the insulating layer and faces the organic semiconductor layer through the insulating layer, and is electrically insulated from the organic semiconductor layer.
  12. 　前記ソース電極および前記ドレイン電極それぞれの前記露出表面と前記有機半導体層との間に、自己組織化単分子膜が設けられた請求項１１に記載の有機薄膜トランジスタ。 The organic thin film transistor according to claim 11, wherein a self-assembled monolayer is provided between the exposed surface of each of the source electrode and the drain electrode and the organic semiconductor layer.
PCT/JP2019/015802 2018-04-24 2019-04-11 Method of forming electrode and device for forming electrode for organic thin film transistor, method of manufacturing organic thin film transistor, and organic thin film transistor WO2019208241A1 (en)

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JP2006163418A (en) * 2004-12-08 2006-06-22 Samsung Sdi Co Ltd Method of forming conductive pattern, thin film transistor transistor using the same, and manufacturing method thereof
JP2013534726A (en) * 2010-06-24 2013-09-05 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング Method for modifying electrodes in organic electronic devices

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JP5459570B2 (en) * 2008-02-05 2014-04-02 セイコーエプソン株式会社 Semiconductor device manufacturing method, electro-optical device manufacturing method, and electronic device manufacturing method
JP2009218295A (en) * 2008-03-07 2009-09-24 Ricoh Co Ltd Thin film transistor, method of manufacturing the same, active matrix type thin film transistor array and active matrix driven display device

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US20060030067A1 (en) * 2004-08-06 2006-02-09 Industrial Technology Research Institute Method for manufacturing organic thin-film transistor with plastic substrate
JP2006163418A (en) * 2004-12-08 2006-06-22 Samsung Sdi Co Ltd Method of forming conductive pattern, thin film transistor transistor using the same, and manufacturing method thereof
JP2013534726A (en) * 2010-06-24 2013-09-05 メルク パテント ゲゼルシャフト ミット ベシュレンクテル ハフツング Method for modifying electrodes in organic electronic devices

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