WO2019184971A1 - 副链路缓存状态报告的上报方法和终端设备 - Google Patents

副链路缓存状态报告的上报方法和终端设备 Download PDF

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Publication number
WO2019184971A1
WO2019184971A1 PCT/CN2019/080078 CN2019080078W WO2019184971A1 WO 2019184971 A1 WO2019184971 A1 WO 2019184971A1 CN 2019080078 W CN2019080078 W CN 2019080078W WO 2019184971 A1 WO2019184971 A1 WO 2019184971A1
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WIPO (PCT)
Prior art keywords
logical channel
channel group
destination address
domain
bitmap
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PCT/CN2019/080078
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English (en)
French (fr)
Inventor
周建萍
杨晓东
郑倩
马景智
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维沃移动通信有限公司
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Publication of WO2019184971A1 publication Critical patent/WO2019184971A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
    • H04L1/0006—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format
    • H04L1/0007—Systems modifying transmission characteristics according to link quality, e.g. power backoff by adapting the transmission format by modifying the frame length
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/0278—Traffic management, e.g. flow control or congestion control using buffer status reports
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W28/00—Network traffic management; Network resource management
    • H04W28/02—Traffic management, e.g. flow control or congestion control
    • H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
    • H04W28/065—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information using assembly or disassembly of packets

Definitions

  • the present disclosure relates to the field of communications, and in particular, to a reporting method and a terminal device for reporting a secondary link cache status.
  • Sidelink BSR Sidelink Buffer Status Report
  • the format of the LTE Sidelink BSR is in the order of the Logical Channel Group Identity (LCG ID). When there are not enough resources to report the resource requirements, one or more destination indexes may be reported for the same LCG ID. Pass the amount of data. For the fast-growing Vehicle to Everything (V2X) services and use cases, the service priority division needs to be more detailed.
  • the number of logical channel groups (LCGs) of the LTE Sidelink BSR is only 4 sets, which cannot meet the current requirements.
  • LTE Sidelink's Buffer Size field occupies 6 bits, and the total index is 64 types, and there are few types, while the enhanced vehicle networking (enhanced V2X, eV2X) service type requires a larger amount of data, if LTE 64 is still used.
  • the index, eV2X indicates that the Buffer Size span of each level is large, and the base station cannot accurately confirm the demand of the Sidelink UE for resources, which will cause a certain amount of resource waste in the resource scheduling process.
  • the current agreement has not yet defined the Sidelink BSR format of New Radio (NR).
  • An object of the embodiments of the present disclosure is to provide a method for transmitting a secondary link buffer status report, and a terminal device, which can more flexibly indicate a Buffer of valid data that can be used for transmission of all logical channels in a logical channel group based on a short-range service destination address. Size.
  • an embodiment of the present disclosure provides a method for transmitting a secondary link buffer status report, where the method includes: sending a secondary link cache status report, where the secondary link cache status report includes: a destination address field, a logical channel Group domain and cache size domain, or include logical channel group domain and cache size domain,
  • the destination address field and at least one of the logical channel group domains are represented based on a bitmap.
  • an embodiment of the present disclosure provides a terminal device, where the terminal device includes: a sending module, and a secondary link buffer status report, where the secondary link cache status report includes: a destination address domain, a logical channel group domain, and Cache size domain, or include logical channel group domain and cache size domain,
  • the destination address field and at least one of the logical channel group domains are represented based on a bitmap.
  • an embodiment of the present disclosure provides a terminal device, including a processor, a memory, and a program stored on the memory and executable on the processor, where the program is used by the processor. The steps of the method as described in the first aspect are implemented when executed.
  • an embodiment of the present disclosure provides a computer readable storage medium storing a program on a computer readable storage medium, the program being executed by a processor to implement the steps of the method as described in the first aspect.
  • bitmap-based per destination index and/or the Perlink BSR format of the per LCG ID it is possible to more flexibly indicate that all logical channels in a logical channel group based on the short-range service destination address are available for transmission. Buffer Size of valid data.
  • FIG. 1 is a flow chart of a method for transmitting a Sidelink BSR according to an embodiment of the present disclosure.
  • FIG. 2 is a schematic diagram of a MAC CE of a Sidelink BSR according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a MAC CE of a Sidelink BSR of another embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 7 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a subheader of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a subheader of a MAC CE of a Sidelink BSR according to another embodiment of the present disclosure.
  • FIG. 10 is a schematic structural diagram of a terminal device according to an embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a terminal device according to another embodiment of the present disclosure.
  • GSM Global System of Mobile communication
  • CDMA Code Division Multiple Access
  • WCDMA Wideband Code Division Multiple Access
  • GPRS General Packet Radio Service
  • LTE Long Term Evolution
  • LTE-A Long Term Evolution advanced
  • New Air Interface New Radio, NR
  • a user equipment which may also be called a mobile terminal, a mobile user equipment, or the like, may be connected to a radio access network (for example, a radio access network (RAN)) and one or The plurality of core networks communicate, and the user equipment can be a terminal device, such as a mobile phone (or "cellular" phone) and a computer with a terminal device, for example, can be portable, pocket-sized, handheld, built-in or on-board Mobile devices that exchange language and/or data with a wireless access network.
  • a radio access network for example, a radio access network (RAN)
  • RAN radio access network
  • the base station may be a Base Transceiver Station (BTS) in GSM or CDMA, or may be a base station (NodeB) in WCDMA, or may be an evolved base station (eNB or e-NodeB) in LTE and
  • BTS Base Transceiver Station
  • NodeB base station
  • eNB evolved base station
  • gNB 5G base station
  • the LCG (logical channel group) of the Sidelink BSR is divided into four groups.
  • the field of one logical channel group index occupies 2 bits, and the LCG (logical channel group) corresponding to the reported (cache area) is specified.
  • the Destination Index is configurable in length, with a maximum of 16 groups, and a destination address index field occupies 4 bits, corresponding to the destination group destination L2ID of the communication.
  • the Buffer Size is arranged in the order in which the logical channel group contains the sub-link logical channel priorities decreasing.
  • the Buffer Size field is 6 bits long and specifies all Media Access Control (MAC) MAC protocol data units (Protocol Data Units) within the Transmission Time Interval (TTI) of the Sendlink UE.
  • MAC Media Access Control
  • TTI Transmission Time Interval
  • the LCG corresponding to the short-range service destination address includes the remaining Radio Link Control (RLC) layer and the Packet Data Convergence Protocol (PDCP) layer of all logical channels. The sum of valid data available for transmission.
  • RLC Radio Link Control
  • PDCP Packet Data Convergence Protocol
  • FIG. 1 is a flowchart of a method for transmitting a Sidelink Buffer Status Report (Sidelink BSR) according to an embodiment of the present disclosure.
  • the method of Figure 1 is performed by a secondary link terminal device.
  • the method can include:
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the role of the Sidelink BSR is that the Sidelink UE transmits the amount of data to be transmitted of all logical channels in a logical channel group based on the ProSe Destination to the base station.
  • the destination address field is a field field carrying the destination address information of the secondary link terminal device, or the destination address field is the destination address information of the secondary link terminal device.
  • the logical channel group domain is a field field carrying logical channel group information of the secondary link terminal device, or the logical channel group domain is logical channel group information of the secondary link terminal device;
  • the buffer size field is a field field of the to-be-sent data amount information of the logical channel group carrying the sub-link terminal device, or the buffer size field is the to-be-sent data amount of the logical channel group of the sub-link terminal device.
  • bitmap-based Per destination index and/or the Perlink BSR format of the per LCG ID it is possible to more flexibly indicate that all logical channels in a logical channel group based on the ProSe Destination are to be sent. Buffer Size of valid data that can be used for transmission.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is an index of at least one destination address reported by the secondary link terminal device, and the at least one destination address is a data transferable destination address of the secondary link terminal device;
  • the logical channel group domain is at least one logical channel group bitmap, the at least one logical channel group bitmap is in one-to-one correspondence with the at least one destination address, and one logical channel group bitmap is used to indicate whether all logical channel groups in the corresponding destination address are available. Pass data
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the first bit in the first logical channel group bitmap corresponding to the index of the first destination address, and the first amount of data to be sent indicates that the secondary link terminal device is a sum of the amount of data to be transmitted of all the logical channels of the first logical channel group of the first destination address, where the first logical channel group is a logical channel group corresponding to the first bit.
  • the destination address index is used to indicate that the secondary link terminal device has a data transferable destination address.
  • each destination address index corresponds to a logical channel group bitmap in the logical channel group domain, and the logical channel group bitmap indicates whether all logical channel groups corresponding to the destination address have transmittable data. For example, when a logical channel group corresponding to a destination address is eight, the logical channel group bitmap indicates whether the logical channel group LCG0-LCG7 corresponding to the destination address has transmittable data.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, and the destination address domain is continuous, and the logical channel group domain is continuous, and the cache size domain is continuous. It is continuous.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • a corresponding amount of pending data on one logical channel group is in a buffer size domain. It occupies 8 bits.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous
  • the number of destination address indexes is an odd number, which may be set to 2*N-1.
  • the length of the logical channel group field is 2*N-1 bytes
  • the length of the buffer size field is m.
  • the first 4 bits of the first byte of the destination address field are reserved bits.
  • the reserved bits may also be located in the last 4 bits of the last byte of the destination address field.
  • the first 4 bits or the last 4 bits of the reserved bit are located in any other byte of the destination address field.
  • FIG. 3 is a schematic diagram of a MAC CE of a Sidelink BSR according to an embodiment of the present disclosure.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous
  • the number of destination address indexes is even, which may be set to 2*N.
  • the destination address is The length of the domain is N bytes
  • the length of the logical channel group domain is 2*N bytes
  • the length of the buffer size domain is m bytes, where m is the bit in all logical channel group bitmaps of the logical channel group domain.
  • the total number of bits is set to 1.
  • the destination address field is continuous, the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, and the cache size domain is discontinuous, the cache The size field includes at least one buffer size sub-domain, and the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is one of the to-be-sent data amounts, and the at least one logical channel group
  • Each of the logical channel group subfields in the domain is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • the corresponding amount of pending data on one logical channel group occupies 8 bits in the buffer size domain.
  • the number of destination address indexes is an odd number, it may be set to 2*N-1.
  • the length of the destination address field is N bytes, and the length of the logical channel group domain is 2*.
  • N-1 bytes the length of the buffer size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the first 4 bits of the first byte of the destination address field are reserved bits, or the last 4 bits of the last byte of the destination address field are reserved bits. Of course, it is not excluded that the first 4 bits or the last 4 bits of the reserved bit are located in any other byte of the destination address field.
  • the number of destination address indexes is an even number, it may be set to 2*N.
  • the length of the destination address field is N bytes, and the length of the logical channel group domain is 2*N.
  • the length of the buffer size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, the logical channel group domain is discontinuous, and the logical channel group domain includes at least one logical channel group
  • the cache size field is not continuous.
  • the cache size field includes at least one cache size sub-domain.
  • the destination address sub-domain is a destination address index
  • the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address.
  • a buffer size sub-domain is the amount of data to be sent, each logical channel group sub-domain in the at least one logical channel group sub-domain is followed by x cache size sub-fields, and x is a logical channel group to be followed.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • one destination address index occupies 4 bits
  • one destination address corresponds to 8 logical channel groups (LCG0-LCG7)
  • the corresponding amount of pending data on one logical channel group occupies 8 bits in the buffer size domain.
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is N bytes
  • the length of the buffer size field is m bytes
  • m is the logic.
  • the number of bits in all logical channel group bitmaps of the channel group domain is set to 1, wherein each byte in the destination address field includes 4 reserved bits.
  • the length of the destination address index of the Sidelink BSR may not be 4 bits, and the logical channel group corresponding to one destination address may not be eight, and the number of bits occupied by one data to be sent may not be eight.
  • Those skilled in the art can derive the length of each domain of the Sidelink BSR in the foregoing scenario based on actual conditions.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is a destination address bitmap reported by the terminal device carrying the secondary link, and the destination address bitmap is used to indicate whether the destination address of the secondary link terminal device has data to be transmitted;
  • the logical channel group domain is at least one logical channel group bitmap, and the at least one logical channel group bitmap is in one-to-one correspondence with the destination address of the destination address bitmap bit set to 1, and one logical channel group bitmap is used to indicate the corresponding destination address. Whether all logical channel groups have data to transmit;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in a logical channel group bitmap of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the second bit of the first logical channel group bitmap corresponding to the first bit of the destination address bitmap, and the first amount of data to be sent represents the secondary link terminal device.
  • the first destination address is a destination address indicated by a first bit of the destination address bitmap
  • the first logical channel group is The logical channel group indicated by the second bit of the first logical channel group bitmap.
  • each bit set to 1 in the destination address bitmap corresponds to one logical channel group bitmap
  • the logical channel group bitmap indicates all logical channel groups corresponding to the destination address corresponding to the bit set to 1. Is there any data available? For example, when the first destination address is set to 1 in the destination address bitmap, and the first destination address corresponds to the first logical channel group bitmap, and a destination address corresponds to 8 logical channel groups, Then, the first logical channel group bitmap indicates whether the logical channel group LCG0-LCG7 corresponding to the first destination address has transmittable data.
  • the logical channel group domain is contiguous and the cache size domain is contiguous.
  • the total number of destination addresses is 16 and one destination address corresponds to 8 logical channel groups (LCG0-LCG7), and the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain. Based on this, the length of each domain of the Sidelink BSR in several different scenarios will be described below.
  • FIG. 4 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the destination address domain is continuous
  • the logical channel group domain is continuous
  • the buffer size domain is continuous, and it is assumed that 2 bytes can be used to indicate whether the destination address of the secondary link terminal device has data transferable, and data is transmittable therein.
  • the number of destination addresses is N
  • the total number of bits in the logical channel group bitmap of the logical channel group domain is set to 1.
  • the length of the destination address field is 2 bytes
  • the length of the logical channel group field is N bytes
  • N is the total number of bits in the destination address bitmap of the destination address field being set to 1
  • the buffer size domain The length is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size
  • a logical channel group sub-domain of the logical channel group is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is a data volume to be sent, and each of the logical channel groups in the at least one logical channel group sub-domain
  • the subfield is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • the length of the destination address field is 2 bytes
  • the length of the logical channel group field is N bytes
  • N is the total number of bits in the destination address bitmap of the destination address field being set to 1
  • the length of the buffer size field For m bytes, m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the total number of destination addresses may not be 16 4
  • the logical channel group corresponding to one destination address may not be 8
  • the number of bits occupied by one pending data volume may not be 8.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes a logical channel group domain and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap corresponding to the size of v2x-DestinationInfoList destination addresses of the secondary link terminal device, and one logical channel group bitmap is used to indicate whether all logical channel groups of the corresponding destination address have data transferable. ;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the amount of data to be transmitted corresponds to the first bit of the first logical channel group bitmap
  • the first logical channel group bitmap corresponds to the first destination address
  • the first amount of data to be sent represents the pair.
  • v2x-DestinationInfoList may be specified by a protocol or configured by a Radio Resource Control (RRC).
  • RRC Radio Resource Control
  • the protocol may specify that the destination addresses of the indices 1, 3, 5, 7 are used among the 16 destination addresses; for example, the first six destination addresses of the 16 destination addresses may be configured by RRC signaling, and so on.
  • the logical channel group domain occupies the same number of bytes as the parameter size of v2x-DestinationInfoList; the buffer size field has a length of m bytes, and m is all logic of the logical channel group domain.
  • the logical channel group domain is contiguous and the cache size domain is contiguous.
  • FIG. 5 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the logical channel group domain is continuous and the buffer size domain is continuous.
  • the logical channel group domain includes size of v2x-DestinationInfoList consecutive logical channel group bitmaps, each logical channel group bitmap corresponds to one destination address, and each logical channel group bitmap occupies 1 byte.
  • the length of the buffer size field is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size
  • a logical channel group sub-domain of the logical channel group is a logical channel group bitmap corresponding to a destination address, and the buffer size sub-domain is a data volume to be sent, and each of the logical channel groups in the at least one logical channel group sub-domain
  • the subfield is followed by x buffer size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield.
  • the value of x can be zero.
  • the value of x may be 0-8.
  • the logical channel group corresponding to one destination address may not be eight, and the number of bits occupied by one data to be sent may not be eight.
  • Those skilled in the art can derive the length of each domain of the Sidelink BSR in the foregoing scenario based on actual conditions.
  • the MAC CE of the Sidelink BSR includes information of the entire Sidelink BSR; if the secondary link If the uplink resource of the terminal device is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR after the truncation process.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap, and the one logical channel group bitmap is used to indicate whether the secondary link terminal device has data to be transmitted in all logical channel groups;
  • the destination address field is at least one destination address bitmap, and the at least one destination address bitmap is in one-to-one correspondence with a logical channel group in which the bit in the logical channel group bitmap is set to 1, and a destination address bitmap is used to indicate the secondary link terminal. Whether all destination addresses of the device have data to be transmitted on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first bit of the logical channel group address bitmap, and the first amount of data to be sent indicates that the secondary link terminal device is in the first purpose.
  • the total number of logical channel groups is eight, the total number of destination addresses is 16, and the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain.
  • the logical channel group domain length is 1 byte; a destination address bitmap occupies 2 bytes, the destination address field length is 2*N bytes, and N is set to 1 in the logical channel group bitmap.
  • the total number of bits; the size of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps in the destination address field.
  • the destination address fields are contiguous and the cache size fields are contiguous.
  • FIG. 6 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the destination address field is contiguous and the cache size field is contiguous.
  • the logical channel group includes one logical channel group bitmap, that is, a bitmap of eight logical channel groups of LCG0-LCG7, and the number of logical channel groups in which data can be transmitted is N, and the destination address domain
  • the total number of bits in the middle destination address bitmap is set to 1 and is m.
  • the logical channel group field has a length of 1 byte
  • a destination address bitmap occupies 2 bytes
  • the destination address field has a length of 2*N bytes
  • the cache size field has a length of m bytes, m. The total number of bits set to 1 in all destination address bitmaps in the destination address field.
  • the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain,
  • the destination address sub-domain is a destination address bitmap corresponding to a logical channel group, and the buffer size sub-domain is a pending data volume, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by the x caches.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient.
  • the Sidelink BSR's MAC CE contains the information of the Sidelink BSR after truncation.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is an index of at least one logically transferable logical channel group of the secondary link terminal device
  • the destination address field is at least one destination address bitmap, the at least one destination address bitmap is in one-to-one correspondence with the at least one logically channelizable logical channel group, and a destination address bitmap is used to indicate all destination addresses of the secondary link terminal device. Whether data is transmittable on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first logical channel group, and the first amount of data to be sent indicates the first of the first destination address of the secondary link terminal device.
  • the logical channel group index occupies 3 bits, and the total number of destination addresses is 16.
  • the corresponding amount of data to be sent on one logical channel group occupies 8 bits in the buffer size domain. Based on this, the length of each domain of the Sidelink BSR in several different scenarios will be described below.
  • the logical channel group domain is contiguous
  • the destination address domain is contiguous
  • the cache size domain is contiguous
  • FIG. 7 is a schematic diagram of a MAC CE of a Sidelink BSR according to still another embodiment of the present disclosure.
  • the logical channel group domain is contiguous
  • the destination address domain is contiguous
  • the cache size domain is contiguous.
  • the logical channel group domain includes an index of at least one logical channel group.
  • the length of the destination address field is 2*N bytes
  • the length of the buffer size field is m bytes
  • m is the total number of bits set to 1 in all destination address bitmaps in the destination address domain.
  • the length of the logical channel group domain is related to the number of bits occupied by one logical channel group index and the number N of indexes of the at least one logical channel group, specifically Ceiling (N*L/8), where L represents a logic The number of occupied bits of the channel group index, Ceiling (y) represents the smallest integer not less than y.
  • the logical channel group domain is continuous, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, and the cache size domain is discontinuous, and the cache size domain is And including at least one cache size sub-domain, where the destination address sub-domain is a destination address bitmap corresponding to a logical channel group, and one of the cache size sub-domains is a quantity of the to-be-sent data, and the at least one destination address sub-domain each of the destinations
  • the address subfield is followed by x cache size subfields, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to one.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the length of the destination address field is 2*N bytes
  • the length of the buffer size field is m bytes
  • m is the total number of bits set to 1 in all destination address bitmaps in the destination address domain.
  • the length of the logical channel group domain is related to the number of bits occupied by one logical channel group index and the number N of indexes of the at least one logical channel group, specifically Ceiling (N*L/8), where L represents a logic The number of occupied bits of the channel group index, Ceiling (y) represents the smallest integer not less than y.
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the destination address domain is discontinuous, and the destination address domain includes at least one destination address sub
  • the domain of the cache size is not continuous.
  • the cache size field includes at least one cache size sub-domain.
  • the logical channel group sub-domain is a logical channel group index, and the destination address sub-domain is a destination address bitmap corresponding to a logical channel group.
  • One of the cache size sub-domains is a quantity of the to-be-sent data, and each destination address sub-domain in the at least one destination address sub-domain is followed by x cache size sub-domains, and x is a destination of the following destination address sub-domain. The total number of bits in the address bitmap that are set to 1.
  • the value of x can be zero.
  • the value of x can be 0-16.
  • the length of the logical channel group domain is N bytes, and one destination address bitmap occupies 2 bytes.
  • the length of the address field is 2*N bytes, the length of the buffer size field is m bytes, and m is the total number of bits in the destination address bitmap of the destination address field being set to 1.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink of the secondary link terminal device If the resource is insufficient to upload the size of the entire Sidelink BSR, the MAC CE of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated.
  • the sub-header of the MAC CE of the Sidelink BSR may include an R domain, an F domain, an LCID domain, and an L domain, where
  • the length of the L field is 8 bits, and when the F field is 1, the length of the L field is 16 bits.
  • the LCID field is used to indicate that the MAC CE type following the subheader is a Sidelink BSR
  • the L field is used to indicate the byte length of the MAC CE of the Sidelink BSR.
  • the F-domain is set to "0", and the sub-header of the MAC CE of the Sidelink BSR is as shown in FIG. 8.
  • the sub-head of the MAC CE of the Sidelink BSR is as shown in FIG. 8.
  • the Buffer Size of valid data available for transmission can be more flexibly indicated by the bitmap-based per-point index and/or Per LCG ID's Sidelink BSR format for fast-growing V2X services.
  • the V2X service priority can be more clearly divided, the Buffer Size is expanded from 6 bits to 8 bits, and the corresponding index total class is increased from 64 to 256. This provides the network with a more granular and accurate Buffer Size information of the Sidelink UE.
  • the terminal device provided by the embodiment of the present disclosure can implement the processes implemented by the terminal device in the various embodiments of FIG. 1 and support the Sidelink BSR format provided in FIG. 2-7, and the MAC CE of the Sidelink BSR provided in FIG. 8 and FIG.
  • the subheader format, to avoid repetition, will not be described here.
  • the secondary link terminal device can report the cached data size on the corresponding destination address and the logical channel group to the base station.
  • the network device such as a base station, can receive the Sidelink BSR accordingly, and receive the cache data size sent by the secondary link terminal device on the destination address and logical channel group indicated by the Sidelink BSR.
  • FIG. 10 is a block diagram of a terminal device of another embodiment of the present disclosure.
  • the terminal device 1000 shown in FIG. 10 includes at least one processor 1001, a memory 1002, at least one network interface 1004, and a user interface 1003.
  • the various components in terminal device 1000 are coupled together by bus system 1005.
  • bus system 1005 is used to implement connection communication between these components.
  • the bus system 1005 includes a power bus, a control bus, and a status signal bus in addition to the data bus.
  • various buses are labeled as bus system 1005 in FIG.
  • the user interface 1003 may include a display, a keyboard, a pointing device (eg, a mouse, a trackball), a touch panel, or a touch screen.
  • a pointing device eg, a mouse, a trackball
  • a touch panel e.g., a touch screen.
  • the memory 1002 in the embodiments of the present disclosure may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be a read-only memory (ROM), a programmable read only memory (PROM), an erasable programmable read only memory (Erasable PROM, EPROM), or an electric Erase programmable read only memory (EEPROM) or flash memory.
  • the volatile memory can be a Random Access Memory (RAM) that acts as an external cache.
  • RAM Random Access Memory
  • many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (Synchronous DRAM).
  • SDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • DDRSDRAM Double Data Rate Synchronous Dynamic Random Access Memory
  • ESDRAM Enhanced Synchronous Dynamic Random Access Memory
  • SDRAM Synchronous Connection Dynamic Random Access Memory
  • DRRAM direct memory bus random access memory
  • the memory 1002 stores elements, executable modules or data structures, or a subset thereof, or their extended set: an operating system 10021 and an application 10022.
  • the operating system 10021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, for implementing various basic services and processing hardware-based tasks.
  • the application 10022 includes various applications, such as a media player (Media Player), a browser, and the like, for implementing various application services.
  • a program implementing the method of the embodiments of the present disclosure may be included in the application 10022.
  • the terminal device 1000 further includes: a computer program stored in the memory 1002 and executable on the processor 1001.
  • a computer program stored in the memory 1002 and executable on the processor 1001.
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the method disclosed in the above embodiments of the present disclosure may be applied to the processor 1001 or implemented by the processor 1001.
  • the processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the foregoing method may be completed by an integrated logic circuit of hardware in the processor 1001 or an instruction in a form of software.
  • the processor 1001 may be a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or the like. Programmable logic devices, discrete gates or transistor logic devices, discrete hardware components.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • the general purpose processor may be a microprocessor or the processor or any conventional processor or the like.
  • the steps of the method disclosed in connection with the embodiments of the present disclosure may be directly implemented by the hardware decoding processor, or may be performed by a combination of hardware and software modules in the decoding processor.
  • the software modules can be located in a conventional computer readable storage medium of the art, such as random access memory, flash memory, read only memory, programmable read only memory or electrically erasable programmable memory, registers, and the like.
  • the computer readable storage medium is located in the memory 1002, and the processor 1001 reads the information in the memory 1002 and performs the steps of the above method in combination with its hardware.
  • the computer readable storage medium stores a computer program, and when the computer program is executed by the processor 1001, the steps of the method embodiment shown in FIG. 1 are implemented.
  • the embodiments described in the embodiments of the present disclosure may be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof.
  • the processing unit can be implemented in one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processing (DSP), Digital Signal Processing Equipment (DSP Device, DSPD), programmable Programmable Logic Device (PLD), Field-Programmable Gate Array (FPGA), general purpose processor, controller, microcontroller, microprocessor, other for performing the functions described in this disclosure In an electronic unit or a combination thereof.
  • ASICs Application Specific Integrated Circuits
  • DSP Digital Signal Processing
  • DSP Device Digital Signal Processing Equipment
  • PLD programmable Programmable Logic Device
  • FPGA Field-Programmable Gate Array
  • the techniques described in the embodiments of the present disclosure may be implemented by modules (eg, procedures, functions, etc.) that perform the functions described in the embodiments of the present disclosure.
  • the software code can be stored in memory and executed by the processor.
  • the memory can be implemented in the processor or external to the processor.
  • the terminal device 1000 can implement various processes implemented by the terminal device in the foregoing embodiment. To avoid repetition, details are not described herein again.
  • the embodiment of the present disclosure further provides a computer readable storage medium, where the computer program is stored on a computer program, and when the computer program is executed by the processor, the processes of the foregoing method embodiment of FIG. 1 are implemented, and the same technology can be achieved. The effect, to avoid repetition, will not be repeated here.
  • the computer readable storage medium such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
  • the terminal device 1100 may include a transmitting module 1110. among them,
  • the sending module 1110 sends a secondary link buffer status report.
  • the sub-link cache status report includes a destination address field, a logical channel group domain, and a cache size domain, or includes a logical channel group domain and a cache size domain, where the destination address domain and the logical channel group domain are at least One is based on a bitmap.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is an index of at least one destination address reported by the secondary link terminal device, and the at least one destination address is a data transferable destination address of the secondary link terminal device;
  • the logical channel group domain is at least one logical channel group bitmap, the at least one logical channel group bitmap is in one-to-one correspondence with the at least one destination address, and one logical channel group bitmap is used to indicate whether all logical channel groups in the corresponding destination address are available. Pass data
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the first bit in the first logical channel group bitmap corresponding to the index of the first destination address, and the first amount of data to be sent indicates that the secondary link terminal device is a sum of the amount of data to be transmitted of all the logical channels of the first logical channel group of the first destination address, where the first logical channel group is a logical channel group corresponding to the first bit.
  • the destination address field is continuous
  • the logical channel group domain is continuous
  • the cache size domain is continuous
  • the destination address field is contiguous, the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain, and one
  • the logical channel group sub-domain is a logical channel group bitmap corresponding to a destination address
  • the buffer size sub-domain is the amount of the to-be-issued data
  • the at least one logical channel group sub-domain is followed by each of the logical channel group sub-domains. Following x cache size subfields, where x is the total number of bits set to 1 in a logical channel group bitmap of the following logical channel group subfield; or
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, the logical channel group domain is discontinuous, and the logical channel group domain includes at least one logical channel group sub-domain, the cache size domain is discontinuous, the cache The size field includes at least one cache size sub-domain, the destination address sub-domain is a destination address index, and one of the logical channel group sub-domains is a logical channel group bitmap corresponding to a destination address, and one of the cache size sub-domains is one Sending data volume, each logical channel group subfield in the at least one logical channel group subfield is followed by x cache size subfields, and x is a logical channel group subfield of the following logical channel group subfield is set to The total number of bits of 1;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the length of the index of the destination address is 4 bits, and the number of logical channels corresponding to the destination address is 8, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is 2*N- 1 byte
  • the length of the buffer size field is m bytes
  • m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain, wherein the first word of the destination address field
  • the first 4 bits of the section are reserved bits, or the last 4 bits of the last byte of the destination address field are reserved bits; or
  • the length of the destination address field is N bytes
  • the length of the logical channel group field is 2*N bytes.
  • the length of the buffer size field is m bytes, and m is the total number of bits in all logical channel group bitmaps of the logical channel group domain being set to 1; or
  • the cache The size of the size field is m bytes, where m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain, wherein each byte in the destination address field includes 4 reserved bits.
  • the Sidelink BSR includes: a destination address domain, a logical channel group domain, and a cache size domain, where
  • the destination address field is a destination address bitmap reported by the terminal device carrying the secondary link, and the destination address bitmap is used to indicate whether the destination address of the secondary link terminal device has data to be transmitted;
  • the logical channel group domain is at least one logical channel group bitmap, and the at least one logical channel group bitmap is in one-to-one correspondence with the destination address of the destination address bitmap bit set to 1, and one logical channel group bitmap is used to indicate the corresponding destination address. Whether all logical channel groups have data to transmit;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in a logical channel group bitmap of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the data volume corresponds to the second bit of the first logical channel group bitmap corresponding to the first bit of the destination address bitmap, and the first amount of data to be sent represents the secondary link terminal device.
  • the first destination address is a destination address indicated by a first bit of the destination address bitmap
  • the first logical channel group is The logical channel group indicated by the second bit of the first logical channel group bitmap.
  • the logical channel group domain is continuous, and the buffer size domain is continuous;
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, the cache size domain includes at least one cache size subdomain, and one logical channel group subdomain is one a logical channel group bitmap corresponding to the destination address, where the buffer size sub-domain is the amount of data to be sent, and each of the logical channel group sub-domains in the at least one logical channel group sub-domain is followed by the x cache size sub-domains.
  • x is the total number of bits set to 1 in a logical channel group bitmap of the followed logical channel group subfield;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the length of the index of the destination address is 4 bits, and the number of logical channels corresponding to the destination address is 8, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the destination address field has a length of 2 bytes.
  • the length of the logical channel group field is N bytes, and N is the total number of bits in the destination address bitmap set to 1.
  • the length of the buffer size field is m bytes, and m is the total number of bits in the bitmap of all logical channel groups in the logical channel group domain.
  • the Sidelink BSR includes a logical channel group domain and a cache size domain.
  • the logical channel group domain is a logical channel group bitmap corresponding to the size of v2x-DestinationInfoList destination addresses of the secondary link terminal device, and one logical channel group bitmap is used to indicate whether all logical channel groups of the corresponding destination address have data transferable. ;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in all logical channel group bitmaps of the logical channel group domain, wherein if the at least one to wait
  • the first amount of data to be sent in the amount of data to be transmitted corresponds to the first bit of the first logical channel group bitmap
  • the first logical channel group bitmap corresponds to the first destination address
  • the first amount of data to be sent represents the pair.
  • the logical channel group domain is continuous, and the buffer size domain is continuous;
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the cache size domain is discontinuous, the cache size domain includes at least one cache size subdomain, and one logical channel group subdomain is one a logical channel group bitmap corresponding to the destination address, where the buffer size sub-domain is the amount of data to be sent, and each of the logical channel group sub-domains in the at least one logical channel group sub-domain is followed by the x cache size sub-domains.
  • x is the total number of bits set to 1 in a logical channel group bitmap of the followed logical channel group subfield;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • a logical channel group corresponding to the destination address is eight, and one amount of the to-be-sent data occupies 8 bits in the buffer size domain, where
  • the number of bytes occupied by the logical channel group domain is the same as the size of v2x-DestinationInfoList parameter;
  • the length of the buffer size field is m bytes, and m is the total number of logical channel groups in which the bits in all logical channel group bitmaps of the logical channel group domain are set to 1.
  • the parameter size of v2x-DestinationInfoList is configured by the radio resource control RRC, or is specified by the protocol.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is a logical channel group bitmap, and the one logical channel group bitmap is used to indicate whether the secondary link terminal device has data to be transmitted in all logical channel groups;
  • the destination address field is at least one destination address bitmap, and the at least one destination address bitmap is in one-to-one correspondence with a logical channel group in which the bit in the logical channel group bitmap is set to 1, and a destination address bitmap is used to indicate the secondary link terminal. Whether all destination addresses of the device have data to be transmitted on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first bit of the logical channel group address bitmap, and the first amount of data to be sent indicates that the secondary link terminal device is in the first purpose.
  • the destination address field is contiguous and the cache size domain is contiguous;
  • the destination address field is discontinuous, the destination address field includes at least one destination address sub-domain, and the cache size domain is discontinuous, and the cache size domain includes at least one cache size sub-domain, where the destination address sub-domain corresponds to a logical channel group.
  • a destination address bitmap wherein the buffer size sub-domain is an amount of the to-be-sent data, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by x cache size sub-domains, where x is the followed destination address.
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the total number of logical channel groups is eight, and the total number of destination addresses is 16, and one amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the logical channel group domain has a length of 1 byte
  • the one destination address bitmap occupies 2 bytes
  • the destination address field is 2*N bytes in length, and N is the total number of bits set to 1 in the logical channel group bitmap;
  • the buffer size field has a length of m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field.
  • the Sidelink BSR includes: a logical channel group domain, a destination address domain, and a cache size domain, where
  • the logical channel group domain is an index of at least one logically transferable logical channel group of the secondary link terminal device
  • the destination address field is at least one destination address bitmap, the at least one destination address bitmap is in one-to-one correspondence with the at least one logically channelizable logical channel group, and a destination address bitmap is used to indicate all destination addresses of the secondary link terminal device. Whether data is transmittable on the logical channel group corresponding to the destination address bitmap;
  • the buffer size field is at least one amount of data to be sent, and the at least one amount of data to be sent corresponds to a bit set to 1 in the at least one destination address bitmap, wherein if the at least one amount of data to be sent is in the
  • the first amount of data to be sent corresponds to the second bit of the first destination address bitmap corresponding to the first logical channel group, and the first amount of data to be sent indicates the first of the first destination address of the secondary link terminal device.
  • the logical channel group domain is continuous, the destination address domain is continuous, and the cache size domain is continuous;
  • the logical channel group domain is contiguous, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, the cache size domain is discontinuous, and the cache size domain includes at least one cache size subdomain, the destination address
  • the sub-domain is a destination address bitmap corresponding to a logical channel group, and the buffer size sub-domain is a data volume to be sent, and each of the destination address sub-domains in the at least one destination address sub-domain is followed by x cache sizes. Domain, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to 1; or
  • the logical channel group domain is discontinuous, the logical channel group domain includes at least one logical channel group subdomain, the destination address domain is discontinuous, the destination address domain includes at least one destination address subdomain, and the cache size domain is discontinuous, the cache The size field includes at least one cache size subdomain.
  • the logical channel group sub-domain is a logical channel group index
  • the destination address sub-domain is a destination address bitmap corresponding to a logical channel group
  • the buffer size sub-domain is a pending data volume
  • the at least one destination address sub-domain Each destination address subfield is followed by x cache size subfields, where x is the total number of bits in the destination address bitmap of the followed destination address subfield set to 1;
  • the MAC CE of the Sidelink BSR includes the information of the entire Sidelink BSR; if the uplink resource of the secondary link terminal device is insufficient to upload the entire
  • the size of the Sidelink BSR includes the information of the Sidelink BSR that has been truncated in the MAC CE of the Sidelink BSR.
  • the total number of destination addresses is 16, and the amount of data to be sent occupies 8 bits in the buffer size domain, where
  • the length of the logical channel group domain is related to the number N of indexes of the at least one logical channel group, and the length of the destination address domain is 2*N bytes, and the one destination address bitmap is occupied. 2 bytes, the length of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field; or
  • the logical channel group domain When the logical channel group domain is discontinuous, and the number of indexes of the at least one logical channel group is N, the logical channel group domain has a length of N bytes, and the destination address domain has a length of 2*N.
  • the length of the buffer size field is m bytes, and m is the total number of bits set to 1 in all destination address bitmaps of the destination address field.
  • the sub-header of the MAC CE of the Sidelink BSR includes an R domain, an F domain, an LCID domain, and an L domain, where
  • the length of the L field is 8 bits, and when the F field is 1, the length of the L field is 16 bits.
  • the LCID field is used to indicate that the MAC CE type following the subheader is a Sidelink BSR
  • the L field is used to indicate the byte length of the MAC CE of the Sidelink BSR.
  • the terminal device 1100 can implement various processes implemented by the terminal device in the foregoing embodiment. To avoid repetition, details are not described herein again.

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Abstract

本公开提供了一种副链路缓存状态报告的传输方法和副链路终端设备，包括：发送副链路缓存状态报告，副链路缓存状态报告中包括：目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，其中，目的地址域和该逻辑信道组域中至少一个是基于比特图表示的。

Description

副链路缓存状态报告的上报方法和终端设备
相关申请的交叉引用
本申请主张在2018年3月29日在中国提交的中国专利申请号No.201810273355.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及通信领域，尤其涉及一种副链路缓存状态报告的上报方法和终端设备。
背景技术
副链路缓存状态报告(Sidelink Buffer Status Report，Sidelink BSR)的作用是Sidelink UE告诉基站基于近距离服务目的地址(ProSe Destination)的一个逻辑信道组内所有逻辑信道待发的数据量(以字节为单位)。
LTE Sidelink BSR的格式是按照逻辑信道组索引(Logical Channel Group Identity，LCG ID)顺序排列，当没有足够的资源上报资源需求情况，对于相同的LCG ID，可能上报一个或多个destination index相应的待传数据量。对于快速增长的车联网(Vehicle to Everything，V2X)业务和用例，业务优先级划分也需要更加细致，LTE Sidelink BSR的逻辑信道组(Logical Channel Group，LCG)组数只有4组，不能满足当前的要求；LTE Sidelink的Buffer Size域占6比特，总共的index就64种，种类少，而增强型车联网(enhanced V2X，eV2X)业务类型急剧增加需要更大的数据量，如果还沿用LTE的64种index，eV2X每个级别指示的Buffer Size跨度就大，基站并不能精确的确认Sidelink UE对资源的需求，在资源调度过程中会造成一定程度的资源浪费。此外目前协议对于新空口(New Radio，NR)的Sidelink BSR格式也尚未作出定义。
发明内容
本公开实施例的目的是提供一种副链路缓存状态报告的传输方法、终端设备，能够更加灵活指示基于近距离服务目的地址的一个逻辑信道组内所有 逻辑信道可用于传输的有效数据的Buffer Size。
第一方面，本公开实施例提供了一种副链路缓存状态报告的传输方法，该方法包括：发送副链路缓存状态报告，该副链路缓存状态报告中包括：目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，
其中，该目的地址域和该逻辑信道组域中的至少一个是基于比特图表示的。
第二方面，本公开实施例提供了一种终端设备，该终端设备包括：发送模块，发送副链路缓存状态报告，该副链路缓存状态报告中包括：目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，
其中，该目的地址域和该逻辑信道组域中的至少一个是基于比特图表示的。
第三方面，本公开实施例提供了一种终端设备，该终端设备包括处理器、存储器及存储在所述存储器上并可在所述处理器上运行的程序，所述程序被所述处理器执行时实现如第一方面所述的方法的步骤。
第四方面，本公开实施例提供了一种计算机可读存储介质，所述计算机可读存储介质上存储程序，所述程序被处理器执行时实现如第一方面所述的方法的步骤。
在本公开实施例中，通过基于bitmap设计的per destination index和/或per LCG ID的Sidelink BSR格式，从而能够更加灵活指示基于近距离服务目的地址的一个逻辑信道组内所有逻辑信道可用于传输的有效数据的Buffer Size。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1是本公开的一个实施例Sidelink BSR的发送方法流程图。
图2是本公开的一个实施例Sidelink BSR的MAC CE的示意图。
图3是本公开的另一个实施例Sidelink BSR的MAC CE的示意图。
图4是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。
图5是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。
图6是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。
图7是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。
图8是本公开的再一个实施例Sidelink BSR的MAC CE的子头的示意图。
图9是本公开的另一个实施例Sidelink BSR的MAC CE的子头的示意图。
图10是本公开的一个实施例终端设备的结构示意图。
图11是本公开的另一个实施例终端设备的结构示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
本公开的技术方案，可以应用于各种通信***，例如：全球移动通讯***(Global System of Mobile communication，GSM)，码分多址(Code Division Multiple Access，CDMA)***，宽带码分多址(Wideband Code Division Multiple Access，WCDMA)，通用分组无线业务(General Packet Radio Service，GPRS)，长期演进(Long Term Evolution，LTE)/增强长期演进(Long Term Evolution advanced，LTE-A)，新空口(New Radio，NR)等。
用户端(User Equipment，UE)，也可称之为终端设备(Mobile Terminal)、移动用户设备等，可以经无线接入网(例如，无线接入网(Radio Access Network，RAN))与一个或多个核心网进行通信，用户设备可以是终端设备，如移动电话(或称为“蜂窝”电话)和具有终端设备的计算机，例如，可以是便携式、袖珍式、手持式、计算机内置的或者车载的移动装置，它们与无线接入网交换语言和/或数据。
基站，可以是GSM或CDMA中的基站(Base Transceiver Station，BTS)，也可以是WCDMA中的基站(NodeB)，还可以是LTE中的演进型基站(evolutional Node B，eNB或e-NodeB)及5G基站(gNB)，本公开并不限 定，但为描述方便，下述实施例以gNB为例进行说明。
以下结合附图，详细说明本公开各实施例提供的技术方案。
R14及以前的Sidelink BSR是按照每个目的地址索引(Destination Index)+每个逻辑信道组索引(LCG ID)+待传数据量(Buffer Size Level)上报。其中，
Sidelink BSR的LCG(逻辑信道组)最多被分为4组，一个逻辑信道组索引的字段占2比特，指定上报的(缓存区域)对应的LCG(逻辑信道组)。
Destination Index长度可配置，最多有16个组，一个目的地址索引的字段占4比特，对应到通信的目标群组destination L2ID。
Buffer Size是以逻辑信道组包含副链路逻辑信道优先级递减的顺序排列。Buffer Size域长为6比特，指定了Sidelink UE在发送这个BSR的传输时间间隔(Transmission Time Interval，TTI)内的所有媒体访问控制层(Media Access Control，MAC)MAC协议数据单元(Protocol Data Unit，PDU)都生成以后，对应近距离服务目的地址的LCG包含所有逻辑信道的无线链路层控制协议(Radio Link Control，RLC)层和分组数据汇聚协议(Packet Data Convergence Protocol，PDCP)层中剩余的可用于传输的有效数据总和。
图1是本公开的一个实施例副链路缓存状态报告(Sidelink Buffer Status Report，Sidelink BSR)的发送方法流程图。图1的方法由副链路终端设备执行。该方法可包括：
S110，发送副链路缓存状态报告。
其中，该副链路缓存状态报告中包括目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，其中，该目的地址域和该逻辑信道组域中的至少一个是基于比特图表示的。
应理解，Sidelink BSR的作用是：Sidelink UE将基于近距离服务目的地址(ProSe Destination)的一个逻辑信道组内所有逻辑信道的待发数据量，发送给基站。
其中，目的地址域为携带有副链路终端设备的目的地址信息的字段域，或者说，目的地址域为副链路终端设备的目的地址信息；
逻辑信道组域为携带有副链路终端设备的逻辑信道组信息的字段域，或者说，逻辑信道组域为副链路终端设备的逻辑信道组信息；
缓存大小域为携带有所述副链路终端设备的逻辑信道组的待发数据量信息的字段域，或者说，缓存大小域为副链路终端设备的逻辑信道组的待发数据量。
本公开实施例中，通过基于bitmap设计的per destination index和/或per LCG ID的Sidelink BSR格式，能够更加灵活指示基于近距离服务目的地址(ProSe Destination)的一个逻辑信道组内所有逻辑信道待发可用于传输的有效数据的Buffer Size。
下面，将对Sidelink BSR具体可能的实现方式，逐个进行说明。
可选地，在一些实施例中，该Sidelink BSR包括：目的地址域、逻辑信道组域和缓存大小域，其中，
该目的地址域为该副链路终端设备上报的至少一个目的地址的索引，该至少一个目的地址为该副链路终端设备的有数据可传的目的地址；
该逻辑信道组域为至少一个逻辑信道组bitmap，该至少一个逻辑信道组bitmap与该至少一个目的地址一一对应，一个逻辑信道组bitmap用于指示对应的目的地址中所有逻辑信道组是否有可传数据；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的所有逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一目的地址的索引对应的第一逻辑信道组bitmap中的第一比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一逻辑信道组为该第一比特位对应的逻辑信道组。
应理解，在统计待发数据量时，包括RLC和PDCP层剩余待传数据，但不将RLC头部和MAC头部信息计算在内。后续实施例提到的待发数据量与此类似，不再赘述。
应理解，在这些实施例中，目的地址索引用于指示副链路终端设备的有数据可传的目的地址。
应理解，每一个目的地址索引在逻辑信道组域中对应于一个逻辑信道组bitmap，该逻辑信道组bitmap指示该目的地址对应的所有逻辑信道组是否有可传数据。例如，当一个目的地址对应的逻辑信道组为8个时，该逻辑信道 组bitmap指示该目的地址对应的逻辑信道组LCG0-LCG7是否有可传数据。
进一步地，在这些实施例中，该Sidelink BSR依次包括：目的地址域、逻辑信道组域和缓存大小域，且该目的地址域是连续的，该逻辑信道组域是连续的，该缓存大小域是连续的。
可选地，在一些实施例中，一个目的地址索引占用4个比特，一个目的地址对应8个逻辑信道组(LCG0-LCG7)，且一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。
图2是本公开的一个实施例Sidelink BSR的媒体访问控制控制元素(Media Access Control Control Element，MAC CE)的示意图。图2中，目的地址域连续，逻辑信道组域连续，缓存大小域连续，且目的地址索引的个数为奇数，不妨设为2*N-1个，则在上述可选的实施例中，目的地址域的长度为Ceiling((2*N-1)*4/8)＝N个字节，逻辑信道组域的长度为2*N-1个字节，缓存大小域的长度为m个字节，其中，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
从图2还可提看出，目的地址域的第一个字节的前4个比特为保留比特。当然，应理解，保留比特也可以位于目的地址域的最后一个字节的后4个比特。此外，也不排除保留比特位于目的地址域中的其它任意一个字节的前4个比特或后4个比特。
图3是本公开的一个实施例Sidelink BSR的MAC CE的示意图。图3中，目的地址域连续，逻辑信道组域连续，缓存大小域连续，且目的地址索引的个数为偶数，不妨设为2*N个，则在上述可选的实施例中，目的地址域的长度为N个字节，逻辑信道组域的长度为2*N个字节，缓存大小域的长度为m个字节，其中，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
或者，进一步地，在这些实施例中，该目的地址域是连续的，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后 跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，当一个目的地址对应的逻辑信道组为8个时，x的取值可以为0-8。
可选地，一个目的地址索引占用4个比特，一个目的地址对应8个逻辑信道组(LCG0-LCG7)，且一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。
如果目的地址索引的个数为奇数，不妨设为2*N-1个，则在上述可选的实施例中，目的地址域的长度为N个字节，逻辑信道组域的长度为2*N-1个字节，缓存大小域的长度为m个字节，其中，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
此外，目的地址域的第一个字节的前4个比特为保留比特，或者，目的地址域的最后一个字节的后4个比特为保留比特。当然，也不排除保留比特位于目的地址域中的其它任意一个字节的前4个比特或后4个比特。
如果目的地址索引的个数为偶数，不妨设为2*N个，则在上述可选的实施例中，目的地址域的长度为N个字节，逻辑信道组域的长度为2*N个字节，缓存大小域的长度为m个字节，其中，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
或者，进一步地，在这些实施例中，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子域为一个目的地址索引，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，当一个目的地址对应的逻辑信道组为8个时，x的取值可以为0-8。
可选地，一个目的地址索引占用4个比特，一个目的地址对应8个逻辑 信道组(LCG0-LCG7)，且一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。
在上述可选的实施例中，该目的地址域的长度为N个字节，该逻辑信道组域的长度为N个字节，该缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数，其中，该目的地址域中每个字节包括4个保留比特。
当然，应理解，Sidelink BSR的目的地址索引的长度可能不是4比特，一个目的地址对应的逻辑信道组也可能不是8个，一个待发数据量占用的比特数也可能不是8个。本领域的技术人员可以基于实际情况推导出前述场景中Sidelink BSR的各个域的长度。
此外，应理解，在前述实施例中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
可选地，在一些实施例中，该Sidelink BSR包括：目的地址域、逻辑信道组域和缓存大小域，其中，
该目的地址域为携带该副链路终端设备上报的目的地址bitmap，该目的地址bitmap用于指示副链路终端设备的目的地址是否有数据可传；
该逻辑信道组域为至少一个逻辑信道组bitmap，该至少一个逻辑信道组bitmap与该目的地址bitmap比特位被置为1的目的地址一一对应，一个逻辑信道组bitmap用于指示对应的目的地址的所有逻辑信道组是否有可传数据；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的一个逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于目的地址bitmap的第一比特位对应的第一逻辑信道组bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一目的地址为该目的地址bitmap的第一比特位指示的目的地址，该第一逻辑信道组为该第一逻辑信道组bitmap的第二比特位指示 的逻辑信道组。
应理解，目的地址bitmap中每个被置为1的比特位对应于1个逻辑信道组bitmap，该逻辑信道组bitmap指示该被置为1的比特位对应的目的地址所对应的所有逻辑信道组是否有可传数据。例如，当第一目的地址在目的地址bitmap中对应的比特位被置为1，且该第一目的地址对应于第一逻辑信道组bitmap，且一个目的地址对应的逻辑信道组为8个时，则第一逻辑信道组bitmap指示第一目的地址对应的逻辑信道组LCG0-LCG7是否有可传数据。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该缓存大小域是连续的。
可选地，目的地址总数为16个，一个目的地址对应8个逻辑信道组(LCG0-LCG7)，且一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。下面将基于此，对Sidelink BSR各个域在几种不同场景中的长度进行说明。
图4是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。图4中，目的地址域连续，逻辑信道组域连续，缓存大小域连续，并假设可以用2个字节指示副链路终端设备的目的地址是否有数据可传，且其中有数据可传的目的地址个数为N，逻辑信道组域的逻辑信道组bitmap中比特位被置为1的总数为m。
由图4可知，目的地址域的长度为2个字节，逻辑信道组域的长度为N个字节，N为目的地址域的目的地址bitmap中比特位被置为1的总数；缓存大小域的长度为m个字节，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
或者，进一步地，在这些实施例中，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，当一个目的地址对应的逻辑信道组为8个时，x的取值可以为0-8。
此时，目的地址域的长度为2个字节，逻辑信道组域的长度为N个字节，N为目的地址域的目的地址bitmap中比特位被置为1的总数；缓存大小域的长度为m个字节，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
当然，应理解，目的地址总数可能不是16个4，一个目的地址对应的逻辑信道组也可能不是8个，一个待发数据量占用的比特数也可能不是8个。本领域的技术人员可以基于实际情况推导出前述场景中Sidelink BSR的各个域的长度。
此外，应理解，在前述实施例中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
可选地，在一些实施例中，该Sidelink BSR中包括逻辑信道组域和缓存大小域，其中，
该逻辑信道组域为该副链路终端设备的size of v2x-DestinationInfoList个目的地址对应的逻辑信道组bitmap，一个逻辑信道组bitmap用于指示对应的目的地址的所有逻辑信道组是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的所有逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组bitmap的第一比特位，且第一逻辑信道组bitmap对应于第一目的地址，则该第一待发数据量表示该副链路终端设备在该第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一逻辑信道组为该第一逻辑信道组bitmap的第一比特位指示的逻辑信道组。
应理解，参数size of v2x-DestinationInfoList可以是协议规定的，或者是通过无线资源控制协议(Radio Resource Control，RRC)配置的。
例如，协议可以规定在16个目的地址中使用索引1、3、5、7的目的地址；又例如，可以通过RRC信令配置使用16个目的地址中的前6个目的地址，等等。
应理解，在这些实施例中，逻辑信道组域占用的字节个数与参数size of v2x-DestinationInfoList值相同；缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的逻辑信道组的总数。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该缓存大小域是连续的。
图5是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。图5中，逻辑信道组域连续，缓存大小域连续。
如图5所示，逻辑信道组域中包括size of v2x-DestinationInfoList个连续的逻辑信道组bitmap，每个逻辑信道组bitmap对应于一个目的地址，每个逻辑信道组bitmap占据1个字节。缓存大小域的长度为m个字节，m为逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数。
或者，进一步地，在这些实施例中，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，当一个目的地址对应的逻辑信道组为8个时，x的取值可以为0-8。
当然，应理解，一个目的地址对应的逻辑信道组也可能不是8个，一个待发数据量占用的比特数也可能不是8个。本领域的技术人员可以基于实际情况推导出前述场景中Sidelink BSR的各个域的长度。
此外，应理解，在前述实施例中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个 Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
可选地，在一些实施例中，该Sidelink BSR中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
该逻辑信道组域为一个逻辑信道组bitmap，该一个逻辑信道组bitmap用于指示该副链路终端设备在所有逻辑信道组是否有数据可传；
该目的地址域为至少一个目的地址bitmap，该至少一个目的地址bitmap与该逻辑信道组bitmap中比特位被置为1的逻辑信道组一一对应，一个目的地址bitmap用于指示该副链路终端设备的所有目的地址在该目的地址bitmap对应的逻辑信道组上是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该至少一个目的地址bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于逻辑信道组地址bitmap的第一比特位对应的第一目的地址bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组所有逻辑信道的待发数据量的总和，该第一目的地址为第一目的地址bitmap的第二比特位指示的目的地址，该第一逻辑信道组为该逻辑信道组地址bitmap的第一比特位指示的逻辑信道组。
可选地，逻辑信道组总数为8个、目的地址总数16个、一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。此时，该逻辑信道组域长度为1个字节；一个目的地址bitmap占用2字节，该目的地址域长度为2*N个字节，N为该逻辑信道组bitmap中被置为1的比特的总数；该缓存大小域长度为m个字节，m为该目的地址域中的所有目的地址bitmap中被置为1的比特的总数。
进一步地，在这些实施例中，目的地址域是连续的，且缓存大小域是连续的。
图6是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。图6中，目的地址域是连续的，且缓存大小域是连续的。
如图6所示，逻辑信道组域中包括1个逻辑信道组bitmap，即LCG0-LCG7 共8个逻辑信道组的bitmap，且其中有数据可传的逻辑信道组个数为N，目的地址域中目的地址bitmap的比特位被置为1的总数为m。
由图6可知，逻辑信道组域的长度为1字节，一个目的地址bitmap占用2字节，目的地址域的长度为2*N个字节，缓存大小域的长度为m个字节，m为该目的地址域中的所有目的地址bitmap中被置为1的比特的总数。
或者，进一步地，在这些实施例中，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个该目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，当目的地址总数为16个时，x的取值可以为0-16。
当然，应理解，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息
可选地，在一些实施例中，该Sidelink BSR中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
该逻辑信道组域为该副链路终端设备的至少一个有数据可传的逻辑信道组的索引；
该目的地址域为至少一个目的地址bitmap，该至少一个目的地址bitmap与该至少一个有数据可传的逻辑信道组一一对应，一个目的地址bitmap用于指示该副链路终端设备的所有目的地址在该目的地址bitmap对应的逻辑信道组上是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该至少一个目的地址bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组对应的第一目的地址bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目 的地址的该第一逻辑信道组上所有逻辑信道的待发数据量的总和，该第一目的地址为第一逻辑信道组对应的第一目的地址bitmap的第二比特位所指示的目的地址。。
可选地，逻辑信道组索引占用3比特、目的地址总数16个，一个逻辑信道组上对应的待发数据量在缓存大小域中占用8个比特。下面基于此，对Sidelink BSR各个域在几种不同场景中的长度进行说明。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该目的地址域是连续的，该缓存大小域是连续的。
图7是本公开的再一个实施例Sidelink BSR的MAC CE的示意图。图7中，逻辑信道组域是连续的，目的地址域是连续的，且缓存大小域是连续的。
如图7所示，逻辑信道组域中包括至少一个逻辑信道组的索引。当然，逻辑信道组域中还可能存在保留比特。不妨假设该至少一个逻辑信道组的索引个数为N，目的地址域的目的地址bitmap中比特位被置为1的总数为m。
由图7可知，目的地址域的长度为2*N个字节，缓存大小域的长度为m个字节，m为该目的地址域中的所有目的地址bitmap中被置为1的比特的总数。
逻辑信道组域的长度与一个逻辑信道组索引占用的比特数及所述至少一个逻辑信道组的索引的个数N相关，具体可为Ceiling(N*L/8)，其中，L表示一个逻辑信道组索引的占用的比特数，Ceiling(y)表示不小于y的最小整数。
或者，进一步地，在这些实施例中，该逻辑信道组域是连续的，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个该目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，目的地址总数为16个时，x的取值可以为0-16。
此时，目的地址域的长度为2*N个字节，缓存大小域的长度为m个字节， m为该目的地址域中的所有目的地址bitmap中被置为1的比特的总数。逻辑信道组域的长度与一个逻辑信道组索引占用的比特数及所述至少一个逻辑信道组的索引的个数N相关，具体可为Ceiling(N*L/8)，其中，L表示一个逻辑信道组索引的占用的比特数，Ceiling(y)表示不小于y的最小整数。
或者，进一步地，在这些实施例中，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该逻辑信道组子域为一个逻辑信道组索引，该目的地址子域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数。
应理解，x的取值可以为0。例如，目的地址总数为16个时，x的取值可以为0-16。
当该逻辑信道组域不连续，且该至少一个逻辑信道组的索引的个数为N个，则该逻辑信道组域的长度为N个字节，一个目的地址bitmap占用2字节，该目的地址域的长度为2*N个字节，该缓存大小域的长度为m个字节，m为该目的地址域的目的地址bitmap中比特位被置为1的总数。
当然，应理解，其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
可选地，对于前述实施例的Sidelink BSR来说，该Sidelink BSR的MAC CE的子头可包括R域、F域、LCID域和L域，其中，
F域为0时表示L域长度为8比特，F域为1时表示L域长度为16比特；
LCID域用于指示跟随该子头的MAC CE类型为Sidelink BSR；
L域用于指示该Sidelink BSR的MAC CE的字节长度。
具体的，F域置为“0”，该Sidelink BSR的MAC CE的子头如图8所示， 该域置为“1”时，该Sidelink BSR的MAC CE的子头如图9所示。
本公开实施例中，通过对于快速增长的V2X业务，通过基于bitmap设计的per destination index和/或per LCG ID的Sidelink BSR格式能够更加灵活的指示可用于传输的有效数据的Buffer Size。
此外，当新设计的Sidelink BSR将逻辑信道组拓展为8，能将V2X业务优先级划分的更加清楚，Buffer Size由6比特拓展为8比特，相应的index总类由64增加到256种，以此给网络提供粒度更细、精度更高的Sidelink UE的Buffer Size信息。
本公开实施例提供的终端设备能够实现图1的各个实施例中终端设备实现的各个过程，并支持图2-7提供的Sidelink BSR格式，以及图8、图9提供的Sidelink BSR的MAC CE的子头格式，为避免重复，这里不再赘述。
当然，应理解，副链路终端设备在上报Sidelink BSR之后，即可将相应的目的地址和逻辑信道组上的缓存数据大小上报给基站。
相应地，网络设备如基站等，可相应地接收Sidelink BSR，并在Sidelink BSR指示的目的地址和逻辑信道组上接收副链路终端设备发送的缓存数据大小。
图10是本公开另一个实施例的终端设备的框图。图10所示的终端设备1000包括：至少一个处理器1001、存储器1002、至少一个网络接口1004和用户接口1003。终端设备1000中的各个组件通过总线***1005耦合在一起。可理解，总线***1005用于实现这些组件之间的连接通信。总线***1005除包括数据总线之外，还包括电源总线、控制总线和状态信号总线。但是为了清楚说明起见，在图10中将各种总线都标为总线***1005。
其中，用户接口1003可以包括显示器、键盘、点击设备(例如，鼠标、轨迹球(trackball))、触感板或者触摸屏等。
可以理解，本公开实施例中的存储器1002可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(Read-Only Memory，ROM)、可编程只读存储器(Programmable ROM，PROM)、可擦除可编程只读存储器(Erasable PROM，EPROM)、电可擦除可编程只读存储器(Electrically EPROM，EEPROM)或闪 存。易失性存储器可以是随机存取存储器(Random Access Memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用，例如静态随机存取存储器(Static RAM，SRAM)、动态随机存取存储器(Dynamic RAM，DRAM)、同步动态随机存取存储器(Synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(Double Data Rate SDRAM，DDRSDRAM)、增强型同步动态随机存取存储器(Enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(Synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(Direct Rambus RAM，DRRAM)。本公开实施例描述的***和方法的存储器1002旨在包括但不限于这些和任意其它适合类型的存储器。
在一些实施方式中，存储器1002存储了如下的元素，可执行模块或者数据结构，或者他们的子集，或者他们的扩展集：操作***10021和应用程序10022。
其中，操作***10021，包含各种***程序，例如框架层、核心库层、驱动层等，用于实现各种基础业务以及处理基于硬件的任务。应用程序10022，包含各种应用程序，例如媒体播放器(Media Player)、浏览器(Browser)等，用于实现各种应用业务。实现本公开实施例方法的程序可以包含在应用程序10022中。
在本公开实施例中，终端设备1000还包括：存储在存储器1002并可在处理器1001上运行的计算机程序，计算机程序被处理器1001执行时实现如下步骤：
发送副链路缓存状态报告；
其中，该副链路缓存状态报告中包括目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，其中，该目的地址域和该逻辑信道组域中的至少一个是基于比特图表示的。
上述本公开实施例揭示的方法可以应用于处理器1001中，或者由处理器1001实现。处理器1001可能是一种集成电路芯片，具有信号的处理能力。在实现过程中，上述方法的各步骤可以通过处理器1001中的硬件的集成逻辑电路或者软件形式的指令完成。上述的处理器1001可以是通用处理器、数字 信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件。可以实现或者执行本公开实施例中的公开的各方法、步骤及逻辑框图。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。结合本公开实施例所公开的方法的步骤可以直接体现为硬件译码处理器执行完成，或者用译码处理器中的硬件及软件模块组合执行完成。软件模块可以位于随机存储器，闪存、只读存储器，可编程只读存储器或者电可擦写可编程存储器、寄存器等本领域成熟的计算机可读存储介质中。该计算机可读存储介质位于存储器1002，处理器1001读取存储器1002中的信息，结合其硬件完成上述方法的步骤。具体地，该计算机可读存储介质上存储有计算机程序，计算机程序被处理器1001执行时实现如上述图1所示方法实施例的各步骤。
可以理解的是，本公开实施例描述的这些实施例可以用硬件、软件、固件、中间件、微码或其组合来实现。对于硬件实现，处理单元可以实现在一个或多个专用集成电路(Application Specific Integrated Circuits，ASIC)、数字信号处理器(Digital Signal Processing，DSP)、数字信号处理设备(DSP Device，DSPD)、可编程逻辑设备(Programmable Logic Device，PLD)、现场可编程门阵列(Field-Programmable Gate Array，FPGA)、通用处理器、控制器、微控制器、微处理器、用于执行本公开所述功能的其它电子单元或其组合中。
对于软件实现，可通过执行本公开实施例所述功能的模块(例如过程、函数等)来实现本公开实施例所述的技术。软件代码可存储在存储器中并通过处理器执行。存储器可以在处理器中或在处理器外部实现。
终端设备1000能够实现前述实施例中终端设备实现的各个过程，为避免重复，这里不再赘述。
本公开实施例还提供一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，该计算机程序被处理器执行时实现上述图1方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。其中，所述的计算机可读存储介质，如只读存储器(Read-Only Memory，简称ROM)、随机存取存储器(Random Access Memory，简称RAM)、磁碟或者光盘等。
图11是本公开的另一个实施例终端设备的结构示意图。如图11所示，终端设备1100可包括发送模块1110。其中，
发送模块1110，发送副链路缓存状态报告。
其中，该副链路缓存状态报告中包括目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，其中，该目的地址域和该逻辑信道组域中的至少一个是基于比特图表示的。
可选的，在一些实施例中，该Sidelink BSR包括：目的地址域、逻辑信道组域和缓存大小域，其中，
该目的地址域为该副链路终端设备上报的至少一个目的地址的索引，该至少一个目的地址为该副链路终端设备的有数据可传的目的地址；
该逻辑信道组域为至少一个逻辑信道组bitmap，该至少一个逻辑信道组bitmap与该至少一个目的地址一一对应，一个逻辑信道组bitmap用于指示对应的目的地址中所有逻辑信道组是否有可传数据；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的所有逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一目的地址的索引对应的第一逻辑信道组bitmap中的第一比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一逻辑信道组为该第一比特位对应的逻辑信道组。
进一步地，在这些实施例中，该目的地址域是连续的，该逻辑信道组域是连续的，该缓存大小域是连续的；或者
该目的地址域是连续的，该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数；或者
该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该逻 辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子域为一个目的地址索引，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数；
其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
更进一步地，一个该目的地址的索引的长度为4比特，一个该目的地址对应的逻辑信道组为8个，一个该待发数据量在该缓存大小域中占用8比特，其中，
当该目的地址域连续，且该至少一个目的地址索引的个数为2*N-1个，则该目的地址域的长度为N个字节，该逻辑信道组域的长度为2*N-1个字节，该缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数，其中，该目的地址域第一个字节的前4个比特为保留比特，或该目的地址域的最后一个字节的后4个比特为保留比特；或者
当该目的地址域连续，且该至少一个目的地址索引的个数为2*N个，则该目的地址域的长度为N个字节，该逻辑信道组域的长度为2*N个字节，该缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数；或者
当该目的地址域不连续，且该至少一个目的地址索引的个数为N个，则该目的地址域的长度为N个字节，该逻辑信道组域的长度为N个字节，该缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的总数，其中，该目的地址域中每个字节包括4个保留比特。
可选地，在一些实施例中，该Sidelink BSR包括：目的地址域、逻辑信 道组域和缓存大小域，其中，
该目的地址域为携带该副链路终端设备上报的目的地址bitmap，该目的地址bitmap用于指示副链路终端设备的目的地址是否有数据可传；
该逻辑信道组域为至少一个逻辑信道组bitmap，该至少一个逻辑信道组bitmap与该目的地址bitmap比特位被置为1的目的地址一一对应，一个逻辑信道组bitmap用于指示对应的目的地址的所有逻辑信道组是否有可传数据；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的一个逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于目的地址bitmap的第一比特位对应的第一逻辑信道组bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一目的地址为该目的地址bitmap的第一比特位指示的目的地址，该第一逻辑信道组为该第一逻辑信道组bitmap的第二比特位指示的逻辑信道组。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该缓存大小域是连续的；或者
该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数；
其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
更进一步地，一个该目的地址的索引的长度为4比特，一个该目的地址对应的逻辑信道组为8个，一个该待发数据量在该缓存大小域中占用8比特，其中，
该目的地址域的长度为2个字节；
该逻辑信道组域的长度为N个字节，N为该目的地址bitmap中比特位被置为1的总数；
该缓存大小域的长度为m个字节，m为该逻辑信道组域中所有逻辑信道组bitmap中比特位被置为1的总数。
可选地，在一些实施例中，该Sidelink BSR中包括逻辑信道组域和缓存大小域，
其中，
该逻辑信道组域为该副链路终端设备的size of v2x-DestinationInfoList个目的地址对应的逻辑信道组bitmap，一个逻辑信道组bitmap用于指示对应的目的地址的所有逻辑信道组是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该逻辑信道组域的所有逻辑信道组bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组bitmap的第一比特位，且第一逻辑信道组bitmap对应于第一目的地址，则该第一待发数据量表示该副链路终端设备在该第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，该第一逻辑信道组为该第一逻辑信道组bitmap的第一比特位指示的逻辑信道组。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该缓存大小域是连续的；或者
该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，一个该逻辑信道组子域为一个目的地址对应的一个逻辑信道组bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个逻辑信道组子域中每个该逻辑信道组子域之后跟随x个该缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组bitmap中被置为1的比特的总数；
其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该 Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
一个该目的地址对应的逻辑信道组为8个，一个该待发数据量在该缓存大小域中占用8比特，其中，
该逻辑信道组域占用的字节个数与参数size of v2x-DestinationInfoList值相同；
该缓存大小域的长度为m个字节，m为该逻辑信道组域的所有逻辑信道组bitmap中比特位被置为1的逻辑信道组的总数。
其中，参数size of v2x-DestinationInfoList是通过无线资源控制RRC配置的，或者是协议规定的。
可选地，在一些实施例中，该Sidelink BSR中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
该逻辑信道组域为一个逻辑信道组bitmap，该一个逻辑信道组bitmap用于指示该副链路终端设备在所有逻辑信道组是否有数据可传；
该目的地址域为至少一个目的地址bitmap，该至少一个目的地址bitmap与该逻辑信道组bitmap中比特位被置为1的逻辑信道组一一对应，一个目的地址bitmap用于指示该副链路终端设备的所有目的地址在该目的地址bitmap对应的逻辑信道组上是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该至少一个目的地址bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于逻辑信道组地址bitmap的第一比特位对应的第一目的地址bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的第一逻辑信道组所有逻辑信道的待发数据量的总和，该第一目的地址为第一目的地址bitmap的第二比特位指示的目的地址，该第一逻辑信道组为该逻辑信道组地址bitmap的第一比特位指示的逻辑信道组。
进一步地，在这些实施例中，该目的地址域是连续的，且该缓存大小域是连续的；或者
该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子 域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个该目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数；
其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
更进一步地，逻辑信道组的总数为8个，目的地址总数为16个，一个该待发数据量在该缓存大小域中占用8比特，其中，
该逻辑信道组域长度为1个字节；
该一个目的地址bitmap占用2字节；
该目的地址域长度为2*N个字节，N为该逻辑信道组bitmap中被置为1的比特的总数；
该缓存大小域长度为m个字节，m为该目的地址域的所有目的地址bitmap中被置为1的比特的总数。
可选地，在一些实施例中，该Sidelink BSR中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
该逻辑信道组域为该副链路终端设备的至少一个有数据可传的逻辑信道组的索引；
该目的地址域为至少一个目的地址bitmap，该至少一个目的地址bitmap与该至少一个有数据可传的逻辑信道组一一对应，一个目的地址bitmap用于指示该副链路终端设备的所有目的地址在该目的地址bitmap对应的逻辑信道组上是否有数据可传；
该缓存大小域为至少一个待发数据量，该至少一个待发数据量与该至少一个目的地址bitmap中被置为1的比特位一一对应，其中，如果该至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组对应的第一目的地址bitmap的第二比特位，则该第一待发数据量表示该副链路终端设备在第一目的地址的该第一逻辑信道组上所有逻辑信道的待发数据量的总和，该第一目 的地址为第一逻辑信道组对应的第一目的地址bitmap的第二比特位所指示的目的地址。
进一步地，在这些实施例中，该逻辑信道组域是连续的，该目的地址域是连续的，该缓存大小域是连续的；或者
该逻辑信道组域是连续的，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，该目的地址子域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个该目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数；或者
该逻辑信道组域不连续，该逻辑信道组域包括至少一个逻辑信道组子域，该目的地址域不连续，该目的地址域包括至少一个目的地址子域，该缓存大小域不连续，该缓存大小域包括至少一个缓存大小子域，
该逻辑信道组子域为一个逻辑信道组索引，该目的地址子域为一个逻辑信道组对应的目的地址bitmap，一个该缓存大小子域为一个该待发数据量，该至少一个目的地址子域中每个目的地址子域之后跟随x个该缓存大小子域，x为被跟随的目的地址子域的一个目的地址bitmap中被置为1的比特的总数；
其中，如果该副链路终端设备的上行资源足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含整个该Sidelink BSR的信息；如果该副链路终端设备的上行资源不足以上传整个Sidelink BSR的大小，则该Sidelink BSR的MAC CE中包含该Sidelink BSR经截短处理后的信息。
更进一步地，目的地址总数为16个，一个该待发数据量在该缓存大小域中占用8比特，其中，
当该逻辑信道组域连续，该逻辑信道组域的长度与该至少一个逻辑信道组的索引的个数N相关，该目的地址域的长度为2*N个字节，该一个目的地址bitmap占用2字节，该缓存大小域的长度为m个字节，m为该目的地址域的所有目的地址bitmap中被置为1的比特的总数；或者
当该逻辑信道组域不连续，且该至少一个逻辑信道组的索引的个数为N个，则该逻辑信道组域的长度为N个字节，该目的地址域的长度为2*N个字 节，该缓存大小域的长度为m个字节，m为该目的地址域的所有目的地址bitmap中被置为1的比特的总数。
可选地，在一些实施例中，该Sidelink BSR的MAC CE的子头包括R域、F域、LCID域和L域，其中，
F域为0时表示L域长度为8比特，F域为1时表示L域长度为16比特；
LCID域用于指示跟随该子头的MAC CE类型为Sidelink BSR；
L域用于指示该Sidelink BSR的MAC CE的字节长度。
终端设备1100能够实现前述实施例中终端设备实现的各个过程，为避免重复，这里不再赘述。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机、计算机、服务器、空调器，或者网络设备等)执行本公开各个实施例所述的方法。
上面结合附图对本公开的实施例进行了描述，但是本公开并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本公开的启示下，在不脱离本公开宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本公开的保护之内。

Claims (20)

  1. 一种副链路缓存状态报告的传输方法，应用于副链路终端设备，包括：
    发送副链路缓存状态报告，所述副链路缓存状态报告中包括：目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，
    其中，所述目的地址域和所述逻辑信道组域中的至少一个是基于比特图表示的。
  2. 如权利要求1所述的方法，其中，
    所述副链路缓存状态报告包括：目的地址域、逻辑信道组域和缓存大小域，其中，
    所述目的地址域为所述副链路终端设备上报的至少一个目的地址的索引，所述至少一个目的地址为所述副链路终端设备的有数据可传的目的地址；
    所述逻辑信道组域为至少一个逻辑信道组比特图，所述至少一个逻辑信道组比特图与所述至少一个目的地址一一对应，一个逻辑信道组比特图用于指示对应的目的地址中所有逻辑信道组是否有可传数据；
    所述缓存大小域为至少一个待发数据量，所述至少一个待发数据量与所述逻辑信道组域的所有逻辑信道组比特图中被置为1的比特位一一对应，其中，如果所述至少一个待发数据量中的第一待发数据量对应于第一目的地址的索引对应的第一逻辑信道组比特图中的第一比特位，则所述第一待发数据量表示所述副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，所述第一逻辑信道组为所述第一比特位对应的逻辑信道组。
  3. 如权利要求2所述的方法，其中，
    所述目的地址域是连续的，所述逻辑信道组域是连续的，所述缓存大小域是连续的；或者
    所述目的地址域是连续的，所述逻辑信道组域不连续，所述逻辑信道组域包括至少一个逻辑信道组子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，一个所述逻辑信道组子域为一个目的地址对应的一个逻辑信道组比特图，一个所述缓存大小子域为一个所述待发数据量， 所述至少一个逻辑信道组子域中每个所述逻辑信道组子域之后跟随x个所述缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组比特图中被置为1的比特的总数；或者
    所述目的地址域不连续，所述目的地址域包括至少一个目的地址子域，所述逻辑信道组域包括至少一个逻辑信道组子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，所述目的地址子域为一个目的地址索引，一个所述逻辑信道组子域为一个目的地址对应的一个逻辑信道组比特图，一个所述缓存大小子域为一个所述待发数据量，所述至少一个逻辑信道组子域中每个逻辑信道组子域之后跟随x个所述缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组比特图中被置为1的比特的总数；
    其中，如果所述副链路终端设备的上行资源足以上传整个所述副链路缓存状态报告大小，则所述副链路缓存状态报告的媒体访问控制层控制元素MAC CE中包含整个所述副链路缓存状态报告的信息；如果所述副链路终端设备的上行资源不足以上传整个所述副链路缓存状态报告大小，则所述副链路缓存状态报告的MAC CE中包含所述副链路缓存状态报告经截短处理后的信息。
  4. 如权利要求3所述的方法，其中，一个所述目的地址的索引的长度为4比特，一个所述目的地址对应的逻辑信道组为8个，一个所述待发数据量在所述缓存大小域中占用8比特，其中，
    当所述目的地址域连续，且所述至少一个目的地址索引的个数为2*N-1个，则所述目的地址域的长度为N个字节，所述逻辑信道组域的长度为2*N-1个字节，所述缓存大小域的长度为m个字节，m为所述逻辑信道组域的所有逻辑信道组比特图中比特位被置为1的总数，其中，所述目的地址域第一个字节的前4个比特为保留比特，或所述目的地址域的最后一个字节的后4个比特为保留比特；或者
    当所述目的地址域连续，且所述至少一个目的地址索引的个数为2*N个，则所述目的地址域的长度为N个字节，所述逻辑信道组域的长度为2*N个字节，所述缓存大小域的长度为m个字节，m为所述逻辑信道组域的所有逻辑信道组比特图中比特位被置为1的总数；或者
    当所述目的地址域不连续，且所述至少一个目的地址索引的个数为N个，则所述目的地址域的长度为N个字节，所述逻辑信道组域的长度为N个字节，所述缓存大小域的长度为m个字节，m为所述逻辑信道组域的所有逻辑信道组比特图中比特位被置为1的总数，其中，所述目的地址域中每个字节包括4个保留比特。
  5. 如权利要求1所述的方法，其中，
    所述副链路缓存状态报告包括：目的地址域、逻辑信道组域和缓存大小域，其中，
    所述目的地址域为携带所述副链路终端设备上报的目的地址比特图，所述目的地址比特图用于指示副链路终端设备的目的地址是否有数据可传；
    所述逻辑信道组域为至少一个逻辑信道组比特图，所述至少一个逻辑信道组比特图与所述目的地址比特图比特位被置为1的目的地址一一对应，一个逻辑信道组比特图用于指示对应的目的地址的所有逻辑信道组是否有可传数据；
    所述缓存大小域为至少一个待发数据量，所述至少一个待发数据量与所述逻辑信道组域的一个逻辑信道组比特图中被置为1的比特位一一对应，其中，如果所述至少一个待发数据量中的第一待发数据量对应于目的地址比特图的第一比特位对应的第一逻辑信道组比特图的第二比特位，则所述第一待发数据量表示所述副链路终端设备在第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，所述第一目的地址为所述目的地址比特图的第一比特位指示的目的地址，所述第一逻辑信道组为所述第一逻辑信道组比特图的第二比特位指示的逻辑信道组。
  6. 如权利要求5所述的方法，其中，
    所述逻辑信道组域是连续的，所述缓存大小域是连续的；或者
    所述逻辑信道组域不连续，所述逻辑信道组域包括至少一个逻辑信道组子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，一个所述逻辑信道组子域为一个目的地址对应的一个逻辑信道组比特图，一个所述缓存大小子域为一个所述待发数据量，所述至少一个逻辑信道组子域中每个所述逻辑信道组子域之后跟随x个所述缓存大小子域，x为被跟随的 逻辑信道组子域的一个逻辑信道组比特图中被置为1的比特的总数；
    其中，如果所述副链路终端设备的上行资源足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含整个所述副链路缓存状态报告的信息；如果所述副链路终端设备的上行资源不足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含所述副链路缓存状态报告经截短处理后的信息。
  7. 如权利要求5或6所述的方法，其中，一个所述目的地址的索引的长度为4比特，一个所述目的地址对应的逻辑信道组为8个，一个所述待发数据量在所述缓存大小域中占用8比特，其中，
    所述目的地址域的长度为2个字节；
    所述逻辑信道组域的长度为N个字节，N为所述目的地址比特图中比特位被置为1的总数；
    所述缓存大小域的长度为m个字节，m为所述逻辑信道组域中所有逻辑信道组比特图中比特位被置为1的总数。
  8. 如权利要求1所述的方法，其中，
    所述副链路缓存状态报告中包括逻辑信道组域和缓存大小域，
    其中，
    所述逻辑信道组域为所述副链路终端设备的size of v2x-DestinationInfoList个目的地址对应的逻辑信道组比特图，一个逻辑信道组比特图用于指示对应的目的地址的所有逻辑信道组是否有数据可传；
    所述缓存大小域为至少一个待发数据量，所述至少一个待发数据量与所述逻辑信道组域的所有逻辑信道组比特图中被置为1的比特位一一对应，其中，如果所述至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组比特图的第一比特位，且第一逻辑信道组比特图对应于第一目的地址，则所述第一待发数据量表示所述副链路终端设备在所述第一目的地址的第一逻辑信道组的所有逻辑信道的待发数据量的总和，所述第一逻辑信道组为所述第一逻辑信道组比特图的第一比特位指示的逻辑信道组。
  9. 如权利要求8所述的方法，其中，
    所述逻辑信道组域是连续的，所述缓存大小域是连续的；或者
    所述逻辑信道组域不连续，所述逻辑信道组域包括至少一个逻辑信道组子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，一个所述逻辑信道组子域为一个目的地址对应的一个逻辑信道组比特图，一个所述缓存大小子域为一个所述待发数据量，所述至少一个逻辑信道组子域中每个所述逻辑信道组子域之后跟随x个所述缓存大小子域，x为被跟随的逻辑信道组子域的一个逻辑信道组比特图中被置为1的比特的总数；
    其中，如果所述副链路终端设备的上行资源足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含整个所述副链路缓存状态报告的信息；如果所述副链路终端设备的上行资源不足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含所述副链路缓存状态报告经截短处理后的信息。
  10. 如权利要求8或9所述的方法，其中，
    一个所述目的地址对应的逻辑信道组为8个，一个所述待发数据量在所述缓存大小域中占用8比特，其中，
    所述逻辑信道组域占用的字节个数与参数size of v2x-DestinationInfoList值相同；
    所述缓存大小域的长度为m个字节，m为所述逻辑信道组域的所有逻辑信道组比特图中比特位被置为1的逻辑信道组的总数。
  11. 如权利要求1所述的方法，其中，
    所述副链路缓存状态报告中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
    所述逻辑信道组域为一个逻辑信道组比特图，所述一个逻辑信道组比特图用于指示所述副链路终端设备在所有逻辑信道组是否有数据可传；
    所述目的地址域为至少一个目的地址比特图，所述至少一个目的地址比特图与所述逻辑信道组比特图中比特位被置为1的逻辑信道组一一对应，一个目的地址比特图用于指示所述副链路终端设备的所有目的地址在所述目的地址比特图对应的逻辑信道组上是否有数据可传；
    所述缓存大小域为至少一个待发数据量，所述至少一个待发数据量与所述至少一个目的地址比特图中被置为1的比特位一一对应，其中，如果所述 至少一个待发数据量中的第一待发数据量对应于逻辑信道组地址比特图的第一比特位对应的第一目的地址比特图的第二比特位，则所述第一待发数据量表示所述副链路终端设备在第一目的地址的第一逻辑信道组所有逻辑信道的待发数据量的总和，所述第一目的地址为第一目的地址比特图的第二比特位指示的目的地址，所述第一逻辑信道组为所述逻辑信道组地址比特图的第一比特位指示的逻辑信道组。
  12. 如权利要求11所述的方法，其中，
    所述目的地址域是连续的，且所述缓存大小域是连续的；或者
    所述目的地址域不连续，所述目的地址域包括至少一个目的地址子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，所述目的地址子域为一个逻辑信道组对应的目的地址比特图，一个所述缓存大小子域为一个所述待发数据量，所述至少一个目的地址子域中每个所述目的地址子域之后跟随x个所述缓存大小子域，x为被跟随的目的地址子域的一个目的地址比特图中被置为1的比特的总数；
    其中，如果所述副链路终端设备的上行资源足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含整个所述副链路缓存状态报告的信息；如果所述副链路终端设备的上行资源不足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含所述副链路缓存状态报告经截短处理后的信息。
  13. 如权利要求12的方法，其中，
    逻辑信道组的总数为8个，目的地址总数为16个，一个所述待发数据量在所述缓存大小域中占用8比特，其中，
    所述逻辑信道组域长度为1个字节；
    所述一个目的地址比特图占用2字节；
    所述目的地址域长度为2*N个字节，N为所述逻辑信道组比特图中被置为1的比特的总数；
    所述缓存大小域长度为m个字节，m为所述目的地址域的所有目的地址比特图中被置为1的比特的总数。
  14. 如权利要求1所述的方法，其中，
    所述副链路缓存状态报告中包括：逻辑信道组域、目的地址域和缓存大小域，其中，
    所述逻辑信道组域为所述副链路终端设备的至少一个有数据可传的逻辑信道组的索引；
    所述目的地址域为至少一个目的地址比特图，所述至少一个目的地址比特图与所述至少一个有数据可传的逻辑信道组一一对应，一个目的地址比特图用于指示所述副链路终端设备的所有目的地址在所述目的地址比特图对应的逻辑信道组上是否有数据可传；
    所述缓存大小域为至少一个待发数据量，所述至少一个待发数据量与所述至少一个目的地址比特图中被置为1的比特位一一对应，其中，如果所述至少一个待发数据量中的第一待发数据量对应于第一逻辑信道组对应的第一目的地址比特图的第二比特位，则所述第一待发数据量表示所述副链路终端设备在第一目的地址的所述第一逻辑信道组上所有逻辑信道的待发数据量的总和，所述第一目的地址为第一逻辑信道组对应的第一目的地址比特图的第二比特位所指示的目的地址。
  15. 如权利要求14所述的方法，其中，
    所述逻辑信道组域是连续的，所述目的地址域是连续的，所述缓存大小域是连续的；或者
    所述逻辑信道组域是连续的，所述目的地址域不连续，所述目的地址域包括至少一个目的地址子域，所述缓存大小域包括至少一个缓存大小子域，所述目的地址子域为一个逻辑信道组对应的目的地址比特图，一个所述缓存大小子域为一个所述待发数据量，所述至少一个目的地址子域中每个所述目的地址子域之后跟随x个所述缓存大小子域，x为被跟随的目的地址子域的一个目的地址比特图中被置为1的比特的总数；或者
    所述逻辑信道组域不连续，所述逻辑信道组域包括至少一个逻辑信道组子域，所述目的地址域不连续，所述目的地址域包括至少一个目的地址子域，所述缓存大小域不连续，所述缓存大小域包括至少一个缓存大小子域，所述逻辑信道组子域为一个逻辑信道组索引，所述目的地址子域为一个逻辑信道组对应的目的地址比特图，一个所述缓存大小子域为一个所述待发数据量， 所述至少一个目的地址子域中每个目的地址子域之后跟随x个所述缓存大小子域，x为被跟随的目的地址子域的一个目的地址比特图中被置为1的比特的总数；
    其中，如果所述副链路终端设备的上行资源足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含整个所述副链路缓存状态报告的信息；如果所述副链路终端设备的上行资源不足以上传整个所述副链路缓存状态报告的大小，则所述副链路缓存状态报告的MAC CE中包含所述副链路缓存状态报告经截短处理后的信息。
  16. 如权利要求15所述的方法，其中，
    目的地址总数为16个，一个所述待发数据量在所述缓存大小域中占用8比特，其中，
    当所述逻辑信道组域连续，所述逻辑信道组域的长度与所述至少一个逻辑信道组的索引的个数N相关，所述一个目的地址比特图占用2字节，所述目的地址域的长度为2*N个字节，所述缓存大小域的长度为m个字节，m为所述目的地址域的所有目的地址比特图中被置为1的比特的总数；或者
    当所述逻辑信道组域不连续，且所述至少一个逻辑信道组的索引的个数为N个，则所述逻辑信道组域的长度为N个字节，所述目的地址域的长度为2*N个字节，所述缓存大小域的长度为m个字节，m为所述目的地址域的所有目的地址比特图中被置为1的比特的总数。
  17. 如权利要求1-16中任一项所述的方法，其中，
    所述副链路缓存状态报告的MAC CE的子头包括R域、F域、LCID域和L域，其中，
    F域为0时表示L域长度为8比特，F域为1时表示L域长度为16比特；
    LCID域用于指示跟随所述子头的MAC CE类型为副链路缓存状态报告；
    L域用于指示所述副链路缓存状态报告的MAC CE的字节长度。
  18. 一种副链路终端设备，包括：
    发送模块，发送副链路缓存状态报告，所述副链路缓存状态报告中包括：目的地址域、逻辑信道组域和缓存大小域，或者包括逻辑信道组域和缓存大小域，
    其中，所述目的地址域和所述逻辑信道组域中的至少一个是基于比特图表示的。
  19. 一种终端设备，包括：存储器、处理器及存储在所述存储器上并可在所述处理器上运行的程序，所述程序被所述处理器执行时实现如权利要求1至17中任一项所述的方法的步骤。
  20. 一种计算机可读存储介质，所述计算机可读存储介质上存储有程序，所述程序被处理器执行时实现如权利要求1至17中任一项所述的方法的步骤。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159102A2 (ko) * 2010-06-18 2011-12-22 엘지전자 주식회사 무선 통신 시스템에서 단말이 버퍼 상태 보고를 전송하는 방법 및 이를 위한 장치
CN106454687A (zh) * 2015-07-21 2017-02-22 电信科学技术研究院 一种分配资源的方法和设备
WO2017049728A1 (zh) * 2015-09-25 2017-03-30 宇龙计算机通信科技(深圳)有限公司 副链路缓冲状态报告的生成方法及装置
CN107347215A (zh) * 2016-05-06 2017-11-14 普天信息技术有限公司 在v2x网络中资源的分配方法及终端
CN107360591A (zh) * 2017-06-15 2017-11-17 电信科学技术研究院 一种上报缓存状态报告的方法和设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159102A2 (ko) * 2010-06-18 2011-12-22 엘지전자 주식회사 무선 통신 시스템에서 단말이 버퍼 상태 보고를 전송하는 방법 및 이를 위한 장치
CN106454687A (zh) * 2015-07-21 2017-02-22 电信科学技术研究院 一种分配资源的方法和设备
WO2017049728A1 (zh) * 2015-09-25 2017-03-30 宇龙计算机通信科技(深圳)有限公司 副链路缓冲状态报告的生成方法及装置
CN107347215A (zh) * 2016-05-06 2017-11-14 普天信息技术有限公司 在v2x网络中资源的分配方法及终端
CN107360591A (zh) * 2017-06-15 2017-11-17 电信科学技术研究院 一种上报缓存状态报告的方法和设备

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