WO2019184612A1 - 一种终端及电子设备 - Google Patents

一种终端及电子设备 Download PDF

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Publication number
WO2019184612A1
WO2019184612A1 PCT/CN2019/075070 CN2019075070W WO2019184612A1 WO 2019184612 A1 WO2019184612 A1 WO 2019184612A1 CN 2019075070 W CN2019075070 W CN 2019075070W WO 2019184612 A1 WO2019184612 A1 WO 2019184612A1
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WIPO (PCT)
Prior art keywords
memory
repair
processor
module
array
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PCT/CN2019/075070
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English (en)
French (fr)
Inventor
魏威
普玉伟
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华为技术有限公司
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Publication of WO2019184612A1 publication Critical patent/WO2019184612A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals

Definitions

  • the present application relates to the field of memory technologies, and in particular, to a terminal and an electronic device.
  • the failure of the terminal chip is an important cause of the field failure of the terminal.
  • SRAM static random access memory
  • ATE automatic test equipment
  • MBIST memory built-in self-test
  • BISR built-in self-repair
  • the above method cannot be performed on the running terminal, that is, the memory failure problem that occurs after the terminal is used cannot be solved by the above method, and there is currently no effective method for repairing the memory in the terminal.
  • the embodiment of the present application provides a terminal and an electronic device, which are used to detect and repair a memory in the terminal.
  • an embodiment of the present application provides a terminal, including: a determining module, a processor, a memory, and a repairing module.
  • the determining module is configured to notify the processor when an abnormality occurs in the memory.
  • the processor is configured to instruct the repair module to repair the memory when an abnormality occurs in the memory.
  • the processor may be a central processing unit (CPU), or an application processing unit, or a low-power processor that exclusively performs auxiliary operations such as repairing memory.
  • CPU central processing unit
  • application processing unit application processing unit
  • low-power processor that exclusively performs auxiliary operations such as repairing memory.
  • the foregoing memory may be a cache memory, an embedded multimedia card, a universal flash memory, or a double rate synchronous dynamic random access memory.
  • the repair module may be a self-repair module built in the memory.
  • the terminal further includes: a test module
  • the processor When the processor instructs the repair module to repair the memory, the processor is specifically configured to:
  • the repair module is instructed to repair the failed storage unit.
  • the test module may be a self-test module built in the memory.
  • the processor is further configured to:
  • the test module is instructed to test the memory to determine whether the repair is successful.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the processor is further configured to: before instructing the test module to detect each storage array:
  • a flag bit of the memory array is read, the flag bit indicating that the memory array is not repaired.
  • the processor is further configured to: set a flag bit of the memory, and the set flag bit indicates that the storage array has been Was fixed.
  • the terminal provided in the foregoing embodiment can repair the processor that has been used in the terminal, thereby improving the user experience.
  • an embodiment of the present application provides an electronic device, including: a processor, a determining module, and a repairing module, where the processor is configured to execute a program, and access a memory based on the program instruction, where the processor further uses Generating an exception report when an abnormality occurs during execution of the program, the determining module is configured to analyze the abnormality report, and determine whether a memory is faulty based on the abnormality report, where the repair module is used when a memory failure occurs , repair the memory.
  • the electronic device further includes: a testing module, configured to detect the storage unit in the memory;
  • the repair module is specifically configured to: repair a storage unit that detects a failure.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the processor is further configured to: read a flag bit of the storage array before the testing module detects each storage array, the flag bit indicating that the storage array is not repaired.
  • an embodiment of the present application provides an electronic device, including one or more processors and an instruction storage device, where the instruction storage device stores an instruction, where the instruction is used to cause the one or more processes
  • the device performs the following actions:
  • the memory is repaired when the exception is caused by a memory failure.
  • the instruction is specifically configured to cause the one or more processors to perform an action of: detecting a storage unit in the memory; and detecting a failed storage unit, The failed storage unit is repaired.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the instructions cause the one or more processors to read a flag bit of the memory array prior to detecting each memory array, the flag bit indicating that the memory array is not repaired.
  • the embodiment of the present application provides a non-transitory computer-readable medium, where the readable storage medium includes:
  • the instruction for repairing a memory includes: an instruction for detecting a storage unit in the memory; and a storage unit for detecting a failure, An instruction to repair a failed storage unit.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the terminal described in the embodiment of the present invention includes a mobile terminal device, and various network devices.
  • FIG. 1 is a schematic diagram of a test and repair process of a memory chip according to an embodiment of the present application
  • FIG. 2 is a schematic structural diagram of a terminal according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a terminal execution according to an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a connection between a processor and a repair module according to an embodiment of the present application
  • FIG. 5 is a schematic diagram of a connection between a processor and a test module according to an embodiment of the present application
  • FIG. 6 is a schematic flowchart of repairing a memory by a terminal according to an embodiment of the present disclosure
  • FIG. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • a memory chip includes a plurality of memory cells for storing data, and each memory cell can store one or more bits of data.
  • MBIST and BISR are usually built in the memory chip. Before the memory chip is shipped from the factory, the memory chip can be tested by ATE to detect whether there is any failure. The storage unit, and after detecting the existence of the failed storage unit, invokes the BISR to repair the memory chip.
  • MBIST usually adopts one or more algorithms to specifically design one or more defect types of test memory.
  • MBIST can automatically implement storage unit or storage array (for example: one row of storage unit or one column of storage unit) for built-in self-test.
  • EDA electronic design automation
  • MBIST can also include automatic fault diagnosis to facilitate fault location and develop targeted test vectors.
  • the MBIST can include a test vector generation circuit, a BIST control circuit, and a response analyzer.
  • the test vector generation circuit can generate a variety of test vectors, and the test vector content generated by the circuit implemented by different test algorithms is also different;
  • the BIST control circuit is usually implemented by a state machine to control the read and write operations on the memory;
  • the response analyzer can be used
  • the comparator implementation can also be implemented with a Compressor Multiple Input Shift Register (MISR) circuit that compares the actual memory model response and detects device errors against known normal memory responses.
  • MISR Compressor Multiple Input Shift Register
  • the process of testing and repairing the memory chip can be as shown in FIG. 1 , wherein the design for testability (DFT) in the ATE calls the MBIST to test the storage unit in the storage chip to detect whether the existence exists. Failed storage unit. If there are no failed memory locations, the DFT continues to perform additional tests on the memory chip. If there is a failed storage unit, it can be further determined whether the storage unit can be repaired by the BISR. If the judgment cannot be repaired, the chip is considered to be invalid; if it is judged that the storage unit can be repaired by the BISR, the DFT can call the BISR to repair the failed storage unit. After the BISR repair is complete, call MBIST again to test the storage unit to check whether the repair is successful. If the test passes, the corresponding flag bit of the storage unit is programmed to indicate that the storage unit has been repaired; if the test fails to pass the test, the chip is considered to be invalid.
  • DFT design for testability
  • the above test and repair of the memory chip are implemented based on ATE. If a memory chip is placed on a terminal, the memory chip fails after the terminal is used. At this time, since the terminal does not have the function of testing and repairing the memory chip, the memory chip may need to be replaced to enable the terminal to continue. Work, causing inconvenience to the user, reducing the user experience.
  • the embodiment of the present application provides a terminal, which implements repairing a memory that has been used in the terminal, and helps improve the user experience.
  • the terminal provided by the embodiment of the present application includes a determining module 201, a processor 202, a memory 203, and a repairing module 204.
  • the repair module 204 may be a repair module built into the memory 203, such as a BISR; or the repair module 204 may be independent of the memory 203.
  • the processor 202 and the memory 203 in the embodiment of the present application may be located on one integrated circuit chip, for example, the CPU may be located on a chip with a cache; or the processor 202 and the memory 203 may be located on different chips. Both implement data communication through the chip's external interface.
  • the judging module 201 in the embodiment of the present application may also be located on an integrated circuit chip with the memory 203, or on different chips, and the two implement data communication through the external interface of the chip.
  • the storage management system in the embodiment of the present application may be disposed in the terminal, and perform the steps shown in FIG. 3:
  • Step 301 When the determining module 201 determines that an abnormality occurs in the memory 203, the processor 201 is notified.
  • Step 302 When the processor 202 generates an abnormality in the memory 203, the instruction repair module 204 repairs the memory 203.
  • the foregoing embodiment can be applied to the terminal to repair the memory in the terminal, so that the terminal can also repair the memory when the memory fails after use, thereby improving the user experience.
  • the decision module 201 can be a logical module in the processor 202.
  • the processor 202 is configured to instruct the repair module 204 to repair the memory.
  • the processor 202 can be a CPU, or a processor that specifically performs a specific service, such as an application processor, or even a low-power processor that exclusively performs auxiliary operations such as repairing memory.
  • the processor usually involves reading and writing data from the memory during operation, and the failure of the memory causes erroneous read and write feedback, which is detected by the determining module 201. On this basis, it is possible to set the processor's own ability to discover and instruct the repair of such a memory failure. For example, when the application processor reads and writes the memory, the memory module is found by the judgment module 201, and then the processor instruction repair module is applied. Repair the memory. In other alternative embodiments, a dedicated low power processor can also be set to repair the memory when the application processor finds a memory exception.
  • the judging module may be a logic module in the application processor to determine whether the abnormality is caused by a memory abnormality when an abnormality occurs in the application processor.
  • the determining module may also be a logic module of the low power processor, analyzing an abnormality of the application processor, and then identifying a memory failure.
  • the determining module 201 determines whether the memory is abnormal according to the abnormality report. If the determining module 201 determines the memory abnormality according to the abnormality report, it sends a message to the corresponding processor to notify the memory abnormality, and then the corresponding processor repairs the memory.
  • the determining module 201 determines whether the memory 203 is abnormal according to the abnormality cause in the abnormality report.
  • memory exceptions or other device anomalies are not directly reported in the exception report. For example, if some of the memory cells in the memory fail, data cannot be read from the failed memory cells, and data cannot be written into the failed memory cells, which may result in failure to read data or data write failure. The program does not work properly, and the exception report generated at this time may indicate that the data acquisition failed. Therefore, the judging module 201 needs to judge whether the failure of acquiring data is caused by the abnormality of the memory 203.
  • the abnormal cause in the plurality of abnormal reports and the final determined fault cause may be statistically analyzed in advance to determine which types of abnormal causes may be Due to memory failure.
  • the general failure to obtain an address and data may be due to an abnormality in the memory 203.
  • the storage management system provided by the embodiment of the present application further includes a test module 205.
  • the processor 202 can further instruct the test module 205 to detect the memory 203 before the processor 202 instructs the repair module 204 to repair the memory 203 to finally determine whether the memory 203 has a failed memory location.
  • test module 205 may be a test module built in the memory 203, such as MBIST; or the test module 205 may be independent of the memory 203.
  • the processor 202 can be connected to the test module 205 and the repair module 204 via a bus, respectively.
  • connection between the processor 202 and the repair module 204 can be as shown in FIG. 4, wherein the BISR is respectively associated with a memory repair block (MRB) and an electrical programming fuse in the memory ( EFUSE)
  • MRB memory repair block
  • EFUSE electrical programming fuse in the memory
  • an interface is provided for connecting the processor in the terminal or the DFT in the ATE.
  • the processor can control the BISR to repair the memory by setting a function register.
  • the processor can be connected to the function register through the X2J (AXI to JTAG) bus to control the function register.
  • the function register can also be implemented through the DFT register to avoid adding new devices.
  • the connection between the processor 202 and the test module 205 can be as shown in FIG. 5, wherein the MBIST can include one or more MBIST controllers (for example, two MBIST controllers in FIG. 5), each MBIST is used for Test the attached storage array.
  • the DFT in ATE can control the memory array by controlling the MBIST through the DFT register.
  • the processor can also access the MBIST by setting the function register to control the MBIST to test the storage array.
  • the function register can also be implemented through the DFT register to avoid adding new devices.
  • the processor 202 since the processor 202 is connected to the MBIST and the BISR through the bus, the MBIST and the BISR built in the memory 203 can be accessed, so that when the terminal is in normal operation, the processor in the terminal can also control the MBIST and the BISR to detect the memory. Repair without having to disassemble or repair with professional repair equipment.
  • a redundant memory array is typically used to replace the memory array with the failed memory cell.
  • the BISR can read data from the MRB to obtain the location information of the failed memory cell, compress the read data, and write to the EFUSE device.
  • the BISR is The compressed data is read by the EFUSE device, and the decompressed data is input into the MRB corresponding to the replacement storage array to replace the failed storage array with the redundant storage array.
  • the BISR when replacing the storage array with the failed storage unit, can set the address of the redundant storage array to the address of the storage array in which the failed storage unit exists, so that the data can be redundantly read after the data is read according to the address. The corresponding data is obtained in the storage array.
  • the processor 202 may further instruct the test module 205 to detect the memory again to detect whether the memory is successfully repaired. If the repair is successful, the terminal can continue to work or continue to detect other components. If the repair fails, the memory may not continue to work normally, and the memory may need to be replaced.
  • a corresponding flag bit can be set for each memory array in the memory, and the flag bit is used to indicate whether the corresponding storage array is repaired.
  • the processor 202 may first read the corresponding flag bit of each storage array. If the flag bit indicates that its corresponding storage array has not been repaired, the processor 202 instructs the test module 205 to perform the storage array. Detecting, detecting whether there is a failed storage unit; if the flag indicates that its corresponding storage array has been repaired, the detection of the storage array may be skipped and the flag of the next storage array may continue to be read. Alternatively, instead of the processor reading the flag bit, the hardware array can be automatically skipped by hardware implementation.
  • the processor 202 may further instruct the repair module 204 to set the flag to indicate that the storage array has been repaired.
  • a plurality of processors may be included in one terminal, and a low power processor may be included.
  • Low-power processors are typically used to execute low-level programs, not for running applications and application-based applications.
  • the processor in the terminal may control the terminal to restart. After the terminal is restarted, only the low-power processor in the terminal may be run to perform the foregoing step 301. And step 302.
  • the processor connected to the test module 2021 and the repair module 2022 in the memory is a low power processor.
  • the processor that determines whether the terminal abnormality is related to the memory may be a low power processor or another processor.
  • step 601 an abnormality occurs in the terminal operation.
  • Step 602 The processor in the terminal determines whether the abnormality is related to the memory. If the processor determines that the exception may be related to the memory, then step 603 is performed; otherwise, the memory may be considered normal and other tests may be performed.
  • Step 603 The processor in the terminal controls the terminal to restart, and only the low power processor is run after the terminal restarts.
  • Step 604 The MBIST in the low power processor control memory detects the memory to detect whether there is a failed storage unit.
  • the MBIST can perform row-by-row or column-by-column detection on the memory cells in the memory.
  • column-by-column detection each column of memory cells can be referred to as a memory array, before MBIST tests each memory array.
  • the low-power processor can read the flag bit corresponding to the storage array to determine whether the storage array has been repaired. If it has been repaired, skip the detection of the storage array and continue to read the flag of the next storage array. Bit, if the flag indicates that the memory array has not been repaired, then the MBIST is controlled to test the memory array to detect if there is a failed memory cell in the memory array.
  • Step 605 If it is detected that there is a failed storage unit, the low power processor controls the BISR to repair the memory.
  • the BISR can replace a storage array with failed storage units with redundant storage arrays. Specifically, in the memory test phase, the BISR can read data from the MRB to obtain the location information of the failed memory cell, compress the read data, and write to the EFUSE device; in the memory repair phase, the BISR The compressed data is read from the EFUSE device, decompressed, and the decompressed data is input into the MRB corresponding to the replacement storage array to replace the failed storage array with the redundant storage array.
  • Step 606 The low power processor controls the MBIST to detect the memory again, and detects whether the repair is successful. If the repair is successful, step 607 is performed; otherwise, the memory is considered to be unrepairable.
  • the terminal may not continue to work normally, and it may need to be repaired by a professional or device, or replaced with a new memory.
  • Step 607 If the repair is successful, the low power processor controls the terminal to restart the terminal and runs the application system. After the repair, the terminal can run and work normally.
  • the embodiment of the present application further provides an electronic device, as shown in FIG. 7, including: a processor 701, a determining module 702, and a repairing module 703, where the processor 701 is configured to execute a program. And accessing the memory based on the program instruction, the processor 701 is further configured to generate an exception report when an abnormality occurs during execution of the program, the determining module 702 is configured to analyze the abnormality report, and based on the abnormality report Determining whether the memory has failed, the repair module 703 is configured to repair the memory when the memory fails.
  • the electronic device further includes: a test module (not shown) for detecting a storage unit in the memory; the repair module 703 is specifically configured to: detect The failed storage unit is repaired.
  • test module is further configured to: test the memory to determine whether the repair is successful.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the processor 701 is further configured to: read a flag bit of the storage array before the testing module detects each storage array, the flag bit indicating that the storage array is not repaired.
  • the processor 701 is further configured to: set a flag bit of the memory, and the set flag bit indicates the storage array Has been fixed.
  • an embodiment of the present application further provides an electronic device, including one or more processors and an instruction storage device, wherein the instruction storage device stores an instruction, where the instruction is used to make
  • the one or more processors perform the following actions:
  • the memory is repaired when the exception is caused by a memory failure.
  • the instruction is specifically configured to cause the one or more processors to perform an action of: detecting a storage unit in the memory; and detecting a failed storage unit, The failed storage unit is repaired.
  • the instructions cause the one or more processors to test the memory after repairing the memory to determine whether the repair is successful.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the instructions cause the one or more processors to read a flag bit of the memory array prior to detecting each memory array, the flag bit indicating that the memory array is not repaired.
  • the instruction causes the one or more processors to set a flag of the memory after repairing the memory, and the set flag indicates that the storage array has been Fixed it.
  • the embodiment of the present application further provides a non-transitory computer readable storage medium, where the readable storage medium includes:
  • the instruction for repairing a memory includes: an instruction for detecting a storage unit in the memory; and a storage unit for detecting a failure, An instruction to repair a failed storage unit.
  • the readable storage medium further includes: an instruction for testing the memory to determine whether the repair is successful after repairing the memory.
  • each storage array in the memory is provided with a flag bit for indicating whether the storage array is repaired, and each storage array includes multiple storages. unit;
  • the readable storage medium also includes instructions for reading a flag bit of the memory array prior to detecting each memory array, the flag indicating that the memory array is not repaired.
  • the readable storage medium further includes: an instruction for setting a flag bit of the memory after repairing the memory, the set flag bit indicating that the storage array has been Was fixed.
  • the instruction storage device may be an off-chip storage device such as an embedded multimedia card (eMMC)/universal flash storage (UFS).
  • eMMC embedded multimedia card
  • UFS universal flash storage
  • program instructions that the computer needs to run are usually pre-stored in eMMC and UFS.
  • the instruction storage device may also be a memory, such as a double data rate memory (DDR memory).
  • DDR memory double data rate memory
  • embodiments of the present application can be provided as a method, system, or computer program product.
  • the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment in combination of software and hardware.
  • the application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, optical storage, etc.) including computer usable program code.

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Abstract

一种终端及电子设备。该终端包括判断模块（201），处理器（202），存储器（203），修复模块（204）；所述判断模块（201）用于在所述存储器（203）发生异常时，通知所述处理器（202）；所述处理器（202）用于在所述存储器（203）发生异常时，指令所述修复模块（204）对所述存储器（203）进行修复。该终端实现了对终端中已使用的存储器（203）进行修复。

Description

一种终端及电子设备
本申请要求在2018年3月30日提交中国专利局、申请号为201810289503.3、发明名称为“一种终端及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储器技术领域，尤其涉及一种终端及电子设备。
背景技术
一般来说，集成电路在研制、生产和使用过程中失效不可避免。随着人们对产品质量和可靠性要求的不断提高，越来越注重对芯片的测试、修复。
终端类芯片的失效，是造成终端现场失效的重要原因，其中，静态随机存储器(static random access memory，SRAM)的早期失效在终端类芯片早期失效中占有较大比例。为了解决这一问题，可以利用自动测试设备(automatic test equipment，ATE)以及存储器内置的存储器内建自测试(memory build in self-test，MBIST)、内建自修复(build-in self-repair，BISR)对存储器中的存储单元(bit cell)进行检测并修复。利用ATE对存储器进行检测、修复的过程通常在出厂之前进行，能够较好的解决存储器早期失效问题。
然而，上述方法无法在运行的终端上进行，即对于终端在使用后发生的存储器失效问题，并不能通过上述方法解决，且目前也没有有效的对终端中存储器进行修复的方法。
发明内容
本申请实施例提供一种终端及电子设备，用以实现对终端中的存储器进行检测、修复。
第一方面，本申请实施例提供了一种终端，包括：判断模块，处理器，存储器，修复模块。
其中，所述判断模块用于在所述存储器发生异常时，通知所述处理器。
所述处理器用于在所述存储器发生异常时，指令所述修复模块对所述存储器进行修复。
可选地，上述处理器可以为中央处理器(central processing unit，CPU)，或者为应用处理器(application processing unit)，还可以是专门执行诸如修复存储器这种辅助工作的低功耗处理器。
可选地，上述存储器可以为高速缓冲存储器、嵌入式多媒体卡、通用闪存存储器或双倍速率同步动态随机存储器等。
可选地，上述修复模块可以为存储器中内置的自修复模块。
在一种可能的实现方式中，所述终端还包括：测试模块；
所述处理器在指令所述修复模块对存储器进行修复时，具体用于：
指令所述测试模块对所述存储器中的存储单元进行检测；
若检测到失效的存储单元，指令所述修复模块对所述失效的存储单元进行修复。
可选地，上述测试模块可以为存储器中内置的自测试模块。
在一种可能的实现方式中，所述处理器在指令所述修复模块对所述存储器进行修复之 后，还用于：
指令所述测试模块对所述存储器进行测试，确定是否修复成功。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述处理器在指令所述测试模块对每个存储阵列进行检测之前，还用于：
读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
在一种可能的实现方式中，所述处理器在指令所述修复模块对所述存储器进行修复之后，还用于：设置所述存储器的标志位，设置后的标志位表示所述存储阵列已被修复过。
上述实施例所提供的终端，能够对终端中已使用的处理器进行修复，从而提高用户体验。
第二方面，本申请实施例提供了一种电子设备，包括：处理器，判断模块，以及修复模块，所述处理器用于执行程序，并基于所述程序指令访问存储器，所述处理器还用于在所述程序执行过程中发生异常时生成异常报告，所述判断模块用于分析所述异常报告，并基于所述异常报告判断存储器是否发生故障，所述修复模块用于在存储器发生故障时，对存储器进行修复。
在一种可能的实现方式中，该电子设备还包括：测试模块，用于对所述存储器中的存储单元进行检测；
所述修复模块具体用于：对检测到失效的存储单元进行修复。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述处理器在所述测试模块对每个存储阵列进行检测之前，还用于：读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
第三方面，本申请实施例提供了一种电子设备，包括一个或多个处理器和指令存储设备，所述指令存储设备中保存有指令，所述指令用于使得所述一个或多个处理器执行下述动作：
在发生异常时，生成异常报告；
基于所述异常报告，判断异常是否是由存储器故障引起的；
当异常是由存储器故障引起的时候，对存储器进行修复。
在一种可能的实现方式中，所述指令具体用于使得所述一个或多个处理器执行下述动作：对所述存储器中的存储单元进行检测；若检测到失效的存储单元，对所述失效的存储单元进行修复。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述指令使得所述一个或多个处理器在对每个存储阵列进行检测之前，读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
第四方面，本申请实施例提供了一种非易失性计算机可读存储介质(non-transitory computer-readable medium)，所述可读存储介质包括：
用于接收处理器生成的异常报告的指令；
用于基于所述异常报告，判断异常是否是由存储器故障引起的指令；
用于当异常是由存储器故障引起的时候，对存储器进行修复的指令。
在一种可能的实现方式中，所述用于对存储器进行修复的指令，包括：用于对所述存储器中的存储单元进行检测的指令；用于在检测到失效的存储单元，对所述失效的存储单元进行修复的指令。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
用于在对每个存储阵列进行检测之前，读取所述存储阵列的标志位的指令，所述标志位表示所述存储阵列未被修复。
本发明实施例中所述的终端包括移动终端设备，以及各种网络设备。
附图说明
图1为本申请实施例提供的存储芯片测试、修复流程示意图；
图2为本申请实施例提供的终端的结构示意图；
图3为本申请实施例提供的终端执行的流程示意图；
图4为本申请实施例提供的处理器与修复模块连接示意图；
图5为本申请实施例提供的处理器与测试模块连接示意图；
图6为本申请实施例提供的终端对存储器进行修复的流程示意图；
图7为本申请实施例提供的电子设备的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请作进一步地详细描述。
一个存储芯片上包括若干存储单元，用于存储数据，每个存储单元可以存储1个或更多bit的数据。由于加工过程中可能会导致存储单元失效，为了避免这种早期失效，通常在存储芯片上内置MBIST和BISR，存储芯片在出厂前，可以通过ATE调用MBIST对存储芯片进行测试，检测是否存在失效的存储单元，并在检测到存在失效存储单元后，调用BISR对存储芯片进行修复。
其中，MBIST通常采用一种或多种算法为测试存储器一种或多种缺陷类型而特别设计，MBIST可以自动实现存储单元或存储阵列(例如：一行存储单元或一列存储单元)进行内建自测试，MBIST的电子设计自动化(electronic design automatic，EDA)工具支持多种测试算法的自动实现，此外MBIST中还可以包括故障自动诊断功能，方便了故障定位和开发针对性测试向量。
MBIST可以包括测试向量产生电路、BIST控制电路以及响应分析器。测试向量产生电路可生成多种测试向量，不同的测试算法实现的电路所产生的测试向量内容也不同；BIST控制电路通常由状态机实现，控制对存储器的读写操作；响应分析器既可以用比较器实现，也可以用压缩器多输入移位寄存器(MISR)电路实现，它对照已知正常的存储器响应，比较实际存储器模型响应并检测器件错误。
具体地，对存储芯片进行测试、修复的流程可以如图1所示，其中，ATE中的可测试性设计(design for testability，DFT)调用MBIST对存储芯片中的存储单元进行测试，检测是否存在失效的存储单元。若没有失效的存储单元，则DFT继续对存储芯片进行其他测 试。若存在失效的存储单元，可以进一步判断该存储单元是否能够被BISR修复。若判断不能被修复，则认为该芯片失效；若判断该存储单元能够被BISR修复，则DFT可以调用BISR对失效的存储单元进行修复。待BISR修复完成后，再次调用MBIST对存储单元进行测试，检测是否修复成功。若通过测试，则对该存储单元对应的标志位进行烧写，表示该存储单元被修复过；若修复后仍无法通过测试，则认为该芯片失效。
然而，上述对存储芯片的测试、修复均是基于ATE实现的。若一个存储芯片在被置于一个终端上，该终端在使用后存储芯片发生了故障，此时，由于终端并不具备对存储芯片进行测试、修复的功能，可能需要更换存储芯片才能使终端继续工作，给用户造成了不便，降低了用户体验。
为了解决上述问题，本申请实施例提供了一种终端，实现对终端中已经使用的存储器进行修复，有助于提高用户体验。
如图2所示，本申请实施例提供的终端包括判断模块201，处理器202、存储器203和修复模块204。
可选地，修复模块204可以为存储器203中内置的修复模块，例如BISR；或者，修复模块204也可以独立于存储器203。
本申请实施例中的处理器202与存储器203可以位于一个集成电路芯片上，例如，CPU可以与高速缓冲存储器(cache)位于一个芯片上；或者，处理器202与存储器203位于不同的芯片上，二者通过芯片的外部接口实现数据通信。
本申请实施例中的判断模块201也可以与存储器203可以位于一个集成电路芯片上，或者，位于不同的芯片上，二者通过芯片的外部接口实现数据通信。
具体地，本申请实施例中的存储管理***可以设置于终端中，并执行如图3所示的步骤：
步骤301、判断模块201判断存储器203发生异常时，通知处理器201。
步骤302、处理器202在存储器203发生异常时，指令修复模块204对存储器203进行修复。
上述实施例可以应用于终端上，对终端中的存储器进行修复，以实现存储器在使用后发生失效时终端也能够对其进行修复，从而提高用户体验。
在一种可能的设计中，判断模块201可以为所述处理器202中逻辑上的模块。所述处理器202用于指令修复模块204对存储器进行修复。所述处理器202可以为CPU，也可以为诸如应用处理器那样的专门执行特定业务的处理器，甚至是专门执行诸如修复存储器这种辅助工作的低功耗处理器。
处理器在工作中通常都会涉及到从存储器中读写数据，而存储器的故障会带来错误的读写反馈，从而被所述判断模块201侦测到。在这个基础上，可以设定处理器自身有能力发现并指令修复这种存储器的故障，比如应用处理器在执行程序读写存储器时，通过判断模块201发现存储器异常，然后应用处理器指令修复模块对存储器进行修复。在其它可选择的实施例中，也可以设定一个专门的低功耗处理器，在应用处理器发现存储器异常时，来修复存储器。而判断模块可以为应用处理器中的一个逻辑模块，以在应用处理器发生异常时判断该异常是否为存储器异常导致的。判断模块也可以是所述低功耗处理器的逻辑模块，对应用处理器的异常进行分析，然后识别出存储器发生故障。
比如，处理器在运行应用***程序以及其他应用程序时，若程序运行异常并生成异常 报告，判断模块201则根据异常报告判断存储器是否异常。若判断模块201根据异常报告判断存储器异常，则向对应的处理器发送信息，通知存储器异常，然后该对应的处理器则对存储器进行修复。
具体地，判断模块201根据异常报告中的异常原因判断存储器203是否异常。然而，通常情况下，异常报告中不会直接上报存储器异常或其他器件异常。例如，若存储器中部分存储单元失效，将无法从该失效的存储单元中读取数据，也无法将数据写入该失效的存储单元中，从而可能导致读取数据失败或写入数据失败，使得程序无法正常运行，此时生成的异常报告中可能指示获取数据失败。因此，判断模块201需要判断获取数据失败是否为存储器203异常导致的。
可选地，为了提高判断模块201给出的判断结果的准确度，可以预先对多种异常报告中的异常原因，以及最终确定出的故障原因进行统计分析，确定出哪些类型的异常原因可能是由于存储器故障导致的。例如，通常获取地址、数据失败较大可能是由于存储器203异常导致的。
应当理解，虽然读取或写入数据失败较大可能是由于存储器故障导致的，但不排除其他原因导致失败的可能性。在一种可能的实现方式中，本申请实施例提供的存储管理***中还包括测试模块205。处理器202还可以在处理器202指令修复模块204对存储器203进行修复前，进一步指令测试模块205对存储器203进行检测，以最终确定存储器203是否存在失效的存储单元。
可选地，测试模块205可以为存储器203中内置的测试模块，例如MBIST；或者，测试模块205也可以独立于存储器203。
可选地，处理器202可以通过总线分别与测试模块205和修复模块204连接。
在一个具体实施例中，处理器202与修复模块204(BISR)的连接可以如图4所示，其中，BISR分别与存储器中的存储器修复模块(memory repair block，MRB)以及电编程熔丝(EFUSE)器件连接，此外，还设置有一个接口，用于连接终端中的处理器或者ATE中的DFT。如图所示，处理器可以通过设置功能寄存器，以实现控制BISR对存储器进行修复，其中，处理器可以通过X2J(AXI to JTAG)总线与功能寄存器连接进而控制功能寄存器。进一步地，该功能寄存器也可以通过DFT寄存器实现，以避免增加新的器件。
处理器202与测试模块205(MBIST)的连接可以如图5所示，其中，MBIST可以包括一个或多个MBIST控制器(图5中以2个MBIST控制器为例)，每个MBIST用于对其连接的存储阵列进行测试。ATE中的DFT可以通过DFT寄存器控制MBIST对存储阵列进行测试；此外，处理器也可以通过设置功能寄存器实现访问MBIST，从而实现控制MBIST对存储阵列进行测试。进一步地，该功能寄存器也可以通过DFT寄存器实现，以避免增加新的器件。
通过上述实施例，由于处理器202通过总线与MBIST、BISR连接，能够访问存储器203内置的MBIST和BISR，使得在终端正常运行时，终端中的处理器也能够控制MBIST、BISR对存储器进行检测、修复，而不必进行拆机或利用专业维修设备进行维修。
当存储阵列中存在失效存储单元时，通常采用冗余的存储阵列替换存在失效存储单元的存储阵列。具体地，在存储器测试阶段，BISR可以从MRB中读取数据，以获取失效存储单元的位置信息，对读取的数据进行压缩处理后写入到EFUSE器件中，在存储器修复阶段中，BISR从EFUSE器件中读取压缩后的数据，经过解压，将解压后的数据输入到替 换存储阵列所对应的MRB中，以实现利用冗余存储阵列替换失效的存储阵列。
其中，对存在失效存储单元的存储阵列进行替换时，BISR可以将冗余的存储阵列的地址设置为存在失效存储单元的存储阵列的地址，使得后续根据该地址读取数据时能够从冗余的存储阵列中获取到相应数据。
在一种可能的实现方式中，处理器202在指令修复模块204对失效的存储单元进行修复之后，还可以指令测试模块205再次对存储器进行检测，以检测存储器是否修复成功。若修复成功，终端可继续工作或继续对其它部件进行检测，若未能修复成功，存储器可能无法继续正常工作，可能需要更换存储器。
由于对存储器的修复通常是采用冗余存储阵列，对失效的存储单元所在的存储阵列进行替换，而经过替换后的存储阵列通常再次发生故障的可能性极低，故通常仅对一个存储阵列替换一次，而不再对替换后的存储阵列再次替换。因此，在一种可能的实现方式中，可以对存储器中的每个存储阵列设置一个对应的标志位，该标志位用于表示与其对应的存储阵列是否被修复过。
在上述方式中，处理器202可以先读取每个存储阵列的对应的标志位，若该标志位表示其对应的存储阵列没有被修复过，则处理器202指令测试模块205对该存储阵列进行检测，检测是否存在失效的存储单元；若该标志位表示其对应的存储阵列已被修复过，则可以跳过对该存储阵列的检测，继续读取下一个存储阵列的标志位。或者，也可以无需处理器读取标志位，而是通过硬件实现自动跳过已被修复过的存储阵列。
在一种可能的实现方式中，处理器202在执行完上述步骤302之后，可以进一步指令修复模块204设置该标志位，以表示该存储阵列被修复过。
通常情况下，一个终端中可以包括多个处理器，其中，可以包括低功耗处理器。低功耗处理器通常用于执行底层程序，并不用于运行应用***以及基于应用***的应用程序等。在一种可能的实现方式中，终端中处理器在发现终端发生异常后，可以控制该终端重新启动，在终端重启后，可以仅运行该终端中的低功耗处理器，以执行上述步骤301和步骤302。相应地，与存储器中的测试模块2021和修复模块2022连接的处理器，为低功耗处理器。可选地，判断终端异常是否与存储器是否相关的处理器，可以是低功耗处理器，也可以是其他处理器。
为了清楚理解上述实施例，下面结合图6进行说明详细说明。
步骤601、终端运行中发生异常。
步骤602、终端中的处理器判断异常是否与存储器相关。若处理器判断该异常可能与存储器有关，则执行步骤603；否则，可以认为存储器正常，可执行其他检测。
步骤603、终端中的处理器控制该终端重新启动，且终端重启后仅运行低功耗处理器。
步骤604、低功耗处理器控制存储器中的MBIST对存储器进行检测，检测是否存在失效的存储单元。
具体地，MBIST可以对存储器中的存储单元可以进行逐行或逐列的检测，以逐列检测为例，每列存储单元可以称为一个存储阵列，在MBIST对每个存储阵列进行测试之前，低功耗处理器可以读取该存储阵列对应的标志位，判断该存储阵列是否被修复过，若已被修复过，则跳过对该存储阵列的检测，继续读取下一个存储阵列的标志位，若标志位表示该存储阵列未被修复过，则控制MBIST对该存储阵列进行测试，以检测该存储阵列中是否存在失效的存储单元。
步骤605、若检测到存在失效的存储单元，则低功耗处理器控制BISR对存储器进行修复。
BISR可以利用冗余的存储阵列替换存在失效存储单元的存储阵列。具体地，在存储器测试阶段中，BISR可以从MRB中读取数据，以获取失效存储单元的位置信息，对读取的数据进行压缩处理后写入到EFUSE器件中；在存储器修复阶段中，BISR从EFUSE器件中读取压缩后的数据，经过解压，将解压后的数据输入到替换存储阵列所对应的MRB中，以实现利用冗余存储阵列替换失效的存储阵列。
步骤606、低功耗处理器控制MBIST再次对存储器进行检测，检测是否修复成功。若修复成功，则执行步骤607；否则，认为该存储器已无法修复。
若判断存储器无法被修复，该终端可能无法继续正常工作，可能需要经过专业人员或设备对其进行修复，或者更换新的存储器。
步骤607、若修复成功，低功耗处理器控制该终端重新启动该终端，并运行应用***。经过修复后，终端能够正常运行、工作。
基于相同的技术构思，本申请实施例还提供了一种电子设备，可如图7所示，包括：处理器701，判断模块702，以及修复模块703，所述处理器701用于执行程序，并基于所述程序指令访问存储器，所述处理器701还用于在所述程序执行过程中发生异常时生成异常报告，所述判断模块702用于分析所述异常报告，并基于所述异常报告判断存储器是否发生故障，所述修复模块703用于在存储器发生故障时，对存储器进行修复。
在一种可能的实现方式中，该电子设备还包括：测试模块(图中未示出)，用于对所述存储器中的存储单元进行检测；所述修复模块703具体用于：对检测到失效的存储单元进行修复。
在一种可能的实现方式中，所述测试模块在所述修复模块703对所述存储器进行修复之后，还用于：对所述存储器进行测试，确定是否修复成功。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述处理器701在所述测试模块对每个存储阵列进行检测之前，还用于：读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
在一种可能的实现方式中，所述处理器701在所述修复模块703对所述存储器进行修复之后，还用于：设置所述存储器的标志位，设置后的标志位表示所述存储阵列已被修复过。
基于相同的技术构思，本申请实施例还提供了一种电子设备，包括一个或多个处理器和指令存储设备，其特征在于，所述指令存储设备中保存有指令，所述指令用于使得所述一个或多个处理器执行下述动作：
在发生异常时，生成异常报告；
基于所述异常报告，判断异常是否是由存储器故障引起的；
当异常是由存储器故障引起的时候，对存储器进行修复。
在一种可能的实现方式中，所述指令具体用于使得所述一个或多个处理器执行下述动作：对所述存储器中的存储单元进行检测；若检测到失效的存储单元，对所述失效的存储单元进行修复。
在一种可能的实现方式中，所述指令使得所述一个或多个处理器在对所述存储器进行 修复之后，对所述存储器进行测试，确定是否修复成功。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述指令使得所述一个或多个处理器在对每个存储阵列进行检测之前，读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
在一种可能的实现方式中，所述指令使得所述一个或多个处理器在对所述存储器进行修复之后，设置所述存储器的标志位，设置后的标志位表示所述存储阵列已被修复过。
基于相同的技术构思，本申请实施例还提供了一种非易失性计算机可读存储介质，所述可读存储介质包括：
用于接收处理器生成的异常报告的指令；
用于基于所述异常报告，判断异常是否是由存储器故障引起的指令；
用于当异常是由存储器故障引起的时候，对存储器进行修复的指令。
在一种可能的实现方式中，所述用于对存储器进行修复的指令，包括：用于对所述存储器中的存储单元进行检测的指令；用于在检测到失效的存储单元，对所述失效的存储单元进行修复的指令。
在一种可能的实现方式中，所述可读存储介质还包括：用于在对所述存储器进行修复之后，对所述存储器进行测试确定是否修复成功的指令。
在一种可能的实现方式中，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
所述可读存储介质还包括：用于在对每个存储阵列进行检测之前，读取所述存储阵列的标志位的指令，所述标志位表示所述存储阵列未被修复。
在一种可能的实现方式中，所述可读存储介质还包括：用于在对所述存储器进行修复之后，设置所述存储器的标志位的指令，设置后的标志位表示所述存储阵列已被修复过。
本发明实施例中，所述指令存储设备可以为诸如嵌入式多媒体卡(embedded multimedia card，eMMC)/通用闪存存储器(universal flash storage，UFS)的芯片外存储设备。在实际产品中，计算机需要运行的程序指令通常被预先保存在eMMC和UFS中。此外，所述指令存储设备也可为内存，比如双倍速率同步动态随机存储器(double data rate memory，DDR memory)。如上文所述程序指令通常被预先保存在eMMC和UFS中，然后在需要执行的时候被写入内存中，从而提高处理速度。
本领域内的技术人员应明白，本申请的实施例可提供为方法、***、或计算机程序产品。因此，本申请可采用完全硬件实施例、完全软件实施例、或结合软件和硬件方面的实施例的形式。而且，本申请可采用在一个或多个其中包含有计算机可用程序代码的计算机可用存储介质(包括但不限于磁盘存储器、光学存储器等)上实施的计算机程序产品的形式。
显然，本领域的技术人员在本申请的技术方案的基础上，对本申请进行的等同替换、改进等，均应包括在本申请的保护范围之内。

Claims (14)

  1. 一种终端，其特征在于，所述存储器管理***包括判断模块，处理器，存储器，修复模块；
    所述判断模块用于在所述存储器发生异常时，通知所述处理器；
    所述处理器用于在所述存储器发生异常时，指令所述修复模块对所述存储器进行修复。
  2. 如权利要求1所述的终端，其特征在于，还包括：测试模块；
    所述处理器在指令所述修复模块对存储器进行修复时，具体用于：
    指令所述测试模块对所述存储器中的存储单元进行检测；
    若检测到失效的存储单元，指令所述修复模块对所述失效的存储单元进行修复。
  3. 如权利要求2所述的终端，其特征在于，所述处理器在指令所述修复模块对所述存储器进行修复之后，还用于：
    指令所述测试模块对所述存储器进行测试，确定是否修复成功。
  4. 如权利要求2所述的终端，其特征在于，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
    所述处理器在指令所述测试模块对每个存储阵列进行检测之前，还用于：
    读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
  5. 如权利要求4所述的终端，其特征在于，所述处理器在指令所述修复模块对所述存储器进行修复之后，还用于：
    设置所述存储器的标志位，设置后的标志位表示所述存储阵列已被修复过。
  6. 一种电子设备，其特征在于，包括处理器，判断模块，以及修复模块，所述处理器用于执行程序，并基于所述程序指令访问存储器，所述处理器还用于在所述程序执行过程中发生异常时生成异常报告，所述判断模块用于分析所述异常报告，并基于所述异常报告判断存储器是否发生故障，所述修复模块用于在存储器发生故障时，对存储器进行修复。
  7. 如权利要求6所述的电子设备，其特征在于，还包括：
    测试模块，用于对所述存储器中的存储单元进行检测；
    所述修复模块具体用于：对检测到失效的存储单元进行修复。
  8. 如权利要求7所述的电子设备，其特征在于，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
    所述处理器在所述测试模块对每个存储阵列进行检测之前，还用于：读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
  9. 一种电子设备，包括一个或多个处理器和指令存储设备，其特征在于，所述指令存储设备用于保存指令，所述指令用于使得所述一个或多个处理器执行下述动作：
    在发生异常时，生成异常报告；
    基于所述异常报告，判断异常是否是由存储器故障引起的；
    当异常是由存储器故障引起的时候，对存储器进行修复。
  10. 如权利要求9所述的电子设备，其特征在于，所述指令具体用于使得所述一个或多个处理器执行下述动作：对所述存储器中的存储单元进行检测；若检测到失效的存储单 元，对所述失效的存储单元进行修复。
  11. 如权利要求10所述的电子设备，其特征在于，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
    所述指令使得所述一个或多个处理器在对每个存储阵列进行检测之前，读取所述存储阵列的标志位，所述标志位表示所述存储阵列未被修复。
  12. 一种非易失性计算机可读存储介质，其特征在于，所述可读存储介质包括：
    用于接收处理器生成的异常报告的指令；
    用于基于所述异常报告，判断异常是否是由存储器故障引起的指令；
    用于当异常是由存储器故障引起的时候，对存储器进行修复的指令。
  13. 如权利要求12所述的非易失性计算机可读存储介质，其特征在于，所述用于对存储器进行修复的指令，包括：
    用于对所述存储器中的存储单元进行检测的指令；
    用于在检测到失效的存储单元，对所述失效的存储单元进行修复的指令。
  14. 如权利要求13所述的非易失性计算机可读存储介质，其特征在于，所述存储器中的每个存储阵列设置有一个标志位，所述标志位用于表示所述存储阵列是否被修复过，所述每个存储阵列包括多个存储单元；
    所述可读存储介质还包括：
    用于在对每个存储阵列进行检测之前，读取所述存储阵列的标志位的指令，所述标志位表示所述存储阵列未被修复。
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