WO2019184543A1 - 显示面板及其制作方法以及显示装置 - Google Patents

显示面板及其制作方法以及显示装置 Download PDF

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Publication number
WO2019184543A1
WO2019184543A1 PCT/CN2019/070190 CN2019070190W WO2019184543A1 WO 2019184543 A1 WO2019184543 A1 WO 2019184543A1 CN 2019070190 W CN2019070190 W CN 2019070190W WO 2019184543 A1 WO2019184543 A1 WO 2019184543A1
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Prior art keywords
substrate
signal line
region
display panel
area
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PCT/CN2019/070190
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English (en)
French (fr)
Inventor
张迪
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/611,647 priority Critical patent/US11215894B2/en
Publication of WO2019184543A1 publication Critical patent/WO2019184543A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133354—Arrangements for aligning or assembling substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133388—Constructional arrangements; Manufacturing methods with constructional differences between the display region and the peripheral region
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers

Definitions

  • Embodiments of the present disclosure relate to the field of display technology, and in particular, to a display panel, a method of fabricating the same, and a display device.
  • TFT liquid crystal display devices with low power consumption, high resolution, fast response speed and high aperture ratio have gradually become mainstream, and have been widely used.
  • electronic devices such as LCD TVs, smart phones, tablets, and digital electronic devices.
  • a display panel includes a display area at the center and a bezel area surrounding the display area.
  • the display panel further includes: a first substrate and a second substrate disposed opposite to each other; a patterned black matrix layer between the first substrate and the second substrate; and disposed in the frame region
  • the first substrate is adjacent to the signal line array on one side of the second substrate.
  • the signal line array includes a common electrode feedback signal line and a clock signal line.
  • the bezel area includes a first area in which the common electrode feedback signal line is disposed and a second area in which the clock signal line is disposed.
  • the patterned black matrix layer includes a hollowed out region in the bezel area. An orthographic projection of at least one of the first region and the second region on the first substrate at least partially overlaps an orthographic projection of the hollow region on the first substrate.
  • the patterned black matrix layer is disposed on a side of the signal line array away from the first substrate, or the second substrate is adjacent to the first On one side of a substrate.
  • the clock signal line and the common electrode feedback signal line are directly adjacent to each other, and at least one of the first region and the second region is The orthographic projection on the first substrate completely coincides with the orthographic projection of the hollowed out region on the first substrate.
  • the signal line array further includes a signal line sub-array disposed between the clock signal line and the common electrode feedback signal line, and the second The area includes a first sub-area configured with the signal line sub-array and a second sub-area configured with the clock signal line.
  • an orthographic projection of at least one of the first region, the first sub-region, and the second sub-region on the first substrate The orthographic projections of the hollow regions on the first substrate completely coincide.
  • the first sub-region further includes a first portion adjacent to the clock signal line and a second portion near the common electrode feedback signal line, wherein the The orthographic projection of the first portion or the second portion on the first substrate completely coincides with the orthographic projection of the hollowed out region on the first substrate.
  • the patterned black matrix layer is made of a first black matrix material
  • the display panel further includes a second black matrix filled in the cutout region The material, the second black matrix material has a resistivity greater than a resistivity of the first black matrix material.
  • the hollowed out area is annular.
  • the first portion or the second portion has a width of 15 to 25 ⁇ m.
  • a display device is also provided.
  • the display device includes the display panel according to any of the preceding embodiments.
  • a method of fabricating a display panel includes a display area at the center and a bezel area surrounding the display area.
  • the manufacturing method includes: providing a first substrate and a second substrate opposite to each other; forming a patterned black matrix layer between the first substrate and the second substrate, the patterned black matrix layer including a hollowed out area in the bezel area; and an array of signal lines located in the bezel area on a side of the first substrate adjacent to the second substrate.
  • the signal line array includes a common electrode feedback signal line and a clock signal line.
  • the bezel area includes a first area in which the common electrode feedback signal line is disposed and a second area in which the clock signal line is disposed.
  • An orthographic projection of at least one of the first region and the second region on the first substrate at least partially overlaps an orthographic projection of the hollow region on the first substrate.
  • FIG. 1 schematically shows a cross-sectional view of a display panel according to the related art
  • FIG. 2A schematically illustrates a cross-sectional view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 2B schematically illustrates a cross-sectional view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 3 schematically illustrates a partial plan view of a signal line array in a display panel in accordance with an embodiment of the present disclosure
  • FIG. 4A schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 4B schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 4C schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 5 schematically illustrates a partial plan view of a signal line array in a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6A schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6B schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6C schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6D schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6E schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6F schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • 6G schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 6H schematically illustrates a partial top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 7 schematically illustrates a cross-sectional view of a display panel in accordance with an embodiment of the present disclosure
  • Figure 8 is a schematic partial plan view of the display panel of Figure 7;
  • FIG. 9 schematically illustrates a top view of a display panel in accordance with an embodiment of the present disclosure.
  • FIG. 10 schematically illustrates a top view of a display panel in accordance with an embodiment of the present disclosure
  • FIG. 11 schematically illustrates a flow chart for a method of fabricating a display panel in accordance with an embodiment of the present disclosure.
  • FIG. 1 schematically shows a cross-sectional view of a display panel according to the related art.
  • the display panel includes a display area AA' located at the center and a bezel area BB' surrounding the display area AA'.
  • the display panel in FIG. 1 includes a base substrate 1, a signal line array 2, and a patterned black matrix layer 3 from bottom to top.
  • the signal line array may include signal lines such as a clock signal line, a common electrode feedback signal line, a common electrode signal line, and a ground line.
  • a black matrix layer is placed over all signal lines.
  • an embodiment of the present disclosure provides a display panel and a method of fabricating the same, and a corresponding display device, for the purpose of, for example, reducing and even eliminating coupling capacitance in a display device to avoid generation of horizontal stripes. .
  • a display panel is provided.
  • 2A schematically illustrates a cross-sectional view of a display panel according to an embodiment of the present disclosure
  • FIG. 2B schematically illustrates a cross-sectional view of a display panel according to another embodiment of the present disclosure.
  • the display panel includes: a first substrate 10 and a second substrate 40 disposed opposite to each other, a signal line array 20 disposed on an upper surface of the first substrate 10, And a patterned black matrix layer 30 disposed on the upper surface of the first substrate 10 (FIG. 2B) or the lower surface of the second substrate 40 (FIG. 2A).
  • the entire display panel is divided into two areas, that is, a central display area AA' and a surrounding border area BB'.
  • the signal line array includes a clock signal line and a common electrode feedback signal line.
  • the bezel area BB' of the display panel includes a first area A1 configured with a common electrode feedback signal line and a second area A2 configured with a clock signal line.
  • the patterned black matrix layer 30 includes a hollowed out region 31 located in the bezel area BB', wherein the orthographic projection of at least one of the first region A1 and the second region A2 on the first substrate 10 and the hollowed out region 31 are The orthographic projections on the first substrate 10 have overlapping regions AA, i.e., at least partially overlap.
  • the display panel further includes a liquid crystal layer 50 disposed between the first substrate 10 and the second substrate 40.
  • the expression "the patterned black matrix layer includes a hollow region” refers to a blank region in which no black matrix material is disposed in the patterned black matrix layer. That is, there is an opening in the patterned black matrix layer. It can be seen that, for example, as shown in FIG. 2B, due to the presence of the hollow region 31 in the patterned black matrix layer 30, the clock signal line and the common electrode feedback signal line can no longer generate signals between each other by means of the black matrix layer. interference.
  • the first substrate 10 and the second substrate 40 may be a glass substrate, a quartz substrate, a plastic substrate, or the like.
  • the embodiments of the present disclosure are not limited in any way.
  • FIG. 2A is an example in which a patterned black matrix layer is disposed on a second substrate
  • FIG. 2B is an example in which a patterned black matrix layer is disposed on a first substrate.
  • the embodiments of the present disclosure are also not limited in any way.
  • the signal line array may further include other signal lines, such as an initial signal line, a ground line, and the like.
  • the number of clock signal lines may also be one or more, and the embodiment of the present disclosure does not limit this.
  • each signal line can also take any suitable arrangement.
  • the clock signal line may be disposed on a side of the common electrode feedback signal line near the display area.
  • the clock signal line may also be disposed on a side of the common electrode feedback signal line away from the display area.
  • 2A and 2B illustrate that the clock signal line is disposed on the side of the common electrode feedback signal line close to the display area, and the embodiment of the present disclosure is not limited thereto.
  • this may include, for example, a case where the orthographic projection of the first region A1 on the first substrate 10 coincides with the orthographic projection of the cutout region 31 on the first substrate 10; the positive of the second region A2 on the first substrate 10 Projection and orthographic projection of the hollow region 31 on the first substrate 10 coincide; orthographic projection of both the first region A1 and the second region A2 on the first substrate 10 and the orthographic projection of the hollow region 31 on the first substrate 10 The coincidence; the orthographic projection of the second region A2 on the first substrate 10 overlaps with the orthographic projection of the hollow region 31 on the first substrate 10, and the like.
  • the embodiment of the present disclosure is not limited as long as it is finally ensured that a coupling capacitance is not formed between the clock signal line and the common electrode feedback signal line, or even if a coupling capacitance is formed. Thereby, mutual coupling between the clock signal line and the common electrode feedback signal line can be reduced and even eliminated, thereby reducing signal crosstalk between the signal lines.
  • FIG. 2A and FIG. 2B illustrate that the orthogonal projection of the second region A2 on the first substrate 10 and the orthographic projection of the hollow region 31 on the first substrate 10 are completely overlapped, and the present disclosure The embodiment is not limited to this.
  • An embodiment of the present disclosure provides a display panel including: a first substrate and a second substrate disposed opposite to each other, a signal line array disposed on the first substrate, and a patterning disposed on the first substrate or the second substrate Black matrix layer.
  • the signal line array includes a clock signal line and a common electrode feedback signal line
  • the bezel area of the display panel includes a first area in which the common electrode feedback signal line is disposed and a second area in which the clock signal line is disposed.
  • the patterned black matrix layer includes a hollowed out area located in the bezel area. There is an overlap region between the orthographic projection of the at least one of the first region and the second region on the first substrate and the orthographic projection of the hollow region on the first substrate.
  • the clock can be avoided by designing an orthographic projection of at least one of the first region and the second region on the first substrate to have an overlapping region with the orthographic projection of the hollow region on the first substrate A coupling capacitance is formed between the signal line and the common electrode feedback signal line and the problem of horizontal horizontal stripes is eliminated.
  • the patterned black matrix layer is disposed on the first substrate, that is, the patterned black matrix layer is located on a side of the signal line array away from the first substrate.
  • the patterned black matrix layer is disposed on the second substrate, that is, the patterned black matrix layer is located on a side of the second substrate adjacent to the first substrate.
  • FIG. 3 a partial top view of a signal line array in a display panel in accordance with an embodiment of the present disclosure is schematically illustrated. As shown in FIG. 3, in the display panel provided by the embodiment of the present disclosure, the clock signal line CLK and the common electrode feedback signal line Vcom-Feedback in the signal line array are directly adjacent to each other.
  • FIG. 4A schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 4A is an orthographic projection of the first area A1 on the first substrate and the hollowed out area 31 on the first substrate.
  • the orthographic projections are completely coincident as an example.
  • FIG. 4B schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG.
  • FIG. 4B is an orthographic projection of the second area A2 on the first substrate and the hollowed out area 31 at the first The orthographic projections on the substrate are completely overlapped as an example for explanation.
  • FIG. 4C schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 4C is an orthographic projection on the first substrate together with both the first area A1 and the second area A2 An example in which the orthographic projection of the hollow region on the first substrate completely coincides is described.
  • the clock signal line CLK and the common electrode feedback signal line Vcom-Feedback are directly adjacent, and the orthographic projection and hollowing of at least one of the first area A1 and the second area A2 on the first substrate The orthographic projections of the regions on the first substrate are completely coincident.
  • the coupling capacitance is no longer formed between the clock signal line CLK and the common electrode feedback signal line Vcom-Feedback, so that the coupling between the clock signal line CLK and the common electrode feedback signal line Vcom-Feedback can be eliminated, and the coupling can be reduced.
  • the signal line array may further include: a first signal line sub-array disposed at a side of the common electrode feedback signal line Vcom-Feedback away from the clock signal line CLK; and a feedback provided on the clock signal line CLK away from the common electrode A second sub-array of signal lines at one side of the signal line Vcom-Feedback.
  • the orthographic projection of the hollow region on the first substrate may cover the orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • the orthographic projection of the hollowed out region on the first substrate may also not cover the orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • 4A-4C illustrate an example in which an orthographic projection of a hollow region on a first substrate and an orthographic projection of a first signal sub-array and a second signal sub-array on a first substrate are not present, and The disclosed embodiments are not limited thereto.
  • the orthographic projection of the cutout region on the first substrate is designed not to cover the orthographic projection of the first signal sub-array and the second signal sub-array on the first substrate.
  • FIG. 5 schematically illustrates a partial top view of a signal line array in a display panel in accordance with an embodiment of the present disclosure.
  • the signal line array may further include a signal line sub-array disposed between the clock signal line CLK and the common electrode feedback signal line Vcom-Feedback.
  • the second area A2 may include: a first sub-area A21 configured with a signal line sub-array; and a second sub-area A22 configured with a clock signal line CLK.
  • the signal line array may further include: a first signal line sub-array disposed at a side of the common electrode feedback signal line Vcom-Feedback away from the clock signal line CLK; and being disposed away from the clock signal line CLK A common sub-array of signal lines at one side of the common electrode feedback signal line Vcom-Feedback.
  • the orthogonal projection of the at least one of the first region A1, the first sub-region A21, and the second sub-region A22 on the first substrate completely coincides with the orthographic projection of the hollow region on the first substrate.
  • FIG. 6A schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6A is an orthographic projection of the first sub-area A21 on the first substrate and the hollowed out region 31 on the first substrate.
  • FIG. 6B schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG.
  • FIG. 6B is an orthographic projection of the second sub-area A22 on the first substrate and the hollowed out area 31 at the first The orthographic projections on the substrate are completely overlapped as an example for explanation.
  • FIG. 6C schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6C is a positive on the first substrate together with both the first sub-area A21 and the second sub-area A22. The projection and the evacuation of the hollow region 31 on the first substrate are completely overlapped as an example.
  • the orthographic projection of the hollow region on the first substrate may cover the orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • the orthographic projection of the hollowed out region on the first substrate may also not cover the orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • 6A-6C illustrate an example in which an orthographic projection of a hollow region on a first substrate and an orthographic projection of a first signal sub-array and a second signal sub-array on a first substrate are not present, and The disclosed embodiments are not limited thereto.
  • the orthographic projection of the first region A1 on the first substrate completely coincides with the orthographic projection of the hollow region 31 on the first substrate.
  • the orthographic projection of at least one of the first sub-region A21 and the second sub-region A22 on the first substrate completely coincides with the orthographic projection of the hollow region 31 on the first substrate.
  • FIG. 6D schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6D is an orthographic projection on the first substrate together with both the first area A1 and the first sub-area A21
  • FIG. 6D is an orthographic projection on the first substrate together with both the first area A1 and the first sub-area A21
  • FIG. 6E schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6E is a positive on the first substrate together with both the first area A1 and the second sub-area A22 The projection and the evacuation of the hollow region 31 on the first substrate are completely overlapped as an example.
  • FIG. 6F schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6F is in a first area A1, a first sub-area A21, and a second sub-area A22.
  • the orthographic projection on a substrate and the orthographic projection of the hollow region 31 on the first substrate are completely overlapped as an example.
  • the orthographic projection of the hollowed out region on the first substrate may cover an orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • the orthographic projection of the hollowed out region on the first substrate may also not cover the orthographic projection of the first signal sub-array and/or the second signal sub-array on the first substrate.
  • 6D-6F illustrate an example in which an orthographic projection of a hollow region on a first substrate and an orthographic projection of a first signal sub-array and a second signal sub-array on a first substrate are not present, and The disclosed embodiments are not limited thereto.
  • FIG. 6G schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6G is an orthographic projection of the first area A1 on the first substrate and the hollowed out area 31 on the first substrate.
  • the orthographic projections are completely coincident as an example.
  • the first sub-area A21 may further include, for example, a first portion a1 close to the common electrode feedback signal line and a second portion a2 near the clock signal line, wherein the first portion a1 or the second portion a2 is on the first substrate
  • the orthographic projection completely coincides with the orthographic projection of the cutout region 31 on the first substrate.
  • FIG. 6H schematically illustrates a partial plan view of a display panel according to an embodiment of the present disclosure, wherein FIG. 6H is an orthographic projection of the first portion a1 on the first substrate and the hollowed out region 31 on the first substrate.
  • the orthographic projections are completely overlapped as an example for explanation.
  • the width of the first portion a1 or the second portion a2 is 15-25 microns, preferably 20 microns.
  • FIG. 7 schematically illustrates a cross-sectional view of a display panel according to an embodiment of the present disclosure
  • FIG. 8 illustrates a corresponding top view of the display panel of FIG.
  • the patterned black matrix layer 30 is made of a first black matrix material, and the hollow region 31 may be filled with a second black matrix material, wherein The resistivity of the second black matrix material is greater than the resistivity of the first black matrix material. Also, in this manner, the coupling between the common electrode feedback signal line Vcom-Feedback and the clock signal line CLK can be reduced.
  • FIG. 7 is an example in which the orthographic projection of the second sub-area A22 on the first substrate 10 and the orthographic projection of the hollow region on the first substrate 10 are completely overlapped.
  • the orthographic projection of the first sub-area A21 on the first substrate 10 and the orthographic projection of the hollow region on the first substrate 10 may be completely Coincident, that is, as shown in FIG.
  • the orthographic projection of the first region A1 on the first substrate 10 may completely coincide with the orthographic projection of the hollow region on the first substrate 10, or the second region as a whole (ie, A21+A22)
  • the orthographic projection on the first substrate 10 coincides with the orthographic projection of the cutout region on the first substrate 10.
  • the embodiments of the present disclosure are not limited in any way.
  • FIG. 9 schematically illustrates a top view of a display panel according to an embodiment of the present disclosure, wherein a central display area of the display panel is schematically illustrated by a white dashed line.
  • the patterned black matrix layer includes two longitudinal hollow areas located in the side frame areas on both sides.
  • FIG. 9 is an example in which the orthographic projection of the first sub-area A21 on the first substrate and the orthographic projection of the hollow region on the first substrate are completely overlapped.
  • FIG. 10 schematically illustrates a top view of a display panel in accordance with an embodiment of the present disclosure, wherein the central display area of the display panel is schematically illustrated by means of a white dashed line as well.
  • the hollowed out area 31 is an annular area located in the surrounding border area.
  • the orthographic projection of the hollow region on the first substrate may cover the first region, the first sub-region, the second sub-region, and any one of the first portion and the second portion of the first sub-region or combination An orthographic projection on the first substrate.
  • the embodiments of the present disclosure are not limited in any way.
  • FIG. 10 is an example in which the orthographic projection of the hollow region on the first substrate covers the orthographic projection of the first sub-region A21 on the first substrate.
  • the hollowed out area is designed to be annular.
  • the black matrix layer portion covering the display area and the black matrix layer portion covering the non-display area are separated from each other, thereby avoiding covering the black matrix layer portion of the display area and the black covering the non-display area. Signal interference between the matrix layer sections and further enhances the display effect.
  • FIG. 3 to FIG. 10 can be applied to a display panel in which a patterned black matrix layer is disposed on a first substrate, and a patterned black matrix layer is disposed in the first In the display panel on the two substrates.
  • the embodiments of the present disclosure are not limited in any way.
  • FIG. 11 schematically illustrates a flow chart of a method of fabricating a display panel in accordance with an embodiment of the present disclosure.
  • a display panel includes a display area located at a center and a frame area surrounding the display area, and the manufacturing method of the display panel specifically includes the following steps.
  • Step 100 providing a first substrate and a second substrate opposite to each other.
  • the first substrate may be a glass substrate, a quartz substrate, a plastic substrate, or the like.
  • the embodiments of the present disclosure are not limited in any way.
  • the second substrate may also be a glass substrate, a quartz substrate, a plastic substrate, or the like.
  • the embodiments of the present disclosure are also not limited in any way.
  • Step 200 forming a patterned black matrix layer between the first substrate and the second substrate such that the patterned black matrix layer includes a hollow region located in the frame region.
  • the patterned black matrix layer may be formed on a side of the signal line array away from the first substrate.
  • the patterned black matrix layer may also be formed on a side of the second substrate adjacent to the first substrate.
  • the signal line array includes a clock signal line and a common electrode feedback signal line.
  • the bezel area of the display panel includes a first area configured with a common electrode feedback signal line and a second area configured with a clock signal line.
  • the orthographic projection of at least one of the first region and the second region on the first substrate at least partially overlaps the orthographic projection of the hollow region on the first substrate.
  • the expression "the patterned black matrix layer includes a hollow region” means that there is a region in the patterned black matrix layer where no black matrix material is provided. That is, there is an opening in the patterned black matrix layer. Thereby, signal interference between the clock signal line and the common electrode feedback signal line can be eliminated by means of the hollowed out region in the patterned black matrix layer.
  • An embodiment of the present disclosure provides a method of fabricating a display panel, including: providing a first substrate and a second substrate; forming a signal line array on the first substrate; and the signal line array includes: providing a first substrate opposite to each other a second substrate; forming a patterned black matrix layer between the first substrate and the second substrate, the patterned black matrix layer including a hollow region in the frame region; and forming on a side of the first substrate adjacent to the second substrate An array of signal lines located in the border area.
  • the signal line array includes a common electrode feedback signal line and a clock signal line.
  • the bezel area includes a first area configured with a common electrode feedback signal line and a second area configured with a clock signal line.
  • the orthographic projection of at least one of the first region and the second region on the first substrate at least partially overlaps the orthographic projection of the hollow region on the first substrate.
  • an orthographic projection of at least one of the first region and the second region on the first substrate to have an overlapping region with an orthographic projection of the hollow region on the first substrate, it is possible to reduce and even The coupling between the clock signal line and the common electrode feedback signal line is eliminated, signal crosstalk between the signal lines is reduced, and horizontal horizontal stripes are avoided.
  • the clock signal line and the common electrode feedback signal line are directly adjacent, and the patterned black matrix layer is formed such that at least one of the first region and the second region is on the first substrate
  • the orthographic projection coincides with the orthographic projection of the hollowed out region on the first substrate.
  • the signal line array further includes a signal line sub-array disposed between the clock signal line and the common electrode feedback signal line, and the second area includes the first portion configured with the signal line sub-array The sub-area and the second sub-area configured with the clock signal line.
  • the patterned black matrix layer is formed such that the orthographic projection of the at least one of the first region, the first sub-region, and the second sub-region on the first substrate and the hollowed out region on the first substrate The orthographic projections coincide.
  • the first sub-region may further include a first portion close to, for example, a common electrode feedback signal line and a second portion close to, for example, a clock signal line, and an orthographic projection and a hollow portion of the first portion or the second portion on the first substrate The orthographic projections on the first substrate coincide.
  • the method for fabricating a display panel may further include: filling a hollow region of the patterned black matrix layer with a resistor having a first black matrix material for forming a patterned black matrix layer; A second black matrix material with a high resistivity.
  • a resistor having a first black matrix material for forming a patterned black matrix layer
  • a second black matrix material with a high resistivity.
  • an embodiment of the present disclosure further provides a display device including: the display panel described in any of the above embodiments.
  • the implementation principle and implementation effect of such a display device are similar to those of the display panel described above, and will not be described herein.
  • the display device may be a liquid crystal display (LCD), an electronic paper, an organic light-emitting diode (OLED) display, a mobile phone, a tablet computer, a television, a display, a notebook computer. Any product or component that has a display function, such as a digital photo frame or a navigator.
  • LCD liquid crystal display
  • OLED organic light-emitting diode

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Abstract

一种显示面板及其制作方法以及显示装置。显示面板包括位于中心的显示区(AA')和围绕显示区(AA')的边框区(BB')。显示面板进一步包括：相对设置的第一基板(10)和第二基板(40)；位于第一基板(10)与第二基板(40)之间的图案化黑矩阵层(30)；以及在边框区(BB')中设置在第一基板(10)靠近第二基板(40)的一侧上的信号线阵列(20)。信号线阵列(20)包括时钟信号线和公共电极反馈信号线。边框区(BB')包括配置有公共电极反馈信号线的第一区域(A1)和配置有时钟信号线的第二区域(A2)。图案化黑矩阵层(30)包括位于边框区(BB')中的镂空区域(31)。第一区域(A1)和第二区域(A2)中的至少一个在第一基板(10)上的正投影与镂空区域(31)在第一基板(10)上的正投影至少部分地重叠。

Description

显示面板及其制作方法以及显示装置
对相关申请的交叉引用
本申请要求2018年3月26日提交的中国专利申请号201810256464.7的优先权，该中国专利申请以其整体通过引用并入本文。
技术领域
本公开的实施例涉及显示技术领域，并且具体地涉及显示面板及其制作方法以及显示装置。
背景技术
随着薄膜晶体管(Thin Film Transistor，简称TFT)液晶显示技术的不断发展，具备功耗低、分辨率高、反应速度快以及开口率高等特点的TFT液晶显示装置逐渐成为主流，并且已经广泛应用于各种电子设备中，诸如，液晶电视、智能手机、平板电脑以及数字电子设备。
已经发现，在目前的TFT液晶显示装置中，由于信号线之间容易形成耦合电容，并且信号线之间的这种耦合作用会引发信号串扰，所以导致TFT液晶显示装置的显示画面产生水平横纹。
发明内容
根据本公开的一个方面，提供了一种显示面板。所述显示面板包括位于中心的显示区和围绕所述显示区的边框区。所述显示面板进一步包括：相对设置的第一基板和第二基板；位于所述第一基板与所述第二基板之间的图案化黑矩阵层；以及在所述边框区中设置在所述第一基板靠近所述第二基板的一侧上的信号线阵列。所述信号线阵列包括公共电极反馈信号线和时钟信号线。所述边框区包括配置有所述公共电极反馈信号线的第一区域和配置有所述时钟信号线的第二区域。所述图案化黑矩阵层包括位于所述边框区中的镂空区域。所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影至少部分地重叠。
根据本公开的实施例，在以上提出的显示面板中，所述图案化黑矩阵层设置在所述信号线阵列远离所述第一基板的一侧上，或者所述第二基板靠近所述第一基板的一侧上。
根据本公开的实施例，在以上提出的显示面板中，所述时钟信号 线和所述公共电极反馈信号线彼此直接相邻，并且所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
根据本公开的实施例，在以上提出的显示面板中，所述信号线阵列还包括设置在所述时钟信号线和所述公共电极反馈信号线之间的信号线子阵列，并且所述第二区域包括配置有所述信号线子阵列的第一子区域和配置有所述时钟信号线的第二子区域。
根据本公开的实施例，在以上提出的显示面板中，所述第一区域、所述第一子区域和所述第二子区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
根据本公开的实施例，在以上提出的显示面板中，所述第一子区域进一步包括靠近所述时钟信号线的第一部分和靠近所述公共电极反馈信号线的第二部分，其中，所述第一部分或所述第二部分在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
根据本公开的实施例，在以上提出的显示面板中，所述图案化黑矩阵层由第一黑矩阵材料制成，并且所述显示面板还包括填充在所述镂空区域中的第二黑矩阵材料，所述第二黑矩阵材料的电阻率大于所述第一黑矩阵材料的电阻率。
根据本公开的实施例，在以上提出的显示面板中，所述镂空区域呈环形。
根据本公开的实施例，在以上提出的显示面板中，所述第一部分或所述第二部分的宽度为15-25微米。
根据本公开的另一方面，还提供了一种显示装置。所述显示装置包括根据前面任一项实施例所述的显示面板。
根据本公开的又一方面，还提供了一种用于显示面板的制作方法。所述显示面板包括位于中心的显示区和围绕所述显示区的边框区。所述制作方法包括：提供彼此相对的第一基板和第二基板；在所述第一基板与所述第二基板之间形成图案化黑矩阵层，所述图案化黑矩阵层包括位于所述边框区中的镂空区域；以及在所述第一基板靠近所述第二基板的一侧上形成位于所述边框区中的信号线阵列。所述信号线阵列包括公共电极反馈信号线和时钟信号线。所述边框区包括配置有所 述公共电极反馈信号线的第一区域和配置有所述时钟信号线的第二区域。所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影至少部分地重叠。
本公开的特征和优点将在随后的说明书实施例中阐述，并且，部分地从说明书实施例中变得显而易见，或者通过实施本公开而了解。本公开的实施例的目的和其它优点可以通过在说明书、权利要求书以及附图中特别指出的结构来实现和获得。
附图说明
附图用来提供对本公开中的技术方案的进一步理解，并且构成说明书的一部分。附图与本申请的实施例一起用于解释本公开中的技术方案，但是并不构成对本公开中的技术方案的任何限制。
图1示意性示出了根据相关技术的显示面板的截面图；
图2A示意性示出了根据本公开的实施例的显示面板的截面图；
图2B示意性示出了根据本公开的实施例的显示面板的截面图；
图3示意性示出了根据本公开的实施例的显示面板中的信号线阵列的部分俯视图；
图4A示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图4B示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图4C示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图5示意性示出了根据本公开的实施例的显示面板中的信号线阵列的部分俯视图；
图6A示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6B示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6C示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6D示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6E示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6F示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6G示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图6H示意性示出了根据本公开的实施例的显示面板的部分俯视图；
图7示意性示出了根据本公开的实施例的显示面板的截面图；
图8示意性示出了图7中的显示面板的部分俯视图；
图9示意性示出了根据本公开的实施例的显示面板的俯视图；
图10示意性示出了根据本公开的实施例的显示面板的俯视图；以及
图11示意性示出了根据本公开的实施例的用于显示面板的制作方法的流程图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
在所附流程图中示出的步骤可以在诸如一组计算机之类的可用于执行指令的计算机***上执行。而且，虽然在流程图中示出了逻辑顺序，但是在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤。
除非另外定义，否则在本公开的实施例中使用的技术术语或者科学术语应当为本公开所属技术领域内的一般技术人员所理解的通常意义。在本公开的实施例中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而是用来区分不同的组成部分。诸如“包括”或者“包含”之类的词语意指的是，在该词语前面的元件不仅涵盖在该词语后面列举的元件或者物件及其等同物，而且还不排除其它的元件或者物件。诸如“上”、“下”、“左”、“右”之类的词语仅仅用于表示相对位置关系。因此，当所描述的对象的绝对位置发生改变时，这种相对位置关系也可能相应地发生改变。
图1示意性示出了根据相关技术的显示面板的截面图。如图1所示，显示面板包括位于中心的显示区AA′和包围该显示区AA′的边框区BB′。在层级结构方面，图1中的显示面板自下而上包括衬底基板1、信号线阵列2和图案化黑矩阵层3。具体地，信号线阵列可以包括时钟信号线、公共电极反馈信号线、公共电极信号线和地线等信号线。通常，在所有信号线上方设置有黑矩阵层。经过实际测量与验证，已经发现，在上述显示装置中，公共电极反馈信号线和时钟信号线可以通过黑矩阵层而形成耦合电容，从而引发信号串扰并且导致水平横纹的产生。
为了减少耦合电容，可以尝试增大公共电极反馈信号线和时钟信号线之间的距离。但是，相关的显示装置大部分为窄边框或无边框产品，并且这使得没有更多的空间来增大公共电极反馈信号线和时钟信号线之间的距离。因此，也就无法进一步减小例如公共电极反馈信号线和时钟信号线之间的耦合电容并且避免水平横纹的产生。
鉴于以上分析，出于例如减小并且甚至消除显示装置中的耦合电容从而避免水平横纹的产生这一目的，本公开的实施例提供了一种显示面板及其制作方法，以及对应的显示装置。
根据本公开的实施例，提供了一种显示面板。图2A示意性示出了根据本公开的一个实施例的显示面板的截面图，并且图2B示意性示出了根据本公开的另一个实施例的显示面板的截面图。如图2A和图2B所示，在本公开的实施例中，显示面板包括：相对设置的第一基板10和第二基板40、设置在第一基板10的上表面上的信号线阵列20、以及设置在第一基板10的上表面上(图2B)或第二基板40的下表面上(图2A)的图案化黑矩阵层30。此外，整个显示面板划分为两个区域，即，位于中心的显示区AA′和位于四周的边框区BB′。
具体地，信号线阵列包括时钟信号线和公共电极反馈信号线。显示面板的边框区BB′包括配置有公共电极反馈信号线的第一区域A1和配置有时钟信号线的第二区域A2。此外，图案化黑矩阵层30包括位于边框区BB′中的镂空区域31，其中，第一区域A1和第二区域A2中的至少一个区域在第一基板10上的正投影与镂空区域31在第一基板10上的正投影存在重叠区域AA，即，至少部分地重叠。
在本公开的实施例中，显示面板还包括设置在第一基板10和第二 基板40之间的液晶层50。
需要说明的是，在本公开的实施例中，表述“图案化黑矩阵层包括镂空区域”指的是在图案化黑矩阵层中不设置任何黑矩阵材料的空白区域。也就是说，在图案化黑矩阵层中存在开口。由此可见，例如参照图2B所示，由于图案化黑矩阵层30中的镂空区域31的存在，时钟信号线和公共电极反馈信号线不再能够借助于黑矩阵层而发生彼此之间的信号干扰。
可选地，第一基板10和第二基板40可以为玻璃基板、石英基板或塑料基板等。对此，本公开的实施例不作任何限定。需要说明的是，图2A是以图案化黑矩阵层设置在第二基板上为例进行说明的，而图2B是以图案化黑矩阵层设置在第一基板上为例进行说明的。对此，本公开的实施例同样不作任何限定。
可选地，信号线阵列还可以包括其它信号线，例如，初始信号线、接地线等。此外，时钟信号线的数量也可以为一个或多个，并且本公开的实施例对此不作任何限定。而且，各个信号线也可以采用任何适合的排列布局。作为示例，时钟信号线可以设置在公共电极反馈信号线靠近显示区的一侧。可替换地，时钟信号线也可以设置在公共电极反馈信号线远离显示区的一侧。图2A和图2B是以时钟信号线设置在公共电极反馈信号线靠近显示区的一侧为例进行说明的，并且本公开的实施例并不仅限于此。
在本公开的实施例中，第一区域A1和第二区域A2中的至少一个区域在第一基板10上的正投影与镂空区域31在第一基板10上的正投影存在重叠区域。具体地，这可以例如包括以下情况：第一区域A1在第一基板10上的正投影与镂空区域31在第一基板10上的正投影重合；第二区域A2在第一基板10上的正投影与镂空区域31在第一基板10上的正投影重合；第一区域A1和第二区域A2二者一起在第一基板10上的正投影与镂空区域31在第一基板10上的正投影重合；第二区域A2在第一基板10上的正投影与镂空区域31在第一基板10上的正投影部分重叠等等。对此，本公开的实施例不作任何限定，只要最终保证时钟信号线和公共电极反馈信号线之间不会形成耦合电容，或者即便形成耦合电容也较小。由此，可以减少并且甚至消除时钟信号线和公共电极反馈信号线之间的相互耦合，从而降低信号线之间的信号串 扰。需要说明的是，图2A和图2B是以第二区域A2在第一基板10上的正投影与镂空区域31在第一基板10上的正投影完全重合为例进行说明的，并且本公开的实施例并不仅限于此。
本公开的实施例提供了一种显示面板，其包括：相对设置的第一基板和第二基板、设置在第一基板上的信号线阵列以及设置在第一基板或第二基板上的图案化黑矩阵层。此外，信号线阵列包括时钟信号线和公共电极反馈信号线，并且显示面板的边框区包括配置有公共电极反馈信号线的第一区域和配置有时钟信号线的第二区域。图案化黑矩阵层包括位于边框区中的镂空区域。第一区域和第二区域中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影存在重叠区域。依照本公开的实施例，通过将第一区域和第二区域中的至少一个区域在第一基板上的正投影设计为与镂空区域在第一基板上的正投影存在重叠区域，可以避免在时钟信号线和公共电极反馈信号线之间形成耦合电容并且消除水平横纹频发的问题。
可选地，作为一种实施方式，图案化黑矩阵层设置在第一基板上，即，图案化黑矩阵层位于信号线阵列远离第一基板的一侧上。
可选地，作为另一种实施方式，图案化黑矩阵层设置在第二基板上，即，图案化黑矩阵层位于第二基板靠近第一基板的一侧上。
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参照图3，其示意性示出了根据本公开的实施例的显示面板中的信号线阵列的部分俯视图。如图3所示，在由本公开的实施例提供的显示面板中，信号线阵列中的时钟信号线CLK和公共电极反馈信号线Vcom-Feedback彼此直接相邻。
在本公开的实施例中，第一区域A1和第二区域A2中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影完全重合。具体地，图4A示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图4A是以第一区域A1在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。进一步可选地，图4B示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图4B是以第二区域A2在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。可替换地，图4C示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图4C是以第一区域A1和第二区域A2二者一起在第一基板上的正投 影与镂空区域在第一基板上的正投影完全重合为例进行说明的。
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在本公开的实施例中，时钟信号线CLK和公共电极反馈信号线Vcom-Feedback直接相邻，并且第一区域A1和第二区域A2中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影完全重合。在这样的情况下，时钟信号线CLK和公共电极反馈信号线Vcom-Feedback之间不再会形成耦合电容，从而可以消除时钟信号线CLK和公共电极反馈信号线Vcom-Feedback之间的耦合作用，降低信号线之间的信号串扰，并且避免水平横纹的产生。
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需要说明的是，信号线阵列还可以包括：设置在公共电极反馈信号线Vcom-Feedback远离时钟信号线CLK的一侧处的第一信号线子阵列；以及设置在时钟信号线CLK远离公共电极反馈信号线Vcom-Feedback的一侧处的第二信号线子阵列。
需要说明的是，在本公开的实施例中，镂空区域在第一基板上的正投影可以覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。可替换地，在其它实施例中，镂空区域在第一基板上的正投影也可以不覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。图4A-图4C是以镂空区域在第一基板上的正投影与第一信号子阵列和第二信号子阵列在第一基板上的正投影均不存在重叠区域为例进行说明的，并且本公开的实施例并不仅限于此。
可选地，为了保证信号线不被用户看到，将镂空区域在第一基板上的正投影设计为不覆盖第一信号子阵列和第二信号子阵列在第一基板上的正投影。
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进一步可选地，作为另一种实施方式，图5示意性示出了根据本公开的实施例的显示面板中的信号线阵列的部分俯视图。如图5所示，在本公开的实施例提供的显示面板中，信号线阵列还可以包括设置在时钟信号线CLK和公共电极反馈信号线Vcom-Feedback之间的信号线子阵列。
具体地，第二区域A2可以包括：配置有信号线子阵列的第一子区域A21；以及配置有时钟信号线CLK的第二子区域A22。
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另外，如图5所示，信号线阵列还可以包括：设置在公共电极反馈信号线Vcom-Feedback远离时钟信号线CLK的一侧处的第一信号线子阵列；以及设置在时钟信号线CLK远离公共电极反馈信号线Vcom-Feedback的一侧处的第二信号线子阵列。
可选地，第一区域A1、第一子区域A21和第二子区域A22中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影完全重合。
可选地，在本公开的实施例中，第一子区域A21和第二子区域A22中的至少一个区域在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合。具体地，图6A示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6A是以第一子区域A21在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。可替换地，图6B示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6B是以第二子区域A22在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。进一步地，图6C示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6C是以第一子区域A21和第二子区域A22二者一起在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。
需要说明的是，在本公开的实施例中，镂空区域在第一基板上的正投影可以覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。可替换地，在其它实施例中，镂空区域在第一基板上的正投影也可以不覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。图6A-图6C是以镂空区域在第一基板上的正投影与第一信号子阵列和第二信号子阵列在第一基板上的正投影均不存在重叠区域为例进行说明的，并且本公开的实施例并不仅限于此。
可选地，在本公开的实施例中，第一区域A1在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合。可替换地，第一子区域A21和第二子区域A22中的至少一个区域在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合。具体地，图6D示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6D是以第一区域A1和第一子区域A21二者一起在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。可替换地，图6E示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6E是以第一区域A1和第二子区域A22二者一起在第一 基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。进一步地，图6F示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6F是以第一区域A1、第一子区域A21和第二子区域A22三者一起在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。
在本公开的实施例中，镂空区域在第一基板上的正投影可以覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。可替换地，在其它实施例中，镂空区域在第一基板上的正投影也可以不覆盖第一信号子阵列和/或第二信号子阵列在第一基板上的正投影。图6D-图6F是以镂空区域在第一基板上的正投影与第一信号子阵列和第二信号子阵列在第一基板上的正投影均不存在重叠区域为例进行说明的，并且本公开的实施例并不仅限于此。
可选地，第一区域A1在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合。具体地，图6G示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6G是以第一区域A1在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。
可选地，第一子区域A21可以进一步包括例如靠近公共电极反馈信号线的第一部分a1和靠近时钟信号线的第二部分a2，其中，第一部分a1或第二部分a2在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合。具体地，图6H示意性示出了根据本公开的实施例的显示面板的部分俯视图，其中，图6H是以第一部分a1在第一基板上的正投影与镂空区域31在第一基板上的正投影完全重合为例进行说明的。
可选地，第一部分a1或者第二部分a2的宽度为15-25微米，优选地，20微米。
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可选地，图7示意性示出了根据本公开的实施例的显示面板的截面图，并且图8示出了图7中的显示面板的对应俯视图。如图7和图8所示，在本公开的实施例提供的显示面板中，图案化黑矩阵层30由第一黑矩阵材料制成，并且镂空区域31可以填充有第二黑矩阵材料，其中，第二黑矩阵材料的电阻率大于第一黑矩阵材料的电阻率。同样地，以这样的方式，可以减小公共电极反馈信号线Vcom-Feedback和时钟 信号线CLK之间的耦合作用。
需要说明的是，图7是以第二子区域A22在第一基板10上的正投影与镂空区域在第一基板10上的正投影完全重合为例进行说明的。当然，可替换地，在本公开的实施例提供的显示面板中，还可以是第一子区域A21在第一基板10上的正投影与镂空区域在所述第一基板10上的正投影完全重合，即，如图8所示。可替换地，在其它实施例中，第一区域A1在第一基板10上的正投影可以与镂空区域在第一基板10上的正投影完全重合，或者第二区域整体(即，A21+A22)在第一基板10上的正投影与镂空区域在所述第一基板10上的正投影重合。对此，本公开的实施例不作任何限定。
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在本公开的实施例中，通过在镂空区域中采用电阻率较大的第二黑矩阵材料，可以大幅度减小公共电极反馈信号线Vcom-Feedback和时钟信号线CLK之间的耦合作用，从而使水平横纹减轻或者甚至消失。
需要说明的是，图9示意性示出了根据本公开的实施例的显示面板的俯视图，其中，通过白色虚线示意性示出显示面板的中心显示区。如图9所示，由于显示面板中的信号线阵列分布在显示区的两侧边框区中，因此，图案化黑矩阵层包括位于两侧边框区中的两个纵向镂空区域。需要强调的是，图9是以第一子区域A21在第一基板上的正投影与镂空区域在第一基板上的正投影完全重合为例进行说明的。
可选地，图10示意性示出了根据本公开的实施例的显示面板的俯视图，其中，同样地借助于白色虚线示意性示出显示面板的中心显示区。如图10所示，镂空区域31为位于四周边框区中的环形区域。
需要说明的是，镂空区域在第一基板上的正投影可以覆盖第一区域、第一子区域、第二子区域、以及第一子区域的第一部分和第二部分中的任一区域或者组合在第一基板上的正投影。对此，本公开的实施例不做任何限定。另外，图10是以镂空区域在第一基板上的正投影覆盖第一子区域A21在第一基板上的正投影为例进行说明的。
在本公开的实施例中，镂空区域被设计为环形。以这样的方式，使得覆盖显示区的黑矩阵层部分和覆盖非显示区(即，边框区)的黑矩阵层部分彼此分离，从而避免覆盖显示区的黑矩阵层部分和覆盖非显示区的黑矩阵层部分之间的信号干扰，并且进一步提升显示效果。
需要说明的是，在图3-图10中提供的技术方案既可以应用在其中 图案化黑矩阵层设置于第一基板上的显示面板中，还可以应用在其中图案化黑矩阵层设置于第二基板上的显示面板中。对此，本公开的实施例不作任何限定。
基于相同的发明构思，本公开的实施例还提供了一种显示面板的制作方法。图11示意性示出了根据本公开的实施例的显示面板的制作方法的流程图。如图11所示，根据本公开的实施例，显示面板包括位于中心的显示区和包围显示区的边框区，并且显示面板的制作方法具体包括以下步骤。
步骤100、提供彼此相对的第一基板和第二基板。
可选地，第一基板可以为玻璃基板、石英基板或塑料基板等。对此，本公开的实施例不作任何限定。
可选地，第二基板也可以为玻璃基板、石英基板或塑料基板等。对此，本公开的实施例同样不作任何限定。
步骤200、在第一基板与第二基板之间形成图案化黑矩阵层，使得图案化黑矩阵层包括位于边框区中的镂空区域。
可选地，作为一种实施方式，图案化黑矩阵层可以形成在信号线阵列远离第一基板的一侧上。
可选地，作为另一种实施方式，图案化黑矩阵层也可以形成在第二基板靠近第一基板的一侧上。
S300、在第一基板靠近第二基板的一侧上形成位于边框区中的信号线阵列。
具体地，信号线阵列包括时钟信号线和公共电极反馈信号线。显示面板的边框区包括配置有公共电极反馈信号线的第一区域和配置有时钟信号线的第二区域。第一区域和第二区域中的至少一个在第一基板上的正投影与镂空区域在第一基板上的正投影至少部分地重叠。
需要说明的是，在本公开的实施例中，表述“图案化黑矩阵层包括镂空区域”指的是图案化黑矩阵层中存在不设置任何黑矩阵材料的区域。也就是说，图案化黑矩阵层中存在开口。由此，可以借助于图案化黑矩阵层中的镂空区域来消除时钟信号线和公共电极反馈信号线之间的信号干扰。
本公开的实施例提供了一种显示面板的制作方法，其包括：提供第一基板和第二基板；在第一基板上形成信号线阵列；信号线阵列包 括：提供彼此相对的第一基板和第二基板；在第一基板与第二基板之间形成图案化黑矩阵层，该图案化黑矩阵层包括位于边框区中的镂空区域；以及在第一基板靠近第二基板的一侧上形成位于边框区中的信号线阵列。信号线阵列包括公共电极反馈信号线和时钟信号线。边框区包括配置有公共电极反馈信号线的第一区域和配置有时钟信号线的第二区域。第一区域和第二区域中的至少一个在第一基板上的正投影与镂空区域在第一基板上的正投影至少部分地重叠。根据本公开的实施例，通过将第一区域和第二区域中的至少一个区域在第一基板上的正投影设计为与镂空区域在第一基板上的正投影存在重叠区域，可以减少并且甚至消除时钟信号线和公共电极反馈信号线之间的耦合作用，降低信号线之间的信号串扰，并且避免水平横纹的产生。
可选地，作为一种实施方式，时钟信号线和公共电极反馈信号线直接相邻，并且将图案化黑矩阵层形成为使得第一区域和第二区域中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影重合。
可选地，作为另一种实施例方式，信号线阵列还包括设置在时钟信号线和公共电极反馈信号线之间的信号线子阵列，并且第二区域包括配置有信号线子阵列的第一子区域和配置有时钟信号线的第二子区域。在这样的情况下，将图案化黑矩阵层形成为使得第一区域、第一子区域和第二子区域中的至少一个区域在第一基板上的正投影与镂空区域在第一基板上的正投影重合。可替换地，第一子区域还可以包括靠近例如公共电极反馈信号线的第一部分和靠近例如时钟信号线的第二部分，并且第一部分或第二部分在第一基板上的正投影与镂空区域在第一基板上的正投影重合。
可选地，根据本公开的实施例，用于显示面板制作方法还可以包括：向图案化黑矩阵层的镂空区域中填充具有比用于形成图案化黑矩阵层的第一黑矩阵材料的电阻率大的电阻率的第二黑矩阵材料。由此，可以减小公共电极反馈信号线和时钟信号线之间的耦合作用。
基于同样的发明构思，本公开的实施例还提供了一种显示装置，其包括：在以上任一个实施例中描述的显示面板。这样的显示装置的实现原理和实现效果与上文所述的显示面板类似，并且在此不再赘述。
需要说明的是，显示装置可以为液晶显示器(Liquid Crystal  Display，简称LCD)、电子纸、有机发光二极管(Organic Light-Emitting Diode，简称OLED)显示器、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等具有显示功能的任何产品或部件。
需要说明的是，本公开的实施例中的附图仅仅涉及在本公开的实施例中提到的结构，并且其它结构可以参考通常设计。
此外，为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸已经被放大。可以理解到，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者也可以存在中间元件。
而且，在不发生冲突的情况下，本公开的实施例，即，实施例中的特征，可以相互组合以得到新的实施例。
虽然已经在上文描述了本公开所揭露的实施方式，但是所述内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化。然而，本公开的专利保护范围仍须以所附权利要求书界定的范围为准。

Claims (11)

  1. 一种显示面板，包括位于中心的显示区和围绕所述显示区的边框区，所述显示面板进一步包括：
    相对设置的第一基板和第二基板；
    位于所述第一基板与所述第二基板之间的图案化黑矩阵层；以及
    在所述边框区中设置在所述第一基板靠近所述第二基板的一侧上的信号线阵列，其中
    所述信号线阵列包括公共电极反馈信号线和时钟信号线；
    所述边框区包括配置有所述公共电极反馈信号线的第一区域和配置有所述时钟信号线的第二区域；
    所述图案化黑矩阵层包括位于所述边框区中的镂空区域；并且
    所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影至少部分地重叠。
  2. 根据权利要求1所述的显示面板，其中
    所述图案化黑矩阵层设置在所述信号线阵列远离所述第一基板的一侧上，或者所述第二基板靠近所述第一基板的一侧上。
  3. 根据权利要求1所述的显示面板，其中
    所述时钟信号线和所述公共电极反馈信号线彼此直接相邻；并且
    所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
  4. 根据权利要求1所述的显示面板，其中
    所述信号线阵列还包括设置在所述时钟信号线和所述公共电极反馈信号线之间的信号线子阵列；并且
    所述第二区域包括配置有所述信号线子阵列的第一子区域和配置有所述时钟信号线的第二子区域。
  5. 根据权利要求4所述的显示面板，其中
    所述第一区域、所述第一子区域和所述第二子区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
  6. 根据权利要求4所述的显示面板，其中
    所述第一子区域进一步包括靠近所述时钟信号线的第一部分和靠 近所述公共电极反馈信号线的第二部分，所述第一部分或所述第二部分在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影完全重合。
  7. 根据权利要求1-6中任一项所述的显示面板，其中
    所述图案化黑矩阵层由第一黑矩阵材料制成，并且
    所述显示面板还包括填充在所述镂空区域中的第二黑矩阵材料，所述第二黑矩阵材料的电阻率大于所述第一黑矩阵材料的电阻率。
  8. 根据权利要求1-6中任一项所述的显示面板，其中
    所述镂空区域呈环形。
  9. 根据权利要求6所述的显示面板，其中
    所述第一部分或所述第二部分的宽度为15-25微米。
  10. 一种显示装置，包括：根据权利要求1-9中任一项所述的显示面板。
  11. 一种用于显示面板的制作方法，所述显示面板包括位于中心的显示区和围绕所述显示区的边框区，并且所述制作方法包括：
    提供彼此相对的第一基板和第二基板；
    在所述第一基板与所述第二基板之间形成图案化黑矩阵层，所述图案化黑矩阵层包括位于所述边框区中的镂空区域；以及
    在所述第一基板靠近所述第二基板的一侧上形成位于所述边框区中的信号线阵列，其中
    所述信号线阵列包括公共电极反馈信号线和时钟信号线；
    所述边框区包括配置有所述公共电极反馈信号线的第一区域和配置有所述时钟信号线的第二区域；并且
    所述第一区域和所述第二区域中的至少一个在所述第一基板上的正投影与所述镂空区域在所述第一基板上的正投影至少部分地重叠。
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