WO2019173985A1 - 一种用于提高tia中跨阻放大级输出直流电平的电路 - Google Patents

一种用于提高tia中跨阻放大级输出直流电平的电路 Download PDF

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WO2019173985A1
WO2019173985A1 PCT/CN2018/078974 CN2018078974W WO2019173985A1 WO 2019173985 A1 WO2019173985 A1 WO 2019173985A1 CN 2018078974 W CN2018078974 W CN 2018078974W WO 2019173985 A1 WO2019173985 A1 WO 2019173985A1
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Prior art keywords
amplifier stage
transimpedance amplifier
pmos transistor
resistor
output
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PCT/CN2018/078974
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English (en)
French (fr)
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彭慧耀
陈伟
洪佳程
潘剑华
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厦门优迅高速芯片有限公司
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Priority to PCT/CN2018/078974 priority Critical patent/WO2019173985A1/zh
Priority to US16/977,462 priority patent/US11218124B2/en
Publication of WO2019173985A1 publication Critical patent/WO2019173985A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H03F3/082—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light with FET's
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/04—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only
    • H03F3/08—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements with semiconductor devices only controlled by light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3001—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor with field-effect transistors
    • H03F3/3022—CMOS common source output SEPP amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183—Long tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45237—Complementary long tailed pairs having parallel inputs and being supplied in series
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/30—Indexing scheme relating to single-ended push-pull [SEPP]; Phase-splitters therefor
    • H03F2203/30031—A resistor being coupled as feedback circuit in the SEPP amplifier
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45—Indexing scheme relating to differential amplifiers
    • H03F2203/45674—Indexing scheme relating to differential amplifiers the LC comprising one current mirror

Definitions

  • the present invention relates to the field of electronic circuits, and in particular to a circuit for improving the output DC level of a transimpedance amplifier stage in a TIA.
  • the transimpedance amplifying circuit (TIA) of the receiving front end is mainly composed of a transimpedance amplification stage and a differential amplification stage.
  • the transimpedance amplifier stage converts the photocurrent signal into a voltage signal, and the differential amplifier stage further amplifies the preamplifier output voltage signal to meet the output voltage amplitude requirement.
  • the transimpedance amplifier stage is usually composed of a single-ended circuit, and its output DC level often cannot match the input DC level of the differential amplifier stage, and other circuit structures need to be added to achieve level matching.
  • the current method is to use a CS amplification stage composed of an NMOS transistor MN3 and a resistor R3 to boost the V1 level and then connect to the differential amplification stage.
  • the CS amplifier stage composed of the NMOS transistor MN3 and the resistor R3 has a bias current determined by the transimpedance amplification stage. If there is a deviation in the production process or I in ⁇ 0, V1 will change, and the bias current of the CS stage will also change, and the bandwidth and gain of the entire TIA will also change, affecting the stability of the overall circuit operation.
  • a circuit for improving a DC level of a transimpedance amplifier stage in a TIA comprising a transimpedance amplifier stage, a differential amplification stage, a level boosting unit, and a DC recovery loop; the input of the transimpedance amplifier stage is used for input
  • the photocurrent signal has its output directly connected to the input of the differential amplifier stage;
  • the DC recovery loop includes a pseudo transimpedance amplification stage, a first filtering unit, a second filtering unit, a DC recovery operational amplifier, and a DC path unit, and the transimpedance amplification stage and the pseudo transimpedance amplification stage are connected in parallel with the power supply VDD and the power
  • the output terminal of the transimpedance amplifier stage is connected to the inverting input end of the DC recovery op amp through a first filter circuit, and the output end of the pseudo transimpedance amplifier stage is connected to the DC recovery through the second filter unit.
  • the non-inverting input end of the operational amplifier, the output end of the DC recovery operational amplifier is connected to the DC path unit, and the DC path unit is further connected to the input end of the transimpedance amplification stage.
  • the level boosting unit includes a tail current source Itail and a capacitor C3.
  • the tail current source Itail and the capacitor C3 are connected in parallel, one end of which is connected to the transimpedance amplifier stage and the pseudo transimpedance amplifier stage, and the other end is grounded.
  • the pseudo transimpedance amplifier stage includes a PMOS transistor MP2, an NMOS transistor MN2, and a resistor Rdummy, a source of the PMOS transistor MP2 is connected to the power supply VDD, one end of the gate connection resistor Rdummy, and the other end of the drain connection resistor Rdummy; the NMOS transistor MN2
  • the gate is connected to one end of the resistor Rdummy connected to the gate of the PMOS transistor MP2
  • the drain of the NMOS transistor MN2 is connected to one end of the drain of the resistor Rdummy connected to the PMOS transistor MP2
  • the source of the NMOS transistor MN2 is connected to the level boosting unit, and the resistor Rdummy
  • One end of the PMOS transistor MP2 and the NMOS transistor MN2 is connected to the second filtering unit as an output terminal of the pseudo-transimpedance amplification stage.
  • the DC path unit includes an NMOS transistor MN0.
  • the gate of the NMOS transistor MN0 is connected to the output end of the DC recovery op amp, the drain is connected to the input end of the transimpedance amplifier stage, and the source is grounded.
  • the DC recovery operational amplifier includes a PMOS transistor MP7, an NMOS transistor MN7, a PMOS transistor MP8, an NMOS transistor MN8, a PMOS transistor MP9, a resistor Rc, a capacitor Cc, a tail current source Itail2, a tail current source Itail3, and a gate connection of the NMOS transistor MN7.
  • the inverting input terminal of the DC recovery op amp, the source is grounded via the tail current source Itail2, and the drain is connected to the drain of the PMOS transistor MP7 on the one hand, and the drain of the PMOS transistor MP7 is also connected to the drain of the PMOS transistor MP7 on the other hand.
  • the source of the tube MP7 is connected to the power source VDD;
  • the gate of the PMOS transistor MP9 is connected to the drain of the PMOS transistor MP8, the source of the PMOS transistor MP9 is connected to the power supply VDD, and the drain of the PMOS transistor MP9 is grounded via the tail current source Itail3, and the drain of the PMOS transistor MP9 is connected.
  • DC restores the output of the op amp.
  • the transimpedance amplifier stage includes a PMOS transistor MP1, an NMOS transistor MN1, and a variable resistor RF.
  • the gate of the PMOS transistor MP1 is connected to the input terminal IN of the transimpedance amplifier stage, the source is connected to the power supply VDD, and the drain is connected to the transimpedance amplifier stage.
  • the output end; the gate of the NMOS transistor MN1 is connected to the input end of the transimpedance amplifier stage, the source is connected to the level boosting unit, and the drain is connected to the output end of the transimpedance amplifier stage; one end of the variable resistor RF is connected to the input of the transimpedance amplifier stage The other end is connected to the output of the transimpedance amplifier stage.
  • the first filter circuit includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the output end of the transimpedance amplifier stage, and the other end is grounded via the capacitor C1. At the same time, one end of the resistor R1 connected to the capacitor C1 is also connected to the reverse phase of the DC recovery op amp.
  • the second filter unit includes a resistor R2 and a capacitor C2. One end of the resistor R2 is connected to the output end of the pseudo-span amplifier amplifier stage, and the other end is grounded via the capacitor C2. At the same time, one end of the resistor R2 connected to the capacitor C2 is also connected to the DC recovery operation. Put the non-inverting input.
  • the present invention realizes the output DC level of the transimpedance amplifier stage and the input DC level of the differential amplifier stage by introducing the tail current source Itail in the transimpedance amplifier stage to increase the output DC level of the transimpedance amplifier stage.
  • the present invention adds a DC recovery loop if the transimpedance amplifier stage When the input current increases and changes, in the clamp of the DC recovery loop, the DC portion of the input current of the transimpedance amplifier stage is introduced to the ground potential, so that the output DC level of the transimpedance amplifier stage is restored, so that the transimpedance is achieved.
  • the output DC level of the amplifier stage and the input DC level of the differential amplifier stage are re-matched to improve the stability of the entire circuit.
  • FIG. 1 is a circuit diagram of a transimpedance amplifier stage of the prior art
  • FIG. 2 is a circuit diagram of a differential amplification stage of the prior art
  • FIG. 3 is a circuit diagram of a transimpedance amplifier stage of the present invention.
  • the invention discloses a circuit for improving the output DC level of the transimpedance amplifier stage in the TIA, which realizes the improvement of the DC level of the transimpedance amplifier stage by introducing the level boosting unit 2 and the DC recovery loop 3, and achieves differential amplification.
  • the level of input DC level matches the purpose.
  • the circuit for improving the output DC level of the transimpedance amplifier stage in the TIA includes a transimpedance amplifier stage 1, a differential amplifier stage, a level boosting unit 2, and a DC recovery loop 3 (DC-RESTORE loop), wherein The input terminal IN of the transimpedance amplifier stage 1 is connected to the photodiode L1 for inputting a photocurrent signal, and the output terminal out1 of the transimpedance amplifier stage 1 is directly connected to the input end of the differential amplification stage.
  • the specific circuit connection relationship of the transimpedance amplifier stage 1, the level boosting unit 2, and the DC recovery loop 3 will be described in detail below.
  • the differential amplifier stage since it is a prior art, the following description will not be repeated. .
  • the drain is connected to the output terminal out1 of the transimpedance amplifier stage 1; the gate of the NMOS transistor MN1 is connected to the input terminal IN of the transimpedance amplifier stage 1, the source is grounded via the level boosting unit 2, and the drain is connected to the transimpedance amplifier stage 1
  • the DC recovery loop 3 specifically includes a pseudo transimpedance amplifier stage 31, a resistor R1, a resistor R2, a capacitor C1, a capacitor C2, a DC recovery op amp 32 (DC-RESTORE op amp), and an NMOS transistor MN0, wherein the pseudo transimpedance amplifier stage 31 includes a PMOS transistor MP2, an NMOS transistor MN2, and a resistor Rdummy.
  • the source of the PMOS transistor MP2 is connected to the power supply VDD, one end of the gate connection resistor Rdummy, and the other end of the drain connection resistor Rdummy.
  • the gate of the NMOS transistor MN2 is connected to the resistor Rdummy.
  • One end of the gate of the PMOS transistor MP2 is connected, the drain of the NMOS transistor MN2 is connected to one end of the drain of the resistor Rdummy connected to the PMOS transistor MP2, and the source of the NMOS transistor MN2 is grounded via the level boosting unit 2.
  • the resistor Rdummy connected to the PMOS transistor MP2 and the NMOS transistor MN2 is connected to the non-inverting input terminal INP of the DC recovery op amp 32 via the resistor R2, and the non-inverting input terminal INP of the DC recovery op amp 32 is grounded via the capacitor C2, the resistor R2 and The capacitor C2 constitutes the second filtering unit 35.
  • the inverting input terminal INN of the DC recovery op amp 32 is connected to the output terminal out1 of the transimpedance amplifier stage via the resistor R1, and the inverting input terminal INN of the DC recovery op amp 32 is also grounded via the capacitor C1, and the resistor R1 and the capacitor C1 are formed.
  • the first filtering unit 34 is connected to the output terminal out1 of the transimpedance amplifier stage via the resistor R1, and the inverting input terminal INN of the DC recovery op amp 32 is also grounded via the capacitor C1, and the resistor R1 and the capacitor C1 are formed.
  • the level boosting unit 2 includes a tail current source Itail and a capacitor C3.
  • the tail current source Itail and the capacitor C3 are connected in parallel, one end of which is connected to the ground, and the other end of which is connected to the source of the NMOS transistor MN1 of the transimpedance amplifier stage 1, and the terminal is also connected.
  • the present invention also introduces a tail current source Itail in the transimpedance amplifier stage 1 to increase its output DC level.
  • the output DC level of the transimpedance amplifier stage 1 is originally determined by the PMOS transistor MP1, the NMOS transistor MN1, and the power supply VDD.
  • the output DC level is determined by the tail current source Itail, the PMOS transistor MP1, and the power supply VDD.
  • the output DC level Vout of the transimpedance amplifier stage 1 and the output DC level Vdummy of the pseudo transimpedance amplifier stage 31 are equal, and the MN0 tube is turned off (ie, turned off).
  • the input current Iin of the input terminal IN of the transimpedance amplifier stage 1 increases, the DC level of the transimpedance amplifier stage 1 decreases, and the voltage of the non-inverting input terminal of the DC recovery op amp 32 is greater than the voltage of the inverting input terminal, resulting in a DC recovery op amp.
  • the output voltage of 32 is increased, the NMOS transistor MN0 is turned on, and the DC portion of the input current Iin of the input terminal IN of the transimpedance amplifier stage 1 is introduced to the ground potential, so that the output DC level of the transimpedance amplifier stage 1 is restored, thereby The output DC level Vout1 of the transimpedance amplifier stage 1 and the input DC level V2 of the differential amplifier stage are re-matched. If the current changes again, the output voltage of the DC recovery op amp 32 also changes, so that the voltage and current of the NMOS transistor MN0 are converted, and the current flowing through the MN0 is increased or decreased, forcing the DC level recovery of the transimpedance amplifier stage output. To the level close to Vdummy, the output DC level Vout1 of the transimpedance amplifier stage and the input DC level V2 of the differential amplifier stage are re-matched, thereby improving the stability of the entire circuit.

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Abstract

本发明涉及一种用于提高TIA中跨阻放大级输出直流电平的电路，其包括包括跨阻放大级、差分放大级、电平提升单元和直流恢复环路；所述跨阻放大级的输入端用于输入光电流信号，其输出端则直接连接差分放大级的输入端。本发明通过引入电平提升单元和直流恢复环路实现跨阻放大级输出直流电平的提升，达到与差分放大级输入直流电平相匹配的目的，提高整体电路的稳定性。

Description

一种用于提高TIA中跨阻放大级输出直流电平的电路 技术领域
本发明涉及电子电路领域，具体涉及一种用于提高TIA中跨阻放大级输出直流电平的电路。
背景技术
光通信中，接收前端的跨阻放大电路(TIA)主要由跨阻放大级和差分放大级组成。跨阻放大级将光电流信号转换为电压信号，差分放大级将前级输出电压信号进一步放大，以满足输出电压幅度的要求。跨阻放大级通常由单端电路构成，其输出直流电平往往无法和差分放大级的输入直流电平相匹配，需要加入其他的电路结构来实现电平匹配。
如图1所示，由NMOS管MN1，PMOS管MP1，可调电阻RF构成的跨阻放大级，其输出直流电平为V1，在I in＝0时，V1＝VGS MN1。图2为差分放大级的输入级，由于增加了尾电流Itail1，其所需输入直流电平为V2＝VGS MN5+Vtail。由于VGS MN1≈VGS MN5，V1和V2相差一个Vtail的电压，不好直接相连。目前所采用的方法是利用NMOS管MN3和电阻R3构成的CS放大级，将V1电平进行提升后，再与差分放大级相连。
由NMOS管MN3，电阻R3构成的CS放大级，其偏置电流由跨阻 放大级所决定。如果生产工艺出现偏差或者I in≠0，V1将发生变化，CS级的偏置电流也随之发生变化，进而整个TIA的带宽和增益也将发生变化，影响整体电路工作的稳定性。
发明内容
本发明的目的在于提供一种用于提高TIA中跨阻放大级输出直流电平的电路，其不引入额外的中间级即可实现跨阻放大级和差分放大级之间的直流电平匹配，提高整体电路的稳定性。
为实现上述目的，本发明采用的技术方案是：
一种用于提高TIA中跨阻放大级输出直流电平的电路，其包括跨阻放大级、差分放大级、电平提升单元和直流恢复环路；所述跨阻放大级的输入端用于输入光电流信号，其输出端则直接连接差分放大级的输入端；
所述直流恢复环路包括伪跨阻放大级、第一滤波单元、第二滤波单元、直流恢复运放和直流通路单元，所述跨阻放大级和伪跨阻放大级并联在电源VDD和电平提升单元之间，所述跨阻放大级的输出端通过第一滤波电路连接直流恢复运放的的反相输入端，所述伪跨阻放大级的输出端通过第二滤波单元连接直流恢复运放的同相输入端，所述直流恢复运放的输出端连接直流通路单元，所述直流通路单元还连接跨阻放大级的输入端。
所述电平提升单元包括尾电流源Itail和电容C3，所述尾电流源Itail和电容C3并联，其一端连接跨阻放大级和伪跨阻放大级， 另一端接地。
所述伪跨阻放大级包括包括PMOS管MP2、NMOS管MN2和电阻Rdummy，PMOS管MP2的源极连接电源VDD，栅极连接电阻Rdummy的一端，漏极连接电阻Rdummy的另一端；NMOS管MN2的栅极与电阻Rdummy连接PMOS管MP2栅极的一端连接，NMOS管MN2的漏极与电阻Rdummy连接PMOS管MP2漏极的一端连接，而NMOS管MN2的源极连接电平提升单元，电阻Rdummy接PMOS管MP2、NMOS管MN2的一端作为伪跨阻放大级的输出端连接至第二滤波单元。
所述直流通路单元包括NMOS管MN0，该NMOS管MN0的栅极连接直流恢复运放的输出端，漏极连接跨阻放大级的输入端，源极接地。
所述直流恢复运放包括PMOS管MP7、NMOS管MN7、PMOS管MP8、NMOS管MN8、PMOS管MP9、电阻Rc、电容Cc、尾电流源Itail2、尾电流源Itail3，NMOS管MN7的栅极连接直流恢复运放的反向输入端，源极经由尾电流源Itail2接地，漏极一方面连接PMOS管MP7的漏极，另一方面NMOS管MN7的漏极还连接PMOS管MP7的栅极，PMOS管MP7的源极连接电源VDD；
NMOS管MN8的栅极连接直流恢复运放的同向输入端INP，源极经由尾电流源Itail2接地，漏极一方面理解PMOS管MP8的漏极,另一方面依次经由电阻Rc和电容Cc连接至直流回复运放的输出端；PMOS管MP8的栅极连接PMOS管MP7的栅极，PMOS管MP8的源极连接电源VDD；
PMOS管MP9的栅极连接PMOS管MP8的漏极，PMOS管MP9的源极 连接电源VDD，PMOS管MP9的漏极一方面经由尾电流源Itail3接地，另一方面该PMOS管MP9的漏极连接直流恢复运放的输出端。
所述跨阻放大级包括PMOS管MP1、NMOS管MN1和可变电阻RF，PMOS管MP1的栅极连接跨阻放大级的输入端IN，源极连接电源VDD，漏极连接跨阻放大级的输出端；NMOS管MN1的栅极连接跨阻放大级的输入端，源极连接电平提升单元，漏极连接跨阻放大级的输出端；可变电阻RF的一端连接跨阻放大级的输入端，另一端连接跨阻放大级的输出端。
所述第一滤波电路包括电阻R1和电容C1，电阻R1一端连接跨阻放大级的输出端，另一端经由电容C1接地，同时，电阻R1连接电容C1的一端还连接直流恢复运放的反相输入端；所述第二滤波单元包括电阻R2和电容C2，电阻R2一端连接伪跨阻放大级的输出端，另一端经由电容C2接地，同时，电阻R2连接电容C2的一端还连接直流恢复运放的同相输入端。
采用上述方案后，本发明通过在跨阻放大级中在引入尾电流源Itail，以提高跨阻放大级的输出直流电平，从而实现跨阻放大级的输出直流电平与差分放大级的输入直流电平之间的匹配。而为了避免因跨阻放大级的输入电流变化而引起跨阻放大级的输出直流电平和差分放大级的输入直流电平之间的不匹配问题，本发明增加了直流恢复环路，若跨阻放大级的输入电流增大而发生变化时，在直流恢复环路的钳制作用下，将跨阻放大级的输入电流的直流部分导入地电位，从而使跨阻放大级输出直流电平得到恢复，使跨阻放大级的输出直流 电平和差分放大级的输入直流电平重新实现匹配，进而提高整个电路的稳定性。
附图说明
图1为现有技术的跨阻放大级电路图；
图2为现有技术的差分放大级电路图；
图3为本发明跨阻放大级电路图；
图4为本发明DC-RESTORE运放的电路图。
具体实施方式
本发明揭示了一种用于提高TIA中跨阻放大级输出直流电平的电路，其通过引入电平提升单元2和直流恢复环路3实现跨阻放大级输出直流电平的提升，达到与差分放大级输入直流电平相匹配的目的。
具体地，本发明用于提高TIA中跨阻放大级输出直流电平的电路包括跨阻放大级1、差分放大级、电平提升单元2和直流恢复环路3(DC-RESTORE环路)，其中，跨阻放大级1的输入端IN连接光敏二极管L1，用于输入光电流信号，跨阻放大级1的输出端out1直接连接至差分放大级的输入端。以下将对跨阻放大级1、电平提升单元2和直流恢复环路3的具体电路连接关系进行详述，而对于差分放大级而言，由于其为现有技术，因此以下不再进行赘述。
如图3所示，上述跨阻放大级1包括PMOS管MP1、NMOS管MN1 和可变电阻RF，其中，PMOS管MP1的栅极连接跨阻放大级1的输入端IN，源极连接电源VDD，漏极连接跨阻放大级1的输出端out1；NMOS管MN1的栅极连接跨阻放大级1的输入端IN，源极经由电平提升单元2接地，漏极连接跨阻放大级1的输出端out1；可变电阻RF的一端连接跨阻放大级1的输入端IN，另一端连接跨阻放大级1的输出端out1。
直流恢复环路3具体包括伪跨阻放大级31、电阻R1、电阻R2、电容C1、电容C2、直流恢复运放32(DC-RESTORE运放)、NMOS管MN0，其中，伪跨阻放大级31包括PMOS管MP2、NMOS管MN2和电阻Rdummy，PMOS管MP2的源极连接电源VDD，栅极连接电阻Rdummy的一端，漏极连接电阻Rdummy的另一端；NMOS管MN2的栅极与电阻Rdummy连接PMOS管MP2栅极的一端连接，NMOS管MN2的漏极与电阻Rdummy连接PMOS管MP2漏极的一端连接，而NMOS管MN2的源极经电平提升单元2接地。
电阻Rdummy连接PMOS管MP2、NMOS管MN2的一端经由电阻R2连接直流恢复运放32的同向输入端INP，同时，该直流恢复运放32的同向输入端INP经电容C2接地，电阻R2和电容C2构成第二滤波单元35。直流恢复运放32的反向输入端INN经由电阻R1连接跨阻放大级的输出端out1，同时面该直流恢复运放32的反向输入端INN还经由电容C1接地，电阻R1和电容C1构成第一滤波单元34。直流恢复运放32的输出端连接NMOS管MN0的栅极，而NMOS管MN0的源极接地，漏极连接跨阻放大级的输入端IN，该NMOS管MN0构成直流 通路单元33。
电平提升单元2包括尾电流源Itail和电容C3，尾电流源Itail和电容C3并联，其一端连接接地，另一端连接跨阻放大级1的NMOS管MN1的源极，同时，该端还连接伪跨阻放大级31的NMOS管MN2的源极。加入尾电流Itail后,跨阻放大级1环路增益会下降,加入电容C3可以起到高频交流短路的作用,提高跨阻放大级1的环路增益。
如图4所示，直流恢复运放32包括PMOS管MP7、NMOS管MN7、PMOS管MP8、NMOS管MN8、PMOS管MP9、电阻Rc、电容Cc、尾电流源Itail2、尾电流源Itail3，NMOS管MN7的栅极连接直流恢复运放32的反向输入端，源极经由尾电流源Itail2接地，漏极一方面连接PMOS管MP7的漏极，另一方面NMOS管MN7的漏极还连接PMOS管MP7的栅极，PMOS管MP7的源极连接电源VDD。
NMOS管MN8的栅极连接直流恢复运放32的同向输入端INP，源极经由尾电流源Itail2接地，漏极一方面连接PMOS管MP8的漏极,另一方面依次经由电阻Rc和电容Cc连接至直流回复运放32的输出端out2；PMOS管MP8的栅极连接PMOS管MP7的栅极，PMOS管MP8的源极连接电源VDD。
PMOS管MP9的栅极连接PMOS管MP8的漏极，PMOS管MP9的源极连接电源VDD，PMOS管MP9的漏极一方面经由尾电流源Itail3接地，另一方面该PMOS管MP9的漏极连接直流恢复运放32的输出端out2。
由于差分放大级引入的尾电流造成了其与跨阻放大级1之间的直流电平上的不匹配，故本发明在跨阻放大级1中也引入尾电流源 Itail，提高其输出直流电平。跨阻放大级1输出直流电平原来由PMOS管MP1、NMOS管MN1和电源VDD所决定，引入尾电流源Itail后，其输出直流电平由尾电流源Itail，PMOS管MP1和电源VDD所决定。当跨阻放大级1的输入电流Iin为0或者很小时，由于引入尾电流Itail，跨阻放大级1的输出直流电平Vout1在原来的基础上提高了Vtail，即Vout1＝VGS MN1+V tail,与V2直流电平相匹配。
但是，如果单引入尾电流源Itail，当跨阻放大级1的输入电流Iin增大时，其输出直流电平会因为输入电流Iin的增大而降低，最终导致直流电平不匹配。因此在引入尾电流源Itail的同时，引入直流恢复环路3。直流恢复环路3中的PMOS管MP2、NMOS管MN2、电阻Rdummy构成了一个伪跨阻放大级31，其输出直流电平Vdummy提供了一个参考电平。跨阻放大级1的输入电流Iin为零或者接近于零时，跨阻放大级1的输出直流电平Vout和伪跨阻放大级31的输出直流电平Vdummy相等，MN0管被关闭(即断开)。当跨阻放大级1的输入端IN的输入电流Iin增大时，跨阻放大级1输出直流电平降低，直流恢复运放32的同相输入端电压大于反相输入端电压，导致直流恢复运放32的输出端电压升高，NMOS管MN0被开启，将跨阻放大级1的输入端IN的输入电流Iin的直流部分导入地电位，从而使跨阻放大级1输出直流电平得到恢复，进而使跨阻放大级1的输出直流电平Vout1和差分放大级的输入直流电平V2重新实现匹配。若此时电流又发生变化，直流恢复运放32输出电压也随之发生变化，使NMOS管MN0的电压电流转换，流过MN0的电流增大或减小，迫使跨阻放大级 输出直流电平恢复到与Vdummy相近的电平，重新匹配跨阻放大级的输出直流电平Vout1和差分放大级的输入直流电平V2，从而提高整个电路的稳定性。
以上所述，仅是本发明实施例而已，并非对本发明的技术范围作任何限制，故凡是依据本发明的技术实质对以上实施例所作的任何细微修改、等同变化与修饰，均仍属于本发明技术方案的范围内。

Claims (7)

  1. 一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：包括跨阻放大级、差分放大级、电平提升单元和直流恢复环路；所述跨阻放大级的输入端用于输入光电流信号，其输出端则直接连接差分放大级的输入端；
    所述直流恢复环路包括伪跨阻放大级、第一滤波单元、第二滤波单元、直流恢复运放和直流通路单元，所述跨阻放大级和伪跨阻放大级并联在电源VDD和电平提升单元之间，所述跨阻放大级的输出端通过第一滤波电路连接直流恢复运放的的反相输入端，所述伪跨阻放大级的输出端通过第二滤波单元连接直流恢复运放的同相输入端，所述直流恢复运放的输出端连接直流通路单元，所述直流通路单元还连接跨阻放大级的输入端。
  2. 根据权利要求1所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述电平提升单元包括尾电流源Itail和电容C3，所述尾电流源Itail和电容C3并联，其一端连接跨阻放大级和伪跨阻放大级，另一端接地。
  3. 根据权利要求1所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述伪跨阻放大级包括包括PMOS管MP2、NMOS管MN2和电阻Rdummy，PMOS管MP2的源极连接电源VDD，栅极连接电阻Rdummy的一端，漏极连接电阻Rdummy的另一端；NMOS管MN2的栅极与电阻Rdummy连接PMOS管MP2栅极的一端连接，NMOS 管MN2的漏极与电阻Rdummy连接PMOS管MP2漏极的一端连接，而NMOS管MN2的源极连接电平提升单元，电阻Rdummy接PMOS管MP2、NMOS管MN2的一端作为伪跨阻放大级的输出端连接至第二滤波单元。
  4. 根据权利要求1所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述直流通路单元包括NMOS管MN0，该NMOS管MN0的栅极连接直流恢复运放的输出端，漏极连接跨阻放大级的输入端，源极接地。
  5. 根据权利要求1所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述直流恢复运放包括PMOS管MP7、NMOS管MN7、PMOS管MP8、NMOS管MN8、PMOS管MP9、电阻Rc、电容Cc、尾电流源Itail2、尾电流源Itail3，NMOS管MN7的栅极连接直流恢复运放的反向输入端，源极经由尾电流源Itail2接地，漏极一方面连接PMOS管MP7的漏极，另一方面NMOS管MN7的漏极还连接PMOS管MP7的栅极，PMOS管MP7的源极连接电源VDD；
    NMOS管MN8的栅极连接直流恢复运放的同向输入端INP，源极经由尾电流源Itail2接地，漏极一方面理解PMOS管MP8的漏极,另一方面依次经由电阻Rc和电容Cc连接至直流回复运放的输出端；PMOS管MP8的栅极连接PMOS管MP7的栅极，PMOS管MP8的源极连接电源VDD；
    PMOS管MP9的栅极连接PMOS管MP8的漏极，PMOS管MP9的源极连接电源VDD，PMOS管MP9的漏极一方面经由尾电流源Itail3接地，另一方面该PMOS管MP9的漏极连接直流恢复运放的输出端。
  6. 根据权利要求1至5任一所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述跨阻放大级包括PMOS管MP1、NMOS管MN1和可变电阻RF，PMOS管MP1的栅极连接跨阻放大级的输入端IN，源极连接电源VDD，漏极连接跨阻放大级的输出端；NMOS管MN1的栅极连接跨阻放大级的输入端，源极连接电平提升单元，漏极连接跨阻放大级的输出端；可变电阻RF的一端连接跨阻放大级的输入端，另一端连接跨阻放大级的输出端。
  7. 根据权利要求6所述的一种用于提高TIA中跨阻放大级输出直流电平的电路，其特征在于：所述第一滤波电路包括电阻R1和电容C1，电阻R1一端连接跨阻放大级的输出端，另一端经由电容C1接地，同时，电阻R1连接电容C1的一端还连接直流恢复运放的反相输入端；所述第二滤波单元包括电阻R2和电容C2，电阻R2一端连接伪跨阻放大级的输出端，另一端经由电容C2接地，同时，电阻R2连接电容C2的一端还连接直流恢复运放的同相输入端。
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