WO2019144754A1 - 信号接收方法 - Google Patents

信号接收方法 Download PDF

Info

Publication number
WO2019144754A1
WO2019144754A1 PCT/CN2018/124202 CN2018124202W WO2019144754A1 WO 2019144754 A1 WO2019144754 A1 WO 2019144754A1 CN 2018124202 W CN2018124202 W CN 2018124202W WO 2019144754 A1 WO2019144754 A1 WO 2019144754A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
sampling
data
bit
clock
Prior art date
Application number
PCT/CN2018/124202
Other languages
English (en)
French (fr)
Inventor
黄廉真
Original Assignee
固高科技(深圳)有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 固高科技(深圳)有限公司 filed Critical 固高科技(深圳)有限公司
Priority to DE112018006746.7T priority Critical patent/DE112018006746T5/de
Publication of WO2019144754A1 publication Critical patent/WO2019144754A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Definitions

  • the present application relates to the field of communications technologies, and in particular, to a signal receiving method.
  • a signal receiving method is provided.
  • a signal receiving method for receiving a data signal sent from a device comprising:
  • the counter When the signal edge of the first sampling signal is detected, the counter is cleared and the counting is restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed;
  • the first sampling signal is collected to obtain a second sampling signal belonging to the local clock of the master device, and a sampling clock signal is generated at the same time, where n is an integer not less than zero, the collecting station
  • the frequency of the data signal sent by the slave device is four times the transmission rate of the data signal sent by the slave device;
  • Sampling is performed in the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value conforms to a rule of a transmission protocol, the second sampling signal is received.
  • the step of collecting a data signal sent from the device to obtain a first sampling signal belonging to the local clock of the slave device includes:
  • the signal edge of the first sampled signal is one of a rising edge and a falling edge.
  • the transmission protocol is an asynchronous transceiving transmission protocol.
  • the transmission protocol is a controller area network bus protocol.
  • the sampling the clock signal is used to sample the second sampling signal to obtain a sampling value.
  • the step of receiving the second sampling signal includes: :
  • sampling clock signal uses the sampling clock signal to extract feature points of the transmission protocol in the second sampling signal and perform verification, and if the verification result is correct, determine a transmission sequence of one frame of data in the second sampling signal.
  • the second sampling signal is received when it is detected that the transmission sequence of the second sampling signal conforms to the rules of the transmission protocol.
  • the feature points include a start bit, an idle bit, and a stop bit.
  • the feature points include a start bit, a parity bit, and a stop bit.
  • the sampling signal is used to extract feature points of the transmission protocol in the second sampling signal and perform verification. If the verification result is correct, determine one of the second sampling signals.
  • the steps of the transmission sequence of the frame data include:
  • the method further includes:
  • the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain the first sample value.
  • the sampling clock signal is a square wave.
  • the data format of the one frame of data includes a 1-bit start bit, a 5-bit data bit, a 1-bit parity bit, and a 1-bit, 1.5-bit or 2-bit end bit.
  • the method further includes: when the transmission sequence of the second sampling signal does not comply with a rule of a transmission protocol, reporting an application layer, and continuing to perform the rising edge of the sampling clock signal The second sampled signal is collected to obtain a first sampled value.
  • the counter when the signal edge of the first sampling signal is detected, the counter is cleared and restarted, and the counter is added every time a clock period of the local clock of the master device is passed.
  • the steps of one include:
  • a signal receiving method for receiving a data signal sent from a device comprising:
  • the counter When the signal edge of the first sampling signal is detected, the counter is cleared and the counting is restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed;
  • the first sampling signal is collected to obtain a second sampling signal belonging to the local clock of the master device, and a sampling clock signal is generated at the same time, where n is an integer not less than zero, the collecting station
  • the frequency of the data signal sent by the slave device is four times the transmission rate of the data signal sent by the slave device;
  • sampling the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value meets a rule of a transmission protocol, receiving the second sampling signal;
  • the step of collecting the data signal sent from the device to obtain the first sampling signal belonging to the local clock of the slave device includes:
  • the step of sampling the second sampling signal by using the sampling clock signal to obtain a sampling value includes:
  • the second sampling signal is received when it is detected that the transmission sequence of the second sampling signal conforms to the rules of the transmission protocol.
  • FIG. 1 is a schematic flow chart of a signal receiving method provided by an embodiment
  • step S140 in the signal receiving method in the embodiment shown in FIG. 1;
  • step S141 in the signal receiving method in the embodiment shown in FIG. 2;
  • step S120 is a schematic flow chart of one embodiment of step S120 in the signal receiving method in the embodiment shown in FIG. 1;
  • FIG. 5 is a timing diagram of one of the steps S110 to S130 in the signal receiving method in the embodiment shown in FIG. 1;
  • Fig. 6 is a timing chart showing one of the embodiments of step S140 in the signal receiving method in the embodiment shown in Fig. 1.
  • an embodiment provides a signal receiving method.
  • the signal receiving method is for receiving a data signal transmitted from a device.
  • the method includes:
  • Step S110 collecting a data signal sent from the device to obtain a first sampling signal belonging to the local clock of the slave device.
  • the I2C bus is a simple, bidirectional two-wire synchronous serial bus.
  • the external physical interface of I2C uses two logical signal lines, one transmission data (SDA) and one transmission clock (SCL), to realize communication between multiple devices through protocols.
  • SDA transmission data
  • SCL transmission clock
  • the master device the device that initiates the bus to transfer data and generate a clock to open the transmission
  • any addressed device is called a slave device.
  • the relationship between master and slave, transmit and receive on the bus is not constant, but depends on the direction of data transfer at this time.
  • the master device wants to send data to the slave device, the master device first addresses the slave device, then actively sends data to the slave device, and finally the master device terminates the data transfer; if the master device wants to receive the slave device's data, the master device first searches for the slave device. Address from the device. The master device then receives the data sent from the slave device and finally terminates the receiving process by the master device.
  • the slave device transmits a data signal with the slave device local clock to the master device, and the master device receives the data signal and performs acquisition, thereby obtaining a first sampled signal with the slave device local clock.
  • Step S120 when the signal edge of the first sampling signal is detected, the counter is cleared and restarted, and the counter is incremented every time the clock period of the local clock of the master device is passed.
  • the master device internally detects the obtained first sampling signal, and when the signal edge of the first sampling signal is detected, clears the counter count, and restarts counting from zero, and the counter encounters one master every time.
  • the count of the device's local clock is incremented by one.
  • the signal edge of the first sampled signal may be a rising edge or a falling edge, but only one of them may be selected.
  • Step S130 when the counter counts up to 2+4n, collecting the first sampling signal, obtaining a second sampling signal belonging to the local clock of the master device, and simultaneously generating a sampling clock signal, where n is an integer not less than zero, and collecting the The frequency of the data signal sent from the device is four times the transmission rate of the data signal transmitted from the device.
  • the first sampling signal is internally sampled by the master device, and the second sampling signal with the local clock of the master device is obtained after multiple sampling, and at the same time, the internal device is in the counter.
  • the sampling is performed, so the count is 2+4n as the sampling clock, and the sampling clock signal is generated.
  • the primary sampling device internally samples the first sampling signal, and on the other hand, the main device internally generates a square wave sampling clock signal, which is equivalent to the local device of the slave device.
  • the clock is synchronized with the local clock of the master device, thereby eliminating the accumulated error caused by the sampling, and after a plurality of times, the second sampling signal and the sampling clock signal with the local clock of the master device are obtained.
  • n is an integer not less than zero
  • the frequency of the data signal transmitted from the device is four times the transmission rate of the data signal transmitted from the device, and four times here may be other multiples, for example, five times, six times, etc. This allows more sampled signals to be acquired from the data signals sent from the device.
  • This step eliminates the problem of time deviation caused by the inconsistent clock frequencies of the master device and the slave device, and also solves the problem that the high-level and low-level durations of the transmitted data signals are not strictly equal.
  • Step S140 sampling the second sampling signal by using the sampling clock signal to obtain a sampling value, and when the sampling value conforms to the rule of the transmission protocol, receiving the second sampling signal.
  • the transmission protocol is an asynchronous transceiver transmission protocol.
  • the transmission protocol may be a CAN (Controller Area Network) protocol or an I2C protocol, and the transmission protocol is not limited to these, as long as the transmission protocol to which the signal receiving method can be applied.
  • this article uses the asynchronous Asynchronous Receiver/Transmitter (Uart) as an example.
  • step S140 includes:
  • Step S141 extracting feature points of the transmission protocol in the second sampling signal by using the sampling clock signal and performing verification, and if the verification result is correct, determining a transmission sequence of one frame of data in the second sampling signal.
  • the feature point includes a start bit, a parity bit, and a stop bit.
  • the feature point may be adjusted according to a transmission protocol.
  • the feature point may also include a start bit and a stop bit, and may also include a start bit, a stop bit, an idle bit, and the like.
  • step S141 includes:
  • Step S1411 collecting the second sampling signal on the rising edge of the sampling clock signal to obtain a first sampling value.
  • the sampling clock signal is a square wave.
  • the main sampling device internally samples the second sampling signal to obtain a sampling value for the second sampling signal.
  • Step S1412 When the first sampled value is zero, the position where the sampled value of the second sampled signal is zero is used as the start bit of one frame of data in the second sampled signal.
  • the data format of one frame of data includes a 1-bit start bit, a 5-bit data bit, a 1-bit parity bit, and a 1-bit, 1.5-bit or 2-bit end bit.
  • the start bit must be a logical "0" level that lasts one bit time, marking the beginning of a character transfer.
  • the data bit is the valid data bit of the transmitted character immediately after the start bit.
  • the low bit of the character is transmitted first, and the high bit of the character is transmitted after the transfer.
  • the data bits are several bits, which can be set by hardware or software. In general, the number of data bits can be between 5 and 8 bits.
  • the parity bit is only one bit and is used for odd or even parity, or no parity.
  • the stop bit is 1 bit, 1.5 bit or 2 bits and can be set by software. It must be a logic "1" level, marking the end of the transmission of a character.
  • the data format of the one frame of data may further include an idle bit, and the idle bit indicates that the line is in an idle state, and the line is at a logic "1" level.
  • the idle bit can be absent, and the efficiency of asynchronous transfer is the highest at this time.
  • the first The position of the sampled value in the second sampled signal is used as the start bit of one frame of data in the second sampled signal.
  • Step S1413 relocating the parity bit and the end bit of one frame of data, and sampling the parity bit and the end bit, respectively corresponding to obtaining the second sample value and the third sample value.
  • the master device internally determines the parity bit and the end bit after 5 bits from the start bit, and then samples the parity bit and the end bit, thereby obtaining respectively.
  • the first sample value and the end bit corresponding to the parity bit correspond to the obtained second sample value.
  • Step S1414 When both the second sample value and the third sample value conform to the rules of the transmission protocol, a transmission sequence of one frame of data in the second sampled signal is determined. For example, in the value of the second sampled value plus the number of bits of "1" in the data bit is even (even parity) or odd (odd check) match, when the third sample value is 1, just send and receive asynchronously
  • the logical "1" level of the stop bit of the transmission protocol matches, meaning the end of one character, thereby determining that the transmission sequence of one frame of data in the current second sampled signal is correct.
  • the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain the first sampling value.
  • the value of the second sample value plus the number of bits of "1" in the data bit is not an odd number or the value of the second sample value is added to the data bit when the even parity is performed.
  • the number of 1" bits is not even, or if the third sample value is not 1, and does not match the logic "1" level of the stop bit of the asynchronous transceiver transmission protocol, it does not comply with the rules of the asynchronous transceiver transmission protocol.
  • the start bit that is initially determined is wrong, so when the main device internally encounters the next rising edge of the sampling clock signal, the second sampling signal is continuously collected, and a first sample value is obtained again.
  • Step S142 buffering a transmission sequence of one frame of data in the second sampling signal, and continuing to determine a transmission sequence of the next frame data in the second sampling signal until a transmission sequence of the second sampling signal is obtained.
  • the transmission sequence of one frame of the correct second sampling signal is buffered, and then the transmission sequence of the next frame data in the second sampling signal is determined according to the above method until the transmission sequence of the second sampling signal is obtained.
  • the first-in first-out method is adopted, that is, the instruction that enters first completes and retires, and then executes the next instruction.
  • Step S143 when it is detected that the transmission sequence of the second sampling signal conforms to the rule of the transmission protocol, the second sampling signal is received. Specifically, it is next detected whether the transmission sequence of the obtained second sampling signal is really correct. If the transmission sequence of the second sampling signal also satisfies the rule of the asynchronous transmission and reception transmission protocol, the obtained second sampling signal is correct. Then the master device receives the second sampling signal. In addition, the detection of the transmission sequence of the second sampled signal is ongoing to ensure the correctness of the transmission sequence of the second sampled signal.
  • the rules for asynchronous transmit and receive transport protocols may also include a level of "1" when there is no data transmission. Therefore, it can also be added to the monitoring rule of the asynchronous transceiving transmission protocol according to this feature, thereby detecting whether the transmission sequence of the transmitted second sampling signal is correct.
  • the application layer is reported, and the second sampling signal is continuously collected on the rising edge of the sampling clock signal to obtain a first sampling value.
  • the master device determines whether the transmission sequence of the obtained second sampling signal is really correct. If the transmission sequence of the second sampling signal does not satisfy the rule of the asynchronous transmission and reception transmission protocol, it is determined that the obtained second sampling signal is an error. On the one hand, the master device initializes and reports to the application layer. On the other hand, the master device then collects the second sampled signal on the next rising signal edge of the sampling clock signal, obtains the first sampled value again, and repeats the above steps.
  • the above signal receiving method first collects a data signal sent from the device to obtain a first sampling signal belonging to a local clock of the slave device, and when detecting a rising edge or a falling edge of the first sampling signal, clearing the counter and restarting counting,
  • the counter counts to 2+4n
  • the first sampling signal is collected, and the second sampling signal belonging to the local clock of the master device is obtained, thereby eliminating the time deviation problem caused by the inconsistent clock frequencies of the master device and the slave device, and counting up at the counter.
  • 2+4n as the sampling clock signal instead of the traditional 0+4n, also solves the problem that the high-level and low-level durations of the transmitted data signal are not strictly equal.
  • the sampling clock signal is used in the second sampling signal.
  • the method solves the problem that the line length transmission delay is introduced between the devices due to the existence of the transmission distance, thereby causing the sequence of the received data to be misaligned.
  • step S110 includes:
  • the data signal sent from the device is collected, the data signal is filtered, and the filtered data signal is output through the register to obtain a first sampling signal belonging to the local clock of the slave device.
  • the master device collects the data signal sent by the slave device, first filters some noise in the data signal through low-pass filtering, and then outputs the filtered data signal through the register, thereby reducing the appearance of the master device when collecting the data signal.
  • the probability of steady state also reduces the distortion of the signal transmission, and also obtains the first sampled signal with the local clock of the slave device.
  • step S120 includes:
  • Step S121 detecting and collecting a signal edge of the first sampling signal to generate a signal edge signal, wherein the signal edge is a rising edge or a falling edge.
  • the signal of the first sampling signal is detected to be edge-acquired, so that the signal edge is generated according to the acquired signal edge, and the signal edge can only be one of a rising edge or a falling edge of the first sampling signal.
  • Step S122 when the counter encounters the signal edge of the signal edge signal, the counter is cleared and restarts counting. Specifically, when the counter encounters a rising or falling edge of the signal edge when counting, the counter's count will all be cleared and recounted from zero.
  • FIG. 5 a timing diagram of a data signal sent by a master device to a slave device according to an embodiment of the signal receiving method.
  • the slave device transmits the data signal B_Tx with the slave device local clock to the master device, and the master device receives the data signal B_Tx and performs acquisition to obtain the data signal A_Rx. Then, some noise in the data signal A_Rx is filtered out by low-pass filtering, and the filtered data signal is output through the register to obtain a first sampling signal A_Rx_Filter with a slave local clock.
  • the acquisition is performed when the rising edge of the first sampling signal A_Rx_Filter is detected, thereby generating a signal edge positive_edge according to the collected rising edge.
  • the main device internally samples the first sampling signal A_Rx_Filter once, and after sampling a plurality of times, obtains the second sampling signal A_Rx_Filter_q with the local clock of the main device, and at the same time, the counter is internally in the counter.
  • the count of Cnt is 2+4n, sampling is performed, so the count is 2+4n as the sampling clock, and the sampling clock signal sample_clk is generated.
  • the second sampling signal A_Rx_Filter_q is collected on the rising edge of the sampling clock signal sample_clk to obtain a first sampling value.
  • the position where the sampled value of the second sampled signal A_Rx_Filter_q is zero is taken as the start bit Beg of one frame of data in the second sampled signal A_Rx_Filter_q.
  • the parity bit Check and the end bit End of one frame of data are repositioned, and the parity bit Check and the end bit End are sampled, and the second sample value and the third sample value are respectively obtained.
  • a transmission sequence of one frame of data in the second sampled signal A_Rx_Filter_q is determined.
  • the transmission sequence of one frame of data in the second sampling signal A_Rx_Filter_q is buffered, and the transmission sequence of the next frame data in the second sampling signal A_Rx_Filter_q is continuously determined until the transmission sequence of the second sampling signal A_Rx_Filter_q is obtained.
  • the second sampling signal A_Rx_Filter_q is received.
  • the application layer is reported, and the second sampling signal A_Rx_Filter_q is continuously collected on the rising edge of the sampling clock signal sample_clk to obtain a first sampling value.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

一种信号接收方法，用于接收从设备发送的数据信号，方法包括：采集从设备发送的数据信号，得到属于从设备本地时钟的第一采样信号；当检测到第一采样信号的信号沿时，将计数器清零并重新开始计数；在计数器计数达2+4n时，对第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，采集从设备发送的数据信号的频率为四倍从设备发送的数据信号的传输速率；及利用采样时钟信号在第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收第二采样信号。

Description

信号接收方法
本申请要求于2018年1月25日提交中国专利局，申请号为2018100745811，申请名称为“信号接收方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，特别是涉及一种信号接收方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成现有技术。
在工业设备中，很大一部分设备之间的通信采用协议加串行通信的方法。其通信过程一般是设备A往设备B发起数据，然后设备B应答。根据数字电路的采集信号原理，对建立保持时间的要求，设备对线上信号进行可靠采集必须满足采样保持时间的要求。同时，在处理协议时，由于设备之间存在一定的传输距离，而该传输距离的存在会引入线长传输延迟，导致接收数据的序列发生错位。
发明内容
根据本申请公开的各种实施例，提供一种信号接收方法。
一种信号接收方法，用于接收从设备发送的数据信号，所述方法包括：
采集所述从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号；
当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器每经过一个所述主设备本地时钟的时钟周期时加一；
在所述计数器计数达2+4n时，对所述第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，其中n为不小于零的整数，采集所述从设备发送的数据信号的频率为四倍所述从设备发送的数据信号的传输速率；及
利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号。
在其中一个实施例中，所述采集从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号的步骤包括：
采集从设备发送的数据信号，对所述数据信号进行滤波处理，并将滤波后的所述数据信号通过寄存器输出，得到属于所述从设备本地时钟的第一采样信号。
在其中一个实施例中，所述第一采样信号的信号沿为上升沿和下降沿中的一种。
在其中一个实施例中，所述传输协议为异步收发传输协议。
在其中一个实施例中，所述传输协议为控制器局域网总线协议。
在其中一个实施例中，所述利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号的步骤包括：
利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列。
缓存所述第二采样信号中一帧数据的传输序列，继续确定所述第二采样信号中下一帧数据的传输序列，直至得到所述第二采样信号的传输序列；及
当检测到所述第二采样信号的传输序列符合传输协议的规则时，则接收所述第二采样信号。
在其中一个实施例中，所述特征点包括起始位、空闲位及停止位。
在其中一个实施例中，所述特征点包括起始位、奇偶校验位及停止位。
在其中一个实施例中，所述利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列的步骤包括：
在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值；
当所述第一采样值为零时，将所述第二采样信号中所述采样值为零的位置作为所述第二采样信号中一帧数据的起始位；
再定位到所述一帧数据的奇偶校验位和结束位，并对所述奇偶校验位和所述结束位进行采样，分别对应得到第二采样值和第三采样值；及
当所述第二采样值和所述第三采样值均符合传输协议的规则时，则确定所述第二采样信号中一帧数据的传输序列。
在其中一个实施例中，所述方法还包括：
当所述第二采样值和所述第三采样值中的任一个不符合传输协议的规则时，则继续在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值。
在其中一个实施例中，所述采样时钟信号呈方形波。
在其中一个实施例中，所述一帧数据的数据格式包括1位起始位、5位数据位、1位奇偶校验位及1位、1.5位或2位结束位。
在其中一个实施例中，所述方法还包括：当所述第二采样信号的传输序列不符合传输协议的规则时，则上报应用层，并继续在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值。
在其中一个实施例中，所述当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器是每经过一个所述主设备本地时钟的时钟周期时加一的步骤包括：
检测并采集所述第一采样信号的信号沿，生成信号沿信号，其中所述信号沿是上升沿或下降沿；
当计数器遇到所述信号沿信号的信号沿时，计数器清零并重新开始计数。
一种信号接收方法，用于接收从设备发送的数据信号，所述方法包括：
采集所述从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号；
当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器每经过一个所述主设备本地时钟的时钟周期时加一；
在所述计数器计数达2+4n时，对所述第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，其中n为不小于零的整数，采集所述从设备发送的数据信号的频率为四倍所述从设备发送的数据信号的传输速率；及
利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号；
其中，所述采集从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号的步骤包括：
采集从设备发送的数据信号，对所述数据信号进行滤波处理，并将滤波后的所述数据信号通过寄存器输出，得到属于所述从设备本地时钟的第一采样信号；
所述利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号的步骤包括：
利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列；
缓存所述第二采样信号中一帧数据的传输序列，继续确定所述第二采样信号中下一帧数据的传输序列，直至得到所述第二采样信号的传输序列；及
当检测到所述第二采样信号的传输序列符合传输协议的规则时，则接收所述第二采样信号。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1为一实施方式提供的信号接收方法的流程示意图；
图2为图1所示实施方式中的信号接收方法中步骤S140的其中一个实施例的流程示意图；
图3为图2所示实施例中的信号接收方法中步骤S141的其中一个实施例的流程示意图；
图4为图1所示实施方式中的信号接收方法中步骤S120的其中一个实施例的流程示意图；
图5为图1所示实施方式中的信号接收方法中步骤S110至步骤S130的其中一个实施例的时序图；
图6为图1所示实施方式中的信号接收方法中步骤S140的其中一个实施例的时序图。
具体实施方式
为了使本申请的技术方案及优点更加清楚明白，以下结合附图及实施例，对本申请进行进一步详细说明。应当理解，此处描述的具体实施例仅仅用以解释本申请，并不用于限定本申请。
请参考图1，一实施方式提供了一种信号接收方法。该信号接收方法用于接收从设备发送的数据信号。该方法包括：
步骤S110，采集从设备发送的数据信号，得到属于从设备本地时钟的第一采样信号。
例如，I2C总线是一种简单、双向二线制同步串行总线。I2C的外部物理 接口采用两根逻辑信号线，一根传输数据(SDA)，一根传输时钟(SCL)，通过协议实现多个设备间的通信。那么，启动总线传送数据，并产生时钟以开放传送的设备称之为主设备，此时任何被寻址的设备均称之为从设备。在总线上主和从、发和收的关系也不是恒定的，而取决于此时数据传送方向。如果主设备要发送数据给从设备，则主设备首先寻址从设备，然后主动发送数据至从设备，最后由主设备终止数据传送；如果主设备要接收从设备的数据，首先由主设备寻址从设备。然后主设备接收从设备发送的数据，最后由主设备终止接收过程。
具体地，从设备将带有从设备本地时钟的数据信号发送至主设备，主设备接收该数据信号并进行采集，从而得到带有从设备本地时钟的第一采样信号。
步骤S120，当检测到第一采样信号的信号沿时，将计数器清零并重新开始计数，计数器是每经过一个主设备本地时钟的时钟周期时加一。
具体地，主设备内部对所得到的第一采样信号进行检测，当检测到第一采样信号的信号沿时，将计数器的计数清零，并重新开始从零计数，计数器在每遇到一个主设备本地时钟的时钟周期时计数加一。另外，第一采样信号的信号沿可以是上升沿，也可以是下降沿，但只能选择其中的一种。
步骤S130，在计数器计数达2+4n时，对第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，其中n为不小于零的整数，采集所述从设备发送的数据信号的频率为四倍从设备发送的数据信号的传输速率。
具体地，在计数器的计数为2+4n时，主设备内部对第一采样信号进行一次采样，多次采样后得到带有主设备本地时钟的第二采样信号，同时由于主设备内部是在计数器的计数为2+4n时进行采样，因此将计数为2+4n作为采样时钟，而生成采样时钟信号。简单来说，在计数器计数为2+4n时，一方面主设备内部对第一采样信号进行一次采样，另一方面主设备内部也生成一个方波的采样时钟信号，相当于将从设备的本地时钟与主设备的本地时钟同步 一次，从而消除对采样所造成的累计误差，多次之后就得到带有主设备本地时钟的第二采样信号和采样时钟信号。其中n为不小于零的整数，采集从设备发送的数据信号的频率为四倍从设备发送的数据信号的传输速率，这里的四倍也可以是其他倍数，例如，五倍、六倍等，这样可以从从设备发送的数据信号中获取到更多的采样信号。该步骤消除了主设备和从设备的时钟频率不一致而引起的时间偏差问题，也解决了所传输的数据信号的高电平和低电平持续时间不严格相等的问题。
步骤S140，利用采样时钟信号在第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收第二采样信号。
其中，传输协议是异步收发传输协议。另外传输协议可以是CAN(Controller Area Network，控制器局域网总线)协议，也可以是I2C协议，传输协议并不限于这些，只要能适用该信号接收方法的传输协议均可。为了方便，本文以异步收发传输协议(Universal Asynchronous Receiver/Transmitter，Uart)为例进行说明。
在一实施例中，请参考图2，步骤S140包括：
步骤S141，利用采样时钟信号在第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定第二采样信号中一帧数据的传输序列。
其中，该特征点包括起始位、奇偶校验位及停止位。另外，该特征点可根据传输协议做出调整，例如，特征点也可包括起始位和停止位，还可包括起始位、停止位和空闲位等。
具体地，请参考图3，步骤S141包括：
步骤S1411，在采样时钟信号的上升沿对第二采样信号进行采集，得到第一采样值。可选地，采样时钟信号呈方形波，在遇到采样时钟信号的上升沿时，主设备内部对第二采样信号进行一次采样，从而得到关于第二采样信号的一个采样值。
步骤S1412，当第一采样值为零时，将第二采样信号中采样值为零的位置作为第二采样信号中一帧数据的起始位。
其中，一帧数据的数据格式包括1位起始位、5位数据位、1位奇偶校验位及1位、1.5位或2位结束位。具体地，起始位必须是持续一个比特时间的逻辑“0”电平，标志传送一个字符的开始。数据位是紧跟在起始位之后，是被传送字符的有效数据位，传送时先传送字符的低位，后传送字符的高位。数据位究竟是几位，可由硬件或软件来设定，一般情况下，数据位的位数可以在5至8位之间。奇偶校验位仅占一位，用于进行奇校验或偶校验，也可以不设奇偶位。停止位为1位、1.5位或2位，可由软件设定。它一定是逻辑“1”电平，标志着传送一个字符的结束。另外，该一帧数据的数据格式还可包括空闲位，空闲位表示线路处于空闲状态，此时线路上为逻辑“1”电平。空闲位可以没有，此时异步传送的效率为最高。
具体地，先判断该第一采样值是否为零，当该第一采样值为零时，正好与一帧数据中的起始位的逻辑“0”电平相匹配，则先将该第一采样值在第二采样信号中的位置作为第二采样信号中一帧数据的起始位。
步骤S1413，再定位到一帧数据的奇偶校验位和结束位，并对奇偶校验位和结束位进行采样，分别对应得到第二采样值和第三采样值。例如，在数据位为5位时，主设备内部从而依次确定了与起始位相隔5位之后的奇偶校验位和结束位，再对该奇偶校验位和结束位进行采样，从而分别得到该奇偶校验位对应的第一采样值和结束位对应得到的第二采样值。
步骤S1414，当第二采样值和第三采样值均符合传输协议的规则时，则确定第二采样信号中一帧数据的传输序列。例如，在第二采样值的数值加上数据位中“1”的位数为偶数(偶校验)或奇数(奇校验)相匹配，在第三采样值为1时，正好与异步收发传输协议的停止位的逻辑“1”电平相匹配，意味着一个字符的结束，从而确定了当前的第二采样信号中的一帧数据的传输序列是正确的。
在一实施例中，当第二采样值和第三采样值中的任一个不符合传输协议的规则时，则继续在采样时钟信号的上升沿对第二采样信号进行采集，得到第一采样值。具体地，在进行奇校验时，第二采样值的数值加上数据位中“1” 的位数不为奇数或者在进行偶校验时，第二采样值的数值加上数据位中“1”的位数不为偶数，或者在第三采样值不为1，与异步收发传输协议的停止位的逻辑“1”电平不相匹配，则不符合异步收发传输协议的规则，说明刚开始确定的起始位是错误的，于是主设备内部在遇到采样时钟信号的下一个上升沿时，继续对第二采样信号进行采集，再次获得一个第一采样值。
步骤S142，缓存第二采样信号中一帧数据的传输序列，继续确定第二采样信号中下一帧数据的传输序列，直至得到第二采样信号的传输序列。具体地，对该正确的第二采样信号中的一帧数据的传输序列进行缓存，接着按照上述方法确定第二采样信号中的下一帧数据的传输序列，直至得到第二采样信号的传输序列。对于所缓存的一帧数据采用先入先出的方式，即先进入的指令先完成并引退，跟着才执行下一条指令。
步骤S143，当检测到第二采样信号的传输序列符合传输协议的规则时，则接收第二采样信号。具体地，接着检测上述所得到的第二采样信号的传输序列是否真的正确，如果第二采样信号的传输序列也满足异步收发传输协议的规则时，则获得的第二采样信号是正确的，则主设备接收该第二采样信号。另外，对第二采样信号的传输序列的检测是一直进行的，以确保第二采样信号的传输序列的正确性。异步收发传输协议的规则也可包括在没有数据传输时，电平一直为“1”。因此，也可根据这一特点添加到异步收发传输协议的监控规则里，从而检测所传输的第二采样信号的传输序列是否正确。
在一实施例中，当第二采样信号的传输序列不符合传输协议的规则时，则上报应用层，并继续在采样时钟信号的上升沿对第二采样信号进行采集，得到第一采样值。
具体地，接着检测上述所得到的第二采样信号的传输序列是否真的正确，如果第二采样信号的传输序列不满足异步收发传输协议的规则时，则判断所获得的第二采样信号是错误的，一方面主设备进行初始化，并上报应用层，另一方面主设备接着在采样时钟信号的下一个上升信号沿对第二采样信号进行采集，再次获得第一采样值，再重复上述步骤。
上述信号接收方法，先采集从设备发送的数据信号，得到属于从设备本地时钟的第一采样信号，检测到第一采样信号的上升沿或下降沿时，将计数器清零并重新开始计数，在计数器计数为2+4n时开始采集第一采样信号，得到属于主设备本地时钟的第二采样信号，从而消除了主设备和从设备的时钟频率不一致而引起的时间偏差问题，同时在计数器计数达2+4n作为采样时钟信号，而不是传统的0+4n，也解决了所传输的数据信号的高电平和低电平持续时间不严格相等的问题，最后利用采样时钟信号在第二采样信号中进行采样得到采样值，判断出采样值符合传输协议的规则时，则接收第二采样信号的传输序列。因此，该方法解决了设备之间由于传输距离的存在而引入线长传输延迟，进而导致接收数据的序列发生错位的问题。
在一实施例中，步骤S110包括：
采集从设备发送的数据信号，对数据信号进行滤波处理，并将滤波后的数据信号通过寄存器输出，得到属于从设备本地时钟的第一采样信号。
具体地，主设备采集从设备发送的数据信号，先通过低通滤波滤除数据信号中的一些噪声，再将经过滤波后的数据信号通过寄存器输出，从而降低了主设备采集数据信号时出现亚稳态的概率，也减少了信号传输畸变，同时也得到了带有从设备本地时钟的第一采样信号。
在一实施例中，请参考图4，步骤S120包括：
步骤S121，检测并采集第一采样信号的信号沿，生成信号沿信号，其中信号沿是上升沿或下降沿。具体地，检测到第一采样信号的信号沿时进行采集，从而根据所采集到的信号沿生成信号沿信号，该信号沿只能是第一采样信号的上升沿或下降沿中的一种。
步骤S122，当计数器遇到信号沿信号的信号沿时，计数器清零并重新开始计数。具体地，计数器在计数时遇到信号沿信号的上升沿或下降沿时，计数器的计数将全部清零，并从零开始重新计数。
请参考图5，为信号接收方法中一实施例主设备接收从设备所发送的数据信号的时序图。从设备将带有从设备本地时钟的数据信号B_Tx发送至主设 备，主设备接收该数据信号B_Tx并进行采集，得到数据信号A_Rx。再通过低通滤波滤除数据信号A_Rx中的一些噪声，将经过滤波后的数据信号通过寄存器输出，得到了带有从设备本地时钟的第一采样信号A_Rx_Filter。检测到第一采样信号A_Rx_Filter的上升沿时进行采集，从而根据所采集到的上升沿生成信号沿信号positive_edge。计数器Cnt在计数时遇到信号沿信号positive_edge的上升沿时，计数器Cnt的计数将全部清零，并从零开始计数，且计数器Cnt在每经过一个主设备本地时钟Clock的时钟周期时加一。在计数器Cnt的计数为2+4n时，主设备内部对第一采样信号A_Rx_Filter进行一次采样，多次采样后得到带有主设备本地时钟的第二采样信号A_Rx_Filter_q，同时由于主设备内部是在计数器Cnt的计数为2+4n时进行采样，因此将计数为2+4n作为采样时钟，而生成采样时钟信号sample_clk。请参考图6，在采样时钟信号sample_clk的上升沿对第二采样信号A_Rx_Filter_q进行采集，得到第一采样值。当第一采样值为零时，将第二采样信号A_Rx_Filter_q中采样值为零的位置作为第二采样信号A_Rx_Filter_q中一帧数据的起始位Beg。再定位到一帧数据的奇偶校验位Check和结束位End，并对奇偶校验位Check和结束位End进行采样，分别对应得到第二采样值和第三采样值。当第二采样值和第三采样值均符合Uart传输协议的规则时，则确定第二采样信号A_Rx_Filter_q中一帧数据的传输序列。缓存第二采样信号A_Rx_Filter_q中一帧数据的传输序列，继续确定第二采样信号A_Rx_Filter_q中下一帧数据的传输序列，直至得到第二采样信号A_Rx_Filter_q的传输序列。当检测到第二采样信号A_Rx_Filter_q的传输序列符合传输协议的规则时，则接收第二采样信号A_Rx_Filter_q。当第二采样信号A_Rx_Filter_q的传输序列不符合Uart传输协议的规则时，则上报应用层，并继续在采样时钟信号sample_clk的上升沿对第二采样信号A_Rx_Filter_q进行采集，得到第一采样值。
应该理解的是，虽然上述实施例的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以 以其它的顺序执行。而且，图1至图4中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也并非都需要依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本申请的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对本申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本申请构思的前提下，还可以做出若干变形和改进，这些都属于本申请的保护范围。因此，本申请专利的保护范围应以所附权利要求为准。

Claims (15)

  1. 一种信号接收方法，用于接收从设备发送的数据信号，所述方法包括：
    采集所述从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号；
    当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器每经过一个所述主设备本地时钟的时钟周期时加一；
    在所述计数器计数达2+4n时，对所述第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，其中n为不小于零的整数，采集所述从设备发送的数据信号的频率为四倍所述从设备发送的数据信号的传输速率；及
    利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号。
  2. 根据权利要求1所述的信号接收方法，其中，所述采集从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号的步骤包括：
    采集从设备发送的数据信号，对所述数据信号进行滤波处理，并将滤波后的所述数据信号通过寄存器输出，得到属于所述从设备本地时钟的第一采样信号。
  3. 根据权利要求1所述的信号接收方法，其中，所述第一采样信号的信号沿包括上升沿和下降沿中的一种。
  4. 根据权利要求1所述的信号接收方法，其中，所述传输协议为异步收发传输协议。
  5. 根据权利要求1所述的信号接收方法，其中，所述传输协议为控制器局域网总线协议。
  6. 根据权利要求1所述的信号接收方法，其中，所述利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号的步骤包括：
    利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并 进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列；
    缓存所述第二采样信号中一帧数据的传输序列，继续确定所述第二采样信号中下一帧数据的传输序列，直至得到所述第二采样信号的传输序列；及
    当检测到所述第二采样信号的传输序列符合传输协议的规则时，则接收所述第二采样信号。
  7. 根据权利要求6所述的信号接收方法，其中，所述特征点包括起始位、空闲位及停止位。
  8. 根据权利要求6所述的信号接收方法，其中，所述特征点包括起始位、奇偶校验位及停止位。
  9. 根据权利要求8所述的信号接收方法，其中，所述利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列的步骤包括：
    在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值；
    当所述第一采样值为零时，将所述第二采样信号中所述采样值为零的位置作为所述第二采样信号中一帧数据的起始位；
    再定位到所述一帧数据的奇偶校验位和结束位，并对所述奇偶校验位和所述结束位进行采样，分别对应得到第二采样值和第三采样值；及
    当所述第二采样值和所述第三采样值均符合传输协议的规则时，则确定所述第二采样信号中一帧数据的传输序列。
  10. 根据权利要求9所述的信号接收方法，其中，所述方法还包括：
    当所述第二采样值和所述第三采样值中的任一个不符合传输协议的规则时，则继续在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值。
  11. 根据权利要求9所述的信号接收方法，其中，所述采样时钟信号呈方形波。
  12. 根据权利要求6所述的信号接收方法，其中，所述一帧数据的数据格式包括1位起始位、5位数据位、1位奇偶校验位及1位、1.5位或2位结束位。
  13. 根据权利要求6所述的信号接收方法，其中，所述方法还包括：当所述第二采样信号的传输序列不符合传输协议的规则时，则上报应用层，并继续在所述采样时钟信号的上升沿对所述第二采样信号进行采集，得到第一采样值。
  14. 根据权利要求1所述的信号接收方法，其中，所述当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器是每经过一个所述主设备本地时钟的时钟周期时加一的步骤包括：
    检测并采集所述第一采样信号的信号沿，生成信号沿信号，其中所述信号沿是上升沿或下降沿；
    当计数器遇到所述信号沿信号的信号沿时，计数器清零并重新开始计数。
  15. 一种信号接收方法，用于接收从设备发送的数据信号，所述方法包括：
    采集所述从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号；
    当检测到所述第一采样信号的信号沿时，将计数器清零并重新开始计数，所述计数器每经过一个所述主设备本地时钟的时钟周期时加一；
    在所述计数器计数达2+4n时，对所述第一采样信号进行采集，得到属于主设备本地时钟的第二采样信号，同时生成采样时钟信号，其中n为不小于零的整数，采集所述从设备发送的数据信号的频率为四倍所述从设备发送的数据信号的传输速率；及
    利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号；
    其中，所述采集从设备发送的数据信号，得到属于所述从设备本地时钟的第一采样信号的步骤包括：
    采集从设备发送的数据信号，对所述数据信号进行滤波处理，并将滤波后的所述数据信号通过寄存器输出，得到属于所述从设备本地时钟的第一采样信号；
    所述利用所述采样时钟信号在所述第二采样信号中进行采样得到采样值，当采样值符合传输协议的规则时，则接收所述第二采样信号的步骤包括：
    利用所述采样时钟信号在所述第二采样信号中提取传输协议的特征点并进行校验，若校验结果正确，则确定所述第二采样信号中一帧数据的传输序列；
    缓存所述第二采样信号中一帧数据的传输序列，继续确定所述第二采样信号中下一帧数据的传输序列，直至得到所述第二采样信号的传输序列；及
    当检测到所述第二采样信号的传输序列符合传输协议的规则时，则接收所述第二采样信号。
PCT/CN2018/124202 2018-01-25 2018-12-27 信号接收方法 WO2019144754A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE112018006746.7T DE112018006746T5 (de) 2018-01-25 2018-12-27 Signalempfangsverfahren

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201810074581.1A CN108390752B (zh) 2018-01-25 2018-01-25 信号接收方法
CN201810074581.1 2018-01-25

Publications (1)

Publication Number Publication Date
WO2019144754A1 true WO2019144754A1 (zh) 2019-08-01

Family

ID=63077240

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/124202 WO2019144754A1 (zh) 2018-01-25 2018-12-27 信号接收方法

Country Status (3)

Country Link
CN (1) CN108390752B (zh)
DE (1) DE112018006746T5 (zh)
WO (1) WO2019144754A1 (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108390752B (zh) * 2018-01-25 2020-12-22 固高科技(深圳)有限公司 信号接收方法
CN109885525B (zh) * 2019-03-19 2021-02-12 西安联飞智能装备研究院有限责任公司 Uart接收方法、装置、电子设备及可读存储介质
CN112165525B (zh) * 2020-09-28 2023-12-08 北京视界恒通科技有限公司 一种串行数据透传方法及装置
CN112653924A (zh) * 2020-12-15 2021-04-13 上海安路信息科技有限公司 Hdmi接收方法及装置
CN113656340A (zh) * 2021-08-20 2021-11-16 西安易朴通讯技术有限公司 I2c总线的通信控制方法、***和装置
CN114885046B (zh) * 2022-07-12 2022-09-20 成都市易冲半导体有限公司 一种scp串行通信协议的可靠高效解析方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110122981A1 (en) * 2001-02-21 2011-05-26 Wi-Lan, Inc. Synchronizing clocks across a communication link
CN102347813A (zh) * 2011-09-26 2012-02-08 华为技术有限公司 一种选取采样时钟信号的方法和设备
US8737552B1 (en) * 2011-01-19 2014-05-27 Xilinx, Inc. Synchronous data transfer
CN106301656A (zh) * 2016-08-30 2017-01-04 北京飞利信电子技术有限公司 一种提高时间戳测量精度的方法及装置
CN106921463A (zh) * 2015-12-28 2017-07-04 航天信息股份有限公司 一种抗干扰解码方法及***
CN108390752A (zh) * 2018-01-25 2018-08-10 固高科技(深圳)有限公司 信号接收方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1510861A (zh) * 2002-12-26 2004-07-07 华为技术有限公司 一种控制***时钟频率的方法
US9335785B2 (en) * 2011-07-20 2016-05-10 Aviat U.S., Inc. Systems and methods of clock synchronization between devices on a network
CN107623556A (zh) * 2016-07-13 2018-01-23 北京捷联微芯科技有限公司 通讯***中时钟同步方法及其***

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110122981A1 (en) * 2001-02-21 2011-05-26 Wi-Lan, Inc. Synchronizing clocks across a communication link
US8737552B1 (en) * 2011-01-19 2014-05-27 Xilinx, Inc. Synchronous data transfer
CN102347813A (zh) * 2011-09-26 2012-02-08 华为技术有限公司 一种选取采样时钟信号的方法和设备
CN106921463A (zh) * 2015-12-28 2017-07-04 航天信息股份有限公司 一种抗干扰解码方法及***
CN106301656A (zh) * 2016-08-30 2017-01-04 北京飞利信电子技术有限公司 一种提高时间戳测量精度的方法及装置
CN108390752A (zh) * 2018-01-25 2018-08-10 固高科技(深圳)有限公司 信号接收方法

Also Published As

Publication number Publication date
CN108390752A (zh) 2018-08-10
CN108390752B (zh) 2020-12-22
DE112018006746T5 (de) 2020-09-17

Similar Documents

Publication Publication Date Title
WO2019144754A1 (zh) 信号接收方法
Fang et al. Design and simulation of UART serial communication module based on VHDL
WO2020029023A1 (zh) 波特率校准电路及串口芯片
CN1812317A (zh) 同步媒介访问控制器
CN109101453B (zh) 异步串行通信采样***和方法
CN104008078A (zh) 一种基于fpga的数据传输板之间进行高速传输的方法
CN103595588A (zh) 一种非同步以太网精确测量线路延时方法
CN103107862B (zh) 逻辑器件及其mdio数据发送方法
CN103024367B (zh) 低压差分信号lvds接收器、发送器及lvds接收、发送处理方法
CN101719858A (zh) Can控制器的位时序的同步处理方法
US20230071506A1 (en) Method for signal detection, electronic device, and storage medium
US20130016762A1 (en) Data communication system, method of optimizing preamble length, and communication apparatus
JPH0983608A (ja) 時刻同期装置
CN113688083B (zh) 一种基于同步422接口的数据帧头识别***及方法
JP2011091742A (ja) 通信装置
CN103840934A (zh) 一种基于时钟自动恢复的开销传递方法及装置
CN107786309B (zh) 一种免时钟同步的芯片数据传输方法、***及电子设备
CN113534888A (zh) 一种基于fpga的多张vpx板卡时间同步方法和装置
KR101396912B1 (ko) ＳｅｒＤｅｓ 네트워크에서의 직렬 링크 동기화 방법
CN112640355B (zh) 一种mac装置及时间点估算方法
KR100949856B1 (ko) 입력되는 직렬 배열 시퀀스의 레이트 검증
CN108509365B (zh) 一种dbi的数据传输方法及***
JP3277948B2 (ja) ディジタル信号受信装置
CN111966623A (zh) Mcu与多个fpga使用spi进行实时全双工可靠通信的方法
JP4157064B2 (ja) 同期開始信号検出装置、その検出方法、及びそのプログラム

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18902287

Country of ref document: EP

Kind code of ref document: A1

122 Ep: pct application non-entry in european phase

Ref document number: 18902287

Country of ref document: EP

Kind code of ref document: A1