WO2019142065A1 - 表示装置 - Google Patents
表示装置 Download PDFInfo
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- WO2019142065A1 WO2019142065A1 PCT/IB2019/050112 IB2019050112W WO2019142065A1 WO 2019142065 A1 WO2019142065 A1 WO 2019142065A1 IB 2019050112 W IB2019050112 W IB 2019050112W WO 2019142065 A1 WO2019142065 A1 WO 2019142065A1
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- WIPO (PCT)
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- transistor
- display device
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- circuit
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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Definitions
- One embodiment of the present invention relates to a display device and an operation method thereof.
- the technical field of one embodiment of the present invention includes a semiconductor device, a display device, a light emitting device, a display system, an electronic device, a lighting device, an input device (eg, a touch sensor or the like), an input / output device (eg, a touch panel or the like),
- an input device eg, a touch sensor or the like
- an input / output device eg, a touch panel or the like
- the driving method of or the manufacturing method of them can be mentioned as an example.
- a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
- Display devices liquid crystal display devices, light emitting display devices, and the like
- projection devices lighting devices
- electro-optical devices power storage devices
- memory devices semiconductor circuits
- imaging devices electronic devices, and the like
- semiconductor devices it may be said that these have a semiconductor device.
- Patent Document 1 discloses a display device with high withstand voltage that can drive a display device with a high voltage.
- a source driver circuit capable of outputting a high voltage is required.
- a source driver circuit occupies a large area and is expensive.
- An object of one embodiment of the present invention is to provide a display device capable of supplying a high voltage to a display device.
- An object of one embodiment of the present invention is to provide a small display device.
- An object of one embodiment of the present invention is to provide a low-cost display device.
- An object of one embodiment of the present invention is to provide a display device with low power consumption.
- An object of one embodiment of the present invention is to provide a highly reliable display device.
- An object of one embodiment of the present invention is to provide a display device with high display quality.
- An object of one embodiment of the present invention is to provide a novel display device.
- An object of one embodiment of the present invention is to provide an operation method of the display device.
- One embodiment of the present invention is a display device including a first circuit, a second circuit, and a pixel, wherein the first circuit includes first data and second data.
- the second circuit has a function of generating digital image data, the second circuit is electrically connected to the pixel through the first wiring, and the second circuit is electrically connected to the pixel through the second wiring.
- the second circuit has a function of setting the potential of the first wiring to one of the potential corresponding to the first data or the potential corresponding to the second data.
- the pixel has a function of changing the potential of the second wiring to the other of the potential corresponding to the first data or the potential corresponding to the second data
- the pixel includes a first transistor and a second transistor, And one of a source and a drain of the first transistor is a capacitor element. And one electrode of the capacitive element is electrically connected to one electrode of the display device, and one of the source or drain of the second transistor is electrically connected to the other electrode of the capacitive element. And the other of the source or the drain of the first transistor is electrically connected to the first wiring, and the other of the source or the drain of the second transistor is electrically connected to the second wiring.
- the display device is a display device having a function of displaying an image corresponding to image data.
- the second circuit includes a selection circuit, and the selection circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal.
- the first input terminal is supplied with a potential corresponding to the first data
- the second input terminal is supplied with a potential corresponding to the second data
- the first output terminal is
- the second output terminal may be electrically connected to the second wiring.
- the second circuit includes a first switch and a second switch, and the second input terminal is one terminal of the first switch and the second switch.
- a first potential is supplied to the other terminal of the first switch, which is electrically connected to one of the terminals, and a second potential is supplied to the other terminal of the second switch.
- the second switch and the second switch may be on / off controlled by the second data.
- the second data may include information on the most significant bit of the digital image data.
- the second circuit may be a source driver circuit.
- the display device may be a liquid crystal device.
- the display device may have a liquid crystal exhibiting a blue phase.
- the first and second transistors each include a metal oxide in a channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, or Y. , Zr, La, Ce, Nd, or Hf).
- a display device capable of supplying a high voltage to a display device can be provided.
- a small display device can be provided.
- a low cost display device can be provided.
- a display device with low power consumption can be provided.
- a highly reliable display device can be provided.
- a display device with high display quality can be provided.
- a novel display device can be provided. According to one aspect of the present invention, it is possible to provide a method of operating the display device.
- FIG. 5A and 5B illustrate an example of a display device and a diagram for describing image data.
- 7A and 7B illustrate an example of a display device and an example of characteristics of a DA converter circuit.
- FIG. 8 shows an example of operation of a display device.
- FIG. 7 is a diagram illustrating an example of a display device.
- 5A and 5B illustrate an example of a display device and a diagram illustrating an example of operation of the display device.
- FIG. 7 is a diagram illustrating an example of a display device.
- FIG. 8 shows an example of operation of a display device.
- FIG. 2 is a diagram showing an example of a pixel.
- FIG. 6 shows an example of the operation of a pixel.
- FIG. 2 is a diagram showing an example of a pixel.
- FIG. 6 shows an example of the operation of a pixel.
- FIG. 2 is a diagram showing an example of a pixel.
- FIG. 2 is a diagram showing an example of a pixel.
- FIG. 7 is a diagram illustrating an example of a display device.
- FIG. 7 is a diagram illustrating an example of a display device.
- FIG. 18 illustrates an example of a transistor.
- FIG. 18 illustrates an example of a transistor.
- FIG. 18 illustrates an example of a transistor.
- FIG. 6 illustrates an example of an electronic device.
- membrane and the term “layer” can be replaced with each other depending on the case or situation.
- conductive layer can be changed to the term “conductive film”.
- insulating film can be changed to the term “insulating layer”.
- the metal oxide is a metal oxide in a broad sense.
- Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like.
- oxide semiconductors also referred to as oxide semiconductor or simply OS
- the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS transistor, the transistor can be put in another way as a transistor having a metal oxide or an oxide semiconductor.
- metal oxides having nitrogen may also be collectively referred to as metal oxides.
- a metal oxide having nitrogen may be referred to as metal oxynitride.
- Embodiment 1 In this embodiment, a display device of one embodiment of the present invention will be described with reference to the drawings.
- One embodiment of the present invention relates to a display device including an image data generation circuit, a source driver circuit, and a pixel.
- the source driver circuit is electrically connected to the pixel through the first wiring, and electrically connected to the pixel through the second wiring.
- the pixel includes a display device, and the potential of one electrode of the display device can be the potential of the first wiring, and the potential of the other electrode of the display device is the potential of the second wiring can do. That is, in the display device of one embodiment of the present invention, the difference between the potential of the first wiring and the potential of the second wiring can be a voltage applied to the display device.
- the first and second wirings can be signal lines
- the display device can be a liquid crystal device.
- the voltage applied to a display device indicates the potential difference between the potential supplied to one electrode of the display device and the potential supplied to the other electrode of the display device. .
- the image data generation circuit has a function of generating digital image data.
- the digital image data has first data and second data.
- first data for example, when digital image data is 9-bit data, the lower 8 bits can be used as the first data, and the most significant bit can be used as the second data.
- the display device of one embodiment of the present invention can operate in the first mode or the second mode.
- the source driver circuit sets the potential of the first wiring to a potential corresponding to the first data and sets the potential of the second wiring to a potential corresponding to the second data.
- the source driver circuit sets the potential of the first wiring to the potential corresponding to the second data and sets the potential of the second wiring to the potential corresponding to the first data. That is, the display device of one embodiment of the present invention supplies image data to a pixel through both the first wiring and the second wiring.
- frame inversion driving can be performed by switching between the first mode and the second mode.
- source line inversion drive, gate line inversion drive, dot inversion drive, or the like can be performed.
- the display device of one embodiment of the present invention for example, even when the potential supplied from the source driver circuit to the pixel is lower than in the case where image data is supplied to the pixel through only the first wiring, the voltage applied to the display device is It can be raised. Thus, even in the case where a high voltage is applied to the display device, power consumption of the display device of one embodiment of the present invention can be reduced. In addition, since the amplifier circuit included in the source driver circuit does not have to have high withstand voltage, the display device of one embodiment of the present invention can be miniaturized and inexpensive.
- FIG. 1A illustrates a configuration example of a display device 10 which is a display device of one embodiment of the present invention.
- the display device 10 includes a pixel array 14 in which pixels 11 are arranged in a matrix of m rows and n columns (m and n are integers of 2 or more), a gate driver circuit 12, a source driver circuit 13, and an image data generation circuit. 61 and an image processing circuit 62.
- the pixel 11 also has a display device 26.
- a liquid crystal device can be used as the display device 26.
- the gate driver circuit 12 is electrically connected to the pixel 11 through m wirings 33.
- the source driver circuit 13 is electrically connected to the pixel 11 through the n wirings 31 and the n wirings 32.
- the image data generation circuit 61 is electrically connected to the image processing circuit 62, and the image processing circuit 62 is electrically connected to the source driver circuit 13.
- the pixel 11 in the i-th row and the j-th column (i is an integer of 1 or more and m or less and j is an integer of 1 or more and n or less) is referred to as a pixel 11 [i, j].
- the wiring 33 electrically connected to the pixel 11 in the i-th row is referred to as a wiring 33 [i]
- the wiring 31 and the wiring 32 electrically connected to the pixel 11 in the j-th column are each The wiring 31 [j] and the wiring 32 [j] are described.
- the potential of one electrode of the display device 26 included in the pixel 11 in the j-th column can be the potential of the wiring 31 [j].
- the potential of the other electrode of the display device 26 included in the pixel 11 in the j-th column can be the potential of the wiring 32 [j]. That is, in the display device 10, the difference between the potential of the wiring 31 [j] and the potential of the wiring 32 [j] can be a voltage applied to the display device 26 included in the pixel 11 in the j-th column.
- the image data generation circuit 61 has a function of generating digital image data corresponding to the image displayed on the pixel array 14.
- FIG. 1B is a diagram for explaining digital image data input to the source driver circuit 13.
- digital image data has first data and second data.
- the lower 8 bits can be used as the first data
- the most significant bit can be used as the second data.
- the lower 8 bits can be used as the first data
- the upper 2 bits can be used as the second data. That is, the second data can be data including information on the most significant bit.
- the image processing circuit 62 has a function of performing image processing such as gamma correction, light control, color adjustment, noise removal, distortion correction, encoding, and decoding on digital image data input to the source driver circuit 13. .
- the gate driver circuit 12 has a function of generating a selection signal which is a signal for selecting the pixel 11 and supplying the selection signal to the pixel 11 through the wiring 33.
- the potential of the wiring 33 is a potential corresponding to the selection signal generated by the gate driver circuit 12. That is, the wiring 33 has a function as a scanning line.
- the source driver circuit 13 performs digital-to-analog conversion (hereinafter referred to as DA conversion) on the first data of the digital image data input to the source driver circuit 13 and It has a function to output to one side.
- the source driver circuit 13 has a function of outputting the potential corresponding to the second data of the digital image data input to the source driver circuit 13 to the other of the wiring 31 or the wiring 32.
- the source driver circuit 13 has a function of setting the potential of one of the wiring 31 or 32 to the potential corresponding to the first data and setting the other potential of the wiring 31 or 32 to the potential corresponding to the second data. It can be said that
- the wiring 31 and the wiring 32 have a function as signal lines.
- an operation mode in which the potential of the wiring 31 corresponds to the first data and the potential of the wiring 32 corresponds to the second data is referred to as a first mode.
- an operation mode in which the potential of the wiring 32 corresponds to the first data and the potential of the wiring 31 corresponds to the second data is referred to as a second mode. That is, by switching between the first mode and the second mode, the voltage applied to the display device 26 is inverted, and frame inversion driving or the like is performed. As a result, when the display device 26 is a liquid crystal device, deterioration of the display device 26 can be suppressed more than when frame inversion driving or the like is not performed, so the reliability of the display device 10 can be improved.
- FIG. 2A is a view showing a specific configuration example of the source driver circuit 13. 2A also shows the pixel 11 [i, j], the gate driver circuit 12, the image data generation circuit 61, and the image processing circuit 62 in addition to the source driver circuit 13.
- the source driver circuit 13 includes a shift register 41, a latch circuit 42, a level shift circuit 43, a DA conversion circuit 44, an amplifier circuit 46, a level shift circuit 63, an inverter circuit 64, a switch 48a, and a switch 48b. And a selection circuit 65.
- a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used as the switch 48a and the switch 48b.
- the output terminal of the image processing circuit 62 is electrically connected to the input terminal of the latch circuit 42 through the data bus line 51.
- the output terminal of the shift register 41 is electrically connected to the clock input terminal of the latch circuit 42.
- the output terminal of the latch circuit 42 is electrically connected to the input terminal of the level shift circuit 43.
- the output terminal of the level shift circuit 43 is electrically connected to the input terminal of the DA conversion circuit 44 and the input terminal of the level shift circuit 63.
- the output terminal of the DA converter circuit 44 is electrically connected to the input terminal of the amplifier circuit 46.
- the output terminal of the level shift circuit 63 is electrically connected to the input terminal of the inverter circuit 64.
- the first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46.
- the second input terminal of the selection circuit 65 is electrically connected to one terminal of the switch 48 a and one terminal of the switch 48 b.
- a connection point of the wiring to which the second input terminal of the selection circuit 65, one terminal of the switch 48a, and the other terminal of the switch 48b are connected is referred to as a node SN.
- the on / off of the switch 48 a can be controlled by a signal output from the inverter circuit 64.
- the on / off of the switch 48 b can be controlled by a signal output from the level shift circuit 63.
- Digital image data corresponding to an image displayed on the pixel array 14 is input to the input terminal of the latch circuit 42 from the data bus wiring 51.
- the latch circuit 42 has a function of holding the digital image data or outputting the held digital image data according to a signal supplied from the shift register 41.
- the level shift circuit 43 has a function of converting the amplitude voltage of the input digital image data to a larger value or a smaller value. Specifically, the level shift circuit 43 has a function of converting the amplitude voltage of the digital image data supplied from the latch circuit 42 into an amplitude voltage which the DA conversion circuit 44 properly operates.
- the DA conversion circuit 44 has a function of converting the first data into analog data based on the digital value of the first data of the digital image data.
- potentials that can be output from the DA conversion circuit 44 are referred to as a potential V M to a potential V H.
- the potential V M can be, for example, a potential higher than the ground potential
- the potential V H can be, for example, a potential higher than the potential V M.
- FIG. 2B is a diagram showing the relationship between the output potential and the digital value of the input first data in the DA conversion circuit 44.
- the output potential becomes higher as the digital value of the first data to be input is larger.
- the DA conversion circuit 44 when the digital value of the first data input to the DA conversion circuit 44 is 0 in decimal notation, the DA conversion circuit 44 generates the potential V M When the digital value is 255 in decimal notation, the DA conversion circuit 44 can output the potential V H.
- the DA conversion circuit 44 may lower the output potential as the digital value of the input first data is larger.
- the DA conversion circuit 44 when the digital value of the first data input to the DA conversion circuit 44 is 0 in decimal notation, the DA conversion circuit 44 outputs the potential V H outputs, when the digital value is 255 in decimal notation, DA converter 44 may output a voltage V M.
- the relationship between the output potential and the digital value of the first data to be input in the DA conversion circuit 44 is preferably linear, but may not be linear. . For example, a curve having no extreme value may be used.
- the amplifier circuit 46 has a function of amplifying analog data input to the input terminal and outputting the amplified data to an output terminal. By providing the amplifier circuit 46, the potential corresponding to the first data can be stably supplied to the pixel 11. As the amplifier circuit 46, a voltage follower circuit or the like having an operational amplifier or the like can be applied. Note that in the case of using a circuit having a differential input circuit as an amplifier circuit, it is preferable that the offset voltage of the differential input circuit be as close to 0 V as possible.
- the potential output from the amplifier circuit 46 when the potential V S1 it is possible that the potential V S1 is a potential corresponding to the first data. Further, the potential of the potential V S1 can be set to the potential V M to the potential V H.
- the level shift circuit 63 has a function of outputting a signal obtained by converting the amplitude voltage of the second data of the digital image data to a larger or smaller value. Specifically, the level shift circuit 63 has a function of converting the amplitude voltage of the second data included in the digital image data supplied from the level shift circuit 43 into an amplitude voltage at which the switch 48a and the switch 48b operate properly. Have. For example, assuming that the number of bits of the second data is one as shown in FIG. 1B, when the value of the second data is "1", the switch 48b is turned on and the switch 48a is turned off.
- the level shift circuit 63 has a function of converting the amplitude voltage of the second data so that the switch 48a is turned on and the switch 48b is turned off when the value of the second data is "0".
- the switch 48a is turned on and the switch 48b is turned off, and when the value of the second data is "0", the switch 48b is turned on and the switch 48a is turned off. It may be
- the inverter circuit 64 has a function of inverting the value of the signal output from the level shift circuit 63. That is, the inverter circuit 64 has a function of inverting the value of the second data. For example, the inverter circuit 64 outputs a signal having a value of "0" when the value of the second data is "1", and the value of "1" when the value of the second data is "0". It has a function of outputting a “signal”. As a result, when the switch 48 b is on, the switch 48 a can be turned off, and when the switch 48 b is off, the switch 48 a can be turned on.
- a potential V M can be applied to the other terminal of the switch 48a.
- the potential V L can be applied to the other terminal of the switch 48 b.
- the potential V L can be, for example, a potential lower than the potential V M.
- the potential V L can be a negative potential.
- the potential V L may be applied to the other terminal of the switch 48 a, and the potential V M may be applied to the other terminal of the switch 48 b.
- the potential V S1 may be set to the potential V L to the potential V M and the potential V H may be applied to the other terminal of the switch 48 a or the other terminal of the switch 48 b.
- the potential of the node SN can be set to a potential corresponding to the second data.
- the potential V S2 is a potential corresponding to the second data.
- the second data can be, for example, the potential V M or the potential V L.
- Selection circuit 65 includes a wiring for outputting an electric potential V S1, a function of selecting a wiring to output the potential V S2. Specifically, when the display device 10 operates in the first mode, the potential V S1 is output to the wiring 31 [j] and the potential V S2 is output to the wiring 32 [j]. On the other hand, when the display device 10 operates in the second mode, the potential VS1 is output to the wiring 32 [j] and the potential VS2 is output to the wiring 31 [j]. That is, it can be said that the selection circuit 65 has a function of performing frame inversion drive and the like.
- the mode switching signal MSS is supplied to the selection circuit 65.
- the mode switching signal MSS has a function of controlling the operation of the selection circuit 65.
- the mode switching signal MSS can be, for example, a 1-bit digital signal. For example, when the value of the mode switching signal MSS is “1”, the selection circuit 65 can output the potential V S1 to the wiring 31 [j] and can output the potential V S2 to the wiring 32 [j] . Also, for example, when the value of the mode switching signal MSS is “0”, the selection circuit 65 outputs the potential V S1 to the wiring 32 [j] and outputs the potential V S2 to the wiring 31 [j] Can.
- the display device 10 operates in the first mode by setting the value of the mode switching signal MSS to "1", and the display device 10 operates in the first mode by setting the value of the mode switching signal MSS to "0". Operates in mode 2. Note that, for example, the display device 10 operates in the first mode by setting the value of the mode switching signal MSS to "0", and the display device 10 operates in the first mode by setting the value of the mode switching signal MSS to "1". It is also possible to operate in the 2 mode.
- 3A1 and 3A2 are diagrams showing the relationship between the potential V S1 and the potential V S2 and the digital value of digital image data input to the source driver circuit 13.
- FIG. 1 it is assumed that the second data is the most significant bit of digital image data, as shown in FIG. 1 (B).
- the source driver circuit 13 has the configuration shown in FIG. 2A, and the potential V S2 is set to the potential V M when the value of the second data is “0”.
- the potential V S2 is set to the potential V L.
- the potential V S2 is set to the potential V M regardless of the value of the second data.
- the maximum value of the difference between the potential V S1 and the potential V S2 can be set to the potential “V H ⁇ V L ”.
- the maximum value of the difference between the potential V S1 and the potential V S2 is the potential “V H ⁇ V M ”. That is, when the range of potentials that can be output by the DA conversion circuit 44 in FIG. 3 (A1) and FIG. 3 (A2), that is, the possible range of the potential V S1 is equal, the case shown in FIG.
- the maximum value of the difference between the potential V S1 and the potential V S2 can be made larger than in the case shown in 3 (A2).
- the display device 10 can be miniaturized and can be inexpensive.
- FIG. 3B shows the relationship between the difference between the potential of the wiring 31 and the potential of the wiring 32 and the digital value of digital image data input to the source driver circuit 13 in the first mode and the second mode.
- the difference between the potential of the wiring 31 and the potential of the wiring 32 is the potential “V S1 ⁇ V S2 ” in the first mode, and the potential “ ⁇ (V S1 ⁇ ) in the second mode. V S2 ) ”. Therefore, by switching between the first mode and the second mode, the voltage applied to the display device 26 is inverted, and frame inversion driving can be performed.
- FIG. 2A the level shift circuit 63, the inverter circuit 64, the switch 48a, the switch 48b, and the selection circuit 65 are provided in the source driver circuit 13, but these are provided in the source driver circuit 13. It does not have to be done.
- FIG. 4 is a modification of the configuration shown in FIG. 2A, and the inverter circuit 64 and the selection circuit 65 are provided in the switch circuit 16 which is a circuit different from the source driver circuit 13.
- the switch circuit 16 is provided with a transistor 68a as the switch 48a and a transistor 68b as the switch 48b.
- the level shift circuit 63 is not provided in any of the source driver circuit 13 and the switch circuit 16. Further, the switch circuit 16 is provided with a potential generation circuit 70.
- CMOS transistor an n-channel transistor, or a p-channel transistor can be used as the transistor 68a and the transistor 68b.
- n-channel transistor an n-channel transistor is used as the transistor 68a and the transistor 68b is described below, the following description can be taken into consideration even when other transistors are used.
- the output terminal of the level shift circuit 43 is electrically connected to the input terminal of the inverter circuit 64 and the gate of the transistor 68 b in addition to the input terminal of the DA conversion circuit 44.
- the output terminal of the inverter circuit 64 is electrically connected to the gate of the transistor 68a.
- the first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46 as in the case shown in FIG.
- the second input terminal of the selection circuit 65 is electrically connected to one of the source or the drain of the transistor 68a and one of the source or the drain of the transistor 68b.
- a connection point of a wiring to which the second input terminal of the selection circuit 65, one of the source or the drain of the transistor 68a, and one of the source or the drain of the transistor 68b is connected is a node SN.
- a potential V M can be applied to the other of the source and the drain of the transistor 68 a.
- a potential V L can be applied to the other of the source and the drain of the transistor 68 b.
- the transistor 68 b is provided with a back gate in addition to the gate.
- the potential generation circuit 70 is electrically connected to the back gate.
- the potential generation circuit 70 has a function of generating a predetermined potential.
- the potential generated by the potential generation circuit 70 can be supplied to the back gate of the transistor 68 b.
- the threshold voltage of the transistor 68b can be controlled.
- the threshold voltage of the transistor 68b can be positively shifted by the potential generation circuit 70 generating a negative potential and supplying the potential to the back gate of the transistor 68b.
- gate may mean a front gate. Or it may mean both the front gate and the back gate.
- the potential of the gate of the transistor 68b needs to be equal to or lower than the potential V L to turn off the transistor 68b.
- the transistor 68 b may be turned off. become unable. Even in such a case, the transistor 68b can be turned off by the potential generation circuit 70 supplying a negative potential to the back gate of the transistor 68b to positively shift the threshold voltage of the transistor 68b.
- the transistor 68a may have a back gate.
- the switch circuit 16 may be configured to have the level shift circuit 63 shown in FIG. In this case, the transistor 68 b may not be provided with a back gate, and the potential generation circuit 70 may not be provided.
- an OS transistor As the transistor 68a and the transistor 68b, a transistor having a metal oxide in a channel formation region (hereinafter, an OS transistor) can be used.
- the OS transistor has a feature of high withstand voltage. Therefore, high potential can be applied to the source, the drain, and the gate of the transistor 68a and the transistor 68b.
- the use of an OS transistor as the transistor 68 b is preferable because the potential V L can be a smaller negative potential, that is, a potential with a larger absolute value.
- transistors 68a and 68b transistors (hereinafter, Si transistors) including silicon in a channel formation region can be used.
- Si transistor a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low temperature polysilicon), a transistor including single crystal silicon, and the like can be given.
- Si transistor has a large on-current, when switching of the potentials V S2, it is possible to determine quickly the potential of the node SN.
- the transistor 68a have a back gate and the potential generation circuit 70 be electrically connected to the back gate.
- FIG. 5A is a modification of the configuration shown in FIG. 4, and the point that the switch circuit 16 does not have the potential generation circuit 70 and the point that the switch circuit 16 has the transistor 71 and the capacitive element 72 is shown in FIG. Different from the configuration shown.
- each of the transistors 68a, 68b, and 71 does not have a back gate in FIG. 5A, some or all of the transistors may have a back gate.
- a potential generation circuit may be electrically connected to the back gate to control the potential of the back gate.
- the gate and the back gate may be electrically connected to make the potential of the back gate equal to the potential of the gate.
- CMOS transistor for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used similarly to the transistor 68a and the transistor 68b.
- n-channel transistor for example, an n-channel transistor is used as the transistor 71 is described below, the following description can be referred to even when other transistors are used.
- An output terminal of the level shift circuit 43 is electrically connected to one of the electrodes of the capacitive element 72 in addition to the input terminal of the DA conversion circuit 44 and the input terminal of the inverter circuit 64.
- the gate of the transistor 68 b is electrically connected to one of the source and the drain of the transistor 71 and the other electrode of the capacitor 72.
- the gate of the transistor 71 is electrically connected to the gate driver circuit 12 through the wiring 81.
- a wiring to which an input terminal of the DA conversion circuit 44, an input terminal of the inverter circuit 64, and one electrode of the capacitor 72 are connected is referred to as a node FN1.
- a wiring to which the gate of the transistor 68 b, one of the source and the drain of the transistor 71, and the other electrode of the capacitor 72 are connected is referred to as a node FN2. Further, a connection point of the wiring to which the output terminal of the inverter circuit 64 and the gate of the transistor 68a are connected is referred to as a node FN3.
- the potential VSS can be applied to the other of the source and the drain of the transistor 71.
- the potential VSS can be equal to or lower than the potential V L.
- the gate driver circuit 12 has a function of controlling conduction / non-conduction of the transistor 71 by controlling the potential of the wiring 81.
- FIG. 5B is a timing chart showing an example of an operation method of the switch circuit 16 configured as shown in FIG.
- the potential VDD can be a potential higher than the potential V H and the potential “VSS + VDD” is higher than the potential V L.
- the source driver circuit 13 can output a potential higher than the potential GND which is the ground potential.
- the second data included in the digital image data is 1-bit data, and the source driver circuit 13 supplies the potential GND or the potential VDD to the switch circuit 16 according to the value of the second data.
- the threshold voltages of the transistors 68a and 68b are 0 V, and the potential V M is higher than the ground potential.
- the potential supplied to the gate of the transistor 68a is the potential VDD when the potential of the node FN1 is the potential GND, and is the potential GND when the potential of the node FN1 is the potential VDD.
- the potential of the node FN1 and the potential of the node FN2 are reset.
- the source driver circuit 13 outputs the potential GND to the switch circuit 16 and writes the potential GND to the node FN1.
- the potential of the wiring 81 is set to the potential VDD at time T01
- the transistor 71 is turned on, and the potential VSS is written to the node FN2. Further, the potential of the node FN3 becomes the potential VDD.
- the operations from time T1 to time T02 can be performed, for example, in the retrace period of the operation of the display device 10.
- Times T02 to T03 show the case where the source driver circuit 13 supplies the potential VDD to the switch circuit 16 as the potential corresponding to the second data.
- the potential of the wiring 81 is set to the potential VSS at time T02 and then the potential VDD is supplied from the source driver circuit 13 to the switch circuit 16, the potential of the node FN1 becomes the potential VDD.
- the capacitive coupling coefficient of the node FN2 is 1, the potential of the node FN2 becomes the potential “VSS + VDD”, which is higher than the potential VL .
- the potential of the node FN3 becomes the potential GND.
- the threshold voltages of the transistors 68a and 68b are 0 V, the transistor 68a becomes nonconductive and the transistor 68b becomes conductive.
- the value of the potential V S2 becomes the potential V L.
- the source driver circuit 13 supplies the potential GND to the switch circuit 16 as the potential corresponding to the second data.
- the potential of the wiring 81 is set to the potential VSS at time T03 and the potential GND is supplied from the source driver circuit 13 to the switch circuit 16 after that, the potential of the node FN1 becomes the potential GND.
- the capacitive coupling coefficient of the node FN2 is 1, the potential of the node FN2 becomes the potential VSS and becomes lower than or equal to the potential VL .
- the potential of the node FN3 is set to the potential VDD.
- the threshold voltages of the transistors 68a and 68b are 0 V, the transistor 68a becomes conductive and the transistor 68b becomes nonconductive.
- the value of the potential V S2 becomes the potential V M.
- the transistor 71 is preferably a transistor with extremely low off-state current.
- the potential of the node FN2 can be held for a long time.
- a transistor with extremely low off current for example, an OS transistor can be mentioned.
- a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
- an oxide semiconductor or the like containing indium can be used, and for example, a CAAC (C-Axis Aligned Crystalline) -OS, or a CAC (Cloud-Aligned Composite) -OS or the like described later can be used.
- the CAAC-OS is a crystalline oxide semiconductor.
- a transistor including the crystalline oxide semiconductor can improve reliability, it is preferably used for the display device of one embodiment of the present invention.
- CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like which performs high-speed driving.
- An OS transistor exhibits extremely low off-current characteristics because of its large energy gap.
- the OS transistor has characteristics different from the Si transistor, such as no impact ionization, avalanche breakdown, short channel effect, and the like, and can form a highly reliable circuit.
- the OS transistor has the feature of high withstand voltage. Therefore, by using an OS transistor for the transistor 71, a high voltage can be applied to the source, the drain, and the gate of the transistor 71.
- the potential VSS can be set to a smaller negative potential, that is, a potential having a larger absolute value.
- a Si transistor may be used as the transistor 71. As described above, since the Si transistor has a large on-state current, the potential of the node FN2 can be reset in a short time.
- Configuration Example 4 of Display Device> 2A and the like show a configuration example of the source driver circuit 13 etc. in the case where the number of bits of the second data contained in the digital image data input to the source driver circuit 13 is 1 bit.
- the number of bits of the second data may be two or more.
- FIG. 6 shows a configuration example of the source driver circuit 13 in the case where the number of bits of the second data is 2 bits, which is a modified example of FIG. 2 (A).
- the source driver circuit 13 includes, in addition to the shift register 41, the latch circuit 42, the level shift circuit 43, the DA conversion circuit 44, the amplifier circuit 46, and the selection circuit 65, the switch 49a, the switch 49b, the switch 49c, the switch 49d, and the level A shift circuit 63a, a level shift circuit 63b, a level shift circuit 63c, and a level shift circuit 63d are provided.
- a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used as the switches 49a to 49d.
- the switches 49a to 49d, the level shift circuits 63a to 63d, and the selection circuit 65 may be provided in a circuit different from the source driver circuit 13.
- the output terminal of the level shift circuit 43 is electrically connected to the input terminals of the level shift circuits 63a to 63d in addition to the input terminal of the DA converter circuit 44.
- the first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46 as in the case shown in FIG.
- the second input terminal of the selection circuit 65 is electrically connected to one terminal of the switch 49a, one terminal of the switch 49b, one terminal of the switch 49c, and one terminal of the switch 49d.
- a connection point of a wire connected to the second input terminal of the selection circuit 65, one terminal of the switch 49a, one terminal of the switch 49b, one terminal of the switch 49c, and one terminal of the switch 49d As a node SN.
- the on / off of the switch 49a can be controlled by the signal output from the level shift circuit 63a.
- the on / off of the switch 49b can be controlled by the signal output from the level shift circuit 63b.
- the on / off of the switch 49c can be controlled by the signal output from the level shift circuit 63c.
- the on / off of the switch 49d can be controlled by the signal output from the level shift circuit 63d.
- the level shift circuits 63a to 63d have a function of outputting a signal obtained by converting the amplitude voltage of the second data to a larger value or a smaller value.
- the level shift circuit 63a to the level shift circuit 63d are an amplitude voltage at which the switches 49a to 49d appropriately operate, with the amplitude voltage of the second data included in the digital image data supplied from the level shift circuit 43.
- the level shift circuit 63a to the level shift circuit convert the amplitude voltage of the second data so that only the switch 49c is turned on in the case of 10 ′ ′ and only the switch 49d is turned on in the case of “11” 63 d has.
- a potential V M can be applied to the other terminal of the switch 49a.
- the potential V ML can be applied to the other terminal of the switch 49 b.
- the potential V LM can be applied to the other terminal of the switch 49 c.
- the potential V L can be applied to the other terminal of the switch 49 d.
- the potential V S2 can be the potential V M , the potential V ML , the potential V LM , or the potential V L. Note that the potential V M , the potential V ML , the potential V LM , and the potential V L can be used in order from the highest potential.
- the difference between the potential VM and the potential V ML , the difference between the potential V ML and the potential V LM , and the difference between the potential V LM and the potential V L be equal to the difference between the potential V H and the potential V M.
- FIGS. 7A1 and 7A2 are diagrams showing the relationship between the potential V S1 and the potential V S2 and the digital value of digital image data input to the source driver circuit 13.
- FIG. 7 (A1) it is assumed that the source driver circuit 13 has the configuration shown in FIG. 6 and the potential V S2 is set to the potential V M when the value of the second data is “00” in binary notation. "If it is the potential V S2 and the potential V ML,” “the case where the potential V S2 and the potential V LM,” 10 11 If it is "in the potential V L potential V S2.
- the potential V S2 is set to the potential V M regardless of the value of the second data.
- the difference between the potential V H which is the maximum value of the potential that the potential V S1 can take, and the potential V M , which is the minimum value.
- the potential "V H -V L " which is the maximum value of the difference between the potential V S1 and the potential V S2 can be increased.
- the voltage applied to the display device 26 can be increased. Therefore, even when a high voltage is applied to the display device 26, the power consumption of the display device 10 can be reduced.
- the amplifier circuit 46 does not have to have a high withstand voltage, the display device 10 can be miniaturized and can be inexpensive.
- FIG. 7B shows the relationship between the difference between the potential of the wiring 31 and the potential of the wiring 32 and the digital value of digital image data input to the source driver circuit 13 in the first mode and the second mode.
- FIG. Similar to the case shown in FIG. 3B, the difference between the potential of the wiring 31 and the potential of the wiring 32 is the potential “V S1 ⁇ V S2 ” in the first mode, and the potential “ ⁇ (V) in the second mode. S1- V S2 ) ". Therefore, by switching between the first mode and the second mode, the voltage applied to the display device 26 is inverted, and frame inversion driving can be performed.
- FIG. 8 is a diagram for explaining a pixel 11 a that can be used as the pixel 11.
- the pixel 11 a includes a transistor 21, a transistor 22, a capacitor 25, and a display device 26.
- the transistor 21 and the transistor 22 for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used.
- the case where an n-channel transistor is used as the transistor 21 and the transistor 22 is described below, the following description can be taken into consideration even when other transistors are used.
- One of the source and the drain of the transistor 21 is electrically connected to one electrode of the capacitor 25.
- One electrode of the capacitive element 25 is electrically connected to one electrode of the display device 26.
- One of the source or the drain of the transistor 22 is electrically connected to the other electrode of the capacitor 25.
- the other electrode of the capacitive element 25 is electrically connected to the other electrode of the display device 26.
- a wiring to which one of the source and the drain of the transistor 21, one of the electrodes of the capacitor 25, and one of the electrodes of the display device 26 are connected is referred to as a node N1.
- a connection point of a wiring to which one of the source and the drain of the transistor 22, the other electrode of the capacitor 25, and the other electrode of the display device 26 is connected is referred to as a node N2.
- the other of the source and the drain of the transistor 21 is electrically connected to the wiring 31.
- the other of the source and the drain of the transistor 22 is electrically connected to the wiring 32.
- the gate of the transistor 21 and the gate of the transistor 22 are electrically connected to the wiring 33.
- the transistor 21 has a function of controlling supply of the potential of the wiring 31 to the pixel 11 a.
- the transistor 22 has a function of controlling supply of the potential of the wiring 32 to the pixel 11 a.
- the potential of the wiring 31 is held at the node N1.
- the potential of the wiring 32 is held at the node N2. Therefore, by using transistors with extremely low off-state current for the transistors 21 and 22, the potentials of the nodes N1 and N2 can be held for a long time.
- an OS transistor can be used for the transistor.
- a Si transistor may be applied to the transistor 21 and the transistor 22.
- an OS transistor may be applied to one of the transistor 21 and the transistor 22, and a Si transistor may be applied to the other.
- time T11 to time T13 and time T14 to time T16 can each be one frame period.
- the transistor 21 and the transistor 22 are made conductive by setting the potential of the wiring 33 to the potential VDD
- the potential of the wiring 33 is necessarily set to the potential VDD if the transistor 21 and the transistor 22 can be made conductive. It does not have to be.
- the transistor 21 and the transistor 22 are turned off by setting the potential of the wiring 33 to the potential VSS.
- the potential of the wiring 33 is not limited to the potential. It does not have to be VSS.
- the transistors 21 and 22 are turned on. Then, the potential V S1 the potential of the wiring 31 at time T12, when the potential of the wiring 32 to a potential V S2, the potential V S1 is written to the node N1, the potential V S2 is written into the node N2. Thereby, display by the display device 26 is performed according to the potential VS1 and the potential VS2 . Note that in FIG. 9, the potential V S2 is assumed to be the potential V M.
- the transistors 21 and 22 are turned on. Thereafter, when the potential of the wiring 31 is set to the potential V S2 and the potential of the wiring 32 is set to the potential V S1 at time T15, the voltage applied to the display device 26 is inverted. Thus, frame inversion driving is performed.
- the display device 10 is operating in the second mode.
- the above is an example of the operation method of the pixel 11a.
- FIG. 10 is a diagram for explaining a pixel 11 b that can be used as the pixel 11.
- the pixel 11 b is a modification of the pixel 11 a and differs from the pixel 11 a in that the transistor 23 is provided.
- the transistor 23 for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used.
- the transistor 23 will be described below, the following description can be referred to even when another transistor is used.
- One of the source and the drain of the transistor 23 is electrically connected to the node N2.
- the other of the source and the drain of the transistor 23 is electrically connected to the wiring 35.
- the gate of the transistor 23 is electrically connected to the wiring 34.
- the wiring 35 has a function as a common wiring. That is, the other of the sources or the drains of the transistors 23 provided in the display device 10, for example, in all the pixels 11b can be electrically connected to each other through the single wiring 35. A constant potential is supplied to the wiring 35, and for example, a ground potential or a potential V M can be supplied. Further, the wiring 34 has a function as a scan line which controls the transistor 23.
- the potential of the wiring 32 is held at the node N2. Therefore, as the transistor 23, a transistor with very low off current, such as an OS transistor, can be used similarly to the transistor 22. Note that a Si transistor may be used as the transistor 23.
- the potential supplied to the wiring 35 is referred to as a potential V M.
- time T21 to time T25 and time T26 to time T30 can be set as one frame period.
- the transistor 23 is turned on by setting the potential of the wiring 34 to the potential VDD, the potential of the wiring 34 may not necessarily be set to the potential VDD as long as the transistor 23 can be turned on.
- the transistor 23 is turned off by setting the potential of the wiring 34 to the potential VSS, the potential of the wiring 34 may not necessarily be set to the potential VSS if the transistor 23 can be turned off. .
- the potential of the wiring 34 is a potential VSS at time T21
- the potential of the wiring 33 is a potential VDD at time T22
- the potential of the wiring 31 is a potential V S1
- the potential of the wiring 32 is a potential V S2 at time T23. 22 is rendered conductive
- the potential V S1 is written to the node N1
- the potential V S2 is written into the node N2.
- display by the display device 26 is performed according to the potential V S1 and the potential V S2 .
- the potential V S2 is assumed to be the potential V L.
- the display device 10 operates in the first mode from time T23 to time T24.
- the transistor 23 When the potential of the wiring 34 to the time T25 to a potential VDD, the transistor 23 becomes conductive, the potential of the node N2 becomes the potential V M. That is, the potential of the node N2 rises by "V M- V S2 ". Thus, if the capacitive coupling coefficient of the node N1 is 1, the potential of the node N1 also "V M -V S2" rises, a potential “V S1 + V M -V S2 ". From the above, the voltage applied to the display device 26 does not change. Here, the potential “V S1 + V M ⁇ V S2 ” may be higher than the potential V H. Also in the following description, the capacitive coupling coefficient of the node N1 is 1.
- the potential of the wiring 34 is set to the potential VSS at time T26, the potential of the wiring 33 is set to the potential VDD at time T27, the potential of the wiring 31 is set to the potential V S2 , and the potential of the wiring 32 is set to the potential V S1 at time T28.
- the transistors 21 and 22 become conductive, and the voltage applied to the display device 26 is inverted.
- frame inversion driving is performed.
- the display device 10 is operating in the second mode from time T28 to time T29.
- the transistor 23 becomes conductive, the potential of the node N2 becomes the potential V M. That is, the potential of the node N2 is increased by “V M ⁇ V S1 ”, that is, decreased by “V S1 ⁇ V M ”. As a result, the potential of the node N1 also rises "V M- V S1 ", that is, drops “V S1- V M ", and becomes the potential "V S2 + V M- V S1 ". From the above, the voltage applied to the display device 26 does not change.
- the potential “V S2 + V M ⁇ V S1 ” may be lower than the potential V L.
- the above is an example of the operation method of the pixel 11b.
- one of the potential V S1 or potential V S2 to the node N1 after writing the other potential V S1 or potential V S2 to the node N2, by the potential of the node N2 and the voltage V M the voltage applied to the display device 26, without changing before and after the potential of the node N2 and the potential V M, the potential of the node N2 can be set to a potential V M.
- fluctuations in voltage applied to the display device 26 due to electrical noise or the like generated from the wirings 31 to 34 can be suppressed. Therefore, the display quality of the image displayed on the display device 10 can be improved.
- FIG. 12A is a diagram for explaining a pixel 11c which can be used as the pixel 11
- FIG. 12B is a diagram for explaining a pixel 11d which can be used as the pixel 11.
- the pixel 11 c has a configuration in which a back gate is provided to the transistor 21 and the transistor 22 provided in the pixel 11 a.
- the pixel 11 d has a configuration in which a back gate is provided to the transistors 21 to 23 provided in the pixel 11 b.
- the back gate can be electrically connected to the front gate of the transistor provided with the back gate, and has an effect of increasing the on current. Further, the back gate may be supplied with a potential different from that of the front gate. With this structure, the threshold voltage of the transistor can be controlled.
- FIGS. 12A and 12B illustrate a structure in which back gates are provided in all the transistors; however, a transistor in which a back gate is not provided may be included.
- FIG. 13A is a diagram for explaining a pixel 11 e that can be used as the pixel 11.
- the pixel 11 e is configured such that the other electrode of the display device 26 provided in the pixel 11 b is not connected to the node N2.
- the other electrode of the display device 26 can be electrically connected to the wiring 36 having a function as a common wiring.
- a constant potential is supplied to the wiring 36.
- the same potential as the potential supplied to the wiring 35 can be supplied to the wiring 36.
- the wiring 36 can be supplied with, for example, the ground potential or the potential V M.
- the pixel 11 e can be operated by the same method as the method shown in FIG.
- FIG. 13B is a diagram for explaining a pixel 11 f that can be used as the pixel 11.
- the pixel 11 f has a configuration in which a back gate is provided to the transistors 21 to 23 provided in the pixel 11 e.
- FIG. 13B illustrates a structure in which back gates are provided for all the transistors, a transistor in which a back gate is not provided may be included.
- FIG. 14 is a cross-sectional view showing a configuration example of the display device 10, and shows a case where the display device 10 is a transmissive liquid crystal display device to which a transverse electric field system is applied.
- FIG. 14 shows a configuration example of the pixel array 14 and the circuit 15.
- the circuit 15 can be a gate driver circuit 12 or a source driver circuit 13 or the like.
- the display device 10 is configured to bond the substrate 111 and the substrate 113 together.
- the transistor 21, the capacitor 25, the display device 26, and the like are provided over the substrate 111.
- the transistor 24 and the like are provided over the substrate 111.
- a coloring layer 131, a light shielding layer 132, and the like are provided on the substrate 113.
- the transistor 21 includes a conductive layer 221 functioning as a gate electrode, an insulating layer 211 functioning as a gate insulating layer, a semiconductor layer 231, and conductive layers 222a and 222b functioning as a source electrode and a drain electrode.
- the capacitor 25 includes the conductive layer 224 and the conductive layer 222 a functioning as an electrode, and the insulating layer 211 functioning as a dielectric layer.
- the transistor 21, the transistor 24, and the capacitor 25 are covered with the insulating layer 212 and the insulating layer 217.
- an insulating layer 215 which functions as an interlayer insulating layer is provided between the transistor 21, the transistor 24 and the capacitor 25 and the display device 26.
- the semiconductor layer 231 can have a metal oxide.
- the transistor 21 is an OS transistor.
- the other transistors provided on the substrate 111 such as the transistor 24 can have the same configuration as the transistor 21.
- the display device 26 is a liquid crystal device to which a horizontal electric field mode, specifically, an FFS (Fringe Field Switching) mode is applied.
- the display device 26 includes an electrode 181, an electrode 182, and a liquid crystal layer 183. By the electric field generated between the electrode 181 and the electrode 182, the alignment of the liquid crystal layer 183 can be controlled.
- the liquid crystal layer 183 is located on the insulating layer 220 and the electrode 182.
- the electrode 181 is electrically connected to the conductive layer 222 a through an opening provided in the insulating layer 215, the insulating layer 217, and the insulating layer 212.
- the electrode 182 is electrically connected to the conductive layer 224 through an opening provided in the insulating layer 215, the insulating layer 217, the insulating layer 212, and the insulating layer 211.
- the electrode 182 may have a comb-like upper surface shape (also referred to as a planar shape) or an upper surface shape provided with a slit.
- the electrode 182 can be provided with one or more openings.
- An insulating layer 220 is provided between the electrode 181 and the electrode 182.
- the electrode 181 has a portion overlapping with the electrode 182 with the insulating layer 220 interposed therebetween.
- a portion where the electrode 182 is not provided over the electrode 181 is provided.
- Light from the backlight unit 552 is emitted to the outside of the display device through the substrate 111, the electrode 181, the electrode 182, the liquid crystal layer 183, the colored layer 131, and the substrate 113.
- the material of these layers through which the light of the backlight unit 552 passes is a material that transmits visible light.
- the display device 10 is colored even without forming the colored layer 131. It can be displayed. When light of all colors is simultaneously supplied, white display can be performed.
- An overcoat 121 is preferably provided between the colored layer 131 and the light shielding layer 132 and the liquid crystal layer 183.
- the overcoat 121 can suppress diffusion of impurities contained in the colored layer 131, the light shielding layer 132, and the like into the liquid crystal layer 183.
- the substrate 111 and the substrate 113 are attached to each other by an adhesive layer 141.
- a liquid crystal layer 183 is sealed in a region surrounded by the substrate 111, the substrate 113, and the adhesive layer 141.
- the polarizing plate 125 a and the polarizing plate 125 b are disposed so as to sandwich the pixel array 14 of the display device, the circuit 15, and the like.
- the light from the backlight unit 552 disposed outside the polarizing plate 125a is incident on the display device 10 through the polarizing plate 125a.
- alignment of the liquid crystal layer 183 can be controlled by a voltage applied between the electrode 181 and the electrode 182, and optical modulation of light can be controlled. That is, the intensity of light emitted from the display device 10 through the polarizing plate 125 b can be controlled.
- the light incident on the display device 26 is light having a color other than a specific wavelength range absorbed by the colored layer 131, so the light emitted from the display device 10 is light exhibiting, for example, red, blue or green.
- the polarizing plate 125 a and the polarizing plate 125 b may not be provided.
- the conductive layer 565 is electrically connected to the FPC 162 through the conductive layer 255 and the connector 242.
- an electrode 181 which is one electrode of the display device 26 and an electrode which is the other electrode of the display device 26 are formed on one surface of the liquid crystal layer 183.
- And 182 can be formed.
- both the electrode 181 and the electrode 182 can be electrically connected to the electrode of the capacitor 25.
- liquid crystal exhibiting a blue phase can be used as a liquid crystal used for a liquid crystal device.
- the blue phase is one of the liquid crystal phases, and is a phase which appears immediately before the cholesteric liquid phase is changed to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with several weight% or more of a chiral agent is used for liquid crystal in order to improve the temperature range.
- a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed and is optically isotropic.
- a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent does not require alignment treatment and has a small viewing angle dependency.
- rubbing processing is also unnecessary, so electrostatic breakdown caused by rubbing processing can be prevented, and defects and breakage of the liquid crystal display device in the manufacturing process can be reduced. .
- liquid crystals other than the blue phase may be used.
- thermotropic liquid crystals low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, etc.
- These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on conditions.
- liquid crystal material either positive liquid crystal or negative liquid crystal may be used.
- liquid crystals other than a blue phase as liquid crystal used for a liquid crystal device, in order to control alignment of a liquid crystal, it is preferable to provide an alignment film.
- FIG. 15 is a cross-sectional view showing a configuration example of the display device 10, and shows a case where the display device 10 is a transmissive liquid crystal display device to which the vertical electric field method is applied.
- the electrode 182 included in the display device 26 may not be electrically connected to the electrode included in the capacitor 25. Therefore, the electrodes 181 and the electrodes 182 included in the display device 26 can be provided at positions facing each other with the liquid crystal layer 183 interposed therebetween. Therefore, the display device 10 is a transmissive liquid crystal display device to which the vertical electric field method is applied. can do.
- the display device 10 is a transmissive liquid crystal display device to which a vertical electric field mode is applied, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, a MVA (Multidomain Vertical Alignment) mode, a PVA
- a liquid crystal device to which a patterned vertical alignment (OC) mode, an optically compensated bend (OCB) mode, or the like is applied can be used.
- a backlight unit may be used as the backlight unit 552, which sequentially supplies light of each color by the field sequential method.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- the display device of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom gate transistor and a top gate transistor. Therefore, according to the existing manufacturing line, the material of the semiconductor layer to be used and the transistor structure can be easily replaced.
- FIG. 16A1 is a cross-sectional view in the channel length direction of a channel protective transistor 810 which is a kind of bottom gate transistor.
- the transistor 810 is formed over a substrate 771.
- the transistor 810 includes an electrode 746 over the substrate 771 with the insulating layer 772 interposed therebetween.
- the semiconductor layer 742 is provided over the electrode 746 with the insulating layer 726 interposed therebetween.
- the electrode 746 can function as a gate electrode.
- the insulating layer 726 can function as a gate insulating layer.
- the insulating layer 741 is provided over the channel formation region of the semiconductor layer 742.
- an electrode 744 a and an electrode 744 b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742.
- the electrode 744a can function as one of a source electrode and a drain electrode.
- the electrode 744 b can function as the other of the source electrode and the drain electrode.
- a portion of the electrode 744 a and a portion of the electrode 744 b are formed over the insulating layer 741.
- the insulating layer 741 can function as a channel protective layer. By providing the insulating layer 741 over the channel formation region, exposure of the semiconductor layer 742 which is generated at the time of formation of the electrode 744a and the electrode 744b can be prevented. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrode 744a and the electrode 744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
- the transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and the insulating layer 729 over the insulating layer 728.
- a part of the semiconductor layer 742 can be deprived of oxygen and oxygen deficiency can be generated in at least a portion of the electrode 744 a and the electrode 744 b in contact with the semiconductor layer 742.
- the region of the semiconductor layer 742 in which oxygen vacancies occur has an increased carrier concentration, and the region becomes n-type to become an n-type region (n + layer). Thus, the region can function as a source region or a drain region.
- tungsten, titanium, or the like can be given as an example of a material that can deprive the semiconductor layer 742 of oxygen and cause oxygen vacancies.
- the contact resistance between the electrode 744 a and the electrode 744 b and the semiconductor layer 742 can be reduced. Accordingly, electrical characteristics of the transistor, such as field effect mobility and threshold voltage, can be improved.
- a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744 a and between the semiconductor layer 742 and the electrode 744 b.
- a layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
- the insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 729 can be omitted as needed.
- the transistor 811 illustrated in FIG. 16A2 is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
- the electrode 723 can be formed by the same material and method as the electrode 746.
- the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode are disposed so as to sandwich the channel formation region of the semiconductor layer.
- the back gate electrode can function similarly to the gate electrode.
- the potential of the back gate electrode may be the same as that of the gate electrode, or may be the ground potential (GND potential) or any potential.
- the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently without interlocking with the gate electrode.
- the electrode 746 and the electrode 723 can both function as a gate electrode.
- the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer.
- the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.
- the other is referred to as a “back gate electrode”.
- the electrode 746 when the electrode 723 is referred to as a “gate electrode”, the electrode 746 is referred to as a “back gate electrode”.
- the transistor 811 can be considered as a kind of top gate transistor.
- one of the electrode 746 and the electrode 723 may be referred to as “first gate electrode”, and the other may be referred to as “second gate electrode”.
- the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction.
- the amount of carrier movement increases.
- the on current of the transistor 811 is increased, and the field effect mobility is increased.
- the transistor 811 is a transistor having a large on current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the on current required. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Thus, according to one embodiment of the present invention, a display device with a high degree of integration can be realized.
- the gate electrode and the back gate electrode are formed of a conductive layer, they have a function to prevent an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (in particular, an electric field shielding function against static electricity or the like). . Note that by providing the back gate electrode so as to have a region overlapping with the semiconductor layer, the electric field shielding function can be enhanced.
- the back gate electrode is formed using a light-shielding conductive film
- light can be prevented from entering the semiconductor layer from the back gate electrode side. Accordingly, light deterioration of the semiconductor layer can be prevented, and deterioration of the electrical characteristics such as a shift in threshold voltage of the transistor can be prevented.
- a highly reliable transistor can be realized.
- a highly reliable semiconductor device can be realized.
- 16B1 is a cross-sectional view in the channel length direction of a channel protective transistor 820 having a different structure from that in FIG. 16A1.
- the transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 741 covers an end portion of the semiconductor layer 742.
- the semiconductor layer 742 and the electrode 744 a are electrically connected in the opening formed by removing part of the insulating layer 741 which has a region overlapping with the semiconductor layer 742.
- the semiconductor layer 742 and the electrode 744 b are electrically connected to each other in another opening which is formed by removing part of the insulating layer 741 overlapping with the semiconductor layer 742.
- the region of the insulating layer 741 overlapping with the channel formation region can function as a channel protective layer.
- the transistor 821 illustrated in FIG. 16B2 is different from the transistor 820 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
- the insulating layer 741 can prevent the semiconductor layer 742 from being exposed at the time of formation of the electrodes 744a and 744b. Thus, thinning of the semiconductor layer 742 can be prevented at the time of formation of the electrode 744a and the electrode 744b.
- the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer than those in the transistors 810 and 811.
- parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced.
- parasitic capacitance generated between the electrode 744 b and the electrode 746 can be reduced.
- a transistor with favorable electrical characteristics can be realized.
- a transistor 825 illustrated in FIG. 16C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 825 which is one of bottom-gate transistors.
- the transistor 825 forms the electrode 744a and the electrode 744b without providing the insulating layer 741. Therefore, part of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be improved.
- a transistor 826 illustrated in FIG. 16C2 is different from the transistor 825 in that the electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
- 17A1 to 17C2 are cross-sectional views in the channel width direction of the transistor 810, the transistor 811, the transistor 820, the transistor 821, the transistor 825, and the transistor 826, respectively.
- the gate electrode and the back gate electrode are connected, and the potentials of the gate electrode and the back gate electrode become the same.
- the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.
- the length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 742, and the entire channel width direction of the semiconductor layer 742 is the insulating layer 726, the insulating layer 741, the insulating layer 728 and the insulating layer 729 are interposed between the gate electrode and the back gate electrode.
- the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.
- a device structure of a transistor that electrically surrounds a semiconductor layer 742 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode It can be called structure.
- an electric field for inducing a channel can be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved. It is possible to obtain high on-current characteristics. In addition, since the on current can be increased, the transistor can be miniaturized. In addition, with the S-channel structure, mechanical strength of the transistor can be increased.
- a transistor 842 illustrated in FIG. 18A1 is one of top-gate transistors.
- the transistor 842 forms the electrode 744a and the electrode 744b after forming the insulating layer 729.
- the electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in an opening formed in the insulating layer 728 and the insulating layer 729.
- a portion of the insulating layer 726 which does not overlap with the electrode 746 is removed, and an impurity is introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask.
- the impurity region can be formed in a self alignment manner (self alignment).
- the transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746.
- the impurity concentration of the region into which the impurity is introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than that of the region into which the impurity is introduced without through the insulating layer 726.
- a lightly doped drain (LDD) region is formed in a region which does not overlap with the electrode 746.
- a transistor 843 illustrated in FIG. 18A2 is different from the transistor 842 in that the electrode 723 is provided.
- the transistor 843 has an electrode 723 formed over the substrate 771.
- the electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween.
- the electrode 723 can function as a back gate electrode.
- the insulating layer 726 in a region which does not overlap with the electrode 746 may be removed.
- the insulating layer 726 may be left.
- transistors 842 to 847 after forming the electrode 746, an impurity is introduced into the semiconductor layer 742 using the electrode 746 as a mask, so that the impurity region can be formed in the semiconductor layer 742 in a self-aligned manner.
- a transistor with favorable electrical characteristics can be realized.
- a semiconductor device with a high degree of integration can be realized.
- 19A1 to 19C2 are cross-sectional views in the channel width direction of the transistors 842 to 847, respectively.
- the transistor 843, the transistor 845, and the transistor 847 each have the S-channel structure described above. However, without limitation thereto, the transistor 843, the transistor 845, and the transistor 847 may not have an S-channel structure.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- the semiconductor layer included in the OS transistor is, for example, an In-M-Zn-based oxide containing indium, zinc and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium).
- the film can be represented by
- the oxide semiconductor forming the semiconductor layer is an In-M-Zn-based oxide
- the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is In ⁇ M, Zn It is preferable to satisfy ⁇ M.
- the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.
- an oxide semiconductor with low carrier density is used.
- the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, more preferably 1 ⁇ 10 11 / cm 3 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use an oxide semiconductor of 1 ⁇ 10 -9 / cm 3 or more carrier density.
- Such an oxide semiconductor is referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor.
- the oxide semiconductor has low defect state density and can be said to be an oxide semiconductor having stable characteristics.
- composition is not limited to those described above, and a composition having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of the required transistor.
- semiconductor characteristics and electrical characteristics field effect mobility, threshold voltage, and the like
- the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
- the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less make it
- the nitrogen concentration (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
- the semiconductor layer may have, for example, a non-single crystal structure.
- the non-single crystal structure includes, for example, a CAAC-OS having a crystal oriented in the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
- the amorphous structure has the highest density of defect states
- CAAC-OS has the lowest density of defect states.
- the oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component.
- the oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.
- the semiconductor layer may be a mixed film having two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure.
- the mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.
- CAC-OS which is one embodiment of a non-single-crystal semiconductor layer is described below.
- the CAC-OS is, for example, a configuration of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof.
- an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof.
- the oxide semiconductor one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less
- the state in which they are mixed is also called a mosaic or patch.
- the oxide semiconductor preferably contains at least indium.
- One or more selected from may be included.
- CAC-OS in the In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
- InO indium oxide
- X1 X1 is a real number greater than 0
- In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers greater than 0
- GaO X3 X3 is a real number greater than 0
- Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 a real number greater than 0) to.
- the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud-like It is also referred to.).
- the CAC-OS is a complex oxide semiconductor having a structure in which a region in which GaO X3 is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are mixed.
- the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.
- IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 + x0) Ga ( 1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.
- the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
- the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.
- CAC-OS relates to the material configuration of an oxide semiconductor.
- the CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components.
- region observed in shape says the structure currently disperse
- CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
- the CAC-OS is partially observed in the form of nanoparticles having the metal element as a main component, and partially having In as a main component.
- region observed in particle form says the structure currently each disperse
- the CAC-OS can be formed by, for example, a sputtering method under conditions in which the substrate is not intentionally heated.
- a sputtering method one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas.
- an inert gas typically, argon
- oxygen gas typically, oxygen gas
- a nitrogen gas may be used as a deposition gas.
- the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible.
- the flow rate ratio of the oxygen gas is 0% to 30%, preferably 0% to 10%. .
- CAC-OS has a feature that a clear peak is not observed when it is measured using a ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods.
- XRD X-ray diffraction
- the CAC-OS has a ring-like high luminance region (ring region) and the ring Several bright spots are observed in the area. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.
- GaO X3 is a main component by EDX mapping acquired using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) It can be confirmed that the region and the region containing In X 2 Zn Y 2 O Z 2 or In O X 1 as the main component have a structure in which the regions are localized and mixed.
- EDX Energy Dispersive X-ray spectroscopy
- the CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase separated into a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.
- the region whose main component is In X2 Zn Y2 O Z2 or InO X1 is a region whose conductivity is higher than the region whose main component is GaO X3 or the like. That is, when carriers flow in a region mainly containing In X2 Zn Y2 O Z2 or InO X1 , conductivity as an oxide semiconductor is exhibited. Accordingly, In X2 Zn Y2 O Z2, or InO X1 is the main component region, that distributed in the cloud-like in the oxide semiconductor, a high field-effect mobility (mu) can be realized.
- the region whose main component is GaO X3 or the like is a region whose insulating property is higher than the region whose main component is In X2 Zn Y2 O Z2 or InO X1 . That is, by distributing a region containing GaO X3 or the like as a main component in the oxide semiconductor, leakage current can be suppressed and favorable switching operation can be realized.
- the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act complementarily to achieve high results.
- the on current (I on ) and high field effect mobility ( ⁇ ) can be realized.
- CAC-OS is suitable as a constituent material of various semiconductor devices.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
- Embodiment 4 In this embodiment, an electronic device of one embodiment of the present invention will be described with reference to FIG.
- the electronic device of this embodiment includes the display device of one embodiment of the present invention. This makes it possible to reduce the price of the electronic device.
- An image having a resolution of, for example, full high definition, 2K, 4K, 8K, 16K, or more can be displayed on the display portion of the electronic device of this embodiment.
- the screen size of the display portion can be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches or more diagonally, 60 inches diagonally or more, or 70 inches diagonally or more.
- Examples of the electronic devices include relatively large screens of television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc.
- digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like can be given.
- the electronic device of one embodiment of the present invention may have an antenna.
- the display portion can display an image, information, and the like.
- the antenna may be used for contactless power transmission.
- the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, inclination, vibration, smell or infrared light.
- the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying date or time, etc., a function of executing various software (programs), wireless communication A function, a function of reading a program or data recorded in a recording medium, or the like can be provided.
- FIG. 20A shows an example of a television set.
- a display portion 7000 is incorporated in a housing 7101.
- a structure in which the housing 7101 is supported by the stand 7103 is shown.
- the display device of one embodiment of the present invention can be applied to the display portion 7000.
- the television set 7100 illustrated in FIG. 20A can be operated by an operation switch of the housing 7101 or a separate remote controller 7111.
- the display portion 7000 may be provided with a touch sensor or may be operated by touching the display portion 7000 with a finger or the like.
- the remote controller 7111 may have a display unit for displaying information output from the remote controller 7111. Channels and volume can be controlled with an operation key or a touch panel of the remote controller 7111, and an image displayed on the display portion 7000 can be manipulated.
- the television set 7100 is provided with a receiver, a modem, and the like.
- the receiver can receive a general television broadcast.
- a modem by connecting to a wired or wireless communication network via a modem, one-way (sender to receiver) or two-way (sender and receiver, or between receivers, etc.) information communication can be performed. It is also possible.
- FIG. 20B shows an example of a laptop personal computer.
- the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
- a display portion 7000 is incorporated in the housing 7211.
- the display device of one embodiment of the present invention can be applied to the display portion 7000.
- FIGS. 20C and 20D show an example of digital signage.
- a digital signage 7300 illustrated in FIG. 20C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.
- FIG. 20D shows a digital signage 7400 attached to a cylindrical column 7401.
- the digital signage 7400 has a display portion 7000 provided along the curved surface of the column 7401.
- the display device of one embodiment of the present invention can be applied to the display portion 7000.
- the display unit 7000 As the display unit 7000 is wider, the amount of information that can be provided at one time can be increased. Also, the wider the display portion 7000, the easier it is for a person to see, and for example, the advertising effect of the advertisement can be enhanced.
- a touch panel By applying a touch panel to the display portion 7000, not only a still image or a moving image can be displayed on the display portion 7000, but also the user can operate intuitively, which is preferable. Moreover, when it uses for the application for providing information, such as route information or traffic information, usability can be improved by intuitive operation.
- the digital signage 7300 or the digital signage 7400 can cooperate with the information terminal 7311 or information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred.
- information of an advertisement displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
- the display of the display portion 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
- the digital signage 7300 or the digital signage 7400 execute a game in which the screen of the information terminal 7311 or the information terminal 7411 is an operation means (controller). In this way, an unspecified number of users can simultaneously participate in and enjoy the game.
- the display system of one embodiment of the present invention can be incorporated along the inner or outer wall of a house or building, or along the curved surface of the interior or exterior of a vehicle.
- This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
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Abstract
Description
本実施の形態では、本発明の一態様の表示装置について図面を用いて説明する。
図1(A)は、本発明の一態様の表示装置である表示装置10の構成例を示す図である。表示装置10は、画素11がm行n列(m、nは2以上の整数)のマトリクス状に設けられた画素アレイ14と、ゲートドライバ回路12と、ソースドライバ回路13と、画像データ生成回路61と、画像処理回路62と、を有する。また、画素11は、表示デバイス26を有する。表示デバイス26として、例えば液晶デバイスを用いることができる。
図2(A)では、レベルシフト回路63と、インバータ回路64と、スイッチ48aと、スイッチ48bと、選択回路65とをソースドライバ回路13に設ける構成としたが、これらがソースドライバ回路13に設けられていなくてもよい。図4は、図2(A)に示す構成の変形例であり、インバータ回路64及び選択回路65が、ソースドライバ回路13とは別の回路であるスイッチ回路16に設けられている。また、スイッチ回路16には、スイッチ48aとしてトランジスタ68aが、スイッチ48bとしてトランジスタ68bがそれぞれ設けられている。なお、レベルシフト回路63は、ソースドライバ回路13及びスイッチ回路16のいずれにも設けられていない。また、スイッチ回路16には、電位生成回路70が設けられている。
図5(A)は、図4に示す構成の変形例であり、スイッチ回路16が電位生成回路70を有さない点、及びスイッチ回路16がトランジスタ71及び容量素子72を有する点が図4に示す構成と異なる。なお、図5(A)では、トランジスタ68a、トランジスタ68b、トランジスタ71のいずれもバックゲートを有さない構成としているが、一部又は全てのトランジスタがバックゲートを有する構成としてもよい。また、当該バックゲートに電位生成回路を電気的に接続し、当該バックゲートの電位を制御してもよい。また、ゲートとバックゲートを電気的に接続し、バックゲートの電位をゲートの電位と等しくする構成としてもよい。
図2(A)等では、ソースドライバ回路13に入力されるデジタル画像データに含まれる第2のデータのビット数が1ビットである場合の、ソースドライバ回路13等の構成例を示しているが、第2のデータのビット数は2ビット以上であってもよい。図6は、第2のデータのビット数が2ビットである場合における、ソースドライバ回路13の構成例であり、図2(A)の変形例である。
以下では、画素11の構成例について説明する。図8は、画素11として用いることができる画素11aを説明する図である。画素11aは、トランジスタ21と、トランジスタ22と、容量素子25と、表示デバイス26を有する。ここで、トランジスタ21及びトランジスタ22として、例えばCMOSトランジスタ、nチャネル型トランジスタ、又はpチャネル型トランジスタを用いることができる。以下では、トランジスタ21及びトランジスタ22として、nチャネル型トランジスタを用いた場合について説明するが、その他のトランジスタを用いた場合であっても以下の説明を参酌することができる。
図10は、画素11として用いることができる画素11bを説明する図である。画素11bは、画素11aの変形例であり、トランジスタ23が設けられている点が画素11aと異なる。ここで、トランジスタ23として、例えばCMOSトランジスタ、nチャネル型トランジスタ、又はpチャネル型トランジスタを用いることができる。以下では、トランジスタ23として、nチャネル型トランジスタを用いた場合について説明するが、その他のトランジスタを用いた場合であっても以下の説明を参酌することができる。
図12(A)は、画素11として用いることができる画素11cを説明する図であり、図12(B)は、画素11として用いることができる画素11dを説明する図である。画素11cは、画素11aに設けられたトランジスタ21及びトランジスタ22にバックゲートを設けた構成である。画素11dは、画素11bに設けられたトランジスタ21乃至トランジスタ23にバックゲートを設けた構成である。バックゲートは、当該バックゲートが設けられたトランジスタのフロントゲートと電気的に接続することができ、オン電流を高める効果を有する。また、バックゲートにフロントゲートと異なる電位を供給できる構成としてもよい。当該構成とすることで、トランジスタのしきい値電圧を制御することができる。なお、図12(A)、(B)においては、全てのトランジスタにバックゲートを設けた構成を図示しているが、バックゲートが設けられないトランジスタを有していてもよい。
図13(A)は、画素11として用いることができる画素11eを説明する図である。画素11eは、画素11bに設けられた表示デバイス26の他方の電極を、ノードN2と接続されない構成としたものである。画素11eでは、表示デバイス26の他方の電極は、共通配線としての機能を有する配線36と電気的に接続することができる。ここで、配線36には、定電位が供給される。配線36には、例えば配線35に供給される電位と同じ電位を供給することができる。配線36には、例えば接地電位又は電位VMを供給することができる。なお、画素11eは、図11に示す方法と同様の方法により動作させることができる。
図14は、表示装置10の構成例を示す断面図であり、表示装置10が、横電界方式が適用された透過型液晶表示装置である場合を示している。
図15は、表示装置10の構成例を示す断面図であり、表示装置10が、縦電界方式が適用された透過型液晶表示装置である場合を示している。表示装置に設けられた画素11が画素11e又は画素11fである場合は、表示デバイス26が有する電極182を、容量素子25が有する電極と電気的に接続しなくてよい。このため、表示デバイス26が有する電極181と、電極182と、が液晶層183を挟んで対向する位置に設けることができ、したがって表示装置10を縦電界方式が適用された透過型液晶表示装置とすることができる。表示装置10が、縦電界方式が適用された透過型液晶表示装置である場合、表示デバイス26として、TN(Twisted Nematic)モード、VA(Vertical Alignment)モード、MVA(Multidomain Vertical Alignment)モード、PVA(Patterned Vertical Alignment)モード、OCB(Optically Compensated Bend)モード等が適用された液晶デバイスを用いることができる。
本実施の形態では、上記実施の形態に示した各トランジスタに置き換えて用いることのできるトランジスタの一例について、図面を用いて説明する。
図16(A1)は、ボトムゲート型のトランジスタの一種であるチャネル保護型のトランジスタ810のチャネル長方向の断面図である。図16(A1)において、トランジスタ810は基板771上に形成されている。また、トランジスタ810は、基板771上に絶縁層772を介して電極746を有する。また、電極746上に絶縁層726を介して半導体層742を有する。電極746はゲート電極として機能できる。絶縁層726はゲート絶縁層として機能できる。
図18(A1)に例示するトランジスタ842は、トップゲート型のトランジスタの1つである。トランジスタ842は、絶縁層729を形成した後に電極744a及び電極744bを形成する。電極744a及び電極744bは、絶縁層728及び絶縁層729に形成した開口部において半導体層742と電気的に接続する。
本実施の形態では、OSトランジスタの詳細な構成例について説明する。
本実施の形態では、本発明の一態様の電子機器について図20を用いて説明する。
Claims (8)
- 第1の回路と、第2の回路と、画素と、を有する表示装置であって、
前記第1の回路は、第1のデータと、第2のデータと、を有するデジタル画像データを生成する機能を有し、
前記第2の回路は、第1の配線を介して前記画素と電気的に接続され、
前記第2の回路は、第2の配線を介して前記画素と電気的に接続され、
前記第2の回路は、前記第1の配線の電位を、前記第1のデータに対応する電位、又は前記第2のデータに対応する電位の一方にする機能を有し、
前記第2の回路は、前記第2の配線の電位を、前記第1のデータに対応する電位、又は前記第2のデータに対応する電位の他方にする機能を有し、
前記画素は、第1のトランジスタと、第2のトランジスタと、容量素子と、表示デバイスと、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記容量素子の一方の電極と電気的に接続され、
前記容量素子の一方の電極は、前記表示デバイスの一方の電極と電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記容量素子の他方の電極と電気的に接続され、
前記第1のトランジスタのソース又はドレインの他方は、第1の配線と電気的に接続され、
前記第2のトランジスタのソース又はドレインの他方は、第2の配線と電気的に接続され、
前記表示デバイスは、前記画像データに対応する画像を表示する機能を有する表示装置。 - 請求項1において、
前記第2の回路は、選択回路を有し、
前記選択回路は、第1の入力端子と、第2の入力端子と、第1の出力端子と、第2の出力端子と、を有し、
前記第1の入力端子には、前記第1のデータに対応する電位が供給され、
前記第2の入力端子には、前記第2のデータに対応する電位が供給され、
前記第1の出力端子は、前記第1の配線と電気的に接続され、
前記第2の出力端子は、前記第2の配線と電気的に接続される表示装置。 - 請求項2において、
前記第2の回路は、第1のスイッチと、第2のスイッチと、を有し、
前記第2の入力端子は、前記第1のスイッチの一方の端子、及び前記第2のスイッチの一方の端子と電気的に接続され、
前記第1のスイッチの他方の端子には、第1の電位が供給され、
前記第2のスイッチの他方の端子には、第2の電位が供給され、
前記第1のスイッチ、及び前記第2のスイッチは、前記第2のデータによりオンオフが制御される表示装置。 - 請求項1乃至3のいずれか一項において、
前記第2のデータは、前記デジタル画像データの最上位ビットに関する情報を含む表示装置。 - 請求項1乃至4のいずれか一項において、
前記第2の回路は、ソースドライバ回路である表示装置。 - 請求項1乃至5のいずれか一項において、
前記表示デバイスは、液晶デバイスである表示装置。 - 請求項6において、
前記表示デバイスは、ブルー相を示す液晶を有する表示装置。 - 請求項1乃至7のいずれか一項において、
前記第1及び第2のトランジスタは、チャネル形成領域に金属酸化物を有し、
前記金属酸化物は、Inと、Znと、M(MはAl、Ti、Ga、Sn、Y、Zr、La、Ce、Nd、又はHf)と、を有する表示装置。
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CN202210718274.9A CN115578983A (zh) | 2018-01-19 | 2019-01-08 | 显示装置 |
JP2019566001A JP7360950B2 (ja) | 2018-01-19 | 2019-01-08 | 表示装置 |
US16/962,304 US11360363B2 (en) | 2018-01-19 | 2019-01-08 | Display apparatus having pixels connected to first and second wirings set to different potentials |
US17/837,711 US11815775B2 (en) | 2018-01-19 | 2022-06-10 | Display apparatus having pixels connected to first and second wirings set to different potentials |
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- 2019-01-08 CN CN202210718274.9A patent/CN115578983A/zh active Pending
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CN111566722A (zh) | 2020-08-21 |
US20200341340A1 (en) | 2020-10-29 |
US11360363B2 (en) | 2022-06-14 |
US20220299831A1 (en) | 2022-09-22 |
KR20200104877A (ko) | 2020-09-04 |
KR102663104B1 (ko) | 2024-05-02 |
CN111566722B (zh) | 2022-07-15 |
JPWO2019142065A1 (ja) | 2021-01-14 |
CN115578983A (zh) | 2023-01-06 |
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US11815775B2 (en) | 2023-11-14 |
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