JP7360950B2 - 表示装置 - Google Patents
表示装置 Download PDFInfo
- Publication number
- JP7360950B2 JP7360950B2 JP2019566001A JP2019566001A JP7360950B2 JP 7360950 B2 JP7360950 B2 JP 7360950B2 JP 2019566001 A JP2019566001 A JP 2019566001A JP 2019566001 A JP2019566001 A JP 2019566001A JP 7360950 B2 JP7360950 B2 JP 7360950B2
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- JP
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- Prior art keywords
- potential
- transistor
- display device
- wiring
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004973 liquid crystal related substance Substances 0.000 claims description 52
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- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
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Description
本実施の形態では、本発明の一態様の表示装置について図面を用いて説明する。
図1(A)は、本発明の一態様の表示装置である表示装置10の構成例を示す図である。表示装置10は、画素11がm行n列(m、nは2以上の整数)のマトリクス状に設けられた画素アレイ14と、ゲートドライバ回路12と、ソースドライバ回路13と、画像データ生成回路61と、画像処理回路62と、を有する。また、画素11は、表示デバイス26を有する。表示デバイス26として、例えば液晶デバイスを用いることができる。
図2(A)では、レベルシフト回路63と、インバータ回路64と、スイッチ48aと、スイッチ48bと、選択回路65とをソースドライバ回路13に設ける構成としたが、これらがソースドライバ回路13に設けられていなくてもよい。図4は、図2(A)に示す構成の変形例であり、インバータ回路64及び選択回路65が、ソースドライバ回路13とは別の回路であるスイッチ回路16に設けられている。また、スイッチ回路16には、スイッチ48aとしてトランジスタ68aが、スイッチ48bとしてトランジスタ68bがそれぞれ設けられている。なお、レベルシフト回路63は、ソースドライバ回路13及びスイッチ回路16のいずれにも設けられていない。また、スイッチ回路16には、電位生成回路70が設けられている。
図5(A)は、図4に示す構成の変形例であり、スイッチ回路16が電位生成回路70を有さない点、及びスイッチ回路16がトランジスタ71及び容量素子72を有する点が図4に示す構成と異なる。なお、図5(A)では、トランジスタ68a、トランジスタ68b、トランジスタ71のいずれもバックゲートを有さない構成としているが、一部又は全てのトランジスタがバックゲートを有する構成としてもよい。また、当該バックゲートに電位生成回路を電気的に接続し、当該バックゲートの電位を制御してもよい。また、ゲートとバックゲートを電気的に接続し、バックゲートの電位をゲートの電位と等しくする構成としてもよい。
図2(A)等では、ソースドライバ回路13に入力されるデジタル画像データに含まれる第2のデータのビット数が1ビットである場合の、ソースドライバ回路13等の構成例を示しているが、第2のデータのビット数は2ビット以上であってもよい。図6は、第2のデータのビット数が2ビットである場合における、ソースドライバ回路13の構成例であり、図2(A)の変形例である。
以下では、画素11の構成例について説明する。図8は、画素11として用いることができる画素11aを説明する図である。画素11aは、トランジスタ21と、トランジスタ22と、容量素子25と、表示デバイス26を有する。ここで、トランジスタ21及びトランジスタ22として、例えばCMOSトランジスタ、nチャネル型トランジスタ、又はpチャネル型トランジスタを用いることができる。以下では、トランジスタ21及びトランジスタ22として、nチャネル型トランジスタを用いた場合について説明するが、その他のトランジスタを用いた場合であっても以下の説明を参酌することができる。
図10は、画素11として用いることができる画素11bを説明する図である。画素11bは、画素11aの変形例であり、トランジスタ23が設けられている点が画素11aと異なる。ここで、トランジスタ23として、例えばCMOSトランジスタ、nチャネル型トランジスタ、又はpチャネル型トランジスタを用いることができる。以下では、トランジスタ23として、nチャネル型トランジスタを用いた場合について説明するが、その他のトランジスタを用いた場合であっても以下の説明を参酌することができる。
図12(A)は、画素11として用いることができる画素11cを説明する図であり、図12(B)は、画素11として用いることができる画素11dを説明する図である。画素11cは、画素11aに設けられたトランジスタ21及びトランジスタ22にバックゲートを設けた構成である。画素11dは、画素11bに設けられたトランジスタ21乃至トランジスタ23にバックゲートを設けた構成である。バックゲートは、当該バックゲートが設けられたトランジスタのフロントゲートと電気的に接続することができ、オン電流を高める効果を有する。また、バックゲートにフロントゲートと異なる電位を供給できる構成としてもよい。当該構成とすることで、トランジスタのしきい値電圧を制御することができる。なお、図12(A)、(B)においては、全てのトランジスタにバックゲートを設けた構成を図示しているが、バックゲートが設けられないトランジスタを有していてもよい。
図13(A)は、画素11として用いることができる画素11eを説明する図である。画素11eは、画素11bに設けられた表示デバイス26の他方の電極を、ノードN2と接続されない構成としたものである。画素11eでは、表示デバイス26の他方の電極は、共通配線としての機能を有する配線36と電気的に接続することができる。ここで、配線36には、定電位が供給される。配線36には、例えば配線35に供給される電位と同じ電位を供給することができる。配線36には、例えば接地電位又は電位VMを供給することができる。なお、画素11eは、図11に示す方法と同様の方法により動作させることができる。
図14は、表示装置10の構成例を示す断面図であり、表示装置10が、横電界方式が適用された透過型液晶表示装置である場合を示している。
図15は、表示装置10の構成例を示す断面図であり、表示装置10が、縦電界方式が適用された透過型液晶表示装置である場合を示している。表示装置に設けられた画素11が画素11e又は画素11fである場合は、表示デバイス26が有する電極182を、容量素子25が有する電極と電気的に接続しなくてよい。このため、表示デバイス26が有する電極181と、電極182と、が液晶層183を挟んで対向する位置に設けることができ、したがって表示装置10を縦電界方式が適用された透過型液晶表示装置とすることができる。表示装置10が、縦電界方式が適用された透過型液晶表示装置である場合、表示デバイス26として、TN(Twisted Nematic)モード、VA(Vertical Alignment)モード、MVA(Multidomain Vertical Alignment)モード、PVA(Patterned Vertical Alignment)モード、OCB(Optically Compensated Bend)モード等が適用された液晶デバイスを用いることができる。
本実施の形態では、上記実施の形態に示した各トランジスタに置き換えて用いることのできるトランジスタの一例について、図面を用いて説明する。
図16(A1)は、ボトムゲート型のトランジスタの一種であるチャネル保護型のトランジスタ810のチャネル長方向の断面図である。図16(A1)において、トランジスタ810は基板771上に形成されている。また、トランジスタ810は、基板771上に絶縁層772を介して電極746を有する。また、電極746上に絶縁層726を介して半導体層742を有する。電極746はゲート電極として機能できる。絶縁層726はゲート絶縁層として機能できる。
図18(A1)に例示するトランジスタ842は、トップゲート型のトランジスタの1つである。トランジスタ842は、絶縁層729を形成した後に電極744a及び電極744bを形成する。電極744a及び電極744bは、絶縁層728及び絶縁層729に形成した開口部において半導体層742と電気的に接続する。
本実施の形態では、OSトランジスタの詳細な構成例について説明する。
本実施の形態では、本発明の一態様の電子機器について図20を用いて説明する。
Claims (8)
- 第1の回路と、第2の回路と、画素と、を有する表示装置であって、
前記第1の回路は、第1のデータと、第2のデータと、を有するデジタル画像データを生成する機能を有し、
前記第2の回路は、第1の配線を介して前記画素と電気的に接続され、
前記第2の回路は、第2の配線を介して前記画素と電気的に接続され、
前記第2の回路は、前記第1の配線の電位を、前記第1のデータに対応する電位、又は前記第2のデータに対応する電位の一方にする機能を有し、
前記第2の回路は、前記第2の配線の電位を、前記第1のデータに対応する電位、又は前記第2のデータに対応する電位の他方にする機能を有し、
前記画素は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、
容量素子と、表示デバイスと、を有し、
前記第1のトランジスタのソース又はドレインの一方は、前記容量素子の一方の電極と電気的に接続され、
前記容量素子の一方の電極は、前記表示デバイスの一方の電極と電気的に接続され、
前記第2のトランジスタのソース又はドレインの一方は、前記容量素子の他方の電極と電気的に接続され、
前記第1のトランジスタのソース又はドレインの他方は、前記第1の配線と電気的に接続され、
前記第2のトランジスタのソース又はドレインの他方は、前記第2の配線と電気的に接続され、
前記第3のトランジスタのソース又はドレインの一方は、前記容量素子の他方の電極及び前記第2のトランジスタのソース又はドレインの一方と電気的に接続され、
前記第1のトランジスタのゲート及び前記第2のトランジスタのゲートは、第3の配線と電気的に接続され、
前記第3のトランジスタのゲートは、第4の配線と電気的に接続され、
前記第3のトランジスタのソース又はドレインの他方は、第5の配線と電気的に接続され、
前記第3の配線は第1の走査線としての機能を有し、
前記第4の配線は第2の走査線としての機能を有し、
前記第5の配線は定電位を供給する機能を有し、
前記表示デバイスは、前記デジタル画像データに対応する画像を表示する機能を有する表示装置。 - 請求項1において、
前記第2の回路は、選択回路を有し、
前記選択回路は、第1の入力端子と、第2の入力端子と、第1の出力端子と、第2の出力端子と、を有し、
前記第1の入力端子には、前記第1のデータに対応する電位が供給され、
前記第2の入力端子には、前記第2のデータに対応する電位が供給され、
前記第1の出力端子は、前記第1の配線と電気的に接続され、
前記第2の出力端子は、前記第2の配線と電気的に接続される表示装置。 - 請求項2において、
前記第2の回路は、第1のスイッチと、第2のスイッチと、を有し、
前記第2の入力端子は、前記第1のスイッチの一方の端子、及び前記第2のスイッチの一方の端子と電気的に接続され、
前記第1のスイッチの他方の端子には、第1の電位が供給され、
前記第2のスイッチの他方の端子には、第2の電位が供給され、
前記第1のスイッチ、及び前記第2のスイッチは、前記第2のデータによりオンオフが制御される表示装置。 - 請求項1乃至3のいずれか一項において、
前記第2のデータは、前記デジタル画像データの最上位ビットに関する情報を含む表示装置。 - 請求項1乃至4のいずれか一項において、
前記第2の回路は、ソースドライバ回路である表示装置。 - 請求項1乃至5のいずれか一項において、
前記表示デバイスは、液晶デバイスである表示装置。 - 請求項6において、
前記表示デバイスは、ブルー相を示す液晶を有する表示装置。 - 請求項1乃至7のいずれか一項において、
前記第1のトランジスタ及び前記第2のトランジスタは、チャネル形成領域に金属酸化物を有し、
前記金属酸化物は、Inと、Znと、M(MはAl、Ti、Ga、Sn、Y、Zr、La、Ce、Nd、又はHf)と、を有する表示装置。
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