WO2019127694A1 - 一种栅极驱动器及驱动电路 - Google Patents

一种栅极驱动器及驱动电路 Download PDF

Info

Publication number
WO2019127694A1
WO2019127694A1 PCT/CN2018/072888 CN2018072888W WO2019127694A1 WO 2019127694 A1 WO2019127694 A1 WO 2019127694A1 CN 2018072888 W CN2018072888 W CN 2018072888W WO 2019127694 A1 WO2019127694 A1 WO 2019127694A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
module
pull
port
gate
Prior art date
Application number
PCT/CN2018/072888
Other languages
English (en)
French (fr)
Inventor
陈帅
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US16/003,532 priority Critical patent/US20190197973A1/en
Publication of WO2019127694A1 publication Critical patent/WO2019127694A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the present invention relates to the field of electronic technologies, and in particular, to a gate driver and a driving circuit.
  • a Gate Driver on Array is an electronic device for scanning and driving a liquid crystal panel. Since the gate driver has the advantages of low cost and high efficiency, it is often used in various display screens, such as an active-matrix organic light emitting diode (AMOLED) of a self-luminous display screen, and The practical application of AMOLED is faster, so the gate driver is also the key technology for the development of LCD panels in the future.
  • AMOLED active-matrix organic light emitting diode
  • Capacitive coupling refers to the presence of capacitance between any two energized conductors, such as between power transmission lines, between power transmission lines and ground, between transistors, and between components. If the capacitive coupling of the data line in the liquid crystal panel to the horizontal signal scan line of the gate driver is serious, the gate driver may not be able to pull down the potential of the horizontal scanning line of the liquid crystal panel, and the gate of the liquid crystal panel may not be effectively turned off. , thus causing the screen to display an abnormality.
  • the embodiment of the invention provides a gate driver, which can effectively lower the level of the horizontal scan line of the gate driver and improve the stability of the circuit.
  • an embodiment of the present invention provides a gate driver, including a pull-up control module, a pull-down maintenance module, a pull-up module, a signal downlink module, a pull-down module, and a bootstrap module;
  • the pull-up control module includes a port;
  • the pull-down maintaining module includes a first port, a second port, and a third port;
  • the pull-up module includes a first port, a second port, and a third port;
  • the signal downlink module includes a first port and a second port;
  • the pull-down module includes a first port, a second port, a third port, a fourth port, and a fifth port;
  • the bootstrap module includes a first port and a second port;
  • the connection point is a gate signal point;
  • the second port of the pull-down maintenance module, the second port of the pull-down module, the second port of the bootstrap module, and The second port of the pull-up module is respectively connected to the horizontal scan line;
  • the third port of the pull-down maintenance module and the third port of the pull-down module are respectively connected to the low-level signal line;
  • the third of the pull-up module The port and the second port of the signal downlink module are respectively connected to the clock signal line;
  • the pull-up control module is configured to precharge the gate signal point, and when the gate signal point is at a high level, control the pull-up module to output the signal of the clock signal line to the a horizontal scan line; in a case where the first control signal received by the fourth port of the pull-down module is at a high level, the pull-down module outputs a signal of the low-level signal line to the horizontal scan line In a case where the second control signal received by the fifth port of the pull-down module is a high level, the pull-down module outputs a signal of the low-level signal line to the gate signal point, and the control station a pull-down maintaining module outputs a signal of the low-level signal line to the horizontal scan line; the bootstrap module is configured to increase and maintain a level of the gate signal point; and the signal downlink module is used to When the gate signal point is at a high level, the signal of the clock signal line is transmitted to other electronic devices.
  • the first control signal is different from the second control signal.
  • the pull-up control module includes: a first transistor; a source and a source of the first transistor a gate signal point connection; controlling a drain of the first transistor to input a received signal to a source of the first transistor when a gate of the first transistor is at a high level; pole.
  • the pull-up circuit includes a second one transistor; a gate of the second one transistor and the gate a pole signal point connection; a drain of the second transistor is coupled to a second port of the signal downlink module; a source of the second transistor is coupled to the horizontal scan line; When the gate of the transistor is at a high level, the drain of the second transistor is controlled to input a signal of the clock signal line to a source of the second transistor.
  • the signal downlink module includes a third transistor; a gate of the third transistor and the a gate signal point is connected; a drain of the third transistor is connected to a third port of the pull-up module; and in a case where a gate of the third transistor is at a high level, the third is controlled A drain of a transistor inputs a signal of the clock signal line to a source of the third transistor.
  • the pull-down module includes a fourth transistor and a fourth transistor; a drain of the fourth transistor Connected to the horizontal scan line, the drain of the fourth transistor is connected to the gate signal point; the source of the fourth transistor and the source of the fourth transistor are maintained with the pull-down a module connection; a gate of the fourth transistor and a gate of the fourth transistor are respectively configured to receive a first control signal and a second control signal; and a gate of the fourth transistor is at a high level a case where a source of the fourth transistor is controlled to input a signal of the low level signal line to a drain of the fourth transistor; and a gate of the fourth transistor is at a high level In a case, the source of the fourth transistor is controlled to input a signal of the low-level signal line to a drain of the fourth transistor.
  • the pull-down maintaining module includes an inverter, a fifth one transistor, and a fifth two transistor;
  • the input end of the device is connected to the gate signal point, the output end of the inverter is connected to the gate of the fifth transistor and the gate of the fifth transistor;
  • the fifth transistor a drain is connected to the horizontal scan line, a source of the fifth transistor is connected to a third port of the pull-down module, and a drain of the fifth transistor is connected to the gate signal point, a source of the fifth transistor is connected to the third port of the pull-down module;
  • when the input of the inverter is at a low level, an output of the inverter is toward the fifth transistor
  • the gate outputs a high level, and a signal for controlling the low level signal line is transmitted from a source of the fifth transistor to a drain of the fifth transistor.
  • the bootstrap module includes a first capacitor; one end of the first capacitor and the gate signal point Connected, the other end is connected to the horizontal scan line.
  • the inverter includes a fifth three transistor, a fifth four transistor, a fifth five transistor, and a fifth six transistor; a pole signal point is connected to a gate of the fifth five transistor and a gate of the fifth six transistor; a source of the fifth five transistor and a source of the fifth six transistor and the pull-down module a third port connection; a drain of the fifth five transistor is connected to a source of the fifth three transistor and a gate of the five or four transistor; a drain of the fifth six transistor and the five or four transistor a source, a gate connection of the five-one transistor, and a gate connection of the five-two transistor; a gate of the five-three transistor, a drain of the five-three transistor, and a drain of the five-four transistor connection.
  • an embodiment of the present invention provides a driving circuit, wherein the driving circuit includes a plurality of gate drivers according to any one of claims 1-9;
  • the signal downlink module further includes a third port;
  • the pull-up control module of the gate driver further includes a second port; and the third port and the (N+) of the signal downlink module of the Nth-level gate driver 1)
  • the second port of the pull-up control module of the stage gate driver is connected.
  • the pull-down module and the pull-up module to jointly pull down the level on the horizontal scan line, the pull-down effect of the gate driver can be effectively improved, and the stability of the circuit is improved.
  • FIG. 1 is a schematic structural diagram of a gate driver according to an embodiment of the present invention.
  • FIG. 2 is a schematic diagram of voltage variation in a gate driver according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of a gate driver according to another embodiment of the present invention.
  • FIG. 4 is a schematic structural diagram of a gate driver according to another embodiment of the present invention.
  • FIG. 5 is a schematic block diagram of a terminal device according to another embodiment of the present invention.
  • FIG. 6 is a schematic diagram of voltage variation in a gate driver according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of voltage changes in a gate signal point of a gate driver according to an embodiment of the present invention.
  • the term “if” can be interpreted as “when” or “on” or “in response to determining” or “in response to detecting” depending on the context. .
  • the phrase “if determined” or “if detected [condition or event described]” may be interpreted in context to mean “once determined” or “in response to determining” or “once detected [condition or event described] ] or “in response to detecting [conditions or events described]”.
  • a device including a display panel includes a driving circuit for driving the display panel, and the driving circuit is often cascaded by a plurality of gate drivers.
  • FIG. 1 is a schematic structural diagram of a gate driver according to an embodiment of the present invention. The gate driver as shown in FIG.
  • the control module 1', the pull-down maintenance module 5', the pull-up module 2', the signal downlink module 3', the pull-down module 4', and the bootstrap module 6' are connected, and the connection point is the gate signal point Q(N);
  • the module 5', the bootstrap module 6', the pull-up module 2', and the pull-down module 4' are connected to the horizontal scanning line G(N), respectively.
  • the pull-up control module 1' is used for pre-charging the gate signal point Q(N)
  • the pull-up module 2' is used to increase the point potential on the horizontal scanning line G(N)
  • the signal downlink module 3' is used for Controlling the opening and closing of the next stage gate driver connected to the gate driver
  • the pull-down module 4' is for pulling the potentials of Q(N) and G(N) to be consistent with the low level signal VSS
  • the pull-down sustaining unit The point potential for controlling Q(N) and G(N) is maintained at VSS
  • the bootstrap capacitor is used to increase and maintain the point potential of Q(N).
  • the pull-up control module 1' When the signals in the pull-up control signals ST(N-1) and G(N-1) are at a high level, the pull-up control module 1' precharges Q(N) when the point potential in Q(N) When the high level capable of driving the pull-up module 2' is reached, the pull-up module 2' transmits the clock signal CK to the pull-up control signal ST(N) of the G(N) and pull-up control module 1' of the next gate driver.
  • the pull-down module 4' transmits the low-level signal VSS to G(N), so that the level of G(N) is pulled low to low level, so VSS
  • VSS low-level signal
  • the signal not only stabilizes the stability of the entire gate driver, but also pulls the high potential G(N) low to a low level, which may result in insufficient VSS pull, resulting in the gate driver not being able to pull down the gate.
  • the potential on the line, the gate on the display panel cannot be turned off immediately, causing the screen to display an abnormality.
  • the signal change in the circuit is as shown in FIG. 2.
  • the pull-up control signal ST(N-1) and the horizontal scan signal G(N-1) transmitted by the previous driver are at a high level, essentially
  • the signals of ST(N-1) and G(N-1) at time t1 are derived from the clock signal obtained by the previous driver, so the pull-up control module 1' precharges Q(N) so that Q(N)
  • the pull-up module 2' transmits the signal of the clock signal line obtained by the third port of the pull-up module 2' from the second port of the pull-up module 2' to the horizontal scan line, so that G(N The point is at a low level; during the time period t2, the point potential of Q(N) due to capacitive coupling is raised to another higher level v2, so that the pull-up module 2' will pull up the module 2'
  • the signal of the clock signal line obtained by the three ports is transmitted from the second port of the pull-up module 2' to
  • Point G (N) point potential during the time period t3, since the control signal G(N-1) obtained by the pull-down module 4' is at a high level, the pull-down module 4' will pull down the module
  • the VSS obtained by the third port of 4' is transmitted from the first port and the second port of the pull-down module 4' to Q(N) and G(N), respectively, such that Q(N) and G(N) are at a low level, Therefore, the pull-down module 4' is used to pull down the point potential of a point G(N) on the horizontal scanning line, and thus it seems that VSS not only needs to stabilize the low level of the horizontal scanning line of the entire liquid crystal panel, but also needs to be
  • the high level of the horizontal scan line of the level gate driver is pulled low to a low level, so the problem of insufficient pulling force of the gate driver may be caused, so that the horizontal scanning line of the liquid crystal panel cannot be pulled down in time, causing the liquid crystal panel to display abnormal.
  • embodiments of the present invention provide a gate driver that can effectively lower the level of a gate line of a liquid crystal panel and improve stability of the circuit. The details are described below.
  • the gate driver includes a pull-up control module, a pull-down maintenance module 5, a pull-up module 2, a signal downlink module 3, and a pull-down module.
  • pull-up control module 1 includes a first port
  • pull-down maintenance module 5 includes a first port, a second port, and a third port
  • pull-up module 2 includes a first port, a second port, and a third a port
  • the signal downlink module 3 includes a first port and a second port
  • the pull-down module 4 includes a first port, a second port, a third port, a fourth port, and a fifth port
  • the bootstrap module 6 includes a first port and a Two ports
  • the port 62 and the second port 22 of the pull-up module 2 are respectively connected to the horizontal scanning line G(N); the third port 53 of the pull-down maintaining module 5 and the third port 43 of the pull-down module 4 are respectively connected to the low-level signal line VSS.
  • the third port 23 of the pull-up module 2 and the second port 32 of the signal downlink module 3 are respectively connected to the clock signal line CK;
  • the pull-up control module 1 is configured to precharge the gate signal point Q(N), and in the case that the gate signal point Q(N) is at a high level, the pull-up module 2 is controlled to output the signal of the clock signal line CK to Horizontal scanning line G(N); in the case where the first control signal G(N+1) received by the fourth port 44 of the pull-down module 4 is at a high level, the pull-down module 4 sets the signal VSS of the low-level signal line Output to the horizontal scan line G(N); in the case where the second control signal G(N+2) received by the fifth port 45 of the pull-down module 4 is at a high level, the pull-down module 4 sets the low-level signal line
  • the signal VSS is output to the gate signal point Q(N), and the pull-down maintaining module 5 outputs the signal VSS of the low-level signal line to the horizontal scanning line G(N); the bootstrap module 6 is used to raise and maintain the gate signal point Q.
  • the level of (N); the signal downlink module 3
  • the first control signal G(N+1) is different from the second control signal G(N+2).
  • the pull-up control module 1 is used to precharge the gate signal point Q(N), and the pull-up module 2 is used to increase the point potential of a point G(N) on the horizontal scanning line;
  • the signal downlink module 3 For controlling the opening and closing of the next-stage gate driver connected to the gate driver;
  • the pull-down module 4 is for pulling the potentials of Q(N) and G(N) to be consistent with the low-level signal VSS;
  • the unit is used to control the point potentials of Q(N) and G(N) to remain unchanged at VSS;
  • the bootstrap capacitor is used to increase and maintain the point potential of Q(N).
  • the signal changes are shown in Figures 6 and 7.
  • the pull-up control module 1 pre-charges Q(N) to a level v1 capable of driving the pull-up module 2, so the pull-up module 2 transmits the signal CK in the clock signal line to G(N)
  • G(N) be low (essentially the pull-up control signal ST(N-1) at time t1 and the signal G(N-1) on the horizontal scan line of the upper driver are derived from the previous driver)
  • the clock signal at this time, the signal for pulling down G(N) is CK; during the time period t2, the point potential in Q(N) continues to be raised to V2 due to capacitive coupling, so that the pull-up module 2
  • the pull-up module 2 Continue to transfer CK to G(N) so that G(N) is high, so pull-up module 2 is used to increase the point potential of a point G(N) on the horizontal scanning line; during time t3, Q( The N) point is pulled low to the high level V3 due to
  • the signal for pulling down G(N) is CK and VSS; at time t4 Inside, the first control signal Q(N+2) is high level, under The pull module 4 transmits the low level signal VSS to Q(N), so that the first port of the pull-down maintaining module 5 inputs a low level, so the pull-down maintaining module 5 pulls down the VSS signal obtained by the third port of the pull-down maintaining module 5
  • the second port of the maintenance module 5 is transmitted to G(N), and the signal for pulling down G(N) is VSS.
  • the gate driver provided by the embodiment of the present invention is directly shifted by the pull-up module 2 and the pull-down module 4 to lower the level of the horizontal scan line of the current gate driver, which can effectively improve the gate driver. Pull down the effect to improve the stability of the circuit.
  • FIG. 4 is a schematic structural view of a gate driver disclosed in an embodiment of the present invention. As shown in Figure 4:
  • the pull-up control module 1 includes: a first transistor T11; a source 11 of the first transistor T11 is connected to a gate signal point Q(N); and a gate of the first transistor T11 is high.
  • the drain of the first transistor T11 is controlled to input the received signal to the source 11 of the first transistor.
  • the pull-up circuit includes a second transistor T21; the gate 21 of the second transistor T21 is connected to the gate signal point Q(N); and the drain 23 of the second transistor T21 is connected to the signal downlink module 3.
  • the second port 32 is connected; the source 22 of the second transistor T11 is connected to the horizontal scanning line G(N); and when the gate 21 of the second transistor T21 is at the high level, the second transistor T21 is controlled.
  • the drain 23 inputs the signal CK of the clock signal line to the source 22 of the second transistor T21.
  • the signal downlink module 3 includes a third transistor T31; the gate 31 of the third transistor T31 is connected to the gate signal point Q(N); and the drain 32 and the pull-up module of the third transistor T31.
  • the third port 23 of 2 is connected; in the case where the gate 31 of the third transistor T31 is at a high level, the drain 32 of the third transistor T31 is controlled to input the signal CK of the clock signal line to the third transistor T31. Source 33.
  • the pull-down module 4 includes a fourth transistor T41 and a fourth transistor T42; the drain 42 of the fourth transistor is connected to the horizontal scan line G(N), and the drain 41 and the gate of the fourth transistor T42 are connected.
  • the pole signal point Q(N) is connected; the source 43 of the fourth transistor and the source 43 of the fourth transistor are connected to the pull-down maintaining module 5; the gate of the fourth transistor and the gate of the fourth transistor are respectively used Receiving the first control signal G(N+1) and the second control signal G(N+2); controlling the source 43 of the fourth transistor T41 when the gate of the fourth transistor is at a high level
  • the signal of the low level signal line VSS is input to the drain 42 of the fourth transistor T41; and when the gate of the fourth transistor receives the high level, the source 43 of the fourth transistor T42 is controlled to be low.
  • the signal of the level signal line VSS is input to the drain 41 of the fourth transistor T42.
  • the pull-down maintaining module 5 includes an inverter, a fifth transistor T51, and a fifth transistor T52; the input terminal 51 of the inverter is connected to the gate signal point Q(N), and the output end of the inverter Connected to the gate of the fifth transistor T51 and the gate of the fifth two transistor T52; the drain 52 of the fifth transistor T51 is connected to the horizontal scanning line G(N), and the source and the pull-down module of the fifth transistor T51 The third port 43 of the fourth port 43 is connected; the drain 51 of the fifth two transistor T52 is connected to the gate signal point Q(N), and the source 53 of the fifth two transistor T52 is connected to the third port 43 of the pull-down module 4; When the input end of the phase comparator is at a low level, the output terminal of the inverter outputs a high level to the gate of the fifth transistor T51, and the signal VSS of the low level signal line is controlled from the source of the fifth transistor T51. The pole 53 is transmitted to the drain 52 of the fifth transistor T51
  • the inverter includes a fifth three transistor T53, a fifth four transistor T54, a fifth five transistor T55, and a fifth six transistor T56; the gate signal point Q(N) and the fifth five The gate of the transistor T55 and the gate of the fifth six transistor T56 are connected; the source of the fifth five transistor T55 and the source of the fifth six transistor T56 are connected to the third port 43 of the pull-down module 4; the fifth five transistor T55 The drain is connected to the source of the fifth three transistor T53 and the gate of the five-four transistor T54; the drain of the fifth six transistor T56 is connected to the source of the five-four transistor T54, the gate of the five-one transistor T51, and the five-two transistor.
  • the gate of T52 is connected; the gate of the five-three transistor T53, the drain of the five-three transistor T53, and the drain of the five-four transistor T54 are connected.
  • the drain input terminal LC of the fifth four-transistor of the pull-down maintenance module is a high-level signal of a direct current.
  • XCK is the reverse signal of the clock signal CK.
  • the bootstrap module 6 includes a first capacitor; one end of the first capacitor is connected to the gate signal point Q(N), and the other end is connected to the horizontal scan line G(N).
  • the signal changes are shown in Figures 6 and 7.
  • the pull-up control signal ST(N-1) and the horizontal scan signal G(N-1) transmitted by the previous driver are at a high level, thus causing the gate of the first transistor T11 of the pull-up control module 1
  • the pole is at a high level, and the ST (N-1) signal is outputted to Q(N), thereby precharging Q(N) to a level V1 of the gate of the second transistor T21 capable of driving the pull-up module 2.
  • the second transistor T21 of the pull-up module 2 transmits the clock signal CK from the drain of the second transistor T21 to the source, that is, to the G(N) point on the horizontal scanning line, so that G(N) Low level; during the time period t2, the point potential in Q(N) continues to be raised to V2 due to capacitive coupling, so the second transistor T21 of the pull-up module 2 continues to transmit CK to G(N) , so that G(N) is high level; in the time period t3, the Q(N) point is pulled down to the high level V3 due to the end of the capacitive coupling action of the CK signal, so the second transistor T21 of the pull-up module 2 Continue to transfer CK to G(N), so that G(N) is low.
  • the second control signal G(N+1) is high, and the fourth transistor T41 of the pull-down module 4 is controlled.
  • Low level letter VSS is transmitted to G(N).
  • the signal for pulling down G(N) is CK and VSS; during the time period t4, the first control signal G(N+2) is high level, and the pull-down module 4 is controlled.
  • the fourth transistor T42 transmits the level signal VSS to Q(N), so that the input port of the inverter is input to a low level, so that the inverter of the pull-down maintaining module 5 outputs a high level to the gate of the fifth transistor.
  • the pole causes the fifth transistor to transfer the obtained VSS signal of the source from the drain of the fifth transistor to G(N), and the signal for pulling down G(N) is VSS.
  • the gate driver described in the embodiment of the present invention can lower the potential on the gate signal point Q(N) by using the low-level signal VSS and the clock signal CK, thereby improving the pull-down effect of the gate driver. Improve the stability of the circuit.
  • the embodiment of the present invention further provides a driving circuit including the gate driver described in the foregoing embodiments of the present invention, the signal downlink module 3 of the gate driver further includes a third port 33; and the pull-up control module 1 of the gate driver A second port 12 is also included; the third port of the signal downlink module 3 of the Nth stage gate driver is coupled to the second port of the pullup control module 1 of the (N+1)th stage gate driver.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Shift Register Type Memory (AREA)

Abstract

本发明实施例公开了一种栅极驱动器及驱动电路，其中，栅极驱动器包括上拉控制模块、下拉维持模块、上拉模块、信号下传模块、下拉模块以及自举模块；所述上拉控制模块、所述下拉维持模块、所述上拉模块、所述信号下传模块、所述下拉模块以及所述自举模块相连，连接点为栅极信号点；所述下拉维持模块、所述自举模块、所述上拉模块以及所述下拉模块分别与水平扫描线连接；本发明实施例通过利用上拉模块与下拉模块共同拉低水平扫描线上的电平，可以有效改善栅极驱动器的下拉效果，提高电路的稳定性。

Description

一种栅极驱动器及驱动电路 技术领域
本发明涉及电子技术领域，尤其涉及一种栅极驱动器及驱动电路。
背景技术
栅极驱动器(Gate Driver on Array，GOA)是一种用于扫描驱动液晶面板的电子器件。由于栅极驱动器有着低成本高效率的优点，因此常常被应用在各种显示屏中，例如自发光显示屏的主动矩阵有机发光二极体(Active-matrix organic light emitting diode，AMOLED)，并且由于AMOLED实用化的脚步较快，因此栅极驱动器也是未来液晶面板发展的重点技术。
在较精密的电路中，电容耦合是一个不容忽视的问题。电容耦合指的是在任何两个通电导体之间都会存在电容，如电力传输线之间、电力传输线与大地之间、晶体管各引脚之间以及元件与元件之间都存在电容。若液晶面板中的数据线对栅极驱动器的水平信号扫描线的电容耦合作用十分严重，可能引发栅极驱动器无法拉低液晶面板的水平扫描线上的电位，导致液晶面板的栅极不能有效关闭，因此造成画面显示异常。
由于电路中的电容耦合严重，而栅极驱动器拉力不足，因此不能有效的拉低栅极驱动器的水平扫描线上的电平。
发明内容
本发明实施例提供一种栅极驱动器，可有效的拉低栅极驱动器的水平扫描线上的电平，提高电路的稳定性。
第一方面，本发明实施例提供了一种栅极驱动器，包括上拉控制模块、下拉维持模块、上拉模块、信号下传模块、下拉模块以及自举模块；所述上拉控制模块含有第一端口；所述下拉维持模块含有第一端口、第二端口以及第三端口；所述上拉模块含第一端口、第二端口以及第三端口；所述信号下传模块含有第一端口以及第二端口；所述下拉模块含有第一端口、第二端口、第三端口、第四端口以及第五端口；所述自举模块含有第一端口以及第二端口；
所述上拉控制模块的第一端口、所述上拉模块的第一端口、所述信号下传模块的第一端口、所述下拉模块的第一端口、所述下拉维持模块的第一端口与所述自举模块的第一端口连接，连接点为栅极信号点；所述下拉维持模块的第二端口、所述下拉模块的第二端口、所述自举模块的第二端口以及所述上拉模块的第二端口分别与水平扫描线连接；所述下拉维持模块的第三端口以及所述下拉模块的第三端口分别与低电平信号线连接；所述上拉模块的第三端口以及所述信号下传模块的第二端口分别与时钟信号线连接；
所述上拉控制模块用于对所述栅极信号点预充电，在所述栅极信号点处于高电平的情况下，控制所述上拉模块将所述时钟信号线的信号输出到所述水平扫描线；在所述下拉模块的第四端口接收到的第一控制信号为高电平的情况下，所述下拉模块将所述低电平信号线的信号输出到所述水平扫描线；在所述下拉模块的第五端口接收到的第二控制信号为高电平的情况下，所述下拉模块将所述低电平信号线的信号输出到所述栅极信号点，控制所述下拉维持模块输出所述低电平信号线的信号到所述水平扫描线；所述自举模块用于提高并维持所述栅极信号点的电平；所述信号下传模块用于在所述栅极信号点为高电平的情况下，将所述时钟信号线的信号传送给其他电子器件。
结合第一方面，在第一方面的第一种实现当中，所述第一控制信号与所述第二控制信号不相同。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第二种实现当中，所述上拉控制模块包括：第一一晶体管；所述第一一晶体管的源极与所述栅极信号点连接；在所述第一一晶体管的栅极处于高电平的情况下，控制所述第一一晶体管的漏极将接收到的信号输入到所述第一一晶体管的源极。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第三种实现当中，所述上拉电路包括第二一晶体管；所述第二一晶体管的栅极与所述栅极信号点连接；所述第二一晶体管的漏极与所述信号下传模块的第二端口连接；所述第二一晶体管的源极与所述水平扫描线连接；在所述第二一晶体管的栅极处于高电平的情况下，控制所述第二一晶体管的漏极将所述时钟信号线的信号输入到所述第二一晶体管的源极。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第四种实现当中，所述信号下传模块包括第三一晶体管；所述第三一晶体管的栅极与所 述栅极信号点连接；所述第三一晶体管的漏极与所述上拉模块的第三端口连接；在所述第三一晶体管的栅极处于高电平的情况下，控制所述第三一晶体管的漏极将所述时钟信号线的信号输入到所述第三一晶体管的源极。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第五种实现当中，所述下拉模块包括第四一晶体管以及第四二晶体管；所述第四一晶体管的漏极与所述水平扫描线连接，所述第四二晶体管的漏极与所述栅极信号点连接；所述第四一晶体管的源极与所述第四二晶体管的源极与所述下拉维持模块连接；所述第四一晶体管的栅极和所述第四二晶体管的栅极分别用于接收第一控制信号和第二控制信号；在所述第四一晶体管的栅极处于高电平的情况下，控制所述第四一晶体管的源极将所述低电平信号线的信号输入到所述第四一晶体管的漏极；在所述第四二晶体管的栅极处于高电平的情况下，控制所述第四二晶体管的源极将所述低电平信号线的信号输入到所述第四二晶体管的漏极。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第六种实现当中，所述下拉维持模块包括反相器、第五一晶体管以及第五二晶体管；所述反相器的输入端与所述栅极信号点连接，所述反相器的输出端与所述第五一晶体管的栅极以及所述第五二晶体管的栅极连接；所述第五一晶体管的漏极与所述水平扫描线连接，所述第五一晶体管的源极与所述下拉模块的第三端口连接；所述第五二晶体管的漏极与所述栅极信号点连接，所述第五二晶体管的源极与所述下拉模块的第三端口连接；在所述反相器的输入端处于低电平的情况下，所述反相器的输出端向所述第五一晶体管的栅极输出高电平，控制所述低电平信号线的信号从所述第五一晶体管的源极传输出到所述五一晶体管的漏极。
结合第一方面以及上述第一方面的任意一种实现，在第一方面的第七种实现当中，所述自举模块包括第一电容；所述第一电容的一端与所述栅极信号点连接，另一端与所述水平扫描线连接。
结合第一方面的第六种实现，在第一方面的第八种实现当中，所述反相器包括第五三晶体管、第五四晶体管、第五五晶体管以及第五六晶体管；所述栅极信号点与所述第五五晶体管的栅极以及所述第五六晶体管的栅极连接；所述第五五晶体管的源极以及所述第五六晶体管的源极与所述下拉模块的第三端口连接；所述第五五晶体管的漏极与所述第五三晶体管的源极以及所述五四晶体 管的栅极连接；所述第五六晶体管的漏级与所述五四晶体管的源极、所述五一晶体管的栅极连接以及所述五二晶体管的栅极连接；所述五三晶体管的栅极、所述五三晶体管的漏极以及所述五四晶体管的漏极连接。
第二方面，本发明实施例提供了一种驱动电路，其特征在于，所述驱动电路包括多个如权利要求1-9任一项所述的栅极驱动器；所述栅极驱动器的所述信号下传模块还含有第三端口；所述栅极驱动器的所述上拉控制模块还含有第二端口；第N级栅极驱动器的所述信号下传模块的第三端口与第(N+1)级栅极驱动器的所述上拉控制模块的第二端口连接。
本发明实施例通过利用下拉模块与上拉模块共同拉低水平扫描线上的电平，可以有效改善栅极驱动器的下拉效果，提高电路的稳定性。
附图说明
为了更清楚地说明本发明实施例技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍。
图1是本发明实施例提供的一种栅极驱动器的结构示意图；
图2是本发明实施例提供的一种栅极驱动器中电压变化的示意图；
图3是本发明另一实施例提供的一种栅极驱动器的结构示意图；
图4是本发明另一实施例提供的一种栅极驱动器的结构示意图；
图5是本发明另一实施例提供的一种终端设备的示意性框图；
图6是本发明实施例提供的一种栅极驱动器中电压变化的示意图；
图7是本发明实施例提供的一种栅极驱动器的栅极信号点中的电压变化的示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
应当理解，当在本说明书和所附权利要求书中使用时，术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
还应当理解，在此本发明说明书中所使用的术语仅仅是出于描述特定实施例的目的而并不意在限制本发明。如在本发明说明书和所附权利要求书中所使用的那样，除非上下文清楚地指明其它情况，否则单数形式的“一”、“一个”及“该”意在包括复数形式。
还应当进一步理解，在本发明说明书和所附权利要求书中使用的术语“和/或”是指相关联列出的项中的一个或多个的任何组合以及所有可能组合，并且包括这些组合。
如在本说明书和所附权利要求书中所使用的那样，术语“如果”可以依据上下文被解释为“当...时”或“一旦”或“响应于确定”或“响应于检测到”。类似地，短语“如果确定”或“如果检测到[所描述条件或事件]”可以依据上下文被解释为意指“一旦确定”或“响应于确定”或“一旦检测到[所描述条件或事件]”或“响应于检测到[所描述条件或事件]”。
含有显示面板的设备中含有用于驱动显示面板的驱动电路，而驱动电路常常是由多个栅极驱动器级联而成。如图1所示，图1是本发明实施例提供的一种栅极驱动器的结构示意图。如图1中所示的栅极驱动器包括上拉控制模块1’、下拉维持模块5’、上拉模块2’、信号下传模块3’、下拉模块4’以及自举模块6’；上拉控制模块1’、下拉维持模块5’、上拉模块2’、信号下传模块3’、下拉模块4’以及自举模块6’相连，连接点为栅极信号点Q(N)；下拉维持模块5’、自举模块6’、上拉模块2’以及下拉模块4’分别与水平扫描线G(N)连接。其中，上拉控制模块1’用于为栅极信号点Q(N)预充电，上拉模块2’用于提高水平扫描线G(N)上的点电位；信号下传模块3’用于控制与该栅极驱动器连接的下一级栅极驱动器的打开与关闭；下拉模块4’用于拉低Q(N)与G(N)的电位至与低电平信号VSS一致；下拉维持单元用于控制Q(N)与G(N)的点电位维持在VSS不变；自举电容，用于提高并维持Q(N)的点电位。
当上拉控制信号ST(N-1)与G(N-1)中的信号为高电平时，上拉控制模块1’对Q(N)进行预充电，当Q(N)中的点电位达到能够驱动上拉模块2’的高电平时，上拉模块2’将时钟信号CK传输到G(N)与下一栅极驱动器的上拉控制模块1’的上拉控制信号ST(N)，当控制信号G(N+1)为高电平时，下拉模块4’将低电平信号VSS传输到G(N)，使得G(N)的电平被拉低为低电平，因此VSS信号不仅应用稳定整个栅极驱动器的稳定性，还要将处于高 电位的G(N)拉低至低电平，从而可能会出现VSS拉力不足的情况，导致与栅极驱动器无法拉低栅极线上的电位，显示面板上的栅极不能立即关闭，造成画面显示异常。
具体的，电路中信号变化如图2所示，在t1时间段，上一驱动器传输的上拉控制信号ST(N-1)与水平扫描信号G(N-1)为高电平，本质上t1时刻的ST(N-1)和G(N-1)的信号来源于上一驱动器所获得的时钟信号，因此上拉控制模块1’对Q(N)进行预充电，使得Q(N)处于高电平v1，从而上拉模块2’将上拉模块2’的第三端口获得的时钟信号线的信号从上拉模块2’的第二端口传输到水平扫描线上，使得G(N)点处于低电平；在t2时间段，由于电容耦合作用Q(N)的点电位被提高至另一更高的高电平v2，从而上拉模块2’将上拉模块2’的第三端口获得的时钟信号线的信号从上拉模块2’的第二端口传输到水平扫描线上，使得G(N)点处于高电平，因此上拉模块2’用于提高水平扫描线上的一点G(N)的点电位；在t3时间段，由于下拉模块4’获得的控制信号G(N-1)为高电平，因此下拉模块4’将下拉模块4’的第三端口获得的VSS从下拉模块4’的第一端口和第二端口分别传输到Q(N)和G(N)，使得Q(N)和G(N)处于低电平，因此下拉模块4’用于拉低水平扫描线上的一点G(N)的点电位，由此看来，VSS不仅需要稳定整个液晶面板的水平扫描线上的低电平，同时还需要将当级栅极驱动器的水平扫描线的高电平拉低为低电平，因此可能会引发栅极驱动器的拉力不足的问题，使得液晶面板的水平扫描线无法及时的被拉低，导致液晶面板显示异常。
针对以上问题，本发明实施例提供一种栅极驱动器，该栅极驱动器可有效的拉低液晶面板的栅极线上的电平，提高电路的稳定性。以下进行详细说明。
参见图3，是本发明实施例提供一种栅极驱动器的结构示意图，如图所示栅极驱动器包括上拉控制模块1、下拉维持模块5、上拉模块2、信号下传模块3、下拉模块4以及自举模块6；上拉控制模块1含有第一端口；下拉维持模块5含有第一端口、第二端口以及第三端口；上拉模块2含第一端口、第二端口以及第三端口；信号下传模块3含有第一端口以及第二端口；下拉模块4含有第一端口、第二端口、第三端口、第四端口以及第五端口；自举模块6含有第一端口以及第二端口；
上拉控制模块1的第一端口11、上拉模块2的第一端口21、信号下传模块 3的第一端口31、下拉模块4的第一端口41、下拉维持模块5的第一端口51与自举模块6的第一端口61连接，连接点为栅极信号点Q(N)；下拉维持模块5的第二端口52、下拉模块4的第二端口42、自举模块6的第二端口62以及上拉模块2的第二端口22分别与水平扫描线G(N)连接；下拉维持模块5的第三端口53以及下拉模块4的第三端口43分别与低电平信号线VSS连接；上拉模块2的第三端口23以及信号下传模块3的第二端口32分别与时钟信号线CK连接；
上拉控制模块1用于对栅极信号点Q(N)预充电，在栅极信号点Q(N)处于高电平的情况下，控制上拉模块2将时钟信号线CK的信号输出到水平扫描线G(N)；在下拉模块4的第四端口44接收到的第一控制信号G(N+1)为高电平的情况下，下拉模块4将低电平信号线的信号VSS输出到水平扫描线G(N)；在下拉模块4的第五端口45接收到的第二控制信号G(N+2)为高电平的情况下，下拉模块4将低电平信号线的信号VSS输出到栅极信号点Q(N)，控制下拉维持模块5输出低电平信号线的信号VSS到水平扫描线G(N)；自举模块6用于提高并维持栅极信号点Q(N)的电平；信号下传模块3用于在栅极信号点Q(N)为高电平的情况下，将时钟信号线的信号CK传送给其他电子器件。
可选的，第一控制信号G(N+1)与第二控制信号G(N+2)不相同。
需要说明的是，上拉控制模块1用于为栅极信号点Q(N)预充电，上拉模块2用于提高水平扫描线上的一点G(N)的点电位；信号下传模块3用于控制与该栅极驱动器连接的下一级栅极驱动器的打开与关闭；下拉模块4用于拉低Q(N)与G(N)的电位至与低电平信号VSS一致；下拉维持单元用于控制Q(N)与G(N)的点电位维持在VSS不变；自举电容，用于提高并维持Q(N)的点电位。
具体的，信号变化参见图6与图7。t1时间段内，上拉控制模块1对Q(N)进行预充达到能够驱动上拉模块2的电平v1，因此上拉模块2将时钟信号线中的信号CK传输到G(N)，使得G(N)为低电平(本质上t1时刻的上拉控制信号ST(N-1)和上一级驱动器的水平扫描线上的信号G(N-1)来源于上一驱动器所获得的时钟信号)，此时用于拉低G(N)的信号为CK；在t2时间段内，由于电容耦合作用，Q(N)中的点电位继续被提高至V2，于是上拉模块2继续将CK传输到G(N)，使得G(N)为高电平，因此上拉模块2用于提高水平 扫描线上的一点G(N)的点电位；在t3时间段内，Q(N)点由于CL信号电容耦合作用结束而被拉低至高电平V3，于是上拉模块2继续将CK传输到G(N)，使得G(N)为低电平，于此同时，第二控制信号Q(N+1)为高电平，下拉模块4将低电平信号VSS传输到G(N)，此时用于拉低G(N)的信号为CK以及VSS；在t4时间段内，第一控制信号Q(N+2)为高电平，下拉模块4将低电平信号VSS传输到Q(N)，使得下拉维持模块5的第一端口输入低电平，因此下拉维持模块5将下拉维持模块5的第三端口获得的VSS信号由下拉维持模块5的第二端口传输到G(N)，此时用于拉低G(N)的信号为VSS。
综合来看，本发明实施例提供的栅极驱动器右移通过上拉模块2以及下拉模块4共同来拉低当级栅极驱动器的水平扫描线上的电平，可以有效的改善栅极驱动器的下拉效果，提高电路的稳定性。
请参见图4，图4是在图3的基础上进一步细化得到的。图4是本发明实施例公开的一种栅极驱动器的结构性示意图。如图4所示：
可选的，上述上拉控制模块1包括：第一一晶体管T11；第一一晶体管T11的源极11与栅极信号点Q(N)连接；在第一一晶体管T11的栅极处于高电平的情况下，控制第一一晶体管T11的漏极将接收到的信号输入到第一一晶体管的源极11。
可选的，上述上拉电路包括第二一晶体管T21；第二一晶体管T21的栅极21与栅极信号点Q(N)连接；第二一晶体管T21的漏极23与信号下传模块3的第二端口32连接；第二一晶体管T11的源极22与水平扫描线G(N)连接；在第二一晶体管T21的栅极21处于高电平的情况下，控制第二一晶体管T21的漏极23将时钟信号线的信号CK输入到第二一晶体管T21的源极22。
可选的，上述信号下传模块3包括第三一晶体管T31；第三一晶体管T31的栅极31与栅极信号点Q(N)连接；第三一晶体管T31的漏极32与上拉模块2的第三端口23连接；在第三一晶体管T31的栅极31处于高电平的情况下，控制第三一晶体管T31的漏极32将时钟信号线的信号CK输入到第三一晶体管T31的源极33。
可选的，上述下拉模块4包括第四一晶体管T41以及第四二晶体管T42；第四一晶体管的漏极42与水平扫描线G(N)连接，第四二晶体管T42的漏极41与栅极信号点Q(N)连接；第四一晶体管的源极43与第四二晶体管的源极 43与下拉维持模块5连接；第四一晶体管的栅极和第四二晶体管的栅极分别用于接收第一控制信号G(N+1)和第二控制信号G(N+2)；在第四一晶体管的栅极处于高电平的情况下，控制第四一晶体管T41的源极43将低电平信号线VSS的信号输入到第四一晶体管T41的漏极42；在第四二晶体管的栅极接收到高电平的情况下，控制第四二晶体管T42的源极43将低电平信号线VSS的信号输入到第四二晶体管T42的漏极41。
可选的，上述下拉维持模块5包括反相器、第五一晶体管T51以及第五二晶体管T52；反相器的输入端51与栅极信号点Q(N)连接，反相器的输出端与第五一晶体管T51的栅极以及第五二晶体管T52的栅极连接；第五一晶体管T51的漏极52与水平扫描线G(N)连接，第五一晶体管T51的源极与下拉模块4的第三端口43连接；第五二晶体管T52的漏极51与栅极信号点Q(N)连接，第五二晶体管T52的源极53与下拉模块4的第三端口43连接；在反相器的输入端处于低电平的情况下，反相器的输出端向第五一晶体管T51的栅极输出高电平，控制低电平信号线的信号VSS从第五一晶体管T51的源极53传输出到五一晶体管T51的漏极52。
进一步的，如图5所示，上述反相器包括第五三晶体管T53、第五四晶体管T54、第五五晶体管T55以及第五六晶体管T56；栅极信号点Q(N)与第五五晶体管T55的栅极以及第五六晶体管T56的栅极连接；第五五晶体管T55的源极以及第五六晶体管T56的源极与下拉模块4的第三端口43连接；第五五晶体管T55的漏极与第五三晶体管T53的源极以及五四晶体管T54的栅极连接；第五六晶体管T56的漏级与五四晶体管T54的源极、五一晶体管T51的栅极连接以及五二晶体管T52的栅极连接；五三晶体管T53的栅极、五三晶体管T53的漏极以及五四晶体管T54的漏极连接。其中，下拉维持模块的第五四晶体管的漏极输入端LC为直流的高电平信号。XCK为时钟信号CK的反向信号。
可选的，上述自举模块6包括第一电容；第一电容的一端与栅极信号点Q(N)连接，另一端与水平扫描线G(N)连接。
具体的，信号变化参见图6与图7。t1时间段内，上一驱动器传输的上拉控制信号ST(N-1)与水平扫描信号G(N-1)为高电平，因此使得上拉控制模块1的第一一晶体管T11的栅极处于高电平，控制ST(N-1)信号输出到Q(N)，从而对Q(N)进行预充达到能够驱动上拉模块2的第二一晶体管T21的栅极的 电平V1，因此上拉模块2的第二一晶体管T21将时钟信号CK，从第二一晶体管T21的漏极传输到源极，即输出到水平扫描线上的G(N)点，使得G(N)为低电平；在t2时间段内，由于电容耦合作用，Q(N)中的点电位继续被提高至V2，于是上拉模块2的第二一晶体管T21继续将CK传输到G(N)，使得G(N)为高电平；在t3时间段内，Q(N)点由于CK信号的电容耦合作用结束而被拉低至高电平V3，于是上拉模块2的第二一晶体管T21继续将CK传输到G(N)，使得G(N)为低电平，于此同时，第二控制信号G(N+1)为高电平，控制下拉模块4的第四一晶体管T41将低电平信号VSS传输到G(N)，此时用于拉低G(N)的信号为CK以及VSS；在t4时间段内，第一控制信号G(N+2)为高电平，控制下拉模块4的第四二晶体管T42将电平信号VSS传输到Q(N)，使得反相器的输入端口输入低电平，因此下拉维持模块5的反相器输出高电平至第五一晶体管的栅极，使得第五一晶体管将源极的获得的VSS信号由第五一晶体管的漏极传输到G(N)，此时用于拉低G(N)的信号为VSS。
综上可以看出，本发明实施例所描述的栅极驱动器通过低电平信号VSS与时钟信号CK共同来拉低栅极信号点Q(N)上的电位，可以改善栅极驱动器的下拉效果，提高电路的稳定性。
本发明实施例还提供了包含多个上述发明实施例所描述的栅极驱动器的驱动电路，上述栅极驱动器的信号下传模块3还含有第三端口33；栅极驱动器的上拉控制模块1还含有第二端口12；第N级栅极驱动器的信号下传模块3的第三端口与第(N+1)级栅极驱动器的上拉控制模块1的第二端口连接。

Claims (10)

  1. 一种栅极驱动器，其特征在于，包括上拉控制模块、下拉维持模块、上拉模块、信号下传模块、下拉模块以及自举模块；所述上拉控制模块含有第一端口；所述下拉维持模块含有第一端口、第二端口以及第三端口；所述上拉模块含第一端口、第二端口以及第三端口；所述信号下传模块含有第一端口以及第二端口；所述下拉模块含有第一端口、第二端口、第三端口、第四端口以及第五端口；所述自举模块含有第一端口以及第二端口；
    所述上拉控制模块的第一端口、所述上拉模块的第一端口、所述信号下传模块的第一端口、所述下拉模块的第一端口、所述下拉维持模块的第一端口与所述自举模块的第一端口连接，连接点为栅极信号点；所述下拉维持模块的第二端口、所述下拉模块的第二端口、所述自举模块的第二端口以及所述上拉模块的第二端口分别与水平扫描线连接；所述下拉维持模块的第三端口以及所述下拉模块的第三端口分别与低电平信号线连接；所述上拉模块的第三端口以及所述信号下传模块的第二端口分别与时钟信号线连接；
    所述上拉控制模块用于对所述栅极信号点预充电，在所述栅极信号点处于高电平的情况下，控制所述上拉模块将所述时钟信号线的信号输出到所述水平扫描线；在所述下拉模块的第四端口接收到的第一控制信号为高电平的情况下，所述下拉模块将所述低电平信号线的信号输出到所述水平扫描线；在所述下拉模块的第五端口接收到的第二控制信号为高电平的情况下，所述下拉模块将所述低电平信号线的信号输出到所述栅极信号点，控制所述下拉维持模块输出所述低电平信号线的信号到所述水平扫描线；所述自举模块用于提高并维持所述栅极信号点的电平；所述信号下传模块用于在所述栅极信号点为高电平的情况下，将所述时钟信号线的信号传送给其他电子器件。
  2. 根据权利要求1所述的栅极驱动器，其特征在于，所述第一控制信号与所述第二控制信号不相同。
  3. 根据权利要求1所述的栅极驱动器，其特征在于，所述上拉控制模块包 括：第一一晶体管；
    所述第一一晶体管的源极与所述栅极信号点连接；
    在所述第一一晶体管的栅极处于高电平的情况下，控制所述第一一晶体管的漏极将接收到的信号输入到所述第一一晶体管的源极。
  4. 根据权利要求1所述的栅极驱动器，其特征在于，所述上拉电路包括第二一晶体管；
    所述第二一晶体管的栅极与所述栅极信号点连接；所述第二一晶体管的漏极与所述信号下传模块的第二端口连接；所述第二一晶体管的源极与所述水平扫描线连接；
    在所述第二一晶体管的栅极处于高电平的情况下，控制所述第二一晶体管的漏极将所述时钟信号线的信号输入到所述第二一晶体管的源极。
  5. 根据权利要求1所述的栅极驱动器，其特征在于，所述信号下传模块包括第三一晶体管；
    所述第三一晶体管的栅极与所述栅极信号点连接；所述第三一晶体管的漏极与所述上拉模块的第三端口连接；
    在所述第三一晶体管的栅极处于高电平的情况下，控制所述第三一晶体管的漏极将所述时钟信号线的信号输入到所述第三一晶体管的源极。
  6. 根据权利要求1所述的栅极驱动器，其特征在于，所述下拉模块包括第四一晶体管以及第四二晶体管；
    所述第四一晶体管的漏极与所述水平扫描线连接，所述第四二晶体管的漏极与所述栅极信号点连接；所述第四一晶体管的源极与所述第四二晶体管的源极与所述下拉维持模块连接；所述第四一晶体管的栅极和所述第四二晶体管的栅极分别用于接收所述第一控制信号和所述第二控制信号；
    在所述四一晶体管的栅极处于高电平的情况下，控制所述第四一晶体管的源极将所述低电平信号线的信号输入到所述第四一晶体管的漏极；在所述第四二晶体管的栅极处于高电平的情况下，控制所述第四二晶体管的源极将所述低电平信号线的信号输入到所述第四二晶体管的漏极。
  7. 根据权利要求1所述的栅极驱动器，其特征在于，所述下拉维持模块包括反相器、第五一晶体管以及第五二晶体管；
    所述反相器的输入端与所述栅极信号点连接，所述反相器的输出端与所述第五一晶体管的栅极以及所述第五二晶体管的栅极连接；所述第五一晶体管的漏极与所述水平扫描线连接，所述第五一晶体管的源极与所述下拉模块的第三端口连接；所述第五二晶体管的漏极与所述栅极信号点连接，所述第五二晶体管的源极与所述下拉模块的第三端口连接；
    在所述反相器的输入端处于低电平的情况下，所述反相器的输出端向所述第五一晶体管的栅极输出高电平，控制所述低电平信号线的信号从所述第五一晶体管的源极传输出到所述五一晶体管的漏极。
  8. 根据权利要求1所述的栅极驱动器，其特征在于，所述自举模块包括第一电容；
    所述第一电容的一端与所述栅极信号点连接，另一端与所述水平扫描线连接。
  9. 根据权利要求7所述的栅极驱动器，其特征在于，所述反相器包括第五三晶体管、第五四晶体管、第五五晶体管以及第五六晶体管；
    所述栅极信号点与所述第五五晶体管的栅极以及所述第五六晶体管的栅极连接；所述第五五晶体管的源极以及所述第五六晶体管的源极与所述下拉模块的第三端口连接；所述第五五晶体管的漏极与所述第五三晶体管的源极以及所述五四晶体管的栅极连接；所述第五六晶体管的漏级与所述五四晶体管的源极、所述五一晶体管的栅极连接以及所述五二晶体管的栅极连接；所述五三晶体管的栅极、所述五三晶体管的漏极以及所述五四晶体管的漏极连接。
  10. 一种驱动电路，其特征在于，所述驱动电路包括多个如权利要求1-9任一项所述的栅极驱动器；所述栅极驱动器的所述信号下传模块还含有第三端口；所述栅极驱动器的所述上拉控制模块还含有第二端口；
    第N级栅极驱动器的所述信号下传模块的第三端口与第(N+1)级栅极驱 动器的所述上拉控制模块的第二端口连接。
PCT/CN2018/072888 2017-12-26 2018-01-16 一种栅极驱动器及驱动电路 WO2019127694A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US16/003,532 US20190197973A1 (en) 2017-12-26 2018-06-08 Gate driver and driving circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201711439365.4A CN107978290A (zh) 2017-12-26 2017-12-26 一种栅极驱动器及驱动电路
CN201711439365.4 2017-12-26

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US16/003,532 Continuation US20190197973A1 (en) 2017-12-26 2018-06-08 Gate driver and driving circuit

Publications (1)

Publication Number Publication Date
WO2019127694A1 true WO2019127694A1 (zh) 2019-07-04

Family

ID=62007885

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/072888 WO2019127694A1 (zh) 2017-12-26 2018-01-16 一种栅极驱动器及驱动电路

Country Status (2)

Country Link
CN (1) CN107978290A (zh)
WO (1) WO2019127694A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109064981B (zh) * 2018-07-20 2019-09-17 深圳市华星光电技术有限公司 Goa电路及包括其的显示面板和显示装置
CN108831400A (zh) * 2018-07-26 2018-11-16 深圳市华星光电技术有限公司 包括goa电路的液晶面板及其驱动方法
CN109119041B (zh) * 2018-09-25 2020-05-22 深圳市华星光电技术有限公司 Goa电路结构
CN109192157A (zh) * 2018-09-26 2019-01-11 深圳市华星光电技术有限公司 Goa电路及显示装置
CN109243356A (zh) * 2018-10-23 2019-01-18 惠科股份有限公司 驱动电路、显示装置及显示装置的驱动方法
CN109300445B (zh) * 2018-12-05 2021-11-30 惠科股份有限公司 阵列基板行驱动电路及显示装置
CN110349536B (zh) * 2019-04-08 2021-02-23 深圳市华星光电半导体显示技术有限公司 Goa电路及显示面板
CN110223648B (zh) * 2019-05-09 2020-07-10 深圳市华星光电半导体显示技术有限公司 用于显示屏的驱动电路
CN110223651B (zh) * 2019-05-31 2020-08-11 深圳市华星光电半导体显示技术有限公司 一种goa电路
CN110415648A (zh) * 2019-07-16 2019-11-05 深圳市华星光电半导体显示技术有限公司 Goa电路
CN111508417A (zh) * 2020-05-06 2020-08-07 Tcl华星光电技术有限公司 Goa电路

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104700899A (zh) * 2015-01-28 2015-06-10 友达光电股份有限公司 移位寄存器电路
CN105161060A (zh) * 2015-08-18 2015-12-16 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105280153A (zh) * 2015-11-24 2016-01-27 深圳市华星光电技术有限公司 一种栅极驱动电路及其显示装置
CN106157916A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 一种栅极驱动单元及驱动电路
CN106205458A (zh) * 2016-08-30 2016-12-07 深圳市华星光电技术有限公司 一种goa驱动单元
CN106652936A (zh) * 2016-12-09 2017-05-10 深圳市华星光电技术有限公司 Goa电路及显示装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104766581B (zh) * 2015-04-27 2017-05-31 深圳市华星光电技术有限公司 Goa电路修复方法
CN104992682B (zh) * 2015-07-03 2017-10-24 深圳市华星光电技术有限公司 一种扫描驱动电路
CN107221280B (zh) * 2017-07-04 2018-01-30 深圳市华星光电半导体显示技术有限公司 扫描驱动电路及显示装置
CN107369421A (zh) * 2017-08-16 2017-11-21 深圳市华星光电半导体显示技术有限公司 一种goa电路及液晶显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104700899A (zh) * 2015-01-28 2015-06-10 友达光电股份有限公司 移位寄存器电路
CN105161060A (zh) * 2015-08-18 2015-12-16 深圳市华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105280153A (zh) * 2015-11-24 2016-01-27 深圳市华星光电技术有限公司 一种栅极驱动电路及其显示装置
CN106205458A (zh) * 2016-08-30 2016-12-07 深圳市华星光电技术有限公司 一种goa驱动单元
CN106157916A (zh) * 2016-08-31 2016-11-23 深圳市华星光电技术有限公司 一种栅极驱动单元及驱动电路
CN106652936A (zh) * 2016-12-09 2017-05-10 深圳市华星光电技术有限公司 Goa电路及显示装置

Also Published As

Publication number Publication date
CN107978290A (zh) 2018-05-01

Similar Documents

Publication Publication Date Title
WO2019127694A1 (zh) 一种栅极驱动器及驱动电路
US10235958B2 (en) Gate driving circuits and liquid crystal devices
US9905182B2 (en) GOA driving circuits, TFT display panels and display devices
US10665191B2 (en) Shift register and driving method therefor, and display device
US7688934B2 (en) Shift register and shift register unit for diminishing clock coupling effect
US10121442B2 (en) Driving methods and driving devices of gate driver on array (GOA) circuit
US20160172054A1 (en) Shift register unit, its driving method, shift register and display device
US20160225336A1 (en) Shift register unit, its driving method, gate driver circuit and display device
US20200020291A1 (en) Shift Register Circuit, Method for Driving the Same, Gate Drive Circuit, and Display Panel
US10152940B2 (en) GOA driver circuit and liquid crystal display
US9928797B2 (en) Shift register unit and driving method thereof, gate driving apparatus and display apparatus
US20180226132A1 (en) Shift register and operation method thereof
TWI404036B (zh) 液晶顯示器
US20190005866A1 (en) Shift Register Unit, Driving Method, Gate Driver on Array and Display Device
WO2016107096A1 (zh) 移位寄存器单元及驱动方法、栅极驱动电路及显示器件
WO2019174061A1 (zh) 一种阵列基板行驱动单元、电路以及液晶显示面板
US9704437B2 (en) Gate driving circuit, array substrate, and display device
WO2018120336A1 (zh) Goa栅极驱动电路以及液晶显示装置
WO2020019426A1 (zh) 包括goa电路的液晶面板及其驱动方法
WO2016000369A1 (zh) 发射电极扫描电路、阵列基板和显示装置
US10204586B2 (en) Gate driver on array (GOA) circuits and liquid crystal displays (LCDs)
WO2018129928A1 (zh) 移位寄存器电路及其驱动方法、栅极驱动电路和显示装置
US20190051262A1 (en) Amoled pixel driving circuit and pixel driving method
WO2018040484A1 (zh) 一种栅极驱动电路
WO2020224133A1 (zh) 一种goa电路、显示面板及显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18896748

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18896748

Country of ref document: EP

Kind code of ref document: A1