WO2019114116A1 - 适用于35GHz交流频率下工作的GaN整流器及其制备方法 - Google Patents

适用于35GHz交流频率下工作的GaN整流器及其制备方法 Download PDF

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WO2019114116A1
WO2019114116A1 PCT/CN2018/074684 CN2018074684W WO2019114116A1 WO 2019114116 A1 WO2019114116 A1 WO 2019114116A1 CN 2018074684 W CN2018074684 W CN 2018074684W WO 2019114116 A1 WO2019114116 A1 WO 2019114116A1
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gan
epitaxial wafer
rectifier
gan rectifier
contact electrode
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PCT/CN2018/074684
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French (fr)
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王文樑
李国强
李筱婵
李媛
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华南理工大学
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Priority to SG11202004696SA priority Critical patent/SG11202004696SA/en
Priority to US16/769,157 priority patent/US11257935B2/en
Publication of WO2019114116A1 publication Critical patent/WO2019114116A1/zh

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Definitions

  • the present invention relates to a rectifier, and more particularly to a GaN rectifier suitable for operation at an AC frequency of 35 GHz and a method of fabricating the same.
  • the third-generation nitride semiconductor materials represented by GaN have wider band gap, higher critical breakdown electric field, higher ultimate operating temperature and saturated electron mobility. It means that GaN rectifier devices are more suitable for high voltage and high frequency operation than Si-based rectifier thyristors.
  • the superior thermal conductivity characteristics give GaN rectifiers a wider application prospect and stable performance in miniaturization and integration applications. Sex. Therefore, the implementation of GaN rectifiers operating at 35 GHz high AC frequency has revolutionary significance and social application value.
  • an object of the present invention is to provide a method for preparing a GaN rectifier suitable for operation at an AC frequency of 35 GHz, which has the advantages of being highly compatible and easy to implement with existing production methods. advantage.
  • a method for preparing a GaN rectifier operating at an AC frequency of 35 GHz comprising the following steps:
  • the epitaxial wafer of the GaN rectifier obtained in the step (1) is sequentially subjected to ultrasonic treatment in acetone, deionized water and anhydrous ethanol, and then taken out and washed with deionized water and then dried with hot high-purity nitrogen;
  • step (3) performing a Schottky contact electrode pattern lithography preparation on the GaN rectifier epitaxial wafer obtained in the step (2): uniformly coating the photoresist on the epitaxial wafer of the GaN rectifier obtained in the step (2) by spin coating, and coating the photoresist
  • the GaN rectifier epitaxial wafer is prebaked, then placed in a lithography machine for exposure, and finally the exposed epitaxial wafer is immersed in a developing solution for photolithographic development and cleaning;
  • the GaN rectifier epitaxial wafer engraved with the ohmic contact electrode corresponding pattern groove obtained in the step (4) is placed in an electron beam evaporation device, and the evaporation chamber is evacuated, and then the Schottky contact electrode metal is sequentially evaporated, and steamed. After the plating is finished, the GaN rectifier epitaxial wafer is annealed;
  • the GaN rectifier epitaxial wafer is immersed in the degumming solution and then removed, and the photoresist and the vapor-deposited metal remaining on the surface of the GaN rectifier epitaxial wafer are ultrasonically removed by using deionized water, and then deionized water is removed after ultrasonication. Wash and then dry with hot high purity nitrogen;
  • step (3) aligning the epitaxial wafer of the GaN rectifier through the alignment mark in the mask, repeating the process of step (3), photolithographically developing at the corresponding position, preparing the ohmic contact electrode pattern of the device and cleaning;
  • ohmic contact electrode preparation for the GaN rectifier epitaxial wafer the GaN rectifier epitaxial wafer obtained by photolithographic development of the ohmic contact electrode pattern obtained in the step (7) is placed in an electron beam evaporation apparatus, and the evaporation chamber is evacuated, followed by steaming. An ohmic contact electrode metal is plated, and after the evaporation is completed, the GaN rectifier epitaxial wafer is annealed;
  • step (9) repeating the step (6), removing the residual photoresist and the vapor-deposited metal on the surface of the GaN epitaxial wafer by removing the glue and ultrasonic cleaning;
  • step (12) using the wet etching method, etching the exposed SiNx, and finally repeating the step (6) process, removing the residual photoresist and silicon nitride on the surface of the GaN rectifier epitaxial wafer by removing the glue and ultrasonic cleaning. Passivation layer and cleaning;
  • Membrane isolation passivation layer fabrication the GaN rectifier epitaxial wafer obtained in step (14) is placed in a plasma-assisted chemical weather deposition apparatus, and the step (10) process is repeated to deposit SiN in the GaN rectifier epitaxial wafer etching recess. x passivation layer;
  • step (12) using the step (12) wet etching process to remove the excess SiN x layer on the surface of the GaN rectifier epitaxial wafer after the step (15), using the step (6) process, removing the GaN rectifier epitaxial by immersion and ultrasonic cleaning.
  • the surface of the sheet remains SiN x and the photoresist; finally, a GaN rectifier chip suitable for operation at an AC frequency of 35 GHz is fabricated on a silicon substrate.
  • the silicon substrate according to the step (1) has an (111) close-packed surface as an epitaxial surface
  • the InGaN films are all oriented in the (0001) direction.
  • the ultrasonic treatment time of step (2) and step (6) is 3 to 15 minutes.
  • the thickness of the photoresist in the step (3) is 0.2 to 0.7 ⁇ m; the exposure time is 1 to 4 s; and the development time is 45 to 95 s.
  • the depth of the groove in the step (4) is 150 to 400 nm.
  • the vacuum degree of the vacuum in steps (5) and (8) is 1 to 5 ⁇ 10 -5 Pa; the annealing temperatures in steps (5) and (8) are both 450 to 800 ° C, and the annealing time is Both are 30 to 120 minutes.
  • the soaking time in step (6) is 45 to 100 min.
  • the deposition time of the SiN x passivation layer in the step (10) and the step (15) is 60 to 120 min.
  • the depth of the groove in the step (14) is 1 to 2.5 ⁇ m.
  • a GaN rectifier suitable for operation at an AC frequency of 35 GHz is prepared by the method of preparing a GaN rectifier suitable for operation at an AC frequency of 35 GHz.
  • the present invention has the following advantages and benefits:
  • the invention realizes the preparation of a high frequency (35 GHz) GaN rectifier, and adopts a T-gate design scheme in the design part of the Schottky contact electrode structure, which can effectively improve the gate control characteristics of the rectifying device and effectively reduce the working process of the rectifying device.
  • the current concentration effect improves the performance stability of the rectifier device under high power operation.
  • the present invention uses a group III nitride represented by GaN as a basic material of a rectifier, and can better realize a device in a higher frequency application by relying on a material superiority of a group III nitride compared with a conventional Si material. Miniaturization and integration.
  • the present invention uses an N-polar surface group III nitride as a device substrate material, which can effectively enhance the two-dimensional electron gas threshold at the interface of the AlGaN/GaN heterojunction compared to the conventional metal polar surface group III nitride.
  • Sexuality and enhanced device gate control easy to fabricate enhanced rectifier devices that are more suitable for operation at 35 GHz AC frequency.
  • the present invention selects the Si material which is most commonly used in an integrated circuit as a device epitaxial substrate, and is easy to implement device integration applications.
  • Example 1 is a schematic cross-sectional view showing a GaN rectifier chip produced in Example 1 of the present invention.
  • Fig. 2 is a GaN (0002) X-ray rocking curve diagram of Example 1 of the present invention.
  • Fig. 3 is a chart showing the atomic force microscopy of the surface topography of the GaN epitaxial wafer of Example 1 of the present invention.
  • a method for preparing a GaN rectifier chip suitable for operation at an AC frequency of 35 GHz on a silicon substrate of the present embodiment :
  • a GaN rectifier epitaxial wafer is grown on a silicon substrate by a metal organic chemical vapor deposition technique, including an N-polar GaN buffer layer 2 grown on a silicon substrate 1, grown in an N polarity.
  • the carbon-doped semi-insulating N-polar GaN layer 3 on the GaN buffer layer 2 has a doping concentration of 5.9 ⁇ 10 18 cm ⁇ 3 and is grown on the carbon-doped semi-insulating N-polar GaN film 3 .
  • the GaN buffer layer has a thickness of 800 nm;
  • the carbon-doped GaN layer has a thickness 4 of 100 nm;
  • the undoped AlGaN layer has a thickness of 450 nm; and the undoped GaN layer
  • the thickness is 500 nm; the thickness of the undoped InGaN layer is 150 nm.
  • GaN rectifier epitaxial wafers were sequentially ultrasonicated in acetone, absolute ethanol, and deionized water for 3 min, removed by deionized water, and the washed GaN rectifier epitaxial wafer was dried with hot high-purity nitrogen.
  • the photoresist coated epitaxial wafer is pre-baked on a hot stage for 45s, then coated with light
  • the engraved epitaxial wafer is placed in a lithography machine for exposure, the exposure time is 3 s, and then the exposed epitaxial wafer is immersed in a positive developing solution, the developer type is RZX3038, the immersion time is 60 s, and finally the development is completed.
  • the epitaxial wafer was taken out, rinsed with deionized water and dried with hot high-purity nitrogen, and baked on a hot plate for baking for 45 s.
  • the GaN rectifier epitaxial wafer is placed in a reactive ion etching machine to perform reactive ion etching on the pattern of the Schottky contact electrode 8 exposed by the lithography to etch the groove corresponding to the pattern, and the groove depth It is 200 nm.
  • Preparing the Schottky contact electrode 8 for the GaN rectifier epitaxial wafer placing the epitaxial wafer of the GaN rectifier after the reactive ion etching into an electron beam evaporation device, and pumping the cavity vacuum to 1 ⁇ 10 -5 Pa Then, the electrode metal MoS 2 /Ni/Au was sequentially evaporated, and after the vapor deposition was completed, the GaN rectifier epitaxial wafer was annealed at an annealing temperature of 500 ° C and an annealing time of 60 min.
  • the GaN rectifier epitaxial wafer prepared with the ohmic electrode was immersed in the degumming solution for 60 minutes, rinsed out, rinsed with deionized water and placed in acetone for 5 min, taken out, rinsed with deionized water and dried with hot nitrogen. .
  • step (6) is repeated, and the photoresist remaining on the surface of the GaN epitaxial wafer and the vapor-deposited metal are removed by immersion and ultrasonic cleaning.
  • Membrane isolation pattern etching repeating the step (4) process, using the reactive ion etching apparatus, the surface of the epitaxial wafer of the GaN rectifier obtained in the step (13) is groove-etched, the etching depth is 2 ⁇ m, and the etching is completed. Rinse the surface of the epitaxial wafer with deionized water and blow dry with hot nitrogen;
  • Step (10) is repeated to deposit a SiN x passivation layer in the etched recess of the GaN rectifier epitaxial wafer. 60min;
  • the GaN rectifier epitaxial wafer After removing the excess SiN x layer on the surface by the step (12) wet etching process, the residual SiN x and the photoresist on the surface of the GaN rectifier epitaxial wafer are removed by the immersion and ultrasonic cleaning using the step (6) process. Finally, a GaN rectifier chip suitable for operation at an AC frequency of 35 GHz on a silicon substrate was fabricated.
  • the GaN rectifier structure obtained in this embodiment is shown in FIG. 1.
  • the GaN (0002) X-ray rocking curve of the GaN film is as shown in FIG. 2, and the FWHM is 0.0096.
  • the atomic force microscopy of the surface morphology of GaN epitaxial wafers is shown in Fig. 3.
  • the surface microscopic morphology shows a smooth laminar flow structure with a surface roughness of RMS ⁇ 0.9 angstroms, and the surface morphology and crystal quality are very good.
  • a method for preparing a GaN rectifier chip suitable for operation at an AC frequency of 35 GHz on a silicon substrate of the present embodiment :
  • a GaN rectifier epitaxial wafer is grown on a silicon substrate by a metal organic chemical vapor deposition technique, including an N-polar GaN buffer layer grown on a silicon substrate, and carbon doped on the N-polar GaN buffer layer.
  • a hetero-insulating N-polar GaN layer having a doping concentration of 5.9 ⁇ 10 18 cm ⁇ 3 and an undoped N-polar AlGaN layer grown on a carbon-doped semi-insulating N-polar GaN film
  • the thickness is 600 nm; the carbon-doped GaN layer has a thickness of 150 nm; the undoped AlGaN layer has a thickness of 300 nm; the undoped GaN layer has a thickness of 400 nm; and the undoped InGaN layer
  • GaN rectifier epitaxial wafers were sequentially ultrasonicated in acetone, absolute ethanol, and deionized water for 3 min, removed by deionized water, and the washed GaN rectifier epitaxial wafer was dried with hot high-purity nitrogen.
  • the photoresist coated epitaxial wafer is pre-baked on a hot stage for 45s, then coated with light
  • the engraved epitaxial wafer is placed in a lithography machine for exposure, the exposure time is 1 s, and then the exposed epitaxial wafer is immersed in a positive developing solution, the developer type is RZX3038, the immersion time is 30 s, and finally the development is completed.
  • the epitaxial wafer was taken out, rinsed with deionized water and dried with hot high-purity nitrogen, and baked on a hot plate for baking for 45 s.
  • the GaN rectifier epitaxial wafer is placed in a reactive ion etching machine, and the Schottky contact electrode pattern exposed by the lithography is subjected to reactive ion etching to etch a groove corresponding to the pattern, and the groove depth is 200nm.
  • Schottky contact electrode preparation for epitaxial wafer of GaN rectifier the epitaxial wafer of the GaN rectifier after reactive ion etching is placed in an electron beam evaporation device, and the vacuum degree of the cavity is pumped to 3 ⁇ 10 -5 Pa, Subsequently, the electrode metal MoS 2 /Ni/Au was sequentially evaporated, and after the vapor deposition was completed, the GaN rectifier epitaxial wafer was annealed at an annealing temperature of 800 ° C and an annealing time of 120 min.
  • the GaN rectifier epitaxial wafer prepared with the ohmic electrode was immersed in the degumming solution for 45 minutes, rinsed out, rinsed with deionized water and placed in acetone for 5 min, taken out, rinsed with deionized water and dried with hot nitrogen. .
  • GaN rectifier epitaxial wafer prepared with device ohmic contact pattern is placed in an electron beam evaporation device, and the cavity vacuum is pumped to 1 ⁇ 10 -5 Pa Then, the ohmic contact electrode material Ti/Al/Ni/Au was sequentially vapor-deposited, and after the vapor deposition was completed, the GaN rectifier epitaxial wafer was annealed at an annealing temperature of 800 ° C and an annealing time of 120 min.
  • step (6) is repeated, and the photoresist remaining on the surface of the GaN epitaxial wafer and the vapor-deposited metal are removed by immersion and ultrasonic cleaning.
  • Step (10) is repeated to deposit a SiN x passivation layer in the etched recess of the GaN rectifier epitaxial wafer. 90min;
  • step (12) using the step (12) wet etching process to remove the excess SiN x layer on the surface of the GaN rectifier epitaxial wafer after the step (15), using the step (6) process, removing the GaN rectifier epitaxial by immersion and ultrasonic cleaning.
  • the surface of the sheet remains SiN x and photoresist.
  • a method for preparing a GaN rectifier chip suitable for operation at an AC frequency of 35 GHz on a silicon substrate of the present embodiment :
  • a GaN rectifier epitaxial wafer is grown on a silicon substrate by a metal organic chemical vapor deposition technique, including an N-polar GaN buffer layer grown on a silicon substrate, and carbon doped on the N-polar GaN buffer layer.
  • a hetero-insulating N-polar GaN layer having a doping concentration of 5.9 ⁇ 10 18 cm ⁇ 3 and an undoped N-polar AlGaN layer grown on a carbon-doped semi-insulating N-polar GaN film
  • the thickness is 850 nm;
  • the carbon-doped GaN layer has a thickness of 200 nm;
  • the undoped AlGaN layer has a thickness of 450 nm;
  • the undoped GaN layer has a thickness of 650 nm; and
  • GaN rectifier epitaxial wafers were sequentially ultrasonicated in acetone, absolute ethanol, and deionized water for 3 min, removed by deionized water, and the washed GaN rectifier epitaxial wafer was dried with hot high-purity nitrogen.
  • the photoresist coated epitaxial wafer is pre-baked on a hot stage for 45s, then coated with light
  • the engraved epitaxial wafer is placed in a lithography machine for exposure, and the exposure time is 4 s.
  • the exposed epitaxial wafer is immersed in a positive developing solution, the developer type is RZX3038, the immersion time is 30 s, and finally the development is completed.
  • the epitaxial wafer was taken out, rinsed with deionized water and dried with hot high-purity nitrogen, and baked on a hot plate for baking for 45 s.
  • the GaN rectifier epitaxial wafer is placed in a reactive ion etching machine, and the Schottky contact electrode pattern exposed by the lithography is subjected to reactive ion etching to etch a groove corresponding to the pattern, and the groove depth is 400nm.
  • the GaN rectifier epitaxial wafer prepared with the ohmic electrode was immersed in the degumming solution for 100 min, rinsed out, rinsed with deionized water and placed in acetone for 15 min, taken out, rinsed with deionized water and dried with hot nitrogen. .
  • ohmic contact electrode preparation for lithographic epitaxial wafer after photolithography GaN rectifier epitaxial wafer prepared with device ohmic contact pattern is placed in an electron beam evaporation device, and the cavity vacuum is pumped to 1 ⁇ 10 -5 Pa Then, the ohmic contact electrode substance Ti/Al/Ni/Au is sequentially evaporated.
  • step (6) is repeated, and the photoresist remaining on the surface of the GaN epitaxial wafer and the vapor-deposited metal are removed by immersion and ultrasonic cleaning.
  • step (3) repeating the step (3), preparing a mask on the surface of the GaN epitaxial wafer by photolithographic development, exposing the ohmic contact electrode and the SiN x on the Schottky contact electrode pattern;
  • Step (10) is repeated to deposit a SiN x passivation layer in the etched recess of the GaN rectifier epitaxial wafer. 120min;
  • step (12) using the step (12) wet etching process to remove the excess SiN x layer on the surface of the GaN rectifier epitaxial wafer after the step (15), using the step (6) process, removing the GaN rectifier epitaxial by immersion and ultrasonic cleaning.
  • the surface of the sheet remains SiN x and photoresist.

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Abstract

一种适用于35GHz交流频率下工作的GaN整流器的制备方法：在硅衬底（1）上依次生长N极性面GaN缓冲层（2）、碳掺杂半绝缘化N极性面GaN层（3）、非掺杂N极性面AlGaN层（4）、非掺杂N极性面GaN层（5）和非掺杂N极性面InGaN薄膜（6），得到整流器外延片；在GaN整流器外延片上制备肖特基接触电极（8）图案凹槽，并在凹槽中沉积肖特基接触电极；制备欧姆接触电极（9）图案，并在外延片表面沉积器件欧姆接触电极；随后在外延片表面无电极部分沉积氮化硅钝化层（7），制备表面电极区域；最后再对GaN整流器外延片进行台面隔离处理。该制备方法实现了高频GaN整流器的制备，提高整流器件在大功率工作下的性能稳定性。

Description

适用于35GHz交流频率下工作的GaN整流器及其制备方法 技术领域
本发明涉及整流器，特别涉及适用于35GHz交流频率下工作的GaN整流器及其制备方法。
背景技术
整流器作为一种在国防、传能等领域具有重要作用的功率电子元器件而备受各界关注。传统的Si基整流晶闸管由于材料本身禁带宽度窄、电子饱和迁移速率低、热导系数低等缺点，造成器件体积大、反向漏电流大、中频工作条件下发热严重，性能稳定性等问题，难以满足日益增长的器件小型化、集成化、高频化需求，因此急需开发一种能应用与高频领域并同时满足器件小型化、集成化应用需求的新一代整流器件。关于以GaN为代表的III族氮化物整流器的研究由此兴起。以GaN为代表的第三代氮化物半导体材料相比于传统Si基材料，具有更宽的禁带宽度、更高的临界击穿电场、更高的极限工作温度与饱和电子迁移率等优异特性意味着GaN整流器件相比于Si基整流晶闸管更适合应用于高压、高频的工作场合，更优异的导热特性更赋予了GaN整流器在小型化、集成化应用领域更广阔的应用前景与性能稳定性。因此，探索35GHz高交流频率下工作的GaN整流器的实现方法具有开创性的革命意义与社会应用价值。
发明内容
为了克服现有技术的上述缺点与不足，本发明的目的在于提供一种适用于35GHz交流频率下工作的GaN整流器的制备方法，该方法具有制备，与现有生产手段匹配性高且易于实现的优点。
本发明的目的通过以下技术方案实现：
适用于35GHz交流频率下工作的GaN整流器的制备方法，包括以下步骤：
(1)在硅衬底上依次生长N极性面GaN缓冲层、碳掺杂半绝缘化N极性面GaN层、非掺杂N极性面AlGaN层、非掺杂N极性面GaN层和非掺杂N极性面InGaN薄膜，得到整流器外延片；
(2)将步骤(1)所得GaN整流器外延片依次置于丙酮、去离子水、无水 乙醇中超声处理，拿出后经去离子水清洗再用热高纯氮气吹干；
(3)对步骤(2)得到的GaN整流器外延片进行肖特基接触电极图案光刻制备：通过旋涂匀胶在步骤(2)所得GaN整流器外延片上均匀涂抹光刻胶，将涂有光刻胶的GaN整流器外延片进行预烘，随后放入光刻机中进行曝光，最后将曝光后的外延片浸入显影液中进行光刻显影并清洗；
(4)对光刻后GaN整流器外延片进行反应离子刻蚀，在GaN整流器外延片中，沿肖特基接触电极图案刻蚀出凹槽，得到欧姆接触电极；
(5)将步骤(4)所得刻有欧姆接触电极对应图案凹槽的GaN整流器外延片放入电子束蒸发设备中，对蒸发腔体抽真空，随后依次蒸镀肖特基接触电极金属，蒸镀结束后，对GaN整流器外延片进行退火；
(6)将GaN整流器外延片浸入去胶液后去除，使用去离子水冲洗并使用丙酮对GaN整流器外延片表面残留的光刻胶与蒸镀金属进行超声处理去除，超声后再经去离子水清洗，再用热高纯氮气吹干；
(7)通过掩膜板中的对准标记，对GaN整流器外延片进行对准，重复步骤(3)工艺，在相应位置上光刻显影，制备器件欧姆接触电极图案并清洗；
(8)对GaN整流器外延片进行欧姆接触电极制备：将步骤(7)所得光刻显影出欧姆接触电极图案的GaN整流器外延片放入电子束蒸发设备中，对蒸发腔抽真空，随后依次蒸镀欧姆接触电极金属，蒸镀结束后，对GaN整流器外延片进行退火；
(9)重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN外延片表面残留的光刻胶与蒸镀金属；
(10)使用等离子体增强化学气相沉积方法制备氮化硅钝化层：将步骤(9)所得的GaN整流器外延片放入等离子体增强化学气相沉积设备中，升温并在抽高真空后通入载气与反应气体，在GaN整流器外延片表面沉积SiN x钝化层；其中x＝1.33-1.5；
(11)重复步骤(3)工艺，通过光刻显影在GaN外延片表面制备掩膜板，将欧姆接触电极与肖特基接触电极图案上的SiNx暴露出来；
(12)使用湿法刻蚀方法，将暴露出来的SiNx刻蚀掉，最后重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残留的光刻胶与氮化硅钝化层并清洗；
(13)通过掩膜板对准标记对准，重复步骤(3)工艺，在GaN外延片表面光刻显影制备台面隔离图案；
(14)台面隔离：重复步骤(4)工艺，使用反应离子刻蚀设备，对步骤(13)得到的GaN整流器外延片表面进行凹槽刻蚀并清洗；
(15)台面隔离钝化层制作：将步骤(14)所得的GaN整流器外延片放入等离子体辅助化学气象沉积设备中，重复步骤(10)工艺，在GaN整流器外延片刻蚀凹槽内沉积SiN x钝化层；
(16)使用步骤(12)湿法腐蚀工艺去除步骤(15)处理后的GaN整流器外延片表面多余SiN x层后，采用步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残余SiN x与光刻胶；最后制得硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片。
步骤(1)所述的硅衬底以(111)密排面为外延面；
所述N极性面GaN缓冲层、碳掺杂半绝缘化N极性面GaN层、非掺杂N极性面AlGaN层、非掺杂N极性面GaN层和非掺杂N极性面InGaN薄膜均以(0001)为外延方向。
步骤(2)和步骤(6)所述超声处理的时间均为3～15min。
步骤(3)所述光刻胶的厚度在0.2～0.7μm；所述曝光的时间为1～4s；所显影的时间为45～95s。
步骤(4)所述凹槽的深度为150～400nm。
步骤(5)和(8)所述真空的真空度均为1～5×10 -5Pa；步骤(5)和(8)所述退火的温度均为450～800℃，所述退火的时间均为30～120min。
步骤(6)所述浸泡时间为45～100min。
步骤(10)和步骤(15)所述SiN x钝化层的沉积时间均为60～120min。
步骤(14)所述凹槽的深度为1～2.5μm。
适用于35GHz交流频率下工作的GaN整流器，由所述适用于35GHz交流频率下工作的GaN整流器的制备方法制备得到。
与现有技术相比，本发明具有以下优点和有益效果：
(1)本发明实现了高频(35GHz)GaN整流器的制备，在肖特基接触电极结构设计部分采用T型栅设计方案，能够有效提高整流器件栅控特性并有效减少整流器件工作过程中的电流集中效应，提高整流器件在大功率工作下的性能稳定性。
(2)本发明使用以GaN为代表的III族氮化物作为整流器基础材料，依托于III族氮化物相比与传统Si材料更加优异的材料特性，能更好地实现器件在更高频应用上的小型化与集成化。
(3)本发明使用N极性面III族氮化物作为器件基底材料，相比于传统金属极性面III族氮化物，可有效增强AlGaN/GaN异质结界面处的二维电子气限阈性并增强器件栅控性，易于制作性能更适用于35GHz交流频率下工作的增强型整流器件。
(4)本发明选用集成电路最普遍应用的Si材料作为器件外延衬底，易于实现器件集成应用。
附图说明
图1是本发明的实施例1制备GaN整流器芯片的截面示意图。
图2是本发明的实施例1的GaN(0002)X射线摇摆曲线图。
图3是本发明的实施例1的GaN外延片表面形貌原子力显微镜图。
具体实施方式
下面结合实施例，对本发明作进一步地详细说明，但本发明的实施方式不限于此。
实施例1
本实施例的硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片的制备方法：
(1)如图1所示，采用金属有机物化学气相沉积技术在硅衬底上生长GaN整流器外延片，包括生长在硅衬底1上的N极性面GaN缓冲层2，生长在N极性面GaN缓冲层2上的碳掺杂半绝缘化N极性面GaN层3，其掺杂浓度为5.9×10 18cm -3，生长在碳掺杂半绝缘化N极性GaN薄膜3上的非掺杂N极性面AlGaN层4，生长在非掺杂N极性面AlGaN层4上的非掺杂N极性面GaN层5，生长在非掺杂N极性面GaN层5上的非掺杂N极性面InGaN薄膜6；所述GaN缓冲层厚度为800nm；所述碳掺杂GaN层厚度4为100nm；所述非掺杂AlGaN层厚度为450nm；所述非掺杂GaN层厚度为500nm；所述非掺杂InGaN层厚度为150nm。
(2)将GaN整流器外延片依次置于丙酮、无水乙醇、去离子水中各自超声3min，去除后经去离子水冲洗，冲洗后的GaN整流器外延片用热高纯氮气吹干。
(3)对清洗后的GaN整流器外延片旋涂正性光刻胶，型号为RZJ304，光刻胶厚度为0.3μm，将涂有光刻胶的外延片置于热台上预烘45s，随后将涂有光刻胶的外延片放入光刻机中进行曝光，曝光时间为3s，再之后将曝光后的外 延片浸泡入正性显影液中，显影液型号为RZX3038，浸泡时间为60s，最后将显影完成的外延片取出，用去离子水冲洗并用热高纯氮气吹干，置于热台上烘烤坚膜，烘烤时间为45s。
(4)将光刻后GaN整流器外延片置入反应离子刻蚀机中对光刻暴露出的肖特基接触电极8图案进行反应离子刻蚀，刻蚀出对应图案的凹槽，凹槽深度为200nm。
(5)对GaN整流器外延片进行肖特基接触电极8制备：将经反应离子刻蚀后的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至1×10 -5Pa，随后依次蒸镀电极金属MoS 2/Ni/Au，蒸镀结束后，对GaN整流器外延片进行退火，退火温度500℃，退火时间60min。
(6)将制备好欧姆电极的GaN整流器外延片浸入去胶液中浸泡60min，捞出后用去离子水冲洗并置于丙酮中超声5min，拿出后经去离子水冲洗并用热氮气吹干。
(7)通过掩膜板中的对准标记，对GaN整流器外延片进行对准，重复步骤(3)光刻工艺，在相应位置上光刻显影，制备GaN整流器外延片上暴露出器件肖特基接触电极图案区域。
(8)对光刻后GaN整流器外延片进行欧姆接触电极9制备：将制备有器件欧姆接触图案的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至1×10 -5Pa，随后依次蒸镀欧姆接触电极物质Ti/Al/Ni/Au。
(9)重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN外延片表面残留的光刻胶与蒸镀金属。
(10)使用等离子体增强化学气相沉积方法制备SiN x钝化层7：将制备好电极的GaN整流器外延片放入等离子体增强化学气相沉积设备中，仪器升温至800℃，腔体真空度抽至1×10 -5Pa，沉积时间60min。
(11)重复步骤(3)工艺，通过光刻显影在GaN外延片表面制备掩膜板，将欧姆接触电极与肖特基接触电极图案上的SiN x(x＝1.33-1.5)暴露出来；
(12)使用湿法刻蚀方法，将暴露出的SiN x钝化层刻蚀掉，取出后用去离子水冲洗，最后重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除外延片表面残留的光刻胶与SiN x；
(13)通过掩膜板对准标记对准，重复步骤(3)工艺，在GaN外延片表面光刻显影制备台面隔离图案；
(14)台面隔离图形刻蚀：重复步骤(4)工艺，使用反应离子刻蚀设备，对步骤(13)得到的GaN整流器外延片表面进行凹槽刻蚀，刻蚀深度为2μm，刻蚀完毕后使用去离子水冲洗外延片表面并用热氮气吹干；
(15)台面隔离钝化层制作：GaN整流器外延片放入等离子体辅助化学气象沉积设备中，重复步骤(10)工艺，在GaN整流器外延片刻蚀凹槽内沉积SiN x钝化层，沉积时间60min；
(16)使用步骤(12)湿法腐蚀工艺去除表面多余SiN x层后，采用步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残余SiN x与光刻胶。最后制得硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片。
本实施例制得的GaN整流器结构如图1所示，GaN薄膜的GaN(0002)X射线摇摆曲线如图2所示，半高宽值为0.0096°。GaN外延片表面形貌原子力显微镜图如3所示，表面微观形貌呈现平滑理想的层流状结构，表面粗糙度RMS≤0.9埃，表面形貌和晶体质量均十分良好。
实施例2
本实施例的硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片的制备方法：
(1)采用金属有机物化学气相沉积技术在硅衬底上生长GaN整流器外延片，包括生长在硅衬底上的N极性面GaN缓冲层，生长在N极性面GaN缓冲层上的碳掺杂半绝缘化N极性面GaN层，其掺杂浓度为5.9×10 18cm -3，生长在碳掺杂半绝缘化N极性GaN薄膜上的非掺杂N极性面AlGaN层，生长在非掺杂N极性面AlGaN层上的非掺杂N极性面GaN层，生长在非掺杂N极性面GaN层上的非掺杂N极性面InGaN薄膜；所述GaN缓冲层厚度为600nm；所述碳掺杂GaN层厚度为150nm；所述非掺杂AlGaN层厚度为300nm；所述非掺杂GaN层厚度为400nm；所述非掺杂InGaN层厚度为70nm。
(2)将GaN整流器外延片依次置于丙酮、无水乙醇、去离子水中各自超声3min，去除后经去离子水冲洗，冲洗后的GaN整流器外延片用热高纯氮气吹干。
(3)对清洗后的GaN整流器外延片旋涂正性光刻胶，型号为RZJ304，光刻胶厚度为0.2μm，将涂有光刻胶的外延片置于热台上预烘45s，随后将涂有光刻胶的外延片放入光刻机中进行曝光，曝光时间为1s，再之后将曝光后的外延片浸泡入正性显影液中，显影液型号为RZX3038，浸泡时间为30s，最后将显影 完成的外延片取出，用去离子水冲洗并用热高纯氮气吹干，置于热台上烘烤坚膜，烘烤时间为45s。
(4)将光刻后GaN整流器外延片置入反应离子刻蚀机中对光刻暴露出的肖特基接触电极图案进行反应离子刻蚀，刻蚀出对应图案的凹槽，凹槽深度为200nm。
(5)对GaN整流器外延片进行肖特基接触电极制备：将经反应离子刻蚀后的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至3×10 -5Pa，随后依次蒸镀电极金属MoS 2/Ni/Au，蒸镀结束后，对GaN整流器外延片进行退火，退火温度800℃，退火时间120min。
(6)将制备好欧姆电极的GaN整流器外延片浸入去胶液中浸泡45min，捞出后用去离子水冲洗并置于丙酮中超声5min，拿出后经去离子水冲洗并用热氮气吹干。
(7)通过掩膜板中的对准标记，对GaN整流器外延片进行对准，重复步骤(3)光刻工艺，在相应位置上光刻显影，制备GaN整流器外延片上暴露出器件肖特基接触电极图案区域。
(8)对光刻后GaN整流器外延片进行欧姆接触电极制备：将制备有器件欧姆接触图案的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至1×10 -5Pa，随后依次蒸镀欧姆接触电极物质Ti/Al/Ni/Au，蒸镀结束后，对GaN整流器外延片进行退火，退火温度800℃，退火时间120min。
(9)重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN外延片表面残留的光刻胶与蒸镀金属。
(10)使用等离子体增强化学气相沉积方法制备SiN x钝化层：将制备好电极的GaN整流器外延片放入等离子体增强化学气相沉积设备中，仪器升温至800℃，腔体真空度抽至5×10 -5Pa，沉积时间60min。
(11)重复步骤(3)工艺，通过光刻显影在GaN外延片表面制备掩膜板，将欧姆接触电极与肖特基接触电极图案上的SiN x(x＝1.33-1.5)暴露出来；
(12)使用湿法刻蚀方法，将暴露出的SiN x钝化层刻蚀掉，取出后用去离子水冲洗，最后重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除外延片表面残留的光刻胶与SiN x(x＝1.33-1.5)；
(13)通过掩膜板对准标记对准，重复步骤(3)工艺，在GaN外延片表面光刻显影制备台面隔离图案；
(14)台面隔离图形刻蚀：重复步骤(4)工艺，使用反应离子刻蚀设备，对步骤(13)得到的GaN整流器外延片表面进行凹槽刻蚀，刻蚀深度为1μm，刻蚀完毕后使用去离子水冲洗外延片表面并用热氮气吹干；
(15)台面隔离钝化层制作：GaN整流器外延片放入等离子体辅助化学气象沉积设备中，重复步骤(10)工艺，在GaN整流器外延片刻蚀凹槽内沉积SiN x钝化层，沉积时间90min；
(16)使用步骤(12)湿法腐蚀工艺去除步骤(15)处理后的GaN整流器外延片表面多余SiN x层后，采用步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残余SiN x与光刻胶。最后制得硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片。
本实施例制得的GaN整流器测试结果与实施例1类似，在此不再赘述。
实施例3
本实施例的硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片的制备方法：
(1)采用金属有机物化学气相沉积技术在硅衬底上生长GaN整流器外延片，包括生长在硅衬底上的N极性面GaN缓冲层，生长在N极性面GaN缓冲层上的碳掺杂半绝缘化N极性面GaN层，其掺杂浓度为5.9×10 18cm -3，生长在碳掺杂半绝缘化N极性GaN薄膜上的非掺杂N极性面AlGaN层，生长在非掺杂N极性面AlGaN层上的非掺杂N极性面GaN层，生长在非掺杂N极性面GaN层上的非掺杂N极性面InGaN薄膜；所述GaN缓冲层厚度为850nm；所述碳掺杂GaN层厚度为200nm；所述非掺杂AlGaN层厚度为450nm；所述非掺杂GaN层厚度为650nm；所述非掺杂InGaN层厚度为150nm。
(2)将GaN整流器外延片依次置于丙酮、无水乙醇、去离子水中各自超声3min，去除后经去离子水冲洗，冲洗后的GaN整流器外延片用热高纯氮气吹干。
(3)对清洗后的GaN整流器外延片旋涂正性光刻胶，型号为RZJ304，光刻胶厚度为0.2μm，将涂有光刻胶的外延片置于热台上预烘45s，随后将涂有光刻胶的外延片放入光刻机中进行曝光，曝光时间为4s，再之后将曝光后的外延片浸泡入正性显影液中，显影液型号为RZX3038，浸泡时间为30s，最后将显影完成的外延片取出，用去离子水冲洗并用热高纯氮气吹干，置于热台上烘烤坚膜，烘烤时间为45s。
(4)将光刻后GaN整流器外延片置入反应离子刻蚀机中对光刻暴露出的肖特基接触电极图案进行反应离子刻蚀，刻蚀出对应图案的凹槽，凹槽深度为400nm。
(5)对GaN整流器外延片进行肖特基接触电极制备：将经反应离子刻蚀后的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至5×10 -5Pa，随后依次蒸镀电极金属MoS 2/Ni/Au，蒸镀结束后，对GaN整流器外延片进行退火，退火温度800℃，退火时间120min。
(6)将制备好欧姆电极的GaN整流器外延片浸入去胶液中浸泡100min，捞出后用去离子水冲洗并置于丙酮中超声15min，拿出后经去离子水冲洗并用热氮气吹干。
(7)通过掩膜板中的对准标记，对GaN整流器外延片进行对准，重复步骤(3)光刻工艺，在相应位置上光刻显影，制备GaN整流器外延片上暴露出器件肖特基接触电极图案区域。
(8)对光刻后GaN整流器外延片进行欧姆接触电极制备：将制备有器件欧姆接触图案的GaN整流器外延片放入电子束蒸发设备中，将腔体真空度抽至1×10 -5Pa，随后依次蒸镀欧姆接触电极物质Ti/Al/Ni/Au。
(9)重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN外延片表面残留的光刻胶与蒸镀金属。
(10)使用等离子体增强化学气相沉积方法制备SiN x(x＝1.33-1.5)钝化层：将制备好电极的GaN整流器外延片放入等离子体增强化学气相沉积设备中，仪器升温至800℃，腔体真空度抽至5×10 -5Pa，沉积时间120min。
(11)重复步骤(3)工艺，通过光刻显影在GaN外延片表面制备掩膜板，将欧姆接触电极与肖特基接触电极图案上的SiN x暴露出来；
(12)使用湿法刻蚀方法，将暴露出的SiN x钝化层刻蚀掉，取出后用去离子水冲洗，最后重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除外延片表面残留的光刻胶与SiN x。
(13)通过掩膜板对准标记对准，重复步骤(3)工艺，在GaN外延片表面光刻显影制备台面隔离图案；
(14)台面隔离图形刻蚀：重复步骤(4)工艺，使用反应离子刻蚀设备，对步骤(13)得到的GaN整流器外延片表面进行凹槽刻蚀，刻蚀深度为2.5μm，刻蚀完毕后使用去离子水冲洗外延片表面并用热氮气吹干；
(15)台面隔离钝化层制作：GaN整流器外延片放入等离子体辅助化学气象沉积设备中，重复步骤(10)工艺，在GaN整流器外延片刻蚀凹槽内沉积SiN x钝化层，沉积时间120min；
(16)使用步骤(12)湿法腐蚀工艺去除步骤(15)处理后的GaN整流器外延片表面多余SiN x层后，采用步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残余SiN x与光刻胶。最后制得硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片。
本实施例制得的GaN整流器测试结果与实施例1类似，在此不再赘述。
上述实施例为本发明较佳的实施方式，但本发明的实施方式并不受所述实施例的限制，其他的任何未背离本发明的精神实质与原理下所作的改变、修饰、替代、组合、简化，均应为等效的置换方式，都包含在本发明的保护范围之内。

Claims (10)

  1. 适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，包括以下步骤：
    (1)在硅衬底上依次生长N极性面GaN缓冲层、碳掺杂半绝缘化N极性面GaN层、非掺杂N极性面AlGaN层、非掺杂N极性面GaN层和非掺杂N极性面InGaN薄膜，得到整流器外延片；
    (2)将步骤(1)所得GaN整流器外延片依次置于丙酮、去离子水、无水乙醇中超声处理，拿出后经去离子水清洗再用热高纯氮气吹干；
    (3)对步骤(2)得到的GaN整流器外延片进行肖特基接触电极图案光刻制备：通过旋涂匀胶在步骤(2)所得GaN整流器外延片上均匀涂抹光刻胶，将涂有光刻胶的GaN整流器外延片进行预烘，随后放入光刻机中进行曝光，最后将曝光后的外延片浸入显影液中进行光刻显影并清洗；
    (4)对光刻后GaN整流器外延片进行反应离子刻蚀，在GaN整流器外延片中，沿肖特基接触电极图案刻蚀出凹槽，得到欧姆接触电极；
    (5)将步骤(4)所得刻有欧姆接触电极对应图案凹槽的GaN整流器外延片放入电子束蒸发设备中，对蒸发腔体抽真空，随后依次蒸镀肖特基接触电极金属，蒸镀结束后，对GaN整流器外延片进行退火；
    (6)将GaN整流器外延片浸入去胶液后去除，使用去离子水冲洗并使用丙酮对GaN整流器外延片表面残留的光刻胶与蒸镀金属进行超声处理去除，超声后再经去离子水清洗，再用热高纯氮气吹干；
    (7)通过掩膜板中的对准标记，对GaN整流器外延片进行对准，重复步骤(3)工艺，在相应位置上光刻显影，制备器件欧姆接触电极图案并清洗；
    (8)对GaN整流器外延片进行欧姆接触电极制备：将步骤(7)所得光刻显影出欧姆接触电极图案的GaN整流器外延片放入电子束蒸发设备中，对蒸发腔抽真空，随后依次蒸镀欧姆接触电极金属，蒸镀结束后，对GaN整流器外延片进行退火；
    (9)重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN外延片表面残留的光刻胶与蒸镀金属；
    (10)使用等离子体增强化学气相沉积方法制备氮化硅钝化层：将步骤(9)所得的GaN整流器外延片放入等离子体增强化学气相沉积设备中，升温并在抽高真空后通入载气与反应气体，在GaN整流器外延片表面沉积SiN x钝化层；其 中x＝1.33-1.5；
    (11)重复步骤(3)工艺，通过光刻显影在GaN外延片表面制备掩膜板，将欧姆接触电极与肖特基接触电极图案上的SiNx暴露出来；
    (12)使用湿法刻蚀方法，将暴露出来的SiNx刻蚀掉，最后重复步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残留的光刻胶与氮化硅钝化层并清洗；
    (13)通过掩膜板对准标记对准，重复步骤(3)工艺，在GaN外延片表面光刻显影制备台面隔离图案；
    (14)台面隔离：重复步骤(4)工艺，使用反应离子刻蚀设备，对步骤(13)得到的GaN整流器外延片表面进行凹槽刻蚀并清洗；
    (15)台面隔离钝化层制作：将步骤(14)所得的GaN整流器外延片放入等离子体辅助化学气象沉积设备中，重复步骤(10)工艺，在GaN整流器外延片刻蚀凹槽内沉积SiN x钝化层；
    (16)使用步骤(12)湿法腐蚀工艺去除步骤(15)处理后的GaN整流器外延片表面多余SiN x层后，采用步骤(6)工艺，通过去胶液浸泡与超声清洗去除GaN整流器外延片表面残余SiN x与光刻胶；最后制得硅衬底上适用于35GHz交流频率下工作的GaN整流器芯片。
  2. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(1)所述的硅衬底以(111)密排面为外延面；
    所述N极性面GaN缓冲层、碳掺杂半绝缘化N极性面GaN层、非掺杂N极性面AlGaN层、非掺杂N极性面GaN层和非掺杂N极性面InGaN薄膜均以
    Figure PCTCN2018074684-appb-100001
    为外延方向。
  3. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(2)和步骤(6)所述超声处理的时间均为3～15min。
  4. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(3)所述光刻胶的厚度在0.2～0.7μm；所述曝光的时间为1～4s；所显影的时间为45～95s。
  5. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(4)所述凹槽的深度为150～400nm。
  6. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(5)和(8)所述真空的真空度均为1～5×10 -5Pa； 步骤(5)和(8)所述退火的温度均为450～800℃，所述退火的时间均为30～120min。
  7. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(6)所述浸泡时间为45～100min。
  8. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(10)和步骤(15)所述SiN x钝化层的沉积时间均为60～120min。
  9. 根据权利要求1所述的适用于35GHz交流频率下工作的GaN整流器的制备方法，其特征在于，步骤(14)所述凹槽的深度为1～2.5μm。
  10. 适用于35GHz交流频率下工作的GaN整流器，其特征在于，由权利要求1～9任一项所述适用于35GHz交流频率下工作的GaN整流器的制备方法制备得到。
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