WO2019114061A1 - Oled backplane structure and manufacturing method of oled backplane - Google Patents

Oled backplane structure and manufacturing method of oled backplane Download PDF

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Publication number
WO2019114061A1
WO2019114061A1 PCT/CN2018/071454 CN2018071454W WO2019114061A1 WO 2019114061 A1 WO2019114061 A1 WO 2019114061A1 CN 2018071454 W CN2018071454 W CN 2018071454W WO 2019114061 A1 WO2019114061 A1 WO 2019114061A1
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layer
insulating layer
gate
interlayer insulating
thin film
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PCT/CN2018/071454
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French (fr)
Chinese (zh)
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张伟彬
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武汉华星光电半导体显示技术有限公司
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Publication of WO2019114061A1 publication Critical patent/WO2019114061A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance

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  • the present invention relates to the field of OLED display technologies, and in particular, to an OLED backplane structure and an OLED backplane manufacturing method.
  • OLED organic light emitting diodes
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • the OLED display has many advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, flexible display and large-area full-color display. Recognized by the industry as the most promising display device.
  • OLED backplanes are an important part of OLED displays.
  • OLED backplanes typically include:
  • An array substrate wherein the array substrate is provided with a plurality of thin film transistors (TFTs) arranged in an array, each of the thin film transistors including a gate, a semiconductor layer, a source and a drain, wherein the source The drains respectively contact the two sides of the semiconductor layer;
  • TFTs thin film transistors
  • An organic material layer disposed on the anode specifically including a hole injection layer (HIL), a hole transport layer (HTL), an organic light emitting layer (EML), an electron transport layer (ETL), and electron injection Layer (EIL);
  • HIL hole injection layer
  • HTL hole transport layer
  • EML organic light emitting layer
  • ETL electron transport layer
  • EIL electron injection Layer
  • the display principle of the OLED display is that, under a certain voltage driving, electrons and holes are injected from the cathode and the anode to the electron transport layer and the hole transport layer, respectively, and electrons and holes are respectively transported through the electron transport layer and the hole transport layer.
  • the organic light-emitting layer is encountered and meets in the organic light-emitting layer to form excitons and excite the luminescent molecules, which emit radiation by radiation relaxation.
  • an OLED backplane that is common in the prior art is covered on the array substrate 100 with a flat layer 200 disposed on the flat layer 200 and via a via 201 extending through the flat layer 200 .
  • the drain 105 of the thin film transistor 10 is contacted.
  • the source 104 and the drain 105 of the thin film transistor 10 respectively contact both sides of the semiconductor layer 101 of the thin film transistor 10, the source 104 is in contact with the semiconductor layer 101, and the drain 105 and the semiconductor layer 101 are The contact is a metal-semiconductor contact.
  • the contact barrier between the metal and the semiconductor is high, and the contact resistance is large; in addition, the anode 300 and the thin film transistor There is also an electrode contact resistance between the drains 105 of 10.
  • the superposition of these two types of contact resistance results in a large on-resistance of the OLED display, so that the energy consumption of the OLED display is high.
  • the existing method for reducing the on-resistance of the OLED display is one between the source 104 and the semiconductor layer 101 and between the drain 105 and the semiconductor layer 101.
  • a thickness of an insulating non-metal oxide dielectric layer, such as silicon oxide (SiOx), silicon nitride (SiNx), or the like, is formed to form a Metal-Interfacial Layer-Semi Conductor (MIS).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • MIS Metal-Interfacial Layer-Semi Conductor
  • the second is to perform metal annealing treatment after the anode 300 is fabricated to release the stress of each structural layer material, The contact resistance between the anode 300 and the drain 105 of the thin film transistor 10 is lowered, but the effect is limited.
  • the object of the present invention is to provide an OLED backplane structure, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing the energy consumption. .
  • Another object of the present invention is to provide a method for fabricating an OLED backplane, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing Energy consumption and streamline processes.
  • the present invention first provides an OLED backplane structure, including:
  • the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
  • a metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor.
  • the material of the portion where the composite electrode is in contact with the semiconductor layer of the thin film transistor is ITO or IZO.
  • the material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO.
  • the via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
  • the array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer
  • the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
  • the drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
  • the invention also provides a method for fabricating an OLED backplane, comprising the following steps:
  • Step S1 forming an array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array and having a drain vacancy;
  • Step S2 coating a flat layer on the array substrate, and patterning the flat layer to obtain a via hole;
  • Step S3 forming a composite electrode on the flat layer, the composite electrode contacting the semiconductor layer of the thin film transistor via the via hole;
  • the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
  • a metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor.
  • a part of the material in which the composite electrode is in contact with the semiconductor layer of the thin film transistor is ITO or IZO.
  • the material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO.
  • the via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
  • the array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer a source of the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer contacting the source of the semiconductor layer; the drain hole penetrating through Depicting the second interlayer insulating layer, the first interlayer
  • the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer are performed after the first interlayer insulating layer is formed. Etching, exposing one side and the other side of the semiconductor layer; then forming the second interlayer insulating layer on the first interlayer insulating layer and performing a patterning process to form the drain hole and a source hole; then depositing a metal film on the second interlayer insulating layer and etching, leaving only a portion of the metal film filling the source hole to form the source, and filling the drain hole A portion of the metal film is etched away and the drain hole is exposed.
  • the invention also provides an OLED backplane structure, comprising:
  • An array substrate wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
  • the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide
  • the metal layer and the superposed layer are laminated on the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor;
  • the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is ITO or IZO;
  • the material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO;
  • the via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
  • the array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer
  • the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
  • the drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
  • the present invention provides an OLED backplane structure in which a composite electrode integrating an anode and a drain of a thin film transistor is disposed, and on the one hand, the composite electrode is in contact with a semiconductor layer of the thin film transistor.
  • Part of the material is a conductive metal oxide, which reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, which can greatly reduce the contact resistance of the metal-semiconductor.
  • the anode is integrated with the drain of the thin film transistor, eliminating contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing power consumption.
  • the invention provides an OLED backplane manufacturing method, which combines an anode and a drain of a thin film transistor to form a composite electrode, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact between the anode and the drain of the thin film transistor.
  • Resistor which greatly reduces the on-resistance of the OLED display, reduces energy consumption, and eliminates the metal annealing process, which simplifies the process.
  • FIG. 1 is a schematic cross-sectional structural view of a conventional OLED backplane
  • FIG. 2 is a schematic cross-sectional view showing the structure of an OLED backplane of the present invention
  • Figure 3 is a partial enlarged view corresponding to A in Figure 2;
  • FIG. 4 is a flow chart of a method for fabricating an OLED backplane according to the present invention.
  • step S1 of the method for fabricating an OLED backplane according to the present invention are schematic views of step S1 of the method for fabricating an OLED backplane according to the present invention.
  • step S2 is a schematic diagram of step S2 of the method for fabricating an OLED backplane according to the present invention.
  • FIG. 10 is a schematic diagram of step S3 of the method for fabricating an OLED backplane of the present invention.
  • the present invention provides an OLED backplane structure, including:
  • the array substrate 1, the array substrate 1 is provided with a plurality of thin film transistors 11 arranged in an array;
  • a pixel defining layer 7 disposed on the composite electrode 5 and the flat layer 3, the pixel defining layer 7 having a pixel opening 71 surrounding the composite electrode 5.
  • the via hole V includes a via hole V2 penetrating through the flat layer 3 and a drain hole V1 communicating with the via hole V2.
  • the structure of the thin film transistor 11 on the array substrate 1 is not limited, and may be a single gate type, a double gate type, a top gate type, a bottom gate type, etc., taking the top double gate type structure shown in FIG. 2 as an example.
  • the array substrate 1 includes a flexible substrate 121, a first buffer layer 122 overlying the flexible substrate 121, a second buffer layer 123 overlying the first buffer layer 122, and a second buffer layer. a semiconductor layer 111 on 123, a first gate insulating layer 124 overlying the second buffer layer 123 and the semiconductor layer 111, and a first gate insulating layer 124 over the semiconductor layer 111.
  • a first gate 112 a second gate insulating layer 125 covering the first gate insulating layer 124 and the first gate 112, and a second gate above the first gate 112.
  • the edge layer 126, the second gate insulating layer 125 and the source hole V3 of the first gate insulating layer 124 are in contact with the source 114 on the side of the semiconductor layer 111; the drain hole V1 extends through the second layer
  • the insulating layer 127, the first interlayer insulating layer 126, the second gate insulating layer 125, and the first gate insulating layer 124 expose the other side of the semiconductor layer 111.
  • the material of the flexible substrate 121 is Polyimide (PI); the materials of the first buffer layer 122 and the second buffer layer 123 are both silicon oxide (SiOx) and silicon nitride (SiNx).
  • the material of the semiconductor layer 111 is not limited to amorphous silicon, low temperature poly-silicon (LTPS), metal oxide semiconductor, germanium (Ge), etc.;
  • the material of the insulating layer 126 is SiOx, SiNx or a combination of the two, the material of the second interlayer insulating layer 127 is an organic photoresist; and the material of the flat layer 3 is PI.
  • the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11. 2 and 3, the composite electrode 5 includes a portion 51 that is in contact with the semiconductor layer 111 of the thin film transistor 11 and a portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11.
  • the metal layer 52 and the overlying layer 53 are laminated on top. It should be noted that FIG. 3 is only a schematic diagram of the number and order of the film layers. In the actual process, the thickness of each layer in the via hole V is not uniform, and the via hole V is substantially filled.
  • the material of the portion 51 of the composite electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
  • the metal layer 52 is made of a metal having good conductivity such as silver (Ag) or copper (Cu), and the superposed layer 53 is made of a conductive metal oxide such as ITO or IZO, that is, the composite.
  • the electrode 5 may be ITO/Ag/ITO, ITO/Ag/IZO, ITO/Cu/ITO, ITO/Cu/IZO, IZO/Ag/IZO, IZO/Ag/ITO, IZO/Cu/IZO, IZO/Cu/ A laminated structure such as ITO.
  • the material of the portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as ITO
  • the conductive metal oxide such as ITO itself has good electrical conductivity
  • the composite The portion 51 of the electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the metal-semiconductor Contact resistance; since the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11, the contact resistance between the anode and the drain of the thin film transistor 11 is eliminated; the combination of these two aspects can greatly reduce the conduction of the OLED display Resistance to reduce energy consumption.
  • the present invention further provides a method for fabricating an OLED backplane, comprising the following steps:
  • Step S1 referring to FIG. 5 to FIG. 8, an array substrate 1 is prepared.
  • the array substrate 1 is provided with a plurality of thin film transistors 11 arranged in an array.
  • the structure of the thin film transistor 11 on the array substrate 1 is not limited, and may be a single gate type, a double gate type, a top gate type, a bottom gate type, etc., and the top double gate type structure shown in FIG. 8 is taken as an example.
  • the array substrate 1 includes a flexible substrate 121, a first buffer layer 122 overlying the flexible substrate 121, and a second buffer layer 123 overlying the first buffer layer 122. a semiconductor layer 111 on the second buffer layer 123, a first gate insulating layer 124 covering the second buffer layer 123 and the semiconductor layer 111, and a first gate insulating layer above the semiconductor layer 111.
  • An interlayer insulating layer 126, a second gate insulating layer 125 and a source hole V3 of the first gate insulating layer 124 are in contact with the source 114 of the semiconductor layer 111; a drain hole V1 extends through the second The interlayer insulating layer 127, the first interlayer insulating layer 126, the second gate insulating layer 125, and the first gate insulating layer 124 expose the other side of the semiconductor layer 111.
  • the material of the flexible substrate 121 is PI; the materials of the first buffer layer 122 and the second buffer layer 123 are both SiOx, SiNx or a combination of the two; the material of the semiconductor layer 111 is not limited to Amorphous silicon, low temperature polysilicon, metal oxide semiconductor, germanium, etc.; the material of the first interlayer insulating layer 126 is SiOx, SiNx or a combination of the two, and the material of the second interlayer insulating layer 127 is organic light.
  • the material of the flat layer 3 is PI.
  • the first interlayer insulating layer 126, the second gate insulating layer 125 and the first gate are formed after the first interlayer insulating layer 126 is formed.
  • the pole insulating layer 124 is etched to expose one side and the other side of the semiconductor layer 111; then the second interlayer insulating layer 127 is formed on the first interlayer insulating layer 126 and exposed or dried Etching the second interlayer insulating layer 127 to form the drain hole V1 and the source hole V3; subsequently depositing a metal thin film on the second interlayer insulating layer 127 and etching, Only a portion of the metal film filling the source hole V3 is left to form the source electrode 114, and a portion of the metal film filling the drain hole V1 is etched away, and the drain hole V1 is exposed.
  • Step S2 referring to FIG. 9, a flat layer 3 made of PI is coated on the array substrate 1, and the flat layer 3 is patterned by exposure or dry etching to form a through layer. 3 and a via hole V2 communicating with the drain hole V1, a via hole V formed by the via hole V2 and the drain hole V1 is obtained.
  • Step S3 referring to FIG. 10, a composite electrode 5 is formed on the flat layer 3 by a conventional process for fabricating an OLED anode, and the composite electrode 5 contacts the semiconductor layer of the thin film transistor 11 via the via hole V. 111.
  • the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11. 10 and 3, the composite electrode 5 includes a portion 51 that is in contact with the semiconductor layer 111 of the thin film transistor 11 and a portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11.
  • the metal layer 52 and the overlying layer 53 are laminated on top.
  • the portion 51 of the composite electrode 5 that is in contact with the semiconductor layer 111 of the thin film transistor 11 is made of a conductive metal oxide such as ITO, IZO, etc.
  • the metal layer 52 is made of a metal having good conductivity such as Ag or Cu.
  • the superposed layer 53 is made of a conductive metal oxide such as ITO or IZO, that is, the composite electrode 5 may be ITO/Ag/ITO, ITO/Ag/IZO, ITO/Cu/ITO, ITO/Cu. Laminated structure of /IZO, IZO/Ag/IZO, IZO/Ag/ITO, IZO/Cu/IZO, IZO/Cu/ITO, etc.
  • the material of the portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as ITO
  • the conductive metal oxide such as ITO itself has good electrical conductivity
  • the composite The portion 51 of the electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the metal-semiconductor Contact resistance; since the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11, the contact resistance between the anode and the drain of the thin film transistor 11 is eliminated; the combination of these two aspects can greatly reduce the conduction of the OLED display Resistance to reduce energy consumption.
  • the composite electrode 5 fabricated in the step S3 can greatly reduce the on-resistance of the OLED display and reduce the power consumption, the subsequent steps need not be performed for the purpose of reducing the contact resistance between the anode and the drain of the thin film transistor 11.
  • Metal annealing treatment can eliminate metal annealing and simplify the process.
  • the OLED backplane manufacturing method further includes a step S4, referring to FIG. 2, depositing a pixel defining layer 7 on the composite electrode 5 and the flat layer 3, and performing patterning processing by dry etching to form the composite electrode 5 Pixel opening 71.
  • the OLED backplane structure of the present invention is provided with a composite electrode in which the anode and the drain of the thin film transistor are integrated, and the material of the portion where the composite electrode is in contact with the semiconductor layer of the thin film transistor is The conductive metal oxide can reduce the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the contact resistance of the metal-semiconductor.
  • the anode and the The drain of the thin film transistor is integrated, eliminating the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing power consumption.
  • the anode and the drain of the thin film transistor are combined to form a composite electrode, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby The on-resistance of the OLED display is greatly reduced, the energy consumption is reduced, and the metal annealing treatment is omitted, which simplifies the process.

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Abstract

Provided are an OLED backplane structure and a manufacturing method of an OLED backplane. The OLED backplane structure is provided with a combined electrode (5). A portion (51) of the combined electrode (5) in contact with a semiconductor layer (111) of a thin film transistor (11) is made of an electrically-conductive metal oxide, such that Fermi-level pinning effect between a metal and a semiconductor can be alleviated while preventing generation of a high series resistance, thereby greatly reducing contact resistance between the metal and the semiconductor. Moreover, a positive electrode and a drain of the thin film transistor (11) form an integral unit, such that contact resistance therebetween is eliminated, thereby greatly reducing turn-on resistance of an OLED display device, and reducing energy consumption.

Description

OLED背板结构及OLED背板制作方法OLED backplane structure and OLED backplane manufacturing method 技术领域Technical field
本发明涉及OLED显示技术领域，尤其涉及一种OLED背板结构及OLED背板制作方法。The present invention relates to the field of OLED display technologies, and in particular, to an OLED backplane structure and an OLED backplane manufacturing method.
背景技术Background technique
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)与有机发光二极管显示器(Organic Light Emitting Diode，OLED)等平板显示技术已经逐步取代CRT显示器。其中，OLED显示器具有自发光、驱动电压低、发光效率高、响应时间短、清晰度与对比度高、近180°视角、使用温度范围宽、可实现柔性显示与大面积全色显示等诸多优点，被业界公认为是最有发展潜力的显示装置。In the field of display technology, flat panel display technologies such as liquid crystal displays (LCDs) and organic light emitting diodes (OLEDs) have gradually replaced CRT displays. Among them, the OLED display has many advantages such as self-illumination, low driving voltage, high luminous efficiency, short response time, high definition and contrast, near 180° viewing angle, wide temperature range, flexible display and large-area full-color display. Recognized by the industry as the most promising display device.
OLED背板是OLED显示器的重要组成部分。OLED背板通常包括：OLED backplanes are an important part of OLED displays. OLED backplanes typically include:
阵列基板，所述阵列基板内设有呈阵列式排布的多个薄膜晶体管(Thin Film Transistor，TFT)，每一薄膜晶体管包括栅极、半导体层、源极及漏极，其中所述源极、漏极分别接触所述半导体层的两侧；An array substrate, wherein the array substrate is provided with a plurality of thin film transistors (TFTs) arranged in an array, each of the thin film transistors including a gate, a semiconductor layer, a source and a drain, wherein the source The drains respectively contact the two sides of the semiconductor layer;
置于所述阵列基板上的阳极，所述阳极接触所述薄膜晶体管的漏极；An anode disposed on the array substrate, the anode contacting a drain of the thin film transistor;
置于所述阳极上有机材料层，所述有机材料层又具体包括空穴注入层(HIL)、空穴传输层(HTL)、有机发光层(EML)、电子传输层(ETL)及电子注入层(EIL)；An organic material layer disposed on the anode, the organic material layer specifically including a hole injection layer (HIL), a hole transport layer (HTL), an organic light emitting layer (EML), an electron transport layer (ETL), and electron injection Layer (EIL);
以及置于所述有机材料层上的阴极。And a cathode disposed on the layer of organic material.
OLED显示器的显示原理为：在一定电压驱动下，电子和空穴分别从所述阴极和阳极注入到电子传输层和空穴传输层，电子和空穴分别经过电子传输层和空穴传输层迁移到有机发光层，并在有机发光层中相遇，形成激子并使发光分子激发，后者经过辐射弛豫而发出可见光。The display principle of the OLED display is that, under a certain voltage driving, electrons and holes are injected from the cathode and the anode to the electron transport layer and the hole transport layer, respectively, and electrons and holes are respectively transported through the electron transport layer and the hole transport layer. The organic light-emitting layer is encountered and meets in the organic light-emitting layer to form excitons and excite the luminescent molecules, which emit radiation by radiation relaxation.
具体地，请参阅图1，现有技术中常见的OLED背板在阵列基板100上覆盖有平坦层200，阳极300设于所述平坦层200上并经由贯穿所述平坦层200的过孔201接触薄膜晶体管10的漏极105。其中，所述薄膜晶体管10的源极104、漏极105分别接触该薄膜晶体管10的半导体层101的两侧，所述源极104与半导体层101的接触及所述漏极105与半导体层101的接触属于金属-半导体接触，由于半导体和金属的接触界面存在强烈的费米能级钉扎效应，金属与半导体的接触势垒很高，接触电阻很大；另外，所述 阳极300与薄膜晶体管10的漏极105之间亦存在电极接触电阻。这两种类型的接触电阻叠加会导致OLED显示器的导通电阻较大，从而OLED显示器的能耗较高。Specifically, referring to FIG. 1 , an OLED backplane that is common in the prior art is covered on the array substrate 100 with a flat layer 200 disposed on the flat layer 200 and via a via 201 extending through the flat layer 200 . The drain 105 of the thin film transistor 10 is contacted. The source 104 and the drain 105 of the thin film transistor 10 respectively contact both sides of the semiconductor layer 101 of the thin film transistor 10, the source 104 is in contact with the semiconductor layer 101, and the drain 105 and the semiconductor layer 101 are The contact is a metal-semiconductor contact. Due to the strong Fermi level pinning effect at the contact interface between the semiconductor and the metal, the contact barrier between the metal and the semiconductor is high, and the contact resistance is large; in addition, the anode 300 and the thin film transistor There is also an electrode contact resistance between the drains 105 of 10. The superposition of these two types of contact resistance results in a large on-resistance of the OLED display, so that the energy consumption of the OLED display is high.
降低导通电阻是降低OLED显示器能耗的关键因素，现有的降低OLED显示器导通电阻的方法一是在所述源极104与半导体层101之间及所述漏极105与半导体层101之间加入一定厚度的绝缘的非金属氧化物介质层，如氧化硅(SiOx)、氮化硅(SiNx)等，形成金属-介质层-半导体结构(Metal-Interfacial layer-Semi conductor，MIS)，以减轻费米能级钉扎效应，但是介质层的绝缘性会使得介质层本身引起额外的电阻串联；二是在制作完所述阳极300之后进行金属退火处理来释放各结构层材料的应力，以降低所述阳极300与薄膜晶体管10的漏极105之间的接触电阻，但效果有限。Reducing the on-resistance is a key factor for reducing the power consumption of the OLED display. The existing method for reducing the on-resistance of the OLED display is one between the source 104 and the semiconductor layer 101 and between the drain 105 and the semiconductor layer 101. A thickness of an insulating non-metal oxide dielectric layer, such as silicon oxide (SiOx), silicon nitride (SiNx), or the like, is formed to form a Metal-Interfacial Layer-Semi Conductor (MIS). Reducing the Fermi level pinning effect, but the insulation of the dielectric layer causes the dielectric layer itself to cause additional resistance in series; the second is to perform metal annealing treatment after the anode 300 is fabricated to release the stress of each structural layer material, The contact resistance between the anode 300 and the drain 105 of the thin film transistor 10 is lowered, but the effect is limited.
发明内容Summary of the invention
本发明的目的在于提供一种OLED背板结构，能够大幅降低金属-半导体的接触电阻，消除阳极与薄膜晶体管的漏极之间的接触电阻，从而大幅降低OLED显示器的导通电阻，减少能耗。The object of the present invention is to provide an OLED backplane structure, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing the energy consumption. .
本发明的另一目的在于提供一种OLED背板制作方法，能够大幅降低金属-半导体的接触电阻，消除阳极与薄膜晶体管漏极之间的接触电阻，从而大幅降低OLED显示器的导通电阻，减少能耗，并简化制程。Another object of the present invention is to provide a method for fabricating an OLED backplane, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing Energy consumption and streamline processes.
为实现上述目的，本发明首先提供一种OLED背板结构，包括：To achieve the above objective, the present invention first provides an OLED backplane structure, including:
阵列基板，所述阵列基板内设有多个呈阵列式排布的薄膜晶体管；An array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
设在所述阵列基板之上的平坦层；a flat layer disposed on the array substrate;
以及设在所述平坦层上经由过孔接触所述薄膜晶体管的半导体层的复合电极；And a composite electrode disposed on the flat layer contacting the semiconductor layer of the thin film transistor via a via;
所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物。The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层。所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为ITO或IZO。A metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor. The material of the portion where the composite electrode is in contact with the semiconductor layer of the thin film transistor is ITO or IZO.
所述金属层的材料为Ag或Cu，所述叠加层的材料为ITO或IZO。The material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO.
所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导 体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer The second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧。The drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
本发明还提供一种OLED背板制作方法，包括如下步骤：The invention also provides a method for fabricating an OLED backplane, comprising the following steps:
步骤S1、制作出阵列基板，所述阵列基板内设有多个呈阵列式排布且漏极空缺的薄膜晶体管；Step S1, forming an array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array and having a drain vacancy;
步骤S2、在所述阵列基板上涂布平坦层，并对所述平坦层进行图案化处理，获得过孔；Step S2, coating a flat layer on the array substrate, and patterning the flat layer to obtain a via hole;
步骤S3、在所述平坦层上成膜复合电极，所述复合电极经由所述过孔接触所述薄膜晶体管的半导体层；Step S3, forming a composite electrode on the flat layer, the composite electrode contacting the semiconductor layer of the thin film transistor via the via hole;
所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物。The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层。A metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor.
所述复合电极与所述薄膜晶体管的半导体层相接触的部分材料为ITO或IZO。A part of the material in which the composite electrode is in contact with the semiconductor layer of the thin film transistor is ITO or IZO.
所述金属层的材料为Ag或Cu，所述叠加层的材料为ITO或IZO。The material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO.
所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer a source of the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer contacting the source of the semiconductor layer; the drain hole penetrating through Depicting the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer The other side of the conductor layer;
所述步骤S1在制作所述阵列基板的过程中，在成膜所述第一层间绝缘层后对所述第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层进行蚀刻，暴露出所述半导体层的一侧与另一侧；然后在所述第一层间绝缘层上成膜所述第二层间绝缘层并进行图案化处理，形成所述漏极孔与源极孔；接下来在所述第二层间绝缘层上沉积金属薄膜并进行蚀刻，只保留填充所述源极孔的部分金属薄膜形成所述源极，而将填充所述漏极孔的部分金属薄膜蚀刻掉，所述漏极孔暴露。In the step S1, in the process of fabricating the array substrate, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer are performed after the first interlayer insulating layer is formed. Etching, exposing one side and the other side of the semiconductor layer; then forming the second interlayer insulating layer on the first interlayer insulating layer and performing a patterning process to form the drain hole and a source hole; then depositing a metal film on the second interlayer insulating layer and etching, leaving only a portion of the metal film filling the source hole to form the source, and filling the drain hole A portion of the metal film is etched away and the drain hole is exposed.
本发明还提供一种OLED背板结构，包括：The invention also provides an OLED backplane structure, comprising:
阵列基板，所述阵列基板内设有多个呈阵列式排布的薄膜晶体管；An array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
设在所述阵列基板之上的平坦层；a flat layer disposed on the array substrate;
以及设在所述平坦层上经由过孔接触所述薄膜晶体管的半导体层的复合电极；And a composite electrode disposed on the flat layer contacting the semiconductor layer of the thin film transistor via a via;
所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物；The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide;
其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层；Wherein the metal layer and the superposed layer are laminated on the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor;
其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为ITO或IZO；Wherein the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is ITO or IZO;
其中，所述金属层的材料为Ag或Cu，所述叠加层的材料为ITO或IZO；Wherein the material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO;
其中，所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer The second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧。The drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
本发明的有益效果：本发明提供的一种OLED背板结构，设置有集阳极与薄膜晶体管的漏极于一体的复合电极，一方面所述复合电极与所述薄 膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物，在减轻金属与半导体之间的费米能级钉扎效应的同时又不会引起较大的串联电阻，能够大幅降低金属-半导体的接触电阻，另一方面，阳极与所述薄膜晶体管的漏极成为一体，消除了阳极与薄膜晶体管的漏极之间的接触电阻，从而能够大幅降低OLED显示器的导通电阻，减少能耗。本发明提供的一种OLED背板制作方法，将阳极与薄膜晶体管的漏极合并在一起制程，形成复合电极，能够大幅降低金属-半导体的接触电阻，消除阳极与薄膜晶体管漏极之间的接触电阻，从而大幅降低OLED显示器的导通电阻，减少能耗，同时省去了金属退火处理，简化了制程。Advantageous Effects of Invention The present invention provides an OLED backplane structure in which a composite electrode integrating an anode and a drain of a thin film transistor is disposed, and on the one hand, the composite electrode is in contact with a semiconductor layer of the thin film transistor. Part of the material is a conductive metal oxide, which reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, which can greatly reduce the contact resistance of the metal-semiconductor. The anode is integrated with the drain of the thin film transistor, eliminating contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing power consumption. The invention provides an OLED backplane manufacturing method, which combines an anode and a drain of a thin film transistor to form a composite electrode, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact between the anode and the drain of the thin film transistor. Resistor, which greatly reduces the on-resistance of the OLED display, reduces energy consumption, and eliminates the metal annealing process, which simplifies the process.
附图说明DRAWINGS
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。The detailed description of the present invention and the accompanying drawings are to be understood,
附图中，In the drawings,
图1为现有的OLED背板的剖面结构示意图；1 is a schematic cross-sectional structural view of a conventional OLED backplane;
图2为本发明的OLED背板结构的剖面示意图；2 is a schematic cross-sectional view showing the structure of an OLED backplane of the present invention;
图3为对应于图2中A处的局部放大图；Figure 3 is a partial enlarged view corresponding to A in Figure 2;
图4为本发明的OLED背板制作方法的流程图；4 is a flow chart of a method for fabricating an OLED backplane according to the present invention;
图5至图8为本发明的OLED背板制作方法的步骤S1的示意图；5 to 8 are schematic views of step S1 of the method for fabricating an OLED backplane according to the present invention;
图9为本发明的OLED背板制作方法的步骤S2的示意图；9 is a schematic diagram of step S2 of the method for fabricating an OLED backplane according to the present invention;
图10为本发明的OLED背板制作方法的步骤S3的示意图。FIG. 10 is a schematic diagram of step S3 of the method for fabricating an OLED backplane of the present invention.
具体实施方式Detailed ways
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。需要说明的是：在本申请中附图仅为示意图，除非特别说明，并不代表各膜层之间的实际厚度比例、平坦程度、形状与图中相同，可以理解的是，因为工艺和制程限制，实际产品会与示意图有一定差异，例如孔洞的形状、各膜层相结合部分的形貌都会与示意图有所差别，这些是本领域技术人员能够理解并且知悉的。本申请中关于工艺步骤顺序以及膜层结构的描述仅表示与本申请技术问题直接相关的各步骤和膜层之间的先后顺序以及相对位置，并不代表其步骤之间绝对不存在其它工艺步骤或其它膜层结构，例如为了控制良率的检查或修补的工艺步骤、为了完成背板上其它区域而进行的工艺步骤、不同结构背板上 膜层数量和种类等，本领域技术人员能够根据本申请的核心思想将这些步骤或结构进行结合。In order to further clarify the technical means and effects of the present invention, the following detailed description will be made in conjunction with the preferred embodiments of the invention and the accompanying drawings. It should be noted that the drawings in the present application are only schematic views. Unless otherwise stated, the actual thickness ratio, flatness and shape between the film layers are not the same as those in the drawings. It can be understood that, because of the process and the process. Limitations, the actual product will be different from the schematic diagram. For example, the shape of the hole and the shape of the combined portion of each film layer will be different from the schematic, which can be understood and understood by those skilled in the art. The description of the process step sequence and the structure of the film layer in the present application merely indicates the sequence and relative position between the steps and the film layers directly related to the technical problem of the present application, and does not mean that there are absolutely no other process steps between the steps. Or other film structure, such as process steps for controlling yield inspection or repair, process steps for completing other regions on the backplane, number and type of film layers on different structural back sheets, etc., those skilled in the art can The core idea of the present application combines these steps or structures.
请参阅图2，本发明提供一种OLED背板结构，包括：Referring to FIG. 2, the present invention provides an OLED backplane structure, including:
阵列基板1，所述阵列基板1内设有多个呈阵列式排布的薄膜晶体管11；The array substrate 1, the array substrate 1 is provided with a plurality of thin film transistors 11 arranged in an array;
设在所述阵列基板1之上的平坦层3；a flat layer 3 disposed on the array substrate 1;
设在所述平坦层3上经由过孔V接触所述薄膜晶体管11的半导体层111的复合电极5；a composite electrode 5 disposed on the flat layer 3 via the via V to contact the semiconductor layer 111 of the thin film transistor 11;
以及设在所述复合电极5与平坦层3上的像素定义层7，所述像素定义层7具有围拢所述复合电极5的像素开口71。And a pixel defining layer 7 disposed on the composite electrode 5 and the flat layer 3, the pixel defining layer 7 having a pixel opening 71 surrounding the composite electrode 5.
具体地：specifically:
所述过孔V包括贯穿所述平坦层3的通孔V2及与所述通孔V2连通的漏极孔V1。The via hole V includes a via hole V2 penetrating through the flat layer 3 and a drain hole V1 communicating with the via hole V2.
所述阵列基板1上薄膜晶体管11的结构形式不限，可以为单栅型、双栅型、顶栅型、底栅型等，以图2所示的顶部双栅型结构为例，所述阵列基板1包括柔性衬底121、覆盖在所述柔性衬底121上的第一缓冲层122、覆盖在所述第一缓冲层122上的第二缓冲层123、设在所述第二缓冲层123上的半导体层111、覆盖在所述第二缓冲层123与半导体层111上的第一栅极绝缘层124、于所述半导体层111上方设在所述第一栅极绝缘层124上的第一栅极112、覆盖在所述第一栅极绝缘层124与第一栅极112上的第二栅极绝缘层125、于所述第一栅极112上方设在所述第二栅极绝缘层125上的第二栅极113、覆盖在所述第二栅极绝缘层125与第二栅极113上的第一层间绝缘层126、覆盖在所述第一层间绝缘层126上的第二层间绝缘层127以及设在所述第二层间绝缘层127上经由贯穿所述第二层间绝缘层127、第一层间绝缘层126、第二栅极绝缘层125与第一栅极绝缘层124的源极孔V3接触所述半导体层111一侧的源极114；所述漏极孔V1贯穿所述第二层间绝缘层127、第一层间绝缘层126、第二栅极绝缘层125与第一栅极绝缘层124，暴露出所述半导体层111的另一侧。进一步地，所述柔性衬底121的材料为聚酰亚胺(Polyimide，PI)；所述第一缓冲层122与第二缓冲层123的材料均为氧化硅(SiOx)、氮化硅(SiNx)或二者的组合；所述半导体层111的材料不限于为非晶硅、低温多晶硅(Low Temperature Poly-silicon，LTPS)、金属氧化物半导体、锗(Ge)等；所述第一层间绝缘层126的材料为SiOx、SiNx或二者的组合，所述第二层间绝缘层127的材料为有机光阻；所述平坦层3的材料为PI。The structure of the thin film transistor 11 on the array substrate 1 is not limited, and may be a single gate type, a double gate type, a top gate type, a bottom gate type, etc., taking the top double gate type structure shown in FIG. 2 as an example. The array substrate 1 includes a flexible substrate 121, a first buffer layer 122 overlying the flexible substrate 121, a second buffer layer 123 overlying the first buffer layer 122, and a second buffer layer. a semiconductor layer 111 on 123, a first gate insulating layer 124 overlying the second buffer layer 123 and the semiconductor layer 111, and a first gate insulating layer 124 over the semiconductor layer 111. a first gate 112, a second gate insulating layer 125 covering the first gate insulating layer 124 and the first gate 112, and a second gate above the first gate 112. a second gate 113 on the insulating layer 125, a first interlayer insulating layer 126 covering the second gate insulating layer 125 and the second gate 113, and covering the first interlayer insulating layer 126 a second interlayer insulating layer 127 and a second interlayer insulating layer 127 are disposed through the second interlayer insulating layer 127 and the first interlayer. The edge layer 126, the second gate insulating layer 125 and the source hole V3 of the first gate insulating layer 124 are in contact with the source 114 on the side of the semiconductor layer 111; the drain hole V1 extends through the second layer The insulating layer 127, the first interlayer insulating layer 126, the second gate insulating layer 125, and the first gate insulating layer 124 expose the other side of the semiconductor layer 111. Further, the material of the flexible substrate 121 is Polyimide (PI); the materials of the first buffer layer 122 and the second buffer layer 123 are both silicon oxide (SiOx) and silicon nitride (SiNx). Or a combination of the two; the material of the semiconductor layer 111 is not limited to amorphous silicon, low temperature poly-silicon (LTPS), metal oxide semiconductor, germanium (Ge), etc.; The material of the insulating layer 126 is SiOx, SiNx or a combination of the two, the material of the second interlayer insulating layer 127 is an organic photoresist; and the material of the flat layer 3 is PI.
所述复合电极5集阳极与所述薄膜晶体管11的漏极于一体。结合图2与图3，所述复合电极5包括与所述薄膜晶体管11的半导体层111相接触的部分51及于所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51之上层叠的有金属层52与叠加层53。需要说明的是，附图3中仅为膜层数量和顺序的示意图，实际工艺中过孔V中的各层形貌厚度并不均匀，会基本填满过孔V。所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51的材料为导电的金属氧化物，如氧化铟锡(Indium Tin Oxide，ITO)、氧化铟锌(Indium Zinc Oxide，IZO)等，所述金属层52以银(Ag)、铜(Cu)等导电性较好的金属为材料，所述叠加层53以ITO、IZO等导电的金属氧化物为材料，即所述复合电极5可为ITO/Ag/ITO、ITO/Ag/IZO、ITO/Cu/ITO、ITO/Cu/IZO、IZO/Ag/IZO、IZO/Ag/ITO、IZO/Cu/IZO、IZO/Cu/ITO等叠层结构。The anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11. 2 and 3, the composite electrode 5 includes a portion 51 that is in contact with the semiconductor layer 111 of the thin film transistor 11 and a portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11. The metal layer 52 and the overlying layer 53 are laminated on top. It should be noted that FIG. 3 is only a schematic diagram of the number and order of the film layers. In the actual process, the thickness of each layer in the via hole V is not uniform, and the via hole V is substantially filled. The material of the portion 51 of the composite electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). The metal layer 52 is made of a metal having good conductivity such as silver (Ag) or copper (Cu), and the superposed layer 53 is made of a conductive metal oxide such as ITO or IZO, that is, the composite. The electrode 5 may be ITO/Ag/ITO, ITO/Ag/IZO, ITO/Cu/ITO, ITO/Cu/IZO, IZO/Ag/IZO, IZO/Ag/ITO, IZO/Cu/IZO, IZO/Cu/ A laminated structure such as ITO.
由于所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51的材料为ITO等导电的金属氧化物，ITO等导电的金属氧化物本身具有较好的导电性能，所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51在减轻金属与半导体之间的费米能级钉扎效应的同时又不会引起较大的串联电阻，能够大幅降低金属-半导体的接触电阻；由于所述复合电极5集阳极与薄膜晶体管11的漏极为一体，消除了阳极与薄膜晶体管11的漏极之间的接触电阻；这两方面综合起来能够大幅降低OLED显示器的导通电阻，减少能耗。Since the material of the portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as ITO, the conductive metal oxide such as ITO itself has good electrical conductivity, and the composite The portion 51 of the electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the metal-semiconductor Contact resistance; since the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11, the contact resistance between the anode and the drain of the thin film transistor 11 is eliminated; the combination of these two aspects can greatly reduce the conduction of the OLED display Resistance to reduce energy consumption.
请参阅图4，本发明还提供一种OLED背板制作方法，包括如下步骤：Referring to FIG. 4, the present invention further provides a method for fabricating an OLED backplane, comprising the following steps:
步骤S1、请参阅图5至图8，制作出阵列基板1，所述阵列基板1内设有多个呈阵列式排布的薄膜晶体管11。Step S1, referring to FIG. 5 to FIG. 8, an array substrate 1 is prepared. The array substrate 1 is provided with a plurality of thin film transistors 11 arranged in an array.
具体地，所述阵列基板1上薄膜晶体管11的结构形式不限，可以为单栅型、双栅型、顶栅型、底栅型等，以图8所示的顶部双栅型结构为例，所述阵列基板1包括柔性衬底121、覆盖在所述柔性衬底121上的第一缓冲层122、覆盖在所述第一缓冲层122上的第二缓冲层123、设在所述第二缓冲层123上的半导体层111、覆盖在所述第二缓冲层123与半导体层111上的第一栅极绝缘层124、于所述半导体层111上方设在所述第一栅极绝缘层124上的第一栅极112、覆盖在所述第一栅极绝缘层124与第一栅极112上的第二栅极绝缘层125、于所述第一栅极112上方设在所述第二栅极绝缘层125上的第二栅极113、覆盖在所述第二栅极绝缘层125与第二栅极113上的第一层间绝缘层126、覆盖在所述第一层间绝缘层126上的第二层间绝缘层127以及设在所述第二层间绝缘层127上经由贯穿所述第二层间绝缘层 127、第一层间绝缘层126、第二栅极绝缘层125与第一栅极绝缘层124的源极孔V3接触所述半导体层111一侧的源极114；一漏极孔V1贯穿所述第二层间绝缘层127、第一层间绝缘层126、第二栅极绝缘层125与第一栅极绝缘层124，暴露出所述半导体层111的另一侧。进一步地，所述柔性衬底121的材料为PI；所述第一缓冲层122与第二缓冲层123的材料均为SiOx、SiNx或二者的组合；所述半导体层111的材料不限于为非晶硅、低温多晶硅、金属氧化物半导体、锗等；所述第一层间绝缘层126的材料为SiOx、SiNx或二者的组合，所述第二层间绝缘层127的材料为有机光阻；所述平坦层3的材料为PI。Specifically, the structure of the thin film transistor 11 on the array substrate 1 is not limited, and may be a single gate type, a double gate type, a top gate type, a bottom gate type, etc., and the top double gate type structure shown in FIG. 8 is taken as an example. The array substrate 1 includes a flexible substrate 121, a first buffer layer 122 overlying the flexible substrate 121, and a second buffer layer 123 overlying the first buffer layer 122. a semiconductor layer 111 on the second buffer layer 123, a first gate insulating layer 124 covering the second buffer layer 123 and the semiconductor layer 111, and a first gate insulating layer above the semiconductor layer 111. a first gate 112 on the 124, a second gate insulating layer 125 covering the first gate insulating layer 124 and the first gate 112, and the first gate 112 is disposed above the first gate 112 a second gate 113 on the second gate insulating layer 125, a first interlayer insulating layer 126 covering the second gate insulating layer 125 and the second gate 113, and covering the first interlayer insulating layer a second interlayer insulating layer 127 on the layer 126 and a second interlayer insulating layer 127 are provided through the second interlayer insulating layer 127. An interlayer insulating layer 126, a second gate insulating layer 125 and a source hole V3 of the first gate insulating layer 124 are in contact with the source 114 of the semiconductor layer 111; a drain hole V1 extends through the second The interlayer insulating layer 127, the first interlayer insulating layer 126, the second gate insulating layer 125, and the first gate insulating layer 124 expose the other side of the semiconductor layer 111. Further, the material of the flexible substrate 121 is PI; the materials of the first buffer layer 122 and the second buffer layer 123 are both SiOx, SiNx or a combination of the two; the material of the semiconductor layer 111 is not limited to Amorphous silicon, low temperature polysilicon, metal oxide semiconductor, germanium, etc.; the material of the first interlayer insulating layer 126 is SiOx, SiNx or a combination of the two, and the material of the second interlayer insulating layer 127 is organic light. The material of the flat layer 3 is PI.
所述步骤S1在制作所述阵列基板1的过程中，在成膜所述第一层间绝缘层126后对所述第一层间绝缘层126、第二栅极绝缘层125与第一栅极绝缘层124进行蚀刻，暴露出所述半导体层111的一侧与另一侧；然后在所述第一层间绝缘层126上成膜所述第二层间绝缘层127并通过曝光或干法蚀刻对所述第二层间绝缘层127进行图案化处理，形成所述漏极孔V1与源极孔V3；接下来在所述第二层间绝缘层127上沉积金属薄膜并进行蚀刻，只保留填充所述源极孔V3的部分金属薄膜形成所述源极114，而将填充所述漏极孔V1的部分金属薄膜蚀刻掉，所述漏极孔V1暴露。In the step S1, in the process of fabricating the array substrate 1, the first interlayer insulating layer 126, the second gate insulating layer 125 and the first gate are formed after the first interlayer insulating layer 126 is formed. The pole insulating layer 124 is etched to expose one side and the other side of the semiconductor layer 111; then the second interlayer insulating layer 127 is formed on the first interlayer insulating layer 126 and exposed or dried Etching the second interlayer insulating layer 127 to form the drain hole V1 and the source hole V3; subsequently depositing a metal thin film on the second interlayer insulating layer 127 and etching, Only a portion of the metal film filling the source hole V3 is left to form the source electrode 114, and a portion of the metal film filling the drain hole V1 is etched away, and the drain hole V1 is exposed.
步骤S2、请参阅图9，在所述阵列基板1上涂布以PI为材料的平坦层3，并通过曝光或干法蚀刻对所述平坦层3进行图案化处理，形成贯穿所述平坦层3并与所述漏极孔V1连通的通孔V2，获得由所述通孔V2与漏极孔V1共同构成的过孔V。Step S2, referring to FIG. 9, a flat layer 3 made of PI is coated on the array substrate 1, and the flat layer 3 is patterned by exposure or dry etching to form a through layer. 3 and a via hole V2 communicating with the drain hole V1, a via hole V formed by the via hole V2 and the drain hole V1 is obtained.
步骤S3、请参阅图10，采用现有的制作OLED阳极的工艺在所述平坦层3上成膜复合电极5，所述复合电极5经由所述过孔V接触所述薄膜晶体管11的半导体层111。Step S3, referring to FIG. 10, a composite electrode 5 is formed on the flat layer 3 by a conventional process for fabricating an OLED anode, and the composite electrode 5 contacts the semiconductor layer of the thin film transistor 11 via the via hole V. 111.
具体地，所述复合电极5集阳极与所述薄膜晶体管11的漏极于一体。结合图10与图3，所述复合电极5包括与所述薄膜晶体管11的半导体层111相接触的部分51及于所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51之上层叠的有金属层52与叠加层53。所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51材料为导电的金属氧化物，如ITO、IZO等，所述金属层52以Ag、Cu等导电性较好的金属为材料，所述叠加层53以ITO、IZO等导电的金属氧化物为材料，即所述复合电极5可为ITO/Ag/ITO、ITO/Ag/IZO、ITO/Cu/ITO、ITO/Cu/IZO、IZO/Ag/IZO、IZO/Ag/ITO、IZO/Cu/IZO、IZO/Cu/ITO等叠层结构。Specifically, the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11. 10 and 3, the composite electrode 5 includes a portion 51 that is in contact with the semiconductor layer 111 of the thin film transistor 11 and a portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11. The metal layer 52 and the overlying layer 53 are laminated on top. The portion 51 of the composite electrode 5 that is in contact with the semiconductor layer 111 of the thin film transistor 11 is made of a conductive metal oxide such as ITO, IZO, etc., and the metal layer 52 is made of a metal having good conductivity such as Ag or Cu. For the material, the superposed layer 53 is made of a conductive metal oxide such as ITO or IZO, that is, the composite electrode 5 may be ITO/Ag/ITO, ITO/Ag/IZO, ITO/Cu/ITO, ITO/Cu. Laminated structure of /IZO, IZO/Ag/IZO, IZO/Ag/ITO, IZO/Cu/IZO, IZO/Cu/ITO, etc.
由于所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部 分51的材料为ITO等导电的金属氧化物，ITO等导电的金属氧化物本身具有较好的导电性能，所述复合电极5与所述薄膜晶体管11的半导体层111相接触的部分51在减轻金属与半导体之间的费米能级钉扎效应的同时又不会引起较大的串联电阻，能够大幅降低金属-半导体的接触电阻；由于所述复合电极5集阳极与薄膜晶体管11的漏极为一体，消除了阳极与薄膜晶体管11的漏极之间的接触电阻；这两方面综合起来能够大幅降低OLED显示器的导通电阻，减少能耗。Since the material of the portion 51 where the composite electrode 5 is in contact with the semiconductor layer 111 of the thin film transistor 11 is a conductive metal oxide such as ITO, the conductive metal oxide such as ITO itself has good electrical conductivity, and the composite The portion 51 of the electrode 5 in contact with the semiconductor layer 111 of the thin film transistor 11 reduces the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the metal-semiconductor Contact resistance; since the anode of the composite electrode 5 is integrated with the drain of the thin film transistor 11, the contact resistance between the anode and the drain of the thin film transistor 11 is eliminated; the combination of these two aspects can greatly reduce the conduction of the OLED display Resistance to reduce energy consumption.
由于该步骤S3制作出的所述复合电极5已经能够大幅降低OLED显示器的导通电阻，减少能耗，后续步骤无需再以降低阳极与薄膜晶体管11的漏极之间的接触电阻为目的来进行金属退火处理，即可以省去金属退火处理，简化制程。Since the composite electrode 5 fabricated in the step S3 can greatly reduce the on-resistance of the OLED display and reduce the power consumption, the subsequent steps need not be performed for the purpose of reducing the contact resistance between the anode and the drain of the thin film transistor 11. Metal annealing treatment can eliminate metal annealing and simplify the process.
该OLED背板制作方法还进一步包括步骤S4、请参照图2，在所述复合电极5与平坦层3上沉积像素定义层7并通过干法蚀刻进行图案化处理，形成围拢所述复合电极5的像素开口71。The OLED backplane manufacturing method further includes a step S4, referring to FIG. 2, depositing a pixel defining layer 7 on the composite electrode 5 and the flat layer 3, and performing patterning processing by dry etching to form the composite electrode 5 Pixel opening 71.
综上所述，本发明的OLED背板结构，设置有集阳极与薄膜晶体管的漏极于一体的复合电极，一方面所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物，在减轻金属与半导体之间的费米能级钉扎效应的同时又不会引起较大的串联电阻，能够大幅降低金属-半导体的接触电阻，另一方面，阳极与所述薄膜晶体管的漏极成为一体，消除了阳极与薄膜晶体管的漏极之间的接触电阻，从而能够大幅降低OLED显示器的导通电阻，减少能耗。本发明的OLED背板制作方法，将阳极与薄膜晶体管的漏极合并在一起制程，形成复合电极，能够大幅降低金属-半导体的接触电阻，消除阳极与薄膜晶体管漏极之间的接触电阻，从而大幅降低OLED显示器的导通电阻，减少能耗，同时省去了金属退火处理，简化了制程。In summary, the OLED backplane structure of the present invention is provided with a composite electrode in which the anode and the drain of the thin film transistor are integrated, and the material of the portion where the composite electrode is in contact with the semiconductor layer of the thin film transistor is The conductive metal oxide can reduce the Fermi level pinning effect between the metal and the semiconductor without causing a large series resistance, and can greatly reduce the contact resistance of the metal-semiconductor. On the other hand, the anode and the The drain of the thin film transistor is integrated, eliminating the contact resistance between the anode and the drain of the thin film transistor, thereby greatly reducing the on-resistance of the OLED display and reducing power consumption. In the OLED backplane manufacturing method of the present invention, the anode and the drain of the thin film transistor are combined to form a composite electrode, which can greatly reduce the contact resistance of the metal-semiconductor and eliminate the contact resistance between the anode and the drain of the thin film transistor, thereby The on-resistance of the OLED display is greatly reduced, the energy consumption is reduced, and the metal annealing treatment is omitted, which simplifies the process.
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明的权利要求的保护范围。In the above, various other changes and modifications can be made in accordance with the technical solutions and technical concept of the present invention, and all such changes and modifications should be protected by the claims of the present invention. range.

Claims (13)

  1. 一种OLED背板结构，包括：An OLED backplane structure includes:
    阵列基板，所述阵列基板内设有多个呈阵列式排布的薄膜晶体管；An array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
    设在所述阵列基板之上的平坦层；a flat layer disposed on the array substrate;
    以及设在所述平坦层上经由过孔接触所述薄膜晶体管的半导体层的复合电极；And a composite electrode disposed on the flat layer contacting the semiconductor layer of the thin film transistor via a via;
    所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物。The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
  2. 如权利要求1所述的OLED背板结构，其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层。The OLED backplane structure according to claim 1, wherein a metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor.
  3. 如权利要求1所述的OLED背板结构，其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为ITO或IZO。The OLED backplane structure according to claim 1, wherein a material of a portion of the composite electrode in contact with a semiconductor layer of the thin film transistor is ITO or IZO.
  4. 如权利要求2所述的OLED背板结构，其中，所述金属层的材料为Ag或Cu。The OLED backplane structure according to claim 2, wherein the material of the metal layer is Ag or Cu.
  5. 如权利要求2所述的OLED背板结构，其中，所述叠加层的材料为ITO或IZO。The OLED back sheet structure according to claim 2, wherein the material of the superposed layer is ITO or IZO.
  6. 如权利要求1所述的OLED背板结构，其中，所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The OLED backplane structure according to claim 1, wherein the via hole comprises a through hole penetrating the flat layer and a drain hole communicating with the through hole;
    所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer The second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
    所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧。The drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
  7. 一种OLED背板制作方法，包括如下步骤：An OLED backplane manufacturing method includes the following steps:
    步骤S1、制作出阵列基板，所述阵列基板内设有多个呈阵列式排布的薄膜晶体管；Step S1, forming an array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
    步骤S2、在所述阵列基板上涂布平坦层，并对所述平坦层进行图案化处理，获得过孔；Step S2, coating a flat layer on the array substrate, and patterning the flat layer to obtain a via hole;
    步骤S3、在所述平坦层上成膜复合电极，所述复合电极经由所述过孔接触所述薄膜晶体管的半导体层；Step S3, forming a composite electrode on the flat layer, the composite electrode contacting the semiconductor layer of the thin film transistor via the via hole;
    所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物。The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide.
  8. 如权利要求7所述的OLED背板制作方法，其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层。The method of fabricating an OLED back sheet according to claim 7, wherein a metal layer and a superposed layer are laminated on a portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor.
  9. 如权利要求7所述的OLED背板制作方法，其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为ITO或IZO。The OLED back sheet manufacturing method according to claim 7, wherein a material of a portion of the composite electrode in contact with a semiconductor layer of the thin film transistor is ITO or IZO.
  10. 如权利要求8所述的OLED背板制作方法，其中，所述金属层的材料为Ag或Cu。The method of fabricating an OLED back sheet according to claim 8, wherein the material of the metal layer is Ag or Cu.
  11. 如权利要求8所述的OLED背板制作方法，其中，所述叠加层的材料为ITO或IZO。The OLED back sheet manufacturing method according to claim 8, wherein the material of the superposed layer is ITO or IZO.
  12. 如权利要求7所述的OLED背板制作方法，其中，所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The OLED backplane manufacturing method according to claim 7, wherein the via hole comprises a through hole penetrating the flat layer and a drain hole communicating with the through hole;
    所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer a source of the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer contacting the source of the semiconductor layer; the drain hole penetrating through Depicting the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer The other side of the conductor layer;
    所述步骤S1在制作所述阵列基板的过程中，在成膜所述第一层间绝缘层后对所述第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层进行蚀刻，暴露出所述半导体层的一侧与另一侧；然后在所述第一层间绝缘层上成膜所述第二层间绝缘层并进行图案化处理，形成所述漏极孔与源极孔；接下来在所述第二层间绝缘层上沉积金属薄膜并进行蚀刻，只保留填充所述源极孔的部分金属薄膜形成所述源极，而将填充所述漏极孔的部分金属薄膜蚀刻掉，所述漏极孔暴露。In the step S1, in the process of fabricating the array substrate, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer are performed after the first interlayer insulating layer is formed. Etching, exposing one side and the other side of the semiconductor layer; then forming the second interlayer insulating layer on the first interlayer insulating layer and performing a patterning process to form the drain hole and a source hole; then depositing a metal film on the second interlayer insulating layer and etching, leaving only a portion of the metal film filling the source hole to form the source, and filling the drain hole A portion of the metal film is etched away and the drain hole is exposed.
  13. 一种OLED背板结构，包括：An OLED backplane structure includes:
    阵列基板，所述阵列基板内设有多个呈阵列式排布的薄膜晶体管；An array substrate, wherein the array substrate is provided with a plurality of thin film transistors arranged in an array;
    设在所述阵列基板之上的平坦层；a flat layer disposed on the array substrate;
    以及设在所述平坦层上经由过孔接触所述薄膜晶体管的半导体层的复合电极；And a composite electrode disposed on the flat layer contacting the semiconductor layer of the thin film transistor via a via;
    所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为导电的金属氧化物；The material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is a conductive metal oxide;
    其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分之上层叠有金属层及叠加层；Wherein the metal layer and the superposed layer are laminated on the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor;
    其中，所述复合电极与所述薄膜晶体管的半导体层相接触的部分的材料为ITO或IZO；Wherein the material of the portion of the composite electrode that is in contact with the semiconductor layer of the thin film transistor is ITO or IZO;
    其中，所述金属层的材料为Ag或Cu，所述叠加层的材料为ITO或IZO；Wherein the material of the metal layer is Ag or Cu, and the material of the superposed layer is ITO or IZO;
    其中，所述过孔包括贯穿所述平坦层的通孔及与所述通孔连通的漏极孔；The via hole includes a through hole penetrating the flat layer and a drain hole communicating with the through hole;
    所述阵列基板包括柔性衬底、覆盖在所述柔性衬底上的第一缓冲层、覆盖在所述第一缓冲层上的第二缓冲层、设在所述第二缓冲层上的半导体层、覆盖在所述第二缓冲层与半导体层上的第一栅极绝缘层、于所述半导体层上方设在所述第一栅极绝缘层上的第一栅极、覆盖在所述第一栅极绝缘层与第一栅极上的第二栅极绝缘层、于所述第一栅极上方设在所述第二栅极绝缘层上的第二栅极、覆盖在所述第二栅极绝缘层与第二栅极上的第一层间绝缘层、覆盖在所述第一层间绝缘层上的第二层间绝缘层以及设在所述第二层间绝缘层上经由贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层的源极孔接触所述半导体层一侧的源极；The array substrate includes a flexible substrate, a first buffer layer overlying the flexible substrate, a second buffer layer overlying the first buffer layer, and a semiconductor layer disposed on the second buffer layer a first gate insulating layer covering the second buffer layer and the semiconductor layer, and a first gate disposed on the first gate insulating layer above the semiconductor layer, covering the first a gate insulating layer and a second gate insulating layer on the first gate, a second gate disposed on the second gate insulating layer above the first gate, covering the second gate a first insulating layer on the second insulating layer, a second interlayer insulating layer covering the first interlayer insulating layer, and a second interlayer insulating layer on the second interlayer insulating layer The second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the source hole of the first gate insulating layer contact the source of the semiconductor layer side;
    所述漏极孔贯穿所述第二层间绝缘层、第一层间绝缘层、第二栅极绝缘层与第一栅极绝缘层，暴露出所述半导体层的另一侧。The drain hole penetrates the second interlayer insulating layer, the first interlayer insulating layer, the second gate insulating layer and the first gate insulating layer to expose the other side of the semiconductor layer.
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