CN109003989B - Array substrate, preparation method thereof, display panel and display device - Google Patents
Array substrate, preparation method thereof, display panel and display device Download PDFInfo
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- CN109003989B CN109003989B CN201810841631.4A CN201810841631A CN109003989B CN 109003989 B CN109003989 B CN 109003989B CN 201810841631 A CN201810841631 A CN 201810841631A CN 109003989 B CN109003989 B CN 109003989B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
Abstract
The invention discloses an array substrate and a preparation method thereof, a display panel and a display device, relating to the technical field of display, wherein the array substrate is provided with a display area and a non-display area, the display area comprises an opening area and a non-opening area, and the array substrate comprises: a substrate base plate; a first buffer layer covering the first surface of the substrate base plate; the first isolation layer is arranged on the surface of the first buffer layer, which is far away from the substrate base plate; the second buffer layer covers the surface of the first isolation layer, which is far away from the substrate base plate; the pixel driving circuit is arranged on one side of the second buffer layer, which is far away from the substrate and comprises a hole digging region; the orthographic projections of the first isolation layer and the second buffer layer on the substrate are overlapped with the hole digging region, and the orthographic projections of the first isolation layer and the second buffer layer on the substrate are not overlapped with the opening region. By introducing the first isolation layer, the problem of over-etching or under-etching caused in the process of grooving the opening area and the hole digging area of the array substrate is effectively solved.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate, a display panel and a display device.
Background
In recent years, with the development of Liquid crystal display technology, the application fields of Liquid Crystal Display (LCD) devices, particularly color LCD devices, have been widened. Liquid crystal display devices have been widely used for televisions or monitors because of their superiority in displaying moving images and high contrast. In general, a liquid crystal display device generates an image using optical anisotropy and polarization characteristics of liquid crystal molecules. A liquid crystal display device generally includes a substrate and a second substrate which are oppositely disposed and a liquid crystal layer between the first substrate and the second substrate, and liquid crystal molecules in the liquid crystal layer are reoriented by an electric field. Accordingly, the orientation of the liquid crystal molecules is changed according to the direction of the electric field and the light transmittance of the liquid crystal panel is also changed, thereby realizing a display function of an image.
Organic Light-Emitting diodes (OLEDs) have also become a very popular flat panel display industry in the sea and abroad, and are known as the next generation of "star" flat panel display technology, mainly because OLEDs have the characteristics of low power consumption, self-luminescence, fast response time, high luminous efficiency, thin panel thickness, capability of manufacturing large-sized and bendable panels, simple manufacturing process, low cost, and the like. The organic electroluminescent device includes a plurality of organic light emitting structures including a reflective electrode (anode), a light emitting material layer, and a semi-reflective electrode (cathode). Holes and electrons are injected into the light emitting material layer from the anode and the cathode, respectively, and energy is generated when excitons are generated in combination in the light emitting material layer and the excitons are shifted from an excited state to a ground state, thereby realizing light emission.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a method for manufacturing the same, a display panel, and a display device, in which a first isolation layer is introduced between a pixel driving circuit and a first buffer layer, an opening region and a via region of the array substrate can be etched separately, and the problem of over-etching or under-etching caused in the process of performing a trench digging on the opening region and the via region of the array substrate is effectively improved.
In a first aspect, the present application provides an array substrate, provided with a display area and a non-display area, the display area includes an opening area and a non-opening area, the array substrate includes:
a substrate base plate;
the first buffer layer covers the first surface of the substrate base plate;
the first isolation layer is arranged on the surface, far away from the substrate base plate, of the first buffer layer;
the second buffer layer covers the surface, far away from the substrate base plate, of the first isolation layer;
the pixel driving circuit is arranged on one side, far away from the substrate, of the second buffer layer and comprises a hole digging region;
wherein, the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are overlapped with the hole digging region, and the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are not overlapped with the opening region.
In a second aspect, the present application provides a method for manufacturing an array substrate, the array substrate being provided with a display area and a non-display area, the display area including an open area and a non-open area, the method comprising:
providing a substrate base plate;
manufacturing a first buffer layer, and enabling the first buffer layer to cover the first surface of the substrate base plate;
manufacturing a first isolation layer, and enabling the first isolation layer to cover the surface of the first buffer layer, which is far away from the substrate base plate;
manufacturing a second buffer layer, and enabling the second buffer layer to cover the surface, far away from the substrate, of the first isolation layer;
and manufacturing a pixel driving circuit on one side of the second buffer layer, which is far away from the substrate base plate, forming the opening area and the hole digging area by adopting a step-by-step etching mode, wherein the hole digging area is positioned in the non-opening area, so that orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are overlapped with the hole digging area, and the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are not overlapped with the opening area.
In a third aspect, the present application provides a display panel including the array substrate provided in the present application.
In a fourth aspect, the present application provides a display device comprising the display panel provided by the present application.
Compared with the prior art, the array substrate, the preparation method thereof, the display panel and the display device provided by the invention at least realize the following beneficial effects:
in the array substrate, the preparation method thereof, the display panel and the display device provided by the application, the first isolation layer and the second buffer layer are introduced at one side of the first buffer layer far away from the substrate, the hole digging region in the pixel driving circuit is arranged at one side of the second buffer layer far away from the substrate and is overlapped with the first isolation layer and the second buffer layer, the opening region is not overlapped with the first isolation layer and the second buffer layer, the grooving design is needed in the process of forming the hole digging area and the opening area, the grooving etching process of the opening area and the grooving etching process of the hole digging area can be separately carried out after the first isolating layer is introduced, the etching time corresponding to the hole digging area and the opening area can be accurately controlled respectively, therefore, the etching precision of the hole digging area and the opening area is improved, and the problem that the hole digging area is over-etched or the opening area is under-etched due to too large area difference of the hole digging area and the opening area when etching is carried out is effectively solved.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a top view of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a top view of a sub-pixel unit in an array substrate according to an embodiment of the present disclosure;
FIG. 3 is an AA' cross-sectional view of the corresponding sub-pixel element of FIG. 2;
FIG. 4 is another cross-sectional view AA' of the corresponding sub-pixel cell of FIG. 2;
FIG. 5 is another cross-sectional view AA' of the corresponding sub-pixel cell of FIG. 2;
FIG. 6 is a cross-sectional view of a BB' of the sub-pixel cell of FIG. 2;
fig. 7 is a flowchart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 8 is a schematic view illustrating a first buffer layer formed on a substrate in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 9 is a schematic view illustrating a first isolation layer formed in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 10 is a schematic view illustrating a second buffer layer formed in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 11 is a structural view of an array substrate formed by a method for manufacturing an array substrate according to an embodiment of the present disclosure;
FIG. 12 is a schematic view showing a color resist layer and a planarization layer formed on the substrate of FIG. 11;
FIG. 13 is a flow chart showing the formation of an opening region and a dug region by a step-by-step etching method;
fig. 14 is a diagram illustrating a forming process of an array substrate in a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 15 is a schematic view showing that the interlayer insulating layer and the gate insulating layer in the first region are removed by a first etching process;
FIG. 16 is a schematic view showing that a second etching process is performed to remove the interlayer insulating layer and the gate insulating layer in the second region;
FIG. 17 is a schematic view of a third etching process for removing the first isolation layer in the first region;
FIG. 18 is a schematic view showing a photoresist applied on an interlayer insulating layer;
FIG. 19 is a schematic view showing exposure development of the photoresist of FIG. 18;
fig. 20 is a schematic view illustrating the interlayer insulating layer, the gate insulating layer, and the second buffer layer corresponding to the first region in fig. 19 after being etched;
FIG. 21 is a schematic view showing the photoresist of FIG. 20 after ashing;
fig. 22 is a schematic view showing the interlayer insulating layer and the gate insulating layer corresponding to the second region after etching;
FIG. 23 is a schematic view of a third etching process performed on the first isolation layer;
FIG. 24 is a schematic view showing the formation of a semiconductor active layer after all of the photoresist has been removed based on FIG. 23;
fig. 25 is a schematic view of a display panel according to an embodiment of the present disclosure;
fig. 26 is a schematic view illustrating a display device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
In the prior art, in order to improve the transmittance of the display panel, a trench is usually formed in a pixel opening area of the array substrate, and since a pixel driving circuit on the array substrate usually includes a trench area, the trench area is also formed by the trench design. Because the regional area of the digging groove that the opening area corresponds is greater than the regional area of the digging groove that the digging hole region corresponds far away, the etching process is gone on simultaneously usually, at the digging groove etching in-process, plasma mainly gathers in the regional digging groove that the area is great, make its reaction rate be greater than the digging hole region far away, make the opening area and the regional etching time that corresponds of digging hole greatly inequality, consequently lead to the unable accurate management and control of etching time, thereby probably lead to the digging hole region to appear the phenomenon of underetching or lead to the opening area to appear the phenomenon of overetching.
In view of the above, the present invention provides an array substrate, a method for manufacturing the same, a display panel, and a display device, in which a first isolation layer is introduced between a pixel driving circuit and a first buffer layer, an opening region and a via region of the array substrate can be etched separately, and the problem of over-etching or under-etching caused in the process of performing a trench digging on the opening region and the via region of the array substrate is effectively improved.
Fig. 1 is a top view of an array substrate according to an embodiment of the present disclosure, fig. 2 is a top view of a sub-pixel unit in an array substrate according to an embodiment of the present disclosure, fig. 3 is an AA' cross-sectional view of the corresponding sub-pixel unit in fig. 2, and referring to fig. 1 to fig. 3, an array substrate 100 according to an embodiment of the present disclosure is provided with a display area 11 and a non-display area 12, the display area 11 includes an opening area 21 and a non-opening area 22, and the array substrate 100 includes:
a base substrate 20;
a first buffer layer 31 covering the first surface of the substrate base plate 20;
a first isolation layer 32 disposed on a surface of the first buffer layer 31 away from the substrate base plate 20;
a second buffer layer 33 covering the surface of the first isolation layer 32 far from the substrate base plate 20;
a pixel drive circuit 40 located in the non-opening region 22, the pixel drive circuit 40 being disposed on a side of the second buffer layer 33 away from the substrate 20 and including a cutout region 23;
wherein, the orthographic projections of the first isolation layer 32 and the second buffer layer 33 on the substrate base plate 20 are overlapped with the hole digging region 23, and the orthographic projections of the first isolation layer 32 and the second buffer layer 33 on the substrate base plate 20 are not overlapped with the opening region 21.
Specifically, referring to fig. 1 and fig. 2, the array substrate 100 provided in the embodiment of the present application is provided with a plurality of gate lines 13 extending along a first direction and arranged along a second direction, a plurality of data lines 14 arranged along the first direction and extending along the second direction, wherein the gate lines 13 and the data lines 14 cross to define a plurality of sub-pixel units 15; the display area 11 is provided with an opening area 21 and a non-opening area 22, wherein the opening area 21 refers to an effective area where each sub-pixel unit 15 can transmit light, and the other areas in the display area 11 except the opening area 21, for example, the area corresponding to the pixel driving circuit 40 is the non-opening area 22. It should be noted that fig. 1 only schematically shows the relative positional relationship among the gate lines 13, the data lines 14, and the sub-pixel units 15, and does not represent actual size and number. Referring to fig. 2 and fig. 3, in the array substrate 100 provided in the embodiment of the present disclosure, the driving circuit located in the non-opening region 22 is disposed on a side of the second buffer layer 33 away from the array substrate 100, that is, the hole-digging region 23 in the driving circuit overlaps the second buffer layer 33 and the first isolation layer 32; the opening area 21 is not overlapped with the second buffer layer 33 and the first isolation layer 32, and the second buffer layer 33 and the first isolation layer 32 corresponding to the opening area 21 are etched away in the process of preparing the array substrate 100. In the process of preparing the array substrate 100, the trench digging design is respectively carried out on the hole digging area 23 and the opening area 21, after the first isolation layer 32 is introduced, the process of carrying out trench digging etching on the hole digging area 23 and the opening area 21 can be separately carried out, so that the time of carrying out trench digging etching on the hole digging area 23 and the opening area 21 can be respectively accurately controlled, the problem of over-etching or under-etching in the process of carrying out etching on the hole digging area 23 and the opening area 21 in the prior art is effectively avoided, and the accuracy of trench digging etching in the array substrate 100 is favorably improved. In addition, in the preparation process of the array substrate 100, the first isolation layer 32 corresponding to the opening area 21 and the plurality of films located on the side of the first isolation layer 32 far away from the substrate 20 are etched in the grooving etching process, so that the film structure corresponding to the opening area 21 is simple finally, thereby being beneficial to improving the penetration rate of the opening area 21 of the array substrate 100 and further being beneficial to improving the penetration rate of the whole array substrate 100. Moreover, this application is favorable to playing the effect of protection to first buffer layer 31 after introducing first isolation layer, avoids appearing impaired phenomenon at the first buffer layer 31 in the etching process to be favorable to guaranteeing the integrality of first buffer layer.
It should be noted that, in order to improve the transmittance of the display panel 400, the array substrate 100 provided in the above embodiments of the present application may be applied to the liquid crystal display panel 400, and may also be applied to the organic electroluminescent display panel 400, when the array substrate is applied to the organic electroluminescent display panel 400, only the planarization layer 50 may be filled at the position corresponding to the opening area 21, please refer to fig. 4, and fig. 4 is another AA' cross-sectional view of the corresponding sub-pixel unit 15 in fig. 2, which is not specifically limited in this application, and the following description will be made on a specific structure of the array substrate 100 when the array substrate is applied to the liquid crystal display panel 400.
Optionally, referring to fig. 5, fig. 5 is another AA' cross-sectional view of the corresponding sub-pixel unit 15 in fig. 2, where the array substrate 100 provided in the embodiment of the present application further includes: a color resist layer 60 disposed on the surface of the first buffer layer 31 away from the base substrate 20 and in the opening area 21; and the number of the first and second groups,
and a planarization layer 50 covering the color resist layer 60 and the surface of the pixel driving circuit 40 away from the substrate 20.
Specifically, referring to fig. 5, the slotted region corresponding to the opening region 21 is filled with a color resistor, in the array substrate 100 provided in the embodiment of the present application, the sub-pixel unit 15 may include a red sub-pixel unit 15, a green sub-pixel unit 15, and a blue sub-pixel unit 15, and correspondingly, the red sub-pixel unit 15 is filled with the red color resistor, the green sub-pixel unit 15 is filled with the green color resistor, and the blue sub-pixel unit 15 is filled with the blue color resistor. The color resist layer 60 and the surface of the pixel driving circuit 40 away from the substrate 20 are filled with the planarization layer 50, so as to provide a planarized surface for the subsequent film layer structure (such as the common electrode 71 layer and the pixel electrode 72 layer shown in fig. 6) of the array substrate 100.
Optionally, fig. 6 is a BB' cross-sectional view of the sub-pixel unit 15 shown in fig. 2, and with reference to fig. 5 and fig. 6, in the array substrate 100 provided in the embodiment of the present application, the pixel driving circuit 40 includes a thin film transistor 41, a height difference between the source/drain metal layer 39 of the thin film transistor 41 and the color resistance layer 60 is h, where h is less than or equal to 0.6 μm. Optionally, the thickness of the color-resisting layer 60 is D0, and D0 is less than or equal to 1.5 μm and less than or equal to 3 μm.
Specifically, in the embodiment shown in fig. 6, the thin film transistor 41 includes a semiconductor active layer 35, a gate insulating layer 36, a gate metal layer 37, an interlayer insulating layer 38, and a source drain metal layer 39, wherein the source drain metal layer 39 is electrically connected to the semiconductor active layer 35 through a via hole formed in the excavated region 23. Particularly, referring to fig. 5, the distance h between the side of the source-drain metal layer 39 away from the substrate 20 and the side of the color barrier layer 60 away from the substrate 20 is less than or equal to 0.6 μm. In the prior art, when the color resist layer 60 is disposed on the array substrate 100, the color resist layer 60 is usually disposed on the surface of the interlayer insulating layer 38 far from the substrate 20, and therefore, the height difference between the color resist layer 60 and the source/drain metal layer 39 is usually 1.4 μm or more while the height of the color resist layer 60 is kept constant. In the array substrate 100 provided in this embodiment of the application, when the trench is formed at the position of the opening area 21, the interlayer insulating layer 38, the gate insulating layer 36, the second buffer layer 33, and the first isolation layer 32 at the corresponding positions are all etched away, and the color-resist layer 60 is filled on the surface of the first buffer layer 31 away from the substrate 20, which is equivalent to moving the color-resist layer 60 downward relative to the source/drain metal layer 39, usually the height of the interlayer insulating layer 38 is greater than 0.8 μm, so the distance of downward movement of the color-resist layer 60 is also greater than 0.8 μm, which makes the height difference h between the source/drain metal layer 39 and the color-resist layer 60 less than or equal to 0.6 μm, that is, compared with the prior art, the height difference between the source/drain metal layer 39 and the color-resist layer 60 is decreased by at least 0.8 μm, the smaller the height difference is, the thickness of the planarization layer 50 required in the subsequent process of filling the planarization layer 50 is smaller, thereby improving the planarization capability in the subsequent planarization process. In addition, referring to fig. 6, since the pixel electrode 72 on the array substrate 100 and the source-drain metal layer 39 need to be electrically connected through the via 70 penetrating through the planarization layer 50, the smaller the thickness of the planarization layer 50, the easier the via 70 is formed, which is more beneficial to simplifying the process of opening the planarization layer 50 and improving the production efficiency of the array substrate 100.
It should be noted that, in the embodiment shown in fig. 6, only the thin film transistor 41 with the top gate structure is shown, that is, the gate metal layer 37 is located on the side of the semiconductor active layer 35 away from the substrate 20, in some other embodiments of the present application, the thin film transistor 41 with the bottom gate structure may also be adopted, that is, the gate metal layer 37 is located on the side of the semiconductor active layer 35 close to the substrate 20, which is not specifically limited in the present application.
Optionally, in the array substrate 100 provided in the embodiment of the present application, the first isolation layer 32 is ito. Specifically, when the ito is used as the first isolation layer 32, considering that the ito has high temperature resistance up to 600 ℃, and the ito is not prone to peeling (peeling in the application field is usually caused by dirt or water vapor on the substrate surface) at high temperature, the performance of the first isolation layer 32 is not affected when the pixel driving circuit 40 and other relevant films are formed. In addition, the indium tin oxide has better etching performance, and when the first isolation layer 32 corresponding to the opening area 21 is etched, the etching can be finished by adopting a conventional wet etching process. Of course, besides using ito as the first isolation layer 32, other materials that are high temperature resistant, easy to etch, and not easy to peel can be used instead in the embodiments of the present application, which is not particularly limited in this application.
Alternatively, referring to fig. 6, embodiments of the present application provide first isolation layer 32 having a thickness D1,
specifically, the thickness of the first isolation layer 32 is designed to be
On one hand, the first isolation layer 32 has better film forming capability, and on the other hand, the first isolation layer 32 within the thickness range is easier to etch, so that the requirement of mass production of a subsequent etching process can be met. When indium tin oxide is used as the first spacer 32, for example, the thickness of indium tin oxide can be designed to be
After film formation, the penetration rate of the first isolation layer 32 can reach 95 percentAccordingly, the use of ito as the first isolation layer 32 has no or little effect on the transmittance of the array substrate 100.
Alternatively, referring to fig. 6, embodiments of the present application provide a second buffer layer 33 having a thickness D2,
in one aspect, the thickness range is
The second buffer layer 33 can provide a flat surface for the formation of the pixel driving circuit 40, and has a small influence on the thickness of the array substrate 100, and on the other hand, can further prevent external moisture and oxygen from entering the pixel driving circuit 40 through the second buffer layer 33, thereby avoiding influencing the performance of the pixel driving circuit 40.
Alternatively, referring to fig. 6, in the array substrate 100 provided in the embodiment of the present application, the total thickness of the first buffer layer 31, the first isolation layer 32, and the second buffer layer 33 is D3, wherein,
specifically, after the first isolation layer 32 is introduced, since the thin film transistor 41 in the pixel driving circuit 40 needs to be formed in a subsequent process, the semiconductor active layer 35 in the thin film transistor 41 is formed on a flat buffer layer, which is beneficial to promoting crystallization, and therefore the second buffer layer 33 is introduced on the side of the first isolation layer 32 away from the first buffer layer 31. In addition, the first buffer layer 31 and the second buffer layer 33 can also perform a dual blocking function on external moisture and oxygen, so as to effectively prevent the external moisture and oxygen from entering the pixel driving circuit 40, and avoid affecting the performance of the pixel driving circuit 40.
Based on the same inventive concept, referring to fig. 7, the present application further provides a method for manufacturing an array substrate 100, and fig. 7 is a flowchart illustrating a method for manufacturing an array substrate 100 according to an embodiment of the present application, where the structure of the array substrate 100 is shown in fig. 1 and fig. 2, the array substrate 100 is provided with a display area 11 and a non-display area 12, the display area 11 includes an opening area 21 and a non-opening area 22, and the method includes:
Specifically, with reference to fig. 7 to 11, in the preparation method of the array substrate 100 provided in this embodiment of the present application, in the process of preparing the array substrate 100, the trench digging regions 23 and the opening regions 21 are designed to be dug separately, after the first isolation layer 32 is introduced in the embodiment of the present application, the process of performing trench digging etching on the trench digging regions 23 and the opening regions 21 can be performed separately, so that the time of performing trench digging etching on the trench digging regions 23 and the opening regions 21 can be accurately controlled, and the problem of over-etching or under-etching in the process of etching the trench digging regions 23 and the opening regions 21 in the prior art is effectively avoided, thereby facilitating improvement of the accuracy of trench digging etching in the array substrate 100. In addition, in the preparation process of the array substrate 100, the first isolation layer 32 corresponding to the opening area 21 and the plurality of films located on the side of the first isolation layer 32 far away from the substrate 20 are etched in the grooving etching process, so that the film structure corresponding to the opening area 21 is simple finally, thereby being beneficial to improving the penetration rate of the opening area 21 of the array substrate 100 and further being beneficial to improving the penetration rate of the whole array substrate 100. Moreover, this application is favorable to playing the effect of protection to first buffer layer 31 after introducing first isolation layer, avoids appearing impaired phenomenon at first buffer layer 31 in the etching process to be favorable to guaranteeing first buffer layer 31's integrality.
Optionally, referring to fig. 12, fig. 12 is a schematic view illustrating after forming the color-resist layer 60 and the planarization layer 50 on the basis of fig. 11, and the method for manufacturing the array substrate 100 according to the embodiment of the present disclosure further includes: manufacturing a color resistance layer 60 in the opening area 21, and enabling the color resistance layer 60 to be positioned on the surface of the first buffer layer 31 far away from the substrate base plate 20;
a planarization layer 50 is formed on the surface of the color resist layer 60 and the pixel driving circuit 40 away from the substrate 20.
Specifically, referring to fig. 12, the slotted region corresponding to the opening region 21 is filled with a color resistor, in the array substrate 100 provided in the embodiment of the present application, the sub-pixel unit 15 may include a red sub-pixel unit 15, a green sub-pixel unit 15, and a blue sub-pixel unit 15, and correspondingly, the red sub-pixel unit 15 is filled with the red color resistor, the green sub-pixel unit 15 is filled with the green color resistor, and the blue sub-pixel unit 15 is filled with the blue color resistor. The color-resist layer 60 and the surface of the pixel driving circuit 40 away from the substrate 20 are filled with a planarization layer 50 to provide a planarized surface for the subsequent film layer structure (such as the common electrode 71 layer and the pixel electrode 72 layer shown in fig. 6) of the array substrate 100.
Alternatively, referring to fig. 13, fig. 13 is a flowchart illustrating a step-by-step etching method for forming the opening region 21 and the hole digging region 23, in the step 105, the pixel driving circuit 40 is fabricated on a side of the second buffer layer 33 away from the substrate 20, and the opening region 21 and the hole digging region 23 are formed by step-by-step etching, further:
Specifically, with reference to fig. 13 to 17, in the embodiment of the present invention, the opening region 21 and the hole-digging region 23 are formed by three etching processes, respectively, in which the interlayer insulating layer 38, the gate insulating layer 36, and the second buffer layer 33 in the first region 91 are removed; in the second etching process, the interlayer insulating layer 38 and the gate insulating layer 36 in the second region 92 are removed, and a hole digging region 23 is formed; in the third etching process, the first isolation layer 32 located in the first region 91 is removed, thereby forming the opening region 21. It can be seen that the etching processes of the hole digging region 23 and the opening region 21 are separately performed, and the opening region 21 is formed by two etching processes (a first etching process and a third etching process), so that the performing processes of the first etching process and the second etching process are completely independent and cannot affect each other, and therefore, the etching time of the first etching process and the etching time of the second etching process can be independently controlled, which is beneficial to improving the etching precision and avoiding the over-etching or under-etching phenomenon. In addition, in the first etching process, in the process of etching the interlayer insulating layer 38 and the gate insulating layer 36 in the first region 91, the first buffer layer 31 is not damaged due to the protective effect of the first isolation layer 32, and the etching process may not affect the first buffer layer 31 by using the third etching process and performing the independent etching process on the first isolation layer 32 through the control of the etching process, so that the preparation method of the array substrate 100 provided in the embodiment of the present application is beneficial to ensuring the integrity of the first buffer layer 31.
Optionally, before performing the first etching process, that is, before performing the step 202, the method further includes:
coating a photoresist 90 on a side of the interlayer insulating layer 38 away from the substrate 20, referring to fig. 18, and performing exposure and development on the photoresist 90 by using a half-transparent mask, referring to fig. 19, removing the photoresist 90 in the first region 91, exposing the interlayer insulating layer 38 in the first region 91, and removing a portion of the photoresist 90 in the second region 92, wherein fig. 18 is a schematic diagram of coating the photoresist 90 on the interlayer insulating layer 38, and fig. 19 is a schematic diagram of performing exposure and development on the photoresist 90 in fig. 18;
it should be noted that, when performing the first etching process, the interlayer insulating layer 38, the gate insulating layer 36 and the second buffer layer 33 in the first region 91 corresponding to those in fig. 19 are etched, and the structure after etching may be referred to fig. 20, where fig. 20 is a schematic diagram after etching the interlayer insulating layer 38, the gate insulating layer 36 and the second buffer layer 33 corresponding to the first region 91 in fig. 19;
before the second etching process is performed, that is, before the step 203 is performed, the method further includes:
ashing the photoresist 90 on the side of the interlayer insulating layer 38 away from the substrate 20, removing the photoresist 90 in the second region 92 and the portion of the photoresist 90 around the second region 92, and exposing the interlayer insulating layer 38 in the second region 92, as shown in fig. 21, where fig. 21 is a schematic diagram of the ashed photoresist 90 in fig. 20. The photoresist ashing process is to etch away the photoresist 90 as an object to be etched, and the photoresist 90 may be an organic substance composed of C, H, O, N, for example, and generally may be reacted with oxygen to generate CO and CO2、H2O、N2The thickness of the photoresist 90 to be etched can be controlled by controlling the ashing rate and ashing time according to the present invention, thereby achieving the effect shown in fig. 20, exposing the interlayer insulating layer 38 in the second region 92.
On the basis of the structure shown in fig. 21, the interlayer insulating layer 38 and the gate insulating layer 36 corresponding to the second region 92 may be etched by using a second etching process, so as to form the hole digging region 23 shown in fig. 22, where fig. 22 is a schematic diagram of the interlayer insulating layer 38 and the gate insulating layer 36 corresponding to the second region 92 after being etched. After the second etching process is completed, the first isolation layer 32 in the first region 91 is etched by using a third etching process under the structure shown in fig. 22, so as to form the structure shown in fig. 23, where fig. 23 is a schematic diagram of etching the first isolation layer 32 by using the third etching process. It should be noted that before forming the source-drain metal layer 39, a step of removing the photoresist 90 shown in fig. 23 is further included, and the structure shown in fig. 24 is finally formed, where fig. 24 is a schematic diagram of forming the semiconductor active layer 39 after removing all the photoresist 90 on the basis of fig. 23.
Optionally, the first etching process and the second etching process are dry etching, and the third etching process is wet etching.
Specifically, the gate insulating layer 36 and the interlayer insulating layer 38 are usually made of silicon oxide, silicon nitride, or the like, and dry etching is performed using, for example, CF gas4The gate insulating layer 36 and the interlayer insulating layer 38 may be etched away, and during the dry etching, the gas CF4The first isolation layer 32 is not affected, and thus the first buffer layer 31 can be protected from the first etching process and the second etching process by the first isolation layer 32. The third etching process is wet etching, i.e. a specific solution (such as hydrochloric acid solution, etc.) is used to etch the first isolation layer 32, the etching rate can be usually controlled by the concentration and temperature of the solution, the concentration of the solution can change the rate of the reaction substance reaching and leaving the surface of the object to be etched, generally, when the concentration of the solution is increased, the etching rate will be increased, and increasing the temperature of the solution can accelerate the chemical reaction rate, thereby accelerating the etching rate. When the first isolation layer 32 is etched by wet etching, the first buffer layer 31 is not affected, so that the integrity of the first buffer layer 31 can be ensured.
Based on the same inventive concept, the present application further provides a display panel 400, referring to fig. 25, including an array substrate 100, where the array substrate 100 is the array substrate 100 provided in the foregoing embodiment, where fig. 25 is a schematic view of the display panel 400 provided in the present embodiment, the display panel 400 includes, in addition to the array substrate 100, a color filter substrate 200 disposed opposite to the array substrate 100, and a liquid crystal layer 300 located between the array substrate 100 and the color filter substrate 200, and the embodiment of the display panel 400 may refer to the embodiment of the array substrate 100, and repeated details are omitted.
Based on the same inventive concept, the present application further provides a display device 500, referring to fig. 26, including a display panel 400, where the display panel 400 is the display panel 400 provided in the above embodiment, and fig. 26 is a schematic view of the display device 500 provided in the embodiment of the present application. The display device 500 provided by the present application may be: any product or component with practical functions such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like. In the present application, the embodiment of the display device 500 can be referred to the embodiment of the display panel 400, and repeated descriptions thereof are omitted here.
According to the embodiment, the array substrate, the preparation method thereof, the display panel and the display device provided by the invention at least realize the following beneficial effects:
in the array substrate, the preparation method thereof, the display panel and the display device provided by the application, the first isolation layer and the second buffer layer are introduced at one side of the first buffer layer far away from the substrate, the hole digging region in the pixel driving circuit is arranged at one side of the second buffer layer far away from the substrate and is overlapped with the first isolation layer and the second buffer layer, the opening region is not overlapped with the first isolation layer and the second buffer layer, the grooving design is needed in the process of forming the hole digging area and the opening area, the grooving etching process of the opening area and the grooving etching process of the hole digging area can be separately carried out after the first isolating layer is introduced, the etching time corresponding to the hole digging area and the opening area can be accurately controlled respectively, therefore, the etching precision of the hole digging area and the opening area is improved, and the problem that the hole digging area is over-etched or the opening area is under-etched due to too large area difference of the hole digging area and the opening area when etching is carried out is effectively solved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (15)
1. An array substrate, wherein a display area and a non-display area are provided, the display area includes an open area and a non-open area, the array substrate includes:
a substrate base plate;
the first buffer layer covers the first surface of the substrate base plate;
the first isolation layer is arranged on the surface, far away from the substrate base plate, of the first buffer layer;
the second buffer layer covers the surface, far away from the substrate base plate, of the first isolation layer;
the pixel driving circuit is arranged on one side, far away from the substrate, of the second buffer layer and comprises a hole digging region;
wherein, the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are overlapped with the hole digging region, and the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are not overlapped with the opening region.
2. The array substrate of claim 1, further comprising:
the color resistance layer is arranged on the surface, far away from the substrate base plate, of the first buffer layer and is positioned in the opening area; and the number of the first and second groups,
and the planarization layer covers the color resistance layer and the surface of the pixel driving circuit far away from the substrate base plate.
3. The array substrate of claim 2, wherein the pixel driving circuit comprises a thin film transistor, and a height difference between a source drain metal layer of the thin film transistor and the color resistance layer is h, wherein h is less than or equal to 0.6 μm.
4. The array substrate of claim 2, wherein the thickness of the color resist layer is D0, 1.5 μm D0 μm 3 μm.
5. The array substrate of claim 1, wherein the first spacer layer is indium tin oxide.
6. The array of claim 1The substrate is characterized in that the thickness of the first isolation layer is D1,
7. the array substrate of claim 1, wherein the second buffer layer has a thickness of D2,
8. the array substrate of claim 1, wherein the first buffer layer, the first isolation layer and the second buffer layer have a total thickness of D3, wherein,
9. a preparation method of an array substrate is characterized in that the array substrate is provided with a display area and a non-display area, the display area comprises an opening area and a non-opening area, and the preparation method comprises the following steps:
providing a substrate base plate;
manufacturing a first buffer layer, and enabling the first buffer layer to cover the first surface of the substrate base plate;
manufacturing a first isolation layer, and enabling the first isolation layer to cover the surface of the first buffer layer, which is far away from the substrate base plate;
manufacturing a second buffer layer, and enabling the second buffer layer to cover the surface, far away from the substrate, of the first isolation layer;
and manufacturing a pixel driving circuit on one side of the second buffer layer, which is far away from the substrate base plate, forming the opening area and the hole digging area in a step-by-step etching mode, wherein the hole digging area is positioned in the non-opening area, so that orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are overlapped with the hole digging area, and the orthographic projections of the first isolation layer and the second buffer layer on the substrate base plate are not overlapped with the opening area.
10. The method for manufacturing an array substrate according to claim 9, further comprising:
manufacturing a color resistance layer in the opening area, and enabling the color resistance layer to be positioned on the surface of the first buffer layer far away from the substrate;
and forming a planarization layer on the surfaces of the color resistance layer and the pixel driving circuit far away from the substrate base plate.
11. The method for manufacturing the array substrate according to claim 9, wherein the pixel driving circuit is formed on a side of the second buffer layer away from the substrate, and the opening region and the hole digging region are formed by step etching, further comprising:
sequentially forming a semiconductor active layer, a gate insulating layer, a gate metal layer and an interlayer insulating layer on one side of the second buffer layer, which is far away from the substrate;
performing a first etching process to remove the interlayer insulating layer, the gate insulating layer and the second buffer layer in a first region and expose the first isolation layer in the first region, wherein the first region is not overlapped with the semiconductor active layer;
performing a second etching process, removing the interlayer insulating layer and the gate insulating layer in a second region, exposing the semiconductor active layer in the second region, and forming a hole digging region, wherein the second region is overlapped with the semiconductor active layer and is not overlapped with the gate metal layer;
executing a third etching process to remove the first isolation layer positioned in the first area and form the opening area in the first area;
and forming a source drain metal layer on the side of the dug hole region and the interlayer insulating layer far away from the substrate.
12. The method for preparing the array substrate according to claim 11, further comprising, before the performing the first etching process:
coating photoresist on one side of the interlayer insulating layer, which is far away from the substrate, exposing and developing the photoresist by using a semi-transparent mask plate, removing the photoresist in the first area, exposing the interlayer insulating layer in the first area, and removing part of the photoresist in the second area;
before the performing of the second etching process, the method further includes:
and ashing the photoresist on the side of the interlayer insulating layer far away from the substrate base plate, removing the photoresist in the second area and part of the photoresist around the second area, and exposing the interlayer insulating layer in the second area.
13. The method for manufacturing the array substrate according to claim 11, wherein the first etching process and the second etching process are dry etching, and the third etching process is wet etching.
14. A display panel comprising an array substrate according to any one of claims 1 to 8.
15. A display device comprising the display panel according to claim 14.
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| CN112230798B (en) * | 2020-10-14 | 2024-03-15 | 京东方科技集团股份有限公司 | Display panel, manufacturing method and display device |
| CN112259560A (en) * | 2020-10-21 | 2021-01-22 | 京东方科技集团股份有限公司 | Display substrate and display device |
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