WO2019111092A1 - Display device and method for operating same - Google Patents

Display device and method for operating same Download PDF

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Publication number
WO2019111092A1
WO2019111092A1 PCT/IB2018/059279 IB2018059279W WO2019111092A1 WO 2019111092 A1 WO2019111092 A1 WO 2019111092A1 IB 2018059279 W IB2018059279 W IB 2018059279W WO 2019111092 A1 WO2019111092 A1 WO 2019111092A1
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WO
WIPO (PCT)
Prior art keywords
pixel
transistor
display
display device
display panel
Prior art date
Application number
PCT/IB2018/059279
Other languages
French (fr)
Japanese (ja)
Inventor
吉本智史
檜山真里奈
楠紘慈
Original Assignee
株式会社半導体エネルギー研究所
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Filing date
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Application filed by 株式会社半導体エネルギー研究所 filed Critical 株式会社半導体エネルギー研究所
Priority to JP2019557701A priority Critical patent/JP7289793B2/en
Priority to CN201880077464.9A priority patent/CN111418000B/en
Publication of WO2019111092A1 publication Critical patent/WO2019111092A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators

Definitions

  • One embodiment of the present invention relates to a display device and an operation method thereof.
  • the technical field of one embodiment of the present invention includes a semiconductor device, a display device, a light emitting device, a display system, an electronic device, a lighting device, an input device (eg, a touch sensor or the like), an input / output device (eg, a touch panel or the like),
  • an input device eg, a touch sensor or the like
  • an input / output device eg, a touch panel or the like
  • the driving method of or the manufacturing method of them can be mentioned as an example.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a display device (a liquid crystal display device, a light emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may be referred to as a semiconductor device. Alternatively, it may be said that these have a semiconductor device.
  • a display device with high resolution has been required.
  • a display device with a large number of pixels such as full high vision (the number of pixels 1920 ⁇ 1080), 4K (the number of pixels 3840 ⁇ 2160 or 4096 ⁇ 2160), and further 8K (the number of pixels 7680 ⁇ 4320 or 8192 ⁇ 4320) is thriving Has been developed.
  • the enlargement of a display apparatus is calculated
  • Patent Document 1 discloses a technique of using amorphous silicon as a semiconductor material of a transistor.
  • Patent Document 2 and Patent Document 3 disclose a technique of using a metal oxide as a semiconductor material of a transistor.
  • Patent Document 4 discloses a technique for manufacturing a large display device by arranging a plurality of display panels.
  • An object of one embodiment of the present invention is to provide a display device with high display quality.
  • An object of one embodiment of the present invention is to provide a display device with reduced display unevenness.
  • An object of one embodiment of the present invention is to provide a display device with high resolution.
  • An object of one embodiment of the present invention is to provide a display device having a large display area.
  • An object of one embodiment of the present invention is to provide a display device operable at a high frame frequency.
  • An object of one embodiment of the present invention is to provide a display device with low power consumption.
  • An object of one embodiment of the present invention is to provide a thin display device.
  • An object of one embodiment of the present invention is to provide a flexible display device.
  • An object of one embodiment of the present invention is to provide a display device with a wide viewing angle.
  • An object of one embodiment of the present invention is to provide a display device that can be manufactured with a small manufacturing device.
  • An object of one embodiment of the present invention is to provide a low-cost display device.
  • An object of one embodiment of the present invention is to provide a highly reliable display device.
  • An object of one embodiment of the present invention is to provide a novel display device.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.
  • An object of one embodiment of the present invention is to provide a method for operating a display device with high display quality.
  • An object of one embodiment of the present invention is to provide a method for operating a display device in which display unevenness is reduced.
  • An object of one embodiment of the present invention is to provide a method for operating a display device with high resolution.
  • An object of one embodiment of the present invention is to provide a method for operating a display device having a large display area.
  • An object of one embodiment of the present invention is to provide a method of operating a display device operable at a high frame frequency.
  • An object of one embodiment of the present invention is to provide a method for operating a display device with low power consumption.
  • An object of one embodiment of the present invention is to provide a method for operating a thin display device.
  • An object of one embodiment of the present invention is to provide a method for operating a flexible display device.
  • An object of one embodiment of the present invention is to provide a method for operating a display device with a wide viewing angle.
  • An object of one embodiment of the present invention is to provide a method for operating a display device that can be manufactured with a small manufacturing device.
  • An object of one embodiment of the present invention is to provide a method for operating a low cost display device.
  • An object of one embodiment of the present invention is to provide a method for operating a highly reliable display device.
  • An object of one embodiment of the present invention is to provide a novel operation method of a display device.
  • An object of one embodiment of the present invention is to provide a method for operating a novel semiconductor device or the like.
  • One embodiment of the present invention is an operation method of a display device including a first pixel portion in which first pixels are arranged in a matrix and a second pixel portion in which second pixels are arranged in a matrix
  • a first correction filter having a function of correcting an image displayed in the first pixel unit, and a second correction filter having a function of correcting an image displayed in the second pixel unit; Of the first correction filter and the filter value of the second correction filter, and correcting the filter value of the first correction filter based on the comparison result. It is.
  • the first correction filter has a filter value corresponding to the first pixel
  • the second correction filter has a filter value corresponding to the second pixel, and the boundary portion with the second pixel portion Corresponding to a second pixel provided at the boundary between the first pixel portion and the average value of the filter values corresponding to the first pixel provided in It compares the average value of the filter value, and based on the comparison result, an operation method of a display device for correcting the filter value of the first correction filter.
  • the first correction filter is emitted from the first pixel by measuring the luminance of light emitted from the first pixel for a plurality of gradation values of the first pixel.
  • Data of the correspondence between the luminance of the light and the gradation value of the first pixel is acquired, and an image of a specific gradation value is displayed in the first pixel portion, and the light is emitted from the first pixel
  • the luminance data is acquired by measuring the luminance of the light, it may be created using the correspondence data and the luminance data.
  • one embodiment of the present invention is a display device including a first pixel portion in which first pixels are arranged in a matrix and a second pixel portion in which second pixels are arranged in a matrix.
  • the first image is displayed in the first pixel portion
  • the second image is displayed in the second pixel portion
  • the luminance of the light emitted from the first pixel and the second pixel are displayed.
  • the luminance of light emitted from the first pixel is corrected, and the luminance of the light emitted from the first pixel is corrected based on the comparison result.
  • the first image is displayed in the first pixel portion
  • the second image is displayed in the second pixel portion
  • the first pixel Is the method of operation of the display device for correcting the brightness of the light emitted from the light source.
  • the luminance of the light emitted from the first pixel is Data of the correspondence between the luminance of the light emitted from the first pixel and the gradation value of the first pixel by measuring a plurality of gradation values of the first pixel;
  • the luminance data is acquired by displaying the image of the specific gradation value on the unit and measuring the luminance of the light emitted from the first pixel, and the correspondence data and the luminance data are used.
  • a correction filter is created, and the first image may be an image corrected using the correction filter.
  • the image of a specific tone value may be an image in which the tone values of all the first pixels are equal.
  • one embodiment of the present invention is a display device including a pixel portion and a processing portion, in the pixel portion, pixels are arrayed in a matrix, and the pixel includes a display element and a memory circuit.
  • the processing unit has a function of creating a correction filter using luminance data acquired based on the image displayed by the display element, and the memory circuit is a display device having a function of holding the correction filter. .
  • the pixel includes the display element, the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, and the second capacitor.
  • One of the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, and the other electrode of the first capacitive element is the source of the second transistor Or one of the drain and one of the source or the drain of the second transistor is electrically connected to the gate of the third transistor, and the gate of the third transistor is The other electrode of the second capacitor element is electrically connected to one of the electrodes, and the other electrode of the second capacitor element is electrically connected to one of the source or the drain of the third transistor, and the source or the drain of the third transistor One is the source or of the fourth transistor is electrically connected to one of the drain, the other of the source and the drain of the fourth transistor may be one electrode electrically connected to the display device.
  • the display element may be an organic EL element.
  • the second transistor includes a metal oxide in the channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
  • a display device with high display quality can be provided.
  • a display device with reduced display unevenness can be provided.
  • a display device with high resolution can be provided.
  • a display device having a large display area can be provided.
  • a display capable of operating at a high frame frequency can be provided.
  • a display device with low power consumption can be provided.
  • a thin display device can be provided.
  • a flexible display device can be provided.
  • a display device with a wide viewing angle can be provided.
  • a display device that can be manufactured with a small manufacturing device can be provided.
  • a low cost display device can be provided.
  • a highly reliable display device can be provided.
  • a novel display device can be provided.
  • a novel semiconductor device or the like can be provided.
  • a method for operating a display device with high display quality can be provided.
  • an operation method of a display device with reduced display unevenness can be provided.
  • an operation method of a display device with high resolution can be provided.
  • an operation method of a display device having a large display area can be provided.
  • a method for operating a display device with low power consumption can be provided.
  • an operation method of a thin display device can be provided.
  • an operation method of a flexible display device can be provided.
  • a method for operating a display device with a wide viewing angle can be provided.
  • an operation method of a display device which can be manufactured with a small manufacturing device can be provided.
  • an inexpensive method for operating a display device can be provided.
  • One embodiment of the present invention can provide a method for operating a highly reliable display device.
  • a novel display device operation method can be provided.
  • an operation method of a novel semiconductor device or the like can be provided.
  • FIG. 7 is a diagram illustrating an example of a display device. The figure which shows an example of a display part.
  • FIG. 7 is a diagram illustrating an example of a display panel.
  • FIG. 7 is a diagram illustrating an example of a display device.
  • FIG. 8 shows an example of operation of a display device.
  • FIG. 8 shows an example of operation of a display device.
  • FIG. 8 shows an example of operation of a display device.
  • FIG. 2 is a diagram showing an example of a pixel.
  • FIG. 7 is a diagram illustrating an example of a display device. The figure which shows an example of a display part.
  • FIG. 2 is a diagram showing an example of a pixel.
  • FIG. 6 shows an example of the operation of a pixel.
  • FIG. 2 is a diagram showing an example of a pixel.
  • FIG. 6 shows an example of the operation of a pixel.
  • FIG. 8 shows an example of operation of a display device.
  • FIG. 8 shows an example of operation of a display device.
  • FIG. 7 is a diagram illustrating an example of a display device.
  • FIG. 18 illustrates an example of a transistor.
  • FIG. 18 illustrates an example of a transistor.
  • FIG. 18 illustrates an example of a transistor.
  • FIG. 18 illustrates an example of a transistor.
  • FIG. 6 illustrates an example of an electronic device.
  • FIG. 2 is a view showing a display device used in Example 1; The photograph which shows the display result of Example 1.
  • FIG. 2 is a view showing a display device used in Example 1; The photograph which shows the display result of Example 1.
  • FIG. The photograph which shows the luminance data of Example 2.
  • FIG. 2 is a view showing a display
  • membrane and the term “layer” can be replaced with each other depending on the case or situation.
  • conductive layer can be changed to the term “conductive film”.
  • insulating film can be changed to the term “insulating layer”.
  • the metal oxide is a metal oxide in a broad sense.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductor or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET, the transistor can be put in another way as a transistor including a metal oxide or an oxide semiconductor.
  • metal oxides having nitrogen may also be collectively referred to as metal oxides.
  • a metal oxide having nitrogen may be referred to as metal oxynitride.
  • Embodiment 1 a display device of one embodiment of the present invention will be described with reference to FIGS.
  • One embodiment of the present invention relates to a display device and its operation method in which a boundary between display panels is difficult to be recognized even when a large display region is realized by arranging a plurality of display panels.
  • FIGS. 1A and 1B are block diagrams showing a configuration example of the display device 10A.
  • the display device 10A has a function of generating image data using data received from the outside, and a function of displaying an image based on the image data.
  • the display device 10A includes a display unit 20A and a signal generation unit 30A.
  • the display unit 20A has a plurality of display panels DP.
  • the signal generation unit 30A has a function of generating image data using data received from the outside.
  • the display panel DP has a function of displaying an image based on the image data.
  • FIG. 1A shows an example in which the display panel DP is arranged in two rows and one column in the display unit 20A.
  • the display of the display panel DP can be controlled independently. Note that three or more lines of display panels DP may be arranged in the display unit 20A, or two or more lines may be arranged.
  • the display panel DP provided at the p-th row and the q-th column (p and q are integers of 1 or more) is referred to as a display panel DP [p, q].
  • the display unit 20A having a wide display area can be manufactured.
  • FIG. 1B shows a configuration example of the display panel DP [1, 1] and the display panel DP [2, 1].
  • the display panel DP [1,1] includes a pixel portion 21A, a scanning line drive circuit 22A (also referred to as a gate driver), a signal line drive circuit 23A (also referred to as a source driver), and a timing controller 24A.
  • the display panel DP [2, 1] includes a pixel unit 21B, a scanning line drive circuit 22B, a signal line drive circuit 23B, and a timing controller 24B.
  • the signal generation unit 30A includes a front end unit 31, a decoder 32, a processing unit 33, a reception unit 34, an interface 35, a control unit 36, a processing unit 40A, and a division unit 45A.
  • a pixel portion provided in a display portion included in a display device of one embodiment of the present invention may be referred to as a pixel portion 21.
  • the scan line drive circuit provided in the display portion of the display device of one embodiment of the present invention such as the scan line drive circuit 22A and the scan line drive circuit 22B, may be referred to as a scan line drive circuit 22.
  • a signal line driver circuit provided in a display portion of the display device of one embodiment of the present invention such as the signal line driver circuit 23A and the signal line driver circuit 23B, may be referred to as a signal line driver circuit 23.
  • the pixel unit 21A and the pixel unit 21B have a plurality of pixels.
  • the pixel unit 21A and the pixel unit 21B have a function of displaying an image.
  • the pixel has a display element.
  • the pixel has a function of emitting light of luminance according to the gradation value.
  • the tone of the pixel is controlled by the signals supplied from the scanning line drive circuit 22A and the signal line drive circuit 23A, and a predetermined image is displayed on the pixel section 21A. Further, the gradation of the pixel is controlled by the signals supplied from the scanning line drive circuit 22B and the signal line drive circuit 23B, and a predetermined image is displayed on the pixel section 21B.
  • the scanning line drive circuit 22A has a function of supplying a signal for selecting a pixel (also referred to as a selection signal) to the pixel portion 21A.
  • the scanning line drive circuit 22B has a function of supplying a selection signal to the pixel portion 21B.
  • the signal line drive circuit 23A has a function of supplying a signal (also referred to as an image signal) representing a gray scale represented by a pixel to the pixel portion 21A.
  • the signal line drive circuit 23B has a function of supplying an image signal to the pixel portion 21B.
  • the timing controller 24A has a function of generating timing signals (clock signal, start pulse signal and the like) used in the scanning line drive circuit 22A, the signal line drive circuit 23A and the like.
  • the timing controller 24B has a function of generating timing signals used in the scanning line drive circuit 22B, the signal line drive circuit 23B, and the like.
  • One or both of the timing when the selection signal is output from the scanning line drive circuit 22A and the timing when the image signal is output from the signal line drive circuit 23A are controlled by the timing signal generated by the timing controller 24A.
  • One or both of the timing when the selection signal is output from the scanning line drive circuit 22B and the timing when the image signal is output from the signal line drive circuit 23B are controlled by the timing signal generated by the timing controller 24B.
  • timings at which signals are output from the plurality of scanning line driving circuits are synchronized by a timing signal generated by the timing controller 24A.
  • the display panel DP [2, 1] includes a plurality of scanning line drive circuits, timings at which signals are output from the plurality of scanning line drive circuits are synchronized by the timing signal generated by the timing controller 24B.
  • the display panel DP [1, 1] has a plurality of signal line drive circuits
  • timings at which signals are output from the signal line drive circuits are synchronized by timing signals generated by the timing controller 24A.
  • the display panel DP [2, 1] includes a plurality of signal line drive circuits, timings at which signals are output from the signal line drive circuits are synchronized by timing signals generated by the timing controller 24B.
  • the front end unit 31 has a function of receiving a signal input from the outside and appropriately performing signal processing.
  • the front end unit 31 receives, for example, a broadcast signal or the like that has been encoded and modulated according to a predetermined method.
  • the front end unit 31 can have a function of demodulating the received image signal, performing analog-digital conversion, and the like.
  • the front end unit 31 may have a function of performing error correction.
  • the data received by the front end unit 31 and subjected to the signal processing is output to the decoder 32.
  • the decoder 32 has a function of decoding the encoded signal.
  • the decoder 32 performs decompression.
  • the decoder 32 can have a function of performing inverse orthogonal transformation such as entropy decoding, inverse quantization, inverse discrete cosine transformation (IDCT), inverse discrete sine transformation (IDST), intra-frame prediction, inter-frame prediction, etc. .
  • the image data generated by the decoding process by the decoder 32 is output to the processing unit 33.
  • the processing unit 33 has a function of performing image processing on the image data input from the decoder 32, generating the first image data SD1, and outputting the first image data SD1 to the processing unit 40A.
  • Examples of the image processing include noise removal processing, tone conversion processing, color tone correction processing, luminance correction processing and the like.
  • Color tone correction processing and luminance correction processing can be performed using gamma correction or the like.
  • Examples of the noise removal process include removal of various noises such as mosquito noise generated around an outline of a character or the like, block noise generated in a high-speed moving image, and random noise causing flicker.
  • the gradation conversion process is a process of converting the gradation indicated by the first image data SD1 into a gradation corresponding to the output characteristic of the display unit 20A. For example, in the case where the number of gradations is increased, processing for smoothing the histogram can be performed by interpolating and allocating gradation values corresponding to respective pixels to an image input with a small number of gradations. Also, high dynamic range (HDR) processing, which extends the dynamic range, is also included in the tone conversion processing.
  • HDR high dynamic range
  • Color tone correction processing is processing for correcting the color tone of an image.
  • the luminance correction processing is processing for correcting the brightness (luminance contrast) of an image. For example, the brightness and the color tone of the image displayed on the display unit 20A are corrected so as to be optimal according to the type and the brightness or the color purity of the illumination in the space where the display unit 20A is provided.
  • the interframe interpolation process is a process of generating an image of a frame (interpolated frame) which does not originally exist, when the frame frequency of the image to be displayed is increased.
  • an image of an interpolation frame to be inserted between two images is generated from the difference between two images.
  • images of a plurality of interpolation frames can be generated between two images.
  • the frame frequency of the image data is 60 Hz
  • the frame frequency of the image signal output to the display unit 20A is doubled by 120 Hz, or quadrupled by 240 Hz, by generating a plurality of interpolation frames. It can be increased to eight times 480 Hz and so on.
  • the above-described image processing can also be performed by a processing unit provided separately from the processing unit 33.
  • one or more of the above-described image processing may be performed by the processing unit 40A.
  • the receiving unit 34 has a function of receiving externally input data or control signals.
  • the arithmetic processing unit 50 a remote controller, a portable information terminal (such as a smartphone or a tablet), an operation button provided on the display unit 20A, a touch panel, or the like can be used to input data or control signals to the reception unit 34.
  • the arithmetic processing unit 50 may be a computer such as a computer, a server, or a cloud, which has an excellent arithmetic processing capability.
  • the interface 35 has a function of appropriately performing signal processing on the data or control signal received by the receiving unit 34 and outputting the data or control signal to the control unit 36.
  • the control unit 36 has a function of supplying control signals to the circuits included in the signal generation unit 30A.
  • the control unit 36 has a function of supplying a control signal to the decoder 32, the processing unit 33, the processing unit 40A, and the dividing unit 45A.
  • the control by the control unit 36 can be performed based on the control signal or the like received by the receiving unit 34.
  • the processing unit 40A has a function of creating a correction filter.
  • the processing unit 40A also has a function of generating the second image data SD2 by correcting the first image data SD1 input from the processing unit 33 using the created correction filter.
  • the processing unit 40A has a function of correcting the first image data SD1 so as to reduce display unevenness of the image displayed on the display unit 20A.
  • the processing unit 40A has a function of correcting the first image data SD1 so that the boundaries between the display panels are not easily recognized.
  • the second image data SD2 generated by the processing unit 40A is output to the dividing unit 45A.
  • the dividing unit 45A has a function of dividing the second image data SD2 input from the processing unit 40A.
  • the second image data SD2 can be divided into the same number as that of the display panel DP provided in the display unit 20A.
  • the second image data SD2 is divided into 2 ⁇ 1 pieces (second image data SD2 [1,1] and second image data SD2 [2,1]) and displayed. It is output to the unit 20A.
  • the second image data SD2 [1,1] is image data corresponding to the image displayed on the display panel DP [1,1]
  • the second image data SD2 [2,1] is the display panel DP It is image data corresponding to the image displayed in [2, 1].
  • the dividing unit 45A outputs the second image data SD2 [1,1] to the signal line drive circuit 23A, and outputs the second image data SD2 [2,1] to the signal line drive circuit 23B.
  • FIG. 2 shows a specific configuration example of the display panel DP [1, 1] and the display panel DP [2, 1].
  • Each of the pixel unit 21A and the pixel unit 21B has a plurality of pixels 25.
  • FIG. 2 illustrates an example in which the pixel unit 21A and the pixel unit 21B each have a plurality of pixels 25 arranged in a matrix of m rows and n columns (m and n are integers of 1 or more).
  • a pixel provided in the pixel portion 21A may be referred to as a first pixel.
  • a pixel provided in the pixel portion 21B may be referred to as a second pixel.
  • a boundary between the pixel unit 21A and the pixel unit 21B is referred to as a boundary 28A.
  • a boundary between the pixel unit 21B and the pixel unit 21A is referred to as a boundary 28B.
  • the pixel 25 in the m-th row can be provided in the boundary portion 28A.
  • the pixels 25 in the (7/8) m + 1st to m-th rows can be provided in the boundary portion 28A.
  • the pixels 25 in the (3/4) m + 1st to m-th rows can be provided in the boundary portion 28A.
  • the pixels 25 in the (1/2) m + 1-th to m-th rows can be provided in the boundary portion 28A.
  • the pixels 25 in the first row can be provided.
  • the pixels 25 in the first to (1/8) m-th rows can be provided.
  • the pixels 25 in the first to (1/4) m-th rows can be provided.
  • the pixels 25 in the first to (1/2) m-th rows can be provided.
  • the display panel DP [1,1] includes m scanning lines GLa (also referred to as selection signal lines, gate lines, and the like).
  • the display panel DP [2, 1] has m scanning lines GLb.
  • the m scanning lines GLa and the m scanning lines GLb respectively extend in the row direction.
  • the m scanning lines GLa and the m scanning lines GLb are electrically connected to the pixels 25 aligned in the row direction.
  • a scan line provided in a display device of one embodiment of the present invention such as the scan line GLa and the scan line GLb, may be referred to as a scan line GL.
  • the scan line GL electrically connected to the pixel 25 in the i-th row (i is an integer of 1 or more and m or less) is referred to as a scan line GL [i].
  • the symbol or code representing the element in the i-th row may be distinguished by adding [i].
  • the scanning line driving circuit 22A has a function of supplying a selection signal to the scanning line GLa
  • the scanning line driving circuit 22B has a function of supplying a selection signal to the scanning line GLb.
  • the selection signal is supplied to the pixel 25 included in the pixel unit 21A through the scanning line GLa, and is supplied to the pixel 25 included in the pixel unit 21B through the scanning line GLb.
  • the scanning line drive circuit 22A has a function of sequentially supplying selection signals from the scanning line GLa [1] to the scanning line GLa [m]. In other words, the scanning line drive circuit 22A has a function of sequentially scanning the scanning lines GLa [1] to the scanning lines GLa [m]. After scanning up to the scanning line GLa [m], scanning is sequentially performed again from the scanning line GLa [1].
  • the scanning line drive circuit 22B has a function of supplying selection signals in order from the scanning line GLb [1] to the scanning line GLb [m]. In other words, the scanning line drive circuit 22B has a function of sequentially scanning the scanning lines GLb [1] to the scanning lines GLb [m]. After scanning up to the scanning line GLb [m], scanning is sequentially performed again from the scanning line GLb [1].
  • another scanning line driving circuit may be provided on the display panel DP [1, 1].
  • the scan line drive circuit is electrically connected to the other end of the scan line GLa. Therefore, two scanning line driving circuits are provided at positions facing each other across the pixel portion 21A.
  • another scanning line driving circuit may be provided in the display panel DP [2, 1].
  • the scan line drive circuit is electrically connected to the other end of the scan line GLb. Thus, two scanning line driving circuits are provided at positions facing each other across the pixel portion 21B.
  • the selection signal is simultaneously supplied from one of the two scanning line driving circuits to one of the scanning lines GLa or scanning line GLb. Can increase the supply capability of the selection signal.
  • the display panel DP [1, 1] has n signal lines SLa (also referred to as image signal lines, source lines and the like), and the display panel DP [2, 1] has n signal lines SLb.
  • n signal lines SLa and the n signal lines SLb extends in the column direction.
  • the n signal lines SLa and the n signal lines SLb are electrically connected to the plurality of pixels 25 arranged in the column direction.
  • signal lines provided in a display device of one embodiment of the present invention such as the signal line SLa and the signal line SLb, may be referred to as a signal line SL.
  • the signal line SL electrically connected to the pixel 25 in the j-th column (j is an integer of 1 or more and n or less) is referred to as a signal line SL [j].
  • the symbol or code representing the element in the j-th column may be distinguished by adding [j].
  • Signal line SLa is electrically connected to signal line drive circuit 23A
  • signal line SLb is electrically connected to signal line drive circuit 23B
  • the signal line drive circuit 23A has a function of supplying an image signal to the signal line SLa
  • the signal line drive circuit 23B has a function of supplying an image signal to the signal line SLb.
  • the image signal is supplied to the pixel 25 of the pixel unit 21A through the signal line SLa, and is supplied to the pixel 25 of the pixel unit 21B through the signal line SLb.
  • the pixel 25 has a display element.
  • a light emitting element can be given as an example of the display element provided in the pixel 25.
  • Examples of light emitting elements include self-luminous light emitting elements such as organic light emitting diodes (OLEDs), light emitting diodes (LEDs), quantum-dot light emitting diodes (QLEDs), and semiconductor lasers.
  • OLEDs organic light emitting diodes
  • LEDs light emitting diodes
  • QLEDs quantum-dot light emitting diodes
  • semiconductor lasers semiconductor lasers.
  • a bright image can be displayed and display quality can be improved by using a light-emitting element, in particular an OLED or a micro LED, as a display element.
  • a display device having a light-emitting element does not require a backlight, so that a thin display device can be provided.
  • a flexible display device can be provided.
  • a display device with a wide viewing angle can be provided.
  • liquid crystal element may be used as the display element.
  • liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements.
  • a shutter type MEMS (Micro Electro Mechanical System) element As a display element, a shutter type MEMS (Micro Electro Mechanical System) element, an optical interference type MEMS element, a microcapsule type, an electrophoresis type, an electrowetting type, an electronic powder fluid (registered trademark) type, etc. are applied.
  • a display element or the like may be used.
  • the number of pixels 25 provided in the display unit 20A can be freely set. In order to increase the size of the display unit 20A and to display a high definition image, it is preferable to dispose a large number of pixels 25. For example, in the case of displaying a 2K image, it is preferable to provide 1920 ⁇ 1080 or more pixels. Further, in the case of displaying a 4K image, it is preferable to provide 3840 ⁇ 2160 or more pixels, or 4096 ⁇ 2160 or more pixels. In the case of displaying an 8K image, it is preferable to provide 7680 ⁇ 4320 or more pixels, or 8192 ⁇ 4320 or more pixels. In addition, more pixels can be provided in the display unit 20A.
  • the size of one display panel DP does not have to be large. Therefore, it is not necessary to increase the size of the manufacturing apparatus for manufacturing the display panel DP, and space can be saved. In addition, since it is possible to use a medium-to-small display panel manufacturing apparatus and not to use a new manufacturing apparatus for increasing the size of the display unit 20A, the manufacturing cost can be reduced. In addition, it is possible to suppress a decrease in yield due to the enlargement of the display panel DP.
  • the display unit having a plurality of display panels DP has a wider display area than the display unit having one display panel DP, and the amount of information which can be displayed at one time is large. And so on.
  • Each of the plurality of pixels 25 illustrated in FIG. 2 can have a function of emitting light of red (R), green (G), or blue (B).
  • each of the plurality of pixels 25 illustrated in FIG. 2 can have a function of emitting light of red (R), green (G), blue (B), or white (W).
  • R red
  • G green
  • B blue
  • W white
  • the pixels 25 capable of emitting light of different colors in the pixel portion 21A and the pixel portion 21B full-color display can be performed. Note that when the pixels 25 capable of emitting light of different colors are provided in the pixel portion 21A and the pixel portion 21B, the pixels 25 can be referred to as sub-pixels.
  • the display panel DP has a non-display area so as to surround the pixel unit 21. At this time, for example, when one image is displayed by combining output images of a plurality of display panels DP, the one image is visually perceived as separated by the user of the display device 10A.
  • the distance between the end of the display panel DP and the element in the display panel DP becomes short, and the element is degraded by impurities entering from the outside of the display panel DP. It may be easier.
  • a plurality of display panels DP are arranged so as to overlap with each other.
  • the display panel DP positioned at least on the display surface side (upper side) of the two superimposed display panels DP has a region transmitting visible light adjacent to the pixel portion 21.
  • the pixel portion 21 of the display panel DP disposed on the lower side and the region transmitting visible light of the display panel DP disposed on the upper side overlap with each other. Therefore, the non-display area between the pixel portions 21 of the two overlapped display panels DP can be reduced or eliminated. As a result, it is possible to realize a large display unit 20A in which the user can not easily recognize the joints of the display panel DP.
  • At least a part of the non-display area of the display panel DP located on the upper side is an area that transmits visible light, and can overlap with the pixel portion 21 of the display panel DP located on the lower side.
  • at least a part of the non-display area of the display panel DP located on the lower side can be overlapped with the pixel portion 21 of the display panel DP located on the upper side or an area that blocks visible light. In these parts, since the narrowing of the frame (reduction of the area other than the pixel part) of the display unit 20A is not affected, the area may not be reduced.
  • the distance between the end of the display panel DP and the element in the display panel DP becomes long, and deterioration of the element by impurities entering from the outside of the display panel DP can be suppressed .
  • impurities such as moisture or oxygen penetrate the organic EL element from the outside of the display panel DP. It becomes difficult (or hard to reach).
  • the area of the non-display region of the display panel DP can be sufficiently ensured, and therefore, a large display portion with high reliability can be obtained even if the display panel DP using an organic EL element or the like is applied 20A can be realized.
  • the plurality of display panels DP be arranged such that the pixel units 21 are continuous between the adjacent display panels DP.
  • FIG. 3A shows a configuration example of the display panel DP
  • FIG. 3B shows an arrangement example of the display panel DP.
  • the display panel DP illustrated in FIG. 3A includes the pixel portion 21, a region 72 which transmits visible light, and a region 73 which blocks visible light.
  • the region 72 transmitting visible light and the region 73 blocking visible light are provided adjacent to the pixel portion 21 respectively.
  • FIG. 3A shows an example in which a flexible printed circuit (FPC) 74 is provided on the display panel DP.
  • FPC flexible printed circuit
  • the pixel unit 21 includes a plurality of pixels 25.
  • the region 72 which transmits visible light may be provided with a pair of substrates constituting the display panel DP, a sealing material for sealing a display element held between the pair of substrates, and the like.
  • a material having transparency to visible light is used as a member provided in the region 72 which transmits visible light.
  • a wire or the like electrically connected to the pixel 25 included in the pixel unit 21 may be provided in the area 73 for blocking visible light.
  • one or both of the scanning line drive circuit 22 and the signal line drive circuit 23 may be provided in the area 73 for blocking visible light.
  • a terminal connected to the FPC 74, a wire connected to the terminal, or the like may be provided in the region 73 for blocking visible light.
  • FIG. 3B is an example in which two display panels DP shown in FIG. 3A are arranged in the vertical direction (row direction), and is a perspective view of the display surface side of the display panel DP.
  • the two display panels DP are arranged so as to have overlapping regions. Specifically, a region 72 transmitting visible light included in the display panel DP [2, 1] is disposed so as to overlap on the pixel portion 21A (display surface side). Thereby, the area where the pixel portion 21A and the pixel portion 21B are arranged substantially without a seam can be set as the display area 29 of the display portion 20A.
  • the display panel DP preferably has flexibility.
  • the pair of substrates that constitute the display panel DP preferably has flexibility.
  • the display panel DP [2, 1] can be gently curved so that the height of the upper surface of the pixel section 21B matches the height of the upper surface of the pixel section 21A. Therefore, it is possible to make the heights of the display areas uniform except in the vicinity of the area where the display panel DP [1, 1] and the display panel DP [2, 1] overlap, and the display quality of the image displayed in the display area 29 Can be enhanced.
  • the thickness of the display panel DP is preferably thin in order to reduce a step between the two adjacent display panels DP.
  • the thickness of the display panel DP is preferably 1 mm or less, more preferably 300 ⁇ m or less, and still more preferably 100 ⁇ m or less.
  • an area where the display panel DP is adjacent that is, an area (joint area S in the drawing) of the joint of the display panel DP exists.
  • an area joint area S in the drawing
  • the characteristics of the transistor of the pixel 25 or the size of the capacitive element, the parasitic resistance or parasitic capacitance of the signal line SL, the drive capability of the signal line drive circuit 23, and the like may vary among the display panels DP. Therefore, when the image signal is supplied to each display panel DP, an error occurs in the display image for each display panel DP, and the image may be discontinuous in the area of the joint. Further, as shown in FIG. 3B, in the case where the pixel portion 21 of one display panel DP has a region overlapping with the region 72 which transmits visible light of the other display panel DP, the pixel portion 21 is formed in the joint region.
  • first image data SD1 [1,1] and first image data SD1 [2,1] obtained by dividing the first image data SD1 generated by the processing unit 33 as it is is displayed on each display panel DP.
  • the discontinuous image can be viewed in the area S, as shown in FIG. 4 (B).
  • the processing unit 40A of the display device 10A can correct the first image data SD1 so as to alleviate the discontinuity of the image at the joint of the two display panels DP.
  • the display unit 20A is configured using a plurality of display panels DP, it is possible to make visual disturbances in the joints of the display panels DP less visible.
  • the difference between the color tone of each display panel for example, the difference between the color tone of the image displayed on the display panel DP [1, 1] and the color tone of the image displayed on the display panel DP [2, 1] be able to.
  • the display quality can be improved.
  • FIGS. 5A and 5B are flowcharts illustrating a method of creating a correction filter used to reduce image discontinuity at the joint of the display panel DP.
  • the processing unit 40A supports the correction filter used to correct the image data corresponding to the image displayed on the display panel DP [1, 1] and the image displayed on the display panel DP [2, 1].
  • a correction filter used to correct image data to be corrected is created (step S01).
  • a correction filter used to correct image data corresponding to an image displayed on the display panel DP [1, 1] is referred to as a first correction filter.
  • a correction filter used to correct image data corresponding to an image displayed on the display panel DP [2, 1] is referred to as a second correction filter.
  • the first correction filter can be, for example, a correction filter for reducing display unevenness of an image displayed on the display panel DP [1, 1].
  • the second correction filter can be, for example, a correction filter for reducing display unevenness of an image displayed on the display panel DP [2, 1].
  • the details of the method of creating the first correction filter and the second correction filter will be described later, but when the first correction filter displays an image of a specific tone value, for example, on the display panel DP [1, 1] The variation in the brightness of light emitted from the pixel 25 between the pixels 25 can be reduced.
  • the second correction filter for example, reduces variation among the pixels 25 in the luminance of light emitted from the pixels 25 when an image of a specific gradation value is displayed on the display panel DP [2, 1]. Can be created as
  • an image of a specific tone value indicates, for example, an image in which the tone values of all pixels are equal.
  • an image having a specific gradation value is to be an image in which the gradation values of all the pixels 25 are equal, for example, it is preferable to set an image in which the gradation values of all the pixels 25 are intermediate gradations.
  • the gradation value that can be expressed by the pixel 25 is 0 to 255, it is preferable to set an image in which the gradation value of all the pixels 25 is 127 or near. For example, it is preferable that it is a full gray image.
  • the first correction filter has, for example, data representing a correction intensity for each pixel 25 of the luminance of the light emitted from the pixel 25 of the display panel DP [1, 1].
  • the second correction filter has, for example, data representing the correction intensity for each pixel 25 of the luminance of light emitted from the pixel 25 of the display panel DP [2, 1].
  • values such as correction strength represented by data of the correction filter are referred to as filter values.
  • the first correction filter can be said to have filter values equal in number to the number of pixels of the pixels 25 provided in the display panel DP [1, 1], for example.
  • the second correction filter can be said to have filter values equal in number to the number of pixels of the pixels 25 provided in the display panel DP [2, 1], for example.
  • the processing unit 40A corrects the image data corresponding to the image of the specific tone value using the first correction filter, and the image corresponding to the corrected image data is displayed on the display panel DP [1 , 1]. Further, the processing unit 40A corrects the image data corresponding to the image of the specific tone value using the second correction filter, and the image corresponding to the image data after the correction is displayed on the display panel DP [2,, Displayed in 1]. Thereafter, the brightness of light emitted from the pixels 25 provided in the boundary portion 28A and the boundary portion 28B is measured using a two-dimensional luminance meter or the like (step S02).
  • the brightness of light emitted from the pixel 25 provided in the boundary portion 28A is compared with the brightness of light emitted from the pixel 25 provided in the boundary portion 28B (step S03).
  • the average value of the luminances of light emitted from the pixels 25 provided in the boundary portion 28A is compared with the average value of the luminances of light emitted from the pixels 25 provided in the boundary portion 28B.
  • the processing unit 40A corrects the correction filter (step S04). For example, when an average value of luminances of light emitted from the pixels 25 provided in the boundary portion 28A is L A , and an average value of luminances of light emitted from the pixels 25 provided in the boundary portion 28B is L B The second correction filter is corrected such that the luminance of light emitted from the pixel 25 provided in the pixel unit 21B is multiplied by L A / L B.
  • the first correction filter is corrected such that the luminance of light emitted from the pixel 25 provided in the pixel unit 21A is multiplied by L B / L A.
  • the brightness of light emitted from the pixel 25 in the pixel portion 21A (L A + L B) / 2L A modifies the first correction filter as multiplying the pixels provided in the pixel portion 21B
  • the second correction filter is corrected so as to multiply the luminance of the light emitted from 25 by (L A + L B ) / 2L B.
  • a new correction filter is created.
  • the above is an example of the method of creating the correction filter used in the display device 10A.
  • the correction filter is corrected to correct the luminance of light emitted from all the pixels 25 provided in the pixel unit 21A and / or the pixel unit 21B based on the comparison result.
  • the correction filter may be modified to correct the luminance of the light emitted from the pixel 25 provided in the boundary portion 28A and / or the boundary portion 28B based on the comparison result.
  • the luminance of light emitted from all of the pixels 25 provided in the boundary portion 28A and / or the boundary portion 28B and a part of the pixels 25 provided in the other region is based on the above comparison result.
  • the correction filter may be corrected to perform the correction. For example, as shown in FIG. 3B, even if the correction filter is corrected so as to correct the luminance of light emitted from the pixel 25 provided in the area overlapping with the area 72 based on the comparison result. Good.
  • step S11 the processing unit 40A creates a first correction filter and a second correction filter (step S11).
  • a filter value corresponding to the pixel 25 provided in the boundary portion 28A, which the first correction filter has, and a filter value corresponding to the pixel 25 provided in the boundary portion 28B, which the second correction filter has (Step S12).
  • the average value of the filter values corresponding to the pixels 25 provided in the boundary portion 28A is compared with the average value of the filter values corresponding to the pixels 25 provided in the boundary portion 28B.
  • the correction filter is corrected based on the comparison result. For example, the average value of the filter value corresponding to the pixel 25 provided in the boundary portion 28A D A, the average value of the filter value corresponding to the pixel 25 provided in the boundary portion 28B if a D B, of the second The second correction filter is corrected such that the filter values of the correction filter are multiplied by D A / D B respectively.
  • the first correction filter is corrected so that, for example, the filter values of the first correction filter are multiplied by D B / D A , respectively.
  • the first correction filter is corrected so that the filter value of the first correction filter is multiplied by (D A + D B ) / 2D A , respectively, and the filter value of the second correction filter is changed to (D A Correct the second correction filter so as to multiply + D B ) / 2D B.
  • a new correction filter is created.
  • the correction filter is corrected to perform correction based on the comparison result for filter values corresponding to all the pixels 25 provided in the pixel unit 21A and / or the pixel unit 21B.
  • the correction filter may be modified to perform correction based on the comparison result for the filter value corresponding to the pixel 25 provided in the boundary portion 28A and / or the boundary portion 28B.
  • the correction filter may be modified to For example, as shown in FIG. 3B, the correction filter may be modified so that correction based on the comparison result is performed on the filter value corresponding to the pixel 25 provided in the area overlapping with the area 72.
  • the correction filter may be further modified to adjust the correction intensity for each pixel 25.
  • the correction intensity for the pixels 25 provided outside the boundary 28A may be weaker than the correction intensity for the pixels 25 provided in the boundary 28A.
  • the correction intensity for the pixel 25 provided outside the boundary portion 28B is weaker than the correction intensity for the pixel 25 provided in the boundary portion 28B. It is also good.
  • the processing unit 40A corrects, for example, the first image data SD1 corresponding to a signal input from the outside using the correction filter, and generates the second image data SD2. .
  • the dividing unit 45A converts the second image data SD2 into image data SD2 [1,1] corresponding to an image displayed on the display panel DP [1,1], and the display panel DP [2,1]. Is divided into image data SD2 [2, 1] corresponding to the image displayed on Thereafter, an image corresponding to the image data SD2 [1,1] is displayed on the pixel unit 21A, and an image corresponding to the image data SD2 [2,1] is displayed on the pixel unit 21B.
  • the above is an example of the operation method of the display device 10A.
  • the correction filter may be further corrected.
  • the correction filter may be modified so as to remove noise that is difficult to remove depending on the correction filter created by the method shown in FIGS. 5A and 5B.
  • the correction filter may be modified to make it difficult to visually recognize a defect such as a pixel drop.
  • the correction filter may be modified so that the same processing as the image processing that can be performed by the processing unit 33 can be performed.
  • the correction filter can be corrected, for example, so that the correction filter created by the method shown in FIGS. 5A and 5B has a function as a smoothing filter. Accordingly, the display quality of the display device of one embodiment of the present invention can be further enhanced.
  • the correction of the correction filter may be performed, for example, between step S01 and step S02 and between step S11 and step S12.
  • the processing unit 40A creates a new correction filter, when the correction filter is further corrected, the processing unit 33 can be omitted.
  • FIGS. 1 to 5 have two display panels DP aligned in the horizontal direction (column direction).
  • the display panel DP [1,1] and the display panel DP [1,1 Even when 2] is provided it is applicable.
  • the term “row” is “column”
  • the term “m line” is “n column”
  • the term “display panel DP [2,1]” is “display panel DP [1 , 2]] and rephrased accordingly.
  • FIGS. 6A, 6B, and 6C are schematic views showing an example of a method of creating a correction filter, and the operation proceeds in the order of (A), (B), and (C).
  • the display panel DP [1, 1], the display panel DP [2, 1], and the display panel DP [1, 1] are used as the display panel DP of 2 rows and 2 columns. 2] and a display panel DP [2, 2].
  • the boundary between the display panel DP [1,1] and the display panel DP [2,1] is referred to as a boundary 28A.
  • the boundary between the display panel DP [2, 1] and the display panel DP [1, 1] is referred to as a boundary 28B.
  • the boundary between the display panel DP [1, 2] and the display panel DP [2, 2] is referred to as a boundary 28C.
  • the boundary between the display panel DP [2, 2] and the display panel DP [1, 2] is referred to as a boundary 28D.
  • the boundary between the display panel DP [1, 1] and the display panel DP [1, 2] is referred to as a boundary 29A. Further, the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is referred to as a boundary 29B. Further, the boundary between the display panel DP [1, 2] and the display panel DP [1, 1] is referred to as a boundary 29C. Further, the boundary between the display panel DP [2, 2] and the display panel DP [2, 1] is referred to as a boundary 29D.
  • step S03 shown to FIG. 5 (A) the brightness
  • the filter value corresponding to the pixel 25 provided in the boundary portion 28C is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 28D.
  • no image is formed at the joint between the display panel DP [1, 1] and the display panel DP [2, 1] and at the joint between the display panel DP [1, 2] and the display panel DP [2, 2]. Continuity is relaxed.
  • the luminance of light emitted from the pixels 25 provided in the boundary portion 28A and the boundary portion 28C is collectively compared with the luminance of light emitted from the pixels 25 provided in the boundary portion 28B and the boundary portion 28D. It is also good. That is, provided, for example pixels 25 provided in the boundary portion 28A, and the light emitted from the pixel 25 provided in the boundary portion 28C Average value L AC luminance pixels 25 provided in the boundary portion 28B, and the boundary portion 28D it may be compared with the average value L BD of the luminance of light emitted from the pixel 25 to be.
  • the filter values corresponding to the pixels 25 provided in the boundary portion 28A and the boundary portion 28C may be collectively compared with the filter values corresponding to the pixels 25 provided in the boundary portion 28B and the boundary portion 28D.
  • pixels to be provided for example pixels 25 provided in the boundary portion 28A, and the average value D AC filter values corresponding to the pixels 25 provided in the boundary portion 28C, the pixels 25 provided in the boundary portion 28B, and the boundary portion 28D It may be compared with the average value D BD of the filter values corresponding to 25.
  • step S03 shown in FIG. 5A the luminance of the light emitted from the pixel 25 provided in the boundary portion 29A and the luminance of the light emitted from the pixel 25 provided in the boundary portion 29C, Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary portion 29A is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 29C.
  • step S03 shown in FIG. 5A the luminance of the light emitted from the pixel 25 provided in the boundary portion 29B and the luminance of the light emitted from the pixel 25 provided in the boundary portion 29D, Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary portion 29B is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 29D.
  • the comparison between the luminance of light emitted from the pixel 25 provided in the boundary portion 29A and the luminance of light emitted from the pixel 25 provided in the boundary portion 29C may not necessarily be performed. Further, the comparison between the filter value corresponding to the pixel 25 provided in the boundary portion 29A and the filter value corresponding to the pixel 25 provided in the boundary portion 29C may not necessarily be performed.
  • FIGS. 7A, 7B, and 7C are schematic views showing an example of a method of creating a correction filter, and the operation proceeds in the order of (A), (B), and (C).
  • the display panel DP [1, 1], the display panel DP [2, 1], and the display panel DP [1, 1] are used as the display panel DP of 2 rows and 3 columns. 2], display panel DP [2, 2], display panel DP [1, 3], and display panel DP [2, 3].
  • the boundary between the display panel DP [1, 2] and the display panel DP [1, 3] is referred to as a boundary 29E.
  • the boundary between the display panel DP [2, 2] and the display panel DP [2, 3] is referred to as a boundary 29F.
  • boundary 29G the boundary between the display panel DP [1, 3] and the display panel DP [1, 2] is referred to as a boundary 29G.
  • boundary 29H the boundary between the display panel DP [2, 3] and the display panel DP [2, 2] is referred to as a boundary 29H.
  • the operations shown in 6 (A), (B) and (C) are performed.
  • the operation illustrated in FIG. 5A or 5B is performed on the display panel DP [1, 3] and the display panel DP [2, 3].
  • step S03 shown to FIG. 5 (A) the brightness
  • step S12 shown in FIG. 5B the filter value corresponding to the pixel 25 provided in the boundary 29E is compared with the filter value corresponding to the pixel 25 provided in the boundary 29G.
  • step S03 shown to FIG. 5 (A) the brightness
  • step S12 shown in FIG. 5B the filter value corresponding to the pixel 25 provided in the boundary 29F is compared with the filter value corresponding to the pixel 25 provided in the boundary 29H.
  • FIG. 8 (A) and (B) are circuit diagram showing a configuration example of the pixel 25 having a light emitting element.
  • FIG. 8B is a circuit diagram showing a configuration example of the pixel 25 having a liquid crystal element.
  • the pixel 25 illustrated in FIG. 8A includes a transistor 446, a capacitor 433, a transistor 251, a transistor 444, and a light emitting element 170.
  • One of the source and the drain of the transistor 446 is electrically connected to a signal line SL to which an image signal is supplied.
  • the gate of the transistor 446 is electrically connected to the scan line GL to which the selection signal is supplied.
  • the transistor 446 has a function of controlling writing of the image signal to the node 445.
  • One electrode of the capacitor 433 is electrically connected to the node 445, and the other electrode of the capacitor 433 is electrically connected to the node 447.
  • the other of the source and the drain of the transistor 446 is electrically connected to the node 445.
  • the capacitor 433 has a function as a storage capacitor which holds data written to the node 445.
  • One of the source or the drain of the transistor 251 is electrically connected to the potential supply line VL_a, and the other of the source or the drain of the transistor 251 is electrically connected to the node 447. Further, the gate of the transistor 251 is electrically connected to the node 445.
  • One of the source or the drain of the transistor 444 is electrically connected to the potential supply line V0, and the other of the source or the drain of the transistor 444 is electrically connected to the node 447. Further, the gate of the transistor 444 is electrically connected to the scan line GL.
  • One electrode of the light emitting element 170 is electrically connected to the potential supply line VL_b, and the other electrode of the light emitting element 170 is electrically connected to the node 447.
  • the power supply potential for example, a relatively high potential side potential or a low potential side potential can be used.
  • the power supply potential on the high potential side is referred to as a high power supply potential (also referred to as "VDD")
  • the power supply potential on the low potential side is referred to as a low power supply potential (also referred to as "VSS").
  • the ground potential can also be used as a high power supply potential or a low power supply potential.
  • the high power supply potential is the ground potential
  • the low power supply potential is a potential lower than the ground potential
  • the low power supply potential is the ground potential
  • the high power supply potential is a potential higher than the ground potential.
  • the high power supply potential VDD is supplied to one of the potential supply line VL_a or the potential supply line VL_b
  • the low power supply potential VSS is supplied to the other of the potential supply line VL_a or the potential supply line VL_b.
  • the pixels 25 in each row are sequentially selected by the scan line driver circuit 22, and the transistor 446 and the transistor 444 are turned on to write an image signal to the node 445.
  • the pixel 25 whose data is written to the node 445 is held by turning off the transistor 446 and the transistor 444. Further, the amount of current flowing between the source and the drain of the transistor 251 is controlled in accordance with the potential of the data written to the node 445, and the light emitting element 170 emits light with luminance according to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.
  • the pixel 25 illustrated in FIG. 8B includes a transistor 446, a capacitor 433, and a liquid crystal element 180.
  • the potential of one of the electrodes of the liquid crystal element 180 is appropriately set in accordance with the specification of the pixel 25.
  • the alignment state of the liquid crystal element 180 is set by data written to the node 445. Note that a common potential (common potential) may be applied to one of the electrodes of the liquid crystal element 180 included in each of the plurality of pixels 25. Further, different potentials may be applied to one electrode of the liquid crystal element 180 for each pixel 25 of each row.
  • one of the source and the drain of the transistor 446 is electrically connected to the signal line SL, and the other is electrically connected to the node 445.
  • the gate of the transistor 446 is electrically connected to the scan line GL.
  • the transistor 446 has a function of controlling writing of an image signal to the node 445.
  • One electrode of the capacitor 433 is electrically connected to a wiring (hereinafter, a capacitor line CL) to which a specific potential is supplied, and the other electrode of the capacitor 433 is electrically connected to the node 445. Further, the other electrode of the liquid crystal element 180 is electrically connected to the node 445. Note that the value of the potential of the capacitor line CL is appropriately set in accordance with the specification of the pixel 25.
  • the capacitor 433 has a function as a storage capacitor which holds data written to the node 445.
  • the scan line driver circuit 22 sequentially selects the pixels 25 in each row, turns on the transistor 446, and writes an image signal to the node 445.
  • the pixel 25 whose image signal is written to the node 445 is held as the transistor 446 is turned off. Images can be displayed by sequentially performing this on a row-by-row basis.
  • FIG. 9 is a block diagram showing a configuration example of the display device 10B.
  • the display device 10B has a function of generating image data using data received from the outside, and a function of displaying an image based on the image data.
  • the display device 10B includes a display unit 20B and a signal generation unit 30B. Similar to the display unit 20A, the display unit 20B includes a plurality of display panels DP. Similar to the signal generation unit 30A, the signal generation unit 30B has a function of generating image data using data received from the outside.
  • FIG. 9 shows an example in which the display panel DP is arranged in two rows and one column on the display unit 20B.
  • the display of the display panel DP can be controlled independently. Similar to the display unit 20A, the display unit 20B may arrange the display panels DP in three or more rows or in two or more columns.
  • the signal generation unit 30B includes a front end unit 31, a decoder 32, a processing unit 33, a reception unit 34, an interface 35, a control unit 36, a processing unit 40B, and a division unit 45B.
  • the processing unit 40B has a function of creating a correction filter.
  • the processing unit 40B may not have the function of correcting the first image data SD1 using the created correction filter. Then, the created correction filter is output as the correction filter FIL to the dividing unit 45B together with the first image data SD1 that is the image data before correction.
  • the dividing unit 45B has a function of dividing the first image data SD1 input from the processing unit 40A and the correction filter FIL.
  • the first image data SD1 and the correction filter FIL can be divided into the same number as the display panels DP provided in the display unit 20B.
  • the first image data SD1 is divided into 2 ⁇ 1 pieces (first image data SD1 [1,1] and first image data [2,1]) and output to the display unit 20B.
  • Ru Further, the correction filter FIL is divided into 2 ⁇ 1 pieces (the correction filter FIL [1, 1] and the correction filter FIL [2, 1]), and is output to the display unit 20B.
  • the first image data SD1 [1,1] and the correction filter FIL [1,1] are output to the display panel DP [1,1], and the first image data SD1 [2,1] and The correction filter FIL [2, 1] is output to the display panel DP [2, 1].
  • a pixel provided in the display panel DP has a memory circuit, and the memory circuit can hold the correction filter FIL. Thereby, the correction of the first image data SD1 can be performed inside the pixel without performing the correction in the processing unit 40B. Therefore, the configuration of the processing unit 40B can be simplified, and power consumption of the display device of one embodiment of the present invention can be reduced.
  • FIG. 10 shows a configuration example of the display panel DP [1, 1] and the display panel DP [2, 1] provided in the display device 10B having the configuration shown in FIG.
  • the display panel DP [1,1] having the configuration shown in FIG. 10 has the pixel portion 21A, the scanning line drive circuit 22A, and the signal line drive circuit 23A, similarly to the display panel DP [1,1] having the configuration shown in FIG. Have.
  • the display panel DP [2,1] having the configuration shown in FIG. 10 has the pixel portion 21B, the scanning line drive circuit 22B, and the signal line drive circuit 23B, similarly to the display panel DP [2,1] having the configuration shown in FIG. Have.
  • the pixel portion 21A and the pixel portion 21B each have a plurality of pixels 26.
  • FIG. 10 shows an example in which the pixel portion 21A and the pixel portion 21B each have a plurality of pixels 26 arranged in a matrix of m rows and n columns.
  • the pixel 26 is provided with a memory circuit MEM.
  • the memory circuit MEM has a function of holding the correction filter FIL.
  • the display panel DP [1,1] has m scanning lines GL1a, m scanning lines GL2a, and m scanning lines GL3a, and the display panel DP [2,1] includes m scanning lines There are GL1 b, m scanning lines GL2 b, and m scanning lines GL3 b.
  • the m scanning lines GL1a, scanning lines GL1b, scanning lines GL2a, scanning lines GL2b, scanning lines GL3a, and scanning lines GL3b extend in the row direction.
  • the m scanning lines GL1a are electrically connected to the memory circuits MEM provided in the pixels 26 aligned in the row direction in the pixel section 21A, and the m scanning lines GL1b are each in the row direction in the pixel section 21B.
  • the m scanning lines GL2a and the scanning line GL3a are electrically connected to the pixels 26 aligned in the row direction in the pixel unit 21A, and the m scanning lines GL2b and the scanning line GL3b are each connected to the pixel unit 21B.
  • scan line drive circuit 22A One end of scan line GL1a, scan line GL2a, and scan line GL3a is electrically connected to scan line drive circuit 22A, and one end of scan line GL1b, scan line GL2b, and scan line GL3b is connected to scan line drive circuit 22B. Electrically connected.
  • the scan line drive circuit 22A has a function of supplying selection signals to the scan line GL1a, the scan line GL2a, and the scan line GL3a
  • the scan line drive circuit 22B corresponds to the scan line GL1b, the scan line GL2b, and the scan line GL3b. It has a function of supplying a selection signal.
  • a scan line provided in a display device of one embodiment of the present invention such as the scan line GL1a and the scan line GL1b, may be referred to as a scan line GL1.
  • a scan line provided in a display device of one embodiment of the present invention such as the scan line GL2a and the scan line GL2b, may be referred to as a scan line GL2.
  • a scan line provided in a display device of one embodiment of the present invention, such as the scan line GL3a and the scan line GL3b may be referred to as a scan line GL3.
  • the display panel DP [1,1] has n signal lines SL1a and n signal lines SL2a
  • the display panel DP [2,1] has n signal lines SL1b and n signals. It has a line SL2b.
  • Each of the n signal lines SL1a, SL1b, SL2a, and SL2b extends in the column direction.
  • the n signal lines SL1a are electrically connected to the memory circuits MEM provided in the plurality of pixels 26 aligned in the column direction in the pixel unit 21A
  • the n signal lines SL1b are each connected in the pixel unit 21B. It is electrically connected to the memory circuit MEM provided in the plurality of pixels 26 aligned in the column direction.
  • Each of the n signal lines SL2a is electrically connected to the plurality of pixels 26 aligned in the column direction in the pixel section 21A
  • each of the n signal lines SL2b is a plurality of pixels aligned in the column direction in the pixel section 21B. It is electrically connected to 26.
  • the signal line SL1a and the signal line SL2a are electrically connected to the signal line drive circuit 23A, and the signal line SL1b and the signal line SL2b are electrically connected to the signal line drive circuit 23B.
  • the signal line drive circuit 23A has a function of supplying a signal corresponding to the correction filter to the signal line SL1a
  • the signal line drive circuit 23B has a function of supplying a signal corresponding to the correction filter to the signal line SL1b.
  • a signal corresponding to the correction filter is referred to as a correction filter signal.
  • the correction filter signal is supplied to the memory circuit MEM via the signal line SL1a or the signal line SL1b.
  • the signal line drive circuit 23A has a function of supplying an image signal to the signal line SL2a
  • the signal line drive circuit 23B has a function of supplying an image signal to the signal line SL2b.
  • the image signal is supplied to the pixel 26 via the signal line SL2a or the signal line SL2b.
  • signal lines provided in a display device of one embodiment of the present invention such as the signal line SL1a and the signal line SL1b, may be referred to as a signal line SL1.
  • a signal line provided in a display device of one embodiment of the present invention such as the signal line SL2a and the signal line SL2b, may be referred to as a signal line SL2.
  • the pixel 26 has a display element.
  • a display element provided in the pixel 26 for example, a light emitting element or a liquid crystal element can be used similarly to the display element provided in the pixel 25.
  • Each of the plurality of pixels 26 illustrated in FIG. 10 can have a function of emitting light of red (R), green (G), or blue (B) similarly to the pixel 25.
  • each of the plurality of pixels 26 illustrated in FIG. 10 can have a function of emitting light of red (R), green (G), blue (B), or white (W).
  • two display panels DP are arranged in the horizontal direction (column direction).
  • the display panel DP [1, 1] and the display panel DP [1, 2] Can be applied even if.
  • the term "display panel DP [2, 1]" is appropriately rephrased as "display panel DP [1, 2]”.
  • Pixel configuration example 2> Below, the structural example of the pixel 26 is demonstrated using FIG.
  • FIG. 11 is a circuit diagram showing a configuration example of the pixel 26.
  • a pixel 26 configured as shown in FIG. 11 includes a transistor 101, a transistor 102, a transistor 111, a transistor 112, a capacitor 103, a capacitor 113, and a light emitting element 104.
  • an organic EL element, an inorganic EL element, or the like can be used as the light emitting element 104.
  • One of the source and the drain of the transistor 101 is electrically connected to one electrode of the capacitor 113.
  • the other electrode of the capacitor 113 is electrically connected to one of the source and the drain of the transistor 111.
  • One of the source and the drain of the transistor 111 is electrically connected to the gate of the transistor 112.
  • the gate of the transistor 112 is electrically connected to one electrode of the capacitor 103.
  • the other electrode of the capacitor 103 is electrically connected to one of the source and the drain of the transistor 112.
  • One of the source or the drain of the transistor 112 is electrically connected to one of the source or the drain of the transistor 102.
  • the other of the source and the drain of the transistor 102 is electrically connected to one electrode of the light-emitting element 104.
  • a wiring to which the other electrode of the capacitor 113, one of the source or the drain of the transistor 111, the gate of the transistor 112, and one electrode of the capacitor 103 is connected is a node NM1.
  • a wiring to which the other of the source and the drain of the transistor 102 and one electrode of the light-emitting element 104 is connected is a node NA1.
  • the gate of the transistor 101 is electrically connected to the scan line GL2.
  • the gate of the transistor 102 is electrically connected to the scan line GL3.
  • the gate of the transistor 111 is electrically connected to the scan line GL1.
  • the other of the source and the drain of the transistor 101 is electrically connected to the signal line SL2.
  • the other of the source and the drain of the transistor 111 is electrically connected to the signal line SL1.
  • the other of the source and the drain of the transistor 112 is electrically connected to the potential supply line 128.
  • the other electrode of the light emitting element 104 is electrically connected to the common wiring 129.
  • the high power supply potential VDD can be supplied to the potential supply line 128.
  • any potential can be supplied to the common wiring 129.
  • the transistor 111 and the capacitor 113 form a memory circuit MEM.
  • the node NM1 is a storage node, and by turning on the transistor 111, the signal supplied to the signal line SL1 can be written to the node NM1.
  • the potential of the node NM1 can be held for a long time.
  • a transistor in which a metal oxide is used for a channel formation region hereinafter referred to as an OS transistor
  • an OS transistor can be used as the transistor.
  • the OS transistor may be applied not only to the transistor 111 but also to other transistors included in the pixel 26.
  • a transistor having Si in a channel formation region (hereinafter, a Si transistor) may be applied to the transistor 111.
  • both an OS transistor and a Si transistor may be used.
  • the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low temperature polysilicon), a transistor having single crystal silicon, and the like.
  • a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used.
  • an oxide semiconductor or the like containing indium can be used, for example, CAAC-OS or CAC-OS described later.
  • the CAAC-OS is suitable for a transistor or the like in which the atoms constituting the crystal are stable and reliability is important.
  • CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like which performs high-speed driving.
  • An OS transistor exhibits extremely low off-current characteristics because of its large energy gap.
  • the OS transistor has characteristics different from Si transistors, such as no impact ionization, avalanche breakdown, short channel effect and the like, and can form a highly reliable circuit.
  • a silicon substrate can be used and a region where an Si transistor and an OS transistor overlap with each other can be formed. Therefore, the pixel density can be improved even if the number of transistors is relatively large.
  • the signal written to the node NM1 is capacitively coupled to the image signal supplied from the signal line SL2, and can be output to the node NA1.
  • the transistor 101 has a function of selecting a pixel.
  • the transistor 102 has a function as a switch which controls light emission of the light emitting element 104.
  • the transistor 112 when the potential of the signal written from the signal line SL1 to the node NM1 is larger than the threshold voltage (V th ) of the transistor 112, the transistor 112 is turned on before the image signal is written, and the light emitting element 104 emits light. It will Therefore, it is preferable that the transistor 102 be provided and the transistor 102 be turned on after the potential of the node NM1 is determined to cause the light emitting element 104 to emit light.
  • the correction filter signal corresponding to the correction filter FIL created by the processing unit 40B is stored in the node NM1, the correction filter signal can be added to the image signal. Thereby, the image signal can be corrected.
  • the correction filter signal since the correction filter signal may be attenuated by an element on the transmission path, it is preferable to generate in consideration of the attenuation.
  • correction filter signal (Vp) supplied to the signal line SL1 can be any signal of positive and negative, here, the case where a signal of positive potential is supplied will be described.
  • the transistor 101 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T1, the transistor 101 is turned on. The potential of the other of the electrodes becomes low.
  • the operation is a reset operation for performing a later capacitive coupling operation. Before time T1, the light emitting operation of the light emitting element 104 in the previous frame is performed, but the potential of the node NM1 is changed by the reset operation and the current flowing to the light emitting element 104 is changed. It is preferable that the light emission of the light emitting element 104 be stopped.
  • the transistor 101 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is low at time T11, the transistor 101 is turned on.
  • the potential of the signal line SL2 is added to the potential of the node NM1 by the capacitive coupling of That is, the node NM1 has a potential (Vs + Vp) obtained by adding the correction filter signal (Vp) to the image signal (Vs).
  • the above is the correction operation of the image signal (Vs) and the operation of causing the light emitting element 104 to emit light.
  • the write operation of the correction filter signal (Vp) described above and the input operation of the image signal (Vs) may be performed continuously, after writing the correction filter signal (Vp) to all the pixels.
  • the input operation of the image signal (Vs) can also be performed.
  • FIG. 13 is a circuit diagram showing a configuration example of the pixel 26 different from FIG.
  • a pixel 26 configured as shown in FIG. 13 includes a transistor 121, a transistor 122, a transistor 123, a capacitor 124, a capacitor 125, and a liquid crystal element 126.
  • One of the source and the drain of the transistor 121 is electrically connected to one electrode of the capacitor 124.
  • the other electrode of the capacitor 124 is electrically connected to one of the source and the drain of the transistor 122.
  • One of the source or the drain of the transistor 122 is electrically connected to one of the source or the drain of the transistor 123.
  • the other of the source and the drain of the transistor 123 is electrically connected to one electrode of the capacitor 125.
  • One electrode of the capacitor 125 is electrically connected to one electrode of the liquid crystal element 126.
  • a wiring to which the other electrode of the capacitor 124, one of the source or the drain of the transistor 122, and one of the source or the drain of the transistor 123 is connected is a node NM2.
  • a wiring to which the other of the source and the drain of the transistor 123, one of the electrodes of the capacitor 125, and one of the electrodes of the liquid crystal element 126 are connected is a node NA2.
  • the gate of the transistor 121 is electrically connected to the scan line GL2.
  • the gate of the transistor 122 is electrically connected to the scan line GL1.
  • the gate of the transistor 123 is electrically connected to the scan line GL3.
  • the other of the source and the drain of the transistor 121 is electrically connected to the signal line SL2.
  • the other of the source and the drain of the transistor 122 is electrically connected to the signal line SL1.
  • the other electrode of the capacitor 125 is electrically connected to the common wiring 132.
  • the other electrode of the liquid crystal element 126 is electrically connected to the common wiring 133. Note that any potential can be supplied to the common wiring 132 and the common wiring 133.
  • the common wiring 132 and the common wiring 133 may be electrically connected.
  • the transistor 122 and the capacitor 124 form a memory circuit MEM.
  • the node NM2 is a memory node, and the transistor 122 is turned on and the transistor 123 is turned off, whereby the signal supplied to the signal line SL1 can be written to the node NM2.
  • the potential of the node NM2 can be held for a long time.
  • an OS transistor can be used for the transistor.
  • an OS transistor may be applied to another transistor included in the pixel.
  • a Si transistor may be applied to a transistor included in a pixel.
  • both an OS transistor and a Si transistor may be used.
  • a silicon substrate can be used, and a silicon transistor and an OS transistor can be formed to have an overlapping region. Therefore, the pixel density can be improved even if the number of transistors is relatively large.
  • the signal written to the node NM2 is capacitively coupled to the image signal supplied from the signal line SL2, and can be output to the node NA2.
  • the transistor 121 has a function of selecting a pixel and supplying an image signal.
  • the transistor 123 has a function as a switch which controls the operation of the liquid crystal element 126.
  • the liquid crystal element 126 may operate before the image signal is written. Therefore, it is preferable that the transistor 123 be provided and the liquid crystal element 126 be operated after the potential of the node NM2 is determined and the transistor 123 is turned on.
  • the correction filter signal corresponding to the correction filter FIL created by the processing unit 40B is stored in the node NM2, the correction filter signal can be added to the image signal. Thereby, the image signal can be corrected.
  • the correction filter signal since the correction filter signal may be attenuated by an element on the transmission path, it is preferable to generate in consideration of the attenuation.
  • the operation of the liquid crystal element 126 can be reset by setting the potential of the signal line SL1 to a reset potential (for example, a reference potential such as 0 V).
  • the transistor 121 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T2, the transistor 121 is turned on. The potential of the other of the electrodes becomes low.
  • the operation is a reset operation for performing a later capacitive coupling operation.
  • the transistor 122 When the potential of the scanning line GL1 is high, the potential of the scanning line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scanning line GL3 is low at time T3, the transistor 122 is turned on and the signal line SL1 Potential (correction filter signal (Vp)) is written to the node NM2.
  • the potential of the signal line SL1 is fixed to a desired value (corrected filter signal (Vp)) from time T2 to time T3.
  • the correction filter signal (Vp) held in the node NM2 is preferably set in consideration of distribution to the node NA2.
  • the transistor 121 is turned on and the capacitor 124 is turned on.
  • the potential of the signal line SL2 is added to the potential of the node NA2 by the capacitive coupling of That is, the node NA2 has a potential (Vs + Vp) 'corresponding to the potential obtained by adding the correction filter signal (Vp) to the image signal (Vs). Note that the potential (Vs + Vp) 'includes the fluctuation of the potential due to the capacitive coupling of the capacitance between the interconnections.
  • the transistor 121 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is low, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is low at time T13, the transistor 121 is turned off. Holds the potential (Vs + Vp) '. Then, a display operation is performed by the liquid crystal element 126 in accordance with the potential.
  • the above is the description of the correction operation of the image signal (Vs) and the display operation of the liquid crystal element 126.
  • the write operation of the correction filter signal (Vp) described above and the input operation of the image signal (Vs) may be performed continuously, after writing the correction filter signal (Vp) to all the pixels.
  • the input operation of the image signal (Vs) can also be performed.
  • the display operation by the liquid crystal element 126 may be performed by supplying an image signal to the signal line SL1 and controlling conduction and non-conduction of the transistor 122 and the transistor 123. At this time, the transistor 121 may be always off.
  • step S01 shown in FIG. 5A and step S11 shown in FIG. 5B that is, an example of a method of creating a correction filter corresponding to one display panel DP will be described with reference to FIG. It demonstrates using the flowchart shown.
  • a first correction filter which is a correction filter corresponding to the display panel DP [1, 1]
  • a second correction filter which is a correction filter corresponding to the display panel DP [2, 1] are shown in FIG. It can be created by the method.
  • the correction filter created by the method shown in FIG. 15 has a function of correcting image data so as to reduce display unevenness of an image displayed on the display panel DP, for example.
  • the brightness of light emitted from the pixels provided in the display panel DP is measured for a plurality of gradation values.
  • the luminance of light is measured using a luminance meter or the like (step S21).
  • the processing unit 40A or the processing unit 40B acquires data of the correspondence between the luminance of the light emitted from the pixel and the gradation value (step S22).
  • FIGS. 16A-1 and 16B-1 are graphs showing the relationship between the luminance of light emitted from a pixel and the gradation value, and the plots shown in FIG. Is the luminance measured in step S21.
  • the solid line shown in FIG. 16 (B-1) represents the brightness of the light emitted from the pixel and the floor, which are calculated in step S22 based on the measurement result shown in FIG. 16 (A-1). There is a correspondence relationship with the price adjustment.
  • the luminance of the light emitted from the pixels may be measured for all the gradation values.
  • the luminance of the light emitted from the pixel may be measured for all of the gradation values 0 to 255.
  • the brightness of light emitted from a pixel may be measured for some gradation values. Even when luminance is measured for some gradation values, it is preferable to measure luminance for white, black, and middle gradation in order to enhance the accuracy of the correspondence data.
  • the luminance of the light emitted from the pixel may be measured for the gradation value 0, the gradation value 127, and the gradation value 255. preferable.
  • the data of the correspondence shown in FIG. 16 (B-1) can be obtained, for example, by regression analysis based on the measurement result shown in FIG. 16 (A-1). For example, it can acquire by curve regression analysis. Alternatively, it can be obtained, for example, using a neural network, such as a fully coupled neural network. Even if the number of measurement points shown in FIG. 16 (A-1) is small, accuracy of the data of the correspondence relationship can be increased by acquiring data of the correspondence relationship shown in FIG. 16 (B-1) using a neural network. it can.
  • FIG. 16A-2 shows measured values when the luminance of light emitted from the pixel is measured for each of red (R), green (G), and blue (B) in step S21.
  • 16 (B-2) is calculated for each of red (R), green (G), and blue (B) based on the measurement results shown in FIG. 16 (A-2) in step S22. It is the correspondence of the luminance of the light emitted from the pixel and the gradation value.
  • high accuracy can be achieved by acquiring the data of the correspondence between the luminance and the gradation value for each color of light emitted from the pixel.
  • a correction filter capable of correction can be created.
  • FIGS. 17A, 17B, and 17C show an example of the position of a pixel for measuring the luminance of the emitted light in step S21.
  • the pixel unit 21 indicates a pixel unit provided in one display panel DP, such as the pixel unit 21A and the pixel unit 21B.
  • the luminance of light emitted from the pixels included in the area 27 shown in FIGS. 17A, 17B, and 17C is measured in step S21.
  • the luminance of light emitted from the pixels may be measured so as to include the central portion of the pixel portion 21 as shown in FIG.
  • measurement may be performed at a plurality of locations of the pixel unit 21, for example, four locations on the upper left, upper right, lower left, and lower right.
  • the entire pixel portion 21 may be measured.
  • the total area of the region 27 is small, the brightness of the light emitted from the pixel can be measured by a simple method.
  • the total area of the region 27 is large, it is possible to create a correction filter capable of highly accurate correction.
  • step S22 an image having a specific gradation value is displayed on the pixel unit 21, and luminance data is acquired by measuring the luminance of light emitted from the pixel using a two-dimensional luminance meter or the like (see FIG. Step S23).
  • luminance data is acquired by measuring the luminance of light emitted from all the pixels provided in the pixel unit 21 using a two-dimensional luminance meter or the like.
  • step S23 luminance data is acquired in order to acquire information on variations in luminance of light emitted from the pixels.
  • a correction filter for correcting the variation in luminance of light emitted from the pixels is processed. It prepares by the department (step S24). For example, if the luminance at a gradation value 127 of a certain pixel that can be read from luminance data is 100 and the correspondence data indicates that the luminance at a gradation value 127 is 120, the luminance of a certain pixel is 1.2 times Create a correction filter to
  • step S22 for example, data of correspondence with luminance is acquired for all gradation values. Therefore, by displaying two or more types of images in step S23 and acquiring luminance data for each image, it is possible to create a correction filter capable of higher accuracy correction. For example, when the gradation value that can be expressed by a pixel is 0 to 255, in step S23, an image in which the gradation of all pixels is 0, an image in which the gradation of all pixels is 127, and all pixels Luminance data can be acquired for each of the images whose gray level is 255. In order to simplify the measurement of the brightness of light in step S23, the number of types of brightness data acquired in step S23 may be smaller than the number of gradation values obtained by measuring the brightness of light in step S21. preferable.
  • the image data is input to the processing unit 40A or 40B, and the input image data is corrected using the correction filter created in step S24 (step S25).
  • the image data input to the processing unit 40A or the processing unit 40B be, for example, image data corresponding to an image of a specific gradation value.
  • Step S25 an image corresponding to the image data corrected in step S25 is displayed on the pixel unit 21, and the luminance of light emitted from the pixel is measured using a two-dimensional luminance meter or the like as in step S23.
  • Step S26 the luminance corresponding to the image after correction measured in step S26 is compared with the luminance calculated from the data of the correspondence obtained in step S22 for each pixel. For example, when the difference between the luminance corresponding to the image after correction and the luminance calculated from the data of the correspondence obtained in step S22 is less than a predetermined value, it is assumed that the correction accuracy is equal to or higher than the specified value. Finish creating the correction filter.
  • Step S24 and S27 are performed again to create a correction filter again (step S27).
  • the above is an example of a method of creating the correction filter used in the display device 10A and the display device 10B. Note that steps S26 and S27 may be omitted.
  • step S23 When two or more types of images are displayed in step S23, the brightness of light emitted from the pixels is measured in step S26, and the correction accuracy of each image is determined in step S27. preferable.
  • step S01 shown in FIG. 5A and step S11 shown in FIG. 5B that is, an example of a method of creating a correction filter corresponding to one display panel DP.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • Second Embodiment a structural example of a display device using a liquid crystal element and a structural example of a display device using an EL element will be described. In the present embodiment, descriptions of the elements, operations, and functions of the display device described in Embodiment 1 will be omitted.
  • FIGS. 18A and 18B are cross-sectional views illustrating configuration examples of a display device of one embodiment of the present invention.
  • the display devices illustrated in FIGS. 18A and 18B each include an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019.
  • the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.
  • the electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed of the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.
  • the display portion 215 and the scan line driver circuit 221 provided over the first substrate 4001 have a plurality of transistors, and are included in the display portion 215 in FIGS. 18A and 18B.
  • the transistor 4010 and the transistor 4011 included in the scan line driver circuit 221 are illustrated.
  • bottom-gate transistors are illustrated as the transistors 4010 and 4011 in FIGS. 18A and 18B, top-gate transistors may be used.
  • the insulating layer 4112 is provided over the transistor 4010 and the transistor 4011.
  • the partition 4510 is formed over the insulating layer 4112.
  • the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102.
  • the transistor 4010 and the transistor 4011 each have an electrode 4017 formed over the insulating layer 4111.
  • the electrode 4017 can function as a back gate electrode.
  • the display devices illustrated in FIGS. 18A and 18B each include a capacitor 4020.
  • the capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010, and an electrode formed in the same step as the source electrode and the drain electrode. Each electrode has a region overlapping with the insulating layer 4103 interposed therebetween.
  • the capacitance of a capacitor provided in a pixel portion of a display device is set so as to hold charge for a predetermined period, in consideration of leakage current or the like of a transistor provided in the pixel portion.
  • the capacitance of the capacitor may be set in consideration of the off current of the transistor and the like.
  • FIG. 18A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element.
  • a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008.
  • an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008.
  • the second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other through the liquid crystal layer 4008.
  • the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control a distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. ing. A spherical spacer may be used.
  • an optical member such as a black matrix (light shielding layer), a colored layer (color filter), a polarization member, a retardation member, an anti-reflection member, etc.
  • an optical member such as a black matrix (light shielding layer), a colored layer (color filter), a polarization member, a retardation member, an anti-reflection member, etc.
  • circularly polarized light by a polarizing substrate and a retardation substrate may be used.
  • a backlight, a sidelight, or the like may be used as a light source.
  • a light shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.
  • the material that can be used as the light shielding layer examples include carbon black, titanium black, metals, metal oxides, and composite oxides containing a solid solution of a plurality of metal oxides.
  • the light shielding layer may be a film containing a resin material or may be a thin film of an inorganic material such as a metal.
  • a stacked film of films including a material of a colored layer can also be used for the light shielding layer.
  • a layered structure of a film containing a material used for a colored layer transmitting light of a certain color and a film containing a material used for a colored layer transmitting light of another color can be used. It is preferable to use a common material for the colored layer and the light shielding layer, as it is possible to share the device and simplify the process.
  • Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like.
  • the light shielding layer and the colored layer may be formed in the same manner as the formation method of each layer described above. For example, it may be performed by an inkjet method or the like.
  • the display devices illustrated in FIGS. 18A and 18B each include an insulating layer 4111 and an insulating layer 4104.
  • As the insulating layer 4111 and the insulating layer 4104 an insulating layer which hardly transmits an impurity element is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.
  • a light-emitting element (EL element) using electroluminescence can be applied as a display element included in a display device.
  • the EL element has a layer containing a light-emitting compound (also referred to as “EL layer”) between a pair of electrodes.
  • a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light emitting compound contained in the EL layer emits light.
  • EL elements are distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and in general, the former is called an organic EL element and the latter is called an inorganic EL element.
  • the organic EL element In the organic EL element, electrons are injected from one electrode and holes are injected from the other electrode to the EL layer by applying a voltage. Then, the carriers (electrons and holes) recombine to form an excited state in the light emitting organic compound, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light emitting element is referred to as a current excitation light emitting element.
  • the EL layer may be formed of a substance having a high hole injecting property, a substance having a high hole transporting property, a hole blocking material, a substance having a high electron transporting property, a substance having a high electron injecting property, or a bipolar other than a light emitting compound. It may have a polar substance (a substance having a high electron transporting property and a hole transporting property) or the like.
  • the EL layer can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
  • Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film-type inorganic EL element according to the element configuration.
  • the dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission utilizing a donor level and an acceptor level.
  • the thin film type inorganic EL element has a structure in which the light emitting layer is sandwiched by dielectric layers and further sandwiched by electrodes, and the light emission mechanism is localized light emission utilizing inner shell electron transition of metal ions.
  • an organic EL element is described as a light emitting element.
  • At least one of the pair of electrodes may be transparent. Then, a transistor and a light emitting element are formed over the substrate, and top emission (top emission) structure in which light emission is extracted from the surface opposite to the substrate, or bottom emission (bottom emission) structure in which light emission is extracted from the surface of the substrate.
  • top emission (top emission) structure in which light emission is extracted from the surface opposite to the substrate
  • bottom emission (bottom emission) structure in which light emission is extracted from the surface of the substrate
  • FIG. 18B illustrates an example of a light-emitting display device (also referred to as “EL display device”) using a light-emitting element as a display element.
  • a light emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the display portion 215.
  • the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031, but is not limited to this structure.
  • the structure of the light emitting element 4513 can be changed as appropriate in accordance with the direction of light extracted from the light emitting element 4513 or the like.
  • the partition 4510 is formed using an organic insulating material or an inorganic insulating material.
  • the light emitting layer 4511 may be either a single layer or a plurality of layers stacked.
  • the emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material of the light-emitting layer 4511.
  • a method of realizing color display there are a method of combining a light emitting element 4513 of white light emitting color and a coloring layer, and a method of providing a light emitting element 4513 of different light emitting color for each pixel.
  • the former method is more productive than the latter method.
  • the productivity is lower than the former method.
  • luminescent color having higher color purity can be obtained than in the former method.
  • the color purity can be further enhanced by providing the light emitting element 4513 with a microcavity structure.
  • the light emitting layer 4511 may have an inorganic compound such as a quantum dot.
  • a quantum dot for the light-emitting layer, it can also function as a light-emitting material.
  • a protective layer may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting element 4513.
  • the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed.
  • a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed.
  • a protective film such as a laminated film or an ultraviolet curable resin film
  • a cover material which has high airtightness and low degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin , PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) or the like can be used.
  • the filler 4514 may contain a desiccant.
  • sealant 4005 a glass material such as a glass frit, a cured resin such as a two-component mixed resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used.
  • the sealant 4005 may contain a desiccant.
  • an optical film such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), a color filter, etc. on the emission surface of the light emitting element You may provide suitably.
  • an antireflective film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare processing can be performed to diffuse reflected light and reduce reflection due to the unevenness of the surface.
  • light with high color purity can be extracted by forming the light-emitting element with a microcavity structure.
  • reflection can be reduced, and the visibility of a display image can be enhanced.
  • first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, and the like) which apply voltage to the display element, the direction of light to be extracted, a location where the electrode layer is provided, Translucency and reflectivity may be selected depending on the pattern structure of the electrode layer.
  • the first electrode layer 4030 and the second electrode layer 403 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium containing titanium oxide
  • a light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.
  • the first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta) Metals such as chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or It can be formed using one or more of metal nitrides.
  • the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer).
  • a conductive high molecule also referred to as a conductive polymer.
  • a so-called ⁇ electron conjugated conductive high molecule can be used.
  • polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole and thiophene or a derivative thereof can be given.
  • a protective circuit for protecting the driver circuit is preferably provided.
  • the protection circuit is preferably configured using a non-linear element.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • the display device of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom gate transistor and a top gate transistor. Therefore, according to the existing manufacturing line, the material of the semiconductor layer to be used and the transistor structure can be easily replaced.
  • FIG. 19A1 is a cross-sectional view in the channel length direction of a channel protective transistor 810 which is a kind of bottom gate transistor.
  • the transistor 810 is formed over a substrate 771.
  • the transistor 810 includes an electrode 746 over the substrate 771 with the insulating layer 772 interposed therebetween.
  • the semiconductor layer 742 is provided over the electrode 746 with the insulating layer 726 interposed therebetween.
  • the electrode 746 can function as a gate electrode.
  • the insulating layer 726 can function as a gate insulating layer.
  • the insulating layer 741 is provided over the channel formation region of the semiconductor layer 742.
  • an electrode 744 a and an electrode 744 b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742.
  • the electrode 744a can function as one of a source electrode and a drain electrode.
  • the electrode 744 b can function as the other of the source electrode and the drain electrode.
  • a portion of the electrode 744 a and a portion of the electrode 744 b are formed over the insulating layer 741.
  • the insulating layer 741 can function as a channel protective layer. By providing the insulating layer 741 over the channel formation region, exposure of the semiconductor layer 742 which is generated at the time of formation of the electrode 744a and the electrode 744b can be prevented. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrode 744a and the electrode 744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
  • the transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and the insulating layer 729 over the insulating layer 728.
  • a part of the semiconductor layer 742 can be deprived of oxygen and oxygen deficiency can be generated in at least a portion of the electrode 744 a and the electrode 744 b in contact with the semiconductor layer 742.
  • the region of the semiconductor layer 742 in which oxygen vacancies occur has an increased carrier concentration, and the region becomes n-type to become an n-type region (n + layer). Thus, the region can function as a source region or a drain region.
  • tungsten, titanium, or the like can be given as an example of a material that can deprive the semiconductor layer 742 of oxygen and cause oxygen vacancies.
  • the contact resistance between the electrode 744 a and the electrode 744 b and the semiconductor layer 742 can be reduced. Accordingly, electrical characteristics of the transistor, such as field effect mobility and threshold voltage, can be improved.
  • a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744 a and between the semiconductor layer 742 and the electrode 744 b.
  • a layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
  • the insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 729 can be omitted as needed.
  • a transistor 811 illustrated in FIG. 19A2 is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
  • the electrode 723 can be formed by the same material and method as the electrode 746.
  • the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode are disposed so as to sandwich the channel formation region of the semiconductor layer.
  • the back gate electrode can function similarly to the gate electrode.
  • the potential of the back gate electrode may be the same as the potential of the gate electrode, or may be the ground potential (GND potential) or any potential.
  • the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently without interlocking with the gate electrode.
  • the electrode 746 and the electrode 723 can both function as a gate electrode.
  • the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer.
  • the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.
  • the other is referred to as a “back gate electrode”.
  • the electrode 746 when the electrode 723 is referred to as a “gate electrode”, the electrode 746 is referred to as a “back gate electrode”.
  • the transistor 811 can be considered as a kind of top gate transistor.
  • one of the electrode 746 and the electrode 723 may be referred to as “first gate electrode”, and the other may be referred to as “second gate electrode”.
  • the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction.
  • the amount of carrier movement increases.
  • the on current of the transistor 811 is increased, and the field effect mobility is increased.
  • the transistor 811 is a transistor having a large on current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the on current required. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Thus, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
  • the gate electrode and the back gate electrode are formed of a conductive layer, they have a function to prevent an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (in particular, an electric field shielding function against static electricity or the like). .
  • the electric field shielding function can be enhanced by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.
  • the back gate electrode is formed using a light-shielding conductive film
  • light can be prevented from entering the semiconductor layer from the back gate electrode side. Accordingly, light deterioration of the semiconductor layer can be prevented, and deterioration of the electrical characteristics such as a shift in threshold voltage of the transistor can be prevented.
  • a highly reliable transistor can be realized.
  • a highly reliable semiconductor device can be realized.
  • FIG. 19B1 is a cross-sectional view in the channel length direction of a channel protective transistor 820 having a different structure from that in FIG. 19A1.
  • the transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 741 covers an end portion of the semiconductor layer 742.
  • the semiconductor layer 742 and the electrode 744 a are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 741 which has a region overlapping with the semiconductor layer 742.
  • the semiconductor layer 742 and the electrode 744 b are electrically connected to each other in another opening which is formed by selectively removing part of the insulating layer 741 which has a region overlapping with the semiconductor layer 742.
  • the region of the insulating layer 741 overlapping with the channel formation region can function as a channel protective layer.
  • the transistor 821 illustrated in FIG. 19B2 is different from the transistor 820 in that the electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
  • the insulating layer 741 can prevent the semiconductor layer 742 from being exposed at the time of formation of the electrodes 744a and 744b. Thus, thinning of the semiconductor layer 742 can be prevented at the time of formation of the electrode 744a and the electrode 744b.
  • the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer than those in the transistors 810 and 811.
  • parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced.
  • parasitic capacitance generated between the electrode 744 b and the electrode 746 can be reduced.
  • a transistor with favorable electrical characteristics can be realized.
  • FIG. 19C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 825 which is one of bottom-gate transistors.
  • the transistor 825 forms the electrode 744a and the electrode 744b without providing the insulating layer 741. Therefore, part of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be improved.
  • a transistor 826 illustrated in FIG. 19C2 is different from the transistor 825 in that the electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
  • 20A1 to 20C2 are cross-sectional views in the channel width direction of the transistor 810, the transistor 811, the transistor 820, the transistor 821, the transistor 825, and the transistor 826, respectively.
  • the gate electrode and the back gate electrode are connected, and the gate electrode and the back gate electrode have the same potential.
  • the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.
  • the length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 742, and the entire channel width direction of the semiconductor layer 742 is the insulating layer 726, the insulating layer 741, the insulating layer 728 and the insulating layer 729 are interposed between the gate electrode and the back gate electrode.
  • the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.
  • a device structure of a transistor that electrically surrounds a semiconductor layer 742 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode It can be called structure.
  • an electric field for inducing a channel can be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved. It is possible to obtain high on-current characteristics. In addition, since the on current can be increased, the transistor can be miniaturized. In addition, with the S-channel structure, mechanical strength of the transistor can be increased.
  • a transistor 842 illustrated in FIG. 21A1 is one of top-gate transistors.
  • the transistor 842 forms the electrode 744a and the electrode 744b after forming the insulating layer 729.
  • the electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in an opening formed in the insulating layer 728 and the insulating layer 729.
  • a portion of the insulating layer 726 which does not overlap with the electrode 746 is removed, and an impurity is introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask.
  • the impurity region can be formed in a self alignment manner (self alignment).
  • the transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746.
  • the impurity concentration of the region into which the impurity is introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than that of the region into which the impurity is introduced without through the insulating layer 726.
  • a lightly doped drain (LDD) region is formed in a region which does not overlap with the electrode 746.
  • a transistor 843 illustrated in FIG. 21A2 is different from the transistor 842 in that the electrode 723 is provided.
  • the transistor 843 has an electrode 723 formed over the substrate 771.
  • the electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween.
  • the electrode 723 can function as a back gate electrode.
  • the transistor 844 illustrated in FIG. 21B1 and the transistor 845 illustrated in FIG. 21B2 all the insulating layer 726 in a region which does not overlap with the electrode 746 may be removed.
  • the insulating layer 726 may be left.
  • transistors 842 to 847 after forming the electrode 746, an impurity is introduced into the semiconductor layer 742 using the electrode 746 as a mask, so that the impurity region can be formed in the semiconductor layer 742 in a self-aligned manner.
  • a transistor with favorable electrical characteristics can be realized.
  • a semiconductor device with a high degree of integration can be realized.
  • 22A1 to 22C2 are cross-sectional views in the channel width direction of the transistors 842 to 847, respectively.
  • the transistor 843, the transistor 845, and the transistor 847 each have the S-channel structure described above. However, without limitation thereto, the transistor 843, the transistor 845, and the transistor 847 may not have an S-channel structure.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • Embodiment 4 In this embodiment, a detailed configuration example of the OS transistor will be described.
  • the semiconductor layer included in the OS transistor is, for example, an In-M-Zn-based oxide containing indium, zinc and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium).
  • the film can be represented by
  • the oxide semiconductor forming the semiconductor layer is an In-M-Zn-based oxide
  • the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is In ⁇ M, Zn It is preferable to satisfy ⁇ M.
  • the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.
  • an oxide semiconductor with low carrier density is used.
  • the semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, more preferably 1 ⁇ 10 11 / cm 3 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use an oxide semiconductor of 1 ⁇ 10 -9 / cm 3 or more carrier density.
  • Such an oxide semiconductor is referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor.
  • the oxide semiconductor has low defect state density and can be said to be an oxide semiconductor having stable characteristics.
  • composition is not limited to those described above, and a composition having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of the required transistor.
  • semiconductor characteristics and electrical characteristics field effect mobility, threshold voltage, and the like
  • the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less make it
  • the nitrogen concentration (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the semiconductor layer may have, for example, a non-single crystal structure.
  • the non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a crystal aligned in the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • the amorphous structure has the highest density of defect states
  • CAAC-OS has the lowest density of defect states.
  • the oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component.
  • the oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.
  • the semiconductor layer may be a mixed film having two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure.
  • the mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.
  • CAC Cloud-Aligned Composite
  • the CAC-OS is, for example, a configuration of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof.
  • an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof.
  • the oxide semiconductor one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less
  • the state in which they are mixed is also called a mosaic or patch.
  • the oxide semiconductor preferably contains at least indium.
  • One or more selected from may be included.
  • CAC-OS in the In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
  • InO indium oxide
  • X1 X1 is a real number greater than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers greater than 0
  • GaO X3 X3 is a real number greater than 0
  • Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 a real number greater than 0) to.
  • the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud-like It is also referred to.).
  • the CAC-OS is a complex oxide semiconductor having a structure in which a region in which GaO X3 is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are mixed.
  • the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 + x0) Ga ( 1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.
  • CAC-OS relates to the material configuration of an oxide semiconductor.
  • the CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components.
  • region observed in shape says the structure currently disperse
  • CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
  • the CAC-OS is partially observed in the form of nanoparticles having the metal element as a main component, and partially having In as a main component.
  • region observed in particle form says the structure currently each disperse
  • the CAC-OS can be formed by, for example, a sputtering method under conditions in which the substrate is not intentionally heated.
  • a sputtering method one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas.
  • an inert gas typically, argon
  • oxygen gas typically, oxygen gas
  • a nitrogen gas may be used as a deposition gas.
  • the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible.
  • the flow rate ratio of the oxygen gas is 0% to 30%, preferably 0% to 10%. .
  • CAC-OS has a feature that a clear peak is not observed when it is measured using a ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods.
  • XRD X-ray diffraction
  • the CAC-OS has a ring-like high luminance region and a plurality of ring regions. A bright spot is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.
  • GaO X3 is a main component by EDX mapping acquired using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) It can be confirmed that the region and the region containing In X 2 Zn Y 2 O Z 2 or In O X 1 as the main component have a structure in which the regions are localized and mixed.
  • EDX Energy Dispersive X-ray spectroscopy
  • the CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase separated into a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.
  • the region whose main component is In X2 Zn Y2 O Z2 or InO X1 is a region whose conductivity is higher than the region whose main component is GaO X3 or the like. That is, when carriers flow in a region mainly containing In X2 Zn Y2 O Z2 or InO X1 , conductivity as an oxide semiconductor is exhibited. Accordingly, In X2 Zn Y2 O Z2, or InO X1 is the main component region, that distributed in the cloud-like in the oxide semiconductor, a high field-effect mobility (mu) can be realized.
  • the region whose main component is GaO X3 or the like is a region whose insulating property is higher than the region whose main component is In X2 Zn Y2 O Z2 or InO X1 . That is, by distributing a region containing GaO X3 or the like as a main component in the oxide semiconductor, leakage current can be suppressed and favorable switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property due to GaO X3 and the like and the conductivity due to In X 2 Zn Y 2 O Z 2 or InO X 1 are high by acting complementarily.
  • the on current (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is suitable as a constituent material of various semiconductor devices.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • the electronic device of this embodiment includes the display device of one embodiment of the present invention.
  • the display quality of the image displayed on the display unit of the electronic device can be improved.
  • An image having a resolution of, for example, full high definition, 2K, 4K, 8K, 16K, or more can be displayed on the display portion of the electronic device of this embodiment.
  • the screen size of the display portion can be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches or more diagonally, 60 inches diagonally or more, or 70 inches diagonally or more.
  • Examples of the electronic devices include relatively large screens of television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc.
  • digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like can be given.
  • the electronic device of one embodiment of the present invention may have an antenna.
  • the display portion can display an image, information, and the like.
  • the antenna may be used for contactless power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, inclination, vibration, smell or infrared light.
  • the electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying dates, time, etc., a function of executing various software (programs), wireless A communication function, a function of reading a program or data recorded in a recording medium, and the like can be provided.
  • FIG. 23A shows an example of a television set.
  • a display portion 7000 is incorporated in a housing 7101.
  • a structure in which the housing 7101 is supported by the stand 7103 is shown.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the television set 7100 illustrated in FIG. 23A can be operated by an operation switch of the housing 7101 or a separate remote controller 7111.
  • the display portion 7000 may be provided with a touch sensor or may be operated by touching the display portion 7000 with a finger or the like.
  • the remote controller 7111 may have a display unit for displaying information output from the remote controller 7111. Channels and volume can be controlled with an operation key or a touch panel of the remote controller 7111, and an image displayed on the display portion 7000 can be manipulated.
  • the television set 7100 is provided with a receiver, a modem, and the like.
  • the receiver can receive a general television broadcast.
  • a modem by connecting to a wired or wireless communication network via a modem, one-way (sender to receiver) or two-way (sender and receiver, or between receivers, etc.) information communication can be performed. It is also possible.
  • FIG. 23B shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • FIGS. 23C and 23D show an example of digital signage.
  • a digital signage 7300 illustrated in FIG. 23C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.
  • FIG. 23D shows a digital signage 7400 attached to a cylindrical column 7401.
  • the digital signage 7400 has a display portion 7000 provided along the curved surface of the column 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the display unit 7000 As the display unit 7000 is wider, the amount of information that can be provided at one time can be increased. Also, the wider the display portion 7000, the easier it is for a person to see, and for example, the advertising effect of the advertisement can be enhanced.
  • a touch panel By applying a touch panel to the display portion 7000, not only a still image or a moving image can be displayed on the display portion 7000, but also the user can operate intuitively, which is preferable. Moreover, when it uses for the application for providing information, such as route information or traffic information, usability can be improved by intuitive operation.
  • the digital signage 7300 or the digital signage 7400 can cooperate with the information terminal 7311 or information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred.
  • information of an advertisement displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display of the display portion 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 execute a game in which the screen of the information terminal 7311 or the information terminal 7411 is an operation means (controller). In this way, an unspecified number of users can simultaneously participate in and enjoy the game.
  • the display device of one embodiment of the present invention can be incorporated along the inner or outer wall of a house or building, or along the curved surface of the interior or exterior of a vehicle.
  • This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
  • FIG. 24 is a diagram for explaining a display device displaying an image in the present embodiment.
  • the display panel (display panel DP [1, 1], display panel DP [2, 1], display panel DP [1, 2], and display panel DP [2, 2] are arranged in two rows and two columns. The image was displayed on the display apparatus which arranged].
  • the display panel is provided with pixels of 720 rows and 1280 columns.
  • an area provided with pixels for 320 columns from the boundary between the display panel DP [1,1] and the display panel DP [1,2] is a boundary portion. It is assumed that 229A. Further, in the display panel DP [2, 1], an area provided with pixels for 320 columns from the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is a boundary portion 229B. I assume. Further, in the display panel DP [1, 2], an area provided with pixels for 320 columns from the boundary between the display panel DP [1, 1] and the display panel DP [1, 2] is a boundary portion 229C. I assume. Further, in the display panel DP [2, 2], an area provided with pixels for 320 columns from the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is a boundary portion 229D. I assume.
  • a correction filter is created for each display panel by the method shown in FIG.
  • the pixels provided in the display panel can express gradation values 0 to 255
  • the images displayed in step S23 and step S26 are images in which the gradation values of all the pixels are 127.
  • the average value D AB of filter values corresponding to the pixels provided in the boundary portion 229A and the boundary portion 229B, and the average value D CD of filter values corresponding to the pixels provided in the boundary portion 229C and the boundary 229D was calculated. Thereafter, the filter value as multiplied D AB / D CD corresponding to the pixel provided in the display panel DP [1, 2] and the display panel DP [2, 2], by modifying the correction filter, a new I created a correction filter.
  • FIG. 25A shows a display result when an image is displayed without correcting the filter created by the method shown in FIG.
  • FIG. 25B shows a display result when the filter created by the method shown in FIG. 15 is corrected by the above method, a new correction filter is created, and an image is displayed.
  • an image corrected by the correction filter created by the method shown in FIG. 15 is displayed on one display panel.
  • the pixels provided in the display panel can express gradation values 0 to 255, and the image to be displayed in step S23 and the image subjected to correction have a gradation value of 127 for all pixels.
  • the image was Moreover, in step S23 and step S26, the luminance of the light emitted from the pixel was measured using a two-dimensional luminance meter.
  • FIG. 26A shows luminance data of the display panel on which the image before correction is displayed, which is obtained by the two-dimensional luminance meter in step S23.
  • FIG. 26B shows luminance data of the display panel on which the image after correction is displayed, which is acquired by the two-dimensional luminance meter after the correction filter is created.
  • the luminance at the central portion of the display panel was higher than the luminance at the peripheral portion of the display panel.
  • the display panel is displaying an image after correction, as shown in FIG. 26B, the luminance is uniformed in the entire display panel before the correction.

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Abstract

Provided is a display device having high display quality. The display device includes: a first pixel section in which first pixels are arranged in a matrix; and a second pixel section in which second pixels are arranged in a matrix. First, a first correction filter including a function of correcting an image displayed by the first pixel section and a second correction filter including a function of correcting an image displayed by the second pixel section are created. Next, a filter value of the first correction filter and a correction value of the second correction filter are compared. Thereafter, the filter value of the first correction filter is corrected on the basis of the comparison results.

Description

表示装置及びその動作方法Display device and operation method thereof
本発明の一態様は、表示装置及びその動作方法に関する。 One embodiment of the present invention relates to a display device and an operation method thereof.
なお、本発明の一態様は、上記の技術分野に限定されない。本発明の一態様の技術分野としては、半導体装置、表示装置、発光装置、表示システム、電子機器、照明装置、入力装置（例えば、タッチセンサ等）、入出力装置（例えば、タッチパネル等）、それらの駆動方法、又はそれらの製造方法を一例として挙げることができる。 Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the present invention includes a semiconductor device, a display device, a light emitting device, a display system, an electronic device, a lighting device, an input device (eg, a touch sensor or the like), an input / output device (eg, a touch panel or the like), The driving method of or the manufacturing method of them can be mentioned as an example.
なお、本明細書等において、半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。表示装置（液晶表示装置、発光表示装置等）、投影装置、照明装置、電気光学装置、蓄電装置、記憶装置、半導体回路、撮像装置、及び電子機器等は、半導体装置といえる場合がある。もしくは、これらは半導体装置を有するといえる場合がある。 Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may be referred to as a semiconductor device. Alternatively, it may be said that these have a semiconductor device.
近年、解像度の高い表示装置が求められている。例えば、フルハイビジョン（画素数１９２０×１０８０）、４Ｋ（画素数３８４０×２１６０もしくは４０９６×２１６０等）、さらには８Ｋ（画素数７６８０×４３２０もしくは８１９２×４３２０等）といった画素数の多い表示装置が盛んに開発されている。 In recent years, display devices with high resolution have been required. For example, a display device with a large number of pixels such as full high vision (the number of pixels 1920 × 1080), 4K (the number of pixels 3840 × 2160 or 4096 × 2160), and further 8K (the number of pixels 7680 × 4320 or 8192 × 4320) is thriving Has been developed.
また、表示装置の大型化が求められている。例えば、家庭用のテレビジョン装置では、画面サイズが対角５０インチを超えるものが主流となっている。画面のサイズが大きいほど、一度に表示可能な情報量を多くできるため、デジタルサイネージ等では更なる大画面化が求められている。 Moreover, the enlargement of a display apparatus is calculated | required. For example, in home-use television devices, those having a screen size exceeding 50 inches diagonal are in the mainstream. As the size of the screen is larger, the amount of information that can be displayed at one time can be increased, and thus digital signage and the like are required to further increase the screen size.
表示装置としては、液晶表示装置や発光表示装置に代表されるフラットパネルディスプレイが広く用いられている。これらの表示装置を構成するトランジスタの半導体材料には主にシリコンが用いられているが、近年、金属酸化物を用いたトランジスタを表示装置の画素に用いる技術も開発されている。 As a display device, flat panel displays represented by liquid crystal display devices and light emitting display devices are widely used. Although silicon is mainly used as a semiconductor material of the transistor which comprises these display apparatuses, the technique which uses the transistor which used the metal oxide for the pixel of a display apparatus is also developed in recent years.
特許文献１には、トランジスタの半導体材料に非晶質シリコンを用いる技術が開示されている。特許文献２及び特許文献３には、トランジスタの半導体材料に金属酸化物を用いる技術が開示されている。特許文献４には、複数の表示パネルを並べることで、大型の表示装置を作製する技術が開示されている。 Patent Document 1 discloses a technique of using amorphous silicon as a semiconductor material of a transistor. Patent Document 2 and Patent Document 3 disclose a technique of using a metal oxide as a semiconductor material of a transistor. Patent Document 4 discloses a technique for manufacturing a large display device by arranging a plurality of display panels.
特開２００１−５３２８３号公報JP, 2001-53283, A 特開２００７−１２３８６１号公報Unexamined-Japanese-Patent No. 2007-123861 特開２００７−９６０５５号公報JP 2007-96055 A 特開２０１５−１８０９２４号公報JP, 2015-180924, A
複数の表示パネルを並べることで大きな表示領域を実現した表示装置の場合、各表示パネルの特性のばらつきに起因して、表示パネル間の境界が視認されやすくなってしまう。 In the case of a display device in which a large display area is realized by arranging a plurality of display panels, the boundaries between the display panels are easily visible due to the variation in the characteristics of the display panels.
また、表示パネルに設けられた画素数が多くなると、当該表示パネルが有するトランジスタ及び表示素子の数が増える。このため、トランジスタの特性のばらつき及び表示素子の特性のばらつきに起因する、表示パネルに表示される画像の表示ムラが顕著になってしまう。 In addition, when the number of pixels provided in a display panel is increased, the number of transistors and display elements included in the display panel is increased. Therefore, display unevenness of an image displayed on the display panel due to the dispersion of the characteristics of the transistors and the dispersion of the characteristics of the display elements becomes remarkable.
本発明の一態様は、表示品位の高い表示装置を提供することを課題の一つとする。本発明の一態様は、表示ムラが軽減された表示装置を提供することを課題の一つとする。本発明の一態様は、解像度の高い表示装置を提供することを課題の一つとする。本発明の一態様は、大型の表示領域を有する表示装置を提供することを課題の一つとする。本発明の一態様は、高いフレーム周波数で動作可能な表示装置を提供することを課題の一つとする。本発明の一態様は、消費電力が低い表示装置を提供することを課題の一つとする。本発明の一態様は、薄型の表示装置を提供することを課題の一つとする。本発明の一態様は、可撓性を有する表示装置を提供することを課題の一つとする。本発明の一態様は、視野角が広い表示装置を提供することを課題の一つとする。本発明の一態様は、小型の製造装置で作製できる表示装置を提供することを課題の一つとする。本発明の一態様は、低価格な表示装置を提供することを課題の一つとする。本発明の一態様は、信頼性の高い表示装置を提供することを課題の一つとする。本発明の一態様は、新規な表示装置を提供することを課題の一つとする。本発明の一態様は、新規な半導体装置等を提供することを課題の一つとする。 An object of one embodiment of the present invention is to provide a display device with high display quality. An object of one embodiment of the present invention is to provide a display device with reduced display unevenness. An object of one embodiment of the present invention is to provide a display device with high resolution. An object of one embodiment of the present invention is to provide a display device having a large display area. An object of one embodiment of the present invention is to provide a display device operable at a high frame frequency. An object of one embodiment of the present invention is to provide a display device with low power consumption. An object of one embodiment of the present invention is to provide a thin display device. An object of one embodiment of the present invention is to provide a flexible display device. An object of one embodiment of the present invention is to provide a display device with a wide viewing angle. An object of one embodiment of the present invention is to provide a display device that can be manufactured with a small manufacturing device. An object of one embodiment of the present invention is to provide a low-cost display device. An object of one embodiment of the present invention is to provide a highly reliable display device. An object of one embodiment of the present invention is to provide a novel display device. An object of one embodiment of the present invention is to provide a novel semiconductor device or the like.
本発明の一態様は、表示品位の高い表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、表示ムラが軽減された表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、解像度の高い表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、大型の表示領域を有する表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、高いフレーム周波数で動作可能な表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、消費電力が低い表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、薄型の表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、可撓性を有する表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、視野角が広い表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、小型の製造装置で作製できる表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、低価格な表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、信頼性の高い表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、新規な表示装置の動作方法を提供することを課題の一つとする。本発明の一態様は、新規な半導体装置等の動作方法を提供することを課題の一つとする。 An object of one embodiment of the present invention is to provide a method for operating a display device with high display quality. An object of one embodiment of the present invention is to provide a method for operating a display device in which display unevenness is reduced. An object of one embodiment of the present invention is to provide a method for operating a display device with high resolution. An object of one embodiment of the present invention is to provide a method for operating a display device having a large display area. An object of one embodiment of the present invention is to provide a method of operating a display device operable at a high frame frequency. An object of one embodiment of the present invention is to provide a method for operating a display device with low power consumption. An object of one embodiment of the present invention is to provide a method for operating a thin display device. An object of one embodiment of the present invention is to provide a method for operating a flexible display device. An object of one embodiment of the present invention is to provide a method for operating a display device with a wide viewing angle. An object of one embodiment of the present invention is to provide a method for operating a display device that can be manufactured with a small manufacturing device. An object of one embodiment of the present invention is to provide a method for operating a low cost display device. An object of one embodiment of the present invention is to provide a method for operating a highly reliable display device. An object of one embodiment of the present invention is to provide a novel operation method of a display device. An object of one embodiment of the present invention is to provide a method for operating a novel semiconductor device or the like.
なお、これらの課題の記載は、他の課題の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの課題の全てを解決する必要はないものとする。明細書、図面、請求項の記載から、これら以外の課題を抽出することが可能である。 Note that the descriptions of these objects do not disturb the existence of other objects. One aspect of the present invention does not necessarily have to solve all of these problems. Other problems can be extracted from the description, drawings, and claims.
本発明の一態様は、第１の画素がマトリクス状に配列された第１の画素部と、第２の画素がマトリクス状に配列された第２の画素部と、を有する表示装置の動作方法であって、第１の画素部に表示される画像を補正する機能を有する第１の補正フィルタと、第２の画素部に表示される画像を補正する機能を有する第２の補正フィルタと、を作成し、第１の補正フィルタのフィルタ値と、第２の補正フィルタのフィルタ値と、を比較し、比較結果を基に、第１の補正フィルタのフィルタ値を修正する表示装置の動作方法である。 One embodiment of the present invention is an operation method of a display device including a first pixel portion in which first pixels are arranged in a matrix and a second pixel portion in which second pixels are arranged in a matrix A first correction filter having a function of correcting an image displayed in the first pixel unit, and a second correction filter having a function of correcting an image displayed in the second pixel unit; Of the first correction filter and the filter value of the second correction filter, and correcting the filter value of the first correction filter based on the comparison result. It is.
又は、本発明の一態様は、ｍ行ｎ列（ｍ、ｎは２以上の整数）の第１の画素がマトリクス状に配列された第１の画素部と、ｍ行ｎ列の第２の画素がマトリクス状に配列された第２の画素部と、を有し、ｍ行目の第１の画素と、１行目の第２の画素と、は隣接する表示装置の動作方法であって、第１の画素部に表示される画像を補正する機能を有する第１の補正フィルタと、第２の画素部に表示される画像を補正する機能を有する第２の補正フィルタと、を作成し、第１の補正フィルタは、第１の画素に対応するフィルタ値を有し、第２の補正フィルタは、第２の画素に対応するフィルタ値を有し、第２の画素部との境界部に設けられた第１の画素に対応するフィルタ値の平均値と、第１の画素部との境界部に設けられた第２の画素に対応するフィルタ値の平均値と、を比較し、比較結果を基に、第１の補正フィルタのフィルタ値を修正する表示装置の動作方法である。 Alternatively, in one embodiment of the present invention, a first pixel portion in which first pixels of m rows and n columns (m and n are integers of 2 or more) are arranged in a matrix, and a second pixel portion of m rows and n columns And a second pixel portion in which pixels are arranged in a matrix, and the first pixel in the m-th row and the second pixel in the first row are an operation method of the adjacent display device. Creating a first correction filter having a function of correcting an image displayed in the first pixel unit, and a second correction filter having a function of correcting an image displayed in the second pixel unit; The first correction filter has a filter value corresponding to the first pixel, and the second correction filter has a filter value corresponding to the second pixel, and the boundary portion with the second pixel portion Corresponding to a second pixel provided at the boundary between the first pixel portion and the average value of the filter values corresponding to the first pixel provided in It compares the average value of the filter value, and based on the comparison result, an operation method of a display device for correcting the filter value of the first correction filter.
又は、上記態様において、第１の補正フィルタは、第１の画素から射出される光の輝度を、第１の画素の複数の階調値について測定することにより、第１の画素から射出される光の輝度と、第１の画素の階調値と、の対応関係のデータを取得し、第１の画素部に特定の階調値の画像を表示して、第１の画素から射出される光の輝度を測定することにより、輝度データを取得した後、対応関係のデータと、輝度データと、を用いて作成されてもよい。 Alternatively, in the above aspect, the first correction filter is emitted from the first pixel by measuring the luminance of light emitted from the first pixel for a plurality of gradation values of the first pixel. Data of the correspondence between the luminance of the light and the gradation value of the first pixel is acquired, and an image of a specific gradation value is displayed in the first pixel portion, and the light is emitted from the first pixel After the luminance data is acquired by measuring the luminance of the light, it may be created using the correspondence data and the luminance data.
又は、本発明の一態様は、第１の画素がマトリクス状に配列された第１の画素部と、第２の画素がマトリクス状に配列された第２の画素部と、を有する表示装置の動作方法であって、第１の画素部に第１の画像を、第２の画素部に第２の画像をそれぞれ表示し、第１の画素から射出される光の輝度と、第２の画素から射出される光の輝度と、を比較し、比較結果を基に、第１の画素から射出される光の輝度を補正する表示装置の動作方法である。 Alternatively, one embodiment of the present invention is a display device including a first pixel portion in which first pixels are arranged in a matrix and a second pixel portion in which second pixels are arranged in a matrix. In the operation method, the first image is displayed in the first pixel portion, the second image is displayed in the second pixel portion, and the luminance of the light emitted from the first pixel and the second pixel are displayed. And the luminance of light emitted from the first pixel is corrected, and the luminance of the light emitted from the first pixel is corrected based on the comparison result.
又は、本発明の一態様は、ｍ行ｎ列（ｍ、ｎは２以上の整数）の第１の画素がマトリクス状に配列された第１の画素部と、ｍ行ｎ列の第２の画素がマトリクス状に配列された第２の画素部と、を有し、ｍ行目の第１の画素と、１行目の第２の画素と、は隣接する表示装置の動作方法であって、第１の画素部に第１の画像を、第２の画素部に第２の画像をそれぞれ表示し、第２の画素部との境界部に設けられた第１の画素から射出される光の輝度の平均値と、第１の画素部との境界部に設けられた第２の画素から射出される光の輝度の平均値と、を比較し、比較結果を基に、第１の画素から射出される光の輝度を補正する表示装置の動作方法である。 Alternatively, in one embodiment of the present invention, a first pixel portion in which first pixels of m rows and n columns (m and n are integers of 2 or more) are arranged in a matrix, and a second pixel portion of m rows and n columns And a second pixel portion in which pixels are arranged in a matrix, and the first pixel in the m-th row and the second pixel in the first row are an operation method of the adjacent display device. The first image is displayed in the first pixel portion, the second image is displayed in the second pixel portion, and the light emitted from the first pixel provided at the boundary with the second pixel portion. And the average value of the luminance of the light emitted from the second pixel provided at the boundary with the first pixel portion, and based on the comparison result, the first pixel Is the method of operation of the display device for correcting the brightness of the light emitted from the light source.
又は、上記態様において、第１の画素部に第１の画像を、第２の画素部に第２の画像をそれぞれ表示する前に、第１の画素から射出される光の輝度を、第１の画素の複数の階調値について測定することにより、第１の画素から射出される光の輝度と、第１の画素の階調値と、の対応関係のデータを取得し、第１の画素部に特定の階調値の画像を表示して、第１の画素から射出される光の輝度を測定することにより、輝度データを取得し、対応関係のデータと、輝度データと、を用いて、補正フィルタを作成し、第１の画像は、補正フィルタを用いて補正された画像であってもよい。 Alternatively, in the above aspect, before displaying the first image in the first pixel portion and the second image in the second pixel portion, the luminance of the light emitted from the first pixel is Data of the correspondence between the luminance of the light emitted from the first pixel and the gradation value of the first pixel by measuring a plurality of gradation values of the first pixel; The luminance data is acquired by displaying the image of the specific gradation value on the unit and measuring the luminance of the light emitted from the first pixel, and the correspondence data and the luminance data are used. , A correction filter is created, and the first image may be an image corrected using the correction filter.
又は、上記態様において、特定の階調値の画像は、全ての第１の画素の階調値が等しい画像であってもよい。 Alternatively, in the above aspect, the image of a specific tone value may be an image in which the tone values of all the first pixels are equal.
又は、本発明の一態様は、画素部と、処理部と、を有する表示装置であり、画素部には、画素がマトリクス状に配列され、画素は、表示素子と、メモリ回路と、を有し、処理部は、表示素子により表示された画像に基づき取得された輝度データを用いて、補正フィルタを作成する機能を有し、メモリ回路は、補正フィルタを保持する機能を有する表示装置である。 Alternatively, one embodiment of the present invention is a display device including a pixel portion and a processing portion, in the pixel portion, pixels are arrayed in a matrix, and the pixel includes a display element and a memory circuit. The processing unit has a function of creating a correction filter using luminance data acquired based on the image displayed by the display element, and the memory circuit is a display device having a function of holding the correction filter. .
又は、上記態様において、画素は、表示素子と、第１のトランジスタと、第２のトランジスタと、第３のトランジスタと、第４のトランジスタと、第１の容量素子と、第２の容量素子と、を有し、第１のトランジスタのソース又はドレインの一方は、第１の容量素子の一方の電極と電気的に接続され、第１の容量素子の他方の電極は、第２のトランジスタのソース又はドレインの一方と電気的に接続され、第２のトランジスタのソース又はドレインの一方は、第３のトランジスタのゲートと電気的に接続され、第３のトランジスタのゲートは、第２の容量素子の一方の電極と電気的に接続され、第２の容量素子の他方の電極は、第３のトランジスタのソース又はドレインの一方と電気的に接続され、第３のトランジスタのソース又はドレインの一方は、第４のトランジスタのソース又はドレインの一方と電気的に接続され、第４のトランジスタのソース又はドレインの他方は、表示素子の一方の電極と電気的に接続されていてもよい。 Alternatively, in the above embodiment, the pixel includes the display element, the first transistor, the second transistor, the third transistor, the fourth transistor, the first capacitor, and the second capacitor. , One of the source or drain of the first transistor is electrically connected to one electrode of the first capacitive element, and the other electrode of the first capacitive element is the source of the second transistor Or one of the drain and one of the source or the drain of the second transistor is electrically connected to the gate of the third transistor, and the gate of the third transistor is The other electrode of the second capacitor element is electrically connected to one of the electrodes, and the other electrode of the second capacitor element is electrically connected to one of the source or the drain of the third transistor, and the source or the drain of the third transistor One is the source or of the fourth transistor is electrically connected to one of the drain, the other of the source and the drain of the fourth transistor may be one electrode electrically connected to the display device.
又は、上記態様において、表示素子は、有機ＥＬ素子であってもよい。 Alternatively, in the above aspect, the display element may be an organic EL element.
又は、上記態様において、第２のトランジスタは、チャネル形成領域に金属酸化物を有し、金属酸化物は、Ｉｎと、Ｚｎと、Ｍ（ＭはＡｌ、Ｔｉ、Ｇａ、Ｓｎ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、又はＨｆ）と、を有してもよい。 Alternatively, in the above embodiment, the second transistor includes a metal oxide in the channel formation region, and the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
本発明の一態様により、表示品位の高い表示装置を提供することができる。本発明の一態様により、表示ムラが軽減された表示装置を提供することができる。本発明の一態様により、解像度の高い表示装置を提供することができる。本発明の一態様により、大型の表示領域を有する表示装置を提供することができる。本発明の一態様により、高いフレーム周波数で動作可能な表示装置を提供することができる。本発明の一態様により、消費電力が低い表示装置を提供することができる。本発明の一態様により、薄型の表示装置を提供することができる。本発明の一態様により、可撓性を有する表示装置を提供することができる。本発明の一態様により、視野角が広い表示装置を提供することができる。本発明の一態様により、小型の製造装置で作製できる表示装置を提供することができる。本発明の一態様により、低価格な表示装置を提供することができる。本発明の一態様により、信頼性の高い表示装置を提供することができる。本発明の一態様により、新規な表示装置を提供することができる。本発明の一態様により、新規な半導体装置等を提供することができる。 According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a display device with reduced display unevenness can be provided. According to one embodiment of the present invention, a display device with high resolution can be provided. According to one embodiment of the present invention, a display device having a large display area can be provided. According to one embodiment of the present invention, a display capable of operating at a high frame frequency can be provided. According to one embodiment of the present invention, a display device with low power consumption can be provided. According to one embodiment of the present invention, a thin display device can be provided. According to one embodiment of the present invention, a flexible display device can be provided. According to one embodiment of the present invention, a display device with a wide viewing angle can be provided. According to one embodiment of the present invention, a display device that can be manufactured with a small manufacturing device can be provided. According to one embodiment of the present invention, a low cost display device can be provided. According to one embodiment of the present invention, a highly reliable display device can be provided. According to one embodiment of the present invention, a novel display device can be provided. According to one embodiment of the present invention, a novel semiconductor device or the like can be provided.
本発明の一態様により、表示品位の高い表示装置の動作方法を提供することができる。本発明の一態様により、表示ムラが軽減された表示装置の動作方法を提供することができる。本発明の一態様により、解像度の高い表示装置の動作方法を提供することができる。本発明の一態様により、大型の表示領域を有する表示装置の動作方法を提供することができる。本発明の一態様により、高いフレーム周波数で動作可能な表示装置の動作方法を提供することができる。本発明の一態様により、消費電力が低い表示装置の動作方法を提供することができる。本発明の一態様により、薄型の表示装置の動作方法を提供することができる。本発明の一態様により、可撓性を有する表示装置の動作方法を提供することができる。本発明の一態様により、視野角が広い表示装置の動作方法を提供することができる。本発明の一態様により、小型の製造装置で作製できる表示装置の動作方法を提供することができる。本発明の一態様により、低価格な表示装置の動作方法を提供することができる。本発明の一態様により、信頼性の高い表示装置の動作方法を提供することができる。本発明の一態様により、新規な表示装置の動作方法を提供することができる。本発明の一態様により、新規な半導体装置等の動作方法を提供することができる。 According to one embodiment of the present invention, a method for operating a display device with high display quality can be provided. According to one embodiment of the present invention, an operation method of a display device with reduced display unevenness can be provided. According to one embodiment of the present invention, an operation method of a display device with high resolution can be provided. According to one embodiment of the present invention, an operation method of a display device having a large display area can be provided. According to one aspect of the present invention, it is possible to provide a method of operating a display operable at a high frame frequency. According to one embodiment of the present invention, a method for operating a display device with low power consumption can be provided. According to one embodiment of the present invention, an operation method of a thin display device can be provided. According to one embodiment of the present invention, an operation method of a flexible display device can be provided. According to one embodiment of the present invention, a method for operating a display device with a wide viewing angle can be provided. According to one embodiment of the present invention, an operation method of a display device which can be manufactured with a small manufacturing device can be provided. According to one embodiment of the present invention, an inexpensive method for operating a display device can be provided. One embodiment of the present invention can provide a method for operating a highly reliable display device. According to one aspect of the present invention, a novel display device operation method can be provided. According to one embodiment of the present invention, an operation method of a novel semiconductor device or the like can be provided.
なお、これらの効果の記載は、他の効果の存在を妨げるものではない。本発明の一態様は、必ずしも、これらの効果の全てを有する必要はない。明細書、図面、請求項の記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. One aspect of the present invention does not necessarily have to have all of these effects. Other effects can be extracted from the description, the drawings, and the claims.
表示装置の一例を示す図。FIG. 7 is a diagram illustrating an example of a display device. 表示部の一例を示す図。The figure which shows an example of a display part. 表示パネルの一例を示す図。FIG. 7 is a diagram illustrating an example of a display panel. 表示装置の一例を示す図。FIG. 7 is a diagram illustrating an example of a display device. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 画素の一例を示す図。FIG. 2 is a diagram showing an example of a pixel. 表示装置の一例を示す図。FIG. 7 is a diagram illustrating an example of a display device. 表示部の一例を示す図。The figure which shows an example of a display part. 画素の一例を示す図。FIG. 2 is a diagram showing an example of a pixel. 画素の動作の一例を示す図。FIG. 6 shows an example of the operation of a pixel. 画素の一例を示す図。FIG. 2 is a diagram showing an example of a pixel. 画素の動作の一例を示す図。FIG. 6 shows an example of the operation of a pixel. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 表示装置の動作の一例を示す図。FIG. 8 shows an example of operation of a display device. 表示装置の一例を示す図。FIG. 7 is a diagram illustrating an example of a display device. トランジスタの一例を示す図。FIG. 18 illustrates an example of a transistor. トランジスタの一例を示す図。FIG. 18 illustrates an example of a transistor. トランジスタの一例を示す図。FIG. 18 illustrates an example of a transistor. トランジスタの一例を示す図。FIG. 18 illustrates an example of a transistor. 電子機器の一例を示す図。FIG. 6 illustrates an example of an electronic device. 実施例１で用いた表示装置を示す図。FIG. 2 is a view showing a display device used in Example 1; 実施例１の表示結果を示す写真。The photograph which shows the display result of Example 1. FIG. 実施例２の輝度データを示す写真。The photograph which shows the luminance data of Example 2. FIG.
実施の形態について、図面を用いて詳細に説明する。但し、本発明は以下の説明に限定されず、本発明の主旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは当業者であれば容易に理解される。従って、本発明は以下に示す実施の形態の記載内容に限定して解釈されるものではない。 Embodiments will be described in detail with reference to the drawings. However, it is easily understood by those skilled in the art that the present invention is not limited to the following description, and various changes in the form and details can be made without departing from the spirit of the present invention and the scope thereof. Therefore, the present invention should not be construed as being limited to the description of the embodiments below.
なお、以下に説明する発明の構成において、同一部分又は同様な機能を有する部分には同一の符号を異なる図面間で共通して用い、その繰り返しの説明は省略する。また、同様の機能を指す場合には、ハッチパターンを同じくし、特に符号を付さない場合がある。 Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated. In addition, when referring to the same function, the hatch pattern may be the same and no reference numeral may be given.
また、図面において示す各構成の、位置、大きさ、範囲等は、理解の簡単のため、実際の位置、大きさ、範囲等を表していない場合がある。このため、開示する発明は、必ずしも、図面に開示された位置、大きさ、範囲等に限定されない。 In addition, the positions, sizes, ranges, and the like of the components shown in the drawings may not indicate actual positions, sizes, ranges, and the like for ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, range, and the like disclosed in the drawings.
なお、「膜」という用語と、「層」という用語とは、場合によっては、又は、状況に応じて、互いに入れ替えることが可能である。例えば、「導電層」という用語を、「導電膜」という用語に変更することが可能である。又は、例えば、「絶縁膜」という用語を、「絶縁層」という用語に変更することが可能である。 In addition, the term "membrane" and the term "layer" can be replaced with each other depending on the case or situation. For example, the term "conductive layer" can be changed to the term "conductive film". Alternatively, for example, the term "insulating film" can be changed to the term "insulating layer".
本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い意味での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む）、酸化物半導体（Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ又は単にＯＳともいう）等に分類される。例えば、トランジスタの半導体層に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、ＯＳ　ＦＥＴと記載する場合においては、金属酸化物又は酸化物半導体を有するトランジスタと換言することができる。 In the present specification and the like, the metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductor or simply OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, in the case of describing an OS FET, the transistor can be put in another way as a transistor including a metal oxide or an oxide semiconductor.
また、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。 In the present specification and the like, metal oxides having nitrogen may also be collectively referred to as metal oxides. In addition, a metal oxide having nitrogen may be referred to as metal oxynitride.
（実施の形態１）
本実施の形態では、本発明の一態様の表示装置について図１乃至図１７を用いて説明する。 Embodiment 1
In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.
本発明の一態様は、複数の表示パネルを並べることで大きな表示領域を実現した場合であっても、表示パネル間の境界が認識されにくくなる表示装置及びその動作方法に関する。 One embodiment of the present invention relates to a display device and its operation method in which a boundary between display panels is difficult to be recognized even when a large display region is realized by arranging a plurality of display panels.
＜１−１．表示装置の構成例１＞
図１（Ａ）、（Ｂ）は、表示装置１０Ａの構成例を示すブロック図である。 <1-1. Configuration Example 1 of Display Device>
FIGS. 1A and 1B are block diagrams showing a configuration example of the display device 10A.
表示装置１０Ａは、外部から受信したデータを用いて、画像データを生成する機能と、当該画像データに基づいて、画像を表示する機能と、を有する。 The display device 10A has a function of generating image data using data received from the outside, and a function of displaying an image based on the image data.
図１（Ａ）に示すように、表示装置１０Ａは、表示部２０Ａ及び信号生成部３０Ａを有する。表示部２０Ａは、複数の表示パネルＤＰを有する。信号生成部３０Ａは、外部から受信したデータを用いて、画像データを生成する機能を有する。表示パネルＤＰは、当該画像データに基づいて、画像を表示する機能を有する。 As shown in FIG. 1A, the display device 10A includes a display unit 20A and a signal generation unit 30A. The display unit 20A has a plurality of display panels DP. The signal generation unit 30A has a function of generating image data using data received from the outside. The display panel DP has a function of displaying an image based on the image data.
図１（Ａ）では、表示部２０Ａに、表示パネルＤＰが２行１列に並べられた例を示す。表示パネルＤＰの表示はそれぞれ独立に制御することができる。なお、表示部２０Ａに、表示パネルＤＰを３行以上並べてもよいし、２列以上並べてもよい。 FIG. 1A shows an example in which the display panel DP is arranged in two rows and one column in the display unit 20A. The display of the display panel DP can be controlled independently. Note that three or more lines of display panels DP may be arranged in the display unit 20A, or two or more lines may be arranged.
本明細書等において、ｐ行ｑ列目（ｐ，ｑは１以上の整数）に設けられた表示パネルＤＰを、表示パネルＤＰ［ｐ，ｑ］と示す。 In the present specification and the like, the display panel DP provided at the p-th row and the q-th column (p and q are integers of 1 or more) is referred to as a display panel DP [p, q].
複数の表示パネルＤＰを並べることで、広い表示領域を有する表示部２０Ａを作製することができる。 By arranging the plurality of display panels DP, the display unit 20A having a wide display area can be manufactured.
図１（Ｂ）に、表示パネルＤＰ［１，１］及び表示パネルＤＰ［２，１］の構成例を示す。表示パネルＤＰ［１，１］は、画素部２１Ａ、走査線駆動回路２２Ａ（ゲートドライバともいう）、信号線駆動回路２３Ａ（ソースドライバともいう）、及びタイミングコントローラ２４Ａを有する。表示パネルＤＰ［２，１］は、画素部２１Ｂ、走査線駆動回路２２Ｂ、信号線駆動回路２３Ｂ、及びタイミングコントローラ２４Ｂを有する。信号生成部３０Ａは、フロントエンド部３１、デコーダ３２、処理部３３、受信部３４、インターフェース３５、制御部３６、処理部４０Ａ、及び分割部４５Ａを有する。 FIG. 1B shows a configuration example of the display panel DP [1, 1] and the display panel DP [2, 1]. The display panel DP [1,1] includes a pixel portion 21A, a scanning line drive circuit 22A (also referred to as a gate driver), a signal line drive circuit 23A (also referred to as a source driver), and a timing controller 24A. The display panel DP [2, 1] includes a pixel unit 21B, a scanning line drive circuit 22B, a signal line drive circuit 23B, and a timing controller 24B. The signal generation unit 30A includes a front end unit 31, a decoder 32, a processing unit 33, a reception unit 34, an interface 35, a control unit 36, a processing unit 40A, and a division unit 45A.
なお、本明細書等において、画素部２１Ａ及び画素部２１Ｂ等の、本発明の一態様の表示装置が有する表示部に設けられた画素部を、画素部２１という場合がある。また、走査線駆動回路２２Ａ及び走査線駆動回路２２Ｂ等の、本発明の一態様の表示装置が有する表示部に設けられた走査線駆動回路を、走査線駆動回路２２という場合がある。さらに、信号線駆動回路２３Ａ及び信号線駆動回路２３Ｂ等の、本発明の一態様の表示装置が有する表示部に設けられた信号線駆動回路を、信号線駆動回路２３という場合がある。 Note that in this specification and the like, a pixel portion provided in a display portion included in a display device of one embodiment of the present invention, such as the pixel portion 21A and the pixel portion 21B, may be referred to as a pixel portion 21. The scan line drive circuit provided in the display portion of the display device of one embodiment of the present invention, such as the scan line drive circuit 22A and the scan line drive circuit 22B, may be referred to as a scan line drive circuit 22. Further, a signal line driver circuit provided in a display portion of the display device of one embodiment of the present invention, such as the signal line driver circuit 23A and the signal line driver circuit 23B, may be referred to as a signal line driver circuit 23.
以下では、表示パネルＤＰ及び信号生成部３０Ａが有する各構成要素について説明する。 Below, each component which display panel DP and signal generation part 30A have is demonstrated.
画素部２１Ａ及び画素部２１Ｂは、複数の画素を有する。画素部２１Ａ及び画素部２１Ｂは、画像を表示する機能を有する。 The pixel unit 21A and the pixel unit 21B have a plurality of pixels. The pixel unit 21A and the pixel unit 21B have a function of displaying an image.
画素は、表示素子を有する。画素は、階調値に応じた輝度の光を射出する機能を有する。走査線駆動回路２２Ａ及び信号線駆動回路２３Ａから供給される信号により、画素の階調が制御され、画素部２１Ａに所定の画像が表示される。また、走査線駆動回路２２Ｂ及び信号線駆動回路２３Ｂから供給される信号により、画素の階調が制御され、画素部２１Ｂに所定の画像が表示される。 The pixel has a display element. The pixel has a function of emitting light of luminance according to the gradation value. The tone of the pixel is controlled by the signals supplied from the scanning line drive circuit 22A and the signal line drive circuit 23A, and a predetermined image is displayed on the pixel section 21A. Further, the gradation of the pixel is controlled by the signals supplied from the scanning line drive circuit 22B and the signal line drive circuit 23B, and a predetermined image is displayed on the pixel section 21B.
走査線駆動回路２２Ａは、画素を選択するための信号（選択信号ともいう）を画素部２１Ａに供給する機能を有する。走査線駆動回路２２Ｂは、選択信号を画素部２１Ｂに供給する機能を有する。 The scanning line drive circuit 22A has a function of supplying a signal for selecting a pixel (also referred to as a selection signal) to the pixel portion 21A. The scanning line drive circuit 22B has a function of supplying a selection signal to the pixel portion 21B.
信号線駆動回路２３Ａは、画素が表現する階調を表した信号（画像信号ともいう）を画素部２１Ａに供給する機能を有する。信号線駆動回路２３Ｂは、画像信号を画素部２１Ｂに供給する機能を有する。選択信号が供給された画素に画像信号が供給されることにより、当該画素は階調値に応じた輝度の光を射出し、画素部２１Ａ及び画素部２１Ｂに所定の画像が表示される。 The signal line drive circuit 23A has a function of supplying a signal (also referred to as an image signal) representing a gray scale represented by a pixel to the pixel portion 21A. The signal line drive circuit 23B has a function of supplying an image signal to the pixel portion 21B. By supplying the image signal to the pixel to which the selection signal is supplied, the pixel emits light of luminance according to the gradation value, and a predetermined image is displayed on the pixel portion 21A and the pixel portion 21B.
タイミングコントローラ２４Ａは、走査線駆動回路２２Ａ、信号線駆動回路２３Ａ等で用いられるタイミング信号（クロック信号、スタートパルス信号等）を生成する機能を有する。タイミングコントローラ２４Ｂは、走査線駆動回路２２Ｂ、信号線駆動回路２３Ｂ等で用いられるタイミング信号を生成する機能を有する。走査線駆動回路２２Ａから選択信号が出力されるタイミング及び信号線駆動回路２３Ａから画像信号が出力されるタイミングのうち、一方又は双方は、タイミングコントローラ２４Ａによって生成されたタイミング信号によって制御される。走査線駆動回路２２Ｂから選択信号が出力されるタイミング及び信号線駆動回路２３Ｂから画像信号が出力されるタイミングのうち、一方又は双方は、タイミングコントローラ２４Ｂによって生成されたタイミング信号によって制御される。また、表示パネルＤＰ［１，１］が、走査線駆動回路を複数有する場合、複数の走査線駆動回路から信号が出力されるタイミングは、タイミングコントローラ２４Ａによって生成されたタイミング信号によって同期される。表示パネルＤＰ［２，１］が、走査線駆動回路を複数有する場合、複数の走査線駆動回路から信号が出力されるタイミングは、タイミングコントローラ２４Ｂによって生成されたタイミング信号によって同期される。同様に、表示パネルＤＰ［１，１］が、信号線駆動回路を複数有する場合、信号線駆動回路から信号が出力されるタイミングは、タイミングコントローラ２４Ａによって生成されたタイミング信号によって同期される。表示パネルＤＰ［２，１］が、信号線駆動回路を複数有する場合、信号線駆動回路から信号が出力されるタイミングは、タイミングコントローラ２４Ｂによって生成されたタイミング信号によって同期される。 The timing controller 24A has a function of generating timing signals (clock signal, start pulse signal and the like) used in the scanning line drive circuit 22A, the signal line drive circuit 23A and the like. The timing controller 24B has a function of generating timing signals used in the scanning line drive circuit 22B, the signal line drive circuit 23B, and the like. One or both of the timing when the selection signal is output from the scanning line drive circuit 22A and the timing when the image signal is output from the signal line drive circuit 23A are controlled by the timing signal generated by the timing controller 24A. One or both of the timing when the selection signal is output from the scanning line drive circuit 22B and the timing when the image signal is output from the signal line drive circuit 23B are controlled by the timing signal generated by the timing controller 24B. Further, when the display panel DP [1, 1] has a plurality of scanning line driving circuits, timings at which signals are output from the plurality of scanning line driving circuits are synchronized by a timing signal generated by the timing controller 24A. When the display panel DP [2, 1] includes a plurality of scanning line drive circuits, timings at which signals are output from the plurality of scanning line drive circuits are synchronized by the timing signal generated by the timing controller 24B. Similarly, when the display panel DP [1, 1] has a plurality of signal line drive circuits, timings at which signals are output from the signal line drive circuits are synchronized by timing signals generated by the timing controller 24A. When the display panel DP [2, 1] includes a plurality of signal line drive circuits, timings at which signals are output from the signal line drive circuits are synchronized by timing signals generated by the timing controller 24B.
フロントエンド部３１は、外部から入力される信号を受信し、適宜信号処理を行う機能を有する。フロントエンド部３１には、例えば、所定の方式で符号化され、変調された放送信号等が入力される。フロントエンド部３１は、受信した画像信号の復調、アナログ−デジタル変換等を行う機能を有することができる。また、フロントエンド部３１はエラー訂正を行う機能を有していてもよい。フロントエンド部３１によって受信され、信号処理が施されたデータは、デコーダ３２に出力される。 The front end unit 31 has a function of receiving a signal input from the outside and appropriately performing signal processing. The front end unit 31 receives, for example, a broadcast signal or the like that has been encoded and modulated according to a predetermined method. The front end unit 31 can have a function of demodulating the received image signal, performing analog-digital conversion, and the like. In addition, the front end unit 31 may have a function of performing error correction. The data received by the front end unit 31 and subjected to the signal processing is output to the decoder 32.
デコーダ３２は、符号化された信号を復号する機能を有する。フロントエンド部３１に入力された放送信号等に含まれる画像データが圧縮されている場合、デコーダ３２によって伸長が行われる。例えば、デコーダ３２は、エントロピー復号、逆量子化、逆離散コサイン変換（ＩＤＣＴ）や逆離散サイン変換（ＩＤＳＴ）等の逆直交変換、フレーム内予測、フレーム間予測等を行う機能を有することができる。デコーダ３２による復号処理により生成された画像データは、処理部３３に出力される。 The decoder 32 has a function of decoding the encoded signal. When image data included in the broadcast signal or the like input to the front end unit 31 is compressed, the decoder 32 performs decompression. For example, the decoder 32 can have a function of performing inverse orthogonal transformation such as entropy decoding, inverse quantization, inverse discrete cosine transformation (IDCT), inverse discrete sine transformation (IDST), intra-frame prediction, inter-frame prediction, etc. . The image data generated by the decoding process by the decoder 32 is output to the processing unit 33.
処理部３３は、デコーダ３２から入力された画像データに対して画像処理を行い、第１の画像データＳＤ１を生成し、処理部４０Ａに出力する機能を有する。 The processing unit 33 has a function of performing image processing on the image data input from the decoder 32, generating the first image data SD1, and outputting the first image data SD1 to the processing unit 40A.
画像処理の例としては、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理等が挙げられる。色調補正処理や輝度補正処理は、ガンマ補正等を用いて行うことができる。 Examples of the image processing include noise removal processing, tone conversion processing, color tone correction processing, luminance correction processing and the like. Color tone correction processing and luminance correction processing can be performed using gamma correction or the like.
ノイズ除去処理としては、文字等の輪郭の周辺に生じるモスキートノイズ、高速の動画で生じるブロックノイズ、ちらつきを生じさせるランダムノイズ等のさまざまなノイズの除去が挙げられる。 Examples of the noise removal process include removal of various noises such as mosquito noise generated around an outline of a character or the like, block noise generated in a high-speed moving image, and random noise causing flicker.
階調変換処理は、第１の画像データＳＤ１が示す階調を表示部２０Ａの出力特性に対応した階調へ変換する処理である。例えば階調数を大きくする場合、小さい階調数で入力された画像に対して、各画素に対応する階調値を補間して割り当てることで、ヒストグラムを平滑化する処理を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 The gradation conversion process is a process of converting the gradation indicated by the first image data SD1 into a gradation corresponding to the output characteristic of the display unit 20A. For example, in the case where the number of gradations is increased, processing for smoothing the histogram can be performed by interpolating and allocating gradation values corresponding to respective pixels to an image input with a small number of gradations. Also, high dynamic range (HDR) processing, which extends the dynamic range, is also included in the tone conversion processing.
色調補正処理は、画像の色調を補正する処理である。また輝度補正処理は、画像の明るさ（輝度コントラスト）を補正する処理である。例えば、表示部２０Ａが設けられる空間の照明の種類や輝度、又は色純度等に応じて、表示部２０Ａに表示される画像の輝度や色調が最適となるように補正される。 Color tone correction processing is processing for correcting the color tone of an image. The luminance correction processing is processing for correcting the brightness (luminance contrast) of an image. For example, the brightness and the color tone of the image displayed on the display unit 20A are corrected so as to be optimal according to the type and the brightness or the color purity of the illumination in the space where the display unit 20A is provided.
フレーム間補間処理は、表示する画像のフレーム周波数を増大させる場合に、本来存在しないフレーム（補間フレーム）の画像を生成する処理である。例えば、ある２枚の画像の差分から２枚の画像の間に挿入する補間フレームの画像を生成する。又は２枚の画像の間に複数枚の補間フレームの画像を生成することもできる。例えば画像データのフレーム周波数が６０Ｈｚであったとき、複数枚の補間フレームを生成することで、表示部２０Ａに出力される画像信号のフレーム周波数を、２倍の１２０Ｈｚ、又は４倍の２４０Ｈｚ、又は８倍の４８０Ｈｚ等に増大させることができる。 The interframe interpolation process is a process of generating an image of a frame (interpolated frame) which does not originally exist, when the frame frequency of the image to be displayed is increased. For example, an image of an interpolation frame to be inserted between two images is generated from the difference between two images. Alternatively, images of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the image data is 60 Hz, the frame frequency of the image signal output to the display unit 20A is doubled by 120 Hz, or quadrupled by 240 Hz, by generating a plurality of interpolation frames. It can be increased to eight times 480 Hz and so on.
なお、上記の画像処理は、処理部３３とは別途設けられた処理部によって行うこともできる。また、上記の画像処理の一つ又は複数を、処理部４０Ａによって行ってもよい。 Note that the above-described image processing can also be performed by a processing unit provided separately from the processing unit 33. In addition, one or more of the above-described image processing may be performed by the processing unit 40A.
受信部３４は、外部から入力されるデータ又は制御信号を受信する機能を有する。受信部３４へのデータ又は制御信号の入力には、演算処理装置５０、リモートコントローラ、携帯情報端末（スマートフォンやタブレット等）、表示部２０Ａに設けられた操作ボタン、タッチパネル等を用いることができる。なお、演算処理装置５０としては、コンピュータ、サーバ、クラウド等、演算処理能力に優れた計算機が挙げられる。 The receiving unit 34 has a function of receiving externally input data or control signals. The arithmetic processing unit 50, a remote controller, a portable information terminal (such as a smartphone or a tablet), an operation button provided on the display unit 20A, a touch panel, or the like can be used to input data or control signals to the reception unit 34. The arithmetic processing unit 50 may be a computer such as a computer, a server, or a cloud, which has an excellent arithmetic processing capability.
インターフェース３５は、受信部３４が受信したデータ又は制御信号に適宜信号処理を施し、制御部３６に出力する機能を有する。 The interface 35 has a function of appropriately performing signal processing on the data or control signal received by the receiving unit 34 and outputting the data or control signal to the control unit 36.
制御部３６は、信号生成部３０Ａが有する各回路に制御信号を供給する機能を有する。例えば、制御部３６は、デコーダ３２、処理部３３、処理部４０Ａ、及び分割部４５Ａに制御信号を供給する機能を有する。制御部３６による制御は、受信部３４が受信した制御信号等に基づいて行うことができる。 The control unit 36 has a function of supplying control signals to the circuits included in the signal generation unit 30A. For example, the control unit 36 has a function of supplying a control signal to the decoder 32, the processing unit 33, the processing unit 40A, and the dividing unit 45A. The control by the control unit 36 can be performed based on the control signal or the like received by the receiving unit 34.
処理部４０Ａは、補正フィルタを作成する機能を有する。また、処理部４０Ａは、処理部３３から入力された第１の画像データＳＤ１を、作成した補正フィルタを用いて補正することにより、第２の画像データＳＤ２を生成する機能を有する。例えば、処理部４０Ａは、表示部２０Ａに表示される画像の表示ムラが軽減されるように、第１の画像データＳＤ１を補正する機能を有する。例えば、処理部４０Ａは、詳細は後述するが、表示パネル間の境界が認識されにくくなるように、第１の画像データＳＤ１を補正する機能を有する。処理部４０Ａによって生成された第２の画像データＳＤ２は、分割部４５Ａに出力される。 The processing unit 40A has a function of creating a correction filter. The processing unit 40A also has a function of generating the second image data SD2 by correcting the first image data SD1 input from the processing unit 33 using the created correction filter. For example, the processing unit 40A has a function of correcting the first image data SD1 so as to reduce display unevenness of the image displayed on the display unit 20A. For example, although details will be described later, the processing unit 40A has a function of correcting the first image data SD1 so that the boundaries between the display panels are not easily recognized. The second image data SD2 generated by the processing unit 40A is output to the dividing unit 45A.
分割部４５Ａは、処理部４０Ａから入力された第２の画像データＳＤ２を分割する機能を有する。第２の画像データＳＤ２は、表示部２０Ａに設けられた表示パネルＤＰと同じ数に分割することができる。図１（Ａ）においては、第２の画像データＳＤ２が２×１個（第２の画像データＳＤ２［１，１］、及び第２の画像データＳＤ２［２，１］）に分割され、表示部２０Ａに出力される。第２の画像データＳＤ２［１，１］は、表示パネルＤＰ［１，１］に表示される画像に対応する画像データであり、第２の画像データＳＤ２［２，１］は、表示パネルＤＰ［２，１］に表示される画像に対応する画像データである。分割部４５Ａは、第２の画像データＳＤ２［１，１］を信号線駆動回路２３Ａに出力し、第２の画像データＳＤ２［２，１］を信号線駆動回路２３Ｂに出力する。 The dividing unit 45A has a function of dividing the second image data SD2 input from the processing unit 40A. The second image data SD2 can be divided into the same number as that of the display panel DP provided in the display unit 20A. In FIG. 1A, the second image data SD2 is divided into 2 × 1 pieces (second image data SD2 [1,1] and second image data SD2 [2,1]) and displayed. It is output to the unit 20A. The second image data SD2 [1,1] is image data corresponding to the image displayed on the display panel DP [1,1], and the second image data SD2 [2,1] is the display panel DP It is image data corresponding to the image displayed in [2, 1]. The dividing unit 45A outputs the second image data SD2 [1,1] to the signal line drive circuit 23A, and outputs the second image data SD2 [2,1] to the signal line drive circuit 23B.
図２に、表示パネルＤＰ［１，１］及び表示パネルＤＰ［２，１］の具体的な構成例を示す。 FIG. 2 shows a specific configuration example of the display panel DP [1, 1] and the display panel DP [2, 1].
画素部２１Ａ及び画素部２１Ｂは、それぞれ複数の画素２５を有する。図２では、画素部２１Ａ及び画素部２１Ｂが、それぞれｍ行ｎ列（ｍ及びｎはそれぞれ１以上の整数）のマトリクス状に配置された複数の画素２５を有する例を示す。 Each of the pixel unit 21A and the pixel unit 21B has a plurality of pixels 25. FIG. 2 illustrates an example in which the pixel unit 21A and the pixel unit 21B each have a plurality of pixels 25 arranged in a matrix of m rows and n columns (m and n are integers of 1 or more).
本明細書等において、画素部２１Ａに設けられた画素を、第１の画素という場合がある。また、画素部２１Ｂに設けられた画素を、第２の画素という場合がある。 In the present specification and the like, a pixel provided in the pixel portion 21A may be referred to as a first pixel. In addition, a pixel provided in the pixel portion 21B may be referred to as a second pixel.
画素部２１Ａの、画素部２１Ｂとの境界部を境界部２８Ａとする。また、画素部２１Ｂの、画素部２１Ａとの境界部を境界部２８Ｂとする。境界部２８Ａには、例えばｍ行目の画素２５が設けられているものとすることができる。例えば、境界部２８Ａには、（７／８）ｍ＋１行目乃至ｍ行目の画素２５が設けられているものとすることができる。例えば、境界部２８Ａには、（３／４）ｍ＋１行目乃至ｍ行目の画素２５が設けられているものとすることができる。又は、境界部２８Ａには、（１／２）ｍ＋１行目乃至ｍ行目の画素２５が設けられているものとすることができる。 A boundary between the pixel unit 21A and the pixel unit 21B is referred to as a boundary 28A. Further, a boundary between the pixel unit 21B and the pixel unit 21A is referred to as a boundary 28B. For example, the pixel 25 in the m-th row can be provided in the boundary portion 28A. For example, in the boundary portion 28A, the pixels 25 in the (7/8) m + 1st to m-th rows can be provided. For example, in the boundary portion 28A, the pixels 25 in the (3/4) m + 1st to m-th rows can be provided. Alternatively, the pixels 25 in the (1/2) m + 1-th to m-th rows can be provided in the boundary portion 28A.
また、境界部２８Ｂには、例えば１行目の画素２５が設けられているものとすることができる。例えば、境界部２８Ｂには、１行目乃至（１／８）ｍ行目の画素２５が設けられているものとすることができる。例えば、境界部２８Ｂには、１行目乃至（１／４）ｍ行目の画素２５が設けられているものとすることができる。例えば、境界部２８Ｂには、１行目乃至（１／２）ｍ行目の画素２５が設けられているものとすることができる。 In addition, in the boundary portion 28B, for example, the pixels 25 in the first row can be provided. For example, in the boundary portion 28B, the pixels 25 in the first to (1/8) m-th rows can be provided. For example, in the boundary portion 28B, the pixels 25 in the first to (1/4) m-th rows can be provided. For example, in the boundary portion 28B, the pixels 25 in the first to (1/2) m-th rows can be provided.
表示パネルＤＰ［１，１］は、ｍ本の走査線ＧＬａ（選択信号線、ゲート線等ともいう）を有する。表示パネルＤＰ［２，１］は、ｍ本の走査線ＧＬｂを有する。ｍ本の走査線ＧＬａ及びｍ本の走査線ＧＬｂは、それぞれ、行方向に延在する。ｍ本の走査線ＧＬａ及びｍ本の走査線ＧＬｂは、それぞれ、行方向に並ぶ画素２５と電気的に接続される。 The display panel DP [1,1] includes m scanning lines GLa (also referred to as selection signal lines, gate lines, and the like). The display panel DP [2, 1] has m scanning lines GLb. The m scanning lines GLa and the m scanning lines GLb respectively extend in the row direction. The m scanning lines GLa and the m scanning lines GLb are electrically connected to the pixels 25 aligned in the row direction.
本明細書等において、走査線ＧＬａ及び走査線ＧＬｂ等、本発明の一態様の表示装置に設けられた走査線を、走査線ＧＬという場合がある。 In this specification and the like, a scan line provided in a display device of one embodiment of the present invention, such as the scan line GLa and the scan line GLb, may be referred to as a scan line GL.
また、本明細書等では、ｉ行目（ｉは１以上ｍ以下の整数）の画素２５と電気的に接続する走査線ＧＬを走査線ＧＬ［ｉ］と示す。なお、走査線ＧＬ以外においても、ｉ行目の要素を表す記号又は符号に［ｉ］と付して区別する場合がある。 Further, in the present specification and the like, the scan line GL electrically connected to the pixel 25 in the i-th row (i is an integer of 1 or more and m or less) is referred to as a scan line GL [i]. In addition to the scanning line GL, the symbol or code representing the element in the i-th row may be distinguished by adding [i].
走査線ＧＬａの一端は、走査線駆動回路２２Ａと電気的に接続され、走査線ＧＬｂの一端は、走査線駆動回路２２Ｂと電気的に接続される。走査線駆動回路２２Ａは、走査線ＧＬａに選択信号を供給する機能を有し、走査線駆動回路２２Ｂは、走査線ＧＬｂに選択信号を供給する機能を有する。選択信号は、走査線ＧＬａを介して、画素部２１Ａが有する画素２５に供給され、走査線ＧＬｂを介して、画素部２１Ｂが有する画素２５に供給される。 One end of the scanning line GLa is electrically connected to the scanning line drive circuit 22A, and one end of the scanning line GLb is electrically connected to the scanning line drive circuit 22B. The scanning line driving circuit 22A has a function of supplying a selection signal to the scanning line GLa, and the scanning line driving circuit 22B has a function of supplying a selection signal to the scanning line GLb. The selection signal is supplied to the pixel 25 included in the pixel unit 21A through the scanning line GLa, and is supplied to the pixel 25 included in the pixel unit 21B through the scanning line GLb.
また、走査線駆動回路２２Ａは、走査線ＧＬａ［１］から走査線ＧＬａ［ｍ］まで順に選択信号を供給する機能を有する。言い換えると、走査線駆動回路２２Ａは、走査線ＧＬａ［１］乃至走査線ＧＬａ［ｍ］を順に走査する機能を有する。走査線ＧＬａ［ｍ］まで走査した後、再び走査線ＧＬａ［１］から順に走査する。また、走査線駆動回路２２Ｂは、走査線ＧＬｂ［１］から走査線ＧＬｂ［ｍ］まで順に選択信号を供給する機能を有する。言い換えると、走査線駆動回路２２Ｂは、走査線ＧＬｂ［１］乃至走査線ＧＬｂ［ｍ］を順に走査する機能を有する。走査線ＧＬｂ［ｍ］まで走査した後、再び走査線ＧＬｂ［１］から順に走査する。 In addition, the scanning line drive circuit 22A has a function of sequentially supplying selection signals from the scanning line GLa [1] to the scanning line GLa [m]. In other words, the scanning line drive circuit 22A has a function of sequentially scanning the scanning lines GLa [1] to the scanning lines GLa [m]. After scanning up to the scanning line GLa [m], scanning is sequentially performed again from the scanning line GLa [1]. In addition, the scanning line drive circuit 22B has a function of supplying selection signals in order from the scanning line GLb [1] to the scanning line GLb [m]. In other words, the scanning line drive circuit 22B has a function of sequentially scanning the scanning lines GLb [1] to the scanning lines GLb [m]. After scanning up to the scanning line GLb [m], scanning is sequentially performed again from the scanning line GLb [1].
なお、表示パネルＤＰ［１，１］に、走査線駆動回路２２Ａの他、もう１つ走査線駆動回路を設けてもよい。当該走査線駆動回路は、走査線ＧＬａの他端と電気的に接続される。よって、２つの走査線駆動回路が、画素部２１Ａを挟んで向かい合う位置に設けられる。また、表示パネルＤＰ［２，１］に、走査線駆動回路２２Ｂの他、もう１つ走査線駆動回路を設けてもよい。当該走査線駆動回路は、走査線ＧＬｂの他端と電気的に接続される。よって、２つの走査線駆動回路が、画素部２１Ｂを挟んで向かい合う位置に設けられる。 In addition to the scanning line driving circuit 22A, another scanning line driving circuit may be provided on the display panel DP [1, 1]. The scan line drive circuit is electrically connected to the other end of the scan line GLa. Therefore, two scanning line driving circuits are provided at positions facing each other across the pixel portion 21A. In addition to the scanning line driving circuit 22B, another scanning line driving circuit may be provided in the display panel DP [2, 1]. The scan line drive circuit is electrically connected to the other end of the scan line GLb. Thus, two scanning line driving circuits are provided at positions facing each other across the pixel portion 21B.
１つの表示パネルＤＰに走査線駆動回路が２個設けられている場合、１本の走査線ＧＬａ又は走査線ＧＬｂに、２つの走査線駆動回路から同時に選択信号を供給することで、当該走査線への選択信号の供給能力を高めることができる。 When two scanning line drive circuits are provided in one display panel DP, the selection signal is simultaneously supplied from one of the two scanning line driving circuits to one of the scanning lines GLa or scanning line GLb. Can increase the supply capability of the selection signal.
表示パネルＤＰ［１，１］は、ｎ本の信号線ＳＬａ（画像信号線、ソース線等ともいう）を有し、表示パネルＤＰ［２，１］は、ｎ本の信号線ＳＬｂを有する。ｎ本の信号線ＳＬａ及びｎ本の信号線ＳＬｂは、それぞれ、列方向に延在する。ｎ本の信号線ＳＬａ及びｎ本の信号線ＳＬｂは、それぞれ、列方向に並ぶ複数の画素２５と電気的に接続される。 The display panel DP [1, 1] has n signal lines SLa (also referred to as image signal lines, source lines and the like), and the display panel DP [2, 1] has n signal lines SLb. Each of the n signal lines SLa and the n signal lines SLb extends in the column direction. The n signal lines SLa and the n signal lines SLb are electrically connected to the plurality of pixels 25 arranged in the column direction.
本明細書等において、信号線ＳＬａ及び信号線ＳＬｂ等、本発明の一態様の表示装置に設けられた信号線を、信号線ＳＬという場合がある。 In this specification and the like, signal lines provided in a display device of one embodiment of the present invention, such as the signal line SLa and the signal line SLb, may be referred to as a signal line SL.
また、本明細書等では、ｊ列目（ｊは１以上ｎ以下の整数）の画素２５と電気的に接続する信号線ＳＬを信号線ＳＬ［ｊ］と示す。なお、信号線ＳＬ以外においても、ｊ列目の要素を表す記号又は符号に［ｊ］と付して区別する場合がある。 Further, in this specification and the like, the signal line SL electrically connected to the pixel 25 in the j-th column (j is an integer of 1 or more and n or less) is referred to as a signal line SL [j]. In addition to the signal line SL, the symbol or code representing the element in the j-th column may be distinguished by adding [j].
信号線ＳＬａは、信号線駆動回路２３Ａと電気的に接続され、信号線ＳＬｂは、信号線駆動回路２３Ｂと電気的に接続される。信号線駆動回路２３Ａは、信号線ＳＬａに画像信号を供給する機能を有し、信号線駆動回路２３Ｂは、信号線ＳＬｂに画像信号を供給する機能を有する。画像信号は、信号線ＳＬａを介して、画素部２１Ａが有する画素２５に供給され、信号線ＳＬｂを介して、画素部２１Ｂが有する画素２５に供給される。 Signal line SLa is electrically connected to signal line drive circuit 23A, and signal line SLb is electrically connected to signal line drive circuit 23B. The signal line drive circuit 23A has a function of supplying an image signal to the signal line SLa, and the signal line drive circuit 23B has a function of supplying an image signal to the signal line SLb. The image signal is supplied to the pixel 25 of the pixel unit 21A through the signal line SLa, and is supplied to the pixel 25 of the pixel unit 21B through the signal line SLb.
画素２５は、表示素子を有する。画素２５に設けられる表示素子の例としては、発光素子が挙げられる。発光素子としては、例えばＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、ＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、ＱＬＥＤ（Ｑｕａｎｔｕｍ−ｄｏｔ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、半導体レーザ等の、自発光性の発光素子が挙げられる。表示素子として発光素子、特にＯＬＥＤ又はマイクロＬＥＤを用いることにより、鮮やかな画像を表示し、表示品位を高めることができる。また、発光素子を有する表示装置は、バックライトを必要としないため、薄型の表示装置を提供することができる。また、可撓性を有する表示装置を提供することができる。さらに、視野角の広い表示装置を提供することができる。 The pixel 25 has a display element. A light emitting element can be given as an example of the display element provided in the pixel 25. Examples of light emitting elements include self-luminous light emitting elements such as organic light emitting diodes (OLEDs), light emitting diodes (LEDs), quantum-dot light emitting diodes (QLEDs), and semiconductor lasers. A bright image can be displayed and display quality can be improved by using a light-emitting element, in particular an OLED or a micro LED, as a display element. Further, a display device having a light-emitting element does not require a backlight, so that a thin display device can be provided. In addition, a flexible display device can be provided. Furthermore, a display device with a wide viewing angle can be provided.
また、表示素子として、液晶素子を用いてもよい。液晶素子としては、透過型の液晶素子、反射型の液晶素子、半透過型の液晶素子等が挙げられる。表示素子として液晶素子を用いることにより、低消費電力の表示装置を提供することができる。 Alternatively, a liquid crystal element may be used as the display element. Examples of liquid crystal elements include transmissive liquid crystal elements, reflective liquid crystal elements, and semi-transmissive liquid crystal elements. By using a liquid crystal element as the display element, a display device with low power consumption can be provided.
また、表示素子として、シャッター方式のＭＥＭＳ（Ｍｉｃｒｏ　Ｅｌｅｃｔｒｏ　Ｍｅｃｈａｎｉｃａｌ　Ｓｙｓｔｅｍ）素子、光干渉方式のＭＥＭＳ素子、マイクロカプセル方式、電気泳動方式、エレクトロウェッティング方式、電子粉流体（登録商標）方式等を適用した表示素子等を用いてもよい。 In addition, as a display element, a shutter type MEMS (Micro Electro Mechanical System) element, an optical interference type MEMS element, a microcapsule type, an electrophoresis type, an electrowetting type, an electronic powder fluid (registered trademark) type, etc. are applied. A display element or the like may be used.
表示部２０Ａに設けられる画素２５の数は自由に設定することができる。表示部２０Ａを大型とし、さらに高精細度の画像を表示するためには、画素２５を多く配置することが好ましい。例えば、２Ｋの画像を表示する場合は、１９２０×１０８０個以上の画素を設けることが好ましい。また、４Ｋの画像を表示する場合は、３８４０×２１６０個以上、又は４０９６×２１６０個以上の画素を設けることが好ましい。また、８Ｋの画像を表示する場合は、７６８０×４３２０個以上、又は８１９２×４３２０個以上の画素を設けることが好ましい。また、表示部２０Ａにはさらに多くの画素を設けることもできる。 The number of pixels 25 provided in the display unit 20A can be freely set. In order to increase the size of the display unit 20A and to display a high definition image, it is preferable to dispose a large number of pixels 25. For example, in the case of displaying a 2K image, it is preferable to provide 1920 × 1080 or more pixels. Further, in the case of displaying a 4K image, it is preferable to provide 3840 × 2160 or more pixels, or 4096 × 2160 or more pixels. In the case of displaying an 8K image, it is preferable to provide 7680 × 4320 or more pixels, or 8192 × 4320 or more pixels. In addition, more pixels can be provided in the display unit 20A.
ここで、複数の表示パネルＤＰを用いて大型の表示部２０Ａを作製する場合、１つの表示パネルＤＰの大きさは大型である必要がない。したがって、表示パネルＤＰを作製するための製造装置を大型化しなくてもよく、省スペース化が可能である。また、中小型の表示パネルの製造装置を用いることができ、表示部２０Ａの大型化のために新規な製造装置を利用しなくてもよいため、製造コストを抑えることができる。また、表示パネルＤＰの大型化に伴う歩留まりの低下を抑制できる。 Here, in the case where a large display unit 20A is manufactured using a plurality of display panels DP, the size of one display panel DP does not have to be large. Therefore, it is not necessary to increase the size of the manufacturing apparatus for manufacturing the display panel DP, and space can be saved. In addition, since it is possible to use a medium-to-small display panel manufacturing apparatus and not to use a new manufacturing apparatus for increasing the size of the display unit 20A, the manufacturing cost can be reduced. In addition, it is possible to suppress a decrease in yield due to the enlargement of the display panel DP.
表示パネルＤＰの大きさが同じである場合、複数の表示パネルＤＰを有する表示部の方が、１つの表示パネルＤＰを有する表示部に比べて表示領域が広く、一度に表示できる情報量が多い等の効果を有する。 When the size of the display panel DP is the same, the display unit having a plurality of display panels DP has a wider display area than the display unit having one display panel DP, and the amount of information which can be displayed at one time is large. And so on.
なお、図２に示す複数の画素２５は、それぞれ、赤色（Ｒ）、緑色（Ｇ）、又は青色（Ｂ）の光を射出する機能を有する構成とすることができる。又は、図２に示す複数の画素２５は、それぞれ、赤色（Ｒ）、緑色（Ｇ）、青色（Ｂ）、又は白色（Ｗ）の光を射出する機能を有する構成とすることができる。このように、異なる色の光を射出することができる画素２５を画素部２１Ａ及び画素部２１Ｂに設けることにより、フルカラーの表示を行うことができる。なお、異なる色の光を射出することができる画素２５を画素部２１Ａ及び画素部２１Ｂに設けた場合、画素２５を副画素ということができる。 Each of the plurality of pixels 25 illustrated in FIG. 2 can have a function of emitting light of red (R), green (G), or blue (B). Alternatively, each of the plurality of pixels 25 illustrated in FIG. 2 can have a function of emitting light of red (R), green (G), blue (B), or white (W). As described above, by providing the pixels 25 capable of emitting light of different colors in the pixel portion 21A and the pixel portion 21B, full-color display can be performed. Note that when the pixels 25 capable of emitting light of different colors are provided in the pixel portion 21A and the pixel portion 21B, the pixels 25 can be referred to as sub-pixels.
ここで、表示パネルＤＰが、画素部２１を囲むように非表示領域を有する場合を考える。このとき、例えば、複数の表示パネルＤＰの出力画像を合わせて一つの画像を表示すると、当該一つの画像は、表示装置１０Ａの使用者にとって分離したように視認されてしまう。 Here, it is assumed that the display panel DP has a non-display area so as to surround the pixel unit 21. At this time, for example, when one image is displayed by combining output images of a plurality of display panels DP, the one image is visually perceived as separated by the user of the display device 10A.
表示パネルＤＰの非表示領域を狭くする（狭額縁な表示パネルＤＰを用いる）ことで、各表示パネルＤＰの表示が分離して見えることを抑制できるが、表示パネルＤＰの非表示領域を完全になくすことは困難である。 By narrowing the non-display area of the display panel DP (using the narrow frame display panel DP), it can be suppressed that the display of each display panel DP appears to be separated, but the non-display area of the display panel DP is completely It is difficult to eliminate.
また、表示パネルＤＰの非表示領域の面積が狭いと、表示パネルＤＰの端部と表示パネルＤＰ内の素子との距離が短くなり、表示パネルＤＰの外部から侵入する不純物によって、素子が劣化しやすくなる場合がある。 In addition, when the area of the non-display area of the display panel DP is narrow, the distance between the end of the display panel DP and the element in the display panel DP becomes short, and the element is degraded by impurities entering from the outside of the display panel DP. It may be easier.
そこで、本発明の一態様では、複数の表示パネルＤＰの一部が重なるように配置する。重ねた２つの表示パネルＤＰのうち、少なくとも表示面側（上側）に位置する表示パネルＤＰは、可視光を透過する領域を画素部２１と隣接して有する。本発明の一態様では、下側に配置される表示パネルＤＰの画素部２１と、上側に配置される表示パネルＤＰの可視光を透過する領域とが重なる。したがって、重ねた２つの表示パネルＤＰの画素部２１の間の非表示領域を縮小すること、さらには無くすことができる。これにより、使用者から表示パネルＤＰのつなぎ目が認識されにくい、大型の表示部２０Ａを実現することができる。 Thus, in one embodiment of the present invention, a plurality of display panels DP are arranged so as to overlap with each other. The display panel DP positioned at least on the display surface side (upper side) of the two superimposed display panels DP has a region transmitting visible light adjacent to the pixel portion 21. In one embodiment of the present invention, the pixel portion 21 of the display panel DP disposed on the lower side and the region transmitting visible light of the display panel DP disposed on the upper side overlap with each other. Therefore, the non-display area between the pixel portions 21 of the two overlapped display panels DP can be reduced or eliminated. As a result, it is possible to realize a large display unit 20A in which the user can not easily recognize the joints of the display panel DP.
上側に位置する表示パネルＤＰの非表示領域の少なくとも一部は、可視光を透過する領域であり、下側に位置する表示パネルＤＰの画素部２１と重ねることができる。また、下側に位置する表示パネルＤＰの非表示領域の少なくとも一部は、上側に位置する表示パネルＤＰの画素部２１、又は可視光を遮る領域と重ねることができる。これらの部分については、表示部２０Ａの狭額縁化（画素部以外の面積の縮小化）に影響しないため、面積の縮小化をしなくてもよい。 At least a part of the non-display area of the display panel DP located on the upper side is an area that transmits visible light, and can overlap with the pixel portion 21 of the display panel DP located on the lower side. In addition, at least a part of the non-display area of the display panel DP located on the lower side can be overlapped with the pixel portion 21 of the display panel DP located on the upper side or an area that blocks visible light. In these parts, since the narrowing of the frame (reduction of the area other than the pixel part) of the display unit 20A is not affected, the area may not be reduced.
表示パネルＤＰの非表示領域が広いと、表示パネルＤＰの端部と表示パネルＤＰ内の素子との距離が長くなり、表示パネルＤＰの外部から侵入する不純物によって、素子が劣化することを抑制できる。例えば、表示素子として有機ＥＬ素子を用いる場合は、表示パネルＤＰの端部と有機ＥＬ素子との距離を長くするほど、表示パネルＤＰの外部から水分又は酸素等の不純物が有機ＥＬ素子に侵入しにくくなる（又は到達しにくくなる）。本発明の一態様の表示装置では、表示パネルＤＰの非表示領域の面積を十分に確保できるため、有機ＥＬ素子等を用いた表示パネルＤＰを適用しても、信頼性が高い大型の表示部２０Ａを実現できる。 When the non-display area of the display panel DP is wide, the distance between the end of the display panel DP and the element in the display panel DP becomes long, and deterioration of the element by impurities entering from the outside of the display panel DP can be suppressed . For example, in the case of using an organic EL element as a display element, as the distance between the end portion of the display panel DP and the organic EL element is increased, impurities such as moisture or oxygen penetrate the organic EL element from the outside of the display panel DP. It becomes difficult (or hard to reach). In the display device according to one embodiment of the present invention, the area of the non-display region of the display panel DP can be sufficiently ensured, and therefore, a large display portion with high reliability can be obtained even if the display panel DP using an organic EL element or the like is applied 20A can be realized.
このように、表示部２０Ａに複数の表示パネルＤＰが設けられる場合、隣接する表示パネルＤＰ間において画素部２１が連続するように、複数の表示パネルＤＰが配置されることが好ましい。 Thus, when a plurality of display panels DP are provided in the display unit 20A, it is preferable that the plurality of display panels DP be arranged such that the pixel units 21 are continuous between the adjacent display panels DP.
図３（Ａ）に、表示パネルＤＰの構成例を示し、図３（Ｂ）に表示パネルＤＰの配置例を示す。 FIG. 3A shows a configuration example of the display panel DP, and FIG. 3B shows an arrangement example of the display panel DP.
図３（Ａ）に示す表示パネルＤＰは、画素部２１、可視光を透過する領域７２、及び可視光を遮る領域７３を有する。可視光を透過する領域７２及び可視光を遮る領域７３は、それぞれ、画素部２１と隣接して設けられる。図３（Ａ）では、表示パネルＤＰにＦＰＣ（Ｆｌｅｘｉｂｌｅ　Ｐｒｉｎｔｅｄ　Ｃｉｒｃｕｉｔ）７４が設けられている例を示す。 The display panel DP illustrated in FIG. 3A includes the pixel portion 21, a region 72 which transmits visible light, and a region 73 which blocks visible light. The region 72 transmitting visible light and the region 73 blocking visible light are provided adjacent to the pixel portion 21 respectively. FIG. 3A shows an example in which a flexible printed circuit (FPC) 74 is provided on the display panel DP.
図２に示すように、画素部２１には、複数の画素２５が含まれる。可視光を透過する領域７２には、表示パネルＤＰを構成する一対の基板、及び当該一対の基板に挟持された表示素子を封止するための封止材等が設けられていてもよい。このとき、可視光を透過する領域７２に設けられる部材には、可視光に対して透光性を有する材料を用いる。可視光を遮る領域７３には、画素部２１に含まれる画素２５と電気的に接続された配線等が設けられていてもよい。また、可視光を遮る領域７３には、走査線駆動回路２２及び信号線駆動回路２３の一方又は双方が設けられていてもよい。また、可視光を遮る領域７３には、ＦＰＣ７４と接続された端子、当該端子と接続された配線等が設けられていてもよい。 As shown in FIG. 2, the pixel unit 21 includes a plurality of pixels 25. The region 72 which transmits visible light may be provided with a pair of substrates constituting the display panel DP, a sealing material for sealing a display element held between the pair of substrates, and the like. At this time, as a member provided in the region 72 which transmits visible light, a material having transparency to visible light is used. In the area 73 for blocking visible light, a wire or the like electrically connected to the pixel 25 included in the pixel unit 21 may be provided. Further, one or both of the scanning line drive circuit 22 and the signal line drive circuit 23 may be provided in the area 73 for blocking visible light. Further, in the region 73 for blocking visible light, a terminal connected to the FPC 74, a wire connected to the terminal, or the like may be provided.
図３（Ｂ）は、図３（Ａ）に示す表示パネルＤＰを、縦方向（行方向）に２つ配置した例であり、表示パネルＤＰの表示面側の斜視図である。 FIG. 3B is an example in which two display panels DP shown in FIG. 3A are arranged in the vertical direction (row direction), and is a perspective view of the display surface side of the display panel DP.
２つの表示パネルＤＰ（表示パネルＤＰ［１，１］及び表示パネルＤＰ［２，１］）は、互いに重なる領域を有するように配置されている。具体的には、表示パネルＤＰ［２，１］が有する可視光を透過する領域７２が、画素部２１Ａの上（表示面側）に重畳するように配置されている。これにより、画素部２１Ａ及び画素部２１Ｂがほぼつなぎ目なく配置された領域を表示部２０Ａの表示領域２９とすることができる。 The two display panels DP (display panel DP [1, 1] and display panel DP [2, 1]) are arranged so as to have overlapping regions. Specifically, a region 72 transmitting visible light included in the display panel DP [2, 1] is disposed so as to overlap on the pixel portion 21A (display surface side). Thereby, the area where the pixel portion 21A and the pixel portion 21B are arranged substantially without a seam can be set as the display area 29 of the display portion 20A.
ここで、表示パネルＤＰは、可撓性を有していることが好ましい。例えば、表示パネルＤＰを構成する一対の基板は可撓性を有することが好ましい。これにより、画素部２１Ｂにおける上面の高さを、画素部２１Ａにおける上面の高さと一致するように、表示パネルＤＰ［２，１］を緩やかに湾曲させることができる。そのため、表示パネルＤＰ［１，１］と表示パネルＤＰ［２，１］とが重なる領域近傍を除き、各表示領域の高さを揃えることが可能で、表示領域２９に表示する画像の表示品位を高めることができる。 Here, the display panel DP preferably has flexibility. For example, the pair of substrates that constitute the display panel DP preferably has flexibility. As a result, the display panel DP [2, 1] can be gently curved so that the height of the upper surface of the pixel section 21B matches the height of the upper surface of the pixel section 21A. Therefore, it is possible to make the heights of the display areas uniform except in the vicinity of the area where the display panel DP [1, 1] and the display panel DP [2, 1] overlap, and the display quality of the image displayed in the display area 29 Can be enhanced.
なお、隣接する２つの表示パネルＤＰ間の段差を軽減するため、表示パネルＤＰの厚さは薄いことが好ましい。例えば、表示パネルＤＰの厚さは、１ｍｍ以下が好ましく、３００μｍ以下はより好ましく、１００μｍ以下がさらに好ましい。 Note that the thickness of the display panel DP is preferably thin in order to reduce a step between the two adjacent display panels DP. For example, the thickness of the display panel DP is preferably 1 mm or less, more preferably 300 μm or less, and still more preferably 100 μm or less.
図４（Ａ）に示すように、表示部２０Ａには、表示パネルＤＰが隣接する領域、すなわち表示パネルＤＰのつなぎ目の領域（図中の領域Ｓ）が存在する。複数の表示パネルＤＰを用いて画像を表示する際、領域Ｓにおける画像の連続性が確保されることが好ましい。 As shown in FIG. 4A, in the display unit 20A, an area where the display panel DP is adjacent, that is, an area (joint area S in the drawing) of the joint of the display panel DP exists. When displaying an image using several display panel DP, it is preferable that the continuity of the image in the area | region S is ensured.
しかしながら、画素２５が有するトランジスタの特性又は容量素子のサイズ、信号線ＳＬの寄生抵抗又は寄生容量、信号線駆動回路２３の駆動能力等は、表示パネルＤＰごとにばらつきが生じ得る。そのため、画像信号が各表示パネルＤＰに供給された際、表示パネルＤＰごとに表示画像に誤差が生じ、これによりつなぎ目の領域において画像が不連続になり得る。また、図３（Ｂ）に示すように、１つの表示パネルＤＰの画素部２１が他の表示パネルＤＰの可視光を透過する領域７２と重なる領域を有する場合、つなぎ目の領域においては画素部２１に表示された画像が可視光を透過する領域７２を介して視認されるため、階調に誤差が生じ得る。よって、処理部３３によって生成された第１の画像データＳＤ１をそのまま分割したデータ（第１の画像データＳＤ１［１，１］及び第１の画像データＳＤ１［２，１］）を各表示パネルＤＰに供給すると、図４（Ｂ）に示すように、領域Ｓにおいて不連続な画像が視認され得る。 However, the characteristics of the transistor of the pixel 25 or the size of the capacitive element, the parasitic resistance or parasitic capacitance of the signal line SL, the drive capability of the signal line drive circuit 23, and the like may vary among the display panels DP. Therefore, when the image signal is supplied to each display panel DP, an error occurs in the display image for each display panel DP, and the image may be discontinuous in the area of the joint. Further, as shown in FIG. 3B, in the case where the pixel portion 21 of one display panel DP has a region overlapping with the region 72 which transmits visible light of the other display panel DP, the pixel portion 21 is formed in the joint region. Because the image displayed on the display is viewed through the area 72 that transmits visible light, an error may occur in gradation. Accordingly, data (first image data SD1 [1,1] and first image data SD1 [2,1]) obtained by dividing the first image data SD1 generated by the processing unit 33 as it is is displayed on each display panel DP. , The discontinuous image can be viewed in the area S, as shown in FIG. 4 (B).
ここで、表示装置１０Ａが有する処理部４０Ａは、２つの表示パネルＤＰのつなぎ目における画像の不連続性が緩和されるように、第１の画像データＳＤ１を補正することができる。これにより、複数の表示パネルＤＰを用いて表示部２０Ａを構成する場合に、表示パネルＤＰのつなぎ目において画像の乱れを視認されにくくできる。また、表示パネルごとの色調のずれ、例えば表示パネルＤＰ［１，１］に表示される画像の色調と、表示パネルＤＰ［２，１］に表示される画像の色調と、のずれを小さくすることができる。以上により、表示品位を高めることができる。 Here, the processing unit 40A of the display device 10A can correct the first image data SD1 so as to alleviate the discontinuity of the image at the joint of the two display panels DP. As a result, when the display unit 20A is configured using a plurality of display panels DP, it is possible to make visual disturbances in the joints of the display panels DP less visible. In addition, the difference between the color tone of each display panel, for example, the difference between the color tone of the image displayed on the display panel DP [1, 1] and the color tone of the image displayed on the display panel DP [2, 1] be able to. Thus, the display quality can be improved.
＜１−２．表示装置の動作方法の一例１＞
次に、表示装置１０Ａの動作方法の一例について説明する。図５（Ａ）、（Ｂ）は、表示パネルＤＰのつなぎ目における画像の不連続性を緩和するために用いられる、補正フィルタの作成方法を説明するフローチャートである。 <1-2. Example of operation method of display device 1>
Next, an example of an operation method of the display device 10A will be described. FIGS. 5A and 5B are flowcharts illustrating a method of creating a correction filter used to reduce image discontinuity at the joint of the display panel DP.
図５（Ａ）に示す動作方法の一例について説明する。まず、処理部４０Ａが、表示パネルＤＰ［１，１］に表示される画像に対応する画像データを補正するために用いる補正フィルタ、及び表示パネルＤＰ［２，１］に表示される画像に対応する画像データを補正するために用いる補正フィルタを作成する（ステップＳ０１）。ここで、本明細書等において、表示パネルＤＰ［１，１］に表示される画像に対応する画像データを補正するために用いる補正フィルタを、第１の補正フィルタという。また、表示パネルＤＰ［２，１］に表示される画像に対応する画像データを補正するために用いる補正フィルタを、第２の補正フィルタという。 An example of the operation method illustrated in FIG. 5A will be described. First, the processing unit 40A supports the correction filter used to correct the image data corresponding to the image displayed on the display panel DP [1, 1] and the image displayed on the display panel DP [2, 1]. A correction filter used to correct image data to be corrected is created (step S01). Here, in the present specification and the like, a correction filter used to correct image data corresponding to an image displayed on the display panel DP [1, 1] is referred to as a first correction filter. Further, a correction filter used to correct image data corresponding to an image displayed on the display panel DP [2, 1] is referred to as a second correction filter.
第１の補正フィルタは、例えば、表示パネルＤＰ［１，１］に表示される画像の表示ムラを軽減するための補正フィルタとすることができる。第２の補正フィルタは、例えば、表示パネルＤＰ［２，１］に表示される画像の表示ムラを軽減するための補正フィルタとすることができる。第１の補正フィルタ及び第２の補正フィルタの作成方法の詳細については後述するが、第１の補正フィルタは、例えば特定の階調値の画像を表示パネルＤＰ［１，１］に表示した際に画素２５から射出される光の輝度の、画素２５間のばらつきが小さくなるように作成することができる。また、第２の補正フィルタは、例えば特定の階調値の画像を表示パネルＤＰ［２，１］に表示した際に画素２５から射出される光の輝度の、画素２５間のばらつきが小さくなるように作成することができる。 The first correction filter can be, for example, a correction filter for reducing display unevenness of an image displayed on the display panel DP [1, 1]. The second correction filter can be, for example, a correction filter for reducing display unevenness of an image displayed on the display panel DP [2, 1]. The details of the method of creating the first correction filter and the second correction filter will be described later, but when the first correction filter displays an image of a specific tone value, for example, on the display panel DP [1, 1] The variation in the brightness of light emitted from the pixel 25 between the pixels 25 can be reduced. In addition, the second correction filter, for example, reduces variation among the pixels 25 in the luminance of light emitted from the pixels 25 when an image of a specific gradation value is displayed on the display panel DP [2, 1]. Can be created as
本明細書等において、特定の階調値の画像とは、例えば全ての画素の階調値が等しい画像を示す。 In the present specification and the like, an image of a specific tone value indicates, for example, an image in which the tone values of all pixels are equal.
ここで、画素から射出される光の輝度の画素間のばらつきは、中間階調の画像を表示する場合に大きくなることが多い。よって、特定の階調値の画像として、全ての画素２５の階調値が等しい画像とする場合、例えば、全ての画素２５の階調値が中間階調である画像とすることが好ましい。例えば、画素２５が表現可能な階調値が０乃至２５５である場合は、全ての画素２５の階調値が１２７又はその近傍である画像とすることが好ましい。例えば、全面灰色の画像であることが好ましい。 Here, the inter-pixel variation of the luminance of light emitted from the pixel often becomes large when displaying an image of intermediate gradation. Therefore, in the case where an image having a specific gradation value is to be an image in which the gradation values of all the pixels 25 are equal, for example, it is preferable to set an image in which the gradation values of all the pixels 25 are intermediate gradations. For example, when the gradation value that can be expressed by the pixel 25 is 0 to 255, it is preferable to set an image in which the gradation value of all the pixels 25 is 127 or near. For example, it is preferable that it is a full gray image.
第１の補正フィルタは、例えば、表示パネルＤＰ［１，１］が有する画素２５から射出される光の輝度の、画素２５毎の補正強度を表すデータを有する。第２の補正フィルタは、例えば、表示パネルＤＰ［２，１］が有する画素２５から射出される光の輝度の、画素２５毎の補正強度を表すデータを有する。なお、本明細書等において、補正フィルタが有するデータが表す、補正強度等の値をフィルタ値という。第１の補正フィルタは、例えば、表示パネルＤＰ［１，１］に設けられた画素２５の画素数と同数のフィルタ値を有すると言うことができる。第２の補正フィルタは、例えば、表示パネルＤＰ［２，１］に設けられた画素２５の画素数と同数のフィルタ値を有すると言うことができる。 The first correction filter has, for example, data representing a correction intensity for each pixel 25 of the luminance of the light emitted from the pixel 25 of the display panel DP [1, 1]. The second correction filter has, for example, data representing the correction intensity for each pixel 25 of the luminance of light emitted from the pixel 25 of the display panel DP [2, 1]. In the present specification and the like, values such as correction strength represented by data of the correction filter are referred to as filter values. The first correction filter can be said to have filter values equal in number to the number of pixels of the pixels 25 provided in the display panel DP [1, 1], for example. The second correction filter can be said to have filter values equal in number to the number of pixels of the pixels 25 provided in the display panel DP [2, 1], for example.
次に、特定の階調値の画像に対応する画像データに対して、処理部４０Ａが第１の補正フィルタを用いて補正を行い、補正後の画像データに対応する画像を表示パネルＤＰ［１，１］に表示する。また、特定の階調値の画像に対応する画像データに対して、処理部４０Ａが第２の補正フィルタを用いて補正を行い、補正後の画像データに対応する画像を表示パネルＤＰ［２，１］に表示する。その後、境界部２８Ａ及び境界部２８Ｂに設けられた画素２５から射出される光の輝度を、二次元輝度計等を用いて測定する（ステップＳ０２）。 Next, the processing unit 40A corrects the image data corresponding to the image of the specific tone value using the first correction filter, and the image corresponding to the corrected image data is displayed on the display panel DP [1 , 1]. Further, the processing unit 40A corrects the image data corresponding to the image of the specific tone value using the second correction filter, and the image corresponding to the image data after the correction is displayed on the display panel DP [2,, Displayed in 1]. Thereafter, the brightness of light emitted from the pixels 25 provided in the boundary portion 28A and the boundary portion 28B is measured using a two-dimensional luminance meter or the like (step S02).
次に、境界部２８Ａに設けられた画素２５から射出される光の輝度と、境界部２８Ｂに設けられた画素２５から射出される光の輝度と、を比較する（ステップＳ０３）。例えば、境界部２８Ａに設けられた画素２５から射出される光の輝度の平均値と、境界部２８Ｂに設けられた画素２５から射出される光の輝度の平均値と、を比較する。 Next, the brightness of light emitted from the pixel 25 provided in the boundary portion 28A is compared with the brightness of light emitted from the pixel 25 provided in the boundary portion 28B (step S03). For example, the average value of the luminances of light emitted from the pixels 25 provided in the boundary portion 28A is compared with the average value of the luminances of light emitted from the pixels 25 provided in the boundary portion 28B.
その後、比較結果を基に、処理部４０Ａが、補正フィルタを修正する（ステップＳ０４）。例えば、境界部２８Ａに設けられた画素２５から射出される光の輝度の平均値をＬＡ、境界部２８Ｂに設けられた画素２５から射出される光の輝度の平均値をＬＢとする場合、画素部２１Ｂに設けられた画素２５から射出される光の輝度をＬＡ／ＬＢ倍するように、第２の補正フィルタを修正する。又は、例えば画素部２１Ａに設けられた画素２５から射出される光の輝度をＬＢ／ＬＡ倍するように、第１の補正フィルタを修正する。又は、例えば画素部２１Ａに設けられた画素２５から射出される光の輝度を（ＬＡ＋ＬＢ）／２ＬＡ倍するように第１の補正フィルタを修正し、画素部２１Ｂに設けられた画素２５から射出される光の輝度を（ＬＡ＋ＬＢ）／２ＬＢ倍するように第２の補正フィルタを修正する。以上により、新たな補正フィルタが作成される。以上が表示装置１０Ａで用いられる補正フィルタの作成方法の一例である。 Thereafter, based on the comparison result, the processing unit 40A corrects the correction filter (step S04). For example, when an average value of luminances of light emitted from the pixels 25 provided in the boundary portion 28A is L A , and an average value of luminances of light emitted from the pixels 25 provided in the boundary portion 28B is L B The second correction filter is corrected such that the luminance of light emitted from the pixel 25 provided in the pixel unit 21B is multiplied by L A / L B. Alternatively, for example, the first correction filter is corrected such that the luminance of light emitted from the pixel 25 provided in the pixel unit 21A is multiplied by L B / L A. Or, for example, the brightness of light emitted from the pixel 25 in the pixel portion 21A (L A + L B) / 2L A modifies the first correction filter as multiplying the pixels provided in the pixel portion 21B The second correction filter is corrected so as to multiply the luminance of the light emitted from 25 by (L A + L B ) / 2L B. Thus, a new correction filter is created. The above is an example of the method of creating the correction filter used in the display device 10A.
なお、上記では、画素部２１Ａ及び／又は画素部２１Ｂに設けられた全ての画素２５から射出される光の輝度に対して上記比較結果に基づいた補正を行うように補正フィルタを修正する場合について示したが、本発明の一態様はこれに限らない。例えば、境界部２８Ａ及び／又は境界部２８Ｂに設けられた画素２５から射出される光の輝度について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。例えば、境界部２８Ａ及び／又は境界部２８Ｂに設けられた画素２５の全てと、それ以外の領域に設けられた画素２５の一部と、から射出される光の輝度について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。例えば、図３（Ｂ）に示すように、領域７２と重なる領域に設けられた画素２５から射出される光の輝度について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。 In the above description, the correction filter is corrected to correct the luminance of light emitted from all the pixels 25 provided in the pixel unit 21A and / or the pixel unit 21B based on the comparison result. Although shown, one embodiment of the present invention is not limited thereto. For example, the correction filter may be modified to correct the luminance of the light emitted from the pixel 25 provided in the boundary portion 28A and / or the boundary portion 28B based on the comparison result. For example, the luminance of light emitted from all of the pixels 25 provided in the boundary portion 28A and / or the boundary portion 28B and a part of the pixels 25 provided in the other region is based on the above comparison result. The correction filter may be corrected to perform the correction. For example, as shown in FIG. 3B, even if the correction filter is corrected so as to correct the luminance of light emitted from the pixel 25 provided in the area overlapping with the area 72 based on the comparison result. Good.
図５（Ｂ）に示す動作方法の一例について説明する。まず、図５（Ａ）に示すステップＳ０１と同様に、処理部４０Ａが、第１の補正フィルタ及び第２の補正フィルタを作成する（ステップＳ１１）。 An example of the operation method illustrated in FIG. 5B will be described. First, as in step S01 shown in FIG. 5A, the processing unit 40A creates a first correction filter and a second correction filter (step S11).
次に、第１の補正フィルタが有する、境界部２８Ａに設けられた画素２５に対応するフィルタ値と、第２の補正フィルタが有する、境界部２８Ｂに設けられた画素２５に対応するフィルタ値と、を比較する（ステップＳ１２）。例えば、境界部２８Ａに設けられた画素２５に対応するフィルタ値の平均値と、境界部２８Ｂに設けられた画素２５に対応するフィルタ値の平均値と、を比較する。 Next, a filter value corresponding to the pixel 25 provided in the boundary portion 28A, which the first correction filter has, and a filter value corresponding to the pixel 25 provided in the boundary portion 28B, which the second correction filter has , (Step S12). For example, the average value of the filter values corresponding to the pixels 25 provided in the boundary portion 28A is compared with the average value of the filter values corresponding to the pixels 25 provided in the boundary portion 28B.
その後、図５（Ａ）に示すステップＳ０４と同様に、比較結果を基に、補正フィルタを修正する。例えば、境界部２８Ａに設けられた画素２５に対応するフィルタ値の平均値をＤＡ、境界部２８Ｂに設けられた画素２５に対応するフィルタ値の平均値をＤＢとする場合、第２の補正フィルタが有するフィルタ値をそれぞれＤＡ／ＤＢ倍するように、第２の補正フィルタを修正する。又は、例えば第１の補正フィルタが有するフィルタ値をそれぞれＤＢ／ＤＡ倍するように、第１の補正フィルタを修正する。又は、例えば第１の補正フィルタが有するフィルタ値をそれぞれ（ＤＡ＋ＤＢ）／２ＤＡ倍するように第１の補正フィルタを修正し、第２の補正フィルタが有するフィルタ値をそれぞれ（ＤＡ＋ＤＢ）／２ＤＢ倍するように第２の補正フィルタを修正する。以上により、新たな補正フィルタが作成される。以上が表示装置１０Ａで用いられる補正フィルタの作成方法の一例である。 Thereafter, as in step S04 shown in FIG. 5A, the correction filter is corrected based on the comparison result. For example, the average value of the filter value corresponding to the pixel 25 provided in the boundary portion 28A D A, the average value of the filter value corresponding to the pixel 25 provided in the boundary portion 28B if a D B, of the second The second correction filter is corrected such that the filter values of the correction filter are multiplied by D A / D B respectively. Alternatively, the first correction filter is corrected so that, for example, the filter values of the first correction filter are multiplied by D B / D A , respectively. Alternatively, for example, the first correction filter is corrected so that the filter value of the first correction filter is multiplied by (D A + D B ) / 2D A , respectively, and the filter value of the second correction filter is changed to (D A Correct the second correction filter so as to multiply + D B ) / 2D B. Thus, a new correction filter is created. The above is an example of the method of creating the correction filter used in the display device 10A.
なお、上記では、画素部２１Ａ及び／又は画素部２１Ｂに設けられた全ての画素２５に対応するフィルタ値について、上記比較結果に基づいた補正を行うように補正フィルタを修正する場合について示したが、本発明の一態様はこれに限らない。例えば、境界部２８Ａ及び／又は境界部２８Ｂに設けられた画素２５に対応するフィルタ値について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。例えば、境界部２８Ａ及び／又は境界部２８Ｂに設けられた画素２５の全てと、それ以外の領域に設けられた画素２５の一部と、に対応するフィルタ値について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。例えば、図３（Ｂ）に示すように、領域７２と重なる領域に設けられた画素２５に対応するフィルタ値について、上記比較結果に基づいた補正を行うように補正フィルタを修正してもよい。 In the above description, the correction filter is corrected to perform correction based on the comparison result for filter values corresponding to all the pixels 25 provided in the pixel unit 21A and / or the pixel unit 21B. One aspect of the present invention is not limited to this. For example, the correction filter may be modified to perform correction based on the comparison result for the filter value corresponding to the pixel 25 provided in the boundary portion 28A and / or the boundary portion 28B. For example, correction based on the comparison result for filter values corresponding to all of the pixels 25 provided in the boundary portion 28A and / or the boundary portion 28B and a part of the pixels 25 provided in the other region The correction filter may be modified to For example, as shown in FIG. 3B, the correction filter may be modified so that correction based on the comparison result is performed on the filter value corresponding to the pixel 25 provided in the area overlapping with the area 72.
図５（Ａ）、（Ｂ）に示す方法により新たな補正フィルタを作成した後、さらに当該補正フィルタを修正し、画素２５ごとに補正強度を調整してもよい。例えば、画素部２１Ａに設けられた画素２５のうち、境界部２８Ａの外部に設けられた画素２５についての補正強度を、境界部２８Ａに設けられた画素２５についての補正強度より弱くしてもよい。また、例えば、画素部２１Ｂに設けられた画素２５のうち、境界部２８Ｂの外部に設けられた画素２５についての補正強度を、境界部２８Ｂに設けられた画素２５についての補正強度より弱くしてもよい。 After creating a new correction filter by the method shown in FIGS. 5A and 5B, the correction filter may be further modified to adjust the correction intensity for each pixel 25. For example, among the pixels 25 provided in the pixel unit 21A, the correction intensity for the pixels 25 provided outside the boundary 28A may be weaker than the correction intensity for the pixels 25 provided in the boundary 28A. . Also, for example, among the pixels 25 provided in the pixel unit 21B, the correction intensity for the pixel 25 provided outside the boundary portion 28B is weaker than the correction intensity for the pixel 25 provided in the boundary portion 28B. It is also good.
上記方法により新たな補正フィルタを作成した後、処理部４０Ａが、例えば外部から入力される信号に対応する第１の画像データＳＤ１を補正フィルタにより補正して、第２の画像データＳＤ２を生成する。次に、分割部４５Ａが、第２の画像データＳＤ２を、表示パネルＤＰ［１，１］に表示される画像に対応する画像データＳＤ２［１，１］、及び表示パネルＤＰ［２，１］に表示される画像に対応する画像データＳＤ２［２，１］に分割する。その後、画像データＳＤ２［１，１］に対応する画像を画素部２１Ａに表示し、画像データＳＤ２［２，１］に対応する画像を画素部２１Ｂに表示する。以上が表示装置１０Ａの動作方法の一例である。 After creating a new correction filter by the above method, the processing unit 40A corrects, for example, the first image data SD1 corresponding to a signal input from the outside using the correction filter, and generates the second image data SD2. . Next, the dividing unit 45A converts the second image data SD2 into image data SD2 [1,1] corresponding to an image displayed on the display panel DP [1,1], and the display panel DP [2,1]. Is divided into image data SD2 [2, 1] corresponding to the image displayed on Thereafter, an image corresponding to the image data SD2 [1,1] is displayed on the pixel unit 21A, and an image corresponding to the image data SD2 [2,1] is displayed on the pixel unit 21B. The above is an example of the operation method of the display device 10A.
なお、処理部４０Ａが新たな補正フィルタを作成した後、当該補正フィルタをさらに修正してもよい。例えば、図５（Ａ）、（Ｂ）に示す方法で作成した補正フィルタによっては除去することが難しいノイズを除去できるように、補正フィルタを修正してもよい。例えば、画素落ち等の欠陥を視認しづらくするように、補正フィルタを修正してもよい。例えば、処理部３３で行うことができる画像処理と同様の処理を行えるように、補正フィルタを修正してもよい。補正フィルタの修正は、例えば図５（Ａ）、（Ｂ）に示す方法で作成した補正フィルタに、平滑化フィルタとしての機能を持たせるように行うことができる。これにより、本発明の一態様の表示装置の表示品位をさらに高めることができる。 In addition, after the processing unit 40A creates a new correction filter, the correction filter may be further corrected. For example, the correction filter may be modified so as to remove noise that is difficult to remove depending on the correction filter created by the method shown in FIGS. 5A and 5B. For example, the correction filter may be modified to make it difficult to visually recognize a defect such as a pixel drop. For example, the correction filter may be modified so that the same processing as the image processing that can be performed by the processing unit 33 can be performed. The correction filter can be corrected, for example, so that the correction filter created by the method shown in FIGS. 5A and 5B has a function as a smoothing filter. Accordingly, the display quality of the display device of one embodiment of the present invention can be further enhanced.
なお、上記補正フィルタの修正は、例えばステップＳ０１とステップＳ０２の間、及びステップＳ１１とステップＳ１２の間に行ってもよい。また、処理部４０Ａが新たな補正フィルタを作成した後、当該補正フィルタをさらに修正する場合、処理部３３を省略することができる。 The correction of the correction filter may be performed, for example, between step S01 and step S02 and between step S11 and step S12. In addition, after the processing unit 40A creates a new correction filter, when the correction filter is further corrected, the processing unit 33 can be omitted.
図５（Ａ）、（Ｂ）に示す方法で新たな補正フィルタを作成した後に画像を表示することにより、表示パネルＤＰのつなぎ目において画像の乱れを視認されにくくできる。また、表示パネルＤＰ［１，１］に表示される画像の色調と、表示パネルＤＰ［２，１］に表示される画像の色調と、のずれを小さくすることができる。以上により、表示品位を高めることができる。 By displaying an image after creating a new correction filter by the method shown in FIGS. 5A and 5B, it is possible to make visual disturbance of the image less noticeable at the joints of the display panel DP. Further, it is possible to reduce the deviation between the color tone of the image displayed on the display panel DP [1, 1] and the color tone of the image displayed on the display panel DP [2, 1]. Thus, the display quality can be improved.
図１乃至図５に示す構成及び動作は、２つの表示パネルＤＰが横方向（列方向）に並んでいる、例えば、表示部２０Ａに表示パネルＤＰ［１，１］及び表示パネルＤＰ［１，２］が設けられている場合であっても適用することができる。この場合、例えば、「行」という用語を「列」と、「ｍ行目」という用語を「ｎ列目」と、「表示パネルＤＰ［２，１］」という用語を「表示パネルＤＰ［１，２］」と適宜言い換えるものとする。 The configuration and operation shown in FIGS. 1 to 5 have two display panels DP aligned in the horizontal direction (column direction). For example, in the display unit 20A, the display panel DP [1,1] and the display panel DP [1,1 Even when 2] is provided, it is applicable. In this case, for example, the term “row” is “column”, the term “m line” is “n column”, and the term “display panel DP [2,1]” is “display panel DP [1 , 2]] and rephrased accordingly.
次に、表示部２０Ａに表示パネルＤＰが２行２列に並べられた場合における、補正フィルタの作成方法の一例について説明する。図６（Ａ）、（Ｂ）、（Ｃ）は、補正フィルタの作成方法の一例を示す模式図であり、（Ａ）、（Ｂ）、（Ｃ）の順に動作が進行する。 Next, an example of a method of creating a correction filter in the case where the display panels DP are arranged in two rows and two columns in the display unit 20A will be described. FIGS. 6A, 6B, and 6C are schematic views showing an example of a method of creating a correction filter, and the operation proceeds in the order of (A), (B), and (C).
図６（Ａ）、（Ｂ）、（Ｃ）には、２行２列の表示パネルＤＰとして、表示パネルＤＰ［１，１］、表示パネルＤＰ［２，１］、表示パネルＤＰ［１，２］、及び表示パネルＤＰ［２，２］を示す。図６（Ａ）において、表示パネルＤＰ［１，１］の、表示パネルＤＰ［２，１］との境界部を境界部２８Ａとする。また、表示パネルＤＰ［２，１］の、表示パネルＤＰ［１，１］との境界部を境界部２８Ｂとする。また、表示パネルＤＰ［１，２］の、表示パネルＤＰ［２，２］との境界部を境界部２８Ｃとする。また、表示パネルＤＰ［２，２］の、表示パネルＤＰ［１，２］との境界部を境界部２８Ｄとする。 In FIGS. 6A, 6B, and 6C, the display panel DP [1, 1], the display panel DP [2, 1], and the display panel DP [1, 1] are used as the display panel DP of 2 rows and 2 columns. 2] and a display panel DP [2, 2]. In FIG. 6A, the boundary between the display panel DP [1,1] and the display panel DP [2,1] is referred to as a boundary 28A. Further, the boundary between the display panel DP [2, 1] and the display panel DP [1, 1] is referred to as a boundary 28B. Further, the boundary between the display panel DP [1, 2] and the display panel DP [2, 2] is referred to as a boundary 28C. Further, the boundary between the display panel DP [2, 2] and the display panel DP [1, 2] is referred to as a boundary 28D.
また、図６（Ｂ）において、表示パネルＤＰ［１，１］の、表示パネルＤＰ［１，２］との境界部を境界部２９Ａとする。また、表示パネルＤＰ［２，１］の、表示パネルＤＰ［２，２］との境界部を境界部２９Ｂとする。また、表示パネルＤＰ［１，２］の、表示パネルＤＰ［１，１］との境界部を境界部２９Ｃとする。また、表示パネルＤＰ［２，２］の、表示パネルＤＰ［２，１］との境界部を境界部２９Ｄとする。 Further, in FIG. 6B, the boundary between the display panel DP [1, 1] and the display panel DP [1, 2] is referred to as a boundary 29A. Further, the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is referred to as a boundary 29B. Further, the boundary between the display panel DP [1, 2] and the display panel DP [1, 1] is referred to as a boundary 29C. Further, the boundary between the display panel DP [2, 2] and the display panel DP [2, 1] is referred to as a boundary 29D.
補正フィルタの作成の際には、まず、表示パネルＤＰ［１，１］及び表示パネルＤＰ［２，１］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。また、表示パネルＤＰ［１，２］及び表示パネルＤＰ［２，２］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。この際、図５（Ａ）に示すステップＳ０３において、境界部２８Ｃに設けられた画素２５から射出される光の輝度と、境界部２８Ｄに設けられた画素２５から射出される光の輝度と、を比較する。又は、図５（Ｂ）に示すステップＳ１２において、境界部２８Ｃに設けられた画素２５に対応するフィルタ値と、境界部２８Ｄに設けられた画素２５に対応するフィルタ値と、を比較する。以上により、表示パネルＤＰ［１，１］と表示パネルＤＰ［２，１］とのつなぎ目、及び表示パネルＤＰ［１，２］と表示パネルＤＰ［２，２］とのつなぎ目において、画像の不連続性が緩和される。 When creating the correction filter, first, the operation shown in FIG. 5A or 5B is performed on the display panel DP [1, 1] and the display panel DP [2, 1]. In addition, the operation illustrated in FIG. 5A or 5B is performed on the display panel DP [1, 2] and the display panel DP [2, 2]. Under the present circumstances, in step S03 shown to FIG. 5 (A), the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 28C, and the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 28D Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary portion 28C is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 28D. Thus, no image is formed at the joint between the display panel DP [1, 1] and the display panel DP [2, 1] and at the joint between the display panel DP [1, 2] and the display panel DP [2, 2]. Continuity is relaxed.
なお、境界部２８Ａ及び境界部２８Ｃに設けられた画素２５から射出される光の輝度を、境界部２８Ｂ及び境界部２８Ｄに設けられた画素２５から射出される光の輝度とまとめて比較してもよい。つまり、例えば境界部２８Ａに設けられる画素２５、及び境界部２８Ｃに設けられる画素２５から射出される光の輝度の平均値ＬＡＣを、境界部２８Ｂに設けられる画素２５、及び境界部２８Ｄに設けられる画素２５から射出される光の輝度の平均値ＬＢＤと比較してもよい。また、境界部２８Ａ及び境界部２８Ｃに設けられた画素２５に対応するフィルタ値を、境界部２８Ｂ及び境界部２８Ｄに設けられた画素２５に対応するフィルタ値とまとめて比較してもよい。つまり、例えば境界部２８Ａに設けられる画素２５、及び境界部２８Ｃに設けられる画素２５に対応するフィルタ値の平均値ＤＡＣを、境界部２８Ｂに設けられる画素２５、及び境界部２８Ｄに設けられる画素２５に対応するフィルタ値の平均値ＤＢＤと比較してもよい。 The luminance of light emitted from the pixels 25 provided in the boundary portion 28A and the boundary portion 28C is collectively compared with the luminance of light emitted from the pixels 25 provided in the boundary portion 28B and the boundary portion 28D. It is also good. That is, provided, for example pixels 25 provided in the boundary portion 28A, and the light emitted from the pixel 25 provided in the boundary portion 28C Average value L AC luminance pixels 25 provided in the boundary portion 28B, and the boundary portion 28D it may be compared with the average value L BD of the luminance of light emitted from the pixel 25 to be. The filter values corresponding to the pixels 25 provided in the boundary portion 28A and the boundary portion 28C may be collectively compared with the filter values corresponding to the pixels 25 provided in the boundary portion 28B and the boundary portion 28D. In other words, pixels to be provided, for example pixels 25 provided in the boundary portion 28A, and the average value D AC filter values corresponding to the pixels 25 provided in the boundary portion 28C, the pixels 25 provided in the boundary portion 28B, and the boundary portion 28D It may be compared with the average value D BD of the filter values corresponding to 25.
次に、表示パネルＤＰ［１，１］及び表示パネルＤＰ［１，２］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。この際、図５（Ａ）に示すステップＳ０３において、境界部２９Ａに設けられた画素２５から射出される光の輝度と、境界部２９Ｃに設けられた画素２５から射出される光の輝度と、を比較する。又は、図５（Ｂ）に示すステップＳ１２において、境界部２９Ａに設けられた画素２５に対応するフィルタ値と、境界部２９Ｃに設けられた画素２５に対応するフィルタ値と、を比較する。 Next, the operation shown in FIG. 5A or 5B is performed on the display panel DP [1,1] and the display panel DP [1,2]. At this time, in step S03 shown in FIG. 5A, the luminance of the light emitted from the pixel 25 provided in the boundary portion 29A and the luminance of the light emitted from the pixel 25 provided in the boundary portion 29C, Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary portion 29A is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 29C.
また、表示パネルＤＰ［２，１］及び表示パネルＤＰ［２，２］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。この際、図５（Ａ）に示すステップＳ０３において、境界部２９Ｂに設けられた画素２５から射出される光の輝度と、境界部２９Ｄに設けられた画素２５から射出される光の輝度と、を比較する。又は、図５（Ｂ）に示すステップＳ１２において、境界部２９Ｂに設けられた画素２５に対応するフィルタ値と、境界部２９Ｄに設けられた画素２５に対応するフィルタ値と、を比較する。 In addition, the operation illustrated in FIG. 5A or 5B is performed on the display panel DP [2, 1] and the display panel DP [2, 2]. At this time, in step S03 shown in FIG. 5A, the luminance of the light emitted from the pixel 25 provided in the boundary portion 29B and the luminance of the light emitted from the pixel 25 provided in the boundary portion 29D, Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary portion 29B is compared with the filter value corresponding to the pixel 25 provided in the boundary portion 29D.
以上により、表示パネルＤＰ［１，１］と表示パネルＤＰ［１，２］とのつなぎ目、及び表示パネルＤＰ［２，１］と表示パネルＤＰ［２，２］とのつなぎ目において、画像の不連続性が緩和される。なお、境界部２９Ａ及び境界部２９Ｂに設けられた画素２５から射出される光の輝度を、境界部２９Ｃ及び境界部２９Ｄに設けられた画素２５から射出される光の輝度とまとめて比較してもよい。また、境界部２９Ａ及び境界部２９Ｂに設けられた画素２５に対応するフィルタ値を、境界部２９Ｃ及び境界部２９Ｄに設けられた画素２５に対応するフィルタ値とまとめて比較してもよい。 As described above, in the joint between the display panel DP [1, 1] and the display panel DP [1, 2] and the joint between the display panel DP [2, 1] and the display panel DP [2, 2] Continuity is relaxed. The brightness of light emitted from the pixels 25 provided in the boundary portion 29A and the boundary portion 29B is collectively compared with the brightness of light emitted from the pixels 25 provided in the boundary portion 29C and the boundary portion 29D. It is also good. Also, filter values corresponding to the pixels 25 provided in the boundary portion 29A and the boundary portion 29B may be collectively compared with filter values corresponding to the pixels 25 provided in the boundary portion 29C and the boundary portion 29D.
なお、境界部２９Ａに設けられた画素２５から射出される光の輝度と、境界部２９Ｃに設けられた画素２５から射出される光の輝度と、の比較は必ずしも行わなくてもよい。また、境界部２９Ａに設けられた画素２５に対応するフィルタ値と、境界部２９Ｃに設けられた画素２５に対応するフィルタ値と、の比較は必ずしも行わなくてもよい。 Note that the comparison between the luminance of light emitted from the pixel 25 provided in the boundary portion 29A and the luminance of light emitted from the pixel 25 provided in the boundary portion 29C may not necessarily be performed. Further, the comparison between the filter value corresponding to the pixel 25 provided in the boundary portion 29A and the filter value corresponding to the pixel 25 provided in the boundary portion 29C may not necessarily be performed.
また、表示部２０Ａに表示パネルＤＰが２行３列に並べられた場合における、補正フィルタの作成方法の一例について説明する。図７（Ａ）、（Ｂ）、（Ｃ）は、補正フィルタの作成方法の一例を示す模式図であり、（Ａ）、（Ｂ）、（Ｃ）の順に動作が進行する。 An example of a method of creating a correction filter when the display panels DP are arranged in two rows and three columns in the display unit 20A will be described. FIGS. 7A, 7B, and 7C are schematic views showing an example of a method of creating a correction filter, and the operation proceeds in the order of (A), (B), and (C).
図７（Ａ）、（Ｂ）、（Ｃ）には、２行３列の表示パネルＤＰとして、表示パネルＤＰ［１，１］、表示パネルＤＰ［２，１］、表示パネルＤＰ［１，２］、表示パネルＤＰ［２，２］、表示パネルＤＰ［１，３］、及び表示パネルＤＰ［２，３］を示す。図７（Ｂ）において、表示パネルＤＰ［１，２］の、表示パネルＤＰ［１，３］との境界部を境界部２９Ｅとする。また、表示パネルＤＰ［２，２］の、表示パネルＤＰ［２，３］との境界部を境界部２９Ｆとする。また、表示パネルＤＰ［１，３］の、表示パネルＤＰ［１，２］との境界部を境界部２９Ｇとする。また、表示パネルＤＰ［２，３］の、表示パネルＤＰ［２，２］との境界部を境界部２９Ｈとする。 In FIGS. 7A, 7B, and 7C, the display panel DP [1, 1], the display panel DP [2, 1], and the display panel DP [1, 1] are used as the display panel DP of 2 rows and 3 columns. 2], display panel DP [2, 2], display panel DP [1, 3], and display panel DP [2, 3]. In FIG. 7B, the boundary between the display panel DP [1, 2] and the display panel DP [1, 3] is referred to as a boundary 29E. Further, the boundary between the display panel DP [2, 2] and the display panel DP [2, 3] is referred to as a boundary 29F. Further, the boundary between the display panel DP [1, 3] and the display panel DP [1, 2] is referred to as a boundary 29G. Further, the boundary between the display panel DP [2, 3] and the display panel DP [2, 2] is referred to as a boundary 29H.
補正フィルタの作成の際には、まず、表示パネルＤＰ［１，１］、表示パネルＤＰ［２，１］、表示パネルＤＰ［１，２］、及び表示パネルＤＰ［２，２］について、図６（Ａ）、（Ｂ）、（Ｃ）に示す動作を行う。また、表示パネルＤＰ［１，３］及び表示パネルＤＰ［２，３］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。 When creating the correction filter, first, display panel DP [1, 1], display panel DP [2, 1], display panel DP [1, 2], and display panel DP [2, 2]. The operations shown in 6 (A), (B) and (C) are performed. In addition, the operation illustrated in FIG. 5A or 5B is performed on the display panel DP [1, 3] and the display panel DP [2, 3].
次に、表示パネルＤＰ［１，２］及び表示パネルＤＰ［１，３］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。この際、図５（Ａ）に示すステップＳ０３において、境界部２９Ｅに設けられた画素２５から射出される光の輝度と、境界部２９Ｇに設けられた画素２５から射出される光の輝度と、を比較する。又は、図５（Ｂ）に示すステップＳ１２において、境界部２９Ｅに設けられた画素２５に対応するフィルタ値と、境界部２９Ｇに設けられた画素２５に対応するフィルタ値と、を比較する。 Next, the operation shown in FIG. 5A or 5B is performed on the display panel DP [1, 2] and the display panel DP [1, 3]. Under the present circumstances, in step S03 shown to FIG. 5 (A), the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 29E, and the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 29G Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary 29E is compared with the filter value corresponding to the pixel 25 provided in the boundary 29G.
また、表示パネルＤＰ［２，２］及び表示パネルＤＰ［２，３］について、図５（Ａ）又は図５（Ｂ）に示す動作を行う。この際、図５（Ａ）に示すステップＳ０３において、境界部２９Ｆに設けられた画素２５から射出される光の輝度と、境界部２９Ｈに設けられた画素２５から射出される光の輝度と、を比較する。又は、図５（Ｂ）に示すステップＳ１２において、境界部２９Ｆに設けられた画素２５に対応するフィルタ値と、境界部２９Ｈに設けられた画素２５に対応するフィルタ値と、を比較する。 In addition, the operation illustrated in FIG. 5A or 5B is performed on the display panel DP [2, 2] and the display panel DP [2, 3]. Under the present circumstances, in step S03 shown to FIG. 5 (A), the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 29F, and the brightness | luminance of the light inject | emitted from the pixel 25 provided in the boundary part 29H Compare Alternatively, in step S12 shown in FIG. 5B, the filter value corresponding to the pixel 25 provided in the boundary 29F is compared with the filter value corresponding to the pixel 25 provided in the boundary 29H.
以上により、表示パネルＤＰ［１，２］と表示パネルＤＰ［１，３］とのつなぎ目、及び表示パネルＤＰ［２，２］と表示パネルＤＰ［２，３］とのつなぎ目において、画像の不連続性が緩和される。なお、境界部２９Ｅ及び境界部２９Ｆに設けられた画素２５から射出される光の輝度を、境界部２９Ｇ及び境界部２９Ｈに設けられた画素２５から射出される光の輝度とまとめて比較してもよい。また、境界部２９Ｅ及び境界部２９Ｆに設けられた画素２５に対応するフィルタ値を、境界部２９Ｇ及び境界部２９Ｈに設けられた画素２５に対応するフィルタ値とまとめて比較してもよい。 As described above, in the joint between the display panel DP [1, 2] and the display panel DP [1, 3] and the joint between the display panel DP [2, 2] and the display panel DP [2, 3] Continuity is relaxed. The luminance of light emitted from the pixels 25 provided in the boundary portion 29E and the boundary portion 29F is collectively compared with the luminance of light emitted from the pixels 25 provided in the boundary portion 29G and the boundary portion 29H. It is also good. In addition, filter values corresponding to the pixels 25 provided in the boundary portion 29E and the boundary portion 29F may be collectively compared with filter values corresponding to the pixels 25 provided in the boundary portion 29G and the boundary portion 29H.
表示部２０Ｃに表示パネルＤＰが３行以上、又は４列以上並べられた場合であっても、図６（Ａ）、（Ｂ）、（Ｃ）及び図７（Ａ）、（Ｂ）、（Ｃ）に示す方法を適用することにより、各表示パネルＤＰに表示される画像に対応する画像データを補正するために用いる補正フィルタを作成することができる。 Even when the display panel DP is arranged in three or more rows or four or more columns in the display unit 20C, FIGS. 6 (A), (B), (C) and FIGS. 7 (A), (B), ( By applying the method shown in C), it is possible to create a correction filter used to correct image data corresponding to an image displayed on each display panel DP.
＜１−３．画素の構成例１＞
以下では、画素２５の構成例について、図８（Ａ）、（Ｂ）を用いて説明する。図８（Ａ）は、発光素子を有する画素２５の構成例を示す回路図である。また、図８（Ｂ）は、液晶素子を有する画素２５の構成例を示す回路図である。 <1-3. Pixel configuration example 1>
Below, the structural example of the pixel 25 is demonstrated using FIG. 8 (A) and (B). FIG. 8A is a circuit diagram showing a configuration example of the pixel 25 having a light emitting element. FIG. 8B is a circuit diagram showing a configuration example of the pixel 25 having a liquid crystal element.
図８（Ａ）に示す画素２５は、トランジスタ４４６と、容量素子４３３と、トランジスタ２５１と、トランジスタ４４４と、発光素子１７０と、を有する。 The pixel 25 illustrated in FIG. 8A includes a transistor 446, a capacitor 433, a transistor 251, a transistor 444, and a light emitting element 170.
トランジスタ４４６のソース又はドレインの一方は、画像信号が供給される信号線ＳＬに電気的に接続される。また、トランジスタ４４６のゲートは、選択信号が供給される走査線ＧＬに電気的に接続される。 One of the source and the drain of the transistor 446 is electrically connected to a signal line SL to which an image signal is supplied. The gate of the transistor 446 is electrically connected to the scan line GL to which the selection signal is supplied.
トランジスタ４４６は、画像信号のノード４４５への書き込みを制御する機能を有する。 The transistor 446 has a function of controlling writing of the image signal to the node 445.
容量素子４３３の一方の電極は、ノード４４５と電気的に接続され、容量素子４３３の他方の電極は、ノード４４７と電気的に接続される。また、トランジスタ４４６のソース又はドレインの他方は、ノード４４５に電気的に接続される。 One electrode of the capacitor 433 is electrically connected to the node 445, and the other electrode of the capacitor 433 is electrically connected to the node 447. In addition, the other of the source and the drain of the transistor 446 is electrically connected to the node 445.
容量素子４３３は、ノード４４５に書き込まれたデータを保持する保持容量としての機能を有する。 The capacitor 433 has a function as a storage capacitor which holds data written to the node 445.
トランジスタ２５１のソース又はドレインの一方は、電位供給線ＶＬ＿ａに電気的に接続され、トランジスタ２５１のソース又はドレインの他方はノード４４７に電気的に接続される。さらに、トランジスタ２５１のゲートは、ノード４４５に電気的に接続される。 One of the source or the drain of the transistor 251 is electrically connected to the potential supply line VL_a, and the other of the source or the drain of the transistor 251 is electrically connected to the node 447. Further, the gate of the transistor 251 is electrically connected to the node 445.
トランジスタ４４４のソース又はドレインの一方は、電位供給線Ｖ０に電気的に接続され、トランジスタ４４４のソース又はドレインの他方はノード４４７に電気的に接続される。さらに、トランジスタ４４４のゲートは、走査線ＧＬに電気的に接続される。 One of the source or the drain of the transistor 444 is electrically connected to the potential supply line V0, and the other of the source or the drain of the transistor 444 is electrically connected to the node 447. Further, the gate of the transistor 444 is electrically connected to the scan line GL.
発光素子１７０の一方の電極は、電位供給線ＶＬ＿ｂに電気的に接続され、発光素子１７０の他方の電極は、ノード４４７に電気的に接続される。 One electrode of the light emitting element 170 is electrically connected to the potential supply line VL_b, and the other electrode of the light emitting element 170 is electrically connected to the node 447.
なお、電源電位としては、例えば相対的に高電位側の電位又は低電位側の電位を用いることができる。高電位側の電源電位を高電源電位（「ＶＤＤ」ともいう）といい、低電位側の電源電位を低電源電位（「ＶＳＳ」ともいう）という。また、接地電位を高電源電位又は低電源電位として用いることもできる。例えば高電源電位が接地電位の場合には、低電源電位は接地電位より低い電位であり、低電源電位が接地電位の場合には、高電源電位は接地電位より高い電位である。 Note that as the power supply potential, for example, a relatively high potential side potential or a low potential side potential can be used. The power supply potential on the high potential side is referred to as a high power supply potential (also referred to as "VDD"), and the power supply potential on the low potential side is referred to as a low power supply potential (also referred to as "VSS"). The ground potential can also be used as a high power supply potential or a low power supply potential. For example, when the high power supply potential is the ground potential, the low power supply potential is a potential lower than the ground potential, and when the low power supply potential is the ground potential, the high power supply potential is a potential higher than the ground potential.
例えば、電位供給線ＶＬ＿ａ又は電位供給線ＶＬ＿ｂの一方には高電源電位ＶＤＤが供給され、電位供給線ＶＬ＿ａ又は電位供給線ＶＬ＿ｂの他方には低電源電位ＶＳＳが供給される。 For example, the high power supply potential VDD is supplied to one of the potential supply line VL_a or the potential supply line VL_b, and the low power supply potential VSS is supplied to the other of the potential supply line VL_a or the potential supply line VL_b.
図８（Ａ）に示す構成の画素２５を有する表示装置では、走査線駆動回路２２によって各行の画素２５を順次選択し、トランジスタ４４６及びトランジスタ４４４をオン状態にして画像信号をノード４４５に書き込む。 In the display device including the pixels 25 having a configuration illustrated in FIG. 8A, the pixels 25 in each row are sequentially selected by the scan line driver circuit 22, and the transistor 446 and the transistor 444 are turned on to write an image signal to the node 445.
ノード４４５にデータが書き込まれた画素２５は、トランジスタ４４６及びトランジスタ４４４がオフ状態になることで保持状態になる。さらに、ノード４４５に書き込まれたデータの電位に応じてトランジスタ２５１のソースとドレインの間に流れる電流量が制御され、発光素子１７０は、流れる電流量に応じた輝度で発光する。これを行毎に順次行うことにより、画像を表示できる。 The pixel 25 whose data is written to the node 445 is held by turning off the transistor 446 and the transistor 444. Further, the amount of current flowing between the source and the drain of the transistor 251 is controlled in accordance with the potential of the data written to the node 445, and the light emitting element 170 emits light with luminance according to the amount of current flowing. Images can be displayed by sequentially performing this on a row-by-row basis.
図８（Ｂ）に示す画素２５は、トランジスタ４４６と、容量素子４３３と、液晶素子１８０と、を有する。 The pixel 25 illustrated in FIG. 8B includes a transistor 446, a capacitor 433, and a liquid crystal element 180.
液晶素子１８０の一方の電極の電位は、画素２５の仕様に応じて適宜設定される。液晶素子１８０は、ノード４４５に書き込まれるデータにより配向状態が設定される。なお、複数の画素２５のそれぞれが有する液晶素子１８０の一方の電極に、共通の電位（コモン電位）を与えてもよい。また、各行の画素２５毎の液晶素子１８０の一方の電極に異なる電位を与えてもよい。 The potential of one of the electrodes of the liquid crystal element 180 is appropriately set in accordance with the specification of the pixel 25. The alignment state of the liquid crystal element 180 is set by data written to the node 445. Note that a common potential (common potential) may be applied to one of the electrodes of the liquid crystal element 180 included in each of the plurality of pixels 25. Further, different potentials may be applied to one electrode of the liquid crystal element 180 for each pixel 25 of each row.
画素２５において、トランジスタ４４６のソース又はドレインの一方は、信号線ＳＬに電気的に接続され、他方はノード４４５に電気的に接続される。トランジスタ４４６のゲートは、走査線ＧＬに電気的に接続される。トランジスタ４４６は、ノード４４５への画像信号の書き込みを制御する機能を有する。 In the pixel 25, one of the source and the drain of the transistor 446 is electrically connected to the signal line SL, and the other is electrically connected to the node 445. The gate of the transistor 446 is electrically connected to the scan line GL. The transistor 446 has a function of controlling writing of an image signal to the node 445.
容量素子４３３の一方の電極は、特定の電位が供給される配線（以下、容量線ＣＬ）に電気的に接続され、容量素子４３３の他方の電極は、ノード４４５に電気的に接続される。また、液晶素子１８０の他方の電極はノード４４５に電気的に接続される。なお、容量線ＣＬの電位の値は、画素２５の仕様に応じて適宜設定される。容量素子４３３は、ノード４４５に書き込まれたデータを保持する保持容量としての機能を有する。 One electrode of the capacitor 433 is electrically connected to a wiring (hereinafter, a capacitor line CL) to which a specific potential is supplied, and the other electrode of the capacitor 433 is electrically connected to the node 445. Further, the other electrode of the liquid crystal element 180 is electrically connected to the node 445. Note that the value of the potential of the capacitor line CL is appropriately set in accordance with the specification of the pixel 25. The capacitor 433 has a function as a storage capacitor which holds data written to the node 445.
図８（Ｂ）の画素２５を有する表示装置では、走査線駆動回路２２によって各行の画素２５を順次選択し、トランジスタ４４６をオン状態にしてノード４４５に画像信号を書き込む。 In the display device including the pixels 25 in FIG. 8B, the scan line driver circuit 22 sequentially selects the pixels 25 in each row, turns on the transistor 446, and writes an image signal to the node 445.
ノード４４５に画像信号が書き込まれた画素２５は、トランジスタ４４６がオフ状態になることで保持状態になる。これを行毎に順次行うことにより、画像を表示できる。 The pixel 25 whose image signal is written to the node 445 is held as the transistor 446 is turned off. Images can be displayed by sequentially performing this on a row-by-row basis.
＜１−４．表示装置の構成例２＞
図９は、表示装置１０Ｂの構成例を示すブロック図である。 <1-4. Configuration Example 2 of Display Device>
FIG. 9 is a block diagram showing a configuration example of the display device 10B.
表示装置１０Ｂは、表示装置１０Ａと同様に、外部から受信したデータを用いて、画像データを生成する機能と、当該画像データに基づいて、画像を表示する機能と、を有する。 Similar to the display device 10A, the display device 10B has a function of generating image data using data received from the outside, and a function of displaying an image based on the image data.
図９に示すように、表示装置１０Ｂは、表示部２０Ｂ及び信号生成部３０Ｂを有する。表示部２０Ｂは、表示部２０Ａと同様に、複数の表示パネルＤＰを有する。信号生成部３０Ｂは、信号生成部３０Ａと同様に、外部から受信したデータを用いて、画像データを生成する機能を有する。 As shown in FIG. 9, the display device 10B includes a display unit 20B and a signal generation unit 30B. Similar to the display unit 20A, the display unit 20B includes a plurality of display panels DP. Similar to the signal generation unit 30A, the signal generation unit 30B has a function of generating image data using data received from the outside.
図９では、表示部２０Ｂに、表示パネルＤＰが２行１列に並べられた例を示す。表示パネルＤＰの表示はそれぞれ独立に制御することができる。なお、表示部２０Ａと同様に、表示部２０Ｂに表示パネルＤＰを３行以上並べてもよいし、２列以上並べてもよい。 FIG. 9 shows an example in which the display panel DP is arranged in two rows and one column on the display unit 20B. The display of the display panel DP can be controlled independently. Similar to the display unit 20A, the display unit 20B may arrange the display panels DP in three or more rows or in two or more columns.
信号生成部３０Ｂは、フロントエンド部３１、デコーダ３２、処理部３３、受信部３４、インターフェース３５、制御部３６、処理部４０Ｂ、及び分割部４５Ｂを有する。 The signal generation unit 30B includes a front end unit 31, a decoder 32, a processing unit 33, a reception unit 34, an interface 35, a control unit 36, a processing unit 40B, and a division unit 45B.
処理部４０Ｂは、処理部４０Ａと同様に、補正フィルタを作成する機能を有する。一方、処理部４０Ｂは、処理部４０Ａと異なり、作成した補正フィルタを用いて第１の画像データＳＤ１を補正する機能は有しないものとすることができる。そして、作成した補正フィルタは、補正フィルタＦＩＬとして、補正前の画像データである第１の画像データＳＤ１と共に分割部４５Ｂに出力される。 Similar to the processing unit 40A, the processing unit 40B has a function of creating a correction filter. On the other hand, unlike the processing unit 40A, the processing unit 40B may not have the function of correcting the first image data SD1 using the created correction filter. Then, the created correction filter is output as the correction filter FIL to the dividing unit 45B together with the first image data SD1 that is the image data before correction.
分割部４５Ｂは、処理部４０Ａから入力された第１の画像データＳＤ１、及び補正フィルタＦＩＬを分割する機能を有する。第１の画像データＳＤ１及び補正フィルタＦＩＬは、表示部２０Ｂに設けられた表示パネルＤＰと同じ数に分割することができる。図９においては、第１の画像データＳＤ１が２×１個（第１の画像データＳＤ１［１，１］及び第１の画像データ［２，１］）に分割され、表示部２０Ｂに出力される。また、補正フィルタＦＩＬが２×１個（補正フィルタＦＩＬ［１，１］及び補正フィルタＦＩＬ［２，１］）に分割され、表示部２０Ｂに出力される。具体的には、第１の画像データＳＤ１［１，１］及び補正フィルタＦＩＬ［１，１］は表示パネルＤＰ［１，１］に出力され、第１の画像データＳＤ１［２，１］及び補正フィルタＦＩＬ［２，１］は表示パネルＤＰ［２，１］に出力される。 The dividing unit 45B has a function of dividing the first image data SD1 input from the processing unit 40A and the correction filter FIL. The first image data SD1 and the correction filter FIL can be divided into the same number as the display panels DP provided in the display unit 20B. In FIG. 9, the first image data SD1 is divided into 2 × 1 pieces (first image data SD1 [1,1] and first image data [2,1]) and output to the display unit 20B. Ru. Further, the correction filter FIL is divided into 2 × 1 pieces (the correction filter FIL [1, 1] and the correction filter FIL [2, 1]), and is output to the display unit 20B. Specifically, the first image data SD1 [1,1] and the correction filter FIL [1,1] are output to the display panel DP [1,1], and the first image data SD1 [2,1] and The correction filter FIL [2, 1] is output to the display panel DP [2, 1].
表示パネルＤＰに設けられた画素は、メモリ回路を有し、当該メモリ回路には、補正フィルタＦＩＬを保持することができる。これにより、第１の画像データＳＤ１の補正を処理部４０Ｂで行わなくても、画素内部で行うことができる。したがって、処理部４０Ｂの構成を簡易なものとすることができ、また本発明の一態様の表示装置の消費電力を低減することができる。 A pixel provided in the display panel DP has a memory circuit, and the memory circuit can hold the correction filter FIL. Thereby, the correction of the first image data SD1 can be performed inside the pixel without performing the correction in the processing unit 40B. Therefore, the configuration of the processing unit 40B can be simplified, and power consumption of the display device of one embodiment of the present invention can be reduced.
図１０は、図９に示す構成の表示装置１０Ｂに設けられた、表示パネルＤＰ［１，１］及び表示パネルＤＰ［２，１］の構成例を示す。 FIG. 10 shows a configuration example of the display panel DP [1, 1] and the display panel DP [2, 1] provided in the display device 10B having the configuration shown in FIG.
図１０に示す構成の表示パネルＤＰ［１，１］は、図２に示す構成の表示パネルＤＰ［１，１］と同様に、画素部２１Ａ、走査線駆動回路２２Ａ、及び信号線駆動回路２３Ａを有する。図１０に示す構成の表示パネルＤＰ［２，１］は、図２に示す構成の表示パネルＤＰ［２，１］と同様に、画素部２１Ｂ、走査線駆動回路２２Ｂ、及び信号線駆動回路２３Ｂを有する。 The display panel DP [1,1] having the configuration shown in FIG. 10 has the pixel portion 21A, the scanning line drive circuit 22A, and the signal line drive circuit 23A, similarly to the display panel DP [1,1] having the configuration shown in FIG. Have. The display panel DP [2,1] having the configuration shown in FIG. 10 has the pixel portion 21B, the scanning line drive circuit 22B, and the signal line drive circuit 23B, similarly to the display panel DP [2,1] having the configuration shown in FIG. Have.
図１０に示すように、画素部２１Ａ及び画素部２１Ｂは、それぞれ複数の画素２６を有する。図１０では、画素部２１Ａ及び画素部２１Ｂが、それぞれｍ行ｎ列のマトリクス状に配置された複数の画素２６を有する例を示す。 As shown in FIG. 10, the pixel portion 21A and the pixel portion 21B each have a plurality of pixels 26. FIG. 10 shows an example in which the pixel portion 21A and the pixel portion 21B each have a plurality of pixels 26 arranged in a matrix of m rows and n columns.
画素２６には、メモリ回路ＭＥＭが設けられる。メモリ回路ＭＥＭは、補正フィルタＦＩＬを保持する機能を有する。画素２６にメモリ回路ＭＥＭを設けることで、前述のように、第１の画像データＳＤ１の補正を処理部４０Ｂで行わなくても、画素内部で行うことができる。 The pixel 26 is provided with a memory circuit MEM. The memory circuit MEM has a function of holding the correction filter FIL. By providing the memory circuit MEM in the pixel 26, as described above, the correction of the first image data SD1 can be performed inside the pixel without being performed by the processing unit 40B.
表示パネルＤＰ［１，１］は、ｍ本の走査線ＧＬ１ａ、ｍ本の走査線ＧＬ２ａ、及びｍ本の走査線ＧＬ３ａを有し、表示パネルＤＰ［２，１］は、ｍ本の走査線ＧＬ１ｂ、ｍ本の走査線ＧＬ２ｂ、及びｍ本の走査線ＧＬ３ｂを有する。ｍ本の走査線ＧＬ１ａ、走査線ＧＬ１ｂ、走査線ＧＬ２ａ、走査線ＧＬ２ｂ、走査線ＧＬ３ａ、及び走査線ＧＬ３ｂは、それぞれ、行方向に延在する。ｍ本の走査線ＧＬ１ａは、それぞれ、画素部２１Ａにおいて行方向に並ぶ画素２６に設けられたメモリ回路ＭＥＭと電気的に接続され、ｍ本の走査線ＧＬ１ｂは、それぞれ、画素部２１Ｂにおいて行方向に並ぶ画素２６に設けられたメモリ回路ＭＥＭと電気的に接続される。ｍ本の走査線ＧＬ２ａ、及び走査線ＧＬ３ａは、それぞれ、画素部２１Ａにおいて行方向に並ぶ画素２６と電気的に接続され、ｍ本の走査線ＧＬ２ｂ、及び走査線ＧＬ３ｂは、それぞれ、画素部２１Ｂにおいて行方向に並ぶ画素２６と電気的に接続される。 The display panel DP [1,1] has m scanning lines GL1a, m scanning lines GL2a, and m scanning lines GL3a, and the display panel DP [2,1] includes m scanning lines There are GL1 b, m scanning lines GL2 b, and m scanning lines GL3 b. The m scanning lines GL1a, scanning lines GL1b, scanning lines GL2a, scanning lines GL2b, scanning lines GL3a, and scanning lines GL3b extend in the row direction. The m scanning lines GL1a are electrically connected to the memory circuits MEM provided in the pixels 26 aligned in the row direction in the pixel section 21A, and the m scanning lines GL1b are each in the row direction in the pixel section 21B. Are electrically connected to the memory circuit MEM provided in the pixels 26 aligned with one another. The m scanning lines GL2a and the scanning line GL3a are electrically connected to the pixels 26 aligned in the row direction in the pixel unit 21A, and the m scanning lines GL2b and the scanning line GL3b are each connected to the pixel unit 21B. Are electrically connected to the pixels 26 aligned in the row direction.
走査線ＧＬ１ａ、走査線ＧＬ２ａ、及び走査線ＧＬ３ａの一端は、走査線駆動回路２２Ａと電気的に接続され、走査線ＧＬ１ｂ、走査線ＧＬ２ｂ、及び走査線ＧＬ３ｂの一端は、走査線駆動回路２２Ｂと電気的に接続される。走査線駆動回路２２Ａは、走査線ＧＬ１ａ、走査線ＧＬ２ａ、及び走査線ＧＬ３ａに選択信号を供給する機能を有し、走査線駆動回路２２Ｂは、走査線ＧＬ１ｂ、走査線ＧＬ２ｂ、及び走査線ＧＬ３ｂに選択信号を供給する機能を有する。 One end of scan line GL1a, scan line GL2a, and scan line GL3a is electrically connected to scan line drive circuit 22A, and one end of scan line GL1b, scan line GL2b, and scan line GL3b is connected to scan line drive circuit 22B. Electrically connected. The scan line drive circuit 22A has a function of supplying selection signals to the scan line GL1a, the scan line GL2a, and the scan line GL3a, and the scan line drive circuit 22B corresponds to the scan line GL1b, the scan line GL2b, and the scan line GL3b. It has a function of supplying a selection signal.
本明細書等において、走査線ＧＬ１ａ及び走査線ＧＬ１ｂ等、本発明の一態様の表示装置に設けられた走査線を、走査線ＧＬ１という場合がある。また、走査線ＧＬ２ａ及び走査線ＧＬ２ｂ等、本発明の一態様の表示装置に設けられた走査線を、走査線ＧＬ２という場合がある。また、走査線ＧＬ３ａ及び走査線ＧＬ３ｂ等、本発明の一態様の表示装置に設けられた走査線を、走査線ＧＬ３という場合がある。 In this specification and the like, a scan line provided in a display device of one embodiment of the present invention, such as the scan line GL1a and the scan line GL1b, may be referred to as a scan line GL1. In addition, a scan line provided in a display device of one embodiment of the present invention, such as the scan line GL2a and the scan line GL2b, may be referred to as a scan line GL2. In addition, a scan line provided in a display device of one embodiment of the present invention, such as the scan line GL3a and the scan line GL3b, may be referred to as a scan line GL3.
表示パネルＤＰ［１，１］は、ｎ本の信号線ＳＬ１ａ、及びｎ本の信号線ＳＬ２ａを有し、表示パネルＤＰ［２，１］は、ｎ本の信号線ＳＬ１ｂ、及びｎ本の信号線ＳＬ２ｂを有する。ｎ本の信号線ＳＬ１ａ、信号線ＳＬ１ｂ、信号線ＳＬ２ａ、及び信号線ＳＬ２ｂは、それぞれ、列方向に延在する。ｎ本の信号線ＳＬ１ａは、それぞれ、画素部２１Ａにおいて列方向に並ぶ複数の画素２６に設けられたメモリ回路ＭＥＭと電気的に接続され、ｎ本の信号線ＳＬ１ｂは、それぞれ、画素部２１Ｂにおいて列方向に並ぶ複数の画素２６に設けられたメモリ回路ＭＥＭと電気的に接続される。ｎ本の信号線ＳＬ２ａは、それぞれ、画素部２１Ａにおいて列方向に並ぶ複数の画素２６と電気的に接続され、ｎ本の信号線ＳＬ２ｂは、それぞれ、画素部２１Ｂにおいて列方向に並ぶ複数の画素２６と電気的に接続される。 The display panel DP [1,1] has n signal lines SL1a and n signal lines SL2a, and the display panel DP [2,1] has n signal lines SL1b and n signals. It has a line SL2b. Each of the n signal lines SL1a, SL1b, SL2a, and SL2b extends in the column direction. The n signal lines SL1a are electrically connected to the memory circuits MEM provided in the plurality of pixels 26 aligned in the column direction in the pixel unit 21A, and the n signal lines SL1b are each connected in the pixel unit 21B. It is electrically connected to the memory circuit MEM provided in the plurality of pixels 26 aligned in the column direction. Each of the n signal lines SL2a is electrically connected to the plurality of pixels 26 aligned in the column direction in the pixel section 21A, and each of the n signal lines SL2b is a plurality of pixels aligned in the column direction in the pixel section 21B. It is electrically connected to 26.
信号線ＳＬ１ａ及び信号線ＳＬ２ａは、信号線駆動回路２３Ａと電気的に接続され、信号線ＳＬ１ｂ及び信号線ＳＬ２ｂは、信号線駆動回路２３Ｂと電気的に接続される。信号線駆動回路２３Ａは、補正フィルタに対応する信号を信号線ＳＬ１ａに供給する機能を有し、信号線駆動回路２３Ｂは、補正フィルタに対応する信号を信号線ＳＬ１ｂに供給する機能を有する。なお、本明細書等において、補正フィルタに対応する信号を、補正フィルタ信号という。補正フィルタ信号は、信号線ＳＬ１ａ又は信号線ＳＬ１ｂを介して、メモリ回路ＭＥＭに供給される。 The signal line SL1a and the signal line SL2a are electrically connected to the signal line drive circuit 23A, and the signal line SL1b and the signal line SL2b are electrically connected to the signal line drive circuit 23B. The signal line drive circuit 23A has a function of supplying a signal corresponding to the correction filter to the signal line SL1a, and the signal line drive circuit 23B has a function of supplying a signal corresponding to the correction filter to the signal line SL1b. In the present specification and the like, a signal corresponding to the correction filter is referred to as a correction filter signal. The correction filter signal is supplied to the memory circuit MEM via the signal line SL1a or the signal line SL1b.
また、信号線駆動回路２３Ａは、信号線ＳＬ２ａに画像信号を供給する機能を有し、信号線駆動回路２３Ｂは、信号線ＳＬ２ｂに画像信号を供給する機能を有する。画像信号は、信号線ＳＬ２ａ又は信号線ＳＬ２ｂを介して、画素２６に供給される。 The signal line drive circuit 23A has a function of supplying an image signal to the signal line SL2a, and the signal line drive circuit 23B has a function of supplying an image signal to the signal line SL2b. The image signal is supplied to the pixel 26 via the signal line SL2a or the signal line SL2b.
本明細書等において、信号線ＳＬ１ａ及び信号線ＳＬ１ｂ等、本発明の一態様の表示装置に設けられた信号線を、信号線ＳＬ１という場合がある。また、信号線ＳＬ２ａ及び信号線ＳＬ２ｂ等、本発明の一態様の表示装置に設けられた信号線を、信号線ＳＬ２という場合がある。 In this specification and the like, signal lines provided in a display device of one embodiment of the present invention, such as the signal line SL1a and the signal line SL1b, may be referred to as a signal line SL1. In addition, a signal line provided in a display device of one embodiment of the present invention, such as the signal line SL2a and the signal line SL2b, may be referred to as a signal line SL2.
画素２６は、表示素子を有する。画素２６に設けられる表示素子として、画素２５に設けられる表示素子と同様に、例えば発光素子、液晶素子を用いることができる。 The pixel 26 has a display element. As a display element provided in the pixel 26, for example, a light emitting element or a liquid crystal element can be used similarly to the display element provided in the pixel 25.
図１０に示す複数の画素２６は、それぞれ、画素２５と同様に、赤色（Ｒ）、緑色（Ｇ）、又は青色（Ｂ）の光を射出する機能を有する構成とすることができる。又は、図１０に示す複数の画素２６は、それぞれ、赤色（Ｒ）、緑色（Ｇ）、青色（Ｂ）、又は白色（Ｗ）の光を射出する機能を有する構成とすることができる。 Each of the plurality of pixels 26 illustrated in FIG. 10 can have a function of emitting light of red (R), green (G), or blue (B) similarly to the pixel 25. Alternatively, each of the plurality of pixels 26 illustrated in FIG. 10 can have a function of emitting light of red (R), green (G), blue (B), or white (W).
図９及び図１０に示す構成は、２つの表示パネルＤＰが横方向（列方向）に並んでいる、例えば、表示部２０Ｂに表示パネルＤＰ［１，１］及び表示パネルＤＰ［１，２］が設けられている場合であっても適用することができる。この場合、例えば、「表示パネルＤＰ［２，１］」という用語を「表示パネルＤＰ［１，２］」と適宜言い換えるものとする。 In the configuration shown in FIGS. 9 and 10, two display panels DP are arranged in the horizontal direction (column direction). For example, in the display unit 20B, the display panel DP [1, 1] and the display panel DP [1, 2] Can be applied even if. In this case, for example, the term "display panel DP [2, 1]" is appropriately rephrased as "display panel DP [1, 2]".
＜１−５．画素の構成例２＞
以下では、画素２６の構成例について、図１１を用いて説明する。 <1-5. Pixel configuration example 2>
Below, the structural example of the pixel 26 is demonstrated using FIG.
図１１は、画素２６の構成例を示す回路図である。図１１に示す構成の画素２６は、トランジスタ１０１と、トランジスタ１０２と、トランジスタ１１１と、トランジスタ１１２と、容量素子１０３と、容量素子１１３と、発光素子１０４を有する。なお、発光素子１０４として、有機ＥＬ素子、無機ＥＬ素子等を用いることができる。 FIG. 11 is a circuit diagram showing a configuration example of the pixel 26. As shown in FIG. A pixel 26 configured as shown in FIG. 11 includes a transistor 101, a transistor 102, a transistor 111, a transistor 112, a capacitor 103, a capacitor 113, and a light emitting element 104. Note that an organic EL element, an inorganic EL element, or the like can be used as the light emitting element 104.
トランジスタ１０１のソース又はドレインの一方は、容量素子１１３の一方の電極と電気的に接続される。容量素子１１３の他方の電極は、トランジスタ１１１のソース又はドレインの一方と電気的に接続される。トランジスタ１１１のソース又はドレインの一方は、トランジスタ１１２のゲートと電気的に接続される。トランジスタ１１２のゲートは、容量素子１０３の一方の電極と電気的に接続される。容量素子１０３の他方の電極は、トランジスタ１１２のソース又はドレインの一方と電気的に接続される。トランジスタ１１２のソース又はドレインの一方は、トランジスタ１０２のソース又はドレインの一方と電気的に接続される。トランジスタ１０２のソース又はドレインの他方は、発光素子１０４の一方の電極と電気的に接続される。 One of the source and the drain of the transistor 101 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to one of the source and the drain of the transistor 111. One of the source and the drain of the transistor 111 is electrically connected to the gate of the transistor 112. The gate of the transistor 112 is electrically connected to one electrode of the capacitor 103. The other electrode of the capacitor 103 is electrically connected to one of the source and the drain of the transistor 112. One of the source or the drain of the transistor 112 is electrically connected to one of the source or the drain of the transistor 102. The other of the source and the drain of the transistor 102 is electrically connected to one electrode of the light-emitting element 104.
ここで、容量素子１１３の他方の電極、トランジスタ１１１のソース又はドレインの一方、トランジスタ１１２のゲート、及び容量素子１０３の一方の電極が接続される配線をノードＮＭ１とする。また、トランジスタ１０２のソース又はドレインの他方、及び発光素子１０４の一方の電極が接続される配線をノードＮＡ１とする。 Here, a wiring to which the other electrode of the capacitor 113, one of the source or the drain of the transistor 111, the gate of the transistor 112, and one electrode of the capacitor 103 is connected is a node NM1. A wiring to which the other of the source and the drain of the transistor 102 and one electrode of the light-emitting element 104 is connected is a node NA1.
トランジスタ１０１のゲートは、走査線ＧＬ２と電気的に接続される。トランジスタ１０２のゲートは、走査線ＧＬ３と電気的に接続される。トランジスタ１１１のゲートは、走査線ＧＬ１に電気的に接続される。トランジスタ１０１のソース又はドレインの他方は、信号線ＳＬ２と電気的に接続される。トランジスタ１１１のソース又はドレインの他方は、信号線ＳＬ１と電気的に接続される。 The gate of the transistor 101 is electrically connected to the scan line GL2. The gate of the transistor 102 is electrically connected to the scan line GL3. The gate of the transistor 111 is electrically connected to the scan line GL1. The other of the source and the drain of the transistor 101 is electrically connected to the signal line SL2. The other of the source and the drain of the transistor 111 is electrically connected to the signal line SL1.
トランジスタ１１２のソース又はドレインの他方は、電位供給線１２８と電気的に接続される。発光素子１０４の他方の電極は、共通配線１２９と電気的に接続される。ここで、電位供給線１２８には、例えば高電源電位ＶＤＤを供給することができる。また、共通配線１２９には、任意の電位を供給することができる。 The other of the source and the drain of the transistor 112 is electrically connected to the potential supply line 128. The other electrode of the light emitting element 104 is electrically connected to the common wiring 129. Here, for example, the high power supply potential VDD can be supplied to the potential supply line 128. In addition, any potential can be supplied to the common wiring 129.
トランジスタ１１１及び容量素子１１３は、メモリ回路ＭＥＭを構成する。ノードＮＭ１は記憶ノードであり、トランジスタ１１１を導通させることで、信号線ＳＬ１に供給された信号をノードＮＭ１に書き込むことができる。トランジスタ１１１に極めてオフ電流の低いトランジスタを用いることで、ノードＮＭ１の電位を長時間保持することができる。当該トランジスタには、例えば、金属酸化物をチャネル形成領域に用いたトランジスタ（以下、ＯＳトランジスタ）を用いることができる。 The transistor 111 and the capacitor 113 form a memory circuit MEM. The node NM1 is a storage node, and by turning on the transistor 111, the signal supplied to the signal line SL1 can be written to the node NM1. With the use of a transistor with extremely low off-state current as the transistor 111, the potential of the node NM1 can be held for a long time. For example, a transistor in which a metal oxide is used for a channel formation region (hereinafter referred to as an OS transistor) can be used as the transistor.
なお、トランジスタ１１１だけでなく、画素２６を構成するその他のトランジスタにＯＳトランジスタを適用してもよい。また、トランジスタ１１１にＳｉをチャネル形成領域に有するトランジスタ（以下、Ｓｉトランジスタ）を適用してもよい。又は、ＯＳトランジスタと、Ｓｉトランジスタとの両方を用いてもよい。なお、上記Ｓｉトランジスタとしては、アモルファスシリコンを有するトランジスタ、結晶性のシリコン（代表的には、低温ポリシリコン）を有するトランジスタ、単結晶シリコンを有するトランジスタ等が挙げられる。 Note that the OS transistor may be applied not only to the transistor 111 but also to other transistors included in the pixel 26. In addition, a transistor having Si in a channel formation region (hereinafter, a Si transistor) may be applied to the transistor 111. Alternatively, both an OS transistor and a Si transistor may be used. Examples of the Si transistor include a transistor having amorphous silicon, a transistor having crystalline silicon (typically, low temperature polysilicon), a transistor having single crystal silicon, and the like.
ＯＳトランジスタに用いる半導体材料としては、エネルギーギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上、より好ましくは３ｅＶ以上である金属酸化物を用いることができる。代表的には、インジウムを含む酸化物半導体等であり、例えば、後述するＣＡＡＣ−ＯＳ又はＣＡＣ−ＯＳ等を用いることができる。ＣＡＡＣ−ＯＳは結晶を構成する原子が安定であり、信頼性を重視するトランジスタ等に適する。また、ＣＡＣ−ＯＳは、高移動度特性を示すため、高速駆動を行うトランジスタ等に適する。 As a semiconductor material used for the OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. Typically, an oxide semiconductor or the like containing indium can be used, for example, CAAC-OS or CAC-OS described later. The CAAC-OS is suitable for a transistor or the like in which the atoms constituting the crystal are stable and reliability is important. In addition, since CAC-OS exhibits high mobility characteristics, it is suitable for a transistor or the like which performs high-speed driving.
ＯＳトランジスタはエネルギーギャップが大きいため、極めて低いオフ電流特性を示す。また、ＯＳトランジスタは、インパクトイオン化、アバランシェ降伏、及び短チャネル効果等が生じない等Ｓｉトランジスタとは異なる特徴を有し、信頼性の高い回路を形成することができる。 An OS transistor exhibits extremely low off-current characteristics because of its large energy gap. In addition, the OS transistor has characteristics different from Si transistors, such as no impact ionization, avalanche breakdown, short channel effect and the like, and can form a highly reliable circuit.
表示素子にＥＬ素子を用いる場合はシリコン基板を用いることができ、ＳｉトランジスタとＯＳトランジスタとが重なる領域を有するように形成することができる。したがって、トランジスタ数が比較的多くても画素密度を向上させることができる。 In the case where an EL element is used for the display element, a silicon substrate can be used and a region where an Si transistor and an OS transistor overlap with each other can be formed. Therefore, the pixel density can be improved even if the number of transistors is relatively large.
画素２６において、ノードＮＭ１に書き込まれた信号は、信号線ＳＬ２から供給される画像信号と容量結合され、ノードＮＡ１に出力することができる。なお、トランジスタ１０１は、画素を選択する機能を有する。トランジスタ１０２は、発光素子１０４の発光を制御するスイッチとしての機能を有する。 In the pixel 26, the signal written to the node NM1 is capacitively coupled to the image signal supplied from the signal line SL2, and can be output to the node NA1. Note that the transistor 101 has a function of selecting a pixel. The transistor 102 has a function as a switch which controls light emission of the light emitting element 104.
例えば、信号線ＳＬ１からノードＮＭ１に書き込まれた信号の電位がトランジスタ１１２のしきい値電圧（Ｖｔｈ）より大きい場合、画像信号が書き込まれる前にトランジスタ１１２が導通し、発光素子１０４が発光してしまう。したがって、トランジスタ１０２を設け、ノードＮＭ１の電位が確定したのちにトランジスタ１０２を導通させ、発光素子１０４を発光させることが好ましい。 For example, when the potential of the signal written from the signal line SL1 to the node NM1 is larger than the threshold voltage (V th ) of the transistor 112, the transistor 112 is turned on before the image signal is written, and the light emitting element 104 emits light. It will Therefore, it is preferable that the transistor 102 be provided and the transistor 102 be turned on after the potential of the node NM1 is determined to cause the light emitting element 104 to emit light.
すなわち、ノードＮＭ１に、処理部４０Ｂによって作成された補正フィルタＦＩＬに対応する補正フィルタ信号を格納しておけば、画像信号に当該補正フィルタ信号を付加することができる。これにより、画像信号を補正することができる。なお、補正フィルタ信号は伝送経路上の要素によって減衰することがあるため、当該減衰を考慮して生成することが好ましい。 That is, when the correction filter signal corresponding to the correction filter FIL created by the processing unit 40B is stored in the node NM1, the correction filter signal can be added to the image signal. Thereby, the image signal can be corrected. In addition, since the correction filter signal may be attenuated by an element on the transmission path, it is preferable to generate in consideration of the attenuation.
次に、図１２（Ａ）、（Ｂ）に示すタイミングチャートを用いて、画素２６の動作方法の一例について説明する。なお、信号線ＳＬ１に供給される補正フィルタ信号（Ｖｐ）は正負の任意の信号を用いることができるが、ここでは正の電位の信号が供給される場合を説明する。 Next, an example of an operation method of the pixel 26 will be described using timing charts shown in FIGS. 12 (A) and 12 (B). Although the correction filter signal (Vp) supplied to the signal line SL1 can be any signal of positive and negative, here, the case where a signal of positive potential is supplied will be described.
まず、図１２（Ａ）を用いて補正フィルタ信号（Ｖｐ）をノードＮＭ１に書き込む動作を説明する。 First, an operation of writing the correction filter signal (Vp) to the node NM1 will be described using FIG. 12 (A).
時刻Ｔ１に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１０１が導通し、容量素子１１３の他方の電極の電位は低電位となる。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T1, the transistor 101 is turned on. The potential of the other of the electrodes becomes low.
当該動作は、後の容量結合動作を行うためのリセット動作である。また、時刻Ｔ１以前は、前フレームにおける発光素子１０４の発光動作が行われているが、上記リセット動作によってノードＮＭ１の電位が変化し発光素子１０４に流れる電流が変化するため、トランジスタ１０２を非導通とし、発光素子１０４の発光を停止することが好ましい。 The operation is a reset operation for performing a later capacitive coupling operation. Before time T1, the light emitting operation of the light emitting element 104 in the previous frame is performed, but the potential of the node NM1 is changed by the reset operation and the current flowing to the light emitting element 104 is changed. It is preferable that the light emission of the light emitting element 104 be stopped.
時刻Ｔ２に走査線ＧＬ１の電位を高電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１１１が導通し、信号線ＳＬ１の電位（補正フィルタ信号（Ｖｐ））がノードＮＭ１に書き込まれる。 When the potential of the scanning line GL1 is high, the potential of the scanning line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scanning line GL3 is low at time T2, the transistor 111 is turned on and the signal line SL1 is turned on. Potential (correction filter signal (Vp)) is written to the node NM1.
時刻Ｔ３に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１１１が非導通となり、ノードＮＭ１に補正フィルタ信号（Ｖｐ）が保持される。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T3, the transistor 111 is turned off. And the correction filter signal (Vp) is held.
時刻Ｔ４に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１０１が非導通となり、補正フィルタ信号（Ｖｐ）の書き込み動作が終了する。 When the potential of the scanning line GL1 is low, the potential of the scanning line GL2 is low, the potential of the signal line SL2 is low, and the potential of the scanning line GL3 is low at time T4, the transistor 101 becomes nonconductive and the correction filter The write operation of the signal (Vp) ends.
次に、図１２（Ｂ）を用いて画像信号（Ｖｓ）の補正動作と、発光素子１０４を発光させる動作を説明する。 Next, a correction operation of the image signal (Vs) and an operation of causing the light emitting element 104 to emit light will be described with reference to FIG.
時刻Ｔ１１に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１０１が導通し、容量素子１１３の容量結合によりノードＮＭ１の電位に信号線ＳＬ２の電位が付加される。すなわち、ノードＮＭ１は、画像信号（Ｖｓ）に補正フィルタ信号（Ｖｐ）が付加された電位（Ｖｓ＋Ｖｐ）となる。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is low at time T11, the transistor 101 is turned on. The potential of the signal line SL2 is added to the potential of the node NM1 by the capacitive coupling of That is, the node NM1 has a potential (Vs + Vp) obtained by adding the correction filter signal (Vp) to the image signal (Vs).
時刻Ｔ１２に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１０１が非導通となり、ノードＮＭ１の電位がＶｓ＋Ｖｐに確定される。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is low, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is low at time T12, the transistor 101 is turned off. Potential is determined to Vs + Vp.
時刻Ｔ１３に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を高電位とすると、トランジスタ１０２が導通し、ノードＮＡ１の電位はＶｓ＋Ｖｐとなり、発光素子１０４が発光する。なお、厳密にはノードＮＡ１の電位は、Ｖｓ＋Ｖｐからトランジスタ１１２のしきい値電圧（Ｖｔｈ）分だけ低い値となるが、ここではＶｔｈは十分に小さく無視できる値とする。 Assuming that the potential of scan line GL1 is low, the potential of scan line GL2 is low, the potential of signal line SL1 is low, and the potential of scan line GL3 is high at time T13, transistor 102 is turned on, and node NA1 is turned on. The potential is Vs + Vp, and the light emitting element 104 emits light. Strictly speaking, the potential of the node NA1 is lower than Vs + Vp by the threshold voltage (V th ) of the transistor 112. Here, V th is sufficiently small and negligible.
以上が画像信号（Ｖｓ）の補正動作と、発光素子１０４を発光させる動作である。なお、先に説明した補正フィルタ信号（Ｖｐ）の書き込み動作と、画像信号（Ｖｓ）の入力動作は連続して行ってもよいが、全ての画素に補正フィルタ信号（Ｖｐ）を書き込んだのちに画像信号（Ｖｓ）の入力動作を行うこともできる。 The above is the correction operation of the image signal (Vs) and the operation of causing the light emitting element 104 to emit light. Although the write operation of the correction filter signal (Vp) described above and the input operation of the image signal (Vs) may be performed continuously, after writing the correction filter signal (Vp) to all the pixels. The input operation of the image signal (Vs) can also be performed.
なお、補正動作を行わない場合は、画像信号を信号線ＳＬ１に供給し、トランジスタ１１１及びトランジスタ１０２の導通、非導通を制御することで発光素子１０４を発光させる動作を行ってもよい。このとき、トランジスタ１０１は常時非導通とすればよい。 Note that in the case where the correction operation is not performed, an operation of causing the light emitting element 104 to emit light by supplying an image signal to the signal line SL1 and controlling conduction and non-conduction of the transistor 111 and the transistor 102 may be performed. At this time, the transistor 101 may be always off.
＜１−６．画素の構成例３＞
以下では、画素２６の他の構成例について、図１３を用いて説明する。 <1-6. Pixel configuration example 3>
Below, the other structural example of the pixel 26 is demonstrated using FIG.
図１３は、画素２６の、図１１とは異なる構成例を示す回路図である。図１３に示す構成の画素２６は、トランジスタ１２１と、トランジスタ１２２と、トランジスタ１２３と、容量素子１２４と、容量素子１２５と、液晶素子１２６を有する。 FIG. 13 is a circuit diagram showing a configuration example of the pixel 26 different from FIG. A pixel 26 configured as shown in FIG. 13 includes a transistor 121, a transistor 122, a transistor 123, a capacitor 124, a capacitor 125, and a liquid crystal element 126.
トランジスタ１２１のソース又はドレインの一方は、容量素子１２４の一方の電極と電気的に接続される。容量素子１２４の他方の電極は、トランジスタ１２２のソース又はドレインの一方と電気的に接続される。トランジスタ１２２のソース又はドレインの一方は、トランジスタ１２３のソース又はドレインの一方と電気的に接続される。トランジスタ１２３のソース又はドレインの他方は、容量素子１２５の一方の電極と電気的に接続される。容量素子１２５の一方の電極は、液晶素子１２６の一方の電極と電気的に接続される。 One of the source and the drain of the transistor 121 is electrically connected to one electrode of the capacitor 124. The other electrode of the capacitor 124 is electrically connected to one of the source and the drain of the transistor 122. One of the source or the drain of the transistor 122 is electrically connected to one of the source or the drain of the transistor 123. The other of the source and the drain of the transistor 123 is electrically connected to one electrode of the capacitor 125. One electrode of the capacitor 125 is electrically connected to one electrode of the liquid crystal element 126.
ここで、容量素子１２４の他方の電極、トランジスタ１２２のソース又はドレインの一方、及びトランジスタ１２３のソース又はドレインの一方が接続される配線をノードＮＭ２とする。また、トランジスタ１２３のソース又はドレインの他方、容量素子１２５の一方の電極、及び液晶素子１２６の一方の電極が接続される配線をノードＮＡ２とする。 Here, a wiring to which the other electrode of the capacitor 124, one of the source or the drain of the transistor 122, and one of the source or the drain of the transistor 123 is connected is a node NM2. A wiring to which the other of the source and the drain of the transistor 123, one of the electrodes of the capacitor 125, and one of the electrodes of the liquid crystal element 126 are connected is a node NA2.
トランジスタ１２１のゲートは、走査線ＧＬ２と電気的に接続される。トランジスタ１２２のゲートは、走査線ＧＬ１と電気的に接続される。トランジスタ１２３のゲートは、走査線ＧＬ３に電気的に接続される。トランジスタ１２１のソース又はドレインの他方は、信号線ＳＬ２と電気的に接続される。トランジスタ１２２のソース又はドレインの他方は、信号線ＳＬ１と電気的に接続される。 The gate of the transistor 121 is electrically connected to the scan line GL2. The gate of the transistor 122 is electrically connected to the scan line GL1. The gate of the transistor 123 is electrically connected to the scan line GL3. The other of the source and the drain of the transistor 121 is electrically connected to the signal line SL2. The other of the source and the drain of the transistor 122 is electrically connected to the signal line SL1.
容量素子１２５の他方の電極は、共通配線１３２と電気的に接続される。液晶素子１２６の他方の電極は、共通配線１３３と電気的に接続される。なお、共通配線１３２及び共通配線１３３には任意の電位を供給することができる。また、共通配線１３２と共通配線１３３が電気的に接続されていてもよい。 The other electrode of the capacitor 125 is electrically connected to the common wiring 132. The other electrode of the liquid crystal element 126 is electrically connected to the common wiring 133. Note that any potential can be supplied to the common wiring 132 and the common wiring 133. In addition, the common wiring 132 and the common wiring 133 may be electrically connected.
トランジスタ１２２及び容量素子１２４は、メモリ回路ＭＥＭを構成する。ノードＮＭ２は記憶ノードであり、トランジスタ１２２を導通とし、トランジスタ１２３を非導通とすることで、信号線ＳＬ１に供給された信号をノードＮＭ２に書き込むことができる。トランジスタ１２２及びトランジスタ１２３に極めてオフ電流の低いトランジスタを用いることで、ノードＮＭ２の電位を長時間保持することができる。当該トランジスタには、例えば、ＯＳトランジスタを用いることができる。 The transistor 122 and the capacitor 124 form a memory circuit MEM. The node NM2 is a memory node, and the transistor 122 is turned on and the transistor 123 is turned off, whereby the signal supplied to the signal line SL1 can be written to the node NM2. With the use of transistors with extremely low off-state current for the transistors 122 and 123, the potential of the node NM2 can be held for a long time. For example, an OS transistor can be used for the transistor.
なお、画素が有するその他のトランジスタにＯＳトランジスタを適用してもよい。また、画素が有するトランジスタにＳｉトランジスタを適用してもよい。又は、ＯＳトランジスタと、Ｓｉトランジスタとの両方を用いてもよい。 Note that an OS transistor may be applied to another transistor included in the pixel. In addition, a Si transistor may be applied to a transistor included in a pixel. Alternatively, both an OS transistor and a Si transistor may be used.
表示素子に反射型の液晶素子を用いる場合はシリコン基板を用いることができ、ＳｉトランジスタとＯＳトランジスタとが重なる領域を有するように形成することができる。したがって、トランジスタ数が比較的多くても画素密度を向上させることができる。 In the case of using a reflective liquid crystal element for the display element, a silicon substrate can be used, and a silicon transistor and an OS transistor can be formed to have an overlapping region. Therefore, the pixel density can be improved even if the number of transistors is relatively large.
画素２６において、ノードＮＭ２に書き込まれた信号は、信号線ＳＬ２から供給される画像信号と容量結合され、ノードＮＡ２に出力することができる。なお、トランジスタ１２１は、画素を選択し、画像信号を供給する機能を有する。トランジスタ１２３は、液晶素子１２６の動作を制御するスイッチとしての機能を有する。 In the pixel 26, the signal written to the node NM2 is capacitively coupled to the image signal supplied from the signal line SL2, and can be output to the node NA2. Note that the transistor 121 has a function of selecting a pixel and supplying an image signal. The transistor 123 has a function as a switch which controls the operation of the liquid crystal element 126.
信号線ＳＬ１からノードＮＭ２に書き込まれた信号の電位が液晶素子１２６を動作させるしきい値より大きい場合、画像信号が書き込まれる前に液晶素子１２６が動作してしまうことがある。したがって、トランジスタ１２３を設け、ノードＮＭ２の電位が確定したのちにトランジスタ１２３を導通させ、液晶素子１２６を動作させることが好ましい。 When the potential of the signal written from the signal line SL1 to the node NM2 is larger than the threshold value for operating the liquid crystal element 126, the liquid crystal element 126 may operate before the image signal is written. Therefore, it is preferable that the transistor 123 be provided and the liquid crystal element 126 be operated after the potential of the node NM2 is determined and the transistor 123 is turned on.
すなわち、ノードＮＭ２に、処理部４０Ｂによって作成された補正フィルタＦＩＬに対応する補正フィルタ信号を格納しておけば、画像信号に当該補正フィルタ信号を付加することができる。これにより、画像信号を補正することができる。なお、補正フィルタ信号は伝送経路上の要素によって減衰することがあるため、当該減衰を考慮して生成することが好ましい。 That is, when the correction filter signal corresponding to the correction filter FIL created by the processing unit 40B is stored in the node NM2, the correction filter signal can be added to the image signal. Thereby, the image signal can be corrected. In addition, since the correction filter signal may be attenuated by an element on the transmission path, it is preferable to generate in consideration of the attenuation.
次に、図１４（Ａ）、（Ｂ）に示すタイミングチャートを用いて、画素２６の動作方法の一例について説明する。なお、信号線ＳＬ１に供給される補正フィルタ信号（Ｖｐ）には正負の任意の信号を用いることができるが、ここでは正の電位の信号が供給される場合を説明する。 Next, an example of an operation method of the pixel 26 will be described using timing charts shown in FIGS. 14 (A) and 14 (B). Although any signal of positive and negative can be used as the correction filter signal (Vp) supplied to the signal line SL1, a case where a signal of positive potential is supplied will be described here.
まず、図１４（Ａ）を用いて補正フィルタ信号（Ｖｐ）をノードＮＭ２に書き込む動作を説明する。 First, an operation of writing the correction filter signal (Vp) to the node NM2 will be described with reference to FIG.
時刻Ｔ１に走査線ＧＬ１の電位を高電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を高電位とすると、トランジスタ１２２及びトランジスタ１２３が導通し、ノードＮＡ２の電位は信号線ＳＬ１の電位となる。このとき、信号線ＳＬ１の電位をリセット電位（例えば０Ｖ等の基準電位）とすることで、液晶素子１２６の動作をリセットすることができる。 When the potential of the scan line GL1 is high, the potential of the scan line GL2 is low, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is high at time T1, the transistors 122 and 123 are turned on. The potential of the node NA2 becomes the potential of the signal line SL1. At this time, the operation of the liquid crystal element 126 can be reset by setting the potential of the signal line SL1 to a reset potential (for example, a reference potential such as 0 V).
なお、時刻Ｔ１より前は、前フレームにおける液晶素子１２６の表示動作が行われている状態である。 Note that before time T1, the display operation of the liquid crystal element 126 in the previous frame is being performed.
時刻Ｔ２に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１２１が導通し、容量素子１２４の他方の電極の電位は低電位となる。当該動作は、後の容量結合動作を行うためのリセット動作である。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T2, the transistor 121 is turned on. The potential of the other of the electrodes becomes low. The operation is a reset operation for performing a later capacitive coupling operation.
時刻Ｔ３に走査線ＧＬ１の電位を高電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１２２が導通し、信号線ＳＬ１の電位（補正フィルタ信号（Ｖｐ））がノードＮＭ２に書き込まれる。なお、信号線ＳＬ１の電位は、時刻Ｔ２以降時刻Ｔ３以前に所望の値（補正フィルタ信号（Ｖｐ））に定まっていることが好ましい。 When the potential of the scanning line GL1 is high, the potential of the scanning line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scanning line GL3 is low at time T3, the transistor 122 is turned on and the signal line SL1 Potential (correction filter signal (Vp)) is written to the node NM2. Preferably, the potential of the signal line SL1 is fixed to a desired value (corrected filter signal (Vp)) from time T2 to time T3.
時刻Ｔ４に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１２２が非導通となり、ノードＮＭ２に補正フィルタ信号（Ｖｐ）が保持される。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL2 is low, and the potential of the scan line GL3 is low at time T4, the transistor 122 is turned off. And the correction filter signal (Vp) is held.
時刻Ｔ５に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ２の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１２１が非導通となり、補正フィルタ信号（Ｖｐ）の書き込み動作が終了する。 When the potential of the scanning line GL1 is low, the potential of the scanning line GL2 is low, the potential of the signal line SL2 is low, and the potential of the scanning line GL3 is low at time T5, the transistor 121 becomes nonconductive and the correction filter The write operation of the signal (Vp) ends.
次に、図１４（Ｂ）を用いて画像信号（Ｖｓ）の補正動作と、液晶素子１２６の表示動作を説明する。 Next, the correction operation of the image signal (Vs) and the display operation of the liquid crystal element 126 will be described with reference to FIG.
時刻Ｔ１１に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を高電位とすると、トランジスタ１２３が導通し、ノードＮＡ２にノードＮＭ２の電位が分配される。なお、ノードＮＭ２に保持する補正フィルタ信号（Ｖｐ）は、ノードＮＡ２への分配を考慮して設定することが好ましい。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is low, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is high at time T11, the transistor 123 conducts and the node NA2 The potential of the node NM2 is distributed. The correction filter signal (Vp) held in the node NM2 is preferably set in consideration of distribution to the node NA2.
時刻Ｔ１２に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を高電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を高電位とすると、トランジスタ１２１が導通し、容量素子１２４の容量結合によりノードＮＡ２の電位に信号線ＳＬ２の電位が付加される。すなわち、ノードＮＡ２は、画像信号（Ｖｓ）に補正フィルタ信号（Ｖｐ）が付加された電位に対応する電位（Ｖｓ＋Ｖｐ）’となる。なお、電位（Ｖｓ＋Ｖｐ）’には、配線間容量の容量結合による電位の変動等も含まれる。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is high, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is high at time T12, the transistor 121 is turned on and the capacitor 124 is turned on. The potential of the signal line SL2 is added to the potential of the node NA2 by the capacitive coupling of That is, the node NA2 has a potential (Vs + Vp) 'corresponding to the potential obtained by adding the correction filter signal (Vp) to the image signal (Vs). Note that the potential (Vs + Vp) 'includes the fluctuation of the potential due to the capacitive coupling of the capacitance between the interconnections.
時刻Ｔ１３に走査線ＧＬ１の電位を低電位、走査線ＧＬ２の電位を低電位、信号線ＳＬ１の電位を低電位、走査線ＧＬ３の電位を低電位とすると、トランジスタ１２１が非導通となり、ノードＮＡ２に電位（Ｖｓ＋Ｖｐ）’が保持される。そして、当該電位に応じて液晶素子１２６で表示動作が行われる。 When the potential of the scan line GL1 is low, the potential of the scan line GL2 is low, the potential of the signal line SL1 is low, and the potential of the scan line GL3 is low at time T13, the transistor 121 is turned off. Holds the potential (Vs + Vp) '. Then, a display operation is performed by the liquid crystal element 126 in accordance with the potential.
以上が画像信号（Ｖｓ）の補正動作と、液晶素子１２６の表示動作の説明である。なお、先に説明した補正フィルタ信号（Ｖｐ）の書き込み動作と、画像信号（Ｖｓ）の入力動作は連続して行ってもよいが、全ての画素に補正フィルタ信号（Ｖｐ）を書き込んだのちに画像信号（Ｖｓ）の入力動作を行うこともできる。 The above is the description of the correction operation of the image signal (Vs) and the display operation of the liquid crystal element 126. Although the write operation of the correction filter signal (Vp) described above and the input operation of the image signal (Vs) may be performed continuously, after writing the correction filter signal (Vp) to all the pixels. The input operation of the image signal (Vs) can also be performed.
なお、補正動作を行わない場合は、画像信号を信号線ＳＬ１に供給し、トランジスタ１２２及びトランジスタ１２３の導通、非導通を制御することで液晶素子１２６による表示動作を行ってもよい。このとき、トランジスタ１２１は常時非導通とすればよい。 Note that in the case where the correction operation is not performed, the display operation by the liquid crystal element 126 may be performed by supplying an image signal to the signal line SL1 and controlling conduction and non-conduction of the transistor 122 and the transistor 123. At this time, the transistor 121 may be always off.
＜１−７．表示装置の動作方法の一例２＞
次に、図５（Ａ）に示すステップＳ０１、及び図５（Ｂ）に示すステップＳ１１の具体例、つまり、１枚の表示パネルＤＰに対応する補正フィルタの作成方法の一例について、図１５に示すフローチャートを用いて説明する。例えば、表示パネルＤＰ［１，１］に対応する補正フィルタである第１の補正フィルタ、及び表示パネルＤＰ［２，１］に対応する補正フィルタである第２の補正フィルタは、図１５に示す方法により作成することができる。図１５に示す方法により作成した補正フィルタは、例えば、表示パネルＤＰに表示される画像の表示ムラを軽減するように、画像データを補正する機能を有する。 <1-7. Example of operation method of display device 2>
Next, a specific example of step S01 shown in FIG. 5A and step S11 shown in FIG. 5B, that is, an example of a method of creating a correction filter corresponding to one display panel DP will be described with reference to FIG. It demonstrates using the flowchart shown. For example, a first correction filter which is a correction filter corresponding to the display panel DP [1, 1] and a second correction filter which is a correction filter corresponding to the display panel DP [2, 1] are shown in FIG. It can be created by the method. The correction filter created by the method shown in FIG. 15 has a function of correcting image data so as to reduce display unevenness of an image displayed on the display panel DP, for example.
まず、複数の階調値に対して、表示パネルＤＰに設けられた画素から射出される光の輝度を測定する。ここで、光の輝度は、輝度計等を用いて測定する（ステップＳ２１）。次に、例えば処理部４０Ａ又は処理部４０Ｂが、測定結果を基にして、画素から射出される光の輝度と、階調値と、の対応関係のデータを取得する（ステップＳ２２）。図１６（Ａ−１）、（Ｂ−１）は、画素から射出される光の輝度と、階調値と、の関係を示すグラフであり、図１６（Ａ−１）に示されたプロットは、ステップＳ２１で測定される輝度である。また、図１６（Ｂ−１）に示された実線は、図１６（Ａ−１）に示された測定結果を基にステップＳ２２で算出される、画素から射出される光の輝度と、階調値と、の対応関係である。 First, the brightness of light emitted from the pixels provided in the display panel DP is measured for a plurality of gradation values. Here, the luminance of light is measured using a luminance meter or the like (step S21). Next, for example, based on the measurement result, the processing unit 40A or the processing unit 40B acquires data of the correspondence between the luminance of the light emitted from the pixel and the gradation value (step S22). FIGS. 16A-1 and 16B-1 are graphs showing the relationship between the luminance of light emitted from a pixel and the gradation value, and the plots shown in FIG. Is the luminance measured in step S21. The solid line shown in FIG. 16 (B-1) represents the brightness of the light emitted from the pixel and the floor, which are calculated in step S22 based on the measurement result shown in FIG. 16 (A-1). There is a correspondence relationship with the price adjustment.
ここで、ステップＳ２１で、全ての階調値について、画素から射出される光の輝度を測定してもよい。例えば、画素が表現可能な階調値が０乃至２５５である場合は、階調値０乃至２５５の全てについて、画素から射出される光の輝度を測定してもよい。又は、一部の階調値について、画素から射出される光の輝度を測定してもよい。なお、一部の階調値について輝度を測定する場合であっても、対応関係のデータの精度を高めるために、白色、黒色、及び中間階調については輝度を測定することが好ましい。例えば、画素が表現可能な階調値が０乃至２５５である場合は、階調値０、階調値１２７、及び階調値２５５については、画素から射出される光の輝度を測定することが好ましい。 Here, in step S21, the luminance of the light emitted from the pixels may be measured for all the gradation values. For example, when the gradation value that can be expressed by the pixel is 0 to 255, the luminance of the light emitted from the pixel may be measured for all of the gradation values 0 to 255. Alternatively, the brightness of light emitted from a pixel may be measured for some gradation values. Even when luminance is measured for some gradation values, it is preferable to measure luminance for white, black, and middle gradation in order to enhance the accuracy of the correspondence data. For example, when the gradation value that can be expressed by the pixel is 0 to 255, the luminance of the light emitted from the pixel may be measured for the gradation value 0, the gradation value 127, and the gradation value 255. preferable.
図１６（Ｂ−１）に示す対応関係のデータは、図１６（Ａ−１）に示す測定結果を基にして、例えば回帰分析により取得することができる。例えば、曲線回帰分析により取得することができる。又は、例えばニューラルネットワーク、例えば全結合型のニューラルネットワークを用いて取得することができる。ニューラルネットワークを用いて図１６（Ｂ−１）に示す対応関係のデータを取得することにより、図１６（Ａ−１）に示す測定点数が少なくても、対応関係のデータの精度を高めることができる。 The data of the correspondence shown in FIG. 16 (B-1) can be obtained, for example, by regression analysis based on the measurement result shown in FIG. 16 (A-1). For example, it can acquire by curve regression analysis. Alternatively, it can be obtained, for example, using a neural network, such as a fully coupled neural network. Even if the number of measurement points shown in FIG. 16 (A-1) is small, accuracy of the data of the correspondence relationship can be increased by acquiring data of the correspondence relationship shown in FIG. 16 (B-1) using a neural network. it can.
図１６（Ａ−２）は、ステップＳ２１で、赤色（Ｒ）、緑色（Ｇ）、及び青色（Ｂ）のそれぞれについて、画素から射出される光の輝度を測定する場合の測定値を示す。図１６（Ｂ−２）は、ステップＳ２２で、図１６（Ａ−２）に示す測定結果を基にして赤色（Ｒ）、緑色（Ｇ）、及び青色（Ｂ）のそれぞれについて算出される、画素から射出される光の輝度と、階調値と、の対応関係である。 FIG. 16A-2 shows measured values when the luminance of light emitted from the pixel is measured for each of red (R), green (G), and blue (B) in step S21. 16 (B-2) is calculated for each of red (R), green (G), and blue (B) based on the measurement results shown in FIG. 16 (A-2) in step S22. It is the correspondence of the luminance of the light emitted from the pixel and the gradation value.
図１６（Ａ−２）、（Ｂ−２）に示すように、画素から射出される光の色ごとに輝度と、階調値と、の対応関係のデータを取得することにより、高精度な補正ができる補正フィルタを作成することができる。 As shown in FIGS. 16 (A-2) and (B-2), high accuracy can be achieved by acquiring the data of the correspondence between the luminance and the gradation value for each color of light emitted from the pixel. A correction filter capable of correction can be created.
図１７（Ａ）、（Ｂ）、（Ｃ）は、ステップＳ２１で、射出される光の輝度を測定する画素の位置の一例を示している。ここで、画素部２１は、画素部２１Ａ、画素部２１Ｂ等、１枚の表示パネルＤＰに設けられた画素部を示す。図１７（Ａ）、（Ｂ）、（Ｃ）に示す領域２７に含まれる画素から射出される光の輝度を、ステップＳ２１で測定する。 FIGS. 17A, 17B, and 17C show an example of the position of a pixel for measuring the luminance of the emitted light in step S21. Here, the pixel unit 21 indicates a pixel unit provided in one display panel DP, such as the pixel unit 21A and the pixel unit 21B. The luminance of light emitted from the pixels included in the area 27 shown in FIGS. 17A, 17B, and 17C is measured in step S21.
画素から射出される光の輝度は、図１７（Ａ）に示すように、画素部２１の中心部を含むように測定してもよい。又は、図１７（Ｂ）に示すように、画素部２１の複数個所、例えば左上、右上、左下、及び右下の４箇所を測定してもよい。又は、図１７（Ｃ）に示すように、画素部２１の全体を測定してもよい。領域２７の総面積が小さい場合、画素から射出される光の輝度を簡易な方法で測定することができる。一方、領域２７の総面積が大きい場合、高精度な補正ができる補正フィルタを作成することができる。 The luminance of light emitted from the pixels may be measured so as to include the central portion of the pixel portion 21 as shown in FIG. Alternatively, as shown in FIG. 17B, measurement may be performed at a plurality of locations of the pixel unit 21, for example, four locations on the upper left, upper right, lower left, and lower right. Alternatively, as shown in FIG. 17C, the entire pixel portion 21 may be measured. When the total area of the region 27 is small, the brightness of the light emitted from the pixel can be measured by a simple method. On the other hand, when the total area of the region 27 is large, it is possible to create a correction filter capable of highly accurate correction.
なお、画素から射出される光の輝度を複数の画素について測定する場合は、例えば、それぞれの画素から射出される光の輝度の平均値を基にして、画素から射出される光の輝度と、階調値と、の対応関係のデータをステップＳ２２において取得することができる。 When the brightness of light emitted from a pixel is measured for a plurality of pixels, for example, based on the average value of the brightness of light emitted from each pixel, the brightness of light emitted from the pixel; Data of the correspondence relationship with the gradation value can be acquired in step S22.
ステップＳ２２の終了後、特定の階調値の画像を画素部２１に表示し、画素から射出される光の輝度を、二次元輝度計等を用いて測定することにより、輝度データを取得する（ステップＳ２３）。例えば、画素部２１に設けられた全ての画素から射出される光の輝度を、二次元輝度計等を用いて測定することにより、輝度データを取得する。 After the end of step S22, an image having a specific gradation value is displayed on the pixel unit 21, and luminance data is acquired by measuring the luminance of light emitted from the pixel using a two-dimensional luminance meter or the like (see FIG. Step S23). For example, luminance data is acquired by measuring the luminance of light emitted from all the pixels provided in the pixel unit 21 using a two-dimensional luminance meter or the like.
特定の階調値の画像として、全ての画素の階調値が等しい画像を画素部２１に表示する場合、１枚の表示パネルＤＰに設けられた全ての画素から射出される光の輝度が等しいことが好ましい。しかし、画素が有するトランジスタの特性ばらつき、及び表示素子の特性ばらつき等により、画素から射出される光の輝度にばらつきが生じる場合がある。ステップＳ２３では、画素から射出される光の輝度の画素間のばらつきに関する情報を取得するために、輝度データを取得する。 When an image having the same gradation value of all the pixels is displayed on the pixel unit 21 as an image having a specific gradation value, the luminances of light emitted from all the pixels provided in one display panel DP are equal. Is preferred. However, variations in the characteristics of transistors included in the pixels, variations in the characteristics of display elements, and the like may cause variations in luminance of light emitted from the pixels. In step S23, luminance data is acquired in order to acquire information on variations in luminance of light emitted from the pixels.
次に、ステップＳ２３で取得した輝度データと、ステップＳ２２で取得した対応関係のデータと、を用いて、画素から射出される光の輝度の画素間のばらつきを補正するための補正フィルタを、処理部により作成する（ステップＳ２４）。例えば、輝度データから読み取れる、ある画素の階調値１２７での輝度が１００で、対応関係のデータでは、階調値１２７での輝度が１２０であったとすると、ある画素の輝度を１．２倍するように補正フィルタを作成する。 Next, using the luminance data acquired in step S23 and the correspondence data acquired in step S22, a correction filter for correcting the variation in luminance of light emitted from the pixels is processed. It prepares by the department (step S24). For example, if the luminance at a gradation value 127 of a certain pixel that can be read from luminance data is 100 and the correspondence data indicates that the luminance at a gradation value 127 is 120, the luminance of a certain pixel is 1.2 times Create a correction filter to
ここで、ステップＳ２２で、例えば全ての階調値について、輝度との対応関係のデータが取得されている。よって、ステップＳ２３で、２種類以上の画像を表示し、それぞれの画像について輝度データを取得することにより、より高精度の補正が可能な補正フィルタを作成することができる。例えば、画素が表現可能な階調値が０乃至２５５である場合、ステップＳ２３において、全ての画素の階調が０である画像、全ての画素の階調が１２７である画像、及び全ての画素の階調が２５５である画像のそれぞれについて、輝度データを取得することができる。なお、ステップＳ２３における光の輝度の測定を簡易なものとするために、ステップＳ２３で取得する輝度データの種類の数は、ステップＳ２１で光の輝度を測定した階調値の数より少ないことが好ましい。 Here, in step S22, for example, data of correspondence with luminance is acquired for all gradation values. Therefore, by displaying two or more types of images in step S23 and acquiring luminance data for each image, it is possible to create a correction filter capable of higher accuracy correction. For example, when the gradation value that can be expressed by a pixel is 0 to 255, in step S23, an image in which the gradation of all pixels is 0, an image in which the gradation of all pixels is 127, and all pixels Luminance data can be acquired for each of the images whose gray level is 255. In order to simplify the measurement of the brightness of light in step S23, the number of types of brightness data acquired in step S23 may be smaller than the number of gradation values obtained by measuring the brightness of light in step S21. preferable.
その後、処理部４０Ａ又は処理部４０Ｂに画像データを入力し、ステップＳ２４で作成した補正フィルタを用いて、入力された画像データを補正する（ステップＳ２５）。ここで、処理部４０Ａ又は処理部４０Ｂに入力される画像データは、例えば特定の階調値の画像に対応する画像データとすることが好ましい。例えば、ステップＳ２３で表示した画像と同じ階調の画像に対応する画像データとすることが好ましい。 Thereafter, the image data is input to the processing unit 40A or 40B, and the input image data is corrected using the correction filter created in step S24 (step S25). Here, it is preferable that the image data input to the processing unit 40A or the processing unit 40B be, for example, image data corresponding to an image of a specific gradation value. For example, it is preferable to set it as the image data corresponding to the image of the same gradation as the image displayed by step S23.
次に、ステップＳ２５で補正を行った画像データに対応する画像を画素部２１に表示し、ステップＳ２３と同様に、画素から射出される光の輝度を、二次元輝度計等を用いて測定する（ステップＳ２６）。その後、ステップＳ２６で測定した補正後の画像に対応する輝度と、ステップＳ２２で取得した対応関係のデータから算出される輝度と、を画素毎に比較する。例えば、補正後の画像に対応する輝度と、ステップＳ２２で取得した対応関係のデータから算出される輝度と、の差分が一定値未満である場合は、補正の精度は規定値以上であるとして、補正フィルタの作成を終了する。一方、補正後の画像に対応する輝度と、ステップＳ２２で取得した対応関係のデータから算出される輝度と、の差分が一定値以上である場合は、補正の精度は規定値未満であるとして、再びステップＳ２４及びステップＳ２７を行い、補正フィルタを再度作成する（ステップＳ２７）。以上が表示装置１０Ａ及び表示装置１０Ｂで用いられる補正フィルタの作成方法の一例である。なお、ステップＳ２６及びステップＳ２７は省略してもよい。 Next, an image corresponding to the image data corrected in step S25 is displayed on the pixel unit 21, and the luminance of light emitted from the pixel is measured using a two-dimensional luminance meter or the like as in step S23. (Step S26). Thereafter, the luminance corresponding to the image after correction measured in step S26 is compared with the luminance calculated from the data of the correspondence obtained in step S22 for each pixel. For example, when the difference between the luminance corresponding to the image after correction and the luminance calculated from the data of the correspondence obtained in step S22 is less than a predetermined value, it is assumed that the correction accuracy is equal to or higher than the specified value. Finish creating the correction filter. On the other hand, if the difference between the luminance corresponding to the image after correction and the luminance calculated from the data of the correspondence obtained in step S22 is equal to or greater than a predetermined value, the correction accuracy is assumed to be less than the specified value. Steps S24 and S27 are performed again to create a correction filter again (step S27). The above is an example of a method of creating the correction filter used in the display device 10A and the display device 10B. Note that steps S26 and S27 may be omitted.
なお、ステップＳ２３で２種類以上の画像を表示した場合は、ステップＳ２６でそれぞれの画像について画素から射出される光の輝度を測定し、ステップＳ２７でそれぞれの画像について補正の精度を判定することが好ましい。 When two or more types of images are displayed in step S23, the brightness of light emitted from the pixels is measured in step S26, and the correction accuracy of each image is determined in step S27. preferable.
以上が図５（Ａ）に示すステップＳ０１、及び図５（Ｂ）に示すステップＳ１１の具体例、つまり、１枚の表示パネルＤＰに対応する補正フィルタの作成方法の一例である。 The above is a specific example of step S01 shown in FIG. 5A and step S11 shown in FIG. 5B, that is, an example of a method of creating a correction filter corresponding to one display panel DP.
図１５に示す方法で補正フィルタを作成することにより、例えば、表示される画像の表示ムラを軽減することができるので、本発明の一態様の表示装置の表示品位を高めることができる。 By creating the correction filter by the method shown in FIG. 15, for example, display unevenness of the displayed image can be reduced, and thus the display quality of the display device of one embodiment of the present invention can be improved.
本実施の形態は、他の実施の形態等に記載した構成と適宜組み合わせて実施することができる。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
（実施の形態２）
本実施の形態では、液晶素子を用いた表示装置の構成例と、ＥＬ素子を用いた表示装置の構成例について説明する。なお、本実施の形態においては、実施の形態１で説明した表示装置の要素、動作及び機能の説明は省略する。 Second Embodiment
In this embodiment, a structural example of a display device using a liquid crystal element and a structural example of a display device using an EL element will be described. In the present embodiment, descriptions of the elements, operations, and functions of the display device described in Embodiment 1 will be omitted.
図１８（Ａ）及び図１８（Ｂ）は、本発明の一態様の表示装置の構成例を示す断面図である。図１８（Ａ）及び図１８（Ｂ）に示す表示装置は電極４０１５を有しており、電極４０１５はＦＰＣ４０１８が有する端子と、異方性導電層４０１９を介して電気的に接続されている。また、図１８（Ａ）及び図１８（Ｂ）では、電極４０１５は、絶縁層４１１２、絶縁層４１１１、及び絶縁層４１１０に形成された開口において配線４０１４と電気的に接続されている。 18A and 18B are cross-sectional views illustrating configuration examples of a display device of one embodiment of the present invention. The display devices illustrated in FIGS. 18A and 18B each include an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. In FIGS. 18A and 18B, the electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.
電極４０１５は、第１の電極層４０３０と同じ導電層から形成され、配線４０１４は、トランジスタ４０１０、及びトランジスタ４０１１のソース電極及びドレイン電極と同じ導電層で形成されている。 The electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed of the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.
また、第１の基板４００１上に設けられた表示部２１５と走査線駆動回路２２１は、トランジスタを複数有しており、図１８（Ａ）、及び図１８（Ｂ）では、表示部２１５に含まれるトランジスタ４０１０、及び走査線駆動回路２２１に含まれるトランジスタ４０１１を例示している。なお、図１８（Ａ）及び図１８（Ｂ）では、トランジスタ４０１０及びトランジスタ４０１１としてボトムゲート型のトランジスタを例示しているが、トップゲート型のトランジスタであってもよい。 In addition, the display portion 215 and the scan line driver circuit 221 provided over the first substrate 4001 have a plurality of transistors, and are included in the display portion 215 in FIGS. 18A and 18B. The transistor 4010 and the transistor 4011 included in the scan line driver circuit 221 are illustrated. Although bottom-gate transistors are illustrated as the transistors 4010 and 4011 in FIGS. 18A and 18B, top-gate transistors may be used.
図１８（Ａ）及び図１８（Ｂ）では、トランジスタ４０１０及びトランジスタ４０１１上に絶縁層４１１２が設けられている。また、図１８（Ｂ）では、絶縁層４１１２上に隔壁４５１０が形成されている。 In FIGS. 18A and 18B, the insulating layer 4112 is provided over the transistor 4010 and the transistor 4011. In FIG. 18B, the partition 4510 is formed over the insulating layer 4112.
また、トランジスタ４０１０及びトランジスタ４０１１は、絶縁層４１０２上に設けられている。また、トランジスタ４０１０及びトランジスタ４０１１は、絶縁層４１１１上に形成された電極４０１７を有する。電極４０１７はバックゲート電極として機能することができる。 The transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. The transistor 4010 and the transistor 4011 each have an electrode 4017 formed over the insulating layer 4111. The electrode 4017 can function as a back gate electrode.
また、図１８（Ａ）及び図１８（Ｂ）に示す表示装置は、容量素子４０２０を有する。容量素子４０２０は、トランジスタ４０１０のゲート電極と同じ工程で形成された電極４０２１と、ソース電極及びドレイン電極と同じ工程で形成された電極と、を有する。それぞれの電極は、絶縁層４１０３を介して重なる領域を有している。 The display devices illustrated in FIGS. 18A and 18B each include a capacitor 4020. The capacitor 4020 includes an electrode 4021 formed in the same step as the gate electrode of the transistor 4010, and an electrode formed in the same step as the source electrode and the drain electrode. Each electrode has a region overlapping with the insulating layer 4103 interposed therebetween.
一般に、表示装置の画素部に設けられる容量素子の容量は、画素部に配置されるトランジスタのリーク電流等を考慮して、所定の期間の間電荷を保持できるように設定される。容量素子の容量は、トランジスタのオフ電流等を考慮して設定すればよい。 In general, the capacitance of a capacitor provided in a pixel portion of a display device is set so as to hold charge for a predetermined period, in consideration of leakage current or the like of a transistor provided in the pixel portion. The capacitance of the capacitor may be set in consideration of the off current of the transistor and the like.
表示部２１５に設けられたトランジスタ４０１０は表示素子と電気的に接続する。図１８（Ａ）は、表示素子として液晶素子を用いた液晶表示装置の一例である。図１８（Ａ）において、表示素子である液晶素子４０１３は、第１の電極層４０３０、第２の電極層４０３１、及び液晶層４００８を含む。なお、液晶層４００８を挟持するように配向膜として機能する絶縁層４０３２、絶縁層４０３３が設けられている。第２の電極層４０３１は第２の基板４００６側に設けられ、第１の電極層４０３０と第２の電極層４０３１は液晶層４００８を介して重畳する。 The transistor 4010 provided in the display portion 215 is electrically connected to the display element. FIG. 18A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 18A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other through the liquid crystal layer 4008.
また、スペーサ４０３５は絶縁層を選択的にエッチングすることで得られる柱状のスペーサであり、第１の電極層４０３０と第２の電極層４０３１との間隔（セルギャップ）を制御するために設けられている。なお球状のスペーサを用いていても良い。 The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control a distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. ing. A spherical spacer may be used.
また、必要に応じて、ブラックマトリクス（遮光層）、着色層（カラーフィルタ）、偏光部材、位相差部材、反射防止部材等の光学部材（光学基板）等を適宜設けてもよい。例えば、偏光基板及び位相差基板による円偏光を用いてもよい。また、光源としてバックライト、サイドライト等を用いてもよい。また、上記バックライト、及びサイドライトとして、マイクロＬＥＤ等を用いても良い。 In addition, if necessary, an optical member (optical substrate) such as a black matrix (light shielding layer), a colored layer (color filter), a polarization member, a retardation member, an anti-reflection member, etc. may be provided appropriately. For example, circularly polarized light by a polarizing substrate and a retardation substrate may be used. In addition, a backlight, a sidelight, or the like may be used as a light source. Moreover, you may use micro LED etc. as said backlight and side light.
図１８（Ａ）に示す表示装置では、第２の基板４００６と第２の電極層４０３１の間に、遮光層４１３２、着色層４１３１、絶縁層４１３３が設けられている。 In the display device illustrated in FIG. 18A, a light shielding layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided between the second substrate 4006 and the second electrode layer 4031.
遮光層として用いることのできる材料としては、カーボンブラック、チタンブラック、金属、金属酸化物、複数の金属酸化物の固溶体を含む複合酸化物等が挙げられる。遮光層は、樹脂材料を含む膜であってもよいし、金属等の無機材料の薄膜であってもよい。また、遮光層に、着色層の材料を含む膜の積層膜を用いることもできる。例えば、ある色の光を透過する着色層に用いる材料を含む膜と、他の色の光を透過する着色層に用いる材料を含む膜との積層構造を用いることができる。着色層と遮光層の材料を共通化することで、装置を共通化できるほか工程を簡略化できるため好ましい。 Examples of the material that can be used as the light shielding layer include carbon black, titanium black, metals, metal oxides, and composite oxides containing a solid solution of a plurality of metal oxides. The light shielding layer may be a film containing a resin material or may be a thin film of an inorganic material such as a metal. In addition, a stacked film of films including a material of a colored layer can also be used for the light shielding layer. For example, a layered structure of a film containing a material used for a colored layer transmitting light of a certain color and a film containing a material used for a colored layer transmitting light of another color can be used. It is preferable to use a common material for the colored layer and the light shielding layer, as it is possible to share the device and simplify the process.
着色層に用いることのできる材料としては、金属材料、樹脂材料、顔料又は染料が含まれた樹脂材料等が挙げられる。遮光層及び着色層は、前述した各層の形成方法と同様に形成すればよい。例えば、インクジェット法等で行なってもよい。 Examples of materials that can be used for the colored layer include metal materials, resin materials, resin materials containing pigments or dyes, and the like. The light shielding layer and the colored layer may be formed in the same manner as the formation method of each layer described above. For example, it may be performed by an inkjet method or the like.
また、図１８（Ａ）及び図１８（Ｂ）に示す表示装置は、絶縁層４１１１と絶縁層４１０４を有する。絶縁層４１１１と絶縁層４１０４として、不純物元素を透過しにくい絶縁層を用いる。絶縁層４１１１と絶縁層４１０４でトランジスタの半導体層を挟むことで、外部からの不純物の浸入を防ぐことができる。 The display devices illustrated in FIGS. 18A and 18B each include an insulating layer 4111 and an insulating layer 4104. As the insulating layer 4111 and the insulating layer 4104, an insulating layer which hardly transmits an impurity element is used. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, entry of impurities from the outside can be prevented.
また、表示装置に含まれる表示素子として、エレクトロルミネッセンスを利用する発光素子（ＥＬ素子）を適用することができる。ＥＬ素子は、一対の電極の間に発光性の化合物を含む層（「ＥＬ層」ともいう。）を有する。一対の電極間に、ＥＬ素子の閾値電圧よりも大きい電位差を生じさせると、ＥＬ層に陽極側から正孔が注入され、陰極側から電子が注入される。注入された電子と正孔はＥＬ層において再結合し、ＥＬ層に含まれる発光性の化合物が発光する。 In addition, as a display element included in a display device, a light-emitting element (EL element) using electroluminescence can be applied. The EL element has a layer containing a light-emitting compound (also referred to as “EL layer”) between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side, and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light emitting compound contained in the EL layer emits light.
また、ＥＬ素子は、発光材料が有機化合物であるか、無機化合物であるかによって区別され、一般的に、前者は有機ＥＬ素子、後者は無機ＥＬ素子と呼ばれている。 In addition, EL elements are distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and in general, the former is called an organic EL element and the latter is called an inorganic EL element.
有機ＥＬ素子は、電圧を印加することにより、一方の電極から電子、他方の電極から正孔がそれぞれＥＬ層に注入される。そして、それらキャリア（電子及び正孔）が再結合することにより、発光性の有機化合物が励起状態を形成し、その励起状態が基底状態に戻る際に発光する。このようなメカニズムから、このような発光素子は、電流励起型の発光素子と呼ばれる。 In the organic EL element, electrons are injected from one electrode and holes are injected from the other electrode to the EL layer by applying a voltage. Then, the carriers (electrons and holes) recombine to form an excited state in the light emitting organic compound, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light emitting element is referred to as a current excitation light emitting element.
なお、ＥＬ層は、発光性の化合物以外に、正孔注入性の高い物質、正孔輸送性の高い物質、正孔ブロック材料、電子輸送性の高い物質、電子注入性の高い物質、又はバイポーラ性の物質（電子輸送性及び正孔輸送性が高い物質）等を有していてもよい。 Note that the EL layer may be formed of a substance having a high hole injecting property, a substance having a high hole transporting property, a hole blocking material, a substance having a high electron transporting property, a substance having a high electron injecting property, or a bipolar other than a light emitting compound. It may have a polar substance (a substance having a high electron transporting property and a hole transporting property) or the like.
ＥＬ層は、蒸着法（真空蒸着法を含む）、転写法、印刷法、インクジェット法、塗布法等の方法で形成することができる。 The EL layer can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
無機ＥＬ素子は、その素子構成により、分散型無機ＥＬ素子と薄膜型無機ＥＬ素子とに分類される。分散型無機ＥＬ素子は、発光材料の粒子をバインダ中に分散させた発光層を有するものであり、発光メカニズムはドナー準位とアクセプター準位を利用するドナー−アクセプター再結合型発光である。薄膜型無機ＥＬ素子は、発光層を誘電体層で挟み込み、さらにそれを電極で挟んだ構造であり、発光メカニズムは金属イオンの内殻電子遷移を利用する局在型発光である。なお、ここでは、発光素子として有機ＥＬ素子を用いて説明する。 Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film-type inorganic EL element according to the element configuration. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission utilizing a donor level and an acceptor level. The thin film type inorganic EL element has a structure in which the light emitting layer is sandwiched by dielectric layers and further sandwiched by electrodes, and the light emission mechanism is localized light emission utilizing inner shell electron transition of metal ions. Here, an organic EL element is described as a light emitting element.
発光素子は発光を取り出すために、一対の電極の少なくとも一方の電極が透明であればよい。そして、基板上にトランジスタ及び発光素子を形成し、当該基板とは逆側の面から発光を取り出す上面射出（トップエミッション）構造や、基板側の面から発光を取り出す下面射出（ボトムエミッション）構造や、両面から発光を取り出す両面射出（デュアルエミッション）構造の発光素子があり、どの射出構造の発光素子も適用することができる。 In order for the light emitting element to emit light, at least one of the pair of electrodes may be transparent. Then, a transistor and a light emitting element are formed over the substrate, and top emission (top emission) structure in which light emission is extracted from the surface opposite to the substrate, or bottom emission (bottom emission) structure in which light emission is extracted from the surface of the substrate There are light emitting elements having a dual emission structure in which light is emitted from both sides, and any light emitting element having any emission structure can be applied.
図１８（Ｂ）は、表示素子として発光素子を用いた発光表示装置（「ＥＬ表示装置」ともいう。）の一例である。表示素子である発光素子４５１３は、表示部２１５に設けられたトランジスタ４０１０と電気的に接続している。なお発光素子４５１３の構成は、第１の電極層４０３０、発光層４５１１、第２の電極層４０３１の積層構造であるが、この構成に限定されない。発光素子４５１３から取り出す光の方向等に合わせて、発光素子４５１３の構成は適宜変えることができる。 FIG. 18B illustrates an example of a light-emitting display device (also referred to as “EL display device”) using a light-emitting element as a display element. A light emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the display portion 215. Note that the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be changed as appropriate in accordance with the direction of light extracted from the light emitting element 4513 or the like.
隔壁４５１０は、有機絶縁材料、又は無機絶縁材料を用いて形成する。特に感光性の樹脂材料を用い、第１の電極層４０３０上に開口部を形成し、その開口部の側面が連続した曲率を持って形成される傾斜面となるように形成することが好ましい。 The partition 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to form an opening on the first electrode layer 4030 using a photosensitive resin material so that the side surface of the opening is an inclined surface formed with a continuous curvature.
発光層４５１１は、単数の層で構成されていても、複数の層が積層されるように構成されていてもどちらでも良い。 The light emitting layer 4511 may be either a single layer or a plurality of layers stacked.
発光素子４５１３の発光色は、発光層４５１１を構成する材料によって、白、赤、緑、青、シアン、マゼンタ、又は黄等とすることができる。 The emission color of the light-emitting element 4513 can be white, red, green, blue, cyan, magenta, yellow, or the like depending on the material of the light-emitting layer 4511.
カラー表示を実現する方法としては、発光色が白色の発光素子４５１３と着色層を組み合わせて行う方法と、画素毎に発光色の異なる発光素子４５１３を設ける方法がある。前者の方法は後者の方法よりも生産性が高い。一方、後者の方法では画素毎に発光層４５１１を作り分ける必要があるため、前者の方法よりも生産性が劣る。ただし、後者の方法では、前者の方法よりも色純度の高い発光色を得ることができる。後者の方法に加えて、発光素子４５１３にマイクロキャビティ構造を付与することにより色純度をさらに高めることができる。 As a method of realizing color display, there are a method of combining a light emitting element 4513 of white light emitting color and a coloring layer, and a method of providing a light emitting element 4513 of different light emitting color for each pixel. The former method is more productive than the latter method. On the other hand, in the latter method, since it is necessary to separately form the light emitting layer 4511 for each pixel, the productivity is lower than the former method. However, in the latter method, luminescent color having higher color purity can be obtained than in the former method. In addition to the latter method, the color purity can be further enhanced by providing the light emitting element 4513 with a microcavity structure.
なお、発光層４５１１は、量子ドット等の無機化合物を有していてもよい。例えば、量子ドットを発光層に用いることで、発光材料として機能させることもできる。 Note that the light emitting layer 4511 may have an inorganic compound such as a quantum dot. For example, by using a quantum dot for the light-emitting layer, it can also function as a light-emitting material.
発光素子４５１３に酸素、水素、水分、二酸化炭素等が侵入しないように、第２の電極層４０３１及び隔壁４５１０上に保護層を形成してもよい。保護層としては、窒化シリコン、窒化酸化シリコン、酸化アルミニウム、窒化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、ＤＬＣ（Ｄｉａｍｏｎｄ　Ｌｉｋｅ　Ｃａｒｂｏｎ）等を形成することができる。また、第１の基板４００１、第２の基板４００６、及びシール材４００５によって封止された空間には充填材４５１４が設けられ密封されている。このように、外気に曝されないように気密性が高く、脱ガスの少ない保護フィルム（貼り合わせフィルム、紫外線硬化樹脂フィルム等）やカバー材でパッケージング（封入）することが好ましい。 A protective layer may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. A filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed. As described above, it is preferable to package (encapsulate) with a protective film (such as a laminated film or an ultraviolet curable resin film) or a cover material which has high airtightness and low degassing so as not to be exposed to the outside air.
充填材４５１４としては窒素やアルゴン等の不活性な気体の他に、紫外線硬化樹脂又は熱硬化樹脂を用いることができ、ＰＶＣ（ポリビニルクロライド）、アクリル系樹脂、ポリイミド、エポキシ系樹脂、シリコーン系樹脂、ＰＶＢ（ポリビニルブチラル）又はＥＶＡ（エチレンビニルアセテート）等を用いることができる。また、充填材４５１４に乾燥剤が含まれていてもよい。 As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin , PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) or the like can be used. In addition, the filler 4514 may contain a desiccant.
シール材４００５には、ガラスフリット等のガラス材料や、二液混合型の樹脂等の常温で硬化する硬化樹脂、光硬化性の樹脂、熱硬化性の樹脂等の樹脂材料を用いることができる。また、シール材４００５に乾燥剤が含まれていてもよい。 For the sealant 4005, a glass material such as a glass frit, a cured resin such as a two-component mixed resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. In addition, the sealant 4005 may contain a desiccant.
また、必要であれば、発光素子の射出面に偏光板、又は円偏光板（楕円偏光板を含む）、位相差板（λ／４板、λ／２板）、カラーフィルタ等の光学フィルムを適宜設けてもよい。また、偏光板又は円偏光板に反射防止膜を設けてもよい。例えば、表面の凹凸により反射光を拡散し、映り込みを低減できるアンチグレア処理を施すことができる。 In addition, if necessary, an optical film such as a polarizing plate or a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, etc. on the emission surface of the light emitting element You may provide suitably. In addition, an antireflective film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare processing can be performed to diffuse reflected light and reduce reflection due to the unevenness of the surface.
また、発光素子をマイクロキャビティ構造とすることで、色純度の高い光を取り出すことができる。また、マイクロキャビティ構造とカラーフィルタを組み合わせることで、映り込みが低減し、表示画像の視認性を高めることができる。 In addition, light with high color purity can be extracted by forming the light-emitting element with a microcavity structure. In addition, by combining the microcavity structure and the color filter, reflection can be reduced, and the visibility of a display image can be enhanced.
表示素子に電圧を印加する第１の電極層及び第２の電極層（画素電極層、共通電極層、対向電極層等ともいう）においては、取り出す光の方向、電極層が設けられる場所、及び電極層のパターン構造によって透光性、反射性を選択すればよい。 In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, and the like) which apply voltage to the display element, the direction of light to be extracted, a location where the electrode layer is provided, Translucency and reflectivity may be selected depending on the pattern structure of the electrode layer.
第１の電極層４０３０、第２の電極層４０３１は、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、インジウム錫酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、酸化ケイ素を添加したインジウム錫酸化物等の透光性を有する導電性材料を用いることができる。 The first electrode layer 4030 and the second electrode layer 403 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium containing titanium oxide A light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.
また、第１の電極層４０３０、第２の電極層４０３１はタングステン（Ｗ）、モリブデン（Ｍｏ）、ジルコニウム（Ｚｒ）、ハフニウム（Ｈｆ）、バナジウム（Ｖ）、ニオブ（Ｎｂ）、タンタル（Ｔａ）、クロム（Ｃｒ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、チタン（Ｔｉ）、白金（Ｐｔ）、アルミニウム（Ａｌ）、銅（Ｃｕ）、銀（Ａｇ）等の金属、又はその合金、もしくはその金属窒化物から一種以上を用いて形成することができる。 The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta) Metals such as chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), or alloys thereof, or It can be formed using one or more of metal nitrides.
また、第１の電極層４０３０、第２の電極層４０３１として、導電性高分子（導電性ポリマーともいう）を含む導電性組成物を用いて形成することができる。導電性高分子としては、いわゆるπ電子共役系導電性高分子を用いることができる。例えば、ポリアニリン若しくはその誘導体、ポリピロール若しくはその誘導体、ポリチオフェン若しくはその誘導体、又は、アニリン、ピロール及びチオフェンの２種以上からなる共重合体若しくはその誘導体等があげられる。 Alternatively, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). As the conductive high molecule, a so-called π electron conjugated conductive high molecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, or a copolymer of two or more of aniline, pyrrole and thiophene or a derivative thereof can be given.
また、トランジスタは静電気等により破壊されやすいため、駆動回路保護用の保護回路を設けることが好ましい。保護回路は、非線形素子を用いて構成することが好ましい。 In addition, since the transistor is easily broken by static electricity or the like, a protective circuit for protecting the driver circuit is preferably provided. The protection circuit is preferably configured using a non-linear element.
本実施の形態は、他の実施の形態等に記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
（実施の形態３）
本実施の形態では、上記実施の形態に示した各トランジスタに置き換えて用いることのできるトランジスタの一例について、図面を用いて説明する。 Third Embodiment
In this embodiment, an example of a transistor that can be used in place of each of the transistors described in the above embodiments is described with reference to drawings.
本発明の一態様の表示装置は、ボトムゲート型のトランジスタや、トップゲート型トランジスタ等の様々な形態のトランジスタを用いて作製することができる。よって、既存の製造ラインに合わせて、使用する半導体層の材料やトランジスタ構造を容易に置き換えることができる。 The display device of one embodiment of the present invention can be manufactured using various types of transistors such as a bottom gate transistor and a top gate transistor. Therefore, according to the existing manufacturing line, the material of the semiconductor layer to be used and the transistor structure can be easily replaced.
〔ボトムゲート型トランジスタ〕
図１９（Ａ１）は、ボトムゲート型のトランジスタの一種であるチャネル保護型のトランジスタ８１０のチャネル長方向の断面図である。図１９（Ａ１）において、トランジスタ８１０は基板７７１上に形成されている。また、トランジスタ８１０は、基板７７１上に絶縁層７７２を介して電極７４６を有する。また、電極７４６上に絶縁層７２６を介して半導体層７４２を有する。電極７４６はゲート電極として機能できる。絶縁層７２６はゲート絶縁層として機能できる。 Bottom-gate transistor
FIG. 19A1 is a cross-sectional view in the channel length direction of a channel protective transistor 810 which is a kind of bottom gate transistor. In FIG. 19A1, the transistor 810 is formed over a substrate 771. In addition, the transistor 810 includes an electrode 746 over the substrate 771 with the insulating layer 772 interposed therebetween. In addition, the semiconductor layer 742 is provided over the electrode 746 with the insulating layer 726 interposed therebetween. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer.
また、半導体層７４２のチャネル形成領域上に絶縁層７４１を有する。また、半導体層７４２の一部と接して、絶縁層７２６上に電極７４４ａ及び電極７４４ｂを有する。電極７４４ａは、ソース電極又はドレイン電極の一方として機能できる。電極７４４ｂは、ソース電極又はドレイン電極の他方として機能できる。電極７４４ａの一部、及び電極７４４ｂの一部は、絶縁層７４１上に形成される。 In addition, the insulating layer 741 is provided over the channel formation region of the semiconductor layer 742. In addition, an electrode 744 a and an electrode 744 b are provided over the insulating layer 726 in contact with part of the semiconductor layer 742. The electrode 744a can function as one of a source electrode and a drain electrode. The electrode 744 b can function as the other of the source electrode and the drain electrode. A portion of the electrode 744 a and a portion of the electrode 744 b are formed over the insulating layer 741.
絶縁層７４１は、チャネル保護層として機能できる。チャネル形成領域上に絶縁層７４１を設けることで、電極７４４ａ及び電極７４４ｂの形成時に生じる半導体層７４２の露出を防ぐことができる。よって、電極７４４ａ及び電極７４４ｂの形成時に、半導体層７４２のチャネル形成領域がエッチングされることを防ぐことができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現することができる。 The insulating layer 741 can function as a channel protective layer. By providing the insulating layer 741 over the channel formation region, exposure of the semiconductor layer 742 which is generated at the time of formation of the electrode 744a and the electrode 744b can be prevented. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrode 744a and the electrode 744b are formed. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
また、トランジスタ８１０は、電極７４４ａ、電極７４４ｂ及び絶縁層７４１上に絶縁層７２８を有し、絶縁層７２８の上に絶縁層７２９を有する。 In addition, the transistor 810 includes the insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and the insulating layer 729 over the insulating layer 728.
半導体層７４２に酸化物半導体を用いる場合、電極７４４ａ及び電極７４４ｂの、少なくとも半導体層７４２と接する部分に、半導体層７４２の一部から酸素を奪い、酸素欠損を生じさせることが可能な材料を用いることが好ましい。半導体層７４２中の酸素欠損が生じた領域はキャリア濃度が増加し、当該領域はｎ型化し、ｎ型領域（ｎ＋層）となる。したがって、当該領域はソース領域又はドレイン領域として機能することができる。半導体層７４２に酸化物半導体を用いる場合、半導体層７４２から酸素を奪い、酸素欠損を生じさせることが可能な材料の一例として、タングステン、チタン等を挙げることができる。 In the case where an oxide semiconductor is used for the semiconductor layer 742, a part of the semiconductor layer 742 can be deprived of oxygen and oxygen deficiency can be generated in at least a portion of the electrode 744 a and the electrode 744 b in contact with the semiconductor layer 742. Is preferred. The region of the semiconductor layer 742 in which oxygen vacancies occur has an increased carrier concentration, and the region becomes n-type to become an n-type region (n + layer). Thus, the region can function as a source region or a drain region. In the case of using an oxide semiconductor for the semiconductor layer 742, tungsten, titanium, or the like can be given as an example of a material that can deprive the semiconductor layer 742 of oxygen and cause oxygen vacancies.
半導体層７４２にソース領域及びドレイン領域が形成されることにより、電極７４４ａ及び電極７４４ｂと半導体層７４２の接触抵抗を低減することができる。よって、電界効果移動度や、しきい値電圧等の、トランジスタの電気特性を良好なものとすることができる。 By forming the source region and the drain region in the semiconductor layer 742, the contact resistance between the electrode 744 a and the electrode 744 b and the semiconductor layer 742 can be reduced. Accordingly, electrical characteristics of the transistor, such as field effect mobility and threshold voltage, can be improved.
半導体層７４２にシリコン等の半導体を用いる場合は、半導体層７４２と電極７４４ａの間、及び半導体層７４２と電極７４４ｂの間に、ｎ型半導体又はｐ型半導体として機能する層を設けることが好ましい。ｎ型半導体又はｐ型半導体として機能する層は、トランジスタのソース領域又はドレイン領域として機能することができる。 In the case where a semiconductor such as silicon is used for the semiconductor layer 742, a layer functioning as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744 a and between the semiconductor layer 742 and the electrode 744 b. A layer functioning as an n-type semiconductor or a p-type semiconductor can function as a source region or a drain region of a transistor.
絶縁層７２９は、外部からのトランジスタへの不純物の拡散を防ぐ、又は低減する機能を有する材料を用いて形成することが好ましい。なお、必要に応じて絶縁層７２９を省略することもできる。 The insulating layer 729 is preferably formed using a material having a function of preventing or reducing diffusion of impurities into the transistor from the outside. Note that the insulating layer 729 can be omitted as needed.
図１９（Ａ２）に示すトランジスタ８１１は、絶縁層７２９上にバックゲート電極として機能できる電極７２３を有する点が、トランジスタ８１０と異なる。電極７２３は、電極７４６と同様の材料及び方法で形成することができる。 A transistor 811 illustrated in FIG. 19A2 is different from the transistor 810 in that an electrode 723 which can function as a back gate electrode is provided over the insulating layer 729. The electrode 723 can be formed by the same material and method as the electrode 746.
一般に、バックゲート電極は導電層で形成され、ゲート電極とバックゲート電極で半導体層のチャネル形成領域を挟むように配置される。よって、バックゲート電極は、ゲート電極と同様に機能させることができる。バックゲート電極の電位は、ゲート電極の電位と同電位としてもよいし、接地電位（ＧＮＤ電位）や、任意の電位としてもよい。また、バックゲート電極の電位をゲート電極と連動させず独立して変化させることで、トランジスタのしきい値電圧を変化させることができる。 In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode are disposed so as to sandwich the channel formation region of the semiconductor layer. Thus, the back gate electrode can function similarly to the gate electrode. The potential of the back gate electrode may be the same as the potential of the gate electrode, or may be the ground potential (GND potential) or any potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently without interlocking with the gate electrode.
また、電極７４６及び電極７２３は、どちらもゲート電極として機能することができる。よって、絶縁層７２６、絶縁層７２８、及び絶縁層７２９は、それぞれがゲート絶縁層として機能することができる。なお、電極７２３は、絶縁層７２８と絶縁層７２９の間に設けてもよい。 Further, the electrode 746 and the electrode 723 can both function as a gate electrode. Thus, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each function as a gate insulating layer. Note that the electrode 723 may be provided between the insulating layer 728 and the insulating layer 729.
なお、電極７４６又は電極７２３の一方を、「ゲート電極」という場合、他方を「バックゲート電極」という。例えば、トランジスタ８１１において、電極７２３を「ゲート電極」という場合、電極７４６を「バックゲート電極」という。また、電極７２３を「ゲート電極」として用いる場合は、トランジスタ８１１をトップゲート型のトランジスタの一種と考えることができる。また、電極７４６及び電極７２３のどちらか一方を、「第１のゲート電極」といい、他方を「第２のゲート電極」という場合がある。 Note that when one of the electrode 746 or the electrode 723 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 811, when the electrode 723 is referred to as a “gate electrode”, the electrode 746 is referred to as a “back gate electrode”. In the case where the electrode 723 is used as a “gate electrode”, the transistor 811 can be considered as a kind of top gate transistor. Further, one of the electrode 746 and the electrode 723 may be referred to as “first gate electrode”, and the other may be referred to as “second gate electrode”.
半導体層７４２を挟んで電極７４６及び電極７２３を設けることで、更には、電極７４６及び電極７２３を同電位とすることで、半導体層７４２においてキャリアの流れる領域が膜厚方向においてより大きくなるため、キャリアの移動量が増加する。この結果、トランジスタ８１１のオン電流が大きくなると共に、電界効果移動度が高くなる。 By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, and by setting the electrode 746 and the electrode 723 to the same potential, the region where carriers flow in the semiconductor layer 742 becomes larger in the film thickness direction. The amount of carrier movement increases. As a result, the on current of the transistor 811 is increased, and the field effect mobility is increased.
したがって、トランジスタ８１１は、占有面積に対して大きいオン電流を有するトランジスタである。すなわち、求められるオン電流に対して、トランジスタ８１１の占有面積を小さくすることができる。本発明の一態様によれば、トランジスタの占有面積を小さくすることができる。よって、本発明の一態様によれば、集積度の高い半導体装置を実現することができる。 Therefore, the transistor 811 is a transistor having a large on current with respect to the occupied area. That is, the area occupied by the transistor 811 can be reduced with respect to the on current required. According to one embodiment of the present invention, the area occupied by the transistor can be reduced. Thus, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
また、ゲート電極とバックゲート電極は導電層で形成されるため、トランジスタの外部で生じる電界が、チャネルが形成される半導体層に作用しないようにする機能（特に静電気等に対する電界遮蔽機能）を有する。なお、バックゲート電極を半導体層よりも大きく形成し、バックゲート電極で半導体層を覆うことで、電界遮蔽機能を高めることができる。 In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they have a function to prevent an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (in particular, an electric field shielding function against static electricity or the like). . Note that the electric field shielding function can be enhanced by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.
また、バックゲート電極を、遮光性を有する導電膜で形成することで、バックゲート電極側から半導体層に光が入射することを防ぐことができる。よって、半導体層の光劣化を防ぎ、トランジスタのしきい値電圧がシフトする等の電気特性の劣化を防ぐことができる。 In addition, when the back gate electrode is formed using a light-shielding conductive film, light can be prevented from entering the semiconductor layer from the back gate electrode side. Accordingly, light deterioration of the semiconductor layer can be prevented, and deterioration of the electrical characteristics such as a shift in threshold voltage of the transistor can be prevented.
本発明の一態様によれば、信頼性の良好なトランジスタを実現することができる。また、信頼性の良好な半導体装置を実現することができる。 According to one embodiment of the present invention, a highly reliable transistor can be realized. In addition, a highly reliable semiconductor device can be realized.
図１９（Ｂ１）は、図１９（Ａ１）とは異なる構成のチャネル保護型のトランジスタ８２０のチャネル長方向の断面図である。トランジスタ８２０は、トランジスタ８１０とほぼ同様の構造を有しているが、絶縁層７４１が半導体層７４２の端部を覆っている点が異なる。また、半導体層７４２と重なる領域を有する絶縁層７４１の一部を選択的に除去して形成した開口部において、半導体層７４２と電極７４４ａが電気的に接続している。また、半導体層７４２と重なる領域を有する絶縁層７４１の一部を選択的に除去して形成した他の開口部において、半導体層７４２と電極７４４ｂが電気的に接続している。絶縁層７４１の、チャネル形成領域と重なる領域は、チャネル保護層として機能できる。 FIG. 19B1 is a cross-sectional view in the channel length direction of a channel protective transistor 820 having a different structure from that in FIG. 19A1. The transistor 820 has substantially the same structure as the transistor 810, except that the insulating layer 741 covers an end portion of the semiconductor layer 742. The semiconductor layer 742 and the electrode 744 a are electrically connected to each other in an opening formed by selectively removing part of the insulating layer 741 which has a region overlapping with the semiconductor layer 742. The semiconductor layer 742 and the electrode 744 b are electrically connected to each other in another opening which is formed by selectively removing part of the insulating layer 741 which has a region overlapping with the semiconductor layer 742. The region of the insulating layer 741 overlapping with the channel formation region can function as a channel protective layer.
図１９（Ｂ２）に示すトランジスタ８２１は、絶縁層７２９上にバックゲート電極として機能できる電極７２３を有する点が、トランジスタ８２０と異なる。 The transistor 821 illustrated in FIG. 19B2 is different from the transistor 820 in that the electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
絶縁層７４１を設けることで、電極７４４ａ及び電極７４４ｂの形成時に生じる半導体層７４２の露出を防ぐことができる。よって、電極７４４ａ及び電極７４４ｂの形成時に半導体層７４２の薄膜化を防ぐことができる。 The insulating layer 741 can prevent the semiconductor layer 742 from being exposed at the time of formation of the electrodes 744a and 744b. Thus, thinning of the semiconductor layer 742 can be prevented at the time of formation of the electrode 744a and the electrode 744b.
また、トランジスタ８２０及びトランジスタ８２１は、トランジスタ８１０及びトランジスタ８１１よりも、電極７４４ａと電極７４６の間の距離と、電極７４４ｂと電極７４６の間の距離と、が長くなる。よって、電極７４４ａと電極７４６の間に生じる寄生容量を小さくすることができる。また、電極７４４ｂと電極７４６の間に生じる寄生容量を小さくすることができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現できる。 Further, in the transistors 820 and 821, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer than those in the transistors 810 and 811. Thus, parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. In addition, parasitic capacitance generated between the electrode 744 b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized.
図１９（Ｃ１）は、ボトムゲート型のトランジスタの１つであるチャネルエッチング型のトランジスタ８２５のチャネル長方向の断面図である。トランジスタ８２５は、絶縁層７４１を設けずに電極７４４ａ及び電極７４４ｂを形成する。このため、電極７４４ａ及び電極７４４ｂの形成時に露出する半導体層７４２の一部がエッチングされる場合がある。一方、絶縁層７４１を設けないため、トランジスタの生産性を高めることができる。 FIG. 19C1 is a cross-sectional view in the channel length direction of a channel-etched transistor 825 which is one of bottom-gate transistors. The transistor 825 forms the electrode 744a and the electrode 744b without providing the insulating layer 741. Therefore, part of the semiconductor layer 742 exposed when the electrode 744a and the electrode 744b are formed may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be improved.
図１９（Ｃ２）に示すトランジスタ８２６は、絶縁層７２９上にバックゲート電極として機能できる電極７２３を有する点が、トランジスタ８２５と異なる。 A transistor 826 illustrated in FIG. 19C2 is different from the transistor 825 in that the electrode 723 which can function as a back gate electrode is provided over the insulating layer 729.
図２０（Ａ１）乃至（Ｃ２）にトランジスタ８１０、トランジスタ８１１、トランジスタ８２０、トランジスタ８２１、及びトランジスタ８２５、トランジスタ８２６のチャネル幅方向の断面図をそれぞれ示す。 20A1 to 20C2 are cross-sectional views in the channel width direction of the transistor 810, the transistor 811, the transistor 820, the transistor 821, the transistor 825, and the transistor 826, respectively.
図２０（Ｂ２）、（Ｃ２）に示す構造では、ゲート電極とバックゲート電極とが接続され、ゲート電極とバックゲート電極との電位が同電位となる。また、半導体層７４２は、ゲート電極とバックゲート電極とに挟まれている。 In the structures shown in FIGS. 20B2 and 20C2, the gate electrode and the back gate electrode are connected, and the gate electrode and the back gate electrode have the same potential. The semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.
ゲート電極及びバックゲート電極のそれぞれのチャネル幅方向の長さは、半導体層７４２のチャネル幅方向の長さよりも長く、半導体層７４２のチャネル幅方向全体は、絶縁層７２６、絶縁層７４１、絶縁層７２８、及び絶縁層７２９を間に挟んでゲート電極及びバックゲート電極に覆われた構成である。 The length in the channel width direction of each of the gate electrode and the back gate electrode is longer than the length in the channel width direction of the semiconductor layer 742, and the entire channel width direction of the semiconductor layer 742 is the insulating layer 726, the insulating layer 741, the insulating layer 728 and the insulating layer 729 are interposed between the gate electrode and the back gate electrode.
当該構成とすることで、トランジスタに含まれる半導体層７４２を、ゲート電極及びバックゲート電極の電界によって電気的に取り囲むことができる。 With this structure, the semiconductor layer 742 included in the transistor can be electrically surrounded by the electric field of the gate electrode and the back gate electrode.
トランジスタ８１１、トランジスタ８２１、及びトランジスタ８２６のように、ゲート電極及びバックゲート電極の電界によって、チャネル形成領域が形成される半導体層７４２を電気的に取り囲むトランジスタのデバイス構造をＳｕｒｒｏｕｎｄｅｄ　ｃｈａｎｎｅｌ（Ｓ−ｃｈａｎｎｅｌ）構造ということができる。 Similar to the transistor 811, the transistor 821, and the transistor 826, a device structure of a transistor that electrically surrounds a semiconductor layer 742 in which a channel formation region is formed by an electric field of a gate electrode and a back gate electrode It can be called structure.
Ｓ−ｃｈａｎｎｅｌ構造とすることで、ゲート電極及びバックゲート電極の一方又は双方によってチャネルを誘起させるための電界を効果的に半導体層７４２に印加することができるため、トランジスタの電流駆動能力が向上し、高いオン電流特性を得ることが可能となる。また、オン電流を高くすることが可能であるため、トランジスタを微細化することが可能となる。また、Ｓ−ｃｈａｎｎｅｌ構造とすることで、トランジスタの機械的強度を高めることができる。 With the S-channel structure, an electric field for inducing a channel can be effectively applied to the semiconductor layer 742 by one or both of the gate electrode and the back gate electrode, so that the current drive capability of the transistor is improved. It is possible to obtain high on-current characteristics. In addition, since the on current can be increased, the transistor can be miniaturized. In addition, with the S-channel structure, mechanical strength of the transistor can be increased.
〔トップゲート型トランジスタ〕
図２１（Ａ１）に例示するトランジスタ８４２は、トップゲート型のトランジスタの１つである。トランジスタ８４２は、絶縁層７２９を形成した後に電極７４４ａ及び電極７４４ｂを形成する。電極７４４ａ及び電極７４４ｂは、絶縁層７２８及び絶縁層７２９に形成した開口部において半導体層７４２と電気的に接続する。 [Top gate type transistor]
A transistor 842 illustrated in FIG. 21A1 is one of top-gate transistors. The transistor 842 forms the electrode 744a and the electrode 744b after forming the insulating layer 729. The electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in an opening formed in the insulating layer 728 and the insulating layer 729.
また、電極７４６と重ならない絶縁層７２６の一部を除去し、電極７４６と、除去した残りの絶縁層７２６とをマスクとして用いて不純物を半導体層７４２に導入することで、半導体層７４２中に自己整合（セルフアライメント）的に不純物領域を形成することができる。トランジスタ８４２は、絶縁層７２６が電極７４６の端部を越えて延伸する領域を有する。半導体層７４２の絶縁層７２６を介して不純物が導入された領域の不純物濃度は、絶縁層７２６を介さずに不純物が導入された領域よりも小さくなる。半導体層７４２は、電極７４６と重ならない領域にＬＤＤ（Ｌｉｇｈｔｌｙ　Ｄｏｐｅｄ　Ｄｒａｉｎ）領域が形成される。 Further, a portion of the insulating layer 726 which does not overlap with the electrode 746 is removed, and an impurity is introduced into the semiconductor layer 742 using the electrode 746 and the remaining insulating layer 726 as a mask. The impurity region can be formed in a self alignment manner (self alignment). The transistor 842 has a region where the insulating layer 726 extends beyond the end of the electrode 746. The impurity concentration of the region into which the impurity is introduced through the insulating layer 726 of the semiconductor layer 742 is smaller than that of the region into which the impurity is introduced without through the insulating layer 726. In the semiconductor layer 742, a lightly doped drain (LDD) region is formed in a region which does not overlap with the electrode 746.
図２１（Ａ２）に示すトランジスタ８４３は、電極７２３を有する点がトランジスタ８４２と異なる。トランジスタ８４３は、基板７７１の上に形成された電極７２３を有する。電極７２３は、絶縁層７７２を介して半導体層７４２と重なる領域を有する。電極７２３は、バックゲート電極として機能することができる。 A transistor 843 illustrated in FIG. 21A2 is different from the transistor 842 in that the electrode 723 is provided. The transistor 843 has an electrode 723 formed over the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. The electrode 723 can function as a back gate electrode.
また、図２１（Ｂ１）に示すトランジスタ８４４、及び図２１（Ｂ２）に示すトランジスタ８４５のように、電極７４６と重ならない領域の絶縁層７２６を全て除去してもよい。また、図２１（Ｃ１）に示すトランジスタ８４６、及び図２１（Ｃ２）に示すトランジスタ８４７のように、絶縁層７２６を残してもよい。 Alternatively, as in the transistor 844 illustrated in FIG. 21B1 and the transistor 845 illustrated in FIG. 21B2, all the insulating layer 726 in a region which does not overlap with the electrode 746 may be removed. Alternatively, as in the transistor 846 illustrated in FIG. 21C1 and the transistor 847 illustrated in FIG. 21C2, the insulating layer 726 may be left.
トランジスタ８４２乃至トランジスタ８４７も、電極７４６を形成した後に、電極７４６をマスクとして用いて不純物を半導体層７４２に導入することで、半導体層７４２中に自己整合的に不純物領域を形成することができる。本発明の一態様によれば、電気特性の良好なトランジスタを実現することができる。また、本発明の一態様によれば、集積度の高い半導体装置を実現することができる。 With the transistors 842 to 847, after forming the electrode 746, an impurity is introduced into the semiconductor layer 742 using the electrode 746 as a mask, so that the impurity region can be formed in the semiconductor layer 742 in a self-aligned manner. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Further, according to one embodiment of the present invention, a semiconductor device with a high degree of integration can be realized.
図２２（Ａ１）乃至（Ｃ２）にトランジスタ８４２乃至トランジスタ８４７のチャネル幅方向の断面図をそれぞれ示す。 22A1 to 22C2 are cross-sectional views in the channel width direction of the transistors 842 to 847, respectively.
トランジスタ８４３、トランジスタ８４５、及びトランジスタ８４７は、それぞれ先に説明したＳ−ｃｈａｎｎｅｌ構造である。ただし、これに限定されず、トランジスタ８４３、トランジスタ８４５、及びトランジスタ８４７をＳ−ｃｈａｎｎｅｌ構造としなくてもよい。 The transistor 843, the transistor 845, and the transistor 847 each have the S-channel structure described above. However, without limitation thereto, the transistor 843, the transistor 845, and the transistor 847 may not have an S-channel structure.
本実施の形態は、他の実施の形態等に記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
（実施の形態４）
本実施の形態では、ＯＳトランジスタの詳細な構成例について説明する。 Embodiment 4
In this embodiment, a detailed configuration example of the OS transistor will be described.
ＯＳトランジスタが有する半導体層は、例えばインジウム、亜鉛及びＭ（アルミニウム、チタン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、セリウム、スズ、ネオジム又はハフニウム等の金属）を含むＩｎ−Ｍ−Ｚｎ系酸化物で表記される膜とすることができる。 The semiconductor layer included in the OS transistor is, for example, an In-M-Zn-based oxide containing indium, zinc and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium or hafnium). The film can be represented by
半導体層を構成する酸化物半導体がＩｎ−Ｍ−Ｚｎ系酸化物の場合、Ｉｎ−Ｍ−Ｚｎ酸化物を成膜するために用いるスパッタリングターゲットの金属元素の原子数比は、Ｉｎ≧Ｍ、Ｚｎ≧Ｍを満たすことが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、Ｉｎ：Ｍ：Ｚｎ＝１：１：１、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、Ｉｎ：Ｍ：Ｚｎ＝４：２：３、Ｉｎ：Ｍ：Ｚｎ＝４：２：４．１、Ｉｎ：Ｍ：Ｚｎ＝５：１：６、Ｉｎ：Ｍ：Ｚｎ＝５：１：７、Ｉｎ：Ｍ：Ｚｎ＝５：１：８等が好ましい。なお、成膜される半導体層の原子数比はそれぞれ、上記のスパッタリングターゲットに含まれる金属元素の原子数比のプラスマイナス４０％の変動を含む。 In the case where the oxide semiconductor forming the semiconductor layer is an In-M-Zn-based oxide, the atomic ratio of metal elements in a sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn It is preferable to satisfy ≧ M. The atomic ratio of the metal elements of such a sputtering target is In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2: 3: In: M: Zn = 4: 2: 4: In: M: Zn = 5: 1: 6, In: M: Zn = 5: 1: 7, In: M: Zn = 5: 1: 8 etc. are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target.
半導体層としては、キャリア密度の低い酸化物半導体を用いる。例えば、半導体層は、キャリア密度が１×１０１７／ｃｍ３以下、好ましくは１×１０１５／ｃｍ３以下、さらに好ましくは１×１０１３／ｃｍ３以下、より好ましくは１×１０１１／ｃｍ３以下、さらに好ましくは１×１０１０／ｃｍ３未満であり、１×１０−９／ｃｍ３以上のキャリア密度の酸化物半導体を用いることができる。そのような酸化物半導体を、高純度真性又は実質的に高純度真性な酸化物半導体という。当該酸化物半導体は欠陥準位密度が低く、安定な特性を有する酸化物半導体であるといえる。 For the semiconductor layer, an oxide semiconductor with low carrier density is used. For example, the semiconductor layer has a carrier density of 1 × 10 17 / cm 3 or less, preferably 1 × 10 15 / cm 3 or less, more preferably 1 × 10 13 / cm 3 or less, more preferably 1 × 10 11 / cm 3 3 or less, more preferably less than 1 × 10 10 / cm 3, it is possible to use an oxide semiconductor of 1 × 10 -9 / cm 3 or more carrier density. Such an oxide semiconductor is referred to as a high purity intrinsic or substantially high purity intrinsic oxide semiconductor. The oxide semiconductor has low defect state density and can be said to be an oxide semiconductor having stable characteristics.
なお、これらに限られず、必要とするトランジスタの半導体特性及び電気特性（電界効果移動度、しきい値電圧等）に応じて適切な組成のものを用いればよい。また、必要とするトランジスタの半導体特性を得るために、半導体層のキャリア密度や不純物濃度、欠陥密度、金属元素と酸素の原子数比、原子間距離、密度等を適切なものとすることが好ましい。 Note that the composition is not limited to those described above, and a composition having an appropriate composition may be used according to the semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, and the like) of the required transistor. In addition, in order to obtain semiconductor characteristics of a required transistor, it is preferable to make appropriate the carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like in the semiconductor layer. .
半導体層を構成する酸化物半導体において、第１４族元素の一つであるシリコンや炭素が含まれると、酸素欠損が増加し、ｎ型化してしまう。このため、半導体層におけるシリコンや炭素の濃度（二次イオン質量分析法により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とする。 When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor forming the semiconductor layer, oxygen vacancies increase and n-type conductivity is obtained. Therefore, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less.
また、アルカリ金属及びアルカリ土類金属は、酸化物半導体と結合するとキャリアを生成する場合があり、トランジスタのオフ電流が増大してしまうことがある。このため、半導体層におけるアルカリ金属又はアルカリ土類金属の濃度（二次イオン質量分析法により得られる濃度）を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にする。 In addition, when an alkali metal or an alkaline earth metal is bonded to an oxide semiconductor, a carrier may be generated, which may increase the off-state current of the transistor. Therefore, the concentration of alkali metal or alkaline earth metal (concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less Make it
また、半導体層を構成する酸化物半導体に窒素が含まれていると、キャリアである電子が生じてキャリア密度が増加し、ｎ型化しやすい。この結果、窒素が含まれている酸化物半導体を用いたトランジスタはノーマリーオン特性となりやすい。このため半導体層における窒素濃度（二次イオン質量分析法により得られる濃度）は、５×１０１８ａｔｏｍｓ／ｃｍ３以下にすることが好ましい。 In addition, when nitrogen is contained in the oxide semiconductor included in the semiconductor layer, electrons which are carriers are generated, carrier density is increased, and n-type is easily formed. As a result, a transistor including an oxide semiconductor which contains nitrogen is likely to be normally on. Therefore, the nitrogen concentration (the concentration obtained by secondary ion mass spectrometry) in the semiconductor layer is preferably 5 × 10 18 atoms / cm 3 or less.
また、半導体層は、例えば非単結晶構造でもよい。非単結晶構造は、例えば、ｃ軸に配向した結晶を有するＣＡＡＣ−ＯＳ（Ｃ−Ａｘｉｓ　Ａｌｉｇｎｅｄ　Ｃｒｙｓｔａｌｌｉｎｅ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、多結晶構造、微結晶構造、又は非晶質構造を含む。非単結晶構造において、非晶質構造は最も欠陥準位密度が高く、ＣＡＡＣ−ＯＳは最も欠陥準位密度が低い。 The semiconductor layer may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having a crystal aligned in the c-axis, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect states, and CAAC-OS has the lowest density of defect states.
非晶質構造の酸化物半導体膜は、例えば、原子配列が無秩序であり、結晶成分を有さない。又は、非晶質構造の酸化物膜は、例えば、完全な非晶質構造であり、結晶部を有さない。 The oxide semiconductor film having an amorphous structure has, for example, disordered atomic arrangement and no crystalline component. Alternatively, the oxide film having an amorphous structure has, for example, a completely amorphous structure and no crystal part.
なお、半導体層が、非晶質構造の領域、微結晶構造の領域、多結晶構造の領域、ＣＡＡＣ−ＯＳの領域、単結晶構造の領域のうち、二種以上を有する混合膜であってもよい。混合膜は、例えば上述した領域のうち、いずれか二種以上の領域を含む単層構造、又は積層構造を有する場合がある。 Note that the semiconductor layer may be a mixed film having two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure. Good. The mixed film may have, for example, a single layer structure or a laminated structure including any two or more of the above-described regions.
以下では、非単結晶の半導体層の一態様であるＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ）−ＯＳの構成について説明する。 Hereinafter, a structure of a Cloud-Aligned Composite (CAC) -OS which is one embodiment of a non-single-crystal semiconductor layer is described.
ＣＡＣ−ＯＳとは、例えば、酸化物半導体を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで偏在した材料の一構成である。なお、以下では、酸化物半導体において、一つあるいはそれ以上の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、又はその近傍のサイズで混合した状態をモザイク状、又はパッチ状ともいう。 The CAC-OS is, for example, a configuration of a material in which an element included in an oxide semiconductor is unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that in the following, in the oxide semiconductor, one or more metal elements are unevenly distributed, and a region including the metal element has a size of 0.5 nm or more and 10 nm or less, preferably 1 nm or more and 2 nm or less The state in which they are mixed is also called a mosaic or patch.
なお、酸化物半導体は、少なくともインジウムを含むことが好ましい。特にインジウム及び亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウム等から選ばれた一種、又は複数種が含まれていてもよい。 Note that the oxide semiconductor preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from may be included.
例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳ（ＣＡＣ−ＯＳの中でもＩｎ−Ｇａ−Ｚｎ酸化物を、特にＣＡＣ−ＩＧＺＯと呼称してもよい。）とは、インジウム酸化物（以下、ＩｎＯＸ１（Ｘ１は０よりも大きい実数）とする。）、又はインジウム亜鉛酸化物（以下、ＩｎＸ２ＺｎＹ２ＯＺ２（Ｘ２、Ｙ２、及びＺ２は０よりも大きい実数）とする。）と、ガリウム酸化物（以下、ＧａＯＸ３（Ｘ３は０よりも大きい実数）とする。）、又はガリウム亜鉛酸化物（以下、ＧａＸ４ＺｎＹ４ＯＺ４（Ｘ４、Ｙ４、及びＺ４は０よりも大きい実数）とする。）等と、に材料が分離することでモザイク状となり、モザイク状のＩｎＯＸ１、又はＩｎＸ２ＺｎＹ２ＯＺ２が、膜中に均一に分布した構成（以下、クラウド状ともいう。）である。 For example, CAC-OS in the In-Ga-Zn oxide (an In-Ga-Zn oxide among the CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter referred to as InO). X1 (X1 is a real number greater than 0)) or indium zinc oxide (hereinafter, In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0)) and gallium Oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)), or gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 a real number greater than 0) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1, or in X2 Zn Y2 O Z2 is configured uniformly distributed in the film (hereinafter, cloud-like It is also referred to.).
つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、混合している構成を有する複合酸化物半導体である。なお、本明細書において、例えば、第１の領域の元素Ｍに対するＩｎの原子数比が、第２の領域の元素Ｍに対するＩｎの原子数比よりも大きいことを、第１の領域は、第２の領域と比較して、Ｉｎの濃度が高いとする。 That is, the CAC-OS is a complex oxide semiconductor having a structure in which a region in which GaO X3 is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are mixed. Note that in this specification, for example, the ratio of the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, It is assumed that the concentration of In is higher than that in the region 2.
なお、ＩＧＺＯは通称であり、Ｉｎ、Ｇａ、Ｚｎ、及びＯによる１つの化合物をいう場合がある。代表例として、ＩｎＧａＯ３（ＺｎＯ）ｍ１（ｍ１は自然数）、又はＩｎ（１＋ｘ０）Ｇａ（１−ｘ０）Ｏ３（ＺｎＯ）ｍ０（−１≦ｘ０≦１、ｍ０は任意数）で表される結晶性の化合物が挙げられる。 Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. Representative examples are represented by InGaO 3 (ZnO) m1 (m1 is a natural number), or In (1 + x0) Ga ( 1-x0) O 3 (ZnO) m0 (-1 ≦ x0 ≦ 1, m0 is an arbitrary number) Crystalline compounds are mentioned.
上記結晶性の化合物は、単結晶構造、多結晶構造、又はＣＡＡＣ構造を有する。なお、ＣＡＡＣ構造とは、複数のＩＧＺＯのナノ結晶がｃ軸配向を有し、かつａ−ｂ面においては配向せずに連結した結晶構造である。 The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. Note that the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without orientation in the a-b plane.
一方、ＣＡＣ−ＯＳは、酸化物半導体の材料構成に関する。ＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、及びＯを含む材料構成において、一部にＧａを主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。したがって、ＣＡＣ−ＯＳにおいて、結晶構造は副次的な要素である。 On the other hand, CAC-OS relates to the material configuration of an oxide semiconductor. The CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material configuration including In, Ga, Zn, and O, and nanoparticles composed mainly of In in some components. The area | region observed in shape says the structure currently disperse | distributed to mosaic shape at random, respectively. Therefore, in CAC-OS, the crystal structure is a secondary element.
なお、ＣＡＣ−ＯＳは、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Ｉｎを主成分とする膜と、Ｇａを主成分とする膜との２層からなる構造は、含まない。 Note that CAC-OS does not include a stacked structure of two or more types of films different in composition. For example, a structure including two layers of a film containing In as a main component and a film containing Ga as a main component is not included.
なお、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とは、明確な境界が観察できない場合がある。 In some cases, a clear boundary can not be observed between the region in which GaO X3 is the main component and the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component.
なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、又はマグネシウム等から選ばれた一種、又は複数種が含まれている場合、ＣＡＣ−ＯＳは、一部に該金属元素を主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。 In addition, it is selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium instead of gallium. In the case where one or more of the above components are contained, the CAC-OS is partially observed in the form of nanoparticles having the metal element as a main component, and partially having In as a main component. The area | region observed in particle form says the structure currently each disperse | distributed to mosaic form at random.
ＣＡＣ−ＯＳは、例えば基板を意図的に加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つ又は複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とすることが好ましい。 The CAC-OS can be formed by, for example, a sputtering method under conditions in which the substrate is not intentionally heated. In addition, in the case of forming the CAC-OS by a sputtering method, one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the film forming gas at the time of film formation is preferably as low as possible. For example, the flow rate ratio of the oxygen gas is 0% to 30%, preferably 0% to 10%. .
ＣＡＣ−ＯＳは、Ｘ線回折（ＸＲＤ：Ｘ−ｒａｙ　ｄｉｆｆｒａｃｔｉｏｎ）測定法のひとつであるＯｕｔ−ｏｆ−ｐｌａｎｅ法によるθ／２θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、Ｘ線回折による解析結果から、測定領域のａ−ｂ面方向、及びｃ軸方向の配向は見られないことが分かる。 CAC-OS has a feature that a clear peak is not observed when it is measured using a θ / 2θ scan by the Out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, from the analysis result by X-ray diffraction, it is understood that the orientation in the a-b plane direction and the c-axis direction of the measurement region is not observed.
また、ＣＡＣ−ＯＳは、プローブ径が１ｎｍの電子線（ナノビーム電子線ともいう。）を照射することで得られる電子線回折パターンにおいて、リング状に輝度の高い領域と、該リング領域に複数の輝点が観測される。したがって、電子線回折パターンから、ＣＡＣ−ＯＳの結晶構造が、平面方向、及び断面方向において、配向性を有さないｎｃ（ｎａｎｏ−ｃｒｙｓｔａｌ）構造を有することがわかる。 Further, in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm, the CAC-OS has a ring-like high luminance region and a plurality of ring regions. A bright spot is observed. Therefore, it can be seen from the electron diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and in the cross-sectional direction.
また、例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域とが、偏在し、混合している構造を有することが確認できる。 In addition, for example, in the case of CAC-OS in In-Ga-Zn oxide, GaO X3 is a main component by EDX mapping acquired using energy dispersive X-ray spectroscopy (EDX: Energy Dispersive X-ray spectroscopy) It can be confirmed that the region and the region containing In X 2 Zn Y 2 O Z 2 or In O X 1 as the main component have a structure in which the regions are localized and mixed.
ＣＡＣ−ＯＳは、金属元素が均一に分布したＩＧＺＯ化合物とは異なる構造であり、ＩＧＺＯ化合物と異なる性質を有する。つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３等が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。 The CAC-OS has a structure different from the IGZO compound in which the metal element is uniformly distributed, and has different properties from the IGZO compound. That is, CAC-OS is phase separated into a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component, and a region in which each element is a main component Has a mosaic-like structure.
ここで、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域は、ＧａＯＸ３等が主成分である領域と比較して、導電性が高い領域である。つまり、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域を、キャリアが流れることにより、酸化物半導体としての導電性が発現する。したがって、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域が、酸化物半導体中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the region whose main component is In X2 Zn Y2 O Z2 or InO X1 is a region whose conductivity is higher than the region whose main component is GaO X3 or the like. That is, when carriers flow in a region mainly containing In X2 Zn Y2 O Z2 or InO X1 , conductivity as an oxide semiconductor is exhibited. Accordingly, In X2 Zn Y2 O Z2, or InO X1 is the main component region, that distributed in the cloud-like in the oxide semiconductor, a high field-effect mobility (mu) can be realized.
一方、ＧａＯＸ３等が主成分である領域は、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１が主成分である領域と比較して、絶縁性が高い領域である。つまり、ＧａＯＸ３等が主成分である領域が、酸化物半導体中に分布することで、リーク電流を抑制し、良好なスイッチング動作を実現できる。 On the other hand, the region whose main component is GaO X3 or the like is a region whose insulating property is higher than the region whose main component is In X2 Zn Y2 O Z2 or InO X1 . That is, by distributing a region containing GaO X3 or the like as a main component in the oxide semiconductor, leakage current can be suppressed and favorable switching operation can be realized.
したがって、ＣＡＣ−ＯＳを半導体素子に用いた場合、ＧａＯＸ３等に起因する絶縁性と、ＩｎＸ２ＺｎＹ２ＯＺ２、又はＩｎＯＸ１に起因する導電性とが、相補的に作用することにより、高いオン電流（Ｉｏｎ）、及び高い電界効果移動度（μ）を実現することができる。 Therefore, when CAC-OS is used for a semiconductor element, the insulating property due to GaO X3 and the like and the conductivity due to In X 2 Zn Y 2 O Z 2 or InO X 1 are high by acting complementarily. The on current (I on ) and high field effect mobility (μ) can be realized.
また、ＣＡＣ−ＯＳを用いた半導体素子は、信頼性が高い。したがって、ＣＡＣ−ＯＳは、様々な半導体装置の構成材料として適している。 In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, CAC-OS is suitable as a constituent material of various semiconductor devices.
本実施の形態は、他の実施の形態等に記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
（実施の形態５）
本実施の形態では、本発明の一態様の電子機器について図２３を用いて説明する。 Fifth Embodiment
In this embodiment, an electronic device of one embodiment of the present invention will be described with reference to FIG.
本実施の形態の電子機器は、本発明の一態様の表示装置を有する。これにより、電子機器の表示部に表示される画像の表示品位を高めることができる。 The electronic device of this embodiment includes the display device of one embodiment of the present invention. Thus, the display quality of the image displayed on the display unit of the electronic device can be improved.
本実施の形態の電子機器の表示部には、例えばフルハイビジョン、２Ｋ、４Ｋ、８Ｋ、１６Ｋ、又はそれ以上の解像度を有する画像を表示させることができる。また、表示部の画面サイズは、対角２０インチ以上、対角３０インチ以上、対角５０インチ以上、対角６０インチ以上、又は対角７０インチ以上とすることができる。 An image having a resolution of, for example, full high definition, 2K, 4K, 8K, 16K, or more can be displayed on the display portion of the electronic device of this embodiment. Further, the screen size of the display portion can be 20 inches or more diagonally, 30 inches or more diagonally, 50 inches or more diagonally, 60 inches diagonally or more, or 70 inches diagonally or more.
電子機器としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用等のモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機等の大型ゲーム機等の比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、等が挙げられる。 Examples of the electronic devices include relatively large screens of television devices, desktop or notebook personal computers, monitors for computers, etc., large-sized game machines such as digital signage (Digital Signage), pachinko machines, etc. Other than the provided electronic devices, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, portable information terminals, sound reproduction devices, and the like can be given.
本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で画像や情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを非接触電力伝送に用いてもよい。 The electronic device of one embodiment of the present invention may have an antenna. By receiving the signal with the antenna, the display portion can display an image, information, and the like. In addition, when the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.
本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、におい又は赤外線を測定する機能を含むもの）を有していてもよい。 The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation number, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, inclination, vibration, smell or infrared light.
本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像等）を表示部に表示する機能、タッチパネル機能、カレンダー、日付、又は時刻等を表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラム又はデータを読み出す機能等を有することができる。 The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a calendar, a function of displaying dates, time, etc., a function of executing various software (programs), wireless A communication function, a function of reading a program or data recorded in a recording medium, and the like can be provided.
図２３（Ａ）にテレビジョン装置の一例を示す。テレビジョン装置７１００は、筐体７１０１に表示部７０００が組み込まれている。ここでは、スタンド７１０３により筐体７１０１を支持した構成を示している。 FIG. 23A shows an example of a television set. In the television set 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by the stand 7103 is shown.
表示部７０００に、本発明の一態様の表示装置を適用することができる。 The display device of one embodiment of the present invention can be applied to the display portion 7000.
図２３（Ａ）に示すテレビジョン装置７１００の操作は、筐体７１０１が備える操作スイッチや、別体のリモコン操作機７１１１により行うことができる。又は、表示部７０００にタッチセンサを備えていてもよく、指等で表示部７０００に触れることで操作してもよい。リモコン操作機７１１１は、当該リモコン操作機７１１１から出力する情報を表示する表示部を有していてもよい。リモコン操作機７１１１が備える操作キー又はタッチパネルにより、チャンネル及び音量の操作を行うことができ、表示部７０００に表示される画像を操作することができる。 The television set 7100 illustrated in FIG. 23A can be operated by an operation switch of the housing 7101 or a separate remote controller 7111. Alternatively, the display portion 7000 may be provided with a touch sensor or may be operated by touching the display portion 7000 with a finger or the like. The remote controller 7111 may have a display unit for displaying information output from the remote controller 7111. Channels and volume can be controlled with an operation key or a touch panel of the remote controller 7111, and an image displayed on the display portion 7000 can be manipulated.
なお、テレビジョン装置７１００は、受信機及びモデム等を備えた構成とする。受信機により一般のテレビ放送の受信を行うことができる。また、モデムを介して有線又は無線による通信ネットワークに接続することにより、一方向（送信者から受信者）又は双方向（送信者と受信者間、あるいは受信者間同士等）の情報通信を行うことも可能である。 Note that the television set 7100 is provided with a receiver, a modem, and the like. The receiver can receive a general television broadcast. In addition, by connecting to a wired or wireless communication network via a modem, one-way (sender to receiver) or two-way (sender and receiver, or between receivers, etc.) information communication can be performed. It is also possible.
図２３（Ｂ）に、ノート型パーソナルコンピュータの一例を示す。ノート型パーソナルコンピュータ７２００は、筐体７２１１、キーボード７２１２、ポインティングデバイス７２１３、外部接続ポート７２１４等を有する。筐体７２１１に、表示部７０００が組み込まれている。 FIG. 23B shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.
表示部７０００に、本発明の一態様の表示装置を適用することができる。 The display device of one embodiment of the present invention can be applied to the display portion 7000.
図２３（Ｃ）、（Ｄ）に、デジタルサイネージの一例を示す。 FIGS. 23C and 23D show an example of digital signage.
図２３（Ｃ）に示すデジタルサイネージ７３００は、筐体７３０１、表示部７０００、及びスピーカ７３０３等を有する。さらに、ＬＥＤランプ、操作キー（電源スイッチ、又は操作スイッチを含む）、接続端子、各種センサ、マイクロフォン等を有することができる。 A digital signage 7300 illustrated in FIG. 23C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be included.
図２３（Ｄ）は円柱状の柱７４０１に取り付けられたデジタルサイネージ７４００である。デジタルサイネージ７４００は、柱７４０１の曲面に沿って設けられた表示部７０００を有する。 FIG. 23D shows a digital signage 7400 attached to a cylindrical column 7401. The digital signage 7400 has a display portion 7000 provided along the curved surface of the column 7401.
図２３（Ｃ）、（Ｄ）において、表示部７０００に、本発明の一態様の表示装置を適用することができる。 In FIGS. 23C and 23D, the display device of one embodiment of the present invention can be applied to the display portion 7000.
表示部７０００が広いほど、一度に提供できる情報量を増やすことができる。また、表示部７０００が広いほど、人の目につきやすく、例えば、広告の宣伝効果を高めることができる。 As the display unit 7000 is wider, the amount of information that can be provided at one time can be increased. Also, the wider the display portion 7000, the easier it is for a person to see, and for example, the advertising effect of the advertisement can be enhanced.
表示部７０００にタッチパネルを適用することで、表示部７０００に静止画又は動画を表示するだけでなく、使用者が直感的に操作することができ、好ましい。また、路線情報もしくは交通情報等の情報を提供するための用途に用いる場合には、直感的な操作によりユーザビリティを高めることができる。 By applying a touch panel to the display portion 7000, not only a still image or a moving image can be displayed on the display portion 7000, but also the user can operate intuitively, which is preferable. Moreover, when it uses for the application for providing information, such as route information or traffic information, usability can be improved by intuitive operation.
また、図２３（Ｃ）、（Ｄ）に示すように、デジタルサイネージ７３００又はデジタルサイネージ７４００は、ユーザーが所持するスマートフォン等の情報端末機７３１１又は情報端末機７４１１と無線通信により連携可能であることが好ましい。例えば、表示部７０００に表示される広告の情報を、情報端末機７３１１又は情報端末機７４１１の画面に表示させることができる。また、情報端末機７３１１又は情報端末機７４１１を操作することで、表示部７０００の表示を切り替えることができる。 Also, as shown in FIGS. 23C and 23D, the digital signage 7300 or the digital signage 7400 can cooperate with the information terminal 7311 or information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred. For example, information of an advertisement displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, the display of the display portion 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
また、デジタルサイネージ７３００又はデジタルサイネージ７４００に、情報端末機７３１１又は情報端末機７４１１の画面を操作手段（コントローラ）としたゲームを実行させることもできる。これにより、不特定多数のユーザーが同時にゲームに参加し、楽しむことができる。 In addition, it is possible to make the digital signage 7300 or the digital signage 7400 execute a game in which the screen of the information terminal 7311 or the information terminal 7411 is an operation means (controller). In this way, an unspecified number of users can simultaneously participate in and enjoy the game.
本発明の一態様の表示装置は、家屋もしくはビルの内壁もしくは外壁、又は、車両の内装もしくは外装の曲面に沿って組み込むことができる。 The display device of one embodiment of the present invention can be incorporated along the inner or outer wall of a house or building, or along the curved surface of the interior or exterior of a vehicle.
本実施の形態は、他の実施の形態等に記載した構成と適宜組み合わせて実施することが可能である。 This embodiment can be implemented in appropriate combination with the structures described in the other embodiments and the like.
本実施例では、表示装置が４枚の表示パネルを有する構成である場合に、画像補正を行った結果について説明する。 In this embodiment, when the display device has a configuration having four display panels, the result of image correction will be described.
図２４は、本実施例で画像を表示した表示装置について説明する図である。図２４に示すように、２行２列に表示パネル（表示パネルＤＰ［１，１］、表示パネルＤＰ［２，１］、表示パネルＤＰ［１，２］、及び表示パネルＤＰ［２，２］）を並べた表示装置に画像を表示した。表示パネルには、それぞれ７２０行１２８０列の画素が設けられている。 FIG. 24 is a diagram for explaining a display device displaying an image in the present embodiment. As shown in FIG. 24, the display panel (display panel DP [1, 1], display panel DP [2, 1], display panel DP [1, 2], and display panel DP [2, 2] are arranged in two rows and two columns. The image was displayed on the display apparatus which arranged]. The display panel is provided with pixels of 720 rows and 1280 columns.
ここで、表示パネルＤＰ［１，１］の中で、表示パネルＤＰ［１，１］と表示パネルＤＰ［１，２］との境界から３２０列分の画素が設けられた領域を、境界部２２９Ａとする。また、表示パネルＤＰ［２，１］の中で、表示パネルＤＰ［２，１］と表示パネルＤＰ［２，２］との境界から３２０列分の画素が設けられた領域を、境界部２２９Ｂとする。また、表示パネルＤＰ［１，２］の中で、表示パネルＤＰ［１，１］と表示パネルＤＰ［１，２］との境界から３２０列分の画素が設けられた領域を、境界部２２９Ｃとする。また、表示パネルＤＰ［２，２］の中で、表示パネルＤＰ［２，１］と表示パネルＤＰ［２，２］との境界から３２０列分の画素が設けられた領域を、境界部２２９Ｄとする。 Here, in the display panel DP [1,1], an area provided with pixels for 320 columns from the boundary between the display panel DP [1,1] and the display panel DP [1,2] is a boundary portion. It is assumed that 229A. Further, in the display panel DP [2, 1], an area provided with pixels for 320 columns from the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is a boundary portion 229B. I assume. Further, in the display panel DP [1, 2], an area provided with pixels for 320 columns from the boundary between the display panel DP [1, 1] and the display panel DP [1, 2] is a boundary portion 229C. I assume. Further, in the display panel DP [2, 2], an area provided with pixels for 320 columns from the boundary between the display panel DP [2, 1] and the display panel DP [2, 2] is a boundary portion 229D. I assume.
本実施例では、まず、図１５に示す方法により、各表示パネルについて補正フィルタを作成した。ここで、表示パネルに設けられた画素は、階調値０乃至２５５を表現可能であり、ステップＳ２３及びステップＳ２６で表示した画像は、全ての画素の階調値を１２７とした画像とした。 In the present embodiment, first, a correction filter is created for each display panel by the method shown in FIG. Here, the pixels provided in the display panel can express gradation values 0 to 255, and the images displayed in step S23 and step S26 are images in which the gradation values of all the pixels are 127.
次に、境界部２２９Ａ及び境界部２２９Ｂに設けられた画素に対応するフィルタ値の平均値ＤＡＢと、境界部２２９Ｃ及び境界部２２９Ｄに設けられた画素に対応するフィルタ値の平均値ＤＣＤと、を算出した。その後、表示パネルＤＰ［１，２］及び表示パネルＤＰ［２，２］に設けられた画素に対応するフィルタ値をＤＡＢ／ＤＣＤ倍するように、補正フィルタを修正することにより、新たな補正フィルタを作成した。 Then, the average value D AB of filter values corresponding to the pixels provided in the boundary portion 229A and the boundary portion 229B, and the average value D CD of filter values corresponding to the pixels provided in the boundary portion 229C and the boundary 229D , Was calculated. Thereafter, the filter value as multiplied D AB / D CD corresponding to the pixel provided in the display panel DP [1, 2] and the display panel DP [2, 2], by modifying the correction filter, a new I created a correction filter.
図２５（Ａ）に、図１５に示す方法により作成したフィルタを修正せずに画像を表示した場合の表示結果を示す。図２５（Ｂ）に、図１５に示す方法により作成したフィルタを、上記方法で修正し、新たな補正フィルタを作成して、画像を表示した場合の表示結果を示す。 FIG. 25A shows a display result when an image is displayed without correcting the filter created by the method shown in FIG. FIG. 25B shows a display result when the filter created by the method shown in FIG. 15 is corrected by the above method, a new correction filter is created, and an image is displayed.
図２５（Ａ）に示す画像では、表示パネルのつなぎ目がはっきりと視認された。一方、図２５（Ｂ）に示す画像では、図２５（Ａ）に示す画像と比べて表示パネルのつなぎ目が視認されにくくなり、また表示パネル間の色調のずれが小さくなった。 In the image shown in FIG. 25A, the joints of the display panel were clearly viewed. On the other hand, in the image shown in FIG. 25B, compared with the image shown in FIG. 25A, the joints of the display panels are less visible and the difference in color tone between the display panels is smaller.
本実施例では、表示装置が１枚の表示パネルを有する構成である場合に、当該表示パネルが有する画素から射出される光の輝度分布の測定結果について説明する。 In this embodiment, when the display device has a single display panel, measurement results of the luminance distribution of light emitted from the pixels of the display panel will be described.
本実施例では、図１５に示す方法で作成した補正フィルタにより補正を行った画像を、１枚の表示パネルで表示した。ここで、当該表示パネルに設けられた画素は、階調値０乃至２５５を表現可能であり、ステップＳ２３で表示する画像、及び補正を行った画像は、全ての画素の階調値を１２７とした画像とした。また、ステップＳ２３及びステップＳ２６において、画素から射出される光の輝度は二次元輝度計を用いて測定した。 In the present embodiment, an image corrected by the correction filter created by the method shown in FIG. 15 is displayed on one display panel. Here, the pixels provided in the display panel can express gradation values 0 to 255, and the image to be displayed in step S23 and the image subjected to correction have a gradation value of 127 for all pixels. The image was Moreover, in step S23 and step S26, the luminance of the light emitted from the pixel was measured using a two-dimensional luminance meter.
図２６（Ａ）に、ステップＳ２３において二次元輝度計で取得した、補正前の画像が表示されている表示パネルの輝度データを示す。図２６（Ｂ）に、補正フィルタ作成後に二次元輝度計で取得した、補正後の画像が表示されている表示パネルの輝度データを示す。 FIG. 26A shows luminance data of the display panel on which the image before correction is displayed, which is obtained by the two-dimensional luminance meter in step S23. FIG. 26B shows luminance data of the display panel on which the image after correction is displayed, which is acquired by the two-dimensional luminance meter after the correction filter is created.
表示パネルが補正前の画像を表示している場合、図２６（Ａ）に示すように、表示パネル中央部の輝度が表示パネル周辺部の輝度より高くなった。一方、表示パネルが補正後の画像を表示している場合、図２６（Ｂ）に示すように、補正前より、表示パネル全体において輝度が均一化された。 When the display panel displayed the image before correction, as shown in FIG. 26A, the luminance at the central portion of the display panel was higher than the luminance at the peripheral portion of the display panel. On the other hand, when the display panel is displaying an image after correction, as shown in FIG. 26B, the luminance is uniformed in the entire display panel before the correction.
１０Ａ：表示装置、１０Ｂ：表示装置、２０Ａ：表示部、２０Ｂ：表示部、２０Ｃ：表示部、２１：画素部、２１Ａ：画素部、２１Ｂ：画素部、２２：走査線駆動回路、２２Ａ：走査線駆動回路、２２Ｂ：走査線駆動回路、２３：信号線駆動回路、２３Ａ：信号線駆動回路、２３Ｂ：信号線駆動回路、２４Ａ：タイミングコントローラ、２４Ｂ：タイミングコントローラ、２５：画素、２６：画素、２７：領域、２８Ａ：境界部、２８Ｂ：境界部、２８Ｃ：境界部、２８Ｄ：境界部、２９：表示領域、２９Ａ：境界部、２９Ｂ：境界部、２９Ｃ：境界部、２９Ｄ：境界部、２９Ｅ：境界部、２９Ｆ：境界部、２９Ｇ：境界部、２９Ｈ：境界部、３０Ａ：信号生成部、３０Ｂ：信号生成部、３１：フロントエンド部、３２：デコーダ、３３：処理部、３４：受信部、３５：インターフェース、３６：制御部、４０Ａ：処理部、４０Ｂ：処理部、４５Ａ：分割部、４５Ｂ：分割部、５０：演算処理装置、７２：領域、７３：領域、７４：ＦＰＣ、１０１：トランジスタ、１０２：トランジスタ、１０３：容量素子、１０４：発光素子、１１１：トランジスタ、１１２：トランジスタ、１１３：容量素子、１２１：トランジスタ、１２２：トランジスタ、１２３：トランジスタ、１２４：容量素子、１２５：容量素子、１２６：液晶素子、１２８：電位供給線、１２９：共通配線、１３２：共通配線、１３３：共通配線、１７０：発光素子、１８０：液晶素子、２１５：表示部、２２１：走査線駆動回路、２２９Ａ：境界部、２２９Ｂ：境界部、２２９Ｃ：境界部、２２９Ｄ：境界部、２５１：トランジスタ、４３３：容量素子、４４４：トランジスタ、４４５：ノード、４４６：トランジスタ、４４７：ノード、７２３：電極、７２６：絶縁層、７２８：絶縁層、７２９：絶縁層、７４１：絶縁層、７４２：半導体層、７４４ａ：電極、７４４ｂ：電極、７４６：電極、７７１：基板、７７２：絶縁層、８１０：トランジスタ、８１１：トランジスタ、８２０：トランジスタ、８２１：トランジスタ、８２５：トランジスタ、８２６：トランジスタ、８４２：トランジスタ、８４３：トランジスタ、８４４：トランジスタ、８４５：トランジスタ、８４６：トランジスタ、８４７：トランジスタ、４００１：基板、４００５：シール材、４００６：基板、４００８：液晶層、４０１０：トランジスタ、４０１１：トランジスタ、４０１３：液晶素子、４０１４：配線、４０１５：電極、４０１７：電極、４０１８：ＦＰＣ、４０１９：異方性導電層、４０２０：容量素子、４０２１：電極、４０３０：電極層、４０３１：電極層、４０３２：絶縁層、４０３３：絶縁層、４０３５：スペーサ、４１０２：絶縁層、４１０３：絶縁層、４１０４：絶縁層、４１１０：絶縁層、４１１１：絶縁層、４１１２：絶縁層、４１３１：着色層、４１３２：遮光層、４１３３：絶縁層、４５１０：隔壁、４５１１：発光層、４５１３：発光素子、４５１４：充填材、７０００：表示部、７１００：テレビジョン装置、７１０１：筐体、７１０３：スタンド、７１１１：リモコン操作機、７２００：ノート型パーソナルコンピュータ、７２１１：筐体、７２１２：キーボード、７２１３：ポインティングデバイス、７２１４：外部接続ポート、７３００：デジタルサイネージ、７３０１：筐体、７３０３：スピーカ、７３１１：情報端末機、７４００：デジタルサイネージ、７４０１：柱、７４１１：情報端末機 10A: display device, 10B: display device, 20A: display portion, 20B: display portion, 20C: display portion, 21: pixel portion, 21A: pixel portion, 21B: pixel portion, 22: scanning line drive circuit, 22A: scanning Line drive circuit 22B: scanning line drive circuit 23: signal line drive circuit 23A: signal line drive circuit 23B: signal line drive circuit 24A: timing controller 24B: timing controller 25: pixel 26: pixel 26 27: region 28A: boundary portion 28B: boundary portion 28C: boundary portion 28D: boundary portion 29: display region 29A: boundary portion 29B: boundary portion 29C: boundary portion 29D: boundary portion 29E : Boundary part 29F: boundary part 29G: boundary part 29H: boundary part 30A: signal generation part, 30B: signal generation part, 31: front end part, 32: decoder, 33: processing Unit 34: Receiver 35: Interface 36: Controller 40A: processor 40B: processor 45A: divider 45B: divider 50: arithmetic processor 72: area 73: area 73 74: FPC, 101: transistor, 102: transistor, 103: capacitance element, 104: light emitting element, 111: transistor, 112: transistor, 113: capacitance element, 121: transistor, 122: transistor, 123: transistor, 124: capacitance Element 125: Capacitive element 126: Liquid crystal element 128: Potential supply line 129: Common wiring 132: Common wiring 133: Common wiring 170: Light emitting element 180: Liquid crystal element 215: Display portion 221: Scanning line drive circuit, 229 A: boundary, 229 B: boundary, 229 C: boundary, 229 D: boundary, 2 1: Transistor 433: Capacitive element 444: Transistor 445: Node 446: Transistor 447: Node 723: Electrode 726: Insulating layer 728: Insulating layer 729: Insulating layer 741: Insulating layer 742 Semiconductor layer 744a: electrode 744b: electrode 746: electrode 771: substrate 772: insulating layer 810: transistor 811: transistor 821: transistor 821: transistor 825: transistor 826: transistor 842 A transistor, 843: transistor, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 4001: substrate, 4005: sealing material, 4006: substrate, 4008: liquid crystal layer, 4010: transistor, 4011: transistor, 4013: liquid crystal element, 4014: wiring, 4015: electrode, 4017: electrode, 4018: FPC, 4019: anisotropic conductive layer, 4020: capacitive element, 4021: electrode, 4030: electrode layer, 4031: electrode layer, 4032: Insulating layer, 4033: insulating layer, 4035: spacer, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 4110: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light shielding Layers, 4133: Insulating layer, 4510: Partition, 4511: Light emitting layer, 4513: Light emitting element, 4514: Filler, 7000: Display portion, 7100: Television device, 7101: Housing, 7103: Stand, 7111: Remote control operation Machine, 7200: laptop personal computer, 7211: housing, 7212: keyboard, 721 : Pointing device, 7214: an external connection port 7300: digital signage, 7301: casing, 7303: speaker, 7311: Information terminal, 7400: digital signage, 7401: pillar, 7411: Information terminal

Claims (8)

  1. 　第１の画素がマトリクス状に配列された第１の画素部と、第２の画素がマトリクス状に配列された第２の画素部と、を有する表示装置の動作方法であって、
    　前記第１の画素部に表示される画像を補正する機能を有する第１の補正フィルタと、前記第２の画素部に表示される画像を補正する機能を有する第２の補正フィルタと、を作成し、
    　前記第１の補正フィルタのフィルタ値と、前記第２の補正フィルタのフィルタ値と、を比較し、
    　前記比較結果を基に、前記第１の補正フィルタのフィルタ値を修正する表示装置の動作方法。     A method of operating a display device, comprising: a first pixel portion in which first pixels are arranged in a matrix; and a second pixel portion in which second pixels are arranged in a matrix.
    Creation of a first correction filter having a function of correcting an image displayed on the first pixel unit, and a second correction filter having a function of correcting an image displayed on the second pixel unit And
    Comparing the filter value of the first correction filter with the filter value of the second correction filter,
    A method of operating a display device, wherein the filter value of the first correction filter is corrected based on the comparison result.
  2. 　ｍ行ｎ列（ｍ、ｎは２以上の整数）の第１の画素がマトリクス状に配列された第１の画素部と、ｍ行ｎ列の第２の画素がマトリクス状に配列された第２の画素部と、を有し、ｍ行目の前記第１の画素と、１行目の前記第２の画素と、は隣接する表示装置の動作方法であって、
    　前記第１の画素部に表示される画像を補正する機能を有する第１の補正フィルタと、前記第２の画素部に表示される画像を補正する機能を有する第２の補正フィルタと、を作成し、
    　前記第１の補正フィルタは、前記第１の画素に対応するフィルタ値を有し、
    　前記第２の補正フィルタは、前記第２の画素に対応するフィルタ値を有し、
    　前記第２の画素部との境界部に設けられた前記第１の画素に対応するフィルタ値の平均値と、前記第１の画素部との境界部に設けられた前記第２の画素に対応するフィルタ値の平均値と、を比較し、
    　前記比較結果を基に、前記第１の補正フィルタのフィルタ値を修正する表示装置の動作方法。     A first pixel portion in which first pixels of m rows and n columns (m and n are integers of 2 or more) are arranged in a matrix, and a second pixel of m rows and n columns are arranged in a matrix An operation method of a display device having two pixel portions, wherein the first pixel in the m-th row and the second pixel in the first row are adjacent to each other,
    Creation of a first correction filter having a function of correcting an image displayed on the first pixel unit, and a second correction filter having a function of correcting an image displayed on the second pixel unit And
    The first correction filter has a filter value corresponding to the first pixel,
    The second correction filter has a filter value corresponding to the second pixel,
    Corresponds to the average value of the filter values corresponding to the first pixel provided at the boundary with the second pixel unit and the second pixel provided at the boundary with the first pixel unit Compare the average value of the filter values
    A method of operating a display device, wherein the filter value of the first correction filter is corrected based on the comparison result.
  3. 　請求項１又は２において、
    　前記第１の補正フィルタは、
    　前記表示装置が、前記第１の画素から射出される光の輝度を、前記第１の画素の複数の階調値について測定することにより、前記第１の画素から射出される光の輝度と、前記第１の画素の階調値と、の対応関係のデータを取得し、
    　前記表示装置が、前記第１の画素部に特定の階調値の画像を表示して、前記第１の画素から射出される光の輝度を測定することにより、輝度データを取得した後、
    　前記対応関係のデータと、前記輝度データと、を用いて作成される表示装置の動作方法。     In claim 1 or 2,
    The first correction filter is
    The brightness of the light emitted from the first pixel by the display device measuring the brightness of the light emitted from the first pixel with respect to a plurality of gradation values of the first pixel; Acquiring data of correspondence with the gradation value of the first pixel,
    After the display device displays an image of a specific gradation value in the first pixel unit and measures the luminance of light emitted from the first pixel, luminance data is obtained,
    A method of operating a display device generated using the data of the correspondence relationship and the luminance data.
  4. 　請求項３において、
    　前記特定の階調値の画像とは、全ての前記第１の画素の階調値が等しい画像である表示装置の動作方法。     In claim 3,
    The operation method of a display device, wherein the image of the specific gradation value is an image in which the gradation values of all the first pixels are equal.
  5. 　画素部と、処理部と、を有する表示装置であり、
    　前記画素部には、画素がマトリクス状に配列され、
    　前記画素は、表示素子と、メモリ回路と、を有し、
    　前記処理部は、前記表示素子により表示された画像に基づき取得された輝度データを用いて、補正フィルタを作成する機能を有し、
    　前記メモリ回路は、前記補正フィルタを保持する機能を有する表示装置。     A display device having a pixel portion and a processing portion;
    In the pixel portion, pixels are arranged in a matrix,
    The pixel includes a display element and a memory circuit.
    The processing unit has a function of creating a correction filter using luminance data acquired based on an image displayed by the display element.
    The memory circuit has a function of holding the correction filter.
  6. 　請求項５において、
    　前記画素は、前記表示素子と、第１のトランジスタと、第２のトランジスタと、第３のトランジスタと、第４のトランジスタと、第１の容量素子と、第２の容量素子と、を有し、
    　前記第１のトランジスタのソース又はドレインの一方は、前記第１の容量素子の一方の電極と電気的に接続され、
    　前記第１の容量素子の他方の電極は、前記第２のトランジスタのソース又はドレインの一方と電気的に接続され、
    　前記第２のトランジスタのソース又はドレインの一方は、前記第３のトランジスタのゲートと電気的に接続され、
    　前記第３のトランジスタのゲートは、前記第２の容量素子の一方の電極と電気的に接続され、
    　前記第２の容量素子の他方の電極は、前記第３のトランジスタのソース又はドレインの一方と電気的に接続され、
    　前記第３のトランジスタのソース又はドレインの一方は、前記第４のトランジスタのソース又はドレインの一方と電気的に接続され、
    　前記第４のトランジスタのソース又はドレインの他方は、前記表示素子の一方の電極と電気的に接続されている表示装置。     In claim 5,
    The pixel includes the display element, a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance element, and a second capacitance element. ,
    One of the source and the drain of the first transistor is electrically connected to one electrode of the first capacitive element,
    The other electrode of the first capacitive element is electrically connected to one of the source and the drain of the second transistor,
    One of the source or the drain of the second transistor is electrically connected to the gate of the third transistor,
    The gate of the third transistor is electrically connected to one electrode of the second capacitive element,
    The other electrode of the second capacitive element is electrically connected to one of the source and the drain of the third transistor,
    One of the source or the drain of the third transistor is electrically connected to one of the source or the drain of the fourth transistor,
    The display device in which the other of the source and the drain of the fourth transistor is electrically connected to one electrode of the display element.
  7. 　請求項６において、
    　前記表示素子は、有機ＥＬ素子である表示装置。     In claim 6,
    The display device, wherein the display element is an organic EL element.
  8. 　請求項６又は７において、
    　前記第２のトランジスタは、チャネル形成領域に金属酸化物を有し、
    　前記金属酸化物は、Ｉｎと、Ｚｎと、Ｍ（ＭはＡｌ、Ｔｉ、Ｇａ、Ｓｎ、Ｙ、Ｚｒ、Ｌａ、Ｃｅ、Ｎｄ、又はＨｆ）と、を有する表示装置。     In claim 6 or 7,
    The second transistor has a metal oxide in a channel formation region,
    The display device, wherein the metal oxide includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
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CN111418000B (en) 2023-09-19
JP7289793B2 (en) 2023-06-12

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