WO2018142238A1 - Image processing circuit, display system, and electronic device - Google Patents

Image processing circuit, display system, and electronic device Download PDF

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Publication number
WO2018142238A1
WO2018142238A1 PCT/IB2018/050415 IB2018050415W WO2018142238A1 WO 2018142238 A1 WO2018142238 A1 WO 2018142238A1 IB 2018050415 W IB2018050415 W IB 2018050415W WO 2018142238 A1 WO2018142238 A1 WO 2018142238A1
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WO
WIPO (PCT)
Prior art keywords
data
luminance
circuit
display
function
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Application number
PCT/IB2018/050415
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French (fr)
Japanese (ja)
Inventor
黒川義元
高橋圭
Original Assignee
株式会社半導体エネルギー研究所
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Priority to JP2018565473A priority Critical patent/JPWO2018142238A1/en
Publication of WO2018142238A1 publication Critical patent/WO2018142238A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes

Definitions

  • One embodiment of the present invention relates to an image processing circuit, a semiconductor device, a display system, and an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and the like Examples of the driving method or the manufacturing method thereof can be given.
  • a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.
  • a transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device.
  • a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell and an organic thin film solar cell), and an electronic device may include a semiconductor device.
  • Patent Documents 1 and 2 disclose a technique in which a transistor using zinc oxide or an In—Ga—Zn-based oxide for a semiconductor layer is used for a pixel of a display device.
  • An object of one embodiment of the present invention is to provide a novel semiconductor device or display system. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can display high-quality video. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can display a high-resolution video. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can operate at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system with low power consumption.
  • one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, claims, drawings, etc., and other issues will be extracted from the description of the specification, claims, drawings, etc. Is possible.
  • An image processing circuit has a function of outputting first to third data to a display portion including a light-emitting element based on image data, and the first data is included in the image data.
  • the first data is data for causing the light emitting element to emit light with the first luminance
  • the second data is data for causing the light emitting element to emit light with the second luminance.
  • the data 3 is data for setting the light emitting element in a non-light emitting state.
  • the second luminance is a luminance at which variation in luminance of light emitted from the light emitting element is equal to or less than a certain value.
  • the first luminance is the first luminance.
  • the first data is output, and when the first luminance is less than the second luminance, the second data and the third data are output.
  • the first data is analog A video signal for displaying video on the display unit using the gradation method Used Te
  • the second data and the third data is an image processing circuit for use as a video signal for displaying an image on the display unit by the digital gray scale method.
  • the image processing circuit has a function of comparing the first luminance with a random number, and when the first luminance is larger than the random number, the second data is output, When the luminance is equal to or less than the random number, the third data may be output.
  • An image processing circuit includes a processing circuit, a random number generation circuit, and a comparison circuit, and the processing circuit has a function of performing image processing on image data and outputting the image data to the comparison circuit.
  • the random number generation circuit has a function of generating a random number and outputting the random number to the comparison circuit
  • the comparison circuit has a function of outputting the first data when the first luminance is equal to or higher than the second luminance.
  • the comparison circuit has a function of outputting the second data when the first luminance is less than the second luminance and larger than the random number.
  • the comparison circuit has the first luminance equal to or less than the random number. In this case, it may have a function of outputting the third data.
  • a display system includes the above-described image processing circuit and a display portion, the display portion includes a plurality of pixels, and the gradation of the pixels is an analog level using the first data.
  • This is a display system controlled by a gradation method and a digital gradation method using the second data and the third data.
  • the pixel includes a light-emitting element and a transistor, and the transistor may include a metal oxide in a channel formation region.
  • An electronic device is an electronic device on which the above display system is mounted.
  • a novel semiconductor device or display system can be provided.
  • a semiconductor device or a display system that can display a high-quality video can be provided.
  • a semiconductor device or a display system that can display a high-resolution video can be provided.
  • a semiconductor device or a display system capable of high-speed operation can be provided.
  • a semiconductor device or a display system with low power consumption can be provided.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 6 illustrates a configuration example of a display device.
  • FIG. 9 illustrates a configuration example of an electronic device.
  • One embodiment of the present invention includes, in its category, any device such as a semiconductor device, a memory device, a display device, an imaging device, and an RF (Radio Frequency) tag.
  • the display device includes a liquid crystal display device, a light emitting device including a light emitting element typified by an organic light emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) and the like are included in the category.
  • a metal oxide is a metal oxide in a broad expression.
  • Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like.
  • oxide semiconductors also referred to as oxide semiconductors or simply OS
  • the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short.
  • a transistor including a metal oxide in a channel region is also referred to as an OS transistor.
  • metal oxides containing nitrogen may be collectively referred to as metal oxides.
  • a metal oxide containing nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.
  • X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text.
  • X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
  • an element that enables electrical connection between X and Y for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.
  • Element, light emitting element, load, etc. are not connected between X and Y
  • elements for example, switches, transistors, capacitive elements, inductors
  • resistor element for example, a diode, a display element, a light emitting element, a load, or the like.
  • an element for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.
  • the switch has a function of controlling on / off. That is, the switch is in an on state or an off state, and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path.
  • the case where X and Y are electrically connected includes the case where X and Y are directly connected.
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.)
  • a circuit for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc.
  • Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down
  • X and Y are functionally connected.
  • the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
  • one component may have the functions of a plurality of components. is there.
  • one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
  • FIG. 1 shows a configuration example of the display system 10.
  • the display system 10 has a function of generating a signal for displaying a video based on data received from the outside and displaying the video based on the signal.
  • the display system 10 includes a display unit 20 and a signal generation unit 30.
  • both the display unit 20 and the signal generation unit 30 can be configured by a semiconductor device. Therefore, the display unit 20 and the signal generation unit 30 can also be called semiconductor devices.
  • the display unit 20 has a function of displaying a video based on the video signal input from the signal generation unit 30.
  • the display unit 20 includes a pixel unit 21, a drive circuit 22, a drive circuit 23, and a timing controller 24.
  • the pixel unit 21 includes a plurality of pixels and has a function of displaying an image. Each pixel has a display element and has a function of displaying a predetermined gradation. The gradation of the pixel is controlled by signals output from the drive circuit 22 and the drive circuit 23, and a predetermined image is displayed on the pixel unit 21.
  • the number of pixels included in the pixel unit 21 can be freely set. In order to display a high-definition image, it is preferable to arrange many pixels. For example, when displaying a 2K video, it is preferable to provide 1920 ⁇ 1080 pixels or more. In the case of displaying 4K video, it is preferable to provide 3840 ⁇ 2160 pixels or more, or 4096 ⁇ 2160 pixels or more. In the case of displaying 8K video, it is preferable to provide 7680 ⁇ 4320 or more pixels.
  • the pixel unit 21 can also display an image with a higher definition than 8K.
  • the drive circuit 22 has a function of supplying a signal for selecting a pixel (hereinafter also referred to as a selection signal) to the pixel portion 21.
  • the drive circuit 23 has a function of supplying a signal (hereinafter also referred to as a video signal) for causing the pixel unit 21 to display a predetermined image.
  • a video signal is supplied to the pixel to which the selection signal is supplied, the pixel displays a predetermined gradation.
  • the timing controller 24 has a function of generating timing signals used in the drive circuit 22, the drive circuit 23, and the like. The timing at which the selection signal is output from the drive circuit 22 or the timing at which the video signal is output from the drive circuit 23 is controlled by the timing signal generated by the timing controller 24.
  • the signal generation unit 30 has a function of generating a video signal based on a signal input from the outside.
  • the signal generation unit 30 includes a front end unit 31, a decoder 32, an image processing circuit 33, a reception unit 34, an interface 35, and a control unit 36.
  • the front end unit 31 has a function of receiving a signal transmitted from the outside and performing signal processing. Data corresponding to video displayed on the display unit 20 (hereinafter also referred to as image data) such as a broadcast signal is input to the front end unit 31.
  • the front end unit 31 can have a function of performing demodulation, analog-digital conversion, and the like of a received signal. Further, the front end unit 31 may have a function of performing error correction.
  • Broadcast signals that can be received by the front end unit 31 include terrestrial waves or radio waves transmitted from satellites.
  • the front end unit 31 can receive broadcasts including video and audio, broadcasts including only audio, and the like.
  • the broadcast received by the front end unit 31 may be an analog broadcast or a digital broadcast.
  • the front end unit 31 can receive broadcast radio waves transmitted in a specific frequency band of, for example, the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, by using a plurality of broadcast signals received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, it becomes easy to display video (2K, 4K, 8K, etc.) having a resolution exceeding full high-vision on the display unit 20.
  • a specific frequency band for example, the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz).
  • the decoder 32 has a function of decoding the encoded signal.
  • the signal is expanded by the decoder 32.
  • the decoder 32 can have functions for performing entropy decoding, inverse quantization, inverse orthogonal transform such as inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST), intraframe prediction, and interframe prediction.
  • IDCT inverse discrete cosine transform
  • IDST inverse discrete sine transform
  • intraframe prediction intraframe prediction
  • interframe prediction interframe prediction.
  • the signal generated by the decoder is output to the image processing circuit 33 as image data Di.
  • the encoding standard for 8K broadcasting includes H.264. H.265 / MPEG-H High Efficiency Video Coding (hereinafter referred to as HEVC) has been adopted.
  • HEVC High Efficiency Video Coding
  • the decoder 32 performs CABAC (Context Adaptive Binary Arithmetic Coding) decoding.
  • the image processing circuit 33 has a function of performing image processing on the image data Di input from the decoder 32 and generating a video signal.
  • the video signal generated by the image processing is output to the drive circuit 23 as the signal SD.
  • Examples of image processing by the image processing circuit 33 include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. Color tone correction processing and luminance correction processing can be performed using gamma correction or the like.
  • the image processing circuit 33 may have a function of executing inter-pixel interpolation processing accompanying resolution up-conversion, inter-frame interpolation processing accompanying frame frequency up-conversion, and the like.
  • noise removal processing examples include removal of various noises such as mosquito noise that occurs around the outline of characters, block noise that occurs in high-speed moving images, random noise that causes flickering, and dot noise that occurs due to resolution up-conversion.
  • the gradation conversion process is a process for converting the gradation into a gradation corresponding to the output characteristics of the display unit 20. For example, when the number of gradations is increased, a process for smoothing the histogram can be performed by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
  • HDR high dynamic range
  • the inter-pixel interpolation process is a process of interpolating data that does not originally exist when the resolution is up-converted. For example, referring to pixels around the target pixel, the data is interpolated so as to display the intermediate colors.
  • the color tone correction process is a process for correcting the color tone of an image.
  • the brightness correction process is a process for correcting the brightness (brightness contrast) of an image. For example, the brightness and color tone of the image displayed on the display unit 20 are corrected to be optimal according to the type, brightness, or color purity of the illumination in the space where the display unit 20 is provided.
  • Interframe interpolation generates an image of a frame (interpolation frame) that does not originally exist when the frame frequency of a video to be displayed is increased.
  • an interpolation frame image to be inserted between two images is generated from the difference between two images.
  • an image of a plurality of interpolation frames can be generated between two images.
  • the frame frequency of the image data input from the decoder 32 is 60 Hz
  • the frame frequency of the video signal output to the display unit 20 is doubled to 120 Hz, or It can be increased to 4 times 240 Hz or 8 times 480 Hz.
  • the image processing circuit 33 may have a function of supplying a signal used for generating a timing signal to the timing controller 24.
  • the image processing circuit 33 can be configured by a semiconductor device. Therefore, the image processing circuit 33 can also be called a semiconductor device.
  • the receiving unit 34 has a function of receiving a control signal input from the outside.
  • the transmission unit 40 can be used to input a control signal to the reception unit 34.
  • a remote controller As the transmission unit 40, a remote controller, a portable information terminal (such as a smartphone or a tablet), an operation button provided on the display unit 20, or the like can be used.
  • the interface 35 has a function of appropriately performing signal processing on the control signal received by the receiving unit 34 and outputting the signal to the control unit 36.
  • the control unit 36 has a function of supplying a control signal to each circuit included in the signal generation unit 30.
  • the control unit 36 has a function of controlling the operation of the image processing circuit 33 by supplying a control signal to the image processing circuit 33.
  • the control by the control unit 36 can be performed based on the control signal received by the receiving unit 34.
  • the control part 36 can be comprised by a central processing unit (CPU: Central Processing Unit) etc., for example.
  • FIG. 2A shows a configuration example of the display unit 20.
  • the pixel portion 21 includes a plurality of pixels 25, and each pixel 25 includes a display element.
  • Examples of the display element provided in the pixel 25 include a liquid crystal element and a light emitting element.
  • a liquid crystal element a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used.
  • a shutter type MEMS (Micro Electro Mechanical Systems) element, an optical interference type MEMS element, a microcapsule type, an electrophoretic method, an electrowetting method, an electropowder fluid (registered trademark) method, etc. are applied.
  • a display element or the like can also be used.
  • light-emitting elements include self-luminous light-emitting elements such as OLEDs (Organic Light Emitting Diodes), LEDs (Light Emitting Diodes), QLEDs (Quantum-dot Light Emitting Diodes), and semiconductor lasers.
  • OLEDs Organic Light Emitting Diodes
  • LEDs Light Emitting Diodes
  • QLEDs Quadantum-dot Light Emitting Diodes
  • semiconductor lasers examples include self-luminous light-emitting elements such as OLEDs (Organic Light Emitting Diodes), LEDs (Light Emitting Diodes), QLEDs (Quantum-dot Light Emitting Diodes), and semiconductor lasers.
  • Each pixel 25 is connected to the wiring SL and the wiring GL. Further, the wiring GL is connected to the driving circuit 22, and the wiring SL is connected to the driving circuit 23. A selection signal is supplied to the wiring GL, and a video signal is supplied to the wiring SL.
  • the drive circuit 22 has a function of supplying a selection signal to the pixel 25. Specifically, the drive circuit 22 has a function of supplying a selection signal to the wiring GL, and the wiring GL has a function of transmitting the selection signal output from the drive circuit 22 to the pixel 25. Note that the wiring GL can also be referred to as a selection signal line, a gate line, or the like.
  • the drive circuit 23 has a function of supplying a video signal to the pixels 25. Specifically, the drive circuit 23 has a function of supplying a video signal to the wiring SL, and the wiring SL has a function of transmitting the video signal output from the drive circuit 23 to the pixel 25. Note that the wiring SL can also be referred to as a video signal line, a source line, or the like.
  • FIG. 2B illustrates a configuration example of the pixel 25 using a light-emitting element as a display element.
  • a pixel 25 illustrated in FIG. 2B includes transistors Tr1 and Tr2, a capacitor C1, and a light-emitting element LE.
  • the transistors Tr1 and Tr2 are n-channel type here, the polarity of the transistors can be changed as appropriate.
  • the gate of the transistor Tr1 is connected to the wiring GL, one of the source and the drain is connected to the gate of the transistor Tr2 and one electrode of the capacitor C1, and the other of the source and the drain is connected to the wiring SL.
  • One of the source and the drain of the transistor Tr2 is connected to the other electrode of the capacitor C1 and the one electrode of the light emitting element LE, and the other of the source and the drain is connected to a wiring to which the potential Va is supplied.
  • the other electrode of the light emitting element LE is connected to a wiring to which the potential Vc is supplied.
  • a node connected to one of the source and the drain of the transistor Tr1, the gate of the transistor Tr2, and one electrode of the capacitor C1 is referred to as a node N1.
  • a node connected to one of the source and the drain of the transistor Tr2 and the other electrode of the capacitor C1 is referred to as a node N2.
  • the capacitor C1 functions as a storage capacitor for holding the potential of the node N1.
  • the transistor Tr1 has a function of controlling supply of the potential of the wiring SL to the node N1. Specifically, by controlling the potential of the wiring GL and turning on the transistor Tr1, the potential of the wiring SL corresponding to the video signal is supplied to the node N1, and the pixel 25 is written. After that, the potential of the node N1 is held by controlling the potential of the wiring GL to turn off the transistor Tr1.
  • the amount of current flowing between the source and drain of the transistor Tr2 is controlled in accordance with the voltage between the nodes N1 and N2, and the light emitting element LE emits light with luminance corresponding to the amount of current. Thereby, the gradation of the pixel 25 can be controlled.
  • the transistor Tr2 is preferably operated in a saturation region.
  • an image for the first frame can be displayed.
  • the progressive method or the interlace method may be used to select the wiring GL.
  • the video signal may be supplied to the wiring SL using dot sequential driving for sequentially supplying the video signal to the wiring SL, or line sequential driving for supplying the video signal to all the wirings SL at the same time. You may go. Further, the video signal may be supplied in order for each of the plurality of wirings SL.
  • a Group 14 element such as silicon or germanium, a compound semiconductor such as gallium arsenide, an organic semiconductor, a metal oxide, or the like can be used.
  • the semiconductor may be a non-single-crystal semiconductor (amorphous semiconductor, microcrystalline semiconductor, polycrystalline semiconductor, or the like) or a single-crystal semiconductor.
  • the transistor included in the pixel 25 preferably includes an amorphous semiconductor, particularly hydrogenated amorphous silicon (a-Si: H), in a channel formation region. Since a transistor using an amorphous semiconductor can easily cope with an increase in area of a substrate, a manufacturing process is required when manufacturing a large-screen display device that can support 2K, 4K, 8K broadcasting, for example. Can be simplified.
  • a-Si: H hydrogenated amorphous silicon
  • a transistor including a metal oxide in a channel formation region can be used as the transistor included in the pixel 25 as the transistor included in the pixel 25, a transistor including a metal oxide in a channel formation region (OS transistor) can be used.
  • An OS transistor has higher field effect mobility than a transistor using hydrogenated amorphous silicon.
  • the crystallization step required for a transistor using polycrystalline silicon is not necessary.
  • the update frequency of the video signal can be set very low during a period in which the video displayed on the pixel unit 21 does not change or in a period in which the change is below a certain level.
  • the frequency of updating the video signal can be set to, for example, not more than once every 0.1 seconds, or less than once per second, or less than once every 10 seconds.
  • a backlight is not required unlike when a liquid crystal element is used. Therefore, by using a light emitting element, the display portion 20 can be reduced in weight, thickness, or power consumption.
  • a black image can be displayed by setting the light emitting element to a non-light emitting state. As a result, the black image can be displayed blacker than when using a liquid crystal element that may cause light leakage from the backlight.
  • the luminance of the light-emitting element is controlled by controlling the current flowing through the light-emitting element with a driving transistor (corresponding to the transistor Tr2 in FIG. 2B).
  • a driving transistor corresponding to the transistor Tr2 in FIG. 2B.
  • variations in luminance can occur. For example, when a predetermined video signal is supplied to the node N1 due to variations in the gain of the drive transistor, variations in current flowing between the source and drain of the transistor Tr2 occur, and light emission with an intended luminance cannot be obtained. In some cases, an error occurs in the gray scale.
  • the influence of the luminance variation caused by the gain variation is particularly great when light emission at a low luminance, that is, when a dark image is displayed. For this reason, a phenomenon in which the light emitting element slightly emits light during black display (black floating) and a phenomenon in which dark black and light black are mixed during black display may occur, which may impair display quality.
  • a method of displaying gray scales with luminance of an analog value (hereinafter also referred to as an analog gray scale method) and a luminance of a digital value in accordance with the luminance of a light-emitting element provided in a pixel
  • a method for displaying gray scales (hereinafter also referred to as a digital gray scale method) is selectively used.
  • a digital gray scale method is used.
  • a light emitting element provided in a pixel is required to emit light with a luminance higher than a predetermined value
  • an analog gradation method is used, and light emission with a luminance lower than a predetermined value is required.
  • a digital gradation method is used.
  • data Dx and data Dy are input to the image processing circuit 33.
  • Data Dx is data included in the image data Di, and is data corresponding to the gradation displayed by the pixel 25. Specifically, the data Dx is data for causing the light emitting element provided in the pixel 25 to emit light with luminance X.
  • Data Dy is data for causing the light emitting element to emit light with luminance Y.
  • the luminance Y is the lowest luminance of the light that can be emitted from the light emitting element provided in the pixel 25, with the luminance variation being equal to or less than a certain value (the lowest luminance within which the luminance variation is within a predetermined range). That is, when the light emitting element emits light with a luminance higher than Y, it can be said that the variation in luminance is small. Note that the luminance variation corresponds to an error in luminance of light emitted from the light emitting element when a predetermined video signal is supplied to the pixel 25.
  • the predetermined range can be freely set according to the content of the video, the surrounding environment, the user, and the like.
  • data for setting the luminance of the light emitting element to “0”, that is, a non-light emitting state is represented as data D 0 .
  • the luminance “0” indicates that the light emitting element is in a non-light emitting state, and thus the luminance variation can be ignored.
  • the image processing circuit 33 uses the data Dy and the data D 0 to set the luminance X.
  • a video signal for realization is generated.
  • the data Dx is output as the signal SD. Since the luminance X at this time is a luminance with small variations, light emission of the luminance X can be accurately obtained from the data Dx.
  • the data Dx is converted into an analog value and then supplied to the pixel 25. As a result, the luminance of the light emitting element becomes an analog value, and the pixel 25 can display a gradation in an analog gradation method.
  • the image processing circuit 33 has a function of comparing the brightness X and the random number RND, and outputs the data Dy or data D 0 in accordance with the result of the comparison as a signal SD.
  • This random number RND is a random number constituted by a sequence of numbers from 0 to Y.
  • the data Dy is output as the signal SD.
  • the luminance X is less than the random number RND (RND ⁇ X ⁇ Y)
  • the data D 0 is output as the signal SD.
  • the probability that the light emitting element emits light with luminance Y is (X / Y).
  • the time average of the luminance of the light emitting elements over a plurality of frames and the area average of the luminance of a region where the plurality of light emitting elements are gathered are X. That is, the luminance X is realized by the time gradation method or the area gradation method using the luminance Y and the luminance “0” with small variations as digital values.
  • the time gray scale method is a method of controlling gray scale according to a period during which a light emitting element emits light.
  • the area gray scale method is a method in which the gray scale is controlled by the area where the light emitting element emits light.
  • Both the time gray scale method and the area gray scale method are digital gray scale methods in which a gray scale is displayed with luminance Y and luminance “0”.
  • the luminance X is expressed by a digital gradation method
  • it is effective to increase the frame frequency or the density of the pixels 25 in order to increase the accuracy of the luminance. Therefore, for example, by setting the frame frequency to 60 Hz or more, preferably 120 Hz or more, the accuracy of gradation display by the time gradation method can be improved. Further, by setting the resolution of the pixel portion 21 to 2K, 4K, 8K, 16K, or higher and increasing the spatial resolution, it is possible to improve the accuracy of gradation display by the area gradation method.
  • the frame frequency can be varied within a predetermined range (for example, 1 Hz to 120 Hz), and the frame frequency can be changed according to the displayed video.
  • the value of the luminance Y may be set in consideration of the result of the display test of the display unit 20, the characteristics of the light emitting element or the driving transistor, the frame frequency, etc., or may be set manually while the user is viewing the video. Good. Further, the value of the luminance Y can be switched according to the content of the video, the surrounding environment, the user, and the like. Further, as described in the second embodiment, the value of luminance Y can be determined using artificial intelligence.
  • the image processing circuit 33 based on the image data Di data Dx, by having a function of outputting the data Dy, and the data D 0, the display of images using an analog gray scale method and the digital gray scale method Is possible.
  • the image processing circuit 33 illustrated in FIG. 4 includes a processing circuit 101, a random number generation circuit 102, and a comparison circuit 103.
  • the processing circuit 101 has a function of performing image processing on the image data Di input from the decoder 32 and outputting the processed image data to the comparison circuit 103.
  • image processing are as described above, and examples include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing.
  • the image data Di output from the processing circuit 101 includes data Dx.
  • the random number generation circuit 102 has a function of generating a random number RND composed of a sequence of numbers from 0 to Y and outputting the random number RND to the comparison circuit 103. Note that the random number generation circuit 102 may be provided outside the image processing circuit 33.
  • the comparison circuit 103 compares the luminance X corresponding to the data Dx included in the image data Di with the luminance Y corresponding to the data Dy, and compares the luminance X and the random number RND, and a signal corresponding to the result of the comparison It has a function to output SD.
  • the comparison circuit 103 the data Dx in the case of X ⁇ Y, a data Dy For RND ⁇ X ⁇ Y, the data D 0 in the case of X ⁇ RND, a function of outputting a signal SD Have.
  • the signal SD is supplied to the pixel unit 21 via the drive circuit 23.
  • the data Dy may be stored in the comparison circuit 103 using a memory circuit.
  • the image processing circuit 33 has a function of selecting a video signal output to the drive circuit 23 based on the luminance X, the luminance Y, and the random number RND in addition to the function of performing image processing.
  • the data Dx used in analog gray scale method the data Dy and data D 0 is used in a digital gray scale method.
  • the cycle of switching the random number RND output from the random number generation circuit 102 is preferably set higher than the cycle in which image data for one frame is input to the image processing circuit 33. Thereby, the precision of the brightness
  • FIG. 5 is a flowchart showing an operation example of the image processing circuit 33.
  • image data Di including data Dx is output from the decoder 32, and the data Dx is input to the image processing circuit 33 (step S1). Then, the image processing circuit 33 appropriately performs image processing on the data Dx (step S2).
  • step S3 When the luminance X corresponding to the data Dx is Y or more (YES in step S3), the data Dx is output to the drive circuit 23 as the signal SD (step S4).
  • the light emitting element emits light accurately with the luminance X based on the data Dx. Therefore, the luminance X can be obtained by an analog gradation method in which the data Dx is supplied to the pixel 25 as an analog value.
  • step S3 when the luminance X is less than the luminance Y (NO in step S3), the luminance X and the random number RND are compared. If X> RND, data Dy is substituted for data Dx (step S6), and data Dy is output as signal SD (step S4). In the case of X ⁇ RND, the data D 0 is assigned to the data Dx (step S7), and the data D 0 is output as the signal SD (step S4). As a result, the data Dy is output with a probability of (X / Y).
  • Luminance Y is obtained by supplying data Dy to the pixel 25, and luminance “0” is obtained by supplying data D 0 .
  • the luminance X can be obtained by a digital gradation method using the luminance Y and the luminance “0” as digital values.
  • step S3 and step S5 can be performed using the comparison circuit 103 shown in FIG.
  • the analog gradation method for supplying a video signal corresponding to the luminance to the pixel is used.
  • the gradation is controlled and the video is displayed.
  • the gradation of pixels is controlled by a digital gradation method using binary luminance (Y and “0”), and the image is displayed. Is displayed. As a result, it is possible to prevent display defects when displaying dark images while maintaining the quality of bright images, and high-quality images can be obtained.
  • FIG. 6A shows a configuration example of the image processing circuit 33.
  • An image processing circuit 33 illustrated in FIG. 6A includes an arithmetic circuit 104 and is different from FIG. 4 in that data Dy is output from the arithmetic circuit 104.
  • the arithmetic circuit 104 has a function of generating data Dy corresponding to the luminance Y by using artificial intelligence (AI). Specifically, the arithmetic circuit 104 has an artificial neural network (ANN: Artificial Neural Network). A function of calculating the value of the luminance Y based on the image data Di is given to the arithmetic circuit 104 by learning of the artificial neural network. The data Dy can be obtained by inputting the image data Di to the learned artificial neural network and performing inference.
  • AI artificial intelligence
  • ANN Artificial Neural Network
  • Artificial intelligence is a computer that mimics human intelligence.
  • An artificial neural network is a circuit simulating a neural network composed of neurons and synapses, and can determine the connection strength between neurons (also referred to as a weighting factor) by learning. Also, constructing a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom is called inference (cognition).
  • An artificial neural network is a kind of artificial intelligence. In this specification and the like, the term “neural network” particularly refers to an artificial neural network.
  • the neural network NN includes a neuron circuit and a synapse circuit provided between the neuron circuits.
  • FIG. 7A shows a configuration example of the neuron circuit NC and the synapse circuit SC constituting the neural network NN.
  • Input data x 1 to x L (L is a natural number of 1 or more) is input to the synapse circuit SC.
  • the synapse circuit SC has a function of storing a weight coefficient w i (i is an integer of 1 to L).
  • the weighting factor w i corresponds to the strength of the connection between the neuron circuits NC.
  • the neuron circuit NC When the input data x 1 to x L are input to the synapse circuit SC, the neuron circuit NC has a product of the input data x i input to the synapse circuit SC and the weight coefficient w i stored in the synapse circuit SC.
  • the supplied value is supplied.
  • this value exceeds the threshold value ⁇ of the neuron circuit NC, the neuron circuit NC outputs a high level signal y. This phenomenon is called firing of the neuron circuit NC.
  • FIG. 7B shows a model of a neural network NN that forms a hierarchical perceptron using the neuron circuit NC and the synapse circuit SC.
  • the neural network NN has an input layer IL, a hidden layer (intermediate layer) HL, and an output layer OL.
  • Input data x 1 to x L are output from the input layer IL.
  • the hidden layer HL has a hidden synapse circuit HS and a hidden neuron circuit HN.
  • the output layer OL has an output synapse circuit OS and an output neuron circuit ON.
  • the hidden neuron circuit HN is supplied with a value obtained by a product-sum operation using the input data x i and the weighting coefficient w i held in the hidden synapse circuit HS.
  • the output neuron circuit ON is supplied with the value obtained by the product-sum operation using the output of the hidden neuron circuit HN and the weighting coefficient w i held in the output synapse circuit OS. Then, output data y 1 to y L are output from the output neuron circuit ON.
  • a plurality of hidden layers HL may be provided.
  • the neural network NN to which predetermined input data is given has a function of outputting, as output data, a value corresponding to the weighting coefficient held in the synapse circuit SC and the threshold value ⁇ of the neuron circuit.
  • the neural network NN can perform supervised learning by inputting teacher data.
  • FIG. 7C shows a model of the neural network NN that performs supervised learning using the error back propagation method.
  • the error back propagation method is a method of changing the weighting factor w i of the synapse circuit so that the error between the output data of the neural network and the teacher signal becomes small.
  • the weighting factor w i of the hidden synapse circuit HS is changed according to the error ⁇ O determined based on the output data y 1 to y L and the teacher signals t 1 to t n .
  • further weighting coefficients w i of the previous synapse circuit SC is changed.
  • the neural network NN can be learned by sequentially changing the weighting coefficient of the synapse circuit SC based on the teacher signals t 1 to t n .
  • Deep learning can be performed by using a neural network having two or more hidden layers HL (deep neural network (DNN)).
  • DNN deep neural network
  • Image data Di is input from the processing circuit 101 to the arithmetic circuit 104.
  • the neural network NN performs a predetermined calculation using the image data Di and outputs output data to the comparison circuit 103.
  • the output data becomes the initial value of the data Dy.
  • a signal SD is generated using the data Dy and supplied to the pixel unit 21 via the drive circuit 23.
  • image data Di and data DDi are input to the neural network NN.
  • the image data Di is data corresponding to the video to be displayed on the pixel unit 21
  • the data DDi is data corresponding to the video actually displayed on the pixel unit 21.
  • the data DDi can be acquired by, for example, capturing an image displayed on the pixel unit 21 with an image sensor or the like.
  • the error between the data DDi and the image data Di is less than a certain value, that is, the error between the image to be displayed on the pixel unit 21 and the image actually displayed on the pixel unit 21 is less than a certain value.
  • the weighting coefficient of the neural network NN is updated.
  • the output data Dy of the neural network NN is also updated with the update of the weighting factor. Then, when the data Dy is updated until the error between the data DDi and the image data Di finally becomes a certain value or less, the learning of the neural network NN is finished.
  • the initial value of the weighting factor of the neural network NN may be determined by a random number. Note that the initial value of the weighting coefficient may affect the learning speed (for example, the convergence speed of the weighting coefficient, the prediction accuracy of the neural network NN, etc.). If the learning speed is slow, the initial value of the weighting coefficient is changed. May be.
  • the data Dy is output.
  • the data Dy is updated so that an image with a small luminance error is displayed on the pixel unit 21.
  • the above-described learning of the neural network NN can be performed using an arithmetic processing device or the like provided outside the signal generation unit 30.
  • the arithmetic processing device a computer having excellent arithmetic processing capability such as a dedicated server or a cloud can be used.
  • the neural network NN can be learned using the arithmetic processing device.
  • the weighting coefficient obtained by learning is supplied to the arithmetic circuit 104 via the receiving unit 34 of the signal generation unit 30, whereby the weighting coefficient of the neural network NN provided in the arithmetic circuit 104 can be updated.
  • the learning of the neural network NN is performed outside the signal generation unit 30, whereby the configuration of the signal generation unit 30 can be simplified.
  • the estimation can also be performed using the above arithmetic processing unit.
  • the data Dy obtained by the estimation can be directly supplied to the comparison circuit 103.
  • the arithmetic circuit 104 can be omitted, and the configuration of the image processing circuit 33 can be further simplified.
  • the processing circuit 101 can also be equipped with a neural network.
  • image processing using a neural network for example, correction of color tone according to a person, building, landscape, etc., processing for sharpening the outline of an object displayed in a video, processing for up-converting low-resolution image data , Gamma correction, data compression, etc.
  • the luminance X is expressed by the digital gradation method, it is effective to increase the frame frequency or the density of the pixels 25 in order to increase the accuracy of the luminance.
  • a configuration example of the display unit 20 having a large number of pixels and capable of high speed operation will be described.
  • FIG. 8 shows a configuration example of the display unit 20 in which the pixel unit 21 is divided into a plurality of regions.
  • the pixel unit 21 is divided into two regions A and B.
  • the regions A and B are connected to different drive circuits 22 and 23, respectively.
  • a video signal is supplied at high speed by independently providing a drive circuit 23 for supplying the video signal to the area A and a drive circuit 23 for supplying the video signal to the area B. Can do.
  • the wiring GL and the wiring SL connected to the pixels 25 included in the region A are referred to as a wiring GLA and a wiring SLA, respectively.
  • the wiring GL and the wiring SL connected to the pixel 25 included in the region B are denoted as a wiring GLB and a wiring SLB, respectively.
  • the driving circuit 22 connected to the wiring GLA and the driving circuit 22 connected to the wiring GLB are referred to as a driving circuit 22A and a driving circuit 22B, respectively.
  • the drive circuit 23 connected to the wiring SLA and the drive circuit 23 connected to the wiring SLB are referred to as a drive circuit 23A and a drive circuit 23B, respectively.
  • two drive circuits 22 are connected to one wiring GL.
  • the pixels 25 included in the region A are connected to the drive circuits 22Aa and 22Ab via the wiring GLA.
  • the pixels 25 included in the region B are connected to the drive circuits 22Ba and 22Bb via the wiring GLB.
  • the timings at which the selection signals are output from the drive circuits 22Aa, 22Ab are synchronized, and the timings at which the selection signals are output from the drive circuits 22Ba, 22Bb are synchronized. Accordingly, the selection signal can be supplied from both ends of the wiring GL, and the selection signal can be supplied at high speed.
  • the display unit 20 can be provided with a larger number of wirings SL than the number of columns of the pixels 25.
  • FIG. 8 shows a case where the number of wirings SL is twice the number of columns of the pixels 25 as an example.
  • the pixels 25 included in the region A are connected to the wiring SLAa or the wiring SLAb, and the pixels 25 included in the region B are connected to the wiring SLBa or the wiring SLBb.
  • the pixel 25 connected to the wiring SLAa or the wiring SLBa is referred to as a pixel 25a
  • the pixel 25 connected to the wiring SLAb or the wiring SLBb is referred to as a pixel 25b.
  • Video signals are supplied to the pixels 25a and 25b from different wirings SL. Therefore, selection signals can be simultaneously supplied to the adjacent pixels 25a and 25b. Thereby, the scanning period of the wiring GL can be shortened, and the operation speed of the display unit 20 can be improved.
  • the wiring GL to which the selection signal is simultaneously supplied can be shared.
  • the wiring GL connected to the adjacent pixels 25a and 25b is shared. Thereby, the number of the wirings GL can be reduced, and the area of the display unit 20 can be reduced.
  • the number of wirings SL is twice the number of columns of the pixels 25.
  • the number of wirings SL may be three or more times the number of columns of the pixels 25.
  • the number of wirings GL to which selection signals are simultaneously supplied can be further increased, and the display unit 20 can be speeded up.
  • FIG. 9 shows a configuration example of a display device 300 that can be used for the display unit 20 in the above embodiment.
  • the display device 300 has a function of displaying an image using a light emitting element.
  • the display device 300 includes an electrode 308, and the electrode 308 is connected to a terminal included in the FPC 309 through an anisotropic conductive layer 310.
  • the electrode 308 is connected to the wiring 304 through an opening formed in the insulating layer 307, the insulating layer 306, and the insulating layer 305.
  • the electrode 308 is formed of the same material as the electrode layer 341.
  • the pixel 25 provided over the substrate 301 includes a transistor Tr2 (see FIG. 2B).
  • the transistor Tr2 is provided over the insulating layer 302.
  • the transistor Tr2 includes an electrode 331 provided over the insulating layer 302, and the insulating layer 303 is formed over the electrode 331.
  • a semiconductor layer 332 is provided over the insulating layer 303.
  • An electrode 333 and an electrode 334 are provided over the semiconductor layer 332, an insulating layer 305 and an insulating layer 306 are provided over the electrode 333 and the electrode 334, and an electrode 335 is provided over the insulating layer 305 and the insulating layer 306.
  • the electrodes 333 and 334 are formed from the same material as the wiring 304.
  • the electrode 331 functions as a gate electrode
  • the electrode 333 functions as one of a source electrode or a drain electrode
  • the electrode 334 functions as the other of the source electrode or the drain electrode
  • the electrode 335 functions as a back gate electrode.
  • the transistor Tr2 has a bottom gate structure and has a back gate, whereby the on-state current can be increased.
  • the threshold value of the transistor can be controlled.
  • the electrode 335 may be omitted in some cases in order to simplify the manufacturing process.
  • a semiconductor material used for the transistor for example, a Group 14 element (silicon, germanium, or the like) or a metal oxide can be used.
  • a semiconductor containing silicon, a semiconductor containing gallium arsenide, a metal oxide containing indium, or the like can be used.
  • silicon can be used for the semiconductor in which the channel of the transistor is formed.
  • silicon it is particularly preferable to use amorphous silicon.
  • amorphous silicon By using amorphous silicon, a transistor can be formed over a large substrate with high yield, and the mass productivity is excellent.
  • crystalline silicon such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon can be used.
  • polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.
  • a metal oxide having a bandgap larger than that of silicon can be used as a semiconductor in which a channel of a transistor is formed. It is preferable to use a semiconductor material with a wider band gap and lower carrier density than silicon because current in an off state of the transistor can be reduced.
  • a transistor using a metal oxide having a band gap larger than that of silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long time because of the low off-state current.
  • the driving circuit can be stopped while maintaining the gradation of an image displayed in each display region. As a result, a display device with extremely reduced power consumption can be realized.
  • the metal oxide is represented by an In-M-Zn-based oxide containing at least indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It is preferable to include a material to be prepared. In addition, in order to reduce variation in electric characteristics of the transistor using the metal oxide, it is preferable to include a stabilizer together with them.
  • stabilizer examples include gallium, tin, hafnium, aluminum, and zirconium.
  • Other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
  • an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.
  • the semiconductor layer and the conductive layer may have the same metal element among the above oxides.
  • Manufacturing costs can be reduced by using the same metal element for the semiconductor layer and the conductive layer.
  • the manufacturing cost can be reduced by using metal oxide targets having the same metal composition.
  • an etching gas or an etching solution for processing the semiconductor layer and the conductive layer can be used in common.
  • the semiconductor layer and the conductive layer may have different compositions even if they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.
  • the metal oxide constituting the semiconductor layer preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
  • the metal oxide forming the semiconductor layer is an In-M-Zn oxide
  • the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ⁇ M, Zn ⁇ It is preferable to satisfy M.
  • the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.
  • semiconductor layer has a carrier density of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, more preferably 1 ⁇ 10 11 / cm 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3, it is possible to use a 1 ⁇ 10 -9 / cm 3 metal oxide or more carrier density.
  • Such a semiconductor layer has stable characteristics because it has a low impurity concentration and a low density of defect states.
  • the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor.
  • the semiconductor layer in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .
  • the concentration of silicon or carbon in the semiconductor layer is 2 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less. preferable.
  • the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry in the semiconductor layer is set to 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. preferable.
  • the metal oxide may have a non-single crystal structure, for example.
  • the non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure.
  • the amorphous structure has the highest density of defect states.
  • a metal oxide having an amorphous structure has, for example, disordered atomic arrangement and no crystal component.
  • an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.
  • the metal oxide may be a mixed film including two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, and a region having a single crystal structure.
  • the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.
  • the display device 300 includes a capacitive element C1.
  • the capacitor C1 has a region where the electrode 334 and the electrode 336 overlap with each other with the insulating layer 303 interposed therebetween.
  • the electrode 336 is formed from the same material as the electrode 331.
  • FIG. 9 illustrates an example of a display device using a light-emitting element such as an EL element as a display element.
  • EL elements are classified into organic EL elements and inorganic EL elements.
  • the organic EL element by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.
  • the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer.
  • Material a material having a high electron transporting property and a high hole transporting property
  • the EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.
  • Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure.
  • the dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level.
  • the thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions.
  • FIG. 9 illustrates an example in which an organic EL element is used as the light emitting element LE.
  • the light emitting element LE is connected to a transistor Tr ⁇ b> 2 provided in the pixel 25.
  • the light-emitting element LE includes a stacked layer of an electrode layer 341, a light-emitting layer 342, and an electrode layer 343, but is not limited to this configuration.
  • the configuration of the light emitting element LE can be changed as appropriate in accordance with the direction of light extracted from the light emitting element LE.
  • the partition 344 is formed using an organic insulating material or an inorganic insulating material.
  • the light emitting layer 342 may be composed of a single layer or a plurality of layers stacked.
  • a protective layer may be formed over the electrode layer 343 and the partition 344 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element LE.
  • As the protective layer silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed.
  • a space sealed with the substrate 301, the substrate 312, and the sealant 311 is provided with a filler 345 and sealed.
  • the protective film As described above, it is preferable to package (enclose) the protective film with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.
  • a protective film bonded film, ultraviolet curable resin film, or the like
  • a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.
  • an ultraviolet curable resin or a thermosetting resin in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used.
  • PVC polyvinyl chloride
  • acrylic resin polyimide
  • epoxy resin epoxy resin
  • silicone resin silicone resin
  • PVB Polyvinyl butyral
  • EVA ethylene vinyl acetate
  • the filler 345 may contain a desiccant.
  • the sealant 31 a glass material such as glass frit, or a resin material such as a curable resin that cures at room temperature, such as a two-component mixed resin, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 311 may contain a desiccant.
  • an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate ( ⁇ / 4 plate, ⁇ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.
  • the light-emitting element has a microcavity structure
  • light with high color purity can be extracted.
  • the reflection can be reduced and the visibility of the display image can be improved.
  • the electrode layer 341 and the electrode layer 343 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, and indium zinc.
  • a light-transmitting conductive material such as an oxide or indium tin oxide to which silicon oxide is added can be used.
  • the electrode layer 341 and the electrode layer 343 include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), One or more metals such as cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), alloys thereof, or metal nitrides thereof Can be used.
  • the electrode layer 341 and the electrode layer 343 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer).
  • a conductive polymer a so-called ⁇ -electron conjugated conductive polymer can be used.
  • polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.
  • the electrode layer 341 and the electrode layer 343 may be transparent. Display devices are classified into a top emission (top emission) structure, a bottom emission (bottom emission) structure, and a double emission (dual emission) structure depending on how light is extracted.
  • the top emission structure refers to a case where light is extracted from the substrate 312 side.
  • the bottom emission structure refers to a case where light is extracted from the substrate 301 side.
  • the dual emission structure refers to a case where light is extracted from both the substrate 312 side and the substrate 301 side.
  • the electrode layer 343 may be transparent.
  • the electrode layer 341 may be transparent.
  • the electrode layer 341 and the electrode layer 343 may be transparent.
  • FIG. 10 is a cross-sectional view in the case where a top-gate transistor is provided as the transistor Tr2 illustrated in FIG.
  • the electrode 331 functions as a gate electrode
  • the electrode 333 functions as one of a source electrode and a drain electrode
  • the electrode 334 functions as the other of the source electrode and the drain electrode.
  • FIG. 9 For the details of the other components in FIG. 10, the description in FIG. 9 may be referred to.
  • the CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material.
  • the conductive function is a function of flowing electrons (or holes) serving as carriers
  • the insulating function is a carrier. This function prevents electrons from flowing.
  • a function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
  • the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region.
  • the conductive region has the above-described conductive function
  • the insulating region has the above-described insulating function.
  • the conductive region and the insulating region may be separated at the nanoparticle level.
  • the conductive region and the insulating region may be unevenly distributed in the material, respectively.
  • the conductive region may be observed with the periphery blurred and connected in a cloud shape.
  • the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
  • CAC-OS or CAC-metal oxide is composed of components having different band gaps.
  • CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region.
  • the carrier when the carrier flows, the carrier mainly flows in the component having the narrow gap.
  • the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
  • CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
  • the CAC-OS is one structure of a material in which elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • the metal oxide one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof.
  • the state mixed with is also referred to as a mosaic or patch.
  • the metal oxide preferably contains at least indium.
  • One kind selected from the above or a plurality of kinds may be included.
  • a CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter referred to as InO).
  • X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.
  • CAC-OS includes a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO X1 is the main component region is a composite metal oxide having a structure that is mixed.
  • the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
  • IGZO is a common name and may refer to one compound of In, Ga, Zn, and O.
  • InGaO 3 (ZnO) m1 (m1 is a natural number of 1 or more), or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 ( ⁇ 1 ⁇ x0 ⁇ 1, m0 is larger than 0.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
  • CAC-OS relates to a material structure of a metal oxide.
  • CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In.
  • the region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions.
  • a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
  • a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, in some cases clear boundary can not be observed.
  • the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In.
  • the region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
  • the CAC-OS can be formed by a sputtering method, for example, without heating the substrate.
  • a CAC-OS is formed by a sputtering method
  • any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good.
  • the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
  • the CAC-OS has a feature that a clear peak is not observed when measurement is performed using a ⁇ / 2 ⁇ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
  • XRD X-ray diffraction
  • an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • a region in which GaO X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component is unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
  • the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2 or InO X1, is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility ( ⁇ ) can be realized.
  • areas such as GaO X3 is the main component, as compared to the In X2 Zn Y2 O Z2 or InO X1 is the main component area, it is highly regions insulating. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high An on-current (I on ) and high field effect mobility ( ⁇ ) can be realized.
  • CAC-OS is optimal for various semiconductor devices.
  • the display system described in the above embodiment can be mounted on the electronic devices exemplified below. Thereby, an electronic device capable of displaying a high-quality video can be provided.
  • the display portion of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high vision, 2K, 4K, 8K, 16K, or higher.
  • the screen size of the display unit may be 20 inches or more diagonal, 30 inches or more diagonal, 50 inches diagonal, 60 inches diagonal, or 70 inches diagonal.
  • Examples of electronic devices include relatively large screens such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and large game machines such as pachinko machines.
  • a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, and the like can be given.
  • the electronic device of one embodiment of the present invention can be incorporated along an inner wall or an outer wall of a house or a building, or a curved surface of an interior or exterior of an automobile.
  • the electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit.
  • the antenna may be used for non-contact power transmission.
  • the electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).
  • the electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.
  • FIG. 11A illustrates an example of a television device.
  • a display portion 7000 is incorporated in a housing 7101.
  • a structure in which the housing 7101 is supported by a stand 7103 is shown.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • Operation of the television device 7100 illustrated in FIG. 11A can be performed with an operation switch included in the housing 7101 or a separate remote controller 7111.
  • the display portion 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display portion 7000 with a finger or the like.
  • the remote controller 7111 may include a display unit that displays information output from the remote controller 7111. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 7111, and an image displayed on the display portion 7000 can be operated.
  • the television device 7100 is provided with a receiver, a modem, and the like.
  • a general television broadcast can be received by the receiver.
  • information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.
  • FIG. 11B illustrates a laptop personal computer 7200.
  • a laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000.
  • FIGS. 11C and 11D show examples of digital signage (digital signage).
  • a digital signage 7300 illustrated in FIG. 11C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
  • FIG. 11D illustrates a digital signage 7400 attached to a columnar column 7401.
  • the digital signage 7400 includes a display portion 7000 provided along the curved surface of the column 7401.
  • the display device of one embodiment of the present invention can be applied to the display portion 7000.
  • the wider the display unit 7000 the more information can be provided at one time.
  • the wider the display unit 7000 the more easily noticeable to the human eye.
  • the advertising effect can be enhanced.
  • a touch panel By applying a touch panel to the display unit 7000, not only an image or a moving image is displayed on the display unit 7000, but also a user can operate intuitively, which is preferable. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.
  • the digital signage 7300 or the digital signage 7400 can be linked to the information terminal 7311 or the information terminal 7411 such as a smartphone possessed by the user by wireless communication.
  • advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate and enjoy the game at the same time.

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Abstract

Provided is a novel semiconductor device or display system. When light used for video display has high luminance and small variation, the gradation of pixels is controlled and video is displayed by an analog gradation system which supplies video signals corresponding to the luminance to pixels. When light used for video display has low luminance and large variation, the gradation of pixels is controlled and video is displayed by a digital gradation system which uses binary luminance. Thereby, high-quality video can be obtained in which the quality of bright video can be maintained, and display defects can be prevented when displaying dark video.

Description

画像処理回路、表示システム及び電子機器Image processing circuit, display system, and electronic device
本発明の一態様は、画像処理回路、半導体装置、表示システム及び電子機器に関する。 One embodiment of the present invention relates to an image processing circuit, a semiconductor device, a display system, and an electronic device.
なお、本発明の一態様は、上記の技術分野に限定されない。本明細書等で開示する本発明の一態様の技術分野としては、半導体装置、表示装置、発光装置、蓄電装置、記憶装置、表示システム、電子機器、照明装置、入力装置、入出力装置、それらの駆動方法、又はそれらの製造方法、を一例として挙げることができる。 Note that one embodiment of the present invention is not limited to the above technical field. Technical fields of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and the like Examples of the driving method or the manufacturing method thereof can be given.
また、本明細書等において、半導体装置とは、半導体特性を利用することで機能しうる装置全般を指す。トランジスタ、半導体回路、演算装置、記憶装置等は半導体装置の一態様である。また、表示装置、撮像装置、電気光学装置、発電装置（薄膜太陽電池、有機薄膜太陽電池等を含む）、及び電子機器は半導体装置を有している場合がある。 In this specification and the like, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, or the like is one embodiment of a semiconductor device. In addition, a display device, an imaging device, an electro-optical device, a power generation device (including a thin film solar cell and an organic thin film solar cell), and an electronic device may include a semiconductor device.
液晶表示装置や発光表示装置に代表されるフラットパネルディスプレイは、映像の表示に広く用いられている。これらの表示装置に用いられているトランジスタとしては主にシリコン半導体などが用いられているが、近年、シリコン半導体に代わって、半導体特性を示す金属酸化物をトランジスタに用いる技術が注目されている。例えば特許文献１、２には、半導体層に、酸化亜鉛、又はＩｎ−Ｇａ−Ｚｎ系酸化物を用いたトランジスタを、表示装置の画素に用いる技術が開示されている。 Flat panel displays typified by liquid crystal display devices and light-emitting display devices are widely used for displaying images. As a transistor used in these display devices, a silicon semiconductor or the like is mainly used. However, in recent years, a technique using a metal oxide exhibiting semiconductor characteristics as a transistor instead of a silicon semiconductor has attracted attention. For example, Patent Documents 1 and 2 disclose a technique in which a transistor using zinc oxide or an In—Ga—Zn-based oxide for a semiconductor layer is used for a pixel of a display device.
特開２００７−９６０５５号公報JP 2007-96055 A 特開２００７−１２３８６１号公報JP 2007-123861 A
本発明の一態様は、新規な半導体装置又は表示システムの提供を課題とする。又は、本発明の一態様は、高品質の映像の表示を可能とする半導体装置又は表示システムの提供を課題とする。又は、本発明の一態様は、高解像度の映像の表示を可能とする半導体装置又は表示システムの提供を課題とする。又は、本発明の一態様は、高速動作が可能な半導体装置又は表示システムの提供を課題とする。又は、本発明の一態様は、消費電力が低い半導体装置又は表示システムの提供を課題とする。 An object of one embodiment of the present invention is to provide a novel semiconductor device or display system. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can display high-quality video. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can display a high-resolution video. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system that can operate at high speed. Another object of one embodiment of the present invention is to provide a semiconductor device or a display system with low power consumption.
なお、本発明の一態様は、必ずしも上記の課題の全てを解決する必要はなく、少なくとも一の課題を解決できるものであればよい。また、上記の課題の記載は、他の課題の存在を妨げるものではない。これら以外の課題は、明細書、特許請求の範囲、図面などの記載から、自ずと明らかとなるものであり、明細書、特許請求の範囲、図面などの記載から、これら以外の課題を抽出することが可能である。 Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, claims, drawings, etc., and other issues will be extracted from the description of the specification, claims, drawings, etc. Is possible.
本発明の一態様に係る画像処理回路は、画像データに基づいて、発光素子を有する表示部に第１乃至第３のデータを出力する機能を有し、第１のデータは、画像データに含まれるデータであり、第１のデータは、発光素子を第１の輝度で発光させるためのデータであり、第２のデータは、発光素子を第２の輝度で発光させるためのデータであり、第３のデータは、発光素子を非発光の状態とするためのデータであり、第２の輝度は、発光素子が発する光の輝度のばらつきが一定以下となる輝度であり、第１の輝度が第２の輝度以上であるとき、第１のデータが出力され、第１の輝度が第２の輝度未満であるとき、第２のデータ及び第３のデータが出力され、第１のデータは、アナログ階調方式により表示部に映像を表示するための映像信号として用いられ、第２のデータ及び第３のデータは、デジタル階調方式により表示部に映像を表示するための映像信号として用いられる画像処理回路である。 An image processing circuit according to one embodiment of the present invention has a function of outputting first to third data to a display portion including a light-emitting element based on image data, and the first data is included in the image data. The first data is data for causing the light emitting element to emit light with the first luminance, and the second data is data for causing the light emitting element to emit light with the second luminance. The data 3 is data for setting the light emitting element in a non-light emitting state. The second luminance is a luminance at which variation in luminance of light emitted from the light emitting element is equal to or less than a certain value. The first luminance is the first luminance. When the luminance is 2 or more, the first data is output, and when the first luminance is less than the second luminance, the second data and the third data are output. The first data is analog A video signal for displaying video on the display unit using the gradation method Used Te, the second data and the third data is an image processing circuit for use as a video signal for displaying an image on the display unit by the digital gray scale method.
また、本発明の一態様に係る画像処理回路は、第１の輝度と乱数を比較する機能を有し、第１の輝度が乱数よりも大きいとき、第２のデータが出力され、第１の輝度が乱数以下であるとき、第３のデータが出力されてもよい。 The image processing circuit according to one embodiment of the present invention has a function of comparing the first luminance with a random number, and when the first luminance is larger than the random number, the second data is output, When the luminance is equal to or less than the random number, the third data may be output.
また、本発明の一態様に係る画像処理回路は、処理回路と、乱数生成回路と、比較回路と、を有し、処理回路は、画像データに画像処理を施し、比較回路に出力する機能を有し、乱数生成回路は、乱数を生成して比較回路に出力する機能を有し、比較回路は、第１の輝度が第２の輝度以上であるとき、第１のデータを出力する機能を有し、比較回路は、第１の輝度が第２の輝度未満であり、且つ乱数よりも大きいとき、第２のデータを出力する機能を有し、比較回路は、第１の輝度が乱数以下であるとき、第３のデータを出力する機能を有していてもよい。 An image processing circuit according to one embodiment of the present invention includes a processing circuit, a random number generation circuit, and a comparison circuit, and the processing circuit has a function of performing image processing on image data and outputting the image data to the comparison circuit. The random number generation circuit has a function of generating a random number and outputting the random number to the comparison circuit, and the comparison circuit has a function of outputting the first data when the first luminance is equal to or higher than the second luminance. And the comparison circuit has a function of outputting the second data when the first luminance is less than the second luminance and larger than the random number. The comparison circuit has the first luminance equal to or less than the random number. In this case, it may have a function of outputting the third data.
また、本発明の一態様に係る表示システムは、上記の画像処理回路及び表示部を有し、表示部は複数の画素を有し、画素の階調は、第１のデータを用いたアナログ階調方式と、第２のデータ及び第３のデータを用いたデジタル階調方式と、によって制御される表示システムである。 In addition, a display system according to one embodiment of the present invention includes the above-described image processing circuit and a display portion, the display portion includes a plurality of pixels, and the gradation of the pixels is an analog level using the first data. This is a display system controlled by a gradation method and a digital gradation method using the second data and the third data.
また、本発明の一態様に係る表示システムにおいて、画素は、発光素子と、トランジスタと、を有し、トランジスタは、チャネル形成領域に金属酸化物を有していてもよい。 In the display system according to one embodiment of the present invention, the pixel includes a light-emitting element and a transistor, and the transistor may include a metal oxide in a channel formation region.
また、本発明の一態様に係る電子機器は、上記の表示システムが搭載された電子機器である。 An electronic device according to one embodiment of the present invention is an electronic device on which the above display system is mounted.
本発明の一態様により、新規な半導体装置又は表示システムを提供することができる。又は、本発明の一態様により、高品質の映像の表示を可能とする半導体装置又は表示システムを提供することができる。又は、本発明の一態様により、高解像度の映像の表示を可能とする半導体装置又は表示システムを提供することができる。又は、本発明の一態様により、高速動作が可能な半導体装置又は表示システムを提供することができる。又は、本発明の一態様により、消費電力が低い半導体装置又は表示システムを提供することができる。 According to one embodiment of the present invention, a novel semiconductor device or display system can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a display system that can display a high-quality video can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a display system that can display a high-resolution video can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a display system capable of high-speed operation can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device or a display system with low power consumption can be provided.
なお、これらの効果の記載は、他の効果の存在を妨げるものではない。また、本発明の一態様は、必ずしも、これらの効果の全てを有する必要はない。これら以外の効果は、明細書、特許請求の範囲、図面などの記載から、自ずと明らかとなるものであり、明細書、特許請求の範囲、図面などの記載から、これら以外の効果を抽出することが可能である。 Note that the description of these effects does not disturb the existence of other effects. Further, one embodiment of the present invention does not necessarily have all of these effects. Effects other than these will be apparent from the description of the specification, claims and drawings, and other effects will be extracted from the description of the specification, claims and drawings. Is possible.
表示システムの構成例を示す図。The figure which shows the structural example of a display system. 表示部の構成例を示す図。The figure which shows the structural example of a display part. 画像処理回路の構成例を示す図。The figure which shows the structural example of an image processing circuit. 画像処理回路の構成例を示す図。The figure which shows the structural example of an image processing circuit. フローチャート。flowchart. 画像処理回路の構成例を示す図。The figure which shows the structural example of an image processing circuit. ニューラルネットワークの構成例を示す図。The figure which shows the structural example of a neural network. 表示部の構成例を示す図。The figure which shows the structural example of a display part. 表示装置の構成例を示す図。FIG. 6 illustrates a configuration example of a display device. 表示装置の構成例を示す図。FIG. 6 illustrates a configuration example of a display device. 電子機器の構成例を示す図。FIG. 9 illustrates a configuration example of an electronic device.
以下、本発明の実施の形態について図面を用いて詳細に説明する。ただし、本発明は以下の実施の形態における説明に限定されず、本発明の趣旨及びその範囲から逸脱することなくその形態及び詳細を様々に変更し得ることは、当業者であれば容易に理解される。したがって、本発明は、以下の実施の形態の記載内容に限定して解釈されるものではない。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.
また、本発明の一態様には、半導体装置、記憶装置、表示装置、撮像装置、ＲＦ（Ｒａｄｉｏ　Ｆｒｅｑｕｅｎｃｙ）タグなど、あらゆる装置がその範疇に含まれる。また、表示装置には、液晶表示装置、有機発光素子に代表される発光素子を各画素に備えた発光装置、電子ペーパー、ＤＭＤ（Ｄｉｇｉｔａｌ　Ｍｉｃｒｏｍｉｒｒｏｒ　Ｄｅｖｉｃｅ）、ＰＤＰ（Ｐｌａｓｍａ　Ｄｉｓｐｌａｙ　Ｐａｎｅｌ）、ＦＥＤ（Ｆｉｅｌｄ　Ｅｍｉｓｓｉｏｎ　Ｄｉｓｐｌａｙ）などが、その範疇に含まれる。 One embodiment of the present invention includes, in its category, any device such as a semiconductor device, a memory device, a display device, an imaging device, and an RF (Radio Frequency) tag. In addition, the display device includes a liquid crystal display device, a light emitting device including a light emitting element typified by an organic light emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) and the like are included in the category.
また、本明細書等において、金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）とは、広い表現での金属の酸化物である。金属酸化物は、酸化物絶縁体、酸化物導電体（透明酸化物導電体を含む）、酸化物半導体（Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒまたは単にＯＳともいう）などに分類される。例えば、トランジスタのチャネル領域に金属酸化物を用いた場合、当該金属酸化物を酸化物半導体と呼称する場合がある。つまり、金属酸化物が増幅作用、整流作用、及びスイッチング作用の少なくとも１つを有する場合、当該金属酸化物を、金属酸化物半導体（ｍｅｔａｌ　ｏｘｉｄｅ　ｓｅｍｉｃｏｎｄｕｃｔｏｒ）、略してＯＳと呼ぶことができる。以下、チャネル領域に金属酸化物を含むトランジスタを、ＯＳトランジスタとも表記する。 In this specification and the like, a metal oxide is a metal oxide in a broad expression. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a channel region of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide has at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor, or OS for short. Hereinafter, a transistor including a metal oxide in a channel region is also referred to as an OS transistor.
また、本明細書等において、窒素を有する金属酸化物も金属酸化物（ｍｅｔａｌ　ｏｘｉｄｅ）と総称する場合がある。また、窒素を有する金属酸化物を、金属酸窒化物（ｍｅｔａｌ　ｏｘｙｎｉｔｒｉｄｅ）と呼称してもよい。金属酸化物の詳細については後述する。 In addition, in this specification and the like, metal oxides containing nitrogen may be collectively referred to as metal oxides. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride. Details of the metal oxide will be described later.
また、本明細書等において、ＸとＹとが接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合と、ＸとＹとが機能的に接続されている場合と、ＸとＹとが直接接続されている場合とが、本明細書等に開示されているものとする。したがって、所定の接続関係、例えば、図又は文章に示された接続関係に限定されず、図又は文章に示された接続関係以外のものも、図又は文章に記載されているものとする。ここで、Ｘ、Ｙは、対象物（例えば、装置、素子、回路、配線、電極、端子、導電膜、層、など）であるとする。 In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and things other than the connection relation shown in the figure or text are also described in the figure or text. Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).
ＸとＹとが直接的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）が、ＸとＹとの間に接続されていない場合であり、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）を介さずに、ＸとＹとが、接続されている場合である。 As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y X and Y are not connected via a resistor element, a diode, a display element, a light emitting element, a load, or the like.
ＸとＹとが電気的に接続されている場合の一例としては、ＸとＹとの電気的な接続を可能とする素子（例えば、スイッチ、トランジスタ、容量素子、インダクタ、抵抗素子、ダイオード、表示素子、発光素子、負荷など）が、ＸとＹとの間に１個以上接続されることが可能である。なお、スイッチは、オンオフが制御される機能を有している。つまり、スイッチは、オン状態、又は、オフ状態になり、電流を流すか流さないかを制御する機能を有している。又は、スイッチは、電流を流す経路を選択して切り替える機能を有している。なお、ＸとＹとが電気的に接続されている場合は、ＸとＹとが直接的に接続されている場合を含むものとする。 As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in an on state or an off state, and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a current flow path. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.
ＸとＹとが機能的に接続されている場合の一例としては、ＸとＹとの機能的な接続を可能とする回路（例えば、論理回路（インバータ、ＮＡＮＤ回路、ＮＯＲ回路など）、信号変換回路（ＤＡ変換回路、ＡＤ変換回路、ガンマ補正回路など）、電位レベル変換回路（電源回路（昇圧回路、降圧回路など）、信号の電位レベルを変えるレベルシフタ回路など）、電圧源、電流源、切り替え回路、増幅回路（信号振幅又は電流量などを大きく出来る回路、オペアンプ、差動増幅回路、ソースフォロワ回路、バッファ回路など）、信号生成回路、記憶回路、制御回路など）が、ＸとＹとの間に１個以上接続されることが可能である。なお、一例として、ＸとＹとの間に別の回路を挟んでいても、Ｘから出力された信号がＹへ伝達される場合は、ＸとＹとは機能的に接続されているものとする。なお、ＸとＹとが機能的に接続されている場合は、ＸとＹとが直接的に接続されている場合と、ＸとＹとが電気的に接続されている場合とを含むものとする。 As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.
なお、ＸとＹとが電気的に接続されている、と明示的に記載されている場合は、ＸとＹとが電気的に接続されている場合（つまり、ＸとＹとの間に別の素子又は別の回路を挟んで接続されている場合）と、ＸとＹとが機能的に接続されている場合（つまり、ＸとＹとの間に別の回路を挟んで機能的に接続されている場合）と、ＸとＹとが直接接続されている場合（つまり、ＸとＹとの間に別の素子又は別の回路を挟まずに接続されている場合）とが、本明細書等に開示されているものとする。つまり、電気的に接続されている、と明示的に記載されている場合は、単に、接続されている、とのみ明示的に記載されている場合と同様な内容が、本明細書等に開示されているものとする。 In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And X and Y are functionally connected (that is, they are functionally connected with another circuit between X and Y). And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that
また、異なる図面間で同じ符号が付されている構成要素は、特に説明がない限り、同じものを表す。 Moreover, the component to which the same code | symbol is attached | subjected between different drawings represents the same unless there is particular description.
また、図面上は独立している構成要素同士が電気的に接続しているように図示されている場合であっても、１つの構成要素が、複数の構成要素の機能を併せ持っている場合もある。例えば配線の一部が電極としても機能する場合は、一の導電膜が、配線の機能、及び電極の機能の両方の構成要素の機能を併せ持っている。したがって、本明細書における電気的に接続とは、このような、一の導電膜が、複数の構成要素の機能を併せ持っている場合も、その範疇に含める。 In addition, even in the case where independent components are illustrated as being electrically connected to each other in the drawing, one component may have the functions of a plurality of components. is there. For example, in the case where a part of the wiring also functions as an electrode, one conductive film has both the functions of the constituent elements of the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.
（実施の形態１）
本実施の形態では、本発明の一態様に係る半導体装置及び表示システムについて説明する。 (Embodiment 1)
In this embodiment, a semiconductor device and a display system according to one embodiment of the present invention will be described.
＜表示システムの構成例＞
図１に、表示システム１０の構成例を示す。表示システム１０は、外部から受信したデータに基づいて映像を表示するための信号を生成し、当該信号に基づいて映像を表示する機能を有する。表示システム１０は、表示部２０、信号生成部３０を有する。 <Configuration example of display system>
FIG. 1 shows a configuration example of the display system 10. The display system 10 has a function of generating a signal for displaying a video based on data received from the outside and displaying the video based on the signal. The display system 10 includes a display unit 20 and a signal generation unit 30.
なお、表示部２０及び信号生成部３０は、いずれも半導体装置によって構成することができる。よって、表示部２０及び信号生成部３０は半導体装置と呼ぶこともできる。 Note that both the display unit 20 and the signal generation unit 30 can be configured by a semiconductor device. Therefore, the display unit 20 and the signal generation unit 30 can also be called semiconductor devices.
表示部２０は、信号生成部３０から入力される映像信号に基づいて、映像を表示する機能を有する。表示部２０は、画素部２１、駆動回路２２、駆動回路２３、タイミングコントローラ２４を有する。 The display unit 20 has a function of displaying a video based on the video signal input from the signal generation unit 30. The display unit 20 includes a pixel unit 21, a drive circuit 22, a drive circuit 23, and a timing controller 24.
画素部２１は、複数の画素によって構成され、映像を表示する機能を有する。画素はそれぞれ表示素子を有し、所定の階調を表示する機能を有する。駆動回路２２及び駆動回路２３から出力される信号により、画素の階調が制御され、画素部２１に所定の映像が表示される。 The pixel unit 21 includes a plurality of pixels and has a function of displaying an image. Each pixel has a display element and has a function of displaying a predetermined gradation. The gradation of the pixel is controlled by signals output from the drive circuit 22 and the drive circuit 23, and a predetermined image is displayed on the pixel unit 21.
画素部２１に含まれる画素の数は自由に設定することができる。高精細度の映像を表示するためには、画素を多く配置することが好ましい。例えば、２Ｋの映像を表示する場合は、１９２０×１０８０個以上の画素を設けることが好ましい。また、４Ｋの映像を表示する場合は、３８４０×２１６０個以上、又は４０９６×２１６０個以上の画素を設けることが好ましい。また、８Ｋの映像を表示する場合は、７６８０×４３２０個以上の画素を設けることが好ましい。また、画素部２１には８Ｋよりも高精細度の映像を表示することもできる。 The number of pixels included in the pixel unit 21 can be freely set. In order to display a high-definition image, it is preferable to arrange many pixels. For example, when displaying a 2K video, it is preferable to provide 1920 × 1080 pixels or more. In the case of displaying 4K video, it is preferable to provide 3840 × 2160 pixels or more, or 4096 × 2160 pixels or more. In the case of displaying 8K video, it is preferable to provide 7680 × 4320 or more pixels. The pixel unit 21 can also display an image with a higher definition than 8K.
駆動回路２２は、画素を選択するための信号（以下、選択信号ともいう）を画素部２１に供給する機能を有する。駆動回路２３は、画素部２１に所定の映像を表示させるための信号（以下、映像信号ともいう）を画素部２１に供給する機能を有する。選択信号が供給された画素に映像信号が供給されることにより、画素が所定の階調を表示する。 The drive circuit 22 has a function of supplying a signal for selecting a pixel (hereinafter also referred to as a selection signal) to the pixel portion 21. The drive circuit 23 has a function of supplying a signal (hereinafter also referred to as a video signal) for causing the pixel unit 21 to display a predetermined image. When a video signal is supplied to the pixel to which the selection signal is supplied, the pixel displays a predetermined gradation.
タイミングコントローラ２４は、駆動回路２２、駆動回路２３などで用いられるタイミング信号を生成する機能を有する。駆動回路２２から選択信号が出力されるタイミング、又は駆動回路２３から映像信号が出力されるタイミングは、タイミングコントローラ２４によって生成されたタイミング信号によって制御される。 The timing controller 24 has a function of generating timing signals used in the drive circuit 22, the drive circuit 23, and the like. The timing at which the selection signal is output from the drive circuit 22 or the timing at which the video signal is output from the drive circuit 23 is controlled by the timing signal generated by the timing controller 24.
信号生成部３０は、外部から入力された信号に基づいて映像信号を生成する機能を有する。信号生成部３０は、フロントエンド部３１、デコーダ３２、画像処理回路３３、受信部３４、インターフェース３５、制御部３６を有する。 The signal generation unit 30 has a function of generating a video signal based on a signal input from the outside. The signal generation unit 30 includes a front end unit 31, a decoder 32, an image processing circuit 33, a reception unit 34, an interface 35, and a control unit 36.
フロントエンド部３１は、外部から送信された信号を受信して信号処理を行う機能を有する。フロントエンド部３１には、放送信号などの、表示部２０に表示される映像に対応するデータ（以下、画像データともいう）が入力される。フロントエンド部３１は、受信した信号の復調、アナログ−デジタル変換などを行う機能を備えることができる。また、フロントエンド部３１は、エラー訂正を行う機能を有していてもよい。 The front end unit 31 has a function of receiving a signal transmitted from the outside and performing signal processing. Data corresponding to video displayed on the display unit 20 (hereinafter also referred to as image data) such as a broadcast signal is input to the front end unit 31. The front end unit 31 can have a function of performing demodulation, analog-digital conversion, and the like of a received signal. Further, the front end unit 31 may have a function of performing error correction.
フロントエンド部３１が受信できる放送信号としては、地上波、または衛星から送信される電波などが挙げられる。フロントエンド部３１は、映像及び音声を含む放送、音声のみを含む放送などを受信することができる。なお、フロントエンド部３１が受信する放送は、アナログ放送であってもデジタル放送であってもよい。 Broadcast signals that can be received by the front end unit 31 include terrestrial waves or radio waves transmitted from satellites. The front end unit 31 can receive broadcasts including video and audio, broadcasts including only audio, and the like. The broadcast received by the front end unit 31 may be an analog broadcast or a digital broadcast.
また、フロントエンド部３１は、例えばＵＨＦ帯（約３００ＭＨｚ乃至３ＧＨｚ）またはＶＨＦ帯（３０ＭＨｚ乃至３００ＭＨｚ）のうちの特定の周波数帯域で送信される放送電波を受信することができる。また、複数の周波数帯域で受信した複数の放送信号を用いることで、転送レートを高くすることができ、より多くの情報を得ることができる。これによりフルハイビジョンを超える解像度を有する映像（２Ｋ、４Ｋ、８Ｋなど）を表示部２０に表示させることが容易になる。 Further, the front end unit 31 can receive broadcast radio waves transmitted in a specific frequency band of, for example, the UHF band (about 300 MHz to 3 GHz) or the VHF band (30 MHz to 300 MHz). Further, by using a plurality of broadcast signals received in a plurality of frequency bands, the transfer rate can be increased and more information can be obtained. As a result, it becomes easy to display video (2K, 4K, 8K, etc.) having a resolution exceeding full high-vision on the display unit 20.
デコーダ３２は、符号化された信号を復号する機能を有する。フロントエンド部３１に入力される信号が圧縮されている場合、デコーダ３２によって信号が伸長される。例えば、デコーダ３２は、エントロピー復号、逆量子化、逆離散コサイン変換（ＩＤＣＴ）や逆離散サイン変換（ＩＤＳＴ）などの逆直交変換、フレーム内予測、フレーム間予測などを行う機能を備えることができる。デコーダによって生成された信号は、画像データＤｉとして画像処理回路３３に出力される。 The decoder 32 has a function of decoding the encoded signal. When the signal input to the front end unit 31 is compressed, the signal is expanded by the decoder 32. For example, the decoder 32 can have functions for performing entropy decoding, inverse quantization, inverse orthogonal transform such as inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST), intraframe prediction, and interframe prediction. . The signal generated by the decoder is output to the image processing circuit 33 as image data Di.
なお、８Ｋ放送における符号化規格には、Ｈ．２６５／ＭＰＥＧ−Ｈ　Ｈｉｇｈ　Ｅｆｆｉｃｉｅｎｃｙ　Ｖｉｄｅｏ　Ｃｏｄｉｎｇ（以下、ＨＥＶＣという）が採用されてぃる。フロントエンド部３１に入力される信号が８Ｋの放送信号であり、ＨＥＶＣに従って符号化されてぃる場合には、デコーダ３２によってＣＡＢＡＣ（Ｃｏｎｔｅｘｔ　Ａｄａｐｔｉｖｅ　Ｂｉｎａｒｙ　Ａｒｉｔｈｍｅｔｉｃ　Ｃｏｄｉｎｇ）復号が行われる。 Note that the encoding standard for 8K broadcasting includes H.264. H.265 / MPEG-H High Efficiency Video Coding (hereinafter referred to as HEVC) has been adopted. When the signal input to the front end unit 31 is an 8K broadcast signal and is encoded according to HEVC, the decoder 32 performs CABAC (Context Adaptive Binary Arithmetic Coding) decoding.
画像処理回路３３は、デコーダ３２から入力された画像データＤｉに画像処理を施し、映像信号を生成する機能を有する。画像処理によって生成された映像信号は、信号ＳＤとして駆動回路２３に出力される。 The image processing circuit 33 has a function of performing image processing on the image data Di input from the decoder 32 and generating a video signal. The video signal generated by the image processing is output to the drive circuit 23 as the signal SD.
画像処理回路３３による画像処理の例としては、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理などが挙げられる。色調補正処理や輝度補正処理は、ガンマ補正などを用いて行うことができる。また、画像処理回路３３は、解像度のアップコンバートに伴う画素間補間処理や、フレーム周波数のアップコンバートに伴うフレーム間補間処理などを実行する機能を有していてもよい。 Examples of image processing by the image processing circuit 33 include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. Color tone correction processing and luminance correction processing can be performed using gamma correction or the like. The image processing circuit 33 may have a function of executing inter-pixel interpolation processing accompanying resolution up-conversion, inter-frame interpolation processing accompanying frame frequency up-conversion, and the like.
ノイズ除去処理としては、文字などの輪郭の周辺に生じるモスキートノイズ、高速の動画で生じるブロックノイズ、ちらつきを生じるランダムノイズ、解像度のアップコンバートにより生じるドットノイズなどのさまざまなノイズの除去が挙げられる。 Examples of the noise removal processing include removal of various noises such as mosquito noise that occurs around the outline of characters, block noise that occurs in high-speed moving images, random noise that causes flickering, and dot noise that occurs due to resolution up-conversion.
階調変換処理は、階調を表示部２０の出力特性に対応した階調へ変換する処理である。例えば階調数を大きくする場合、小さい階調数で入力された画像に対して、各画素に対応する階調値を補間して割り当てることで、ヒストグラムを平滑化する処理を行うことができる。また、ダイナミックレンジを広げる、ハイダイナミックレンジ（ＨＤＲ）処理も、階調変換処理に含まれる。 The gradation conversion process is a process for converting the gradation into a gradation corresponding to the output characteristics of the display unit 20. For example, when the number of gradations is increased, a process for smoothing the histogram can be performed by interpolating and assigning gradation values corresponding to each pixel to an image input with a small number of gradations. Further, a high dynamic range (HDR) process for expanding the dynamic range is also included in the gradation conversion process.
画素間補間処理は、解像度をアップコンバートした際に、本来存在しないデータを補間する処理である。例えば、目的の画素の周囲の画素を参照し、それらの中間色を表示するようにデータを補間する。 The inter-pixel interpolation process is a process of interpolating data that does not originally exist when the resolution is up-converted. For example, referring to pixels around the target pixel, the data is interpolated so as to display the intermediate colors.
色調補正処理は、映像の色調を補正する処理である。また輝度補正処理は、映像の明るさ（輝度コントラスト）を補正する処理である。例えば、表示部２０が設けられる空間の照明の種類や輝度、または色純度などに応じて、表示部２０に表示される映像の輝度や色調が最適となるように補正される。 The color tone correction process is a process for correcting the color tone of an image. The brightness correction process is a process for correcting the brightness (brightness contrast) of an image. For example, the brightness and color tone of the image displayed on the display unit 20 are corrected to be optimal according to the type, brightness, or color purity of the illumination in the space where the display unit 20 is provided.
フレーム間補間は、表示する映像のフレーム周波数を増大させる場合に、本来存在しないフレーム（補間フレーム）の画像を生成する。例えば、ある２枚の画像の差分から２枚の画像の間に挿入する補間フレームの画像を生成する。または２枚の画像の間に複数枚の補間フレームの画像を生成することもできる。例えばデコーダ３２から入力される画像データのフレーム周波数が６０Ｈｚであったとき、複数枚の補間フレームを生成することで、表示部２０に出力される映像信号のフレーム周波数を、２倍の１２０Ｈｚ、または４倍の２４０Ｈｚ、または８倍の４８０Ｈｚなどに増大させることができる。 Interframe interpolation generates an image of a frame (interpolation frame) that does not originally exist when the frame frequency of a video to be displayed is increased. For example, an interpolation frame image to be inserted between two images is generated from the difference between two images. Alternatively, an image of a plurality of interpolation frames can be generated between two images. For example, when the frame frequency of the image data input from the decoder 32 is 60 Hz, by generating a plurality of interpolated frames, the frame frequency of the video signal output to the display unit 20 is doubled to 120 Hz, or It can be increased to 4 times 240 Hz or 8 times 480 Hz.
また、画像処理回路３３は、タイミング信号の生成に用いられる信号を、タイミングコントローラ２４に供給する機能を有していてもよい。 Further, the image processing circuit 33 may have a function of supplying a signal used for generating a timing signal to the timing controller 24.
なお、画像処理回路３３は半導体装置によって構成することができる。よって、画像処理回路３３は半導体装置と呼ぶこともできる。 The image processing circuit 33 can be configured by a semiconductor device. Therefore, the image processing circuit 33 can also be called a semiconductor device.
受信部３４は、外部から入力される制御信号を受信する機能を有する。受信部３４への制御信号の入力には、送信部４０を用いることができる。送信部４０としては、リモートコントローラ、携帯情報端末（スマートフォンやタブレットなど）、表示部２０に設けられた操作ボタンなどを用いることができる。 The receiving unit 34 has a function of receiving a control signal input from the outside. The transmission unit 40 can be used to input a control signal to the reception unit 34. As the transmission unit 40, a remote controller, a portable information terminal (such as a smartphone or a tablet), an operation button provided on the display unit 20, or the like can be used.
インターフェース３５は、受信部３４が受信した制御信号に適宜信号処理を施し、制御部３６に出力する機能を有する。 The interface 35 has a function of appropriately performing signal processing on the control signal received by the receiving unit 34 and outputting the signal to the control unit 36.
制御部３６は、信号生成部３０が有する各回路に制御信号を供給する機能を有する。例えば、制御部３６は、画像処理回路３３に制御信号を供給して画像処理回路３３の動作を制御する機能を有する。制御部３６による制御は、受信部３４が受信した制御信号に基づいて行うことができる。制御部３６は、例えば中央演算装置（ＣＰＵ：Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）などによって構成することができる。 The control unit 36 has a function of supplying a control signal to each circuit included in the signal generation unit 30. For example, the control unit 36 has a function of controlling the operation of the image processing circuit 33 by supplying a control signal to the image processing circuit 33. The control by the control unit 36 can be performed based on the control signal received by the receiving unit 34. The control part 36 can be comprised by a central processing unit (CPU: Central Processing Unit) etc., for example.
図２（Ａ）に、表示部２０の構成例を示す。画素部２１は複数の画素２５を有し、画素２５はそれぞれ表示素子を有する。画素２５に設けられる表示素子の例としては、液晶素子、発光素子などが挙げられる。液晶素子としては、透過型の液晶素子、反射型の液晶素子、半透過型の液晶素子などを用いることができる。また、表示素子として、シャッター方式のＭＥＭＳ（Ｍｉｃｒｏ　Ｅｌｅｃｔｒｏ　Ｍｅｃｈａｎｉｃａｌ　Ｓｙｓｔｅｍｓ）素子、光干渉方式のＭＥＭＳ素子、マイクロカプセル方式、電気泳動方式、エレクトロウェッティング方式、電子粉流体（登録商標）方式等を適用した表示素子などを用いることもできる。また、発光素子の例としては、例えばＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、ＬＥＤ（Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、ＱＬＥＤ（Ｑｕａｎｔｕｍ−ｄｏｔ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）、半導体レーザなどの、自発光性の発光素子が挙げられる。 FIG. 2A shows a configuration example of the display unit 20. The pixel portion 21 includes a plurality of pixels 25, and each pixel 25 includes a display element. Examples of the display element provided in the pixel 25 include a liquid crystal element and a light emitting element. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, or the like can be used. In addition, as a display element, a shutter type MEMS (Micro Electro Mechanical Systems) element, an optical interference type MEMS element, a microcapsule type, an electrophoretic method, an electrowetting method, an electropowder fluid (registered trademark) method, etc. are applied. A display element or the like can also be used. Examples of light-emitting elements include self-luminous light-emitting elements such as OLEDs (Organic Light Emitting Diodes), LEDs (Light Emitting Diodes), QLEDs (Quantum-dot Light Emitting Diodes), and semiconductor lasers.
画素２５はそれぞれ、配線ＳＬ及び配線ＧＬと接続されている。また、配線ＧＬはそれぞれ駆動回路２２と接続され、配線ＳＬはそれぞれ駆動回路２３と接続されている。配線ＧＬには選択信号が供給され、配線ＳＬには映像信号が供給される。 Each pixel 25 is connected to the wiring SL and the wiring GL. Further, the wiring GL is connected to the driving circuit 22, and the wiring SL is connected to the driving circuit 23. A selection signal is supplied to the wiring GL, and a video signal is supplied to the wiring SL.
駆動回路２２は、選択信号を画素２５に供給する機能を有する。具体的には、駆動回路２２は、配線ＧＬに選択信号を供給する機能を有し、配線ＧＬは、駆動回路２２から出力された選択信号を画素２５に伝える機能を有する。なお、配線ＧＬは、選択信号線、ゲート線などと呼ぶこともできる。 The drive circuit 22 has a function of supplying a selection signal to the pixel 25. Specifically, the drive circuit 22 has a function of supplying a selection signal to the wiring GL, and the wiring GL has a function of transmitting the selection signal output from the drive circuit 22 to the pixel 25. Note that the wiring GL can also be referred to as a selection signal line, a gate line, or the like.
駆動回路２３は、映像信号を画素２５に供給する機能を有する。具体的には、駆動回路２３は、配線ＳＬに映像信号を供給する機能を有し、配線ＳＬは、駆動回路２３から出力された映像信号を画素２５に伝える機能を有する。なお、配線ＳＬは、映像信号線、ソース線などと呼ぶこともできる。 The drive circuit 23 has a function of supplying a video signal to the pixels 25. Specifically, the drive circuit 23 has a function of supplying a video signal to the wiring SL, and the wiring SL has a function of transmitting the video signal output from the drive circuit 23 to the pixel 25. Note that the wiring SL can also be referred to as a video signal line, a source line, or the like.
図２（Ｂ）に、表示素子として発光素子を用いた画素２５の構成例を示す。図２（Ｂ）に示す画素２５は、トランジスタＴｒ１、Ｔｒ２、容量素子Ｃ１、発光素子ＬＥを有する。なお、ここではトランジスタＴｒ１、Ｔｒ２をｎチャネル型としているが、トランジスタの極性は適宜変更することができる。 FIG. 2B illustrates a configuration example of the pixel 25 using a light-emitting element as a display element. A pixel 25 illustrated in FIG. 2B includes transistors Tr1 and Tr2, a capacitor C1, and a light-emitting element LE. Although the transistors Tr1 and Tr2 are n-channel type here, the polarity of the transistors can be changed as appropriate.
トランジスタＴｒ１のゲートは配線ＧＬと接続され、ソース又はドレインの一方はトランジスタＴｒ２のゲート、及び容量素子Ｃ１の一方の電極と接続され、ソース又はドレインの他方は配線ＳＬと接続されている。トランジスタＴｒ２のソース又はドレインの一方は容量素子Ｃ１の他方の電極、及び発光素子ＬＥの一方の電極と接続され、ソース又はドレインの他方は電位Ｖａが供給される配線と接続されている。発光素子ＬＥの他方の電極は、電位Ｖｃが供給される配線と接続されている。トランジスタＴｒ１のソース又はドレインの一方、トランジスタＴｒ２のゲート、及び容量素子Ｃ１の一方の電極と接続されたノードを、ノードＮ１とする。また、トランジスタＴｒ２のソース又はドレインの一方、及び容量素子Ｃ１の他方の電極と接続されたノードを、ノードＮ２とする。 The gate of the transistor Tr1 is connected to the wiring GL, one of the source and the drain is connected to the gate of the transistor Tr2 and one electrode of the capacitor C1, and the other of the source and the drain is connected to the wiring SL. One of the source and the drain of the transistor Tr2 is connected to the other electrode of the capacitor C1 and the one electrode of the light emitting element LE, and the other of the source and the drain is connected to a wiring to which the potential Va is supplied. The other electrode of the light emitting element LE is connected to a wiring to which the potential Vc is supplied. A node connected to one of the source and the drain of the transistor Tr1, the gate of the transistor Tr2, and one electrode of the capacitor C1 is referred to as a node N1. A node connected to one of the source and the drain of the transistor Tr2 and the other electrode of the capacitor C1 is referred to as a node N2.
ここでは、電位Ｖａを高電源電位とし、電位Ｖｃを低電源電位とした場合について説明する。また、容量素子Ｃ１は、ノードＮ１の電位を保持するための保持容量としての機能を有する。 Here, a case where the potential Va is a high power supply potential and the potential Vc is a low power supply potential will be described. The capacitor C1 functions as a storage capacitor for holding the potential of the node N1.
トランジスタＴｒ１は、配線ＳＬの電位のノードＮ１への供給を制御する機能を有する。具体的には、配線ＧＬの電位を制御してトランジスタＴｒ１をオン状態とすることにより、映像信号に対応する配線ＳＬの電位がノードＮ１に供給され、画素２５の書き込みが行われる。その後、配線ＧＬの電位を制御してトランジスタＴｒ１をオフ状態とすることにより、ノードＮ１の電位が保持される。 The transistor Tr1 has a function of controlling supply of the potential of the wiring SL to the node N1. Specifically, by controlling the potential of the wiring GL and turning on the transistor Tr1, the potential of the wiring SL corresponding to the video signal is supplied to the node N1, and the pixel 25 is written. After that, the potential of the node N1 is held by controlling the potential of the wiring GL to turn off the transistor Tr1.
そして、ノードＮ１、Ｎ２の間の電圧に応じてトランジスタＴｒ２のソース−ドレインの間に流れる電流量が制御され、発光素子ＬＥが当該電流量に応じた輝度で発光する。これにより、画素２５の階調を制御することができる。なお、トランジスタＴｒ２は飽和領域で動作させることが好ましい。 Then, the amount of current flowing between the source and drain of the transistor Tr2 is controlled in accordance with the voltage between the nodes N1 and N2, and the light emitting element LE emits light with luminance corresponding to the amount of current. Thereby, the gradation of the pixel 25 can be controlled. Note that the transistor Tr2 is preferably operated in a saturation region.
上記の動作を配線ＧＬごとに順次行うことにより、第１フレーム分の映像を表示することができる。 By sequentially performing the above operation for each wiring GL, an image for the first frame can be displayed.
なお、配線ＧＬの選択には、プログレッシブ方式を用いてもよいし、インターレース方式を用いてもよい。また、配線ＳＬへの映像信号の供給は、配線ＳＬに順次映像信号を供給する点順次駆動を用いて行ってもよいし、全ての配線ＳＬに一斉に映像信号を供給する線順次駆動を用いて行ってもよい。また、複数の配線ＳＬごとに順に、映像信号を供給してもよい。 Note that the progressive method or the interlace method may be used to select the wiring GL. Further, the video signal may be supplied to the wiring SL using dot sequential driving for sequentially supplying the video signal to the wiring SL, or line sequential driving for supplying the video signal to all the wirings SL at the same time. You may go. Further, the video signal may be supplied in order for each of the plurality of wirings SL.
その後、第２のフレーム期間において、第１のフレーム期間と同様の動作により、映像の表示が行われる。これにより、画素部２１に表示される映像が書き換えられる。 After that, in the second frame period, video is displayed by the same operation as in the first frame period. Thereby, the video displayed on the pixel unit 21 is rewritten.
画素２５が有するトランジスタに用いられる半導体としては、シリコン、ゲルマニウムなどの第１４族の元素、ガリウムヒ素などの化合物半導体、有機半導体、金属酸化物などを用いることができる。また、半導体は、非単結晶半導体（非晶質半導体、微結晶半導体、多結晶半導体など）、であってもよいし、単結晶半導体であってもよい。 As a semiconductor used for the transistor included in the pixel 25, a Group 14 element such as silicon or germanium, a compound semiconductor such as gallium arsenide, an organic semiconductor, a metal oxide, or the like can be used. The semiconductor may be a non-single-crystal semiconductor (amorphous semiconductor, microcrystalline semiconductor, polycrystalline semiconductor, or the like) or a single-crystal semiconductor.
画素２５が有するトランジスタは、チャネル形成領域に非晶質半導体、特に、水素化アモルファスシリコン（ａ−Ｓｉ：Ｈ）を含むことが好ましい。非晶質半導体を用いたトランジスタは、基板の大面積化に対応することが容易であるため、例えば２Ｋ、４Ｋ、８Ｋ放送などに対応可能な大画面の表示装置を作製する場合に、製造工程を簡略化することができる。 The transistor included in the pixel 25 preferably includes an amorphous semiconductor, particularly hydrogenated amorphous silicon (a-Si: H), in a channel formation region. Since a transistor using an amorphous semiconductor can easily cope with an increase in area of a substrate, a manufacturing process is required when manufacturing a large-screen display device that can support 2K, 4K, 8K broadcasting, for example. Can be simplified.
また、画素２５が有するトランジスタには、チャネル形成領域に金属酸化物を含むトランジスタ（ＯＳトランジスタ）を用いることもできる。ＯＳトランジスタは、水素化アモルファスシリコンを用いたトランジスタと比較して電界効果移動度が高い。また、多結晶シリコンを用いたトランジスタなどで必要であった結晶化の工程が不要である。 As the transistor included in the pixel 25, a transistor including a metal oxide in a channel formation region (OS transistor) can be used. An OS transistor has higher field effect mobility than a transistor using hydrogenated amorphous silicon. In addition, the crystallization step required for a transistor using polycrystalline silicon is not necessary.
また、ＯＳトランジスタはオフ電流が極めて小さいため、トランジスタＴｒ１としてＯＳトランジスタを用いる場合、画素２５に映像信号を極めて長期間にわたって保持することができる。これにより、画素部２１に表示される映像に変化がない期間、又は変化が一定以下である期間において、映像信号の更新の頻度を極めて低く設定することができる。映像信号の更新の頻度は、例えば、０．１秒間に１回以下、又は、１秒間に１回以下、又は、１０秒間に１回以下などに設定することができる。特に、２Ｋ、４Ｋ、８Ｋ放送などに対応して画素２５が多数設けられる場合は、映像信号の更新を省略することによって消費電力を低減することは効果的である。 In addition, since the off-state current of the OS transistor is extremely small, when the OS transistor is used as the transistor Tr1, a video signal can be held in the pixel 25 for a very long time. Thereby, the update frequency of the video signal can be set very low during a period in which the video displayed on the pixel unit 21 does not change or in a period in which the change is below a certain level. The frequency of updating the video signal can be set to, for example, not more than once every 0.1 seconds, or less than once per second, or less than once every 10 seconds. In particular, when many pixels 25 are provided corresponding to 2K, 4K, 8K broadcasting, etc., it is effective to reduce power consumption by omitting the update of the video signal.
画素２５に発光素子を用いた場合、液晶素子を用いる場合と異なりバックライトが不要となる。そのため、発光素子を用いることにより、表示部２０の軽量化、薄型化、又は低消費電力化を図ることができる。また、画素２５に発光素子を用いた場合、黒画像の表示を、発光素子を非発光状態とすることにより行うことができる。これにより、バックライトの光漏れが生じ得る液晶素子を用いる場合と比較して、黒画像をより黒く表示することができる。 When a light emitting element is used for the pixel 25, a backlight is not required unlike when a liquid crystal element is used. Therefore, by using a light emitting element, the display portion 20 can be reduced in weight, thickness, or power consumption. When a light emitting element is used for the pixel 25, a black image can be displayed by setting the light emitting element to a non-light emitting state. As a result, the black image can be displayed blacker than when using a liquid crystal element that may cause light leakage from the backlight.
発光素子の輝度の制御は、発光素子を流れる電流を駆動トランジスタ（図２（Ｂ）におけるトランジスタＴｒ２に相当）によって制御することにより行われる。しかしながら、各画素２５が有する駆動トランジスタの特性にばらつきがある場合、輝度のばらつきが生じ得る。例えば、駆動トランジスタのゲインのばらつきにより、ノードＮ１に所定の映像信号が供給された際に、トランジスタＴｒ２のソース—ドレイン間を流れる電流のばらつきが生じ、意図した輝度の発光が得られず画素２５の階調に誤差が生じる場合がある。 The luminance of the light-emitting element is controlled by controlling the current flowing through the light-emitting element with a driving transistor (corresponding to the transistor Tr2 in FIG. 2B). However, when there are variations in the characteristics of the drive transistors of each pixel 25, variations in luminance can occur. For example, when a predetermined video signal is supplied to the node N1 due to variations in the gain of the drive transistor, variations in current flowing between the source and drain of the transistor Tr2 occur, and light emission with an intended luminance cannot be obtained. In some cases, an error occurs in the gray scale.
また、ゲインのばらつきに起因する輝度のばらつきの影響は、特に低輝度での発光、すなわち暗い映像を表示する際に大きくなる。そのため、黒表示時にも僅かに発光素子が発光してしまう現象（黒浮き）、黒表示時に濃い黒と薄い黒が混在する現象などが発生し、表示品質を損なう場合がある。 In addition, the influence of the luminance variation caused by the gain variation is particularly great when light emission at a low luminance, that is, when a dark image is displayed. For this reason, a phenomenon in which the light emitting element slightly emits light during black display (black floating) and a phenomenon in which dark black and light black are mixed during black display may occur, which may impair display quality.
ここで、本発明の一態様においては、画素に設けられた発光素子の輝度に応じて、アナログ値の輝度によって階調を表示する方式（以下、アナログ階調方式ともいう）とデジタル値の輝度によって階調を表示する方式（以下、デジタル階調方式ともいう）が選択的に用いられる。具体的には、画素に設けられた発光素子が所定の値以上の輝度での発光を要求される場合はアナログ階調方式が用いられ、所定の値よりも低い輝度での発光を要求される場合はデジタル階調方式が用いられる。これにより、特に暗い映像を表示する際の輝度のばらつきを抑えることができ、映像の品質を向上させることができる。上記の動作について、以下詳述する。 Here, in one embodiment of the present invention, a method of displaying gray scales with luminance of an analog value (hereinafter also referred to as an analog gray scale method) and a luminance of a digital value in accordance with the luminance of a light-emitting element provided in a pixel A method for displaying gray scales (hereinafter also referred to as a digital gray scale method) is selectively used. Specifically, when a light emitting element provided in a pixel is required to emit light with a luminance higher than a predetermined value, an analog gradation method is used, and light emission with a luminance lower than a predetermined value is required. In this case, a digital gradation method is used. As a result, it is possible to suppress variation in luminance particularly when displaying a dark video, and to improve the quality of the video. The above operation will be described in detail below.
図３に示すように、画像処理回路３３にはデータＤｘ及びデータＤｙが入力される。データＤｘは、画像データＤｉに含まれるデータであり、画素２５が表示する階調に対応するデータである。具体的には、データＤｘは、画素２５に設けられた発光素子を輝度Ｘで発光させるためのデータである。また、データＤｙは、発光素子を輝度Ｙで発光させるためのデータである。 As shown in FIG. 3, data Dx and data Dy are input to the image processing circuit 33. Data Dx is data included in the image data Di, and is data corresponding to the gradation displayed by the pixel 25. Specifically, the data Dx is data for causing the light emitting element provided in the pixel 25 to emit light with luminance X. Data Dy is data for causing the light emitting element to emit light with luminance Y.
輝度Ｙは、画素２５に設けられた発光素子が発することができる光の輝度のうち、輝度のばらつきが一定以下の最低輝度（輝度のばらつきが所定の範囲内に収まる最低輝度）である。すなわち、発光素子がＹ以上の輝度で発光する場合は、輝度のばらつきが小さいと言える。なお、輝度のばらつきは、画素２５に所定の映像信号が供給された際に発光素子が発する光の輝度の誤差に相当する。 The luminance Y is the lowest luminance of the light that can be emitted from the light emitting element provided in the pixel 25, with the luminance variation being equal to or less than a certain value (the lowest luminance within which the luminance variation is within a predetermined range). That is, when the light emitting element emits light with a luminance higher than Y, it can be said that the variation in luminance is small. Note that the luminance variation corresponds to an error in luminance of light emitted from the light emitting element when a predetermined video signal is supplied to the pixel 25.
なお、上記の所定の範囲は、映像の内容、周囲の環境、ユーザーなどに応じて自由に設定することができる。 The predetermined range can be freely set according to the content of the video, the surrounding environment, the user, and the like.
また、発光素子の輝度を“０”、すなわち非発光の状態とするためのデータを、データＤ０と表記する。輝度“０”は発光素子が非発光の状態を示すため、輝度のばらつきは無視できる。 Further, data for setting the luminance of the light emitting element to “0”, that is, a non-light emitting state is represented as data D 0 . The luminance “0” indicates that the light emitting element is in a non-light emitting state, and thus the luminance variation can be ignored.
図３に示すように、発光素子を輝度Ｙよりも低い輝度で発光させる必要がある場合（Ｘ＜Ｙの場合）、画像処理回路３３は、データＤｙ及びデータＤ０を用いて、輝度Ｘを実現するための映像信号を生成する。輝度Ｘを、ばらつきが生じにくい輝度Ｙ及び輝度“０”を用いて実現することにより、特に暗い映像の品質を向上させることができる。 As shown in FIG. 3, when the light emitting element needs to emit light at a luminance lower than the luminance Y (when X <Y), the image processing circuit 33 uses the data Dy and the data D 0 to set the luminance X. A video signal for realization is generated. By realizing the luminance X by using the luminance Y and the luminance “0” that are less likely to vary, the quality of particularly dark images can be improved.
具体的には、まずＸ≧Ｙである場合は、信号ＳＤとしてデータＤｘが出力される。このときの輝度Ｘはばらつきが小さい輝度であるため、データＤｘにより輝度Ｘの発光が正確に得られる。データＤｘはアナログ値に変換された後、画素２５に供給される。これにより、発光素子の輝度はアナログ値となり、画素２５はアナログ階調方式で階調を表示することができる。 Specifically, first, when X ≧ Y, the data Dx is output as the signal SD. Since the luminance X at this time is a luminance with small variations, light emission of the luminance X can be accurately obtained from the data Dx. The data Dx is converted into an analog value and then supplied to the pixel 25. As a result, the luminance of the light emitting element becomes an analog value, and the pixel 25 can display a gradation in an analog gradation method.
一方、Ｘ＜Ｙである場合は輝度Ｘのばらつきが大きいため、データＤｘを用いて輝度Ｘの発光を得ようとしても、正確な輝度が得られない場合がある。ここで、画像処理回路３３は、輝度Ｘと乱数ＲＮＤを比較し、当該比較の結果に応じてデータＤｙ又はデータＤ０を信号ＳＤとして出力する機能を有する。この乱数ＲＮＤは、０からＹまでの数列によって構成される乱数である。これにより、画素２５はデジタル階調方式で階調を表示することができる。 On the other hand, when X <Y, since the variation in the luminance X is large, there may be a case where accurate luminance cannot be obtained even if light emission of luminance X is obtained using the data Dx. Here, the image processing circuit 33 has a function of comparing the brightness X and the random number RND, and outputs the data Dy or data D 0 in accordance with the result of the comparison as a signal SD. This random number RND is a random number constituted by a sequence of numbers from 0 to Y. Thereby, the pixel 25 can display a gradation by a digital gradation method.
より具体的には、輝度Ｘが輝度Ｙ未満且つ乱数ＲＮＤよりも大きい場合は（ＲＮＤ＜Ｘ＜Ｙ）、信号ＳＤとしてデータＤｙが出力される。一方、輝度Ｘが乱数ＲＮＤ以下である場合は（Ｘ≦ＲＮＤ）、信号ＳＤとしてデータＤ０が出力される。このとき、発光素子が輝度Ｙで発光する確率は（Ｘ／Ｙ）となる。したがって、複数フレームに渡る発光素子の輝度の時間平均、及び、複数の発光素子が集合した領域の輝度の面積平均は、Ｘとなる。すなわち、ばらつきの小さい輝度Ｙ及び輝度“０”をデジタル値として用いた時間階調方式又は面積階調方式によって輝度Ｘが実現される。 More specifically, when the luminance X is less than the luminance Y and larger than the random number RND (RND <X <Y), the data Dy is output as the signal SD. Meanwhile, when the luminance X is less than the random number RND (X ≦ RND), data D 0 is output as the signal SD. At this time, the probability that the light emitting element emits light with luminance Y is (X / Y). Accordingly, the time average of the luminance of the light emitting elements over a plurality of frames and the area average of the luminance of a region where the plurality of light emitting elements are gathered are X. That is, the luminance X is realized by the time gradation method or the area gradation method using the luminance Y and the luminance “0” with small variations as digital values.
なお、時間階調方式は、発光素子が発光する期間によって階調を制御する方法である。また、面積階調方式は、発光素子が発光する面積によって階調を制御する方法である。上記の時間階調方式と面積階調方式はいずれも、輝度Ｙ及び輝度“０”によって階調が表示されるデジタル階調方式である。 Note that the time gray scale method is a method of controlling gray scale according to a period during which a light emitting element emits light. The area gray scale method is a method in which the gray scale is controlled by the area where the light emitting element emits light. Both the time gray scale method and the area gray scale method are digital gray scale methods in which a gray scale is displayed with luminance Y and luminance “0”.
輝度Ｘがデジタル階調方式によって表現される場合、輝度の精度を上げるためには、フレーム周波数を高くする、又は、画素２５の密度を高くすることが効果的である。そのため、例えばフレーム周波数を６０Ｈｚ以上、好ましくは１２０Ｈｚ以上などとすることにより、時間階調方式による階調表示の精度を向上させることができる。また、画素部２１の解像度を２Ｋ、４Ｋ、８Ｋ、１６Ｋ、またはそれ以上などとし、空間分解能を上げることにより、面積階調方式による階調表示の精度を向上させることができる。なお、フレーム周波数を所定の範囲内（例えば、１Ｈｚ以上１２０Ｈｚ以下など）で可変とし、表示される映像に応じてフレーム周波数を変更することもできる。 When the luminance X is expressed by a digital gradation method, it is effective to increase the frame frequency or the density of the pixels 25 in order to increase the accuracy of the luminance. Therefore, for example, by setting the frame frequency to 60 Hz or more, preferably 120 Hz or more, the accuracy of gradation display by the time gradation method can be improved. Further, by setting the resolution of the pixel portion 21 to 2K, 4K, 8K, 16K, or higher and increasing the spatial resolution, it is possible to improve the accuracy of gradation display by the area gradation method. Note that the frame frequency can be varied within a predetermined range (for example, 1 Hz to 120 Hz), and the frame frequency can be changed according to the displayed video.
輝度Ｙの値は、表示部２０の表示試験の結果、発光素子又は駆動トランジスタの特性、フレーム周波数などを考慮して設定してもよいし、ユーザーが映像を視認しながら手動で設定してもよい。また、輝度Ｙの値は、映像の内容、周囲の環境、ユーザーなどに応じて切り替えることもできる。また、実施の形態２で説明するように、人工知能を用いて輝度Ｙの値を決定することもできる。 The value of the luminance Y may be set in consideration of the result of the display test of the display unit 20, the characteristics of the light emitting element or the driving transistor, the frame frequency, etc., or may be set manually while the user is viewing the video. Good. Further, the value of the luminance Y can be switched according to the content of the video, the surrounding environment, the user, and the like. Further, as described in the second embodiment, the value of luminance Y can be determined using artificial intelligence.
上記のように、画像処理回路３３が画像データＤｉに基づいてデータＤｘ、データＤｙ、及びデータＤ０を出力する機能を有することにより、アナログ階調方式及びデジタル階調方式を用いた映像の表示が可能となる。 As described above, the image processing circuit 33 based on the image data Di data Dx, by having a function of outputting the data Dy, and the data D 0, the display of images using an analog gray scale method and the digital gray scale method Is possible.
＜画像処理部の構成例＞
次に、画像処理回路３３の具体的な構成例について説明する。図４に示す画像処理回路３３は、処理回路１０１、乱数生成回路１０２、比較回路１０３を有する。 <Configuration Example of Image Processing Unit>
Next, a specific configuration example of the image processing circuit 33 will be described. The image processing circuit 33 illustrated in FIG. 4 includes a processing circuit 101, a random number generation circuit 102, and a comparison circuit 103.
処理回路１０１は、デコーダ３２から入力された画像データＤｉに画像処理を施し、比較回路１０３に出力する機能を有する。画像処理の例は前述の通りであり、ノイズ除去処理、階調変換処理、色調補正処理、輝度補正処理などが挙げられる。なお、処理回路１０１から出力される画像データＤｉにはデータＤｘが含まれる。 The processing circuit 101 has a function of performing image processing on the image data Di input from the decoder 32 and outputting the processed image data to the comparison circuit 103. Examples of image processing are as described above, and examples include noise removal processing, gradation conversion processing, color tone correction processing, and luminance correction processing. The image data Di output from the processing circuit 101 includes data Dx.
乱数生成回路１０２は、０からＹまでの数列によって構成される乱数ＲＮＤを生成し、比較回路１０３に出力する機能を有する。なお、乱数生成回路１０２は、画像処理回路３３の外部に設けられていてもよい。 The random number generation circuit 102 has a function of generating a random number RND composed of a sequence of numbers from 0 to Y and outputting the random number RND to the comparison circuit 103. Note that the random number generation circuit 102 may be provided outside the image processing circuit 33.
比較回路１０３は、画像データＤｉに含まれるデータＤｘに対応する輝度Ｘと、データＤｙに対応する輝度Ｙの比較、及び、輝度Ｘと乱数ＲＮＤの比較を行い、当該比較の結果に応じた信号ＳＤを出力する機能を有する。具体的には、比較回路１０３は、Ｘ≧Ｙの場合はデータＤｘを、ＲＮＤ＜Ｘ＜Ｙの場合はデータＤｙを、Ｘ≦ＲＮＤの場合はデータＤ０を、信号ＳＤとして出力する機能を有する。そして、信号ＳＤは駆動回路２３を介して画素部２１に供給される。なお、データＤｙは、記憶回路を用いて比較回路１０３の内部に格納されていてもよい。 The comparison circuit 103 compares the luminance X corresponding to the data Dx included in the image data Di with the luminance Y corresponding to the data Dy, and compares the luminance X and the random number RND, and a signal corresponding to the result of the comparison It has a function to output SD. Specifically, the comparison circuit 103, the data Dx in the case of X ≧ Y, a data Dy For RND <X <Y, the data D 0 in the case of X ≦ RND, a function of outputting a signal SD Have. The signal SD is supplied to the pixel unit 21 via the drive circuit 23. Note that the data Dy may be stored in the comparison circuit 103 using a memory circuit.
以上のように、画像処理回路３３は画像処理を行う機能に加え、輝度Ｘ、輝度Ｙ、乱数ＲＮＤに基づいて駆動回路２３に出力される映像信号を選択する機能を有する。これにより、アナログ階調方式で用いられるデータＤｘと、デジタル階調方式で用いられるデータＤｙ及びデータＤ０を生成することができる。 As described above, the image processing circuit 33 has a function of selecting a video signal output to the drive circuit 23 based on the luminance X, the luminance Y, and the random number RND in addition to the function of performing image processing. Thus, it is possible to generate the data Dx used in analog gray scale method, the data Dy and data D 0 is used in a digital gray scale method.
なお、乱数生成回路１０２から出力される乱数ＲＮＤの切り替えの周期は、画像処理回路３３に１フレーム分の画像データが入力される周期よりも高く設定することが好ましい。これにより、輝度Ｘの精度を向上させることができる。 Note that the cycle of switching the random number RND output from the random number generation circuit 102 is preferably set higher than the cycle in which image data for one frame is input to the image processing circuit 33. Thereby, the precision of the brightness | luminance X can be improved.
＜画像処理部の動作例＞
次に、画像処理回路３３の動作例について説明する。図５は、画像処理回路３３の動作例を示すフローチャートである。 <Operation example of image processing unit>
Next, an operation example of the image processing circuit 33 will be described. FIG. 5 is a flowchart showing an operation example of the image processing circuit 33.
まず、デコーダ３２からデータＤｘを含む画像データＤｉが出力され、画像処理回路３３にデータＤｘが入力される（ステップＳ１）。そして、画像処理回路３３はデータＤｘに適宜画像処理を施す（ステップＳ２）。 First, image data Di including data Dx is output from the decoder 32, and the data Dx is input to the image processing circuit 33 (step S1). Then, the image processing circuit 33 appropriately performs image processing on the data Dx (step S2).
データＤｘに対応する輝度ＸがＹ以上である場合は（ステップＳ３でＹＥＳ）、データＤｘが信号ＳＤとして駆動回路２３に出力される（ステップＳ４）。 When the luminance X corresponding to the data Dx is Y or more (YES in step S3), the data Dx is output to the drive circuit 23 as the signal SD (step S4).
このときの輝度Ｘはばらつきが小さいため、データＤｘによって発光素子は正確に輝度Ｘで発光する。よって、データＤｘがアナログ値として画素２５に供給されるアナログ階調方式により、輝度Ｘを得ることができる。 Since the luminance X at this time has a small variation, the light emitting element emits light accurately with the luminance X based on the data Dx. Therefore, the luminance X can be obtained by an analog gradation method in which the data Dx is supplied to the pixel 25 as an analog value.
一方、輝度Ｘが輝度Ｙ未満である場合（ステップＳ３でＮＯ）、輝度Ｘと乱数ＲＮＤが比較される。そして、Ｘ＞ＲＮＤの場合は、データＤｘにデータＤｙが代入され（ステップＳ６）、データＤｙが信号ＳＤとして出力される（ステップＳ４）。また、Ｘ≦ＲＮＤの場合は、データＤｘにデータＤ０が代入され（ステップＳ７）、データＤ０が信号ＳＤとして出力される（ステップＳ４）。これにより、（Ｘ／Ｙ）の確率でデータＤｙが出力される。 On the other hand, when the luminance X is less than the luminance Y (NO in step S3), the luminance X and the random number RND are compared. If X> RND, data Dy is substituted for data Dx (step S6), and data Dy is output as signal SD (step S4). In the case of X ≦ RND, the data D 0 is assigned to the data Dx (step S7), and the data D 0 is output as the signal SD (step S4). As a result, the data Dy is output with a probability of (X / Y).
画素２５にデータＤｙが供給されることにより輝度Ｙが得られ、データＤ０が供給されることにより輝度“０”が得られる。そして、輝度Ｙ及び輝度“０”をデジタル値として用いたデジタル階調方式により、輝度Ｘを得ることができる。 Luminance Y is obtained by supplying data Dy to the pixel 25, and luminance “0” is obtained by supplying data D 0 . The luminance X can be obtained by a digital gradation method using the luminance Y and the luminance “0” as digital values.
なお、ステップＳ３及びステップＳ５における比較は、図４に示す比較回路１０３などを用いて行うことができる。 Note that the comparison in step S3 and step S5 can be performed using the comparison circuit 103 shown in FIG.
以上の通り、本発明の一態様においては、映像の表示に用いられる光の輝度が高く、ばらつきが小さい場合は、当該輝度に対応する映像信号を画素に供給するアナログ階調方式により、画素の階調が制御され、映像が表示される。一方、映像の表示に用いられる光の輝度が低く、ばらつきが大きい場合は、２値の輝度（Ｙ及び“０”）を用いたデジタル階調方式により、画素の階調が制御され、映像が表示される。これにより、明るい映像の品質を維持しつつ、暗い映像の表示時における表示不良を防止することが可能となり、高品質な映像を得ることができる。 As described above, in one embodiment of the present invention, when the luminance of light used for video display is high and the variation is small, the analog gradation method for supplying a video signal corresponding to the luminance to the pixel is used. The gradation is controlled and the video is displayed. On the other hand, when the luminance of light used for image display is low and the variation is large, the gradation of pixels is controlled by a digital gradation method using binary luminance (Y and “0”), and the image is displayed. Is displayed. As a result, it is possible to prevent display defects when displaying dark images while maintaining the quality of bright images, and high-quality images can be obtained.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
（実施の形態２）
本実施の形態では、上記実施の形態で説明した表示システムの他の構成例について説明する。具体的には、画像処理回路３３において用いられる輝度Ｙの値を、人工知能を用いて決定する構成について説明する。 (Embodiment 2)
In this embodiment, another structure example of the display system described in the above embodiment is described. Specifically, a configuration for determining the value of luminance Y used in the image processing circuit 33 using artificial intelligence will be described.
図６（Ａ）に、画像処理回路３３の構成例を示す。図６（Ａ）に示す画像処理回路３３は、演算回路１０４を有し、データＤｙが演算回路１０４から出力される点において図４と異なる。 FIG. 6A shows a configuration example of the image processing circuit 33. An image processing circuit 33 illustrated in FIG. 6A includes an arithmetic circuit 104 and is different from FIG. 4 in that data Dy is output from the arithmetic circuit 104.
演算回路１０４は、人工知能（ＡＩ：Ａｒｔｉｆｉｃｉａｌ　Ｉｎｔｅｌｌｉｇｅｎｃｅ）を利用して、輝度Ｙに対応するデータＤｙを生成する機能を有する。具体的には、演算回路１０４は人工ニューラルネットワーク（ＡＮＮ：Ａｒｔｉｆｉｃｉａｌ　Ｎｅｕｒａｌ　Ｎｅｔｗｏｒｋ）を有する。当該人工ニューラルネットワークの学習により、画像データＤｉに基づいて輝度Ｙの値を算出する機能が、演算回路１０４に付与される。そして、学習後の人工ニューラルネットワークに画像データＤｉを入力して推論を行うことにより、データＤｙを得ることができる。 The arithmetic circuit 104 has a function of generating data Dy corresponding to the luminance Y by using artificial intelligence (AI). Specifically, the arithmetic circuit 104 has an artificial neural network (ANN: Artificial Neural Network). A function of calculating the value of the luminance Y based on the image data Di is given to the arithmetic circuit 104 by learning of the artificial neural network. The data Dy can be obtained by inputting the image data Di to the learned artificial neural network and performing inference.
なお、人工知能とは、人間の知能を模した計算機である。また、人工ニューラルネットワークとは、ニューロンとシナプスで構成される神経網を模した回路であり、学習によってニューロン間の結合強度（重み係数ともいう）を決定することができる。また、学習によって得られた結合強度を用いてニューラルネットワークを構成し、そこから新たな結論を導くことを推論（認知）と呼ぶ。なお、人工ニューラルネットワークは人工知能の一種である。本明細書等において「ニューラルネットワーク」と記載する場合、特に人工ニューラルネットワークを指す。 Artificial intelligence is a computer that mimics human intelligence. An artificial neural network is a circuit simulating a neural network composed of neurons and synapses, and can determine the connection strength between neurons (also referred to as a weighting factor) by learning. Also, constructing a neural network using the connection strength obtained by learning and deriving a new conclusion therefrom is called inference (cognition). An artificial neural network is a kind of artificial intelligence. In this specification and the like, the term “neural network” particularly refers to an artificial neural network.
演算回路１０４が有するニューラルネットワークＮＮの構成例を、図７に示す。ニューラルネットワークＮＮは、ニューロン回路と、ニューロン回路間に設けられたシナプス回路によって構成される。 A configuration example of the neural network NN included in the arithmetic circuit 104 is shown in FIG. The neural network NN includes a neuron circuit and a synapse circuit provided between the neuron circuits.
図７（Ａ）に、ニューラルネットワークＮＮを構成するニューロン回路ＮＣとシナプス回路ＳＣの構成例を示す。シナプス回路ＳＣには、入力データｘ１乃至ｘＬ（Ｌは１以上の自然数）が入力される。また、シナプス回路ＳＣは、重み係数ｗｉ（ｉは１以上Ｌ以下の整数）を記憶する機能を有する。重み係数ｗｉは、ニューロン回路ＮＣ間の結合の強さに対応する。 FIG. 7A shows a configuration example of the neuron circuit NC and the synapse circuit SC constituting the neural network NN. Input data x 1 to x L (L is a natural number of 1 or more) is input to the synapse circuit SC. In addition, the synapse circuit SC has a function of storing a weight coefficient w i (i is an integer of 1 to L). The weighting factor w i corresponds to the strength of the connection between the neuron circuits NC.
シナプス回路ＳＣに入力データｘ１乃至ｘＬが入力されると、ニューロン回路ＮＣには、シナプス回路ＳＣに入力された入力データｘｉと、シナプス回路ＳＣに記憶された重み係数ｗｉとの積（ｘｉｗｉ）を、ｉ＝１乃至Ｌについて足し合わせた値（ｘ１ｗ１＋ｘ２ｗ２＋…＋ｘＬｗＬ）、すなわち、ｘｉとｗｉを用いた積和演算によって得られた値が供給される。この値がニューロン回路ＮＣの閾値θを超えた場合、ニューロン回路ＮＣはハイレベルの信号ｙを出力する。この現象を、ニューロン回路ＮＣの発火と呼ぶ。 When the input data x 1 to x L are input to the synapse circuit SC, the neuron circuit NC has a product of the input data x i input to the synapse circuit SC and the weight coefficient w i stored in the synapse circuit SC. (X i w i ) is obtained by adding the values of i = 1 to L (x 1 w 1 + x 2 w 2 +... + X L w L ), that is, by product-sum operation using x i and w i. The supplied value is supplied. When this value exceeds the threshold value θ of the neuron circuit NC, the neuron circuit NC outputs a high level signal y. This phenomenon is called firing of the neuron circuit NC.
ニューロン回路ＮＣとシナプス回路ＳＣを用いて、階層型パーセプトロンを構成するニューラルネットワークＮＮのモデルを、図７（Ｂ）に示す。ニューラルネットワークＮＮは、入力層ＩＬ、隠れ層（中間層）ＨＬ、出力層ＯＬを有する。 FIG. 7B shows a model of a neural network NN that forms a hierarchical perceptron using the neuron circuit NC and the synapse circuit SC. The neural network NN has an input layer IL, a hidden layer (intermediate layer) HL, and an output layer OL.
入力層ＩＬから、入力データｘ１乃至ｘＬが出力される。隠れ層ＨＬは、隠れシナプス回路ＨＳ、隠れニューロン回路ＨＮを有する。出力層ＯＬは、出力シナプス回路ＯＳ、出力ニューロン回路ＯＮを有する。 Input data x 1 to x L are output from the input layer IL. The hidden layer HL has a hidden synapse circuit HS and a hidden neuron circuit HN. The output layer OL has an output synapse circuit OS and an output neuron circuit ON.
隠れニューロン回路ＨＮには、入力データｘｉと、隠れシナプス回路ＨＳに保持された重み係数ｗｉと、を用いた積和演算によって得られた値が供給される。そして、出力ニューロン回路ＯＮには、隠れニューロン回路ＨＮの出力と、出力シナプス回路ＯＳに保持された重み係数ｗｉを用いた積和演算によって得られた値が供給される。そして、出力ニューロン回路ＯＮから、出力データｙ１乃至ｙＬが出力される。なお、ニューラルネットワークＮＮにおいて、隠れ層ＨＬは複数設けられていてもよい。 The hidden neuron circuit HN is supplied with a value obtained by a product-sum operation using the input data x i and the weighting coefficient w i held in the hidden synapse circuit HS. The output neuron circuit ON is supplied with the value obtained by the product-sum operation using the output of the hidden neuron circuit HN and the weighting coefficient w i held in the output synapse circuit OS. Then, output data y 1 to y L are output from the output neuron circuit ON. In the neural network NN, a plurality of hidden layers HL may be provided.
このように、所定の入力データが与えられたニューラルネットワークＮＮは、シナプス回路ＳＣに保持された重み係数と、ニューロン回路の閾値θに応じた値を、出力データとして出力する機能を有する。 As described above, the neural network NN to which predetermined input data is given has a function of outputting, as output data, a value corresponding to the weighting coefficient held in the synapse circuit SC and the threshold value θ of the neuron circuit.
また、ニューラルネットワークＮＮは、教師データの入力によって教師あり学習を行うことができる。図７（Ｃ）に、誤差逆伝播法を利用して教師あり学習を行うニューラルネットワークＮＮのモデルを示す。 The neural network NN can perform supervised learning by inputting teacher data. FIG. 7C shows a model of the neural network NN that performs supervised learning using the error back propagation method.
誤差逆伝播方式は、ニューラルネットワークの出力データと教師信号の誤差が小さくなるように、シナプス回路の重み係数ｗｉを変更する方式である。具体的には、出力データｙ１乃至ｙＬと教師信号ｔ１乃至ｔｎに基づいて決定される誤差δＯに応じて、隠れシナプス回路ＨＳの重み係数ｗｉが変更される。また、隠れシナプス回路ＨＳの重み係数ｗｉの変更量に応じて、さらに前段のシナプス回路ＳＣの重み係数ｗｉが変更される。このように、教師信号ｔ１乃至ｔｎに基づいて、シナプス回路ＳＣの重み係数を順次変更することにより、ニューラルネットワークＮＮの学習を行うことができる。 The error back propagation method is a method of changing the weighting factor w i of the synapse circuit so that the error between the output data of the neural network and the teacher signal becomes small. Specifically, the weighting factor w i of the hidden synapse circuit HS is changed according to the error δ O determined based on the output data y 1 to y L and the teacher signals t 1 to t n . Further, in accordance with the change amount of the weighting coefficient w i of the hidden synapse circuit HS, further weighting coefficients w i of the previous synapse circuit SC is changed. As described above, the neural network NN can be learned by sequentially changing the weighting coefficient of the synapse circuit SC based on the teacher signals t 1 to t n .
なお、図７（Ｂ）、（Ｃ）には１層の隠れ層ＨＬを示しているが、隠れ層ＨＬの層数は特に限定されず、２以上であってもよい。隠れ層ＨＬを２層以上有するニューラルネットワーク（ディープニューラルネットワーク（ＤＮＮ））を用いることにより、深層学習を行うことができる。 7B and 7C show one hidden layer HL, the number of hidden layers HL is not particularly limited, and may be two or more. Deep learning can be performed by using a neural network having two or more hidden layers HL (deep neural network (DNN)).
演算回路１０４には、処理回路１０１から画像データＤｉが入力される。そして、ニューラルネットワークＮＮは、画像データＤｉを用いて所定の演算を行い、出力データを比較回路１０３に出力する。当該出力データがデータＤｙの初期値となる。そして、データＤｙを用いて信号ＳＤが生成され、駆動回路２３を介して画素部２１に供給される。 Image data Di is input from the processing circuit 101 to the arithmetic circuit 104. The neural network NN performs a predetermined calculation using the image data Di and outputs output data to the comparison circuit 103. The output data becomes the initial value of the data Dy. Then, a signal SD is generated using the data Dy and supplied to the pixel unit 21 via the drive circuit 23.
次に、ニューラルネットワークＮＮの学習が行われる。図６（Ｂ）に示すように、学習時、ニューラルネットワークＮＮには画像データＤｉとデータＤＤｉが入力される。ここで、画像データＤｉは画素部２１に表示しようとする映像に対応するデータであり、データＤＤｉは画素部２１に実際に表示された映像に対応するデータである。データＤＤｉは、例えば、画素部２１に表示された映像をイメージセンサなどで撮像することにより取得することができる。 Next, learning of the neural network NN is performed. As shown in FIG. 6B, at the time of learning, image data Di and data DDi are input to the neural network NN. Here, the image data Di is data corresponding to the video to be displayed on the pixel unit 21, and the data DDi is data corresponding to the video actually displayed on the pixel unit 21. The data DDi can be acquired by, for example, capturing an image displayed on the pixel unit 21 with an image sensor or the like.
そして、データＤＤｉと画像データＤｉの誤差が一定以下となるように、すなわち、画素部２１に表示しようとする映像と実際に画素部２１に表示された映像の誤差が一定以下になるように、ニューラルネットワークＮＮの重み係数が更新される。そして、重み係数の更新に伴い、ニューラルネットワークＮＮの出力データＤｙも更新される。そして、最終的にデータＤＤｉと画像データＤｉの誤差が一定以下になるまでデータＤｙが更新されると、ニューラルネットワークＮＮの学習が終了する。 Then, the error between the data DDi and the image data Di is less than a certain value, that is, the error between the image to be displayed on the pixel unit 21 and the image actually displayed on the pixel unit 21 is less than a certain value. The weighting coefficient of the neural network NN is updated. The output data Dy of the neural network NN is also updated with the update of the weighting factor. Then, when the data Dy is updated until the error between the data DDi and the image data Di finally becomes a certain value or less, the learning of the neural network NN is finished.
重み係数の更新には、前述の誤差逆伝播法などを用いることができる。また、ニューラルネットワークＮＮの重み係数の初期値は、乱数によって決定してもよい。なお、重み係数の初期値は学習速度（例えば、重み係数の収束速度、ニューラルネットワークＮＮの予測精度など）に影響を与える場合があるため、学習速度が遅い場合は、重み係数の初期値を変更してもよい。 For updating the weighting coefficient, the above-described error back propagation method or the like can be used. The initial value of the weighting factor of the neural network NN may be determined by a random number. Note that the initial value of the weighting coefficient may affect the learning speed (for example, the convergence speed of the weighting coefficient, the prediction accuracy of the neural network NN, etc.). If the learning speed is slow, the initial value of the weighting coefficient is changed. May be.
学習後のニューラルネットワークＮＮにデータＤｉが入力され推論が行われると、データＤｙが出力される。そして、このデータＤｙは、画素部２１に輝度の誤差の小さい映像が表示されるように更新されている。このように、データＤｙの生成にニューラルネットワークＮＮを用いることにより、実際に表示された映像に基づいて輝度Ｙを決定することができる。これにより、アナログ階調方式とデジタル階調方式の切り替えの基準を適切に設定することができる。 When the data Di is input to the learned neural network NN and inference is performed, the data Dy is output. The data Dy is updated so that an image with a small luminance error is displayed on the pixel unit 21. Thus, by using the neural network NN to generate the data Dy, the luminance Y can be determined based on the actually displayed video. Thereby, it is possible to appropriately set a reference for switching between the analog gradation method and the digital gradation method.
なお、上記のニューラルネットワークＮＮの学習は、信号生成部３０の外部に設けられた演算処理装置などを用いて行うことができる。当該演算処理装置としては、専用サーバやクラウドなどの演算処理能力の優れた計算機を用いることができる。演算処理装置にニューラルネットワークＮＮに対応するソフトウェアを搭載することにより、演算処理装置を用いてニューラルネットワークＮＮの学習を行うことができる。そして、学習によって得られた重み係数を、信号生成部３０の受信部３４を介して演算回路１０４に供給することにより、演算回路１０４に設けられたニューラルネットワークＮＮの重み係数を更新することができる。このように、ニューラルネットワークＮＮの学習を信号生成部３０の外部で行うことにより、信号生成部３０の構成を簡易化することができる。 Note that the above-described learning of the neural network NN can be performed using an arithmetic processing device or the like provided outside the signal generation unit 30. As the arithmetic processing device, a computer having excellent arithmetic processing capability such as a dedicated server or a cloud can be used. By installing software corresponding to the neural network NN in the arithmetic processing device, the neural network NN can be learned using the arithmetic processing device. Then, the weighting coefficient obtained by learning is supplied to the arithmetic circuit 104 via the receiving unit 34 of the signal generation unit 30, whereby the weighting coefficient of the neural network NN provided in the arithmetic circuit 104 can be updated. . As described above, the learning of the neural network NN is performed outside the signal generation unit 30, whereby the configuration of the signal generation unit 30 can be simplified.
なお、ニューラルネットワークＮＮの学習に加えて推認も上記の演算処理装置を用いて行うこともできる。この場合、推認によって得られたデータＤｙを比較回路１０３に直接供給することができる。これにより、演算回路１０４を省略することができ、画像処理回路３３の構成をさらに簡易化することができる。 In addition to the learning of the neural network NN, the estimation can also be performed using the above arithmetic processing unit. In this case, the data Dy obtained by the estimation can be directly supplied to the comparison circuit 103. Thereby, the arithmetic circuit 104 can be omitted, and the configuration of the image processing circuit 33 can be further simplified.
また、ここでは輝度Ｙの決定にニューラルネットワークを用いる場合について説明したが、処理回路１０１にもニューラルネットワークを搭載することができる。この場合、ニューラルネットワークを用いた画像処理、例えば、人物、建物、風景などに応じた色調の補正、映像に表示された物体の輪郭を鮮明にする処理、解像度の低い画像データをアップコンバートする処理、ガンマ補正、データ圧縮などを行うことができる。 Although the case where a neural network is used for determining the luminance Y has been described here, the processing circuit 101 can also be equipped with a neural network. In this case, image processing using a neural network, for example, correction of color tone according to a person, building, landscape, etc., processing for sharpening the outline of an object displayed in a video, processing for up-converting low-resolution image data , Gamma correction, data compression, etc.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
（実施の形態３）
本実施の形態では、上記実施の形態で説明した表示部の他の構成例について説明する。 (Embodiment 3)
In this embodiment, another example of the structure of the display portion described in the above embodiment is described.
前述の通り、輝度Ｘがデジタル階調方式によって表現される場合、輝度の精度を上げるためには、フレーム周波数を上げる、又は、画素２５の密度を上げることが効果的である。ここでは、画素数が多く、且つ高速動作が可能な表示部２０の構成例について説明する。 As described above, when the luminance X is expressed by the digital gradation method, it is effective to increase the frame frequency or the density of the pixels 25 in order to increase the accuracy of the luminance. Here, a configuration example of the display unit 20 having a large number of pixels and capable of high speed operation will be described.
図８に、画素部２１が複数の領域に分割された表示部２０の構成例を示す。ここでは一例として、画素部２１が２つの領域Ａ、Ｂに分割された構成について説明する。領域Ａ、Ｂは、それぞれ異なる駆動回路２２、駆動回路２３と接続されている。 FIG. 8 shows a configuration example of the display unit 20 in which the pixel unit 21 is divided into a plurality of regions. Here, as an example, a configuration in which the pixel unit 21 is divided into two regions A and B will be described. The regions A and B are connected to different drive circuits 22 and 23, respectively.
配線ＧＬと配線ＳＬは互いに交差するように設けられているため、画素２５の数が増加すると交差部の数も増加する。これにより、配線ＧＬと配線ＳＬによって形成される寄生容量が増大し、映像信号の遅延が生じ得る。ここで、図８に示すように、領域Ａに映像信号を供給する駆動回路２３と、領域Ｂに映像信号を供給する駆動回路２３を独立に設けることにより、映像信号の供給を高速に行うことができる。 Since the wiring GL and the wiring SL are provided so as to intersect with each other, when the number of pixels 25 increases, the number of intersections also increases. As a result, the parasitic capacitance formed by the wiring GL and the wiring SL increases, and a delay of the video signal may occur. Here, as shown in FIG. 8, a video signal is supplied at high speed by independently providing a drive circuit 23 for supplying the video signal to the area A and a drive circuit 23 for supplying the video signal to the area B. Can do.
なお、図８において、領域Ａに含まれる画素２５と接続された配線ＧＬ、配線ＳＬをそれぞれ、配線ＧＬＡ、配線ＳＬＡと表記する。また、領域Ｂに含まれる画素２５と接続された配線ＧＬ、配線ＳＬをそれぞれ、配線ＧＬＢ、配線ＳＬＢと表記する。また、配線ＧＬＡと接続された駆動回路２２、配線ＧＬＢと接続された駆動回路２２をそれぞれ、駆動回路２２Ａ、駆動回路２２Ｂと表記する。また、配線ＳＬＡと接続された駆動回路２３、配線ＳＬＢと接続された駆動回路２３をそれぞれ、駆動回路２３Ａ、駆動回路２３Ｂと表記する。 In FIG. 8, the wiring GL and the wiring SL connected to the pixels 25 included in the region A are referred to as a wiring GLA and a wiring SLA, respectively. In addition, the wiring GL and the wiring SL connected to the pixel 25 included in the region B are denoted as a wiring GLB and a wiring SLB, respectively. In addition, the driving circuit 22 connected to the wiring GLA and the driving circuit 22 connected to the wiring GLB are referred to as a driving circuit 22A and a driving circuit 22B, respectively. In addition, the drive circuit 23 connected to the wiring SLA and the drive circuit 23 connected to the wiring SLB are referred to as a drive circuit 23A and a drive circuit 23B, respectively.
また、図８においては、１本の配線ＧＬに、２つの駆動回路２２が接続されている。具体的には、領域Ａに含まれる画素２５は、配線ＧＬＡを介して駆動回路２２Ａａ、２２Ａｂと接続されている。また、領域Ｂに含まれる画素２５は、配線ＧＬＢを介して駆動回路２２Ｂａ、２２Ｂｂと接続されている。この場合、駆動回路２２Ａａ、２２Ａｂから選択信号が出力されるタイミングが同期され、駆動回路２２Ｂａ、２２Ｂｂから選択信号が出力されるタイミングが同期される。これにより、配線ＧＬの両端から選択信号を供給することが可能となり、選択信号を高速に供給することができる。 In FIG. 8, two drive circuits 22 are connected to one wiring GL. Specifically, the pixels 25 included in the region A are connected to the drive circuits 22Aa and 22Ab via the wiring GLA. Further, the pixels 25 included in the region B are connected to the drive circuits 22Ba and 22Bb via the wiring GLB. In this case, the timings at which the selection signals are output from the drive circuits 22Aa, 22Ab are synchronized, and the timings at which the selection signals are output from the drive circuits 22Ba, 22Bb are synchronized. Accordingly, the selection signal can be supplied from both ends of the wiring GL, and the selection signal can be supplied at high speed.
さらに、表示部２０には、画素２５の列数よりも多い数の配線ＳＬを設けることもできる。図８には一例として、配線ＳＬの数が画素２５の列数の２倍である場合を示している。そして、領域Ａに含まれる画素２５は、配線ＳＬＡａ又は配線ＳＬＡｂと接続され、領域Ｂに含まれる画素２５は、配線ＳＬＢａ又は配線ＳＬＢｂと接続されている。なお、配線ＳＬＡａ又は配線ＳＬＢａと接続された画素２５を画素２５ａと表記し、配線ＳＬＡｂ又は配線ＳＬＢｂと接続された画素２５を画素２５ｂと表記する。 Furthermore, the display unit 20 can be provided with a larger number of wirings SL than the number of columns of the pixels 25. FIG. 8 shows a case where the number of wirings SL is twice the number of columns of the pixels 25 as an example. The pixels 25 included in the region A are connected to the wiring SLAa or the wiring SLAb, and the pixels 25 included in the region B are connected to the wiring SLBa or the wiring SLBb. Note that the pixel 25 connected to the wiring SLAa or the wiring SLBa is referred to as a pixel 25a, and the pixel 25 connected to the wiring SLAb or the wiring SLBb is referred to as a pixel 25b.
画素２５ａと画素２５ｂには、それぞれ異なる配線ＳＬから映像信号が供給される。そのため、隣接する画素２５ａと画素２５ｂには選択信号を同時に供給することができる。これにより、配線ＧＬの走査期間を短縮することができ、表示部２０の動作速度の向上を図ることができる。 Video signals are supplied to the pixels 25a and 25b from different wirings SL. Therefore, selection signals can be simultaneously supplied to the adjacent pixels 25a and 25b. Thereby, the scanning period of the wiring GL can be shortened, and the operation speed of the display unit 20 can be improved.
なお、選択信号が同時に供給される配線ＧＬは、共有化することができる。図８においては、隣接する画素２５ａと画素２５ｂに接続された配線ＧＬが共有化されている。これにより、配線ＧＬの本数を削減し、表示部２０の面積を縮小することができる。 Note that the wiring GL to which the selection signal is simultaneously supplied can be shared. In FIG. 8, the wiring GL connected to the adjacent pixels 25a and 25b is shared. Thereby, the number of the wirings GL can be reduced, and the area of the display unit 20 can be reduced.
また、上記では配線ＳＬの数が画素２５の列数の２倍である場合について説明したが、配線ＳＬの数は画素２５の列数の３倍以上であってもよい。この場合、選択信号が同時に供給される配線ＧＬの本数をさらに増やすことができ、表示部２０の高速化を図ることができる。 In the above description, the number of wirings SL is twice the number of columns of the pixels 25. However, the number of wirings SL may be three or more times the number of columns of the pixels 25. In this case, the number of wirings GL to which selection signals are simultaneously supplied can be further increased, and the display unit 20 can be speeded up.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
（実施の形態４）
本実施の形態では、上記実施の形態で説明した表示システムに用いることができる表示装置の構成例について説明する。 (Embodiment 4)
In this embodiment, a structure example of a display device that can be used for the display system described in the above embodiment will be described.
図９に、上記実施の形態における表示部２０に用いることができる表示装置３００の構成例を示す。表示装置３００は、発光素子を用いて映像を表示する機能を有する。 FIG. 9 shows a configuration example of a display device 300 that can be used for the display unit 20 in the above embodiment. The display device 300 has a function of displaying an image using a light emitting element.
表示装置３００は電極３０８を有しており、電極３０８はＦＰＣ３０９が有する端子と異方性導電層３１０を介して接続されている。また、電極３０８は、絶縁層３０７、絶縁層３０６、および絶縁層３０５に形成された開口を介して配線３０４と接続されている。電極３０８は、電極層３４１と同じ材料から形成されている。 The display device 300 includes an electrode 308, and the electrode 308 is connected to a terminal included in the FPC 309 through an anisotropic conductive layer 310. The electrode 308 is connected to the wiring 304 through an opening formed in the insulating layer 307, the insulating layer 306, and the insulating layer 305. The electrode 308 is formed of the same material as the electrode layer 341.
基板３０１上に設けられた画素２５は、トランジスタＴｒ２（図２（Ｂ）参照）を有している。また、トランジスタＴｒ２は、絶縁層３０２上に設けられている。また、トランジスタＴｒ２は、絶縁層３０２上に設けられた電極３３１を有し、電極３３１上に絶縁層３０３が形成されている。絶縁層３０３上に半導体層３３２が設けられている。半導体層３３２上に電極３３３及び電極３３４が設けられ、電極３３３及び電極３３４上に絶縁層３０５及び絶縁層３０６が設けられ、絶縁層３０５及び絶縁層３０６上に電極３３５が設けられている。電極３３３及び電極３３４は、配線３０４と同じ材料から形成されている。 The pixel 25 provided over the substrate 301 includes a transistor Tr2 (see FIG. 2B). The transistor Tr2 is provided over the insulating layer 302. The transistor Tr2 includes an electrode 331 provided over the insulating layer 302, and the insulating layer 303 is formed over the electrode 331. A semiconductor layer 332 is provided over the insulating layer 303. An electrode 333 and an electrode 334 are provided over the semiconductor layer 332, an insulating layer 305 and an insulating layer 306 are provided over the electrode 333 and the electrode 334, and an electrode 335 is provided over the insulating layer 305 and the insulating layer 306. The electrodes 333 and 334 are formed from the same material as the wiring 304.
トランジスタＴｒ２において、電極３３１はゲート電極としての機能を有し、電極３３３はソース電極又はドレイン電極の一方としての機能を有し、電極３３４はソース電極又はドレイン電極の他方としての機能を有し、電極３３５はバックゲート電極としての機能を有する。 In the transistor Tr2, the electrode 331 functions as a gate electrode, the electrode 333 functions as one of a source electrode or a drain electrode, the electrode 334 functions as the other of the source electrode or the drain electrode, The electrode 335 functions as a back gate electrode.
トランジスタＴｒ２はボトムゲート構造であり、かつ、バックゲートを有することで、オン電流を増大させることができる。また、トランジスタの閾値を制御することができる。なお、電極３３５は、製造工程を簡略化するため、場合によっては省略してもよい。 The transistor Tr2 has a bottom gate structure and has a back gate, whereby the on-state current can be increased. In addition, the threshold value of the transistor can be controlled. Note that the electrode 335 may be omitted in some cases in order to simplify the manufacturing process.
トランジスタに用いる半導体材料としては、例えば、第１４族の元素（シリコン、ゲルマニウム等）、又は金属酸化物を用いることができる。代表的には、シリコンを含む半導体、ガリウムヒ素を含む半導体又はインジウムを含む金属酸化物などを適用できる。 As a semiconductor material used for the transistor, for example, a Group 14 element (silicon, germanium, or the like) or a metal oxide can be used. Typically, a semiconductor containing silicon, a semiconductor containing gallium arsenide, a metal oxide containing indium, or the like can be used.
トランジスタのチャネルが形成される半導体には、例えばシリコンを用いることができる。シリコンとして、特にアモルファスシリコンを用いることが好ましい。アモルファスシリコンを用いることで、大型の基板上に歩留り良くトランジスタを形成でき、量産性に優れる。 For example, silicon can be used for the semiconductor in which the channel of the transistor is formed. As silicon, it is particularly preferable to use amorphous silicon. By using amorphous silicon, a transistor can be formed over a large substrate with high yield, and the mass productivity is excellent.
また、微結晶シリコン、多結晶シリコン、単結晶シリコンなどの結晶性を有するシリコンを用いることもできる。特に、多結晶シリコンは、単結晶シリコンに比べて低温で形成でき、且つアモルファスシリコンに比べて高い電界効果移動度と高い信頼性を備える。 Alternatively, crystalline silicon such as microcrystalline silicon, polycrystalline silicon, or single crystal silicon can be used. In particular, polycrystalline silicon can be formed at a lower temperature than single crystal silicon, and has higher field effect mobility and higher reliability than amorphous silicon.
また、トランジスタのチャネルが形成される半導体として、特にシリコンよりもバンドギャップの大きな金属酸化物を用いることもできる。シリコンよりもバンドギャップが広く、且つキャリア密度の小さい半導体材料を用いると、トランジスタのオフ状態における電流を低減できるため好ましい。 In addition, a metal oxide having a bandgap larger than that of silicon can be used as a semiconductor in which a channel of a transistor is formed. It is preferable to use a semiconductor material with a wider band gap and lower carrier density than silicon because current in an off state of the transistor can be reduced.
シリコンよりもバンドギャップの大きな金属酸化物を用いたトランジスタは、その低いオフ電流により、トランジスタと直列に接続された容量に蓄積した電荷を長期間に亘って保持することが可能である。このようなトランジスタを画素に適用することで、各表示領域に表示した画像の階調を維持しつつ、駆動回路を停止することも可能となる。その結果、極めて消費電力の低減された表示装置を実現できる。 A transistor using a metal oxide having a band gap larger than that of silicon can hold charge accumulated in a capacitor connected in series with the transistor for a long time because of the low off-state current. By applying such a transistor to a pixel, the driving circuit can be stopped while maintaining the gradation of an image displayed in each display region. As a result, a display device with extremely reduced power consumption can be realized.
金属酸化物は、例えば少なくともインジウム、亜鉛及びＭ（アルミニウム、チタン、ガリウム、ゲルマニウム、イットリウム、ジルコニウム、ランタン、セリウム、スズ、ネオジムまたはハフニウム等の金属）を含むＩｎ−Ｍ−Ｚｎ系酸化物で表記される材料を含むことが好ましい。また、該金属酸化物を用いたトランジスタの電気特性のばらつきを減らすため、それらと共に、スタビライザーを含むことが好ましい。 The metal oxide is represented by an In-M-Zn-based oxide containing at least indium, zinc, and M (metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). It is preferable to include a material to be prepared. In addition, in order to reduce variation in electric characteristics of the transistor using the metal oxide, it is preferable to include a stabilizer together with them.
スタビライザーとしては、例えば、ガリウム、スズ、ハフニウム、アルミニウム、またはジルコニウム等がある。また、他のスタビライザーとしては、ランタノイドである、ランタン、セリウム、プラセオジム、ネオジム、サマリウム、ユウロピウム、ガドリニウム、テルビウム、ジスプロシウム、ホルミウム、エルビウム、ツリウム、イッテルビウム、ルテチウム等がある。 Examples of the stabilizer include gallium, tin, hafnium, aluminum, and zirconium. Other stabilizers include lanthanoids such as lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium.
半導体層を構成する金属酸化物として、例えば、Ｉｎ−Ｇａ−Ｚｎ系酸化物、Ｉｎ−Ａｌ−Ｚｎ系酸化物、Ｉｎ−Ｓｎ−Ｚｎ系酸化物、Ｉｎ−Ｈｆ−Ｚｎ系酸化物、Ｉｎ−Ｌａ−Ｚｎ系酸化物、Ｉｎ−Ｃｅ−Ｚｎ系酸化物、Ｉｎ−Ｐｒ−Ｚｎ系酸化物、Ｉｎ−Ｎｄ−Ｚｎ系酸化物、Ｉｎ−Ｓｍ−Ｚｎ系酸化物、Ｉｎ−Ｅｕ−Ｚｎ系酸化物、Ｉｎ−Ｇｄ−Ｚｎ系酸化物、Ｉｎ−Ｔｂ−Ｚｎ系酸化物、Ｉｎ−Ｄｙ−Ｚｎ系酸化物、Ｉｎ−Ｈｏ−Ｚｎ系酸化物、Ｉｎ−Ｅｒ−Ｚｎ系酸化物、Ｉｎ−Ｔｍ−Ｚｎ系酸化物、Ｉｎ−Ｙｂ−Ｚｎ系酸化物、Ｉｎ−Ｌｕ−Ｚｎ系酸化物、Ｉｎ−Ｓｎ−Ｇａ−Ｚｎ系酸化物、Ｉｎ−Ｈｆ−Ｇａ−Ｚｎ系酸化物、Ｉｎ−Ａｌ−Ｇａ−Ｚｎ系酸化物、Ｉｎ−Ｓｎ−Ａｌ−Ｚｎ系酸化物、Ｉｎ−Ｓｎ−Ｈｆ−Ｚｎ系酸化物、Ｉｎ−Ｈｆ−Ａｌ−Ｚｎ系酸化物を用いることができる。 As a metal oxide forming the semiconductor layer, for example, an In—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide, an In—Hf—Zn-based oxide, an In— La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide In-Gd-Zn-based oxide, In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm -Zn oxide, In-Yb-Zn oxide, In-Lu-Zn oxide, In-Sn-Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al- Ga-Zn oxide, In-Sn-Al-Zn oxide, In-Sn-Hf-Zn acid Things, can be used In-Hf-Al-Zn-based oxide.
なお、ここで、Ｉｎ−Ｇａ−Ｚｎ系酸化物とは、ＩｎとＧａとＺｎを主成分として有する酸化物という意味であり、ＩｎとＧａとＺｎの比率は問わない。また、ＩｎとＧａとＺｎ以外の金属元素が入っていてもよい。 Note that here, an In—Ga—Zn-based oxide means an oxide containing In, Ga, and Zn as its main components, and there is no limitation on the ratio of In, Ga, and Zn. Moreover, metal elements other than In, Ga, and Zn may be contained.
また、半導体層と導電層は、上記酸化物のうち同一の金属元素を有していてもよい。半導体層と導電層を同一の金属元素とすることで、製造コストを低減させることができる。例えば、同一の金属組成の金属酸化物ターゲットを用いることで、製造コストを低減させることができる。また半導体層と導電層を加工する際のエッチングガスまたはエッチング液を共通して用いることができる。ただし、半導体層と導電層は、同一の金属元素を有していても、組成が異なる場合がある。例えば、トランジスタ及び容量素子の作製工程中に、膜中の金属元素が脱離し、異なる金属組成となる場合がある。 In addition, the semiconductor layer and the conductive layer may have the same metal element among the above oxides. Manufacturing costs can be reduced by using the same metal element for the semiconductor layer and the conductive layer. For example, the manufacturing cost can be reduced by using metal oxide targets having the same metal composition. Further, an etching gas or an etching solution for processing the semiconductor layer and the conductive layer can be used in common. However, the semiconductor layer and the conductive layer may have different compositions even if they have the same metal element. For example, a metal element in a film may be detached during a manufacturing process of a transistor and a capacitor to have a different metal composition.
半導体層を構成する金属酸化物は、エネルギーギャップが２ｅＶ以上、好ましくは２．５ｅＶ以上、より好ましくは３ｅＶ以上であることが好ましい。このように、エネルギーギャップの広い金属酸化物を用いることで、トランジスタのオフ電流を低減することができる。 The metal oxide constituting the semiconductor layer preferably has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of a transistor can be reduced by using a metal oxide having a wide energy gap.
半導体層を構成する金属酸化物がＩｎ−Ｍ−Ｚｎ酸化物の場合、Ｉｎ−Ｍ−Ｚｎ酸化物を成膜するために用いるスパッタリングターゲットの金属元素の原子数比は、Ｉｎ≧Ｍ、Ｚｎ≧Ｍを満たすことが好ましい。このようなスパッタリングターゲットの金属元素の原子数比として、Ｉｎ：Ｍ：Ｚｎ＝１：１：１、Ｉｎ：Ｍ：Ｚｎ＝１：１：１．２、Ｉｎ：Ｍ：Ｚｎ＝３：１：２、４：２：４．１等が好ましい。なお、成膜される半導体層の原子数比はそれぞれ、誤差として上記のスパッタリングターゲットに含まれる金属元素の原子数比のプラスマイナス４０％の変動を含む。 In the case where the metal oxide forming the semiconductor layer is an In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used for forming the In-M-Zn oxide is In ≧ M, Zn ≧ It is preferable to satisfy M. As the atomic ratio of the metal elements of such a sputtering target, In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 3: 1: 2, 4: 2: 4.1 and the like are preferable. Note that the atomic ratio of the semiconductor layer to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.
半導体層には、キャリア密度の低い金属酸化物を用いることが好ましい。例えば、半導体層は、キャリア密度が１×１０１７／ｃｍ３以下、好ましくは１×１０１５／ｃｍ３以下、さらに好ましくは１×１０１３／ｃｍ３以下、より好ましくは１×１０１１／ｃｍ３以下、さらに好ましくは１×１０１０／ｃｍ３未満であり、１×１０−９／ｃｍ３以上のキャリア密度の金属酸化物を用いることができる。このような半導体層は、不純物濃度が低く、欠陥準位密度が低いため、安定な特性を有する。 It is preferable to use a metal oxide having a low carrier density for the semiconductor layer. For example, semiconductor layer has a carrier density of 1 × 10 17 / cm 3 or less, preferably 1 × 10 15 / cm 3 or less, more preferably 1 × 10 13 / cm 3 or less, more preferably 1 × 10 11 / cm 3 or less, more preferably less than 1 × 10 10 / cm 3, it is possible to use a 1 × 10 -9 / cm 3 metal oxide or more carrier density. Such a semiconductor layer has stable characteristics because it has a low impurity concentration and a low density of defect states.
なお、これらに限られず、必要とするトランジスタの半導体特性及び電気特性（電界効果移動度、しきい値電圧等）に応じて適切な組成のものを用いればよい。また、必要とするトランジスタの半導体特性を得るために、半導体層のキャリア密度や不純物濃度、欠陥密度、金属元素と酸素の原子数比、原子間距離、密度等を適切なものとすることが好ましい。 Note that the composition is not limited thereto, and a transistor having an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, and the like) of the transistor. In addition, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the semiconductor layer have appropriate carrier density, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like. .
半導体層を構成する金属酸化物において、第１４族元素の一つであるシリコンや炭素が含まれると、半導体層において酸素欠損が増加し、ｎ型化してしまう場合がある。このため、半導体層におけるシリコンや炭素の濃度（二次イオン質量分析法により得られる濃度）を、２×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１７ａｔｏｍｓ／ｃｍ３以下とすることが好ましい。 If the metal oxide constituting the semiconductor layer contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies increase in the semiconductor layer, which may become n-type. For this reason, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 2 × 10 18 atoms / cm 3 or less, preferably 2 × 10 17 atoms / cm 3 or less. preferable.
また、アルカリ金属及びアルカリ土類金属は、金属酸化物と結合するとキャリアを生成する場合があり、トランジスタのオフ電流が増大してしまうことがある。このため半導体層における二次イオン質量分析法により得られるアルカリ金属またはアルカリ土類金属の濃度を、１×１０１８ａｔｏｍｓ／ｃｍ３以下、好ましくは２×１０１６ａｔｏｍｓ／ｃｍ３以下にすることが好ましい。 In addition, when an alkali metal and an alkaline earth metal are combined with a metal oxide, carriers may be generated, which may increase the off-state current of the transistor. Therefore, the concentration of alkali metal or alkaline earth metal obtained by secondary ion mass spectrometry in the semiconductor layer is set to 1 × 10 18 atoms / cm 3 or less, preferably 2 × 10 16 atoms / cm 3 or less. preferable.
また、金属酸化物は、例えば非単結晶構造でもよい。非単結晶構造は、例えば、多結晶構造、微結晶構造、または非晶質構造を含む。非単結晶構造において、非晶質構造は最も欠陥準位密度が高い。 The metal oxide may have a non-single crystal structure, for example. The non-single crystal structure includes, for example, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect states.
非晶質構造の金属酸化物は、例えば、原子配列が無秩序であり、結晶成分を有さない。または、非晶質構造の酸化物膜は、例えば、完全な非晶質構造であり、結晶部を有さない。 A metal oxide having an amorphous structure has, for example, disordered atomic arrangement and no crystal component. Alternatively, an amorphous oxide film has, for example, a completely amorphous structure and does not have a crystal part.
なお、金属酸化物が、非晶質構造の領域、微結晶構造の領域、多結晶構造の領域、単結晶構造の領域のうち、二種以上を有する混合膜であってもよい。混合膜は、例えば上述した領域のうち、いずれか二種以上の領域を含む単層構造、または積層構造を有する場合がある。 Note that the metal oxide may be a mixed film including two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, and a region having a single crystal structure. For example, the mixed film may have a single-layer structure or a stacked structure including any two or more of the above-described regions.
なお、上記の半導体材料は、トランジスタＴｒ２の他、図２（Ｂ）におけるトランジスタＴｒ１に用いることもできる。 Note that the above-described semiconductor material can be used for the transistor Tr1 in FIG. 2B in addition to the transistor Tr2.
また、表示装置３００は、容量素子Ｃ１を有する。容量素子Ｃ１は、電極３３４と電極３３６が絶縁層３０３を介して重なる領域を有する。電極３３６は、電極３３１と同じ材料から形成されている。 In addition, the display device 300 includes a capacitive element C1. The capacitor C1 has a region where the electrode 334 and the electrode 336 overlap with each other with the insulating layer 303 interposed therebetween. The electrode 336 is formed from the same material as the electrode 331.
図９は、表示素子としてＥＬ素子などの発光素子を用いた表示装置の一例である。ＥＬ素子は有機ＥＬ素子と無機ＥＬ素子に区別される。 FIG. 9 illustrates an example of a display device using a light-emitting element such as an EL element as a display element. EL elements are classified into organic EL elements and inorganic EL elements.
有機ＥＬ素子は、電圧を印加することにより、一方の電極から電子、他方の電極から正孔がそれぞれＥＬ層に注入される。そして、それらキャリア（電子および正孔）が再結合することにより、発光性の有機化合物が励起状態を形成し、その励起状態が基底状態に戻る際に発光する。このようなメカニズムから、このような発光素子は、電流励起型の発光素子と呼ばれる。なお、ＥＬ層は、発光性の化合物以外に、正孔注入性の高い物質、正孔輸送性の高い物質、正孔ブロック材料、電子輸送性の高い物質、電子注入性の高い物質、またはバイポーラ性の物質（電子輸送性及び正孔輸送性が高い物質）などを有していてもよい。ＥＬ層は、蒸着法（真空蒸着法を含む）、転写法、印刷法、インクジェット法、塗布法などの方法で形成することができる。 In the organic EL element, by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element. Note that in addition to the light-emitting compound, the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer. Material (a material having a high electron transporting property and a high hole transporting property) may be included. The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.
無機ＥＬ素子は、その素子構成により、分散型無機ＥＬ素子と薄膜型無機ＥＬ素子とに分類される。分散型無機ＥＬ素子は、発光材料の粒子をバインダ中に分散させた発光層を有するものであり、発光メカニズムはドナー準位とアクセプター準位を利用するドナー−アクセプター再結合型発光である。薄膜型無機ＥＬ素子は、発光層を誘電体層で挟み込み、さらにそれを電極で挟んだ構造であり、発光メカニズムは金属イオンの内殻電子遷移を利用する局在型発光である。 Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions.
図９は、発光素子ＬＥとして有機ＥＬ素子を用いた例を説明する。 FIG. 9 illustrates an example in which an organic EL element is used as the light emitting element LE.
図９において、発光素子ＬＥは、画素２５に設けられたトランジスタＴｒ２と接続されている。なお発光素子ＬＥは、電極層３４１、発光層３４２、電極層３４３の積層によって構成されているが、この構成に限定されない。発光素子ＬＥから取り出す光の方向などに合わせて、発光素子ＬＥの構成は適宜変えることができる。 In FIG. 9, the light emitting element LE is connected to a transistor Tr <b> 2 provided in the pixel 25. Note that the light-emitting element LE includes a stacked layer of an electrode layer 341, a light-emitting layer 342, and an electrode layer 343, but is not limited to this configuration. The configuration of the light emitting element LE can be changed as appropriate in accordance with the direction of light extracted from the light emitting element LE.
隔壁３４４は、有機絶縁材料、又は無機絶縁材料を用いて形成する。特に感光性の樹脂材料を用い、電極層３４１上に開口部を形成し、その開口部の側面が連続した曲率を持って形成される傾斜面となるように形成することが好ましい。 The partition 344 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material and form an opening on the electrode layer 341 so that the side surface of the opening is an inclined surface formed with a continuous curvature.
発光層３４２は、単数の層で構成されていても、複数の層が積層されるように構成されていてもどちらでも良い。 The light emitting layer 342 may be composed of a single layer or a plurality of layers stacked.
発光素子ＬＥに酸素、水素、水分、二酸化炭素等が侵入しないように、電極層３４３および隔壁３４４上に保護層を形成してもよい。保護層としては、窒化シリコン、窒化酸化シリコン、酸化アルミニウム、窒化アルミニウム、酸化窒化アルミニウム、窒化酸化アルミニウム、ＤＬＣ（Ｄｉａｍｏｎｄ　Ｌｉｋｅ　Ｃａｒｂｏｎ）などを形成することができる。また、基板３０１、基板３１２、及びシール材３１１によって封止された空間には充填材３４５が設けられ密封されている。このように、外気に曝されないように気密性が高く、脱ガスの少ない保護フィルム（貼り合わせフィルム、紫外線硬化樹脂フィルム等）やカバー材でパッケージング（封入）することが好ましい。 A protective layer may be formed over the electrode layer 343 and the partition 344 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element LE. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. A space sealed with the substrate 301, the substrate 312, and the sealant 311 is provided with a filler 345 and sealed. As described above, it is preferable to package (enclose) the protective film with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.
充填材３４５としては窒素やアルゴンなどの不活性な気体の他に、紫外線硬化樹脂または熱硬化樹脂を用いることができ、ＰＶＣ（ポリビニルクロライド）、アクリル樹脂、ポリイミド、エポキシ樹脂、シリコーン樹脂、ＰＶＢ（ポリビニルブチラル）またはＥＶＡ（エチレンビニルアセテート）などを用いることができる。また、充填材３４５に乾燥剤が含まれていてもよい。 As the filler 345, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, the filler 345 may contain a desiccant.
シール材３１１には、ガラスフリットなどのガラス材料や、二液混合型の樹脂などの常温で硬化する硬化樹脂、光硬化性の樹脂、熱硬化性の樹脂などの樹脂材料を用いることができる。また、シール材３１１に乾燥剤が含まれていてもよい。 As the sealant 311, a glass material such as glass frit, or a resin material such as a curable resin that cures at room temperature, such as a two-component mixed resin, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 311 may contain a desiccant.
また、必要であれば、発光素子の射出面に偏光板、又は円偏光板（楕円偏光板を含む）、位相差板（λ／４板、λ／２板）、カラーフィルタなどの光学フィルムを適宜設けてもよい。また、偏光板又は円偏光板に反射防止膜を設けてもよい。例えば、表面の凹凸により反射光を拡散し、映り込みを低減できるアンチグレア処理を施すことができる。 If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.
また、発光素子をマイクロキャビティ構造とすることで、色純度の高い光を取り出すことができる。また、マイクロキャビティ構造とカラーフィルタを組み合わせることで、映り込みが低減し、表示画像の視認性を高めることができる。 In addition, when the light-emitting element has a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.
電極層３４１、電極層３４３は、酸化タングステンを含むインジウム酸化物、酸化タングステンを含むインジウム亜鉛酸化物、酸化チタンを含むインジウム酸化物、インジウム錫酸化物、酸化チタンを含むインジウム錫酸化物、インジウム亜鉛酸化物、酸化ケイ素を添加したインジウム錫酸化物などの透光性を有する導電性材料を用いることができる。 The electrode layer 341 and the electrode layer 343 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, and indium zinc. A light-transmitting conductive material such as an oxide or indium tin oxide to which silicon oxide is added can be used.
また、電極層３４１、電極層３４３はタングステン（Ｗ）、モリブデン（Ｍｏ）、ジルコニウム（Ｚｒ）、ハフニウム（Ｈｆ）、バナジウム（Ｖ）、ニオブ（Ｎｂ）、タンタル（Ｔａ）、クロム（Ｃｒ）、コバルト（Ｃｏ）、ニッケル（Ｎｉ）、チタン（Ｔｉ）、白金（Ｐｔ）、アルミニウム（Ａｌ）、銅（Ｃｕ）、銀（Ａｇ）などの金属、またはその合金、もしくはその金属窒化物から一種以上を用いて形成することができる。 The electrode layer 341 and the electrode layer 343 include tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), One or more metals such as cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), alloys thereof, or metal nitrides thereof Can be used.
また、電極層３４１、電極層３４３として、導電性高分子（導電性ポリマーともいう）を含む導電性組成物を用いて形成することができる。導電性高分子としては、いわゆるπ電子共役系導電性高分子を用いることができる。例えば、ポリアニリンまたはその誘導体、ポリピロールまたはその誘導体、ポリチオフェンまたはその誘導体、もしくは、アニリン、ピロールおよびチオフェンの２種以上からなる共重合体またはその誘導体等が挙げられる。 Alternatively, the electrode layer 341 and the electrode layer 343 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.
発光素子ＬＥが光を外部に取り出すため、少なくとも電極層３４１または電極層３４３の一方が透明であればよい。表示装置は、光の取り出し方によって、上面射出（トップエミッション）構造と、下面射出（ボトムエミッション）構造と、両面射出（デュアルエミッション）構造に分類される。上面射出構造は、基板３１２側から光を取り出す場合をいう。下面射出構造は、基板３０１側から光を取り出す場合をいう。両面射出構造は、基板３１２側と基板３０１側の両方から光を取り出す場合をいう。例えば、上面射出構造の場合、電極層３４３を透明にすればよい。例えば、下面射出構造の場合、電極層３４１を透明にすればよい。例えば、両面射出構造の場合、電極層３４１及び電極層３４３を透明にすればよい。 In order for the light emitting element LE to extract light to the outside, at least one of the electrode layer 341 and the electrode layer 343 may be transparent. Display devices are classified into a top emission (top emission) structure, a bottom emission (bottom emission) structure, and a double emission (dual emission) structure depending on how light is extracted. The top emission structure refers to a case where light is extracted from the substrate 312 side. The bottom emission structure refers to a case where light is extracted from the substrate 301 side. The dual emission structure refers to a case where light is extracted from both the substrate 312 side and the substrate 301 side. For example, in the case of a top emission structure, the electrode layer 343 may be transparent. For example, in the case of a bottom emission structure, the electrode layer 341 may be transparent. For example, in the case of a dual emission structure, the electrode layer 341 and the electrode layer 343 may be transparent.
図１０は、図９に示すトランジスタＴｒ２として、トップゲート型のトランジスタを設けた場合の断面図を示している。図１０のトランジスタＴｒ２において、電極３３１はゲート電極としての機能を有し、電極３３３はソース電極またはドレイン電極の一方としての機能を有し、電極３３４はソース電極またはドレイン電極の他方としての機能を有する。 FIG. 10 is a cross-sectional view in the case where a top-gate transistor is provided as the transistor Tr2 illustrated in FIG. In the transistor Tr2 in FIG. 10, the electrode 331 functions as a gate electrode, the electrode 333 functions as one of a source electrode and a drain electrode, and the electrode 334 functions as the other of the source electrode and the drain electrode. Have.
図１０のその他の構成要素の詳細については、図９の記載を参照すればよい。 For the details of the other components in FIG. 10, the description in FIG. 9 may be referred to.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
（実施の形態５）
本実施の形態では、上記実施の形態で説明したトランジスタに用いることができる、金属酸化物について説明する。以下では特に、金属酸化物とＣＡＣ（Ｃｌｏｕｄ−Ａｌｉｇｎｅｄ　Ｃｏｍｐｏｓｉｔｅ）の詳細について説明する。 (Embodiment 5)
In this embodiment, a metal oxide that can be used for the transistor described in the above embodiment is described. In particular, details of the metal oxide and CAC (Cloud-Aligned Composite) will be described below.
ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、材料の一部では導電性の機能と、材料の一部では絶縁性の機能とを有し、材料の全体では半導体としての機能を有する。なお、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅを、トランジスタのチャネル形成領域に用いる場合、導電性の機能は、キャリアとなる電子（またはホール）を流す機能であり、絶縁性の機能は、キャリアとなる電子を流さない機能である。導電性の機能と、絶縁性の機能とを、それぞれ相補的に作用させることで、スイッチングさせる機能（Ｏｎ／Ｏｆｆさせる機能）をＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅに付与することができる。ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、それぞれの機能を分離させることで、双方の機能を最大限に高めることができる。 The CAC-OS or the CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a function as a semiconductor in the whole material. Note that in the case where a CAC-OS or a CAC-metal oxide is used for a channel formation region of a transistor, the conductive function is a function of flowing electrons (or holes) serving as carriers, and the insulating function is a carrier. This function prevents electrons from flowing. A function of switching (a function of turning on / off) can be imparted to CAC-OS or CAC-metal oxide by causing the conductive function and the insulating function to act complementarily. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be maximized.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、導電性領域、及び絶縁性領域を有する。導電性領域は、上述の導電性の機能を有し、絶縁性領域は、上述の絶縁性の機能を有する。また、材料中において、導電性領域と、絶縁性領域とは、ナノ粒子レベルで分離している場合がある。また、導電性領域と、絶縁性領域とは、それぞれ材料中に偏在する場合がある。また、導電性領域は、周辺がぼけてクラウド状に連結して観察される場合がある。 In addition, the CAC-OS or the CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. In the material, the conductive region and the insulating region may be separated at the nanoparticle level. In addition, the conductive region and the insulating region may be unevenly distributed in the material, respectively. In addition, the conductive region may be observed with the periphery blurred and connected in a cloud shape.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅにおいて、導電性領域と、絶縁性領域とは、それぞれ０．５ｎｍ以上１０ｎｍ以下、好ましくは０．５ｎｍ以上３ｎｍ以下のサイズで材料中に分散している場合がある。 In CAC-OS or CAC-metal oxide, the conductive region and the insulating region are dispersed in the material with a size of 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm, respectively. There is.
また、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、異なるバンドギャップを有する成分により構成される。例えば、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、絶縁性領域に起因するワイドギャップを有する成分と、導電性領域に起因するナローギャップを有する成分と、により構成される。当該構成の場合、キャリアを流す際に、ナローギャップを有する成分において、主にキャリアが流れる。また、ナローギャップを有する成分が、ワイドギャップを有する成分に相補的に作用し、ナローギャップを有する成分に連動してワイドギャップを有する成分にもキャリアが流れる。このため、上記ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅをトランジスタのチャネル形成領域に用いる場合、トランジスタのオン状態において高い電流駆動力、つまり大きなオン電流、及び高い電界効果移動度を得ることができる。 Further, CAC-OS or CAC-metal oxide is composed of components having different band gaps. For example, CAC-OS or CAC-metal oxide includes a component having a wide gap caused by an insulating region and a component having a narrow gap caused by a conductive region. In the case of the configuration, when the carrier flows, the carrier mainly flows in the component having the narrow gap. In addition, the component having a narrow gap acts in a complementary manner to the component having a wide gap, and the carrier flows through the component having the wide gap in conjunction with the component having the narrow gap. Therefore, when the CAC-OS or the CAC-metal oxide is used for a channel formation region of a transistor, high current driving force, that is, high on-state current and high field-effect mobility can be obtained in the on-state of the transistor.
すなわち、ＣＡＣ−ＯＳまたはＣＡＣ−ｍｅｔａｌ　ｏｘｉｄｅは、マトリックス複合材（ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）、または金属マトリックス複合材（ｍｅｔａｌ　ｍａｔｒｉｘ　ｃｏｍｐｏｓｉｔｅ）と呼称することもできる。 That is, CAC-OS or CAC-metal oxide can also be called a matrix composite material (metal matrix composite) or a metal matrix composite material (metal matrix composite).
ＣＡＣ−ＯＳは、例えば、金属酸化物を構成する元素が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、またはその近傍のサイズで偏在した材料の一構成である。なお、以下では、金属酸化物において、一つあるいはそれ以上の金属元素が偏在し、該金属元素を有する領域が、０．５ｎｍ以上１０ｎｍ以下、好ましくは、１ｎｍ以上２ｎｍ以下、またはその近傍のサイズで混合した状態をモザイク状、またはパッチ状ともいう。 The CAC-OS is one structure of a material in which elements forming a metal oxide are unevenly distributed with a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. In the following, in the metal oxide, one or more metal elements are unevenly distributed, and the region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or the vicinity thereof. The state mixed with is also referred to as a mosaic or patch.
なお、金属酸化物は、少なくともインジウムを含むことが好ましい。特にインジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。 Note that the metal oxide preferably contains at least indium. In particular, it is preferable to contain indium and zinc. In addition, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. One kind selected from the above or a plurality of kinds may be included.
例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳ（ＣＡＣ−ＯＳの中でもＩｎ−Ｇａ−Ｚｎ酸化物を、特にＣＡＣ−ＩＧＺＯと呼称してもよい。）とは、インジウム酸化物（以下、ＩｎＯＸ１（Ｘ１は０よりも大きい実数）とする。）、またはインジウム亜鉛酸化物（以下、ＩｎＸ２ＺｎＹ２ＯＺ２（Ｘ２、Ｙ２、およびＺ２は０よりも大きい実数）とする。）と、ガリウム酸化物（以下、ＧａＯＸ３（Ｘ３は０よりも大きい実数）とする。）、またはガリウム亜鉛酸化物（以下、ＧａＸ４ＺｎＹ４ＯＺ４（Ｘ４、Ｙ４、およびＺ４は０よりも大きい実数）とする。）などと、に材料が分離することでモザイク状となり、モザイク状のＩｎＯＸ１、またはＩｎＸ２ＺｎＹ２ＯＺ２が、膜中に均一に分布した構成（以下、クラウド状ともいう。）である。 For example, a CAC-OS in In-Ga-Zn oxide (In-Ga-Zn oxide among CAC-OSs may be referred to as CAC-IGZO in particular) is an indium oxide (hereinafter referred to as InO). X1 (X1 is greater real than 0) and.), or indium zinc oxide (hereinafter, in X2 Zn Y2 O Z2 ( X2, Y2, and Z2 is larger real than 0) and a.), gallium An oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0)) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (where X4, Y4, and Z4 are greater than 0)) to.) and the like, the material becomes mosaic by separate into, mosaic InO X1 or in X2 Zn Y2 O Z2, is a configuration in which uniformly distributed in the film (hereinafter Also referred to as a cloud-like.) A.
つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とが、混合している構成を有する複合金属酸化物である。なお、本明細書において、例えば、第１の領域の元素Ｍに対するＩｎの原子数比が、第２の領域の元素Ｍに対するＩｎの原子数比よりも大きいことを、第１の領域は、第２の領域と比較して、Ｉｎの濃度が高いとする。 That, CAC-OS includes a region GaO X3 is the main component, and In X2 Zn Y2 O Z2, or InO X1 is the main component region is a composite metal oxide having a structure that is mixed. Note that in this specification, for example, the first region indicates that the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region. It is assumed that the concentration of In is higher than that in the second region.
なお、ＩＧＺＯは通称であり、Ｉｎ、Ｇａ、Ｚｎ、およびＯによる１つの化合物をいう場合がある。代表例として、ＩｎＧａＯ３（ＺｎＯ）ｍ１（ｍ１は１以上の自然数）、またはＩｎ（１＋ｘ０）Ｇａ（１−ｘ０）Ｏ３（ＺｎＯ）ｍ０（−１≦ｘ０≦１、ｍ０は０よりも大きい任意数）で表される結晶性の化合物が挙げられる。 Note that IGZO is a common name and may refer to one compound of In, Ga, Zn, and O. As a typical example, InGaO 3 (ZnO) m1 (m1 is a natural number of 1 or more), or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (−1 ≦ x0 ≦ 1, m0 is larger than 0. A crystalline compound represented by any number).
上記結晶性の化合物は、単結晶構造、多結晶構造、またはＣＡＡＣ（ｃ−ａｘｉｓ　ａｌｉｇｎｅｄ　ｃｒｙｓｔａｌ）構造を有する。なお、ＣＡＡＣ構造とは、複数のＩＧＺＯのナノ結晶がｃ軸配向を有し、かつａ−ｂ面においては配向せずに連結した結晶構造である。 The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC (c-axis aligned crystal) structure. The CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have c-axis orientation and are connected without being oriented in the ab plane.
一方、ＣＡＣ−ＯＳは、金属酸化物の材料構成に関する。ＣＡＣ−ＯＳとは、Ｉｎ、Ｇａ、Ｚｎ、およびＯを含む材料構成において、一部にＧａを主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。従って、ＣＡＣ−ＯＳにおいて、結晶構造は副次的な要素である。 On the other hand, CAC-OS relates to a material structure of a metal oxide. CAC-OS refers to a region observed in the form of nanoparticles mainly composed of Ga in a material structure including In, Ga, Zn and O, and nanoparticles mainly composed of In. The region observed in a shape is a configuration in which the regions are randomly dispersed in a mosaic shape. Therefore, in the CAC-OS, the crystal structure is a secondary element.
なお、ＣＡＣ−ＯＳは、組成の異なる二種類以上の膜の積層構造は含まないものとする。例えば、Ｉｎを主成分とする膜と、Ｇａを主成分とする膜との２層からなる構造は、含まない。 Note that the CAC-OS does not include a stacked structure of two or more kinds of films having different compositions. For example, a structure composed of two layers of a film mainly containing In and a film mainly containing Ga is not included.
なお、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とは、明確な境界が観察できない場合がある。 Incidentally, a region GaO X3 is the main component, and In X2 Zn Y2 O Z2 or InO X1 is the main component region, in some cases clear boundary can not be observed.
なお、ガリウムの代わりに、アルミニウム、イットリウム、銅、バナジウム、ベリリウム、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれている場合、ＣＡＣ−ＯＳは、一部に該金属元素を主成分とするナノ粒子状に観察される領域と、一部にＩｎを主成分とするナノ粒子状に観察される領域とが、それぞれモザイク状にランダムに分散している構成をいう。 Instead of gallium, selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. In the case where one or a plurality of types are included, the CAC-OS includes a region that is observed in a part of a nanoparticle mainly including the metal element and a nanoparticle mainly including In. The region observed in the form of particles refers to a configuration in which each region is randomly dispersed in a mosaic shape.
ＣＡＣ−ＯＳは、例えば基板を加熱しない条件で、スパッタリング法により形成することができる。また、ＣＡＣ−ＯＳをスパッタリング法で形成する場合、成膜ガスとして、不活性ガス（代表的にはアルゴン）、酸素ガス、及び窒素ガスの中から選ばれたいずれか一つまたは複数を用いればよい。また、成膜時の成膜ガスの総流量に対する酸素ガスの流量比は低いほど好ましく、例えば酸素ガスの流量比を０％以上３０％未満、好ましくは０％以上１０％以下とすることが好ましい。 The CAC-OS can be formed by a sputtering method, for example, without heating the substrate. In the case where a CAC-OS is formed by a sputtering method, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. Good. Further, the flow rate ratio of the oxygen gas to the total flow rate of the deposition gas during film formation is preferably as low as possible. .
ＣＡＣ−ＯＳは、Ｘ線回折（ＸＲＤ：Ｘ−ｒａｙ　ｄｉｆｆｒａｃｔｉｏｎ）測定法のひとつであるＯｕｔ−ｏｆ−ｐｌａｎｅ法によるθ／２θスキャンを用いて測定したときに、明確なピークが観察されないという特徴を有する。すなわち、Ｘ線回折から、測定領域のａ−ｂ面方向、およびｃ軸方向の配向は見られないことが分かる。 The CAC-OS has a feature that a clear peak is not observed when measurement is performed using a θ / 2θ scan by an out-of-plane method, which is one of X-ray diffraction (XRD) measurement methods. Have. That is, it can be seen from X-ray diffraction that no orientation in the ab plane direction and c-axis direction of the measurement region is observed.
またＣＡＣ−ＯＳは、プローブ径が１ｎｍの電子線（ナノビーム電子線ともいう。）を照射することで得られる電子線回折パターンにおいて、リング状に輝度の高い領域と、該リング領域に複数の輝点が観測される。従って、電子線回折パターンから、ＣＡＣ−ＯＳの結晶構造が、平面方向、および断面方向において、配向性を有さないｎｃ（ｎａｎｏ−ｃｒｙｓｔａｌ）構造を有することがわかる。 In addition, in the CAC-OS, an electron diffraction pattern obtained by irradiating an electron beam with a probe diameter of 1 nm (also referred to as a nanobeam electron beam) has a ring-like region having a high luminance and a plurality of bright regions in the ring region. A point is observed. Therefore, it can be seen from the electron beam diffraction pattern that the crystal structure of the CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
また例えば、Ｉｎ−Ｇａ−Ｚｎ酸化物におけるＣＡＣ−ＯＳでは、エネルギー分散型Ｘ線分光法（ＥＤＸ：Ｅｎｅｒｇｙ　Ｄｉｓｐｅｒｓｉｖｅ　Ｘ−ｒａｙ　ｓｐｅｃｔｒｏｓｃｏｐｙ）を用いて取得したＥＤＸマッピングにより、ＧａＯＸ３が主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域とが、偏在し、混合している構造を有することが確認できる。 Further, for example, in a CAC-OS in an In—Ga—Zn oxide, a region in which GaO X3 is a main component is obtained by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component is unevenly distributed and mixed.
ＣＡＣ−ＯＳは、金属元素が均一に分布したＩＧＺＯ化合物とは異なる構造であり、ＩＧＺＯ化合物と異なる性質を有する。つまり、ＣＡＣ−ＯＳは、ＧａＯＸ３などが主成分である領域と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域と、に互いに相分離し、各元素を主成分とする領域がモザイク状である構造を有する。 CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has a property different from that of an IGZO compound. That is, in the CAC-OS, a region in which GaO X3 or the like is a main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is a main component are phase-separated from each other, and a region in which each element is a main component. Has a mosaic structure.
ここで、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域は、ＧａＯＸ３などが主成分である領域と比較して、導電性が高い領域である。つまり、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域を、キャリアが流れることにより、酸化物半導体としての導電性が発現する。従って、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域が、酸化物半導体中にクラウド状に分布することで、高い電界効果移動度（μ）が実現できる。 Here, the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component is a region having higher conductivity than a region containing GaO X3 or the like as a main component. That, In X2 Zn Y2 O Z2 or InO X1, is an area which is the main component, by carriers flow, expressed the conductivity of the oxide semiconductor. Accordingly, a region where In X2 Zn Y2 O Z2 or InO X1 is a main component is distributed in a cloud shape in the oxide semiconductor, whereby high field-effect mobility (μ) can be realized.
一方、ＧａＯＸ３などが主成分である領域は、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１が主成分である領域と比較して、絶縁性が高い領域である。つまり、ＧａＯＸ３などが主成分である領域が、酸化物半導体中に分布することで、リーク電流を抑制し、良好なスイッチング動作を実現できる。 On the other hand, areas such as GaO X3 is the main component, as compared to the In X2 Zn Y2 O Z2 or InO X1 is the main component area, it is highly regions insulating. That is, a region containing GaO X3 or the like as a main component is distributed in the oxide semiconductor, whereby leakage current can be suppressed and good switching operation can be realized.
従って、ＣＡＣ−ＯＳを半導体素子に用いた場合、ＧａＯＸ３などに起因する絶縁性と、ＩｎＸ２ＺｎＹ２ＯＺ２、またはＩｎＯＸ１に起因する導電性とが、相補的に作用することにより、高いオン電流（Ｉｏｎ）、および高い電界効果移動度（μ）を実現することができる。 Therefore, when CAC-OS is used for a semiconductor element, the insulating property caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high An on-current (I on ) and high field effect mobility (μ) can be realized.
また、ＣＡＣ−ＯＳを用いた半導体素子は、信頼性が高い。従って、ＣＡＣ−ＯＳは、さまざまな半導体装置に最適である。 In addition, a semiconductor element using a CAC-OS has high reliability. Therefore, the CAC-OS is optimal for various semiconductor devices.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
（実施の形態６）
本実施の形態では、本発明の一態様の電子機器について、図面を参照して説明する。 (Embodiment 6)
In this embodiment, electronic devices of one embodiment of the present invention are described with reference to drawings.
以下で例示する電子機器には、上記実施の形態で説明した表示システムを搭載することができる。これにより、高品質な映像を表示可能な電子機器を提供することができる。 The display system described in the above embodiment can be mounted on the electronic devices exemplified below. Thereby, an electronic device capable of displaying a high-quality video can be provided.
本発明の一態様の電子機器の表示部には、例えばフルハイビジョン、２Ｋ、４Ｋ、８Ｋ、１６Ｋ、またはそれ以上の解像度を有する映像を表示させることができる。また、表示部の画面サイズとしては、対角２０インチ以上、または対角３０インチ以上、または対角５０インチ以上、対角６０インチ以上、または対角７０インチ以上とすることもできる。 The display portion of the electronic device of one embodiment of the present invention can display an image having a resolution of, for example, full high vision, 2K, 4K, 8K, 16K, or higher. In addition, the screen size of the display unit may be 20 inches or more diagonal, 30 inches or more diagonal, 50 inches diagonal, 60 inches diagonal, or 70 inches diagonal.
電子機器としては、例えば、テレビジョン装置、デスクトップ型もしくはノート型のパーソナルコンピュータ、コンピュータ用などのモニタ、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）、パチンコ機などの大型ゲーム機などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。 Examples of electronic devices include relatively large screens such as television devices, desktop or notebook personal computers, monitors for computers, digital signage (digital signage), and large game machines such as pachinko machines. In addition to the electronic devices provided, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproduction device, and the like can be given.
本発明の一態様の電子機器は、家屋もしくはビルの内壁もしくは外壁、または、自動車の内装もしくは外装の曲面に沿って組み込むことができる。 The electronic device of one embodiment of the present invention can be incorporated along an inner wall or an outer wall of a house or a building, or a curved surface of an interior or exterior of an automobile.
本発明の一態様の電子機器は、アンテナを有していてもよい。アンテナで信号を受信することで、表示部で映像や情報等の表示を行うことができる。また、電子機器がアンテナ及び二次電池を有する場合、アンテナを、非接触電力伝送に用いてもよい。 The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with an antenna, video, information, and the like can be displayed on the display unit. In the case where the electronic device has an antenna and a secondary battery, the antenna may be used for non-contact power transmission.
本発明の一態様の電子機器は、センサ（力、変位、位置、速度、加速度、角速度、回転数、距離、光、液、磁気、温度、化学物質、音声、時間、硬度、電場、電流、電圧、電力、放射線、流量、湿度、傾度、振動、においまたは赤外線を測定する機能を含むもの）を有していてもよい。 The electronic device of one embodiment of the present invention includes a sensor (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, It may have a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared).
本発明の一態様の電子機器は、様々な機能を有することができる。例えば、様々な情報（静止画、動画、テキスト画像など）を表示部に表示する機能、タッチパネル機能、カレンダー、日付または時刻などを表示する機能、様々なソフトウェア（プログラム）を実行する機能、無線通信機能、記録媒体に記録されているプログラムまたはデータを読み出す機能等を有することができる。 The electronic device of one embodiment of the present invention can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for executing various software (programs), and wireless communication A function, a function of reading a program or data recorded on a recording medium, and the like can be provided.
図１１（Ａ）にテレビジョン装置の一例を示す。テレビジョン装置７１００は、筐体７１０１に表示部７０００が組み込まれている。ここでは、スタンド７１０３により筐体７１０１を支持した構成を示している。 FIG. 11A illustrates an example of a television device. In the television device 7100, a display portion 7000 is incorporated in a housing 7101. Here, a structure in which the housing 7101 is supported by a stand 7103 is shown.
表示部７０００に、本発明の一態様の表示装置を適用することができる。 The display device of one embodiment of the present invention can be applied to the display portion 7000.
図１１（Ａ）に示すテレビジョン装置７１００の操作は、筐体７１０１が備える操作スイッチや、別体のリモコン操作機７１１１により行うことができる。または、表示部７０００にタッチセンサを備えていてもよく、指等で表示部７０００に触れることでテレビジョン装置７１００を操作してもよい。リモコン操作機７１１１は、当該リモコン操作機７１１１から出力する情報を表示する表示部を有していてもよい。リモコン操作機７１１１が備える操作キーまたはタッチパネルにより、チャンネル及び音量の操作を行うことができ、表示部７０００に表示される映像を操作することができる。 Operation of the television device 7100 illustrated in FIG. 11A can be performed with an operation switch included in the housing 7101 or a separate remote controller 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote controller 7111 may include a display unit that displays information output from the remote controller 7111. Channels and volume can be operated with an operation key or a touch panel included in the remote controller 7111, and an image displayed on the display portion 7000 can be operated.
なお、テレビジョン装置７１００は、受信機及びモデムなどを備えた構成とする。受信機により一般のテレビ放送の受信を行うことができる。また、モデムを介して有線または無線による通信ネットワークに接続することにより、一方向（送信者から受信者）または双方向（送信者と受信者間、あるいは受信者間同士など）の情報通信を行うことも可能である。 Note that the television device 7100 is provided with a receiver, a modem, and the like. A general television broadcast can be received by the receiver. In addition, by connecting to a wired or wireless communication network via a modem, information communication is performed in one direction (from the sender to the receiver) or in two directions (between the sender and the receiver or between the receivers). It is also possible.
図１１（Ｂ）に、ノート型パーソナルコンピュータ７２００を示す。ノート型パーソナルコンピュータ７２００は、筐体７２１１、キーボード７２１２、ポインティングデバイス７２１３、外部接続ポート７２１４等を有する。筐体７２１１に、表示部７０００が組み込まれている。 FIG. 11B illustrates a laptop personal computer 7200. A laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.
表示部７０００に、本発明の一態様の半導体装置を適用することができる。 The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000.
図１１（Ｃ）、（Ｄ）に、デジタルサイネージ（Ｄｉｇｉｔａｌ　Ｓｉｇｎａｇｅ：電子看板）の一例を示す。 FIGS. 11C and 11D show examples of digital signage (digital signage).
図１１（Ｃ）に示すデジタルサイネージ７３００は、筐体７３０１、表示部７０００、及びスピーカ７３０３等を有する。さらに、ＬＥＤランプ、操作キー（電源スイッチ、または操作スイッチを含む）、接続端子、各種センサ、マイクロフォン等を有することができる。 A digital signage 7300 illustrated in FIG. 11C includes a housing 7301, a display portion 7000, a speaker 7303, and the like. Furthermore, an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like can be provided.
また、図１１（Ｄ）は円柱状の柱７４０１に取り付けられたデジタルサイネージ７４００である。デジタルサイネージ７４００は、柱７４０１の曲面に沿って設けられた表示部７０００を有する。 FIG. 11D illustrates a digital signage 7400 attached to a columnar column 7401. The digital signage 7400 includes a display portion 7000 provided along the curved surface of the column 7401.
図１１（Ｃ）、（Ｄ）において、表示部７０００に、本発明の一態様の表示装置を適用することができる。 11C and 11D, the display device of one embodiment of the present invention can be applied to the display portion 7000.
表示部７０００が広いほど、一度に提供できる情報量を増やすことができる。また、表示部７０００が広いほど、人の目につきやすく、例えば、広告の宣伝効果を高めることができる。 The wider the display unit 7000, the more information can be provided at one time. In addition, the wider the display unit 7000, the more easily noticeable to the human eye. For example, the advertising effect can be enhanced.
表示部７０００にタッチパネルを適用することで、表示部７０００に画像または動画を表示するだけでなく、使用者が直感的に操作することができ、好ましい。また、路線情報もしくは交通情報などの情報を提供するための用途に用いる場合には、直感的な操作によりユーザビリティを高めることができる。 By applying a touch panel to the display unit 7000, not only an image or a moving image is displayed on the display unit 7000, but also a user can operate intuitively, which is preferable. In addition, when it is used for providing information such as route information or traffic information, usability can be improved by an intuitive operation.
また、図１１（Ｃ）、（Ｄ）に示すように、デジタルサイネージ７３００またはデジタルサイネージ７４００は、ユーザーが所持するスマートフォン等の情報端末機７３１１または情報端末機７４１１と無線通信により連携可能であることが好ましい。例えば、表示部７０００に表示される広告の情報を、情報端末機７３１１または情報端末機７４１１の画面に表示させることができる。また、情報端末機７３１１または情報端末機７４１１を操作することで、表示部７０００の表示を切り替えることができる。 In addition, as illustrated in FIGS. 11C and 11D, the digital signage 7300 or the digital signage 7400 can be linked to the information terminal 7311 or the information terminal 7411 such as a smartphone possessed by the user by wireless communication. Is preferred. For example, advertisement information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Further, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
また、デジタルサイネージ７３００またはデジタルサイネージ７４００に、情報端末機７３１１または情報端末機７４１１の画面を操作手段（コントローラ）としたゲームを実行させることもできる。これにより、不特定多数のユーザーが同時にゲームに参加し、楽しむことができる。 Further, the digital signage 7300 or the digital signage 7400 can execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). As a result, an unspecified number of users can participate and enjoy the game at the same time.
本実施の形態は、他の実施の形態の記載と適宜組み合わせることができる。 This embodiment can be combined with any of the other embodiments as appropriate.
１０　　表示システム
２０　　表示部
２１　　画素部
２２　　駆動回路
２３　　駆動回路
２４　　タイミングコントローラ
２５　　画素
３０　　信号生成部
３１　　フロントエンド部
３２　　デコーダ
３３　　画像処理回路
３４　　受信部
３５　　インターフェース
３６　　制御部
４０　　送信部
１０１　　処理回路
１０２　　乱数生成回路
１０３　　比較回路
１０４　　演算回路
３００　　表示装置
３０１　　基板
３０２　　絶縁層
３０３　　絶縁層
３０４　　配線
３０５　　絶縁層
３０６　　絶縁層
３０７　　絶縁層
３０８　　電極
３０９　　ＦＰＣ
３１０　　異方性導電層
３１１　　シール材
３１２　　基板
３３１　　電極
３３２　　半導体層
３３３　　電極
３３４　　電極
３３５　　電極
３３６　　電極
３４１　　電極層
３４２　　発光層
３４３　　電極層
３４４　　隔壁
３４５　　充填材
７０００　　表示部
７１００　　テレビジョン装置
７１０１　　筐体
７１０３　　スタンド
７１１１　　リモコン操作機
７２００　　ノート型パーソナルコンピュータ
７２１１　　筐体
７２１２　　キーボード
７２１３　　ポインティングデバイス
７２１４　　外部接続ポート
７３００　　デジタルサイネージ
７３０１　　筐体
７３０３　　スピーカ
７３１１　　情報端末機
７４００　　デジタルサイネージ
７４０１　　柱
７４１１　　情報端末機 DESCRIPTION OF SYMBOLS 10 Display system 20 Display part 21 Pixel part 22 Drive circuit 23 Drive circuit 24 Timing controller 25 Pixel 30 Signal generation part 31 Front end part 32 Decoder 33 Image processing circuit 34 Reception part 35 Interface 36 Control part 40 Transmission part 101 Processing circuit 102 Random number Generator circuit 103 Comparison circuit 104 Arithmetic circuit 300 Display device 301 Substrate 302 Insulating layer 303 Insulating layer 304 Wiring 305 Insulating layer 306 Insulating layer 307 Insulating layer 308 Electrode 309 FPC
310 Anisotropic conductive layer 311 Sealing material 312 Substrate 331 Electrode 332 Semiconductor layer 333 Electrode 334 Electrode 335 Electrode 341 Electrode layer 342 Light emitting layer 343 Electrode layer 344 Partition 345 Filling material 7000 Display unit 7100 Television apparatus 7101 Housing 7103 Stand 7111 Remote controller 7200 Notebook personal computer 7211 Case 7212 Keyboard 7213 Pointing device 7214 External connection port 7300 Digital signage 7301 Case 7303 Speaker 7311 Information terminal 7400 Digital signage 7401 Pillar 7411 Information terminal

Claims (6)

  1. 　画像データに基づいて、発光素子を有する表示部に第１乃至第３のデータを出力する機能を有し、
    　前記第１のデータは、前記画像データに含まれるデータであり、
    　前記第１のデータは、前記発光素子を第１の輝度で発光させるためのデータであり、
    　前記第２のデータは、前記発光素子を第２の輝度で発光させるためのデータであり、
    　前記第３のデータは、前記発光素子を非発光の状態とするためのデータであり、
    　前記第２の輝度は、前記発光素子が発する光の輝度のばらつきが一定以下となる輝度であり、
    　前記第１の輝度が前記第２の輝度以上であるとき、前記第１のデータが出力され、
    　前記第１の輝度が前記第２の輝度未満であるとき、前記第２のデータ及び前記第３のデータが出力され、
    　前記第１のデータは、アナログ階調方式により前記表示部に映像を表示するための映像信号として用いられ、
    　前記第２のデータ及び前記第３のデータは、デジタル階調方式により前記表示部に映像を表示するための映像信号として用いられる画像処理回路。     Based on the image data, the display unit having a light emitting element has a function of outputting the first to third data,
    The first data is data included in the image data,
    The first data is data for causing the light emitting element to emit light at a first luminance,
    The second data is data for causing the light emitting element to emit light at a second luminance,
    The third data is data for setting the light emitting element to a non-light emitting state,
    The second luminance is a luminance at which variation in luminance of light emitted from the light emitting element is less than a certain value,
    When the first luminance is greater than or equal to the second luminance, the first data is output;
    When the first luminance is less than the second luminance, the second data and the third data are output,
    The first data is used as a video signal for displaying a video on the display unit by an analog gradation method,
    The second data and the third data are image processing circuits used as video signals for displaying video on the display unit by a digital gradation method.
  2. 　請求項１において、
    　前記第１の輝度と乱数を比較する機能を有し、
    　前記第１の輝度が前記乱数よりも大きいとき、前記第２のデータが出力され、
    　前記第１の輝度が前記乱数以下であるとき、前記第３のデータが出力される画像処理回路。     In claim 1,
    A function of comparing the first luminance with a random number;
    When the first luminance is greater than the random number, the second data is output,
    An image processing circuit for outputting the third data when the first luminance is equal to or less than the random number.
  3. 　請求項２において、
    　処理回路と、乱数生成回路と、比較回路と、を有し、
    　前記処理回路は、前記画像データに画像処理を施し、前記比較回路に出力する機能を有し、
    　前記乱数生成回路は、前記乱数を生成して前記比較回路に出力する機能を有し、
    　前記比較回路は、前記第１の輝度が前記第２の輝度以上であるとき、前記第１のデータを出力する機能を有し、
    　前記比較回路は、前記第１の輝度が前記第２の輝度未満であり、且つ前記乱数よりも大きいとき、前記第２のデータを出力する機能を有し、
    　前記比較回路は、前記第１の輝度が前記乱数以下であるとき、前記第３のデータを出力する機能を有する画像処理回路。     In claim 2,
    A processing circuit, a random number generation circuit, and a comparison circuit;
    The processing circuit has a function of performing image processing on the image data and outputting to the comparison circuit;
    The random number generation circuit has a function of generating the random number and outputting the random number to the comparison circuit;
    The comparison circuit has a function of outputting the first data when the first luminance is equal to or higher than the second luminance;
    The comparison circuit has a function of outputting the second data when the first luminance is less than the second luminance and larger than the random number;
    The comparison circuit is an image processing circuit having a function of outputting the third data when the first luminance is equal to or less than the random number.
  4. 　請求項１乃至３のいずれか一項に記載の画像処理回路及び表示部を有し、
    　前記表示部は複数の画素を有し、
    　前記画素の階調は、前記第１のデータを用いたアナログ階調方式と、前記第２のデータ及び前記第３のデータを用いたデジタル階調方式と、によって制御される表示システム。     It has an image processing circuit and a display part as described in any one of Claims 1 thru | or 3,
    The display unit has a plurality of pixels,
    The display system in which the gradation of the pixel is controlled by an analog gradation method using the first data and a digital gradation method using the second data and the third data.
  5. 　請求項４において、
    　前記画素は、前記発光素子と、トランジスタと、を有し、
    　前記トランジスタは、チャネル形成領域に金属酸化物を有する表示システム。     In claim 4,
    The pixel includes the light emitting element and a transistor,
    The transistor has a metal oxide in a channel formation region.
  6. 　請求項４に記載の表示システムが搭載された電子機器。 Electronic equipment equipped with the display system according to claim 4.
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