WO2019105244A1 - 一种纠错方法和纠错装置 - Google Patents

一种纠错方法和纠错装置 Download PDF

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Publication number
WO2019105244A1
WO2019105244A1 PCT/CN2018/115991 CN2018115991W WO2019105244A1 WO 2019105244 A1 WO2019105244 A1 WO 2019105244A1 CN 2018115991 W CN2018115991 W CN 2018115991W WO 2019105244 A1 WO2019105244 A1 WO 2019105244A1
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Prior art keywords
signal
decision
error correction
error
difference
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PCT/CN2018/115991
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English (en)
French (fr)
Inventor
陆玉春
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华为技术有限公司
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Priority to EP18883658.9A priority Critical patent/EP3713167A4/en
Publication of WO2019105244A1 publication Critical patent/WO2019105244A1/zh
Priority to US16/889,231 priority patent/US11218246B2/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03146—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
    • H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03203—Trellis search techniques
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03178—Arrangements involving sequence estimation techniques
    • H04L25/03312—Arrangements specific to the provision of output signals
    • H04L25/03324—Provision of tentative decisions

Definitions

  • the present application relates to the field of communications technologies, and in particular, to an error correction method and an error correction device.
  • High-speed link technology is the underlying technology for chips and interfaces, including electrical links and optical links.
  • ISI inter-symbol interference
  • PIN/APD Photo Detectors
  • TIAs Transimpedance Amplifiers
  • DFE Decision Feedback Equalizer
  • Figure 1 The structure of DFE is shown in Figure 1. It includes adder (+), subtractor (-), register (D), and multiplier ( ⁇ ) Determinator (indicated by a broken line in Fig. 1).
  • the DFE is a nonlinear feedback equalizer.
  • the input signal is received, the input signal is equalized by the decision signal of the previous signal to obtain an equalized output signal.
  • the equalized output signal is then subjected to a decision by the decider to obtain a decision signal of the equalized output signal.
  • the DFE can accurately equalize the ISI without amplifying the noise.
  • the DFE belongs to the feedback equalizer, when a signal is misjudged and an error occurs, the decision of the next signal is affected, thereby causing error transmission and increasing the bit error rate of the DFE.
  • the application provides an error correction method and an error correction device, which can reduce the bit error rate of the DFE and improve the equalization performance.
  • the present application provides an error correction method, including: acquiring a decision signal of a decision feedback equalizer DFE;
  • the input signal of the DFE, the equalized output signal, the difference value, and the decision can be used to detect the symbol position of the burst error end caused by the DFE, and the error decision signal is corrected, thereby reducing the DFE.
  • the bit error rate improves the balance performance.
  • determining a symbol position of the burst error end of the decision signal is: a difference and a decision signal in a symbol period
  • condition A is the absolute value of the difference in the symbol period It is greater than a preset decision threshold
  • condition B is that the difference in the symbol period is greater than 0, and the level of the decision signal in the symbol period is equal to the preset minimum level value
  • condition C is the difference in the symbol period The value is less than 0, and the level of the decision signal within the symbol period is equal to the preset maximum level value.
  • determining a symbol position of the burst error end of the decision signal is: when the equalized output signal in one symbol period satisfies the condition E or satisfying the condition F, determining that the symbol period is the symbol position of the burst error end of the decision signal; wherein the condition E is that the level value of the equalized output signal in the symbol period is less than the preset minimum level value and the pre- The difference of the decision threshold is set; the condition F is that the level value of the equalized output signal in the symbol period is greater than the sum of the preset maximum level value and the decision threshold.
  • the DFE-based error transmission feature is implemented, and the symbol position of the burst error end of the DFE decision signal is detected.
  • error correction is performed on the decision signal according to at least one of the input signal, the equalized output signal, and the difference, including: at least one of the input signal, the equalized output signal, and the difference, at the symbol position
  • the previous J decision signals are subjected to backtracking error correction to obtain a correct decision signal sequence.
  • backtracking error correction is performed on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value, to obtain a correct decision signal sequence, including: using a maximum likelihood sequence
  • the estimated algorithm performs backtracking error correction on the J decision signals according to the input signal and the output signal to obtain a correct decision signal sequence.
  • backtracking error correction is performed on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference, to obtain a correct sequence of the decision signal, including: using an error of the input signal
  • the control code word ECC performs backtracking error correction on the J decision signals to obtain a correct decision signal sequence.
  • backtracking error correction is performed on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference, to obtain a correct decision signal sequence, including: adopting a direct detection manner
  • the backtracking error correction is performed on the J decision signals according to the input signal and the difference value to obtain a correct decision signal sequence.
  • the equalization performance of the DFE can be made close to the performance curve of the MLSE, and the balance performance of the DFE is improved compared with the existing DFE equalization mode.
  • the method before determining the symbol position of the burst error end of the decision signal according to the detection of the at least one of the decision signal, the equalized output signal, and the difference value, the method further includes: performing the obtained decision signal (1) +D) decoding to obtain a decoded decision signal; correcting the decision signal according to at least one of the input signal, the equalized output signal, and the difference value, comprising: decoding the decoded decision signal at the symbol position Make corrections.
  • the equalization performance of the DFE in the (1+D) channel condition is close to the equalization performance of the AWGN channel, and the equalization performance of the DFE is improved compared to the existing DFE equalization mode.
  • the input signal is a pulse amplitude modulated PAM signal, a quadrature phase shift keyed QPSK signal, or a quadrature amplitude modulated QAM signal.
  • the present application provides an error correction apparatus, including: an obtaining unit, configured to acquire a decision signal of a decision feedback equalizer DFE, and configured to acquire at least one of an input signal, an equalized output signal, and a difference value of the DFE.
  • the difference is a difference between the level value of the decision signal and the level value of the equalized output signal;
  • the detecting unit is configured to determine the decision according to the detection of at least one of the decision signal, the equalized output signal, and the difference value The symbol position of the burst error end of the signal;
  • the error correcting unit configured to perform error correction on the decision signal according to at least one of the input signal, the equalized output signal, and the difference value when the detecting unit detects the symbol position.
  • the detecting unit determines the symbol position of the burst error end of the decision signal according to the detection of the at least one of the decision signal, the equalized output signal, and the difference value: when the difference and the judgment in one symbol period When the signal satisfies both condition A and condition B, or both condition A and condition C, the symbol period is determined as the symbol position of the burst error end of the decision signal; wherein condition A is the absolute value of the difference in the symbol period The value is greater than a preset decision threshold; condition B is that the difference in the symbol period is greater than 0, and the level of the decision signal in the symbol period is equal to a preset minimum level value; condition C is within the symbol period The difference is less than 0, and the level of the decision signal in the symbol period is equal to the preset maximum level value.
  • the detecting unit determines, according to the detection of the at least one of the decision signal, the equalized output signal, and the difference, the symbol position of the burst error end of the decision signal is: when the equalized output signal in one symbol period is satisfied.
  • Condition E or condition F is satisfied, determining that the symbol period is a symbol position of the burst error end of the decision signal; wherein condition E is that the level value of the equalized output signal in the symbol period is less than a preset minimum level value and The difference of the preset decision threshold; condition F is that the level value of the equalized output signal in the symbol period is greater than the sum of the preset maximum level value and the decision threshold.
  • the error correction unit performs error correction on the determination signal according to at least one of the input signal, the equalized output signal, and the difference, and specifically includes: performing, according to at least one of the input signal, the equalized output signal, and the difference,
  • the J decision signals located before the symbol position perform backtracking error correction to obtain a correct decision signal sequence.
  • the error correction unit performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value, to obtain a correct decision signal sequence, which includes: adopting The algorithm of maximum likelihood sequence estimation performs backtracking error correction on J decision signals according to the input signal and the output signal to obtain a correct decision signal sequence.
  • the error correction unit performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value, to obtain a correct sequence of the decision signal, including: utilizing The error control code word ECC of the input signal performs backtracking error correction on the J decision signals to obtain a correct decision signal sequence.
  • the error correction unit performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value, to obtain a correct decision signal sequence, which includes: adopting In the direct detection mode, backtracking error correction is performed on the J decision signals according to the input signal and the difference, and a correct decision signal sequence is obtained.
  • the error correction device further includes: a decoding unit, configured to determine, at the detecting unit, the symbol position of the burst error end of the decision signal according to the detecting of the at least one of the decision signal, the equalized output signal, and the difference signal Previously, (1+D) decoding is performed on the obtained decision signal to obtain a decoded decision signal; and the error correction unit corrects the decision signal according to at least one of the input signal, the equalized output signal, and the difference value, specifically The method includes: correcting the decoded decision signal located at the symbol position.
  • the input signal is a pulse amplitude modulated PAM signal, a quadrature phase shift keyed QPSK signal, or a quadrature amplitude modulated QAM signal.
  • the present application further provides an error correction apparatus, including: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer execution instruction; the processor, the memory and the communication interface through the bus Connected, when the error correction device is in operation, the processor executes computer executed instructions stored in the memory to implement the first aspect and the error correction method of the various implementations of the first aspect.
  • an error correction apparatus including: a processor, a memory, a bus, and a communication interface; the memory is configured to store a computer execution instruction; the processor, the memory and the communication interface through the bus Connected, when the error correction device is in operation, the processor executes computer executed instructions stored in the memory to implement the first aspect and the error correction method of the various implementations of the first aspect.
  • the present application also provides a computer storage medium having instructions stored therein that, when run on a computer, cause the computer to perform the method of the first aspect described above.
  • the present application also provides a computer program product comprising instructions which, when run on a computer, cause the computer to perform the method of the first aspect described above.
  • 1 is a schematic structural view of a DFE
  • FIG. 2 is a schematic diagram of an interconnection link provided by the present application.
  • FIG. 3 is a schematic structural diagram of a transceiver provided by the present application.
  • FIG. 4 is a schematic structural diagram 1 of an error correction device provided by the present application.
  • FIG. 5 is a schematic diagram of error transmission of a DFE provided by the present application.
  • FIG. 6 is a flowchart 1 of an embodiment of an error correction method provided by the present application.
  • FIG. 7 is a schematic diagram of a detection principle provided by the present application.
  • FIG. 8 is a schematic diagram of a modified path provided by the present application.
  • FIG. 9 is a schematic diagram of a sequence path provided by the present application.
  • FIG. 10 is a second flowchart of an embodiment of an error correction method provided by the present application.
  • FIG. 11 is a schematic diagram of an error correction principle provided by the present application.
  • FIG. 13 is a schematic structural diagram 2 of an error correction device provided by the present application.
  • FIG. 14 is a schematic structural diagram 3 of an error correction device provided by the present application.
  • FIG. 2 a schematic diagram of an interconnection link provided by the present application.
  • FIG. 2 a schematic diagram of an interconnection link provided by the present application.
  • FIG. 2 a schematic diagram of an interconnection link provided by the present application.
  • FIG. 2 is an interconnection link between the chip and the chip through a channel
  • FIG. 2 is an interconnection between the chip and the optical module, and the optical module and the light
  • (c) in Figure 2 shows the interconnection link between the board and the board through the channel; as shown in (d) of Figure 2, the system and the system Interconnected links interconnected by channels.
  • the interconnected link may be an electrical link, such as a printed circuit board (PCB), a coaxial cable, or the like; or an optical link or a wireless link.
  • the system involved in (d) of FIG. 2 may be a terminal device such as a general-purpose computer, a router, a switch, or even a mobile phone.
  • the error correction device provided by the present application may specifically be a module with a nonlinear error correction (NEC) function, and may be disposed in a receiver with a DFE in the above chip, optical module, single board, and system.
  • the detection signal and the error correction of the DFE wrong judgment are performed, thereby reducing the bit error rate of the DFE and improving the equalization capability.
  • FIG. 3 is a schematic diagram of a transceiver architecture provided by the present application.
  • (a) in FIG. 3 is a schematic diagram of a transceiver architecture based on a continuous time linear equalization (CTLE), a forward forward equalizer (FFE), a DFE, and an error correction device.
  • CTLE continuous time linear equalization
  • FFE forward forward equalizer
  • DFE DFE
  • the transmitter includes an FFE or an error control coding (ECC) encoder.
  • the FFE output signal of the transmitter is transmitted to the receiver via the channel.
  • the receiver adds the error correction device provided by the present application in the conventional CTLE, FFE, DFE combination mode.
  • the receiver includes a clock and data recovery (CDR) module, a least mean square (LMS) adaptation module, a CTLE, an analog to digital converter (ADC),
  • CDR clock and data recovery
  • LMS least mean square
  • ADC analog to digital converter
  • the FFE, the DFE, and the error correcting means, the arrows shown in (a) of Fig. 3 indicate the flow of signals before the respective modules.
  • the LMS adaptation module transmits a coefficient (c_dfe) of the DFE to the DFE, the FFE, and the error correction device, the coefficient including the tap coefficient ⁇ of the DFE and the interval dlevel between two adjacent levels in the PAM signal.
  • the signal output by the FFE is the input signal (dfe_input) of the DFE, which is input to the DFE and the error correction device.
  • the DFE outputs the equalized output signal (dfe_output) obtained by equalizing the input signal to the error correction device, and the decision signal (sym) obtained by deciding the equalized output signal, and the difference between the decision signal and the equalized output signal (err) ) Output to the LMS adaptive module and error correction device.
  • the error correcting means corrects the decision signal based on the received signal, and then outputs the corrected decision signal (sym_dly).
  • FIG. 3 is a schematic diagram of a transceiver architecture based on CTLE, FFE, DFE, reduced-state sequence estimation (RSSE), and error correction apparatus, and is based on (a) shown in FIG.
  • RSSE is added at the receiving end.
  • the input signal of the DFE and the coefficient of the DFE output by the LMS adaptive module are also input to the RSSE.
  • the corrected decision signal output by the error correction device is also input into the RSSE, and is output as the equalization result of the entire receiver after the RSSE decision.
  • FIG. 4 is a schematic structural diagram of an error correction device provided by the present application.
  • (a) in Fig. 4 shows an external connection structure of the error correction device.
  • the input signal (dfe_input) of the DFE is input to the error correction device and the DFE, respectively, and the equalized output signal (dfe_output), the difference value (err), and the decision signal (sym) output by the DFE are input to the error correction device.
  • the error correction device may also receive the coefficient (c_dfe) of the DFE output by the LMS adaptive module.
  • (b) in FIG. 4 is a schematic diagram of the internal structure of the error correction device, mainly including a detecting unit and an error correcting unit.
  • the detecting unit is configured to detect a symbol position of an end of burst error (EoBE) of the decision signal output by the DFE according to at least one of the received equalized output signal, the difference value, and the decision signal signal (in the present application The symbol position at which the burst error of the decision signal ends is indicated by EoBE).
  • the detecting unit sends the EoBE to the error correcting unit, and the error correcting unit corrects the error according to the at least one of the input signal, the equalized output signal, and the difference, and the EoBE detected by the detecting unit.
  • the correct decision signal (sym_dly) is obtained and the correct decision signal is output.
  • the error correction device can detect the EoBE based on the error transfer characteristic of the DFE and correct the error decision signal. Then, in order to facilitate the reader to understand the error correction method provided by the present application, before introducing the error correction method, firstly, the error transmission characteristics of the DFE are briefly introduced.
  • the first error transmission characteristic of the DFE is: the error transmission of the DFE ends when the level value of the equalized output signal is less than the symbol position of the "lowest symbol level - positive feedback error", and the level of the equalized output signal The value is greater than the symbol position of the "highest symbol level - negative feedback error". That is, EoBE is a symbol position where the level value of the equalized output signal is less than the "lowest symbol level - positive feedback error", or the symbol position where the level value of the equalized output signal is greater than "highest symbol level - negative feedback error".
  • the error transmission principle of the DFE can be as shown in FIG. 5.
  • the level distribution of the equalized output signal output by the DFE is the probability of superimposing random noise on the basis of the four symbol levels (-3, -1, 1 and 3) of the PAM-4 signal. distributed. If the random noise is Gaussian white noise, the level distribution of the equalized output signal is as shown by the "solid curve" in FIG.
  • the DFE can cause an error of " ⁇ dlevel" between adjacent signal levels, where ⁇ represents a coefficient value that adjusts the DFE decision "error abnormality", which parameter is configurable.
  • the DFE Since the DFE decides all the equalized output signals as one of the closest -3, -1, 1 and 3, the level of the bursty equalized output signal is at "3 + ⁇ Between dlevel" and "-3- ⁇ dlevel", then DFE will still misjudge the equalized output signal to get the wrong decision signal.
  • the level value of the equalized output signal is greater than "3+ ⁇ dlevel” or less than "(-3)- ⁇ dlevel”
  • the DFE will judge all equalized output signals to be 3 or -3. , get the correct decision signal, and the error transmission is over. For example, as shown in Figure 5, the "dummy curve", when the equalized output signal is close to 5 due to bit error transmission, the DFE will still decide the equalized output signal to be three.
  • the DFE When the equalized output signal approaches -5 due to bit error transmission, the DFE will still decide the equalized output signal to be -3. Therefore, the first error transmission characteristic of the DFE is that the error transmission of the DFE ends when the level value of the equalized output signal is less than the symbol position of the "lowest symbol level - positive feedback error", and the level of the equalized output signal The value is greater than the symbol position of the "highest symbol level - negative feedback error".
  • the second error transmission characteristic is: the error transmission of the DFE has a regular error pattern.
  • the burst error pattern distribution can be as shown in Table 1 and Table 2 below.
  • the signal input by the 1/(1+D) encoder is the signal that the (1+D) decoder should acquire after decoding the decision signal.
  • the decision signal obtained by the DFE after deciding the equalized output signal should be the same as the signal output by the 1/(1+D) encoder.
  • levels -3, -1, 1, and 3 are represented by 0, 1, 2, and 3.
  • Table 1 is an error pattern in which the burst error ends at the symbol position of the level value "lowest symbol level - positive feedback error" of the equalized output signal. Among them, the burst error of the decision signal starts from the third symbol period and ends at the 17th symbol period. If the decision signal is shifted down by a level compared to the signal output by the 1/(1+D) encoder, the error pattern of the decision signal is -1 if the decision signal is compared to 1/(1+D) When the signal output from the encoder is shifted up by a level, the error pattern of the decision signal is 1.
  • Table 2 is an error pattern in which the burst error ends at the symbol position where the level value of the equalized output signal is greater than the "highest symbol level - negative feedback error". Among them, the burst error of the decision signal starts from the third symbol period and ends at the 18th symbol period.
  • the decision signal decoded by the (1+D) decoder is compared with the signal input by the 1/(1+D) encoder, and the position of the burst error of the decoded decision signal is located in the burst of the pre-decoding decision signal.
  • the error pattern distribution of the decision signal may have other regular action distribution modes in addition to the above-mentioned "1" and "-1" alternately distributed.
  • “-2, -1, 0, 1, 2" alternately distributed, etc. are used for the error correction method provided by the present application.
  • the error correction method provided by the present application is based on two error transmission characteristics of the DFE, and implements detection of a symbol position where a decision signal is terminated with a burst error, and performs error correction when the symbol position is detected to reduce the error of the DFE.
  • the code rate improves the balance performance of the DFE.
  • a flowchart of an embodiment of an error correction method provided by the present application includes the following steps:
  • Step 601 The error correction device acquires a decision signal of the decision feedback equalizer DFE.
  • Step 602 The error correction device acquires at least one of an input signal, an equalized output signal, and a difference value of the DFE, where the difference is a difference between a level value of the decision signal and a level value of the equalized output signal. .
  • which of the input signal, the equalized output signal, and the difference value need to be specifically determined may be determined according to the manner in which the symbol position of the burst error end of the decision signal is determined and the error correction mode employed.
  • the input signal is a pulse amplitude modulation (PAM) signal, a quadrature phase-shift keying (QPSK) signal, or a quadrature amplitude modulation (QAM) signal.
  • PAM pulse amplitude modulation
  • QPSK quadrature phase-shift keying
  • QAM quadrature amplitude modulation
  • Step 603 The error correction device determines, according to the detection of the decision signal, the equalized output signal, and the at least one of the differences, a symbol position of a burst error end of the decision signal.
  • the present application provides two possible detection methods.
  • condition A is that the absolute value of the difference in the symbol period is greater than a preset decision threshold.
  • Condition B is that the difference in the symbol period is greater than 0, and the level value of the decision signal in the symbol period is equal to the preset minimum level value.
  • Condition C is that the difference in the symbol period is less than 0, and the level value of the decision signal in the symbol period is equal to the preset maximum level value.
  • the preset decision threshold may be “ ⁇ dlevel”, where ⁇ represents a coefficient of error of the preset DFE error.
  • the ⁇ dlevel may be acquired simultaneously by the error correction device when acquiring the decision signal, for example, receiving the c_dfe sent by the LAS adaptive module in FIG.
  • ⁇ dlevel may also be a fixed value preset in the error correction device, and the present application is not limited thereto.
  • the minimum level value and the maximum level value may be determined according to the level distribution of the channels in the applied scene. For example, with PAM-4 modulation, the minimum level value can be -3 and the maximum level value can be 3.
  • the detection condition of mode 1 can be expressed as A & (B
  • the schematic diagram of the detection condition may be as shown in (a) of FIG. 7, and the comparator, the SIGN function module, the ABS function module, the AND operation module (AND), and the OR operation module (OR) are as follows.
  • C) can be realized by connecting the signal flow directions (directions indicated by the arrows) shown in (a) of FIG. 7 to each other.
  • the comparator includes a size comparator for comparing the input signals of the two inputs, including a comparator for the magnitude of the preset value within the comparator.
  • the ABS function module is used to take the absolute value of the received value.
  • the SIGN function module is used to take the sign of the difference err.
  • the condition E is that the level value of the equalized output signal in the symbol period is smaller than the difference between the preset minimum level value and the preset decision threshold.
  • the condition F is that the level value of the equalized output signal in the symbol period is greater than the sum of the preset maximum level value and the decision threshold.
  • the detection condition of mode 2 can be expressed as F
  • Step 604 The error correction device, when detecting the symbol position, corrects the decision signal according to at least one of the input signal, the equalized output signal, and the difference.
  • the error correction device may buffer the signals and output them after delaying J+1 symbol periods. That is to say, the error correction device buffers the input signal sequence, the equalized output signal sequence, the difference sequence and the decision signal sequence, and each sequence includes J+1 signals.
  • the error correction device may be located at the at least one of the input signal, the equalized output signal, and the difference value.
  • the J decision signals preceding the symbol position are subjected to backtracking error correction to obtain a correct decision signal sequence, and then the correct decision signal sequence is output.
  • backtracking error correction there are various ways to implement backtracking error correction. This application will enumerate the following three methods of backtracking error correction, and exemplarily describe the specific process of backtracking error correction.
  • the buffered input signal in the error correction device is represented as x[k]
  • the equalized output signal can be represented as y[k]
  • the decision signal can be represented as s[k]
  • the difference can be expressed as e[k].
  • k EoBE, EoBE-1,..., EoBE-J.
  • EoBE represents the symbol position at which the burst error of the decision symbol ends.
  • the error correction device can detect the sequence of the correction value by using the maximum likelihood sequence estimation algorithm, and the specific process is as follows:
  • the detected error pattern of s[EoBE-1] can be expressed as ⁇ -1, 0 ⁇ .
  • the feature of the difference e[EoBE] has an equivalent determination effect as the feature of the decision signal s[EoBE]. If the feature of the difference is used as the criterion, when e[EoBE] ⁇ 0, s[EoBE-1] may need to “correct one level up” or “not correct”, then when e[EoBE] ⁇ 0
  • the set of correction values of s[EoBE-1] is ⁇ 0, 1 ⁇ .
  • s[EoBE-1] may need to “correct one level down” or “do not correct”. That is, when e[EoBE]>0, the set of correction values of s[EoBE-1] is ⁇ -1, 0 ⁇ .
  • L represents the channel response length
  • s'[k] represents the modified decision symbol
  • h[t] represents the channel response
  • the metric value of at least one modified path to the kth EoBE-J symbol period.
  • the error correcting means sequentially receives the input signal x[k], the output equalized signal y[k], the decision signal s[k], and the difference e[k] located in the 0-8th symbol period, and buffers in the order of reception.
  • k 0, 1, 2, ..., 8.
  • the values of x[k], y[k], s[k], and e[k] in the 0-8th symbol period of the buffer are shown in Table 3 below:
  • the original signal in Table 3 is the signal that the transmitter needs to send to the receiver, that is, the decision signal that the DFE should obtain after deciding the equalized output signal.
  • the decision signal located in the 2-7th symbol period has a burst error, which is different from the original signal.
  • the error correction device After acquiring each of x[k], y[k], s[k], and e[k] in Table 3, the error correction device uses the detection conditions in the above manner 1 or 2 to detect whether the current symbol period is sudden. The symbol position where the error ends.
  • the error correction device detects the difference e[8] at the 8th symbol period, and the decision signal s[8] satisfies the detection condition of the mode 1. That is
  • the correction path 0 to 0 indicates that the correction values of s[8] and s[7] are both 0, that is, on the correction path 0 to 0, the correction value sequence is "0, 0".
  • the correction path 0 to 1 indicates that the correction value of s[8] is 0, and the correction value of s[7] is 1, that is, on the correction path 0 to 1, the correction value sequence is "0, 1".
  • the error pattern is alternated in ⁇ -1, 0, 1 ⁇ , and then s[6] can be determined according to the correction value set ⁇ 0, 1 ⁇ of s[7].
  • the set of correction values is ⁇ -1,0 ⁇ .
  • the set of correction values ⁇ -1, 0 ⁇ of the set of correction values ⁇ 0, 1 ⁇ and s [6] of s [7] it can be determined that there are four branch paths between the seventh symbol period and the sixth symbol period. , branch path 0 to -1, branch path 0 to 0, branch path 1 to -1, and branch path 1 to 0, respectively.
  • the metric values of the four branch paths between the seventh symbol period and the sixth symbol period are calculated in the same manner as in S11.
  • the specific process is as follows:
  • the metric of branch path 0 to -1 is:
  • the metric for branch path 0 to 0 is:
  • the metric values for branch paths 1 through -1 are:
  • the metrics for branch paths 1 through 0 are:
  • the metric values of the branch paths 0 to -1 and 0 to 0 between the 7th symbol period and the 6th symbol period are calculated based on the correction value 0 of s[7], and due to the 7th symbol period and the The metric values of the branch paths 1 to -1 and 1 to 0 between the 6 symbol periods are calculated based on the correction value 1 of s[7]. Therefore, the metric values of each branch path can be superimposed on the metric values back to the two modified paths of s[7], and the metric values back to the respective modified paths of s[6] can be obtained.
  • the specific process is as follows:
  • the metric value 1.9182 of the branch path 0 to -1 is superimposed on the metric value 6.2566 of the correction path where the correction value 0 of s[7] is located, and the first correction path back to the correction value -1 of s[6] is obtained.
  • the metric value is 8.1748, and the sequence of correction values corresponding to the correction path is “0, 0, -1”.
  • the metric value 0.3782 of the branch path 1 to -1 is superimposed on the metric value 0.2513 of the correction path where the correction value 1 of s[7] is located, and the second correction path back to the correction value -1 of s[6] is obtained.
  • the metric value is 0.6295, and the sequence of correction values corresponding to the correction path is “0, 1, and ⁇ 1”.
  • the first modified path is determined as the corrected value-1 corrected path back to s[6], and the corrected path is recorded.
  • the metric is 0.6295.
  • the metric value 0.3782 of the branch path 0 to 0 is superimposed on the metric value 6.2566 of the correction path where the correction value 0 of s[7] is located, and the metric value of the first correction path back to the correction value 0 of s[6] is obtained.
  • the sequence of correction values corresponding to the correction path is "0, 0, 0".
  • the metric value 6.8382 of the branch path 1 to 0 is superimposed on the metric value 0.2513 of the correction path where the correction value 1 of s[7] is located, and the metric of the second correction path back to the correction value 0 of s[6] is obtained.
  • the value is 7.0895, and the correction value sequence corresponding to the correction path is “0, 1, 0”.
  • the first modified path is determined as a modified path back to the corrected value 0 of s[6], and the corrected path is recorded.
  • the measure is 6.6348.
  • the metric value of the correction path back to the correction value 0 of s[5] is 4.3274, and the correction value sequence corresponding to the correction path is "0, 1, -1, 0".
  • the metric value of the correction path back to the correction value 1 of s[5] is 0.6355, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1".
  • the metric value of the correction path back to the correction value 0 of s[4] is 4.3325, and the correction value sequence corresponding to the correction path is "0, 1, -1, 0, 0".
  • the metric value of the correction path back to the correction value -1 of s[4] is 0.6405, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1".
  • the metric value of the correction path back to the correction value 0 of s[3] is 2.8619, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 0".
  • the metric value of the correction path back to the correction value 1 of s[3] is 0.9002, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 1".
  • the metric value of the correction path back to the correction value 0 of s[2] is 2.9190, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 0, 0".
  • the metric value of the correction path back to the correction value -1 of s[2] is 0.9574, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 1, -1".
  • the metric value of the correction path back to the correction value 0 of s[1] is 2.0412, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 1, -1, 0".
  • the metric value of the correction path back to the correction value 1 of s[1] is 0.9574, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 1, -1, 1".
  • the metric value of the correction path back to the correction value 0 of s[0] is 2.0423, and the correction value sequence corresponding to the correction path is "0, 1, -1, 1, -1, 1, -1, 0, 0" .
  • the metric value of the correction path back to the correction value -1 of s[0] is 5.9078, and the sequence of correction values corresponding to the correction path is "0,1,-1,1,-1,1,-1,0,- 1".
  • the buffered decision signal sequence is corrected according to the sequence of the correction value being “0, 1, 1, 1, 1, -1, 1, -1, 0, 0”, and the corrected values are as shown in Table 4 below:
  • the error correction device does not modify s[8], s[1], and s[0]. 3. Correct s[7] up to a level correction to 3, s[6] down to a level correction to -1, s[5] up to a level correction to 1 and s[4 ] Correct a level correction to -3, s[3] up to a level correction to -1, and s[2] to a level correction to -3.
  • the corrected decision signal s'[k] is identical to the original signal, so the error correction is successful.
  • the error correction device may further detect the original signal sequence by using a maximum likelihood sequence estimation algorithm.
  • the following takes the channel of (1+ ⁇ D) under PAM-4 modulation as an example to illustrate the specific process of detecting the original signal sequence by using the maximum likelihood sequence estimation algorithm.
  • the error correcting means sequentially receives the input signal x[k], the output equalized signal y[k], the decision signal s[k], and the difference e[k] located in the 0-8th symbol period, and buffers in the order of reception.
  • k 0, 1, 2, ..., 8.
  • the values of x[k], y[k], s[k], and e[k] in the 0-8th symbol period of the buffer are shown in Table 5 below:
  • the original signal in Table 5 is the signal that the transmitter needs to send to the receiver, that is, the decision signal that the DFE should obtain after deciding the equalized output signal.
  • the decision signal located in the 2-7th symbol period has a burst error, which is different from the original signal.
  • the error correction device After acquiring each of x[k], y[k], s[k], and e[k] in Table 5, the error correction device uses the detection conditions in the above manner 1 or 2 to detect whether the current symbol period is sudden. The symbol position where the error ends.
  • the set of values of each of the remaining modified decision signals s'[k] is ⁇ -3.-1, 1, 3 ⁇ .
  • the state number 0 corresponds to the level value -3
  • the state number 1 corresponds to the level value -3
  • the state number 2 corresponds to the level value 1
  • the state number 3 corresponds to the level value 3.
  • the corrected s[EoBE-1] that is, the state number set of s'[7] is ⁇ 0, 1, 2, 3 ⁇ .
  • branch paths between s[8] and s'[7] which are branch paths "3 to 0", “3 to 1", “3 to 2", and "3 to 3".
  • Branch path since the state number sets of s'[7] and s'[6] are both ⁇ -3.-1, 1, 3 ⁇ , there are 16 between s'[7] and s'[6]. Branch path. Among them, there are four branch paths with the state number 0 of s'[6] as the end point, and are branch paths "0 to 0", “1 to 0", “2 to 0", and "3 to 0", respectively.
  • Equation 1 the metric values of the four branch paths ending with the state number 0 of s'[6] are calculated.
  • the metric value 13.458 of the branch path "0 to 0" is superimposed on the metric value 17.237 of the sequence path ending with the state number 0 of s'[7], and the state number 0 of s'[6] is obtained as the end point.
  • the metric value of the first sequence path is 7.4139, and the signal sequence corresponding to the first sequence path with the state number 0 of s'[6] is ⁇ 3, -3, -3 ⁇ .
  • the metric value 2.784 of the branch path "1 to 0" is superimposed on the metric value 4.630 of the sequence path ending with the state number 1 of s'[7], and the state number 0 of s'[6] is obtained as the end point.
  • the metric value of the second sequence path is 7.4139, and the signal sequence corresponding to the second sequence path with the state number 0 of s'[6] is ⁇ 3, -1, -3 ⁇ .
  • the metric value 0.110 of the branch path "2 to 0" is superimposed on the metric value 0.023 of the sequence path ending with the state number 2 of s'[7], and the state number 0 of s'[6] is obtained as the end point.
  • the metric value of the third sequence path is 0.133, and the signal sequence corresponding to the third sequence path with the state number 0 of s'[6] is ⁇ 3, 1, 3 ⁇ .
  • the metric value 0.10989 of the branch path "3 to 0" is superimposed on the metric value 5.436 of the sequence path ending with the state number 3 of s'[7], and the state number 0 of s'[6] is obtained as the end point.
  • the fourth sizing value of the sequence path is 8.852, and the signal sequence corresponding to the fourth sequence path ending with the state number 0 of s'[6] is ⁇ 3, 3, -3 ⁇ .
  • the metric value of the third sequence path is 0.133, so the record with the state number 0 of s'[6] is the end point.
  • the metric of the three sequence paths and the corresponding signal sequence is 0.133, so the record with the state number 0 of s'[6] is the end point.
  • the metric value of the sequence path with the state number 1 of s'[6] as the end point is 4.740, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, -1 ⁇ .
  • the metric value of the sequence path with the state number 2 of s'[6] as the end point is 10.066, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, 1 ⁇ .
  • the metric value of the sequence path ending with state number 3 of s'[6] is 22.673, and the sequence of signals corresponding to the sequence path is ⁇ 3, -3, 3 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[5] as the end point is 13.369, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, 1, -3 ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[5] as the end point is 8.043, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, -1, -1 ⁇ .
  • the metric value of the sequence path with the state number 2 of s'[5] as the end point is 3.436, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1 ⁇ .
  • the metric value of the sequence path ending with state number 3 of s'[5] is 0.166, and the sequence of signals corresponding to the sequence path is ⁇ 3, -1, -3, 3 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[4] as the end point is 4.799, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, -3, 3, -3 ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[4] as the end point is 0.189, and the signal sequence corresponding to the sequence path is ⁇ 3, -1, -3, 3, -1 ⁇ .
  • the metric value of the sequence path ending with state number 2 of s'[4] is 3.460, and the sequence of signals corresponding to the sequence path is ⁇ 3, 1, -3, 1, 1 ⁇ .
  • the metric value of the sequence path ending with state number 3 of s'[4] is 6.850, and the sequence of signals corresponding to the sequence path is ⁇ 3, 1, -3, 1, 3 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[3] as the end point is 11.710, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1, 3, -3 ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[3] as the end point is 6.892, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1, 3, -1 ⁇ .
  • the metric value of the sequence path with the state number 2 of s'[3] as the end point is 3.501, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1, 1, 1 ⁇ .
  • the metric value of the sequence path with the state number 3 of s'[3] as the end point is 0.231, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[2] as the end point is 3.282, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3, -3 ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[2] as the end point is 0.295, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3, -1 ⁇ .
  • the metric value of the sequence path ending with state number 2 of s'[2] is 3.565, and the sequence of signals corresponding to the sequence path is ⁇ 3, 1, -3, 1, 1, 1, 1 ⁇ .
  • the metric value of the sequence path with the state number 3 of s'[2] as the end point is 6.956, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1, 3, -1, -1 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[1] as the end point is 5.331, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 1, 1, 1, 1, 3, ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[1] as the end point is 2.0612, and the signal sequence corresponding to the sequence path is ⁇ 3,1,-3,3,-1,3,-1,-1 ⁇ .
  • the metric value of the sequence path ending with state number 2 of s'[1] is 0.746, and the sequence of signals corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3, -1, 1 ⁇ .
  • the metric value of the sequence path ending with state number 3 of s'[1] is 3.733, and the sequence of signals corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3, -3, 3 ⁇ .
  • the metric value of the sequence path with the state number 0 of s'[0] as the end point is 2.062, and the signal sequence corresponding to the sequence path is ⁇ 3, 1, -3, 3, -1, 3, -1, -1, -3 ⁇ .
  • the metric value of the sequence path with the state number 1 of s'[0] as the end point is 5.332, and the signal sequence corresponding to the sequence path is ⁇ 3,1,-3,1,1,1,1,-3,-1 ⁇ .
  • the metric value of the sequence path ending with state number 2 of s'[0] is 9.467, and the sequence of signals corresponding to the sequence path is ⁇ 3,1,-3,1,1,1,1,-3,1 ⁇ .
  • the metric value of the sequence path ending with state number 3 of s'[0] is 21.602, and the sequence of signals corresponding to the sequence path is ⁇ 3,1,-3,1,1,1,1,-3,3 ⁇ .
  • the corrected decision signal is the same as the original signal, so this error correction is successful, that is, the original signal sequence is successfully detected by using the error correction method provided by the present application.
  • the error correction device uses the ECC of the input signal to perform backtracking error correction on the J decision signals.
  • the specific implementation process of the mode (2) can be as follows:
  • the error correction device acquires an error pattern of the decision signal s[EoBE-1] located in the EoBE-1 symbol period according to the characteristic of the difference e[EoBE] located in the EoBE, and then according to the s[EoBE-1] The error pattern is corrected for s[EoBE-1], and the corrected decision signal s'[EoBE-1] is obtained.
  • the error correcting means calculates the ECC codeword sequence based on the sequence of the new decision signal after determining s'[EoBE-1].
  • s[EoBE-2] is corrected to a level in the opposite direction. For example, if s'[EoBE-1] corrects a level upwards, then s[EoBE-2] corrects a level downward. If s'[EoBE-1] is corrected downward by one level, then s[ EoBE-2] corrects a level upwards. After determining s'[EoBE-2], the ECC codeword sequence is re-determined and the ECC codeword located at EoBE is checked.
  • the ECC codeword may be a CRC check code or an error correcting code such as an RS error correcting code, a BCH error correcting code, or the like.
  • ECC and FEC are used together, the coding gain can be improved.
  • Illustrative, as shown in Figure 7, is an example of an ECC codeword applied to an error correction device provided herein, and an example of an FEC codeword used in conjunction with ECC.
  • ECC codeword types in Table 1 are merely exemplary representations, and are not all ECC codewords that can be selected by the error correction method provided by the present application.
  • the error correction device adopts a direct detection manner, and backtracking error correction is performed on the J decision signals according to the input signal and the difference, to obtain a correct decision signal sequence.
  • the specific implementation process of the mode (3) can be as follows:
  • the error correction device recalculates the difference e'[EoBE-1] of the EoBE-1 symbol periods according to s'[EoBE-1], and determines whether e'[EoBE-1] is If the above condition A is satisfied, it is judged whether
  • the error correction device corrects s[EoBE-2] by a level in the opposite direction according to the error correction direction of s'[EoBE-1]. For example, if s'[EoBE-1] corrects a level upwards, then s[EoBE-2] corrects a level downward. If s'[EoBE-1] is corrected downward by one level, then s[ EoBE-2] corrects a level upwards. After determining s'[EoBE-2], the difference e'[EoBE-2] of the EoBE-2 symbol periods is recalculated, and it is judged whether
  • ⁇ 4> using the methods in ⁇ 2> and ⁇ 3>, sequentially backtracking the J decision signals buffered before the EoBE in the error correction device. Until the decision signal and the difference value of a symbol period are updated, the updated difference does not satisfy the condition A, or the J decision signals are all corrected.
  • the error correcting means sequentially receives the input signal x[k], the output equalized signal y[k], the decision signal s[k], and the difference e[k] located in the 0-8th symbol period, and buffers in the order of reception.
  • k 0, 1, 2, ..., 8.
  • the values of x[k], y[k], s[k], and e[k] in the 0-8th symbol period of the buffer are shown in Table 8 below:
  • the error correction device After acquiring each of x[k], y[k], s[k], and e[k] in Table 8, the error correction device detects whether the current symbol period is sudden by using the detection condition in the first mode or the second mode. The symbol position where the error ends.
  • the error correction device detects the difference e[8] at the 8th symbol period, and the decision signal s[8] satisfies the detection condition of the mode 1. That is
  • the specific process is as follows:
  • the error correction device determines that s[EoBE-1] needs to be corrected upward by one level.
  • the specific calculation process is as follows:
  • FIG. 10 a flowchart of an embodiment of an error correction method provided by the present application, after the foregoing step 601, before step 603, the method includes the following steps:
  • Step 605 The error correction device performs (1+D) decoding on the obtained decision signal to obtain a decoded decision signal.
  • Step 604 specifically includes:
  • Step 604a The error correction device corrects the decision signal according to at least one of the equalized output signal and the difference value.
  • the error correction device may be located in accordance with the characteristics of the decision signal s[EoBE] of the EoBE, the error pattern of the (1+D) decoded decision signal located at the EoBE.
  • the DFE of the (1+ ⁇ D) channel and the number of taps of 1 are all exemplified by the PAM-4 modulation, the present application provides an example.
  • the error correction method can also be applied to any PAM-N modulation scenario such as PAM-1, PAM-2, and PAM-3, or to a modulation scenario such as QPSK or QAM. It also applies to any number of taps of DFE.
  • the implementation process is similar to the various embodiments provided in this application, and will not be further described herein.
  • the error transmission characteristic of the DFE is used to detect the symbol position of the burst error end caused by the DFE, and the error decision signal is corrected, thereby reducing the bit error rate of the DFE. Improve balance performance.
  • the probability of DFE burst error is low.
  • an error of more than 1000 bits is generated at an average error rate of 1e-3, so the overall throughput of the error correction device can be greatly increased. reduce.
  • the schematic diagram of the error correction principle provided by the present application is a schematic diagram of the error correction unit of the error correction device when performing the above step 604.
  • the present application lists three possible examples, including the principles shown in (a), (b), and (c) of FIG.
  • the register (D), the symbol pattern generator, and the processing module are connected to each other in accordance with the signal flow direction (in the direction indicated by the arrow) as shown in (a) of FIG.
  • the signals that can be input to the error correction unit include an equalized output signal (dfe_output), a difference value (err), a decision signal (sym), an EoBE, and a coefficient of the DFE (c_dfe).
  • the error correction device can output a signal including a modified decision signal (sym_dly) and a modified difference (err_dly) (a) manner to implement the above-mentioned "correction method using a maximum likelihood sequence estimation algorithm to detect a sequence of correction values".
  • the register, the processing module, and the EoBE error correction module are connected to each other in accordance with the signal flow as shown in (b) of FIG.
  • the (b) mode can implement the above-described "1+D-based decoding" error correction method.
  • the register, the processing module, and the error pattern generator will be connected to each other in accordance with the signal flow as shown in (c) of FIG.
  • the (c) mode can implement the above-mentioned "detection of the original signal sequence by the maximum likelihood sequence estimation algorithm” and the above-mentioned "direct detection” error correction mode.
  • the balance performance comparison diagram provided by the present application is shown.
  • the horizontal axis indicates the signal-to-noise ratio
  • the vertical axis indicates the bit error rate.
  • Curve 1 shows the equalization performance curve of the DFE under the precoding off condition based on the (1+D) channel in the prior art
  • the curve 2 indicates that the DFE is in the precoding on condition based on the (1+D) channel in the prior art.
  • Curve 4 represents the performance curve of the MLSE under the precoding off condition based on the (1+D) channel in the prior art
  • the curve 5 represents the prior art, based on the (1+D) channel, the MLSE is under the precoding on condition Performance curve.
  • AWGN Additive White Gaussian Noise
  • the graphic designation 1 indicates that the DFE is based on the (1+D) channel equalization performance data after the mode shown in (b) of FIG. 11 provided by the present application. As can be seen from Figure 12, the graphical designation 1 is distributed at curve 3. That is to say, after the error correction method based on (1+D) decoding provided by the present application is used to correct the decision signal output by the DFE, the equalization performance curve of the DFE is close to the performance curve of the DFE under the AWGN channel.
  • the graphic designation 2 indicates the equalization performance data of the DFE under the precoding off condition based on the (1+D) channel after the manner shown in (a) or (c) of FIG. 11 provided by the present application.
  • the graphical logo 2 is distributed at curve 4. That is to say, after the error correction mode outputted by the DFE is corrected by using the error correction mode shown in (a) or (c) of FIG. 11 provided by the present application, the DFE is precoded based on the (1+D) channel.
  • the equalization performance curve under closed conditions is close to the performance curve of the MLSE under precoding off conditions based on the (1+D) channel.
  • the graphic designation 3 indicates the equalization performance data of the DFE under the precoding on condition based on the (1+D) channel after the manner shown in (a) or (c) of FIG. 11 provided by the present application.
  • the graphical logo 2 is distributed at curve 4. That is to say, after the error correction mode outputted by the DFE is corrected by using the error correction mode shown in (a) or (c) of FIG. 11 provided by the present application, the DFE is precoded based on the (1+D) channel.
  • the equalization performance curve under the on condition is close to the performance curve based on the (1+D) channel and the MLSE under the precoding on condition.
  • the error correction device includes corresponding hardware structures and/or software modules for performing the respective functions in order to implement the above functions.
  • the present application can be implemented in a combination of hardware or hardware and computer software in combination with the elements and algorithm steps of the various examples described in the embodiments disclosed herein. Whether a function is implemented in hardware or computer software to drive hardware depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.
  • an error correction device provided by the present application includes:
  • the obtaining unit 130 is configured to obtain a decision signal of the decision feedback equalizer DFE, and is further configured to acquire at least one of an input signal, an equalized output signal, and a difference value of the DFE, where the difference is the power of the decision signal The difference between the flat value and the level value of the equalized output signal.
  • the detecting unit 131 is configured to determine, according to the detection of the at least one of the decision signal, the equalized output signal, and the difference, a symbol position of a burst error end of the decision signal.
  • the error correction unit 132 is configured to correct the decision signal according to at least one of the input signal, the equalized output signal, and the difference value when the detecting unit 131 detects the symbol position. wrong.
  • the detecting unit 131 determines, according to the detection of the at least one of the decision signal, the equalized output signal, and the difference, a symbol position of a burst error end of the decision signal is : when the difference between the difference period and the decision signal satisfies the condition A and the condition B at the same time, or both the condition A and the condition C are satisfied, determining that the symbol period is the end of the burst error of the decision signal Symbol location.
  • the condition A is that the absolute value of the difference in the symbol period is greater than a preset decision threshold.
  • Condition B is that the difference in the symbol period is greater than 0, and the level value of the decision signal in the symbol period is equal to a preset minimum level value.
  • Condition C is that the difference in the symbol period is less than 0, and the level value of the decision signal in the symbol period is equal to a preset maximum level value.
  • a schematic structural diagram of the detecting unit 131 is as shown in (a) of FIG. 7.
  • the detecting unit 131 determines, according to the detection of the at least one of the decision signal, the equalized output signal, and the difference, a symbol position of a burst error end of the decision signal is :
  • the equalized output signal in one symbol period satisfies the condition E or satisfies the condition F, it is determined that the symbol period is a symbol position at which the burst error of the decision signal ends.
  • the condition E is that the level value of the equalized output signal in the symbol period is less than a difference between a preset minimum level value and a preset decision threshold.
  • the condition F is that the level value of the equalized output signal in the symbol period is greater than a sum of a preset maximum level value and the decision threshold.
  • a schematic structural diagram of the detecting unit 131 is as shown in (b) of FIG. 7.
  • the error correction unit 132 performs error correction on the decision signal according to at least one of the input signal, the equalized output signal, and the difference, and specifically includes:
  • the error correction unit 132 performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value.
  • the correct decision signal sequence includes:
  • the maximum likelihood sequence estimation algorithm is used to perform backtracking error correction on the J decision signals according to the input signal and the output signal to obtain a correct decision signal sequence.
  • the structural schematic diagram of the error correction unit 132 may be as shown in (a) or (c) of FIG.
  • the error correction unit 132 performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value.
  • the correct decision signal sequence includes:
  • Backtracking error correction is performed on the J decision signals by using an error control codeword ECC of the input signal to obtain a correct decision signal sequence.
  • the structure diagram of the error correction unit 132 may be as shown in (c) of FIG.
  • the error correction unit 132 performs backtracking error correction on the J decision signals located before the symbol position according to at least one of the input signal, the equalized output signal, and the difference value.
  • the correct decision signal sequence specifically includes: performing direct trace detection according to the input signal and the difference value, and performing backtracking error correction on the J decision signals to obtain a correct decision signal sequence.
  • the structural schematic diagram of the error correction unit 132 may be as shown in (c) of FIG.
  • the error correction device further includes a decoding unit 133.
  • the decoding unit 133 is configured to determine, at the detecting unit 131, that a burst error of the decision signal ends according to detection of at least one of the decision signal, the equalized output signal, and the difference value Before the symbol position, the obtained decision signal is (1+D) decoded to obtain the decoded decision signal.
  • the error correcting unit 132 performs error correction on the decision signal according to at least one of the input signal, the equalized output signal, and the difference, and specifically includes: decoding after being located at the symbol position The decision signal is error corrected.
  • the decoding unit 133 may be a unit module of the error correction unit 132, and the decoding unit 133 may specifically be a 1+D decoder. Then, based on the optional mode, the structure diagram of the error correction unit 132 can be as shown in (b) of FIG.
  • the input signal is a pulse amplitude modulated PAM signal, a quadrature phase shift keying QPSK signal, or a quadrature amplitude modulated QAM signal.
  • the error correction device may be implemented by means of a circuit.
  • the detection unit 131 may be a detection circuit
  • the error correction unit 132 may be an error correction circuit
  • the decoding unit 133 may be a decoding circuit.
  • Unit 130 can be an acquisition circuit.
  • the symbol position of the burst error end caused by the DFE is detected by using the error transmission characteristic of the DFE, and the error decision signal is corrected, thereby reducing the bit error rate of the DFE and improving the equalization performance.
  • FIG. 14 another possible structural diagram of the error correction device provided by the present application includes a processor 140, a communication interface 141, a bus 142, and a memory 143.
  • the processor 140 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), and field programmable.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application-specific integrated circuit
  • FPGA field programmable gate array
  • the processor 140 can also be a combination of computing functions, such as one or more microprocessor combinations, a combination of a DSP and a microprocessor, and the like.
  • the processor 140 can be used to perform the method steps performed by the various functional modules of the error correction device of FIG. 6 or 10.
  • the processor 140 can be used to perform the method steps performed by the various functional modules of the error correction device of FIG. 6 or 10.
  • the processor 140 For details of the error correction method performed by the processor 140, refer to the related description in the embodiment shown in FIG. 6 or 10, and details are not described herein again.
  • Communication interface 141 may be a transceiver of an error correction device.
  • the processor 140 performs signal transmission and reception between the module via the communication interface 141.
  • the processor 140, the communication interface 141 and the memory 143 are interconnected by a bus 142; the bus 142 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus. Wait.
  • the bus 142 can be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is shown in Figure 14, but it does not mean that there is only one bus or one type of bus.
  • the symbol position of the burst error end caused by the DFE is detected by using the error transmission characteristic of the DFE, and the error decision signal is corrected, thereby reducing the bit error rate of the DFE and improving the equalization performance.
  • the steps of a method or algorithm described in connection with the present disclosure may be implemented in a hardware, or may be implemented by a processor executing software instructions.
  • the software instructions may be composed of corresponding software modules, which may be stored in a random access memory (RAM), a flash memory, a read only memory (ROM), an erasable programmable read only memory ( Erasable programmable ROM (EPROM), electrically erasable programmable read only memory (EEPROM), registers, hard disk, removable hard disk, compact disk read only (CD-ROM) or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor to enable the processor to read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and the storage medium can be located in an ASIC.
  • the ASIC can be located in a core network interface device.
  • the processor and the storage medium may also exist as discrete components in the core network interface device.
  • the present application further provides a computer storage medium, wherein the computer storage medium may store a program, and the program may include some or all of the steps in the embodiments of the error correction method provided by the application.
  • the storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), or a random access memory (RAM).
  • the present application also provides a computer program product comprising instructions which, when executed on a computer, cause the computer to perform some or all of the steps of the various embodiments of the error correction method provided herein.

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Abstract

本申请提供一种纠错方法和纠错装置，涉及通信技术领域，能够降低DFE的误码率，提高均衡性能，该方法包括：获取判决反馈均衡器DFE的判决信号；获取所述DFE的输入信号、均衡输出信号和差值中的至少一个信号，所述差值为所述判决信号的电平值与所述均衡输出信号的电平值之间的差值；根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置；当检测到所述符号位置时，根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错。

Description

一种纠错方法和纠错装置
本申请要求在2017年12月1日提交中国专利局、申请号为201711248568.5、发明名称为“一种纠错方法和纠错装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及通信技术领域，尤其涉及一种纠错方法和纠错装置。
背景技术
高速链路技术是芯片和接口的基础技术，包括电链路和光链路。在高速电链路中，由于电缆或者光纤***收发器时产生的插损会导致码间干扰(Inter Symbol Interference，ISI)，而在高速光链路中，光纤的色散以及收发器中光电转换器件、如驱动器(Driver)，调制器(Modulator)，光电检测器(PIN/APD)，跨阻放大器(TIA)等器件的带宽限制也造成ISI。因此，需要在收发器中设置均衡器来补偿由于插损或者器件欠带宽所造成的ISI。
目前判决反馈均衡(Decision Feedback Equalizer，DFE)是较为常用的一种均衡器，DFE的结构如图1所示，包括加法器(+)、减法器(-)、寄存器(D)、乘法器(×)判决器(图1中以折线表示)。DFE属于非线性反馈均衡器，当接收到输入信号后，会利用前一个信号的判决信号对该输入信号进行均衡，得到均衡输出信号。然后将该均衡输出信号经过判决器判决，得到该均衡输出信号的判决信号。在不发生误码的情况下，DFE可以精确的把ISI均衡掉，同时不会放大噪声。
然而，由于DFE属于反馈均衡器，当一个信号错判，出现误码，则会影响下一个信号的判决，从而造成误码传递，提高DFE的误码率。
发明内容
本申请提供一种纠错方法和纠错装置，能够降低DFE的误码率，提高均衡性能。
第一方面，本申请提供一种纠错方法，包括：获取判决反馈均衡器DFE的判决信号；
获取该DFE的输入信号、均衡输出信号和差值中的至少一个信号，该差值为该判决信号的电平值与该均衡输出信号的电平值之间的差值；根据对该判决信号、该均衡输出信号和该差值中的至少一个信号的检测，确定该判决信号的突发错误结束的符号位置；当检测到该符号位置时，根据该输入信号、该均衡输出信号和该差值中的至少一个信号，对该判决信号进行纠错。
采用本申请提供的纠错方法，能够利用DFE的输入信号、均衡输出信号、差值以及判决，检测DFE带来的突发错误结束的符号位置，并且对错误判决信号进行纠错，从而降低DFE的误码率，提高均衡性能。
可选的，根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定该判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的差值和判决信号同时满足条件A和条件B，或者同时满足条件A和条件C时，则确定该符号周期为判决信号的突 发错误结束的符号位置；其中，条件A为该符号周期内的差值的绝对值大于预设的判决门限；条件B为该符号周期内的差值大于0，且该符号周期内的判决信号的电平值等于预设的最小电平值；条件C为该符号周期内的差值小于0，且该符号周期内的判决信号的电平值等于预设的最大电平值。
可选的，根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定该判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的均衡输出信号满足条件E或者满足条件F，则确定该符号周期为判决信号的突发错误结束的符号位置；其中，条件E为该符号周期内的均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值；条件F为该符号周期内的均衡输出信号的电平值大于预设的最大电平值与判决门限的和。
采用两种可选的方式，实现了基于DFE的误码传递特性，检测DFE的判决信号的突发错误结束的符号位置。
可选的，根据输入信号、均衡输出信号和差值中的至少一个信号，对判决信号进行纠错，包括：根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，包括：采用最大似然序列估计的算法，根据该输入信号和该输出信号对该J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，包括：利用输入信号的差错控制码字ECC对该J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，包括：采用直接检测的方式，根据输入信号和差值对该J个判决信号进行回溯纠错，得到正确的判决信号序列。
采用上述四种可选的方式，能够使得DFE的均衡性能接近于MLSE的性能曲线，相比于现有的DFE均衡方式，提高了DFE的均衡性能。可选的，根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定判决信号的突发错误结束的符号位置之前，该方法还包括：对获取到的判决信号进行(1+D)解码，得到解码后的判决信号；根据输入信号、均衡输出信号和差值中的至少一个信号，对判决信号进行纠错，包括：对位于该符号位置处的解码后的该判决信号进行纠错。
采用该可选的方式，能够使得在(1+D)信道条件下DFE的均衡性能接近于AWGN信道的均衡性能，相比于现有的DFE均衡方式，提高了DFE的均衡性能。
可选的，输入信号为脉冲振幅调制PAM信号、正交相移键控QPSK信号或者正交振幅调制QAM信号。
第二方面，本申请提供一种纠错装置，包括：获取单元，用于获取判决反馈均衡器DFE的判决信号，还用于获取DFE的输入信号、均衡输出信号和差值中的至少一个信号，差值为判决信号的电平值与均衡输出信号的电平值之间的差值；检测单元，用于根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定判决信号的突发错误结束的符号 位置；纠错单元，用于在检测单元检测到符号位置时，根据输入信号、均衡输出信号和差值中的至少一个信号，对判决信号进行纠错。
可选的，检测单元根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的差值和判决信号同时满足条件A和条件B，或者同时满足条件A和条件C时，则确定该符号周期为判决信号的突发错误结束的符号位置；其中，条件A为该符号周期内的差值的绝对值大于预设的判决门限；条件B为该符号周期内的差值大于0，且该符号周期内的判决信号的电平值等于预设的最小电平值；条件C为该符号周期内的差值小于0，且该符号周期内的判决信号的电平值等于预设的最大电平值。
可选的，检测单元根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的均衡输出信号满足条件E或者满足条件F，则确定该符号周期为判决信号的突发错误结束的符号位置；其中，条件E为该符号周期内的均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值；条件F为该符号周期内的均衡输出信号的电平值大于预设的最大电平值与判决门限的和。
可选的，纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，对判决信号进行纠错，具体包括：根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：采用最大似然序列估计的算法，根据输入信号和输出信号对J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：利用输入信号的差错控制码字ECC对J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：采用直接检测的方式，根据输入信号和差值对J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，纠错装置还包括解码单元；解码单元，用于在检测单元根据对判决信号、均衡输出信号和差值中的至少一个信号的检测，确定判决信号的突发错误结束的符号位置之前，对获取到的判决信号进行(1+D)解码，得到解码后的判决信号；纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，对判决信号进行纠错，具体包括：对位于符号位置处的解码后的判决信号进行纠错。
可选的，输入信号为脉冲振幅调制PAM信号、正交相移键控QPSK信号或者正交振幅调制QAM信号。
本申请提供的纠错装置的技术效果可以参见上述第一方面或第一方面的各个实现方式的技术效果，此处不再赘述。
第三方面，本申请还提供了一种纠错装置，包括：处理器、存储器、总线以及通信接 口；该存储器，用于存储计算机执行指令；该处理器，通过该总线与该存储器和通信接口连接，当该纠错装置运行时，该处理器执行该存储器中存储的计算机执行指令，以实现第一方面以及第一方面的各种实现方式所述的纠错方法。
本申请提供的纠错装置的技术效果可以参见上述第一方面或第一方面的各个实现方式的技术效果，此处不再赘述。
第四方面，本申请还提供一种计算机存储介质，所述计算机存储介质中存储有指令，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
第五方面，本申请还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述第一方面所述的方法。
附图说明
图1为DFE的结构示意图；
图2为本申请提供的互联链路的示意图；
图3为本申请提供的收发机架构示意图；
图4为本申请提供的一种纠错装置的结构示意图一；
图5为本申请提供的一种DFE的误码传递原理图；
图6为本申请提供的一种纠错方法的一个实施例的流程图一；
图7为本申请提供的检测原理示意图；
图8为本申请提供的一种修正路径示意图；
图9为本申请提供的一种序列路径示意图；
图10为本申请提供的一种纠错方法的一个实施例的流程图二；
图11为本申请提供的纠错原理示意图；
图12为本申请提供的一种均衡性能对比示意图；
图13为本申请提供的一种纠错装置的结构示意图二；
图14为本申请提供的一种纠错装置的结构示意图三。
具体实施方式
本申请提供纠错方法和纠错装置，可以应用于需要高速互联的场景。例如，如图2所示，为本申请提供的互联链路示意图。其中，如图2中的(a)所示为芯片与芯片之间通过信道互联的互联链路；图2中的(b)所示为芯片与光模块之间的互联，以及光模块与光模块之间互联的互联链路；图2中的(c)所示为单板与单板之间通过信道互联的互联链路；如图2中的(d)所示为***与***之间通过信道互联的互联链路。其中，互联的链路可以是电链路，例如，印刷电路板(printed circuit board，PCB)、同轴电缆等；也可以是光链路和无线链路。图2中的(d)所涉及的***可以为通用计算机、路由器、交换机甚至手机等终端设备。
本申请提供的纠错装置具体可以是一种具备非线性误差纠错(nonlinear error correction，NEC)功能的模块，可以设置在上述芯片、光模块、单板以及***中的具备DFE的接收机中，以对DFE错判的判决信号进行检测以及纠错，从而降低DFE的误码率，提高均衡能力。示例性的，如图3所示为本申请提供的收发机架构示意图。其中，图3中的(a)为基于连续时间线性均衡器(continuous time linear equalization，CTLE)、 前向均衡器(feed forward equalizer,FFE)、DFE和纠错装置的收发机架构示意图。在该收发机架构中，发射机包括FFE或者包括差错控制编码(error control coding，ECC)编码器。发射机的FFE输出信号之后，经过信道传输至接收机。该接收机是在传统CTLE、FFE、DFE组合模式下增加本申请提供的纠错装置。该接收机包括时钟和数据恢复(clock and data recovery，CDR)模块、最小均方(least mean square，LMS)自适应(adaption)模块、CTLE、模数转换器(analog to digital converter，ADC)、FFE、DFE以及纠错装置，图3中的(a)所示的箭头表示各个模块之前的信号流向。其中，LMS自适应模块向DFE、FFE以及纠错装置发送DFE的系数(c_dfe)，该系数包括DFE的抽头系数α和PAM信号中相邻两个电平之间的间隔dlevel。FFE输出的信号为DFE的输入信号(dfe_input)，该输入信号输入DFE以及纠错装置。DFE将该输入信号均衡后得到的均衡输出信号(dfe_output)输出至纠错装置，并将对均衡输出信号进行判决后得到的判决信号(sym)，以及判决信号与均衡输出信号的差值(err)输出至LMS自适应模块和纠错装置。纠错装置根据接收到的信号对判决信号进行纠错，然后输出修正后的判决信号(sym_dly)。
图3中的(b)为基于CTLE、FFE、DFE、精简状态序列估计(reduced-state sequence estimation，RSSE)和纠错装置的收发机架构示意图，与图3中的(a)所示的基于CTLE、FFE、DFE和纠错装置的收发机架构相比，在接收端增加了RSSE。DFE的输入信号和LMS自适应模块输出的DFE的系数也会输入到RSSE中。而纠错装置输出的修正后的判决信号也会输入到RSSE中，经过RSSE判决后作为整个接收机的均衡结果输出。
如图4所示，为本申请提供的一种纠错装置的结构示意图。图4中的(a)示出了纠错装置的外部连接结构。DFE的输入信号(dfe_input)分别输入到纠错装置和DFE中，而DFE输出的均衡输出信号(dfe_output)、差值差值(err)以及判决信号(sym)则输入到纠错装置中。可选的，纠错装置也可以接收LMS自适应模块输出的DFE的系数(c_dfe)。图4中的(b)为纠错装置的内部结构示意图，主要包括检测单元和纠错单元。检测单元用于根据接收到的均衡输出信号、差值以及判决信信号中的至少一个信号检测DFE输出的判决信号的突发错误结束(end of burst error，EoBE)的符号位置(在本申请中，判决信号的突发错误结束的符号位置用EoBE表示)。当检测单元检测到EoBE后，将EoBE发送给纠错单元，纠错单元根据输入信号、均衡输出信号和差值中的至少一个信号，以及检测单元检测到的EoBE对错误的判决进行纠错，得到正确的判决信号(sym_dly)，并输出该正确的判决信号。
在本申请中，纠错装置可以基于DFE的误码传递特性检测EoBE以及对错误的判决信号进行纠错。那么为了便于读者理解本申请提供的纠错方法，在介绍该纠错方法之前，首先对DFE的误码传递特性进行简要介绍。
首先，DFE的第一个误码传递特性为：DFE的误码传递会结束于均衡输出信号的电平值小于“最低符号电平-正反馈误差”的符号位置，和均衡输出信号的电平值大于“最高符号电平-负反馈误差”的符号位置。即EoBE为均衡输出信号的电平值小于“最低符号电平-正反馈误差”的符号位置，或者是均衡输出信号的电平值大于“最高符号电平-负反馈误差”的符号位置。
示例性的，以PAM-4调制下(1+αD)信道为例，DFE的误码传递原理可以如图5所示。当没有发生误码传递时，DFE输出的均衡输出信号的电平分布为，在PAM-4信号的四个符 号电平(-3、-1、1以及3)的基础上叠加随机噪音的概率分布。若随机噪声为高斯白噪声，那么均衡输出信号的电平分布如图5中的“实曲线”所示。当发生误码传递时，假设DFE在相邻信号电平之间能够造成的误差的“ε·α·dlevel”，其中，ε表示调节DFE判决“误差异常”的系数值，该参数可配置。由于DFE会将所有的均衡输出信号判决为与其最接近的-3、-1、1以及3中的一个，因此，突发错误的均衡输出信号的电平值若处于“3+ε·α·dlevel”和“-3-ε·α·dlevel”之间，那么DFE则仍然会将均衡输出信号错判，得到错误的判决信号。而当均衡输出信号的电平值大于“3+ε·α·dlevel”，或者小于“(-3)-ε·α·dlevel”时，DFE会将所有的均衡输出信号判决为3或者-3，得到正确的判决信号，从而误码传递结束。例如，如图5所示“虚曲线”，当均衡输出信号由于误码传递而接近于5时，DFE仍然会将均衡输出信号判决为3。当均衡输出信号由于误码传递而接近于-5时，DFE仍然会将均衡输出信号判决为-3。因此，DFE的第一个误码传递特性为：DFE的误码传递会结束于均衡输出信号的电平值小于“最低符号电平-正反馈误差”的符号位置，和均衡输出信号的电平值大于“最高符号电平-负反馈误差”的符号位置。
其次，第二个误码传递特性为：DFE的误码传递具有规律性的错误图样。
示例性的，以PAM-4调制下(1+αD)信道为例，突发错误图样分布可以如下表1、表2所示。其中，待传输的信号先输入发射机的1/(1+D)编码器中，经过1/(1+D)编码后发送到[1，Pos1]信道(α＝Pos1)，经过[1，Pos1]信道传输至接收机，以由接收机中的DFE进行均衡、判决以及(1+D)解码。
可以理解的是，1/(1+D)编码器输入的信号即为(1+D)解码器对判决信号进行解码后应该获取的信号。DFE对均衡输出信号进行判决后得到的判决信号应该与1/(1+D)编码器输出的信号相同。在表1和表2中，用0、1、2、3表示电平-3、-1、1、3。
表1是突发错误结束于均衡输出信号的电平值“最低符号电平-正反馈误差”的符号位置的错误图样。其中，判决信号的突发错误开始于第3个符号周期，结束于第17个符号周期。若判决信号相比于1/(1+D)编码器输出的信号向下错了一个电平，则该判决信号的错误图样是-1，若判决信号相比于1/(1+D)编码器输出的信号向上错了一个电平，则该判决信号的错误图样是1。
表1
Pos1/Main 1
1/(1+D)编码器输入 1 0 1 3 3 0 3 2 0 1 3 3 0 0 0 0 2 3 0 3
1/(1+D)编码器输出 1 3 2 1 2 2 1 1 3 2 1 2 2 2 2 2 0 3 1 2
经过[1，Pos1]信道 1 4 5 3 3 4 3 2 4 5 3 3 4 4 4 4 2 3 4 3
均衡输出信号 1 3 2 2 1 3 0 2 2 3 0 3 1 3 1 3 1 3 1 2
判决信号 1 3 1 2 1 3 0 2 2 3 0 3 1 3 1 3 0 3 1 2
DFE错误图样 0 0 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 0 0 0 0
(1+D)解码输出 1 0 0 3 3 0 3 2 0 1 3 3 0 0 0 0 3 3 0 3
每个码字的错误图样 0 0 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
符号ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
表2是突发错误结束于均衡输出信号的电平值大于“最高符号电平-负反馈误差”的符号位置的错误图样。其中，判决信号的突发错误开始于第3个符号周期，结束于第18 个符号周期。
表2
Pos1/Main 1
1/(1+D)编码器输入 1 0 1 3 3 0 3 2 0 1 3 3 0 2 1 3 0 1 0 3
1/(1+D)编码器输出 1 3 2 1 2 2 1 1 3 2 1 2 2 0 1 2 2 3 1 2
经过[1，Pos1]信道 1 4 5 3 3 4 3 2 4 5 3 3 4 2 1 3 4 5 4 6
均衡输出信号 1 3 2 2 1 3 0 2 2 3 0 3 1 1 0 3 1 4 1 2
判决信号 1 3 1 2 1 3 0 2 2 3 0 3 1 1 0 3 1 3 1 2
DFE错误图样 0 0 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 0 0 0
(1+D)解码输出 1 0 0 3 3 0 3 2 0 1 3 3 0 2 1 3 0 0 0 3
每个码字的错误图样 0 0 -1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -1 0 0
符号ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
从表1和表2中记录的数据可以看出，判决信号的错误图样是“1”和“-1”交替分布。
而经过(1+D)解码器解码后的判决信号，与1/(1+D)编码器输入的信号相比，解码后的判决信号的突发错误的位置位于解码前判决信号的突发错误开始的符号位置，和突发错误结束的符号位置。
需要说明的是，在DFE的第二个误码传递特性中，判决信号的错误图样分布除上述列举的“1”和“-1”交替分布之外，还可以有其他规律性行动分布方式，例如按照“-2,-1,0,1,2”交替分布等，都是用于本申请提供的纠错方法。
本申请提供的纠错方法是基于DFE的两个误码传递特性，实现对判决信号进行突发错误结束的符号位置进行检测，并在检测到该符号位置时进行纠错，以降低DFE的误码率，提高DFE的均衡性能。
下面将结合具体实施例，对本申请提供的纠错方法进行介绍。
参见图6，为本申请提供的一种纠错方法的一个实施例的流程图，该方法包括如下步骤：
步骤601，纠错装置获取判决反馈均衡器DFE的判决信号。
步骤602，纠错装置获取该DFE的输入信号、均衡输出信号和差值中的至少一个信号，该差值为该判决信号的电平值与该均衡输出信号的电平值之间的差值。
在本申请中，可以根据确定判决信号的突发错误结束的符号位置的方式和采用的纠错方式确定具体需要获取输入信号、均衡输出信号和差值中的哪些信号。
其中，输入信号为脉冲振幅调制(pulse amplitude modulation，PAM)信号、正交相移键控(quadrature phase-shift keying，QPSK)信号或者正交振幅调制(quadrature amplitude modulation，QAM)信号。在本申请中，以差值＝判决信号的电平值-均衡输出信号的电平值为例进行说明。
步骤603，纠错装置根据对该判决信号、该均衡输出信号和该差值中的至少一个信号的检测，确定该判决信号的突发错误结束的符号位置。
示例性的，基于上述第一个误码传递特性，本申请提供两种可能的检测方式。
方式一：当一个符号周期内的差值和判决信号同时满足条件A和条件B，或者同时满 足条件A和条件C时，则确定该符号周期为判决信号的突发错误结束的符号位置。
其中，条件A为该符号周期内的差值的绝对值大于预设的判决门限。
条件B为该符号周期内的差值大于0，且该符号周期内的判决信号的电平值等于预设的最小电平值。
条件C为该符号周期内的差值小于0，且符号周期内的判决信号的电平值等于预设的最大电平值。
可选的，预设的判决门限可以为“ε·α·dlevel”，其中，ε表示预设的DFE的误差异常的系数。α·dlevel可以是纠错装置在获取判决信号时同时获取的，例如，接收图3中LAS自适应模块发送的c_dfe。ε·α·dlevel也可以是在纠错装置中预设的固定值，对此，本申请不做限制。
最小电平值和最大电平值可以是根据所应用场景中信道的电平分布来确定。例如，以在PAM-4调制下，最小电平值可以是-3，最大电平值可以是3。
那么，基于判决门限为“ε·α·dlevel”，最小电平值是-3，最大电平值是3，方式一的检测条件可以表示为A&(B|C)，条件A，B，C定义为：
A＝|err|>ε·α·dlevel
B＝(err>0)&(sym＝-3)
C＝(err<0)&(sym＝+3)
示例性的，该检测条件的原理图可以如图7中的(a)所示，将比较器、SIGN函数模块、ABS函数模块、与运算模块(AND)以及或运算模块(OR)，按照如图7中的(a)所示信号流向(箭头所指方向)相互连接即可实现该检测条件A&(B|C)。其中，比较器包括用于比较两个输入端输入信号的大小比较器，包括用于与比较器内预设数值的大小的比较器。ABS函数模块用于将接收的数值进行取绝对值运算。SIGN函数模块用于取差值err的符号。
方式二：当一个符号周期内的均衡输出信号满足条件E或者满足条件F，则确定该符号周期为判决信号的突发错误结束的符号位置。
其中，条件E为该符号周期内的均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值。
条件F为该符号周期内的均衡输出信号的电平值大于预设的最大电平值与判决门限的和。
方式二的检测条件可以表示为F|E，假设最小电平值与预设的判决门限的差值为G1，最大电平值与判决门限的和为G2,那么F|E的原理示意图可以如图7中的(b)所示，将两个比较器和或运算模块(OR)，按照如图7中的(b)所示的信号流向连接可实现该检测条件F|E。
步骤604，纠错装置当检测到该符号位置时，根据该输入信号、该均衡输出信号和该差值中的至少一个信号，对该判决信号进行纠错。
在一个示例中，纠错装置在获取到每个输入信号、均衡输出信号、差值以及判决信号后，可以将这些信号缓存，并延迟J+1个符号周期后输出。也就是说纠错装置中缓存了输入信号序列、均衡输出信号序列、差值序列以及判决信号序列，每个序列包括J+1个信号。
当纠错装置确定缓存的第J+1个符号周期是判决信号的突发错误结束的符号位置时，纠错装置可以根据输入信号、均衡输出信号和差值中的至少一个信号，对位于该符号位置 之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，然后将正确的判决信号序列输出。
需要说明的是，实现回溯纠错的方式有多种，本申请将列举如下三种回溯纠错的方式，对回溯纠错的具体过程进行示例性的说明。
(1)采用最大似然序列估计的算法，根据输入信号和输出信号对J个判决信号进行回溯纠错，得到正确的判决信号序列。
(2)利用输入信号的ECC对J个判决信号进行回溯纠错，得到正确的判决信号序列。
(3)采用直接检测的方式，根据输入信号和差值对J个判决信号进行回溯纠错，得到正确的判决信号序列。
为了便于描述，纠错装置中缓存的输入信号表示为x[k],均衡输出信号可以表示为y[k],判决信号可以表示为s[k]，差值可以表示为e[k]。其中,k＝EoBE,EoBE-1，…,EoBE-J。EoBE表示判决符号的突发错误结束的符号位置。
对于上述方式(1)，纠错装置可以采用最大似然序列估计算法检测修正值序列，具体过程如下：
1)、根据位于EoBE的差值e[EoBE]或者判决信号s[EoBE]的特征，确定位于第k＝EoBE-1符号周期的判决信号s[EoBE-1]的修正值。
例如，若以判决信号的特征作为判断标准，则当s[EoBE]＝最大电平值时，说明s[EoBE-1]并未出错，或者是“向下错判了一个电平”，即检测到的s[EoBE-1]的错误图样可以表示为{-1,0}。那么当s[EoBE]＝最大电平值时，s[EoBE-1]可能需要“向上修正一个电平”或者“不修正”，即s[EoBE-1]的修正值的集合为{0,1}。
当s[EoBE]＝最小电平值时，说明s[EoBE-1]并未出错，或者是“向上错判了一个电平”，即检测到的s[EoBE-1]的错误图样可以表示为{0,1}。那么当s[EoBE]＝最大电平值时，s[EoBE-1]可能“不修正”或者“向下修正一个电平”，即s[EoBE-1]的修正值的集合可以表示为{-1,0}。
由于s[EoBE]是正确的，因此，s[EoBE]的初始修正值为{0}。
可选的，差值e[EoBE]的特征与判决信号s[EoBE]的特征具有等价的判定效果。若以差值的特征作为判断标准，则当e[EoBE]<0时，s[EoBE-1]可能需要“向上修正一个电平”或者“不修正”，那么当e[EoBE]<0时，s[EoBE-1]的修正值的集合为{0,1}。
当e[EoBE]>0时，s[EoBE-1]可能需要“向下修正一个电平”或者“不修正”。即当e[EoBE]>0时，s[EoBE-1]的修正值的集合为{-1,0}。
2)、根据位于EoBE的输入信号x(EoBE)和判决信号s[EoBE]，位于第EoBE-1个符号周期的输入信号x(EoBE-1)和判决信号s[EoBE-1]，以及对应的修正值集合，利用公式一计算从EoBE回溯到第EoBE-1个符号周期的修正路径的度量值。
Figure PCTCN2018115991-appb-000001
其中L表示信道响应长度，s'[k]表示修正后判决符号，h[t]表示信道响应。
3)、基于上述DFE的第二个误码传递特性，当s[EoBE-1]的修正值集合为{0,1}时，s[EoBE-2]的修正值集合为{-1,0}；当s[EoBE-1]的修正值集合为{-1,0}时，s[EoBE-2]的修正值集合为{0,1}。那么在根据S1中确定s[EoBE-1]的修正值集合，确定s[EoBE-2]的修正值集合之后，即可计算从EoBE回溯到第EoBE-2个符号周期的修正路径的度量值。
以此类推，从EoBE向前回溯到位于第k＝EoBE-J个符号周期的判决信号s[EoBE-J]，根据确定的每个判决信号s[k]的修正值集合，计算从EoBE回溯到第k＝EoBE-J个符号周期的至少一个修正路径的度量值。
4)、选择度量值最小的修正路径，根据该修正路径确定修正值序列。
5)、根据得到的修正值序列，对缓存的判决信号序列进行纠错，得到正确的判决信号序列。
下面以PAM-4调制下(1+αD)的信道为例，对上述1)-5)进行举例说明。
假设α＝1，信道响应长度L＝2，信道响应为：{h[0],h[1]}＝{1,α}＝{1,1}，J＝8，ε·α·dlevel＝1.3。纠错装置依次接收位于第0-8个符号周期的输入信号x[k]、输出均衡信号y[k]、判决信号s[k]以及差值e[k]，并按照接收顺序进行缓存。其中，k＝0,1,2……，8。缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表3所示：
表3
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.1970 2.8030 3 3 0.1970
1 5.9664 2.9664 3 3 0.0336
2 1.0411 -1.9589 -1 -3 0.9589
3 -4.2390 -3.2390 -3 -1 0.2390
4 -4.5096 -1.5096 -1 -3 0.5096
5 -2.0712 -1.0712 -1 1 0.0712
6 -0.0770 0.9230 1 -1 0.0770
7 1.3850 0.3850 1 3 0.6150
8 6.5013 5.5013 3 3 -2.5013
表3中的原始信号是发射机需要发送给接收机的信号，也就是DFE对均衡输出信号判决之后应该得到的判决信号。从表3可以看出，位于第2-7个符号周期的判决信号出现突发错误，与原始信号不同。
纠错装置在获取表3中每个x[k]、y[k]、s[k]以及e[k]后都会利用上述方式一或方式二中的检测条件，检测当前符号周期是否为突然错误结束的符号位置。
假设以方式一为例，纠错装置检测到位于第8个符号周期的差值e[8]，以及判决信号s[8]满足方式一的检测条件。即|-2.5013|>1.3，且s[8]＝3。因此，纠错装置确定EoBE＝8，即第8个符号周期为突发错误结束的符号位置。从而纠错装置可以开始采用最大似然序列估计算法检测修正值序列，以完成对第8个符号周期之前的8个判决信号进行回溯纠错，即从s[8]向s[7]、s[6]，一直向前回溯纠错至s[0]。
S10、由于s[8]＝3，即s[EoBE]＝最大电平值，因此s[7]的修正值集合为{0,1}。
S11、根据公式一计算第k＝8个符号周期回溯到第k＝EoBE-1＝7个符号周期的修正路径的度量值。示例性的，取值均保留小数点后四位。具体计算过程如下：
根据s[8]的修正值集合{0}和s[7]的修正值集合{0，1}，可以确定第8个符号周期和第7个符号周期之间存在两条修正路径，分别是修正路径0到0和修正路径0到1。其中，修正路径0到0表示s[8]和s[7]的修正值都是0，也就是说在该修正路径0到0上，修正 值序列是“0,0”。修正路径0到1表示s[8]的修正值是0，s[7]的修正值是1，也就是说在该修正路径0到1上，修正值序列是“0,1”。
对于修正值路径0到0，修正后的判决信号s’[8]＝3，s’[7]＝1。将s’[8]＝3，s’[7]＝1，x[8]＝6.5013，以及L＝2，{h[0],h[1]}＝{1,1}代入公式一，得到的正值路径0到0的度量值为：
(s'[8]·h[0]+s'[7]·h[1]-x[8]) 2＝(3·1+1·1-6.5013) 2＝6.2566
对于修正值路径0到1，修正后的判决信号s’[8]＝3，s’[7]＝3。将s’[8]＝3，s’[7]＝3，x[8]＝6.5013，以及L＝2，{h[0],h[1]}＝{1,1}代入公式一，得到的正值路径0到1的度量值为：
(s'[8]·h[0]+s'[7]·h[1]-x[8]) 2＝(3·1+3·1-6.5013) 2＝0.2513
S12、根据上述第二个误码传递特性中，错误图样是在{-1,0，1}中交替，那么根据s[7]的修正值集合{0,1}，可以确定s[6]的修正值集合为{-1，0}。根据s[7]的修正值集合{0,1}和s[6]的修正值集合{-1，0}，可以确定第7个符号周期和第6个符号周期之间存在4个分支路径，分别是分支路径0到-1、分支路径0到0、分支路径1到-1以及分支路径1到0。
采用与S11中相同的方法，计算第7个符号周期和第6个符号周期之间的4个分支路径的度量值。具体过程如下：
分支路径0到-1的度量值为：
(s'[7]·h[0]+s'[6]·h[1]-x[7]) 2＝(1·1+(-1)·1-1.3850) 2＝1.9182
分支路径0到0的度量值为：
(s'[7]·h[0]+s'[6]·h[1]-x[7]) 2＝(1·1+1·1-1.3850) 2＝0.3782
分支路径1到-1的度量值为：
(s'[7]·h[0]+s'[6]·h[1]-x[7]) 2＝(3·1+(-1)·1-1.3850) 2＝0.3782
分支路径1到0的度量值为：
(s'[7]·h[0]+s'[6]·h[1]-x[7]) 2＝(3·1+1·1-1.3850) 2＝6.8382
由于第7个符号周期与第6个符号周期之间的分支路径0到-1和0到0的度量值是基于s[7]的修正值0计算的，而由于第7个符号周期与第6个符号周期之间的分支路径1到-1和1到0的度量值是基于s[7]的修正值1计算的。因此可以将各个分支路径的度量值叠加到回溯到s[7]两个修正路径的度量值上，得到回溯到s[6]各个修正路径的度量值。具体过程如下：
将分支路径0到-1的度量值1.9182，叠加到s[7]的修正值0所在修正路径的度量值6.2566上，得到回溯到s[6]的修正值-1的第一条修正路径的度量值8.1748，该修正路径对应的修正值序列为“0,0，-1”。
将分支路径1到-1的度量值0.3782，叠加到s[7]的修正值1所在修正路径的度量值0.2513上，得到回溯到s[6]的修正值-1的第二条修正路径的度量值0.6295，该修正路径对应的修正值序列为“0,1，-1”。
由于第二条修正路径的度量值0.6295小于第一条修正路径的度量值8.1748，因此将第一条修正路径确定为回溯到s[6]的修正值-1修正路径，并记录该修正路径的度量值0.6295。
将分支路径0到0的度量值0.3782，叠加到s[7]的修正值0所在修正路径的度量值6.2566上，得到回溯到s[6]的修正值0的第一条修正路径的度量值为6.6348，该修正路径对应的修正值序列为“0,0，0”。
将分支路径1到0的度量值6.8382，叠加到s[7]的修正值1所在修正路径的度量值0.2513上，得到回溯到s[6]的修正值0所在的第二条修正路径的度量值为7.0895，该修正路径对应的修正值序列为“0,1，0”。
由于第一条修正路径的度量值6.6348小于第二条修正路径的度量值7.0895，因此将第一条修正路径确定为回溯到s[6]的修正值0的修正路径，并记录该修正路径的度量值6.6348。
S13，基于S12中的方法，以此类推，计算回溯到每一个s[k]的修正路径的度量值。如图8所示，计算结果如下：
回溯到s[5]的修正值0的修正路径的度量值为4.3274，该修正路径对应的修正值序列为“0,1，-1,0”。
回溯到s[5]的修正值1的修正路径的度量值为0.6355，该修正路径对应的修正值序列为“0,1，-1,1”。
回溯到s[4]的修正值0的修正路径的度量值为4.3325，该修正路径对应的修正值序列为“0,1，-1,0,0”。
回溯到s[4]的修正值-1的修正路径的度量值为0.6405，该修正路径对应的修正值序列为“0,1，-1,1，-1”。
回溯到s[3]的修正值0的修正路径的度量值为2.8619，该修正路径对应的修正值序列为“0,1，-1,1，-1,0”。
回溯到s[3]的修正值1的修正路径的度量值为0.9002，该修正路径对应的修正值序列为“0,1，-1,1，-1,1”。
回溯到s[2]的修正值0的修正路径的度量值为2.9190，该修正路径对应的修正值序列为“0,1，-1,1，-1,0，0”。
回溯到s[2]的修正值-1的修正路径的度量值为0.9574，该修正路径对应的修正值序列为“0,1，-1,1，-1,1，-1”。
回溯到s[1]的修正值0的修正路径的度量值为2.0412，该修正路径对应的修正值序列为“0,1，-1,1，-1,1，-1，0”。
回溯到s[1]的修正值1的修正路径的度量值为0.9574，该修正路径对应的修正值序列为“0,1，-1,1，-1,1，-1,1”。
回溯到s[0]的修正值0的修正路径的度量值为2.0423，该修正路径对应的修正值序列为“0,1，-1,1，-1,1，-1，0,0”。
回溯到s[0]的修正值-1的修正路径的度量值为5.9078，该修正路径对应的修正值序列为“0,1，-1,1，-1,1，-1，0，-1”。
S14，当回溯到s[0]后，由于s[0]的修正值0的所在的修正路径最小，因此确定该路 径对应的修正值序列为“0,1,-1,1,-1,1,-1,0，0”为最终的修正值序列。
S15，根据修正值序列为“0,1,-1,1,-1,1,-1,0，0”对缓存的判决信号序列进行修正，修正后的数值如下表4所示：
表4
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.1970 2.8030 3 3 0.1970
1 5.9664 2.9664 3 3 0.0336
2 1.0411 -1.9589 -3 -3 0.9589
3 -4.2390 -3.2390 -1 -1 0.2390
4 -4.5096 -1.5096 -3 -3 0.5096
5 -2.0712 -1.0712 1 1 0.0712
6 -0.0770 0.9230 -1 -1 0.0770
7 1.3850 0.3850 3 3 0.6150
8 6.5013 5.5013 3 3 -2.5013
根据修正值序列为“0,1,-1,1,-1,1,-1,0，0”，纠错装置对s[8]、s[1]以及s[0]不修改仍为3，将s[7]向上修正一个电平修正为3，将s[6]向下修正一个电平修正为-1，将s[5]向上修正一个电平修正为1，将s[4]向下修正一个电平修正为-3，将s[3]向上修正一个电平修正为-1，将s[2]向下修正一个电平修正为-3。修正之后的判决信号s’[k]与原始信号相同，因此纠错成功。
可选的，对于上述方式(1)，纠错装置还可以采用最大似然序列估计算法检测原始信号序列。
下面以PAM-4调制下(1+αD)的信道为例，对采用最大似然序列估计算法检测原始信号序列的具体过程进行举例说明。
假设α＝1，信道响应长度L＝2，信道响应为：{h[0],h[1]}＝{1,α}＝{1,1}，J＝8，ε·α·dlevel＝1.0。纠错装置依次接收位于第0-8个符号周期的输入信号x[k]、输出均衡信号y[k]、判决信号s[k]以及差值e[k]，并按照接收顺序进行缓存。其中，k＝0,1,2……，8。缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表5所示：
表5
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 0.0806 -2.9194 -3 -3 -0.0806
1 -4.0338 -1.0338 -1 -1 0.0338
2 -0.6712 0.3288 1 -1 0.6712
3 1.7467 0.7467 1 3 0.2533
4 2.2046 1.2046 1 -1 10.2046
5 2.1523 1.1523 1 3 -0.1523
6 -0.1826 -1.1826 -1 -3 0.1826
7 -2.3315 -1.3315 -1 1 0.3315
8 4.1517 5.1517 3 3 -2.1517
表5中的原始信号是发射机需要发送给接收机的信号，也就是DFE对均衡输出信号判决之后应该得到的判决信号。从表5可以看出，位于第2-7个符号周期的判决信号出现突发错误，与原始信号不同。
纠错装置在获取表5中每个x[k]、y[k]、s[k]以及e[k]后都会利用上述方式一或方式二中的检测条件，检测当前符号周期是否为突然错误结束的符号位置。
假设以方式二为例，纠错装置检测到位于第8个符号周期的均衡输出信号y[8]＝5.1517＞3+1.3＝4.3，即满足上述条件F。因此，纠错装置确定EoBE＝8，即第8个符号周期为突发错误结束的符号位置。从而纠错装置可以开始采用最大似然序列估计算法检测原始信号序列。
S20，s[EoBE]＝s[8]不需要修正，始终为3。其余每一个修正后的判决信号s'[k]的取值集合为{-3.-1，1，3}。在该示例中，以状态编号0对应电平值-3，以状态编号1对应电平值-3，以状态编号2对应电平值1，以状态编号3对应电平值3。
以s[8]的状态编号3为起点，修正后的s[EoBE-1]，即s’[7]的状态编号集合为{0,1,2,3}。那么s[8]和s’[7]之间存在4个分支路径，分别为分支路径“3到0”，“3到1”，“3到2”，“3到3”。
S21，根据公式一计算s[8]和s’[7]之间的序列路径的度量值，示例性的，取值均保留小数点后三位。
由于分支路径“3到0”对应的信号序列为{3，-3}，因此，分支路径“3到0”的度量值为((3·1+(-3)·1)-4.1517)^2＝17.237。
由于分支路径“3到1”对应的信号序列为{3，-1}，因此，分支路径“3到1”的度量值为((3·1+(-1)·1)-4.1517)^2＝4.630。
分支路径“3到2”对应的信号序列为{3，1}，因此，分支路径“3到2”的度量值为((3·1+1·1)-4.1517)^2＝0.023。
分支路径“3到3”对应的信号序列为{3，3}，因此，分支路径“3到3”的度量值为((3·1+3·1)-4.1517)^2＝3.416。
由于在EoBE处，s[EoBE]的状态编号始终为3，因此s[8]和s’[7]之间的4个分支路径即为以s’[7]的4个状态编号终点的4个序列路径。
S23，由于s’[7]和s’[6]的状态编号集合均为{-3.-1，1，3}，因此，s’[7]和s’[6]之间存在16个分支路径。其中，以s’[6]的状态编号0为终点的分支路径共4个，分别为分支路径“0到0”、“1到0”、“2到0”、“3到0”。
根据根据公式一，计算以s’[6]的状态编号0为终点的4个分支路径的度量值。
由于分支路径“0到0”对应的序列为{-3,-3}，因此分支路径“0到0”的度量值为(((-3)·1+(-3)·1)-(-2.3315))^2＝13.458。
由于分支路径“1到0”对应的序列为{-1,-3}，因此分支路径“1到0”的度量值为(((-1)·1+(-3)·1)-(-2.3315))^2＝2.784。
由于分支路径“2到0”对应的序列为{+1,-3}，因此分支路径“2到0”的度量值为(((+1)·1+(-3)·1)-(-2.3315))^2＝0.110。
由于分支路径“3到0”对应的序列为{+3,-3}，因此分支路径“3到0”的度量值 为(((+3)·1+(-3)·1)-(-2.3315))^2＝5.436。
然后将分支路径“0到0”的度量值13.458，叠加到以s’[7]的状态编号0为终点的序列路径的度量值17.237上，得到以s’[6]的状态编号0为终点的第一条序列路径的度量值7.4139，以s’[6]的状态编号0为终点的第一条序列路径对应的信号序列为{3,-3,-3}。
将分支路径“1到0”的度量值2.784，叠加到以s'[7]的状态编号1为终点的序列路径的度量值4.630上，得到以s'[6]的状态编号0为终点的第二条序列路径的度量值7.4139，以s’[6]的状态编号0为终点的第二条序列路径对应的信号序列为{3,-1,-3}。
将分支路径“2到0”的度量值0.110，叠加到以s’[7]的状态编号2为终点的序列路径的度量值0.023上，得到以s’[6]的状态编号0为终点的第三条序列路径的度量值0.133，以s’[6]的状态编号0为终点的第三条序列路径对应的信号序列为{3,1,-3}。
将分支路径“3到0”的度量值0.10989，叠加到以s'[7]的状态编号3为终点的序列路径的度量值5.436上，得到以s’[6]的状态编号0为终点的第四条序列路径的度量值8.852，以s’[6]的状态编号0为终点的第四条序列路径对应的信号序列为{3,3,-3}。
通过比较可知，以s’[6]的状态编号0为终点的四个序列路径中，第三条序列路径的度量值0.133最小，因此记录以s’[6]的状态编号0为终点的第三条序列路径的度量值以及对应的信号序列。
S24，采用相同的处理方法计算以s’[6]的状态编号1为终点的序列路径的度量值、以s’[6]的状态编号2为终点的序列路径的度量值、以s’[6]的状态编号3为终点的序列路径的度量值。然后基于s’[6]的每一条序列路径的度量值向前回溯，一直到得到s’[0]的每一条序列路径的度量值。结果如图9所示。
以s’[6]的状态编号1为终点的序列路径的度量值为4.740，该序列路径对应的信号序列为{3，-1,-1}。
以s’[6]的状态编号2为终点的序列路径的度量值为10.066，该序列路径对应的信号序列为{3，-1,1}。
以s’[6]的状态编号3为终点的序列路径的度量值为22.673，该序列路径对应的信号序列为{3，-3,3}。
以s’[5]的状态编号0为终点的序列路径的度量值为13.369，该序列路径对应的信号序列为{3，-1,1,-3}。
以s’[5]的状态编号1为终点的序列路径的度量值为8.043，该序列路径对应的信号序列为{3，-1,-1,-1}。
以s’[5]的状态编号2为终点的序列路径的度量值为3.436，该序列路径对应的信号序列为{3，1,-3,1}。
以s’[5]的状态编号3为终点的序列路径的度量值为0.166，该序列路径对应的信号序列为{3，-1,-3,3}。
以s’[4]的状态编号0为终点的序列路径的度量值为4.799，该序列路径对应的信号序列为{3，-1,-3,3，-3}。
以s’[4]的状态编号1为终点的序列路径的度量值为0.189，该序列路径对应的信号序列为{3，-1,-3,3，-1}。
以s’[4]的状态编号2为终点的序列路径的度量值为3.460，该序列路径对应的信号序列为{3，1,-3,1,1}。
以s’[4]的状态编号3为终点的序列路径的度量值为6.850，该序列路径对应的信号序列为{3，1,-3,1,3}。
以s’[3]的状态编号0为终点的序列路径的度量值为11.710，该序列路径对应的信号序列为{3，1,-3,1,3，-3}。
以s’[3]的状态编号1为终点的序列路径的度量值为6.892，该序列路径对应的信号序列为{3，1,-3,1,3，-1}。
以s’[3]的状态编号2为终点的序列路径的度量值为3.501，该序列路径对应的信号序列为{3，1,-3,1,1，1}。
以s’[3]的状态编号3为终点的序列路径的度量值为0.231，该序列路径对应的信号序列为{3，1,-3,3，-1,3}。
以s’[2]的状态编号0为终点的序列路径的度量值为3.282，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-3}。
以s’[2]的状态编号1为终点的序列路径的度量值为0.295，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-1}。
以s’[2]的状态编号2为终点的序列路径的度量值为3.565，该序列路径对应的信号序列为{3，1,-3,1,1，1，1}。
以s’[2]的状态编号3为终点的序列路径的度量值为6.956，该序列路径对应的信号序列为{3，1,-3,1,3，-1，-1}。
以s’[1]的状态编号0为终点的序列路径的度量值为5.331，该序列路径对应的信号序列为{3，1,-3,1,1，1，1，-3}。
以s’[1]的状态编号1为终点的序列路径的度量值为2.0612，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-1，-1}。
以s’[1]的状态编号2为终点的序列路径的度量值为0.746，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-1，1}。
以s’[1]的状态编号3为终点的序列路径的度量值为3.733，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-3，3}。
以s’[0]的状态编号0为终点的序列路径的度量值为2.062，该序列路径对应的信号序列为{3，1,-3,3，-1,3，-1，-1，-3}。
以s’[0]的状态编号1为终点的序列路径的度量值为5.332，该序列路径对应的信号序列为{3，1,-3,1,1，1，1，-3，-1}。
以s’[0]的状态编号2为终点的序列路径的度量值为9.467，该序列路径对应的信号序列为{3，1,-3,1,1，1，1，-3，1}。
以s’[0]的状态编号3为终点的序列路径的度量值为21.602，该序列路径对应的信号序列为{3，1,-3,1,1，1，1，-3，3}。
S25，根据以s’[0]的4个状态编号为终点的序列路径中，以s’[0]的状态编号0为终点的序列路径的度量值最小，因此确定以s’[0]的状态编号0为终点的序列路径所对应的信号序列{3，1,-3,3，-1,3，-1，-1，-3}替换缓存的判决序列。替换之后结果如下表6 所示：
表6
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 0.0806 -2.9194 -3 -3 -0.0806
1 -4.0338 -1.0338 -1 -1 0.0338
2 -0.6712 0.3288 -1 -1 0.6712
3 1.7467 0.7467 3 3 0.2533
4 2.2046 1.2046 -1 -1 10.2046
5 2.1523 1.1523 3 3 -0.1523
6 -0.1826 -1.1826 -3 -3 0.1826
7 -2.3315 -1.3315 1 1 0.3315
8 4.1517 5.1517 3 3 -2.1517
修正后的判决信号与原始信号相同，因此本次纠错成功，即采用本申请提供的纠错方法，成功检测到原始信号序列。
可选的，对于回溯纠错的方式(2)纠错装置利用输入信号的ECC对J个判决信号进行回溯纠错。示例性的，方式(2)具体实现过程可以如下：
1>，纠错装置根据位于EoBE的差值e[EoBE]的特征，获取位于第EoBE-1个符号周期的判决信号s[EoBE-1]的错误图样，然后根据s[EoBE-1]的错误图样对s[EoBE-1]进行修正，得到修正后的判决信号s’[EoBE-1]。
其中，若e[EoBE]＞0，那么s[EoBE-1]的错误图样为1，则s[EoBE-1]需要向下修正一个电平。若e[EoBE]＜0，那么s[EoBE-1]的错误图样为-1，则s[EoBE-1]需要向上修正一个电平。
2>，纠错装置在确定s’[EoBE-1]之后，根据新的判决信号的序列计算ECC码字序列。
3>，校验位于EoBE的ECC码字，确定该ECC码字是否有效。若校验成功，则完成纠错。若验证失败，则继续执行S33。
4>，根据s'[EoBE-1]的纠错方向，将s[EoBE-2]向相反的方向修正一个电平。例如若s'[EoBE-1]是向上修正一个电平，那么s[EoBE-2]则向下修正一个电平，若s'[EoBE-1]是向下修正一个电平，那么s[EoBE-2]则向上修正一个电平。在确定s'[EoBE-2]之后，重新确定ECC码字序列，并校验位于EoBE的ECC码字是否。
5>，按照S33中的方法，依次回溯缓纠错存的s[k]，直到位于EoBE的ECC码字有效。若修正s[EoBE-J]之后，基于s'[EoBE-J]确定的ECC码字序列中，位于EoBE的ECC码字依然无效，则不对缓存的所有s[k]进行纠错。
在该示例中，ECC码字可以是CRC校验码，也可以是纠错码，例如RS纠错码，BCH纠错码等。当ECC和FEC配合使用时，能够提高编码增益。示例性的，如图表7所示，为本申请提供的应用于纠错装置的ECC码字示例，和与ECC配合使用的FEC码字示例。
表7
Figure PCTCN2018115991-appb-000002
需要说明的是，表1中的ECC码字类型仅为示例性的展示，并不是本申请提供的纠错方法能够选择的全部ECC码字。
可选的，对于回溯纠错的方式(3)，纠错装置采用直接检测的方式，根据输入信号和差值对J个判决信号进行回溯纠错，得到正确的判决信号序列。示例性的，方式(3)具体实现过程可以如下：
<1>，纠错装置根据位于EoBE的差值e[EoBE]或者判决信号s[EoBE]的特征，确定位于第k＝EoBE-1符号周期的判决信号s[EoBE-1]的修正值，并根据该修正值对s[EoBE-1]进行修正，得到修正后的判决信号s'[EoBE-1]。
例如，当s[EoBE]＝最大电平值时，s[EoBE-1]则需要向上修正一个电平；s[EoBE]＝最小电平值时，s[EoBE-1]则需要向下修正一个电平。
可选的，若以差值的特征作为判断标准，则当e[EoBE]<0时，s[EoBE-1]则需要向下修正一个电平；当e[EoBE]>0时，s[EoBE-1]则需要向上修正一个电平。
<2>,纠错装置根据s'[EoBE-1]，利用如下公式二重新计算第EoBE-1个符号周期的差值e'[EoBE-1]，并判断e'[EoBE-1]是否满足上述条件A，即判断|e'[EoBE-1]|>ε·α·dlevel是否成立。
e'[k]＝x[k]-(s'[k]·h[0]+s'[k-1]·h[1])     (公式二)
若满足e'[EoBE-1]满足上述条件A，则纠错完成。若e'[EoBE-1]不满足上述条件A，则执行<3>中的步骤。
<3>,纠错装置根据s'[EoBE-1]的纠错方向，将s[EoBE-2]向相反的方向修正一个电平。例如若s'[EoBE-1]是向上修正一个电平，那么s[EoBE-2]则向下修正一个电平，若s'[EoBE-1]是向下修正一个电平，那么s[EoBE-2]则向上修正一个电平。在确定s'[EoBE-2]之后，重新计算第EoBE-2个符号周期的差值e'[EoBE-2]，判断|e'[EoBE-2]|>ε·α·dlevel是否成立。
<4>,采用<2>和<3>中的方法，依次回溯缓存在纠错装置中位于EoBE之前的J个判决信号。直到某个符号周期的判决信号和差值更新后，更新后的差值不满足条件A，或者J个判决信号全部被修正为止。
下面以PAM-4调制下(1+αD)的信道为例，对上述<1>-<4>的具体过程进行举例说明。
假设α＝1，信道响应长度L＝2，信道响应为：{h[0],h[1]}＝{1,α}＝{1,1}，J＝8。纠错装置依次接收位于第0-8个符号周期的输入信号x[k]、输出均衡信号y[k]、判决信号s[k]以及差值e[k]，并按照接收顺序进行缓存。其中，k＝0,1,2……，8。缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表8所示：
表8
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 1 3 -0.2677
4 1.5404 0.5404 1 -1 0.4596
5 1.7793 0.7793 1 3 0.2207
6 2.1502 1.1502 1 -1 -0.1502
7 1.5025 0.5025 1 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
纠错装置在获取表8中每个x[k]、y[k]、s[k]以及e[k]后，利用上述方式一或方式二中的检测条件，检测当前符号周期是否为突然错误结束的符号位置。
假设以方式一为例，纠错装置检测到位于第8个符号周期的差值e[8]，以及判决信号s[8]满足方式一的检测条件。即|-2.2190|>1.3，且s[8]＝3。因此，纠错装置确定EoBE＝8，即第8个符号周期为突发错误结束的符号位置。从而纠错装置可以开始采用直接检测的方式，根据输入信号和差值对第8个符号周期之前的8个判决信号进行回溯纠错，即从s[8]向s[7]、s[6]，一直向前回溯纠错至s[0]。示例性的，具体过程如下：
S30，由于s[EoBE]＝3，即s[EoBE]＝最大电平值，因此纠错装置确定s[EoBE-1]则需要向上修正一个电平。
S31，纠错装置将s[EoBE-1]＝s[7]＝1向上修正一个电平，那么修正后的第7个符号周期的判决信号s'[7]＝3。
S32，纠错装置将x[7]＝1.5025、s'[7]＝3、s[6]＝1、h[0]＝1，h[1]＝1带入公式二中，计算得到e'[7]。具体计算过程如下：
e'[7]＝x[7]-(s'[7]·h[0]+s[6]·h[1])＝1.5025-[3·1+1·1]＝-2.4975
s'[7]和e'[7]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表9所示：
表9
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 1 3 -0.2677
4 1.5404 0.5404 1 -1 0.4596
5 1.7793 0.7793 1 3 0.2207
6 2.1502 1.1502 1 -1 -0.1502
7 1.5025 0.5025 3 3 -2.4975
8 6.2190 5.2190 3 3 -2.2190
S33，由于|e'[7]|>ε·α·dlevel成立，即e'[7]是否满足条件A。因此，纠错装置根据s'[7]的纠错方式对s[6]进行纠错。即将s[6]＝1向下修正一个电平，得到s'[6]＝-1。然后将x[6]＝2.1502、s'[6]＝-1、s[5]＝1、h[0]＝1，h[1]＝1带入公式二中，计算得到e'[6]＝2.1502。
s'[6]和e'[6]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表10所示：
表10
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 1 3 -0.2677
4 1.5404 0.5404 1 -1 0.4596
5 1.7793 0.7793 1 3 0.2207
6 2.1502 1.1502 -1 -1 2.1502
7 1.5025 0.5025 3 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
S34，采用与S33中相同的方法，依次向前回溯缓存的8个判决信号以及差值，直到某一个周期符号的e'[k]不满足条件A，或者s'[0]完成修正。具体过程如下：
由于|e'[6]|>ε·α·dlevel成立，即e'[6]是否满足条件A。因此，纠错装置根据s'[6]的纠错方式将s[5]＝1向上修正一个电平，得到s'[5]＝3。然后利用公式二中，计算得到e'[5]＝-2.2208。
s'[5]和e'[5]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表11所示:
表11
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 1 3 -0.2677
4 1.5404 0.5404 1 -1 0.4596
5 1.7793 0.7793 3 3 -2.2208
6 2.1502 1.1502 -1 -1 -0.1502
7 1.5025 0.5025 3 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
由于|e'[5]|>ε·α·dlevel成立，即e'[5]是否满足条件A。因此，纠错装置根据s'[5]的纠错方式将s[4]＝1向下修正一个电平，得到s'[4]＝-1。然后利用公式二中，计算得到e'[4]＝1.5404。
s'[4]和e'[4]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表12所示，
表12
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 1 3 -0.2677
4 1.5404 0.5404 -1 -1 1.5404
5 1.7793 0.7793 3 3 -0.2207
6 2.1502 1.1502 -1 -1 -0.1502
7 1.5025 0.5025 3 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
由于|e'[4]|>ε·α·dlevel成立，即e'[4]是否满足条件A。因此，纠错装置根据s'[4]的纠错方式将s[3]＝1向上修正一个电平，得到s'[3]＝3。然后利用公式二中，计算得到e'[3]＝-1.7323。
s'[3]和e'[3]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表13所示，
表13
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -1 -3 0.9963
3 0.2677 1.2677 3 3 -1.7323
4 1.5404 0.5404 -1 -1 0.4596
5 1.7793 0.7793 3 3 -0.2207
6 2.1502 1.1502 -1 -1 -0.1502
7 1.5025 0.5025 3 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
由于|e'[3]|>ε·α·dlevel成立，即e'[3]是否满足条件A。因此，纠错装置根据s'[3]的纠错方式将s[2]＝-1向下修正一个电平，得到s'[2]＝-3。然后利用公式二中，计算得到e'[2]＝1.0037。
s'[2]和e'[2]更新后，缓存的第0-8个符号周期内的x[k]、y[k]、s[k]以及e[k]的数值如下表14所示，
表14
k 输入信号(x) 均衡输出信号(y) 判决信号(s) 原始信号 差值(e)
0 -0.0377 -3.0377 -3 -3 0.0377
1 -2.1528 0.8472 1 1 0.1528
2 -0.9963 -1.9964 -3 -3 1.0037
3 0.2677 1.2677 3 3 0.2677
4 1.5404 0.5404 -1 -1 0.4596
5 1.7793 0.7793 3 3 -0.2207
6 2.1502 1.1502 -1 -1 -0.1502
7 1.5025 0.5025 3 3 0.4975
8 6.2190 5.2190 3 3 -2.2190
由于|e'[2]|>ε·α·dlevel不成立，因此不需要纠正s[2]。纠错装置中缓存的判决信号序列被修正后，为“3，3，-1，3，-1，3，-3，1，-3”，与原始信号序列相同，因此本次纠错成功。
可选的，基于图6，如图10所示，为本申请提供的一种纠错方法的一个实施例的流程图，在上述步骤601之后，步骤603之前，该方法包括如下步骤：
步骤605，纠错装置对获取到的判决信号进行(1+D)解码，得到解码后的判决信号。
步骤604具体可以包括：
步骤604a，纠错装置根据均衡输出信号和差值中的至少一个信号，对判决信号进行纠错。
示例性的，纠错装置可以根据位于EoBE的判决信号s[EoBE]的特征，位于EoBE的经过(1+D)解码后的判决信号的错误图样。
例如，当s[EoBE]＝最大电平值时，位于EoBE的经过(1+D)解码后的判决信号的错误图样是-1，因此需要向上修正一个电平；s[EoBE]＝最小电平值时，错误图样是1，因此需要向下修正一个电平。
需要说明的是，在上述本申请提供的各个实施例中，虽然均以PAM-4调制下(1+αD)的信道，抽头数量为1的DFE为例进行示例性的说明，但本申请提供的纠错方法还可以适用于PAM-1、PAM-2、PAM-3等任何一种PAM-N调制场景，也可以是适用于QPSK、QAM等调制场景。且对于任意抽头数量的DFE也都适用。其实现过程与本申请提供的各个实施方式类似，此处不再一一赘述。
值得说明的是，采用本申请提供的纠错方法，利用DFE的误码传递特性，检测DFE带来的突发错误结束的符号位置，并且对错误判决信号进行修正，从而降低DFE的误码率，提高均衡性能。
另外，在正常工作的条件下，DFE突发错误的概率较低，例如，在1e-3误码率下平均大于1000个比特才会发生一次错误，因此纠错装置的整体吞吐量可以大幅度降低。例如，接收机需要100Gbps的数据吞吐量，而纠错装置实际需要的吞吐量仅为100Gbps/1000＝100Mbps。
示例性的，如图11所示，为本申请提供的纠错原理示意图，即纠错装置的纠错单元在执行上述步骤604时的原理示意图。本申请列举三种可能的示例，包括如图11中的(a)、(b)、(c)所示原理。其中，将寄存器(D)、符号图样发生器以及处理模块(图11中以梯形表示)，按照如图11中的(a)所示信号流向(箭头所指方向)相互连接。其中，可以输入纠错单元的信号包括均衡输出信号(dfe_output)、差值差值(err)、判决信号(sym)、EoBE以及DFE的系数(c_dfe)。纠错装置可以输出的信号包括修正后的判决信号(sym_dly)以及修正后的差值(err_dly)(a)方式能够实现上述“采用最大似然序列估计算法检测修正值序列”的纠错方式。
将寄存器、处理模块以及EoBE纠错模块，按照如图11中的(b)所示信号流向相互连接。(b)方式能够实现上述“基于(1+D)解码”的纠错方式。
将包括寄存器、处理模块以及错误图样发生器，按照如图11中的(c)所示信号流向相互连接。(c)方式能够实现上述“采用最大似然序列估计算法检测原始信号序列”，以及上述“直接检测”的纠错方式。
如图12所示，为本申请提供的均衡性能对比示意图。其中，横轴标识信噪比，纵轴表示误码率。曲线1表示现有技术中，基于(1+D)信道，DFE在预编码关闭条件下的均衡性能曲线；曲线2表示现有技术中，基于(1+D)信道，DFE在预编码开启条件下的性能曲线；曲线3表示现有技术中，在加性高斯白噪声(Additive White Gaussian Noise，AWGN)信道(即(1+αD)信道α＝0的情况下)条件下DFE的性能曲线；曲线4表示现有技术中，基于(1+D)信道，MLSE在预编码关闭条件下的性能曲线；曲线5表示现有技术中，基于(1+D)信道，MLSE在预编码开启条件下的性能曲线。
图形标识1表示采用本申请提供的图11中的(b)所示的方式后，DFE基于(1+D)信道的均衡性能数据。从图12中可以看出，图形标识1分布在曲线3处。也就是说，采用本申请提供的“基于(1+D)解码”的纠错方式，对DFE输出的判决信号进行纠错后，DFE的均衡性能曲线接近于DFE在AWGN信道下的性能曲线。
图形标识2表示采用本申请提供的图11中的(a)或(c)所示的方式后，基于(1+D)信道，DFE在预编码关闭条件下的均衡性能数据。从图12中可以看出，图形标识2分布在曲线4处。也就是说，采用本申请提供的图11中的(a)或(c)所示的纠错方式，对DFE输出的判决信号进行纠错后，基于(1+D)信道，DFE在预编码关闭条件下的均衡性能曲线接近于基于(1+D)信道，MLSE在预编码关闭条件下的性能曲线。
图形标识3表示采用本申请提供的图11中的(a)或(c)所示的方式后，基于(1+D)信道，DFE在预编码开启条件下的均衡性能数据。从图12中可以看出，图形标识2分布在曲线4处。也就是说，采用本申请提供的图11中的(a)或(c)所示的纠错方式，对DFE输出的判决信号进行纠错后，基于(1+D)信道，DFE在预编码开启条件下的均衡性能曲线接近于基于(1+D)信道，MLSE在预编码开启条件下的性能曲线。
可以看出，相比于现有的DFE(曲线1和曲线2)，采用本申请提供的纠错方法，即DFE+纠错装置的方式之后，DFE的均衡性能提高。
且论是否发生误码，MLSE/RSSE都会全速运行，因此，MLSE/RSSE的复杂度和动态功耗都非常高。而本申请提供的DFE+纠错装置的方案，纠错装置在平均大于1000个比特的间隔才需要进行一次纠错，吞吐量需求小于100Gbps/1000＝0.1Gbps。因此，相比于MLSE/RSSE的技术方案，本申请提供的DFE+纠错装置的方案能够在提供高性能的均衡能力的同时，极大的降低实现复杂度以及动态功耗。
上述主要从各个网元之间交互的角度对本申请提供的方案进行了介绍。可以理解的是，纠错装置为了实现上述功能，其包含了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，本申请能够以硬件或硬件和计算机软件的结合形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本申请的范围。
如图13所示，为本申请提供的一种纠错装置，包括：
获取单元130，用于获取判决反馈均衡器DFE的判决信号，还用于获取所述DFE的输入信号、均衡输出信号和差值中的至少一个信号，所述差值为所述判决信号的电平值与所述均衡输出信号的电平值之间的差值。
检测单元131，用于根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置。
纠错单元132，用于在所述检测单元131检测到所述符号位置时，根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错。
可选的，所述检测单元131根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述差值和所述判决信号同时满足条件A和条件B，或者同时满足条件A和条 件C时，则确定所述符号周期为所述判决信号的突发错误结束的符号位置。
其中，条件A为所述符号周期内的所述差值的绝对值大于预设的判决门限。
条件B为所述符号周期内的所述差值大于0，且所述符号周期内的所述判决信号的电平值等于预设的最小电平值。
条件C为所述符号周期内的所述差值小于0，且所述符号周期内的所述判决信号的电平值等于预设的最大电平值。
示例性的，基于该可选方式，检测单元131的结构示意图如图7中的(a)所示。
可选的，所述检测单元131根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述均衡输出信号满足条件E或者满足条件F，则确定所述符号周期为所述判决信号的突发错误结束的符号位置。
其中，条件E为所述符号周期内的所述均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值。
条件F为所述符号周期内的所述均衡输出信号的电平值大于预设的最大电平值与所述判决门限的和。
示例性的，基于该可选方式，检测单元131的结构示意图如图7中的(b)所示。
可选的，所述纠错单元132根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，具体包括：
根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列。
可选的，所述纠错单元132根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：
采用最大似然序列估计的算法，根据所述输入信号和所述输出信号对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
示例性的，基于该可选方式，所述纠错单元132的结构示意图可以如图11中的(a)或(c)所示。
可选的，所述纠错单元132根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：
利用所述输入信号的差错控制码字ECC对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
示例性的，基于该可选方式，所述纠错单元132的结构示意图可以如图11中的(c)所示。
可选的，所述纠错单元132根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：采用直接检测的方式，根据所述输入信号和所述差值对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
示例性的，基于该可选方式，所述纠错单元132的结构示意图可以如图11中的(c) 所示。
可选的，所述纠错装置还包括解码单元133。
所述解码单元133，用于在所述检测单元131根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置之前，对获取到的所述判决信号进行(1+D)解码，得到解码后的所述判决信号。
所述纠错单元132根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，具体包括：对位于所述符号位置处的解码后的所述判决信号进行纠错。
其中，解码单元133可以是纠错单元132的一个单元模块，解码单元133具体可以是1+D解码器。那么基于该可选方式，所述纠错单元132的结构示意图可以如图11中的(b)所示。
可选的，所述输入信号为脉冲振幅调制PAM信号、正交相移键控QPSK信号或者正交振幅调制QAM信号。
在一个示例中，本申请提供的纠错装置可以是通过电路的方式实现，例如，上述检测单元131可以是检测电路，纠错单元132可以是纠错电路，解码单元133可以是解码电路，获取单元130可以是获取电路。
采用本申请提供的纠错装置，利用DFE的误码传递特性，检测DFE带来的突发错误结束的符号位置，并且对错误判决信号进行修正，从而降低DFE的误码率，提高均衡性能。
如图14所示，为本申请提供的纠错装置的另一种可能的结构示意图，包括处理器140、通信接口141、总线142和存储器143。
其中，处理器140可以是中央处理器(central processing unit，CPU)，通用处理器，数字信号处理器(digital signal processor，DSP)，专用集成电路(application-specific integrated circuit，ASIC)，现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。其可以实现或执行结合本申请公开内容所描述的各种示例性的逻辑方框，模块和电路。所述处理器140也可以是实现计算功能的组合，例如包含一个或多个微处理器组合，DSP和微处理器的组合等等。
当该纠错装置作为纠错装置时，该处理器140能够用于执行如图6或10中纠错装置的各个功能模块执行的方法步骤。具体的该处理器140所执行的纠错方法可参见上述如图6或10所示的实施例中的相关描述，此处不再赘述。
通信接口141可以是纠错装置的收发器。该处理器140通过该通信接口141与模块之间进行信号的收发。
处理器140、通信接口141和存储器143之间通过总线142相互连接；总线142可以是外设部件互连标准(peripheral component interconnect，PCI)总线或扩展工业标准结构(extended industry standard architecture，EISA)总线等。所述总线142可以分为地址总线、数据总线、控制总线等。为便于表示，图14中仅用一条粗线表示，但并不表示仅有一根总线或一种类型的总线。
采用本申请提供的纠错装置，利用DFE的误码传递特性，检测DFE带来的突发错误结束的符号位置，并且对错误判决信号进行修正，从而降低DFE的误码率，提高均衡性能。
在一个示例中，结合本申请公开内容所描述的方法或者算法的步骤可以硬件的方式来实现，也可以是由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read only memory，ROM)、可擦除可编程只读存储器(erasable programmable ROM，EPROM)、电可擦可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、只读光盘(CD-ROM)或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于核心网接口设备中。当然，处理器和存储介质也可以作为分立组件存在于核心网接口设备中。
具体实现中，本申请还提供一种计算机存储介质，其中，该计算机存储介质可存储有程序，该程序执行时可包括本申请提供的纠错方法的各实施例中的部分或全部步骤。所述的存储介质可为磁碟、光盘、只读存储记忆体(read-only memory，ROM)或随机存储记忆体(random access memory，RAM)等。
本申请还提供了一种包含指令的计算机程序产品，当其在计算机上运行时，使得计算机执行上述本申请提供的纠错方法的各实施例中的部分或全部步骤。
本领域的技术人员可以清楚地了解到本申请中的技术可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解，本申请中的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品可以存储在存储介质中，如ROM/RAM、磁碟、光盘等，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者VPN网关等)执行本发明各个实施例或者实施例的某些部分所述的方法。
本说明书中各个实施例之间相同相似的部分互相参见即可。尤其，对于装置实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例中的说明即可。
以上所述的本发明实施方式并不构成对本发明保护范围的限定。

Claims (20)

  1. 一种纠错方法，其特征在于，包括：
    获取判决反馈均衡器DFE的判决信号；
    获取所述DFE的输入信号、均衡输出信号和差值中的至少一个信号，所述差值为所述判决信号的电平值与所述均衡输出信号的电平值之间的差值；
    根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置；
    当检测到所述符号位置时，根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错。
  2. 如权利要求1所述的纠错方法，其特征在于，所述根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述差值和所述判决信号同时满足条件A和条件B，或者同时满足条件A和条件C时，则确定所述符号周期为所述判决信号的突发错误结束的符号位置；
    其中，条件A为所述符号周期内的所述差值的绝对值大于预设的判决门限；
    条件B为所述符号周期内的所述差值大于0，且所述符号周期内的所述判决信号的电平值等于预设的最小电平值；
    条件C为所述符号周期内的所述差值小于0，且所述符号周期内的所述判决信号的电平值等于预设的最大电平值。
  3. 如权利要求1所述的纠错方法，其特征在于，所述根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述均衡输出信号满足条件E或者满足条件F，则确定所述符号周期为所述判决信号的突发错误结束的符号位置；
    其中，条件E为所述符号周期内的所述均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值；
    条件F为所述符号周期内的所述均衡输出信号的电平值大于预设的最大电平值与所述判决门限的和。
  4. 根据权利要求1-3任一项所述的纠错方法，其特征在于，所述根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，包括：
    根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列。
  5. 根据权利要求4所述的纠错方法，其特征在于，所述根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，包括：
    采用最大似然序列估计的算法，根据所述输入信号和所述输出信号对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  6. 根据权利要求4所述的纠错方法，其特征在于，所述根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信 号进行回溯纠错，得到正确的判决信号序列，包括：
    利用所述输入信号的差错控制码字ECC对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  7. 根据权利要求4所述的纠错方法，其特征在于，所述根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，包括：
    采用直接检测的方式，根据所述输入信号和所述差值对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  8. 根据权利要求1-3任一项所述的纠错方法，其特征在于，根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置之前，所述方法还包括：
    对获取到的所述判决信号进行(1+D)解码，得到解码后的所述判决信号；
    所述根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，包括：
    对位于所述符号位置处的解码后的所述判决信号进行纠错。
  9. 根据权利要求1-8任一项所述的纠错方法，其特征在于，
    所述输入信号为脉冲振幅调制PAM信号、正交相移键控QPSK信号或者正交振幅调制QAM信号。
  10. 一种纠错装置，其特征在于，包括：
    获取单元，用于获取判决反馈均衡器DFE的判决信号，还用于获取所述DFE的输入信号、均衡输出信号和差值中的至少一个信号，所述差值为所述判决信号的电平值与所述均衡输出信号的电平值之间的差值；
    检测单元，用于根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置；
    纠错单元，用于在所述检测单元检测到所述符号位置时，根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错。
  11. 如权利要求10所述的纠错装置，其特征在于，所述检测单元根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述差值和所述判决信号同时满足条件A和条件B，或者同时满足条件A和条件C时，则确定所述符号周期为所述判决信号的突发错误结束的符号位置；
    其中，条件A为所述符号周期内的所述差值的绝对值大于预设的判决门限；
    条件B为所述符号周期内的所述差值大于0，且所述符号周期内的所述判决信号的电平值等于预设的最小电平值；
    条件C为所述符号周期内的所述差值小于0，且所述符号周期内的所述判决信号的电平值等于预设的最大电平值。
  12. 如权利要求10所述的纠错装置，其特征在于，所述检测单元根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置的方式为：当一个符号周期内的所述均衡输出信号满足条件 E或者满足条件F，则确定所述符号周期为所述判决信号的突发错误结束的符号位置；
    其中，条件E为所述符号周期内的所述均衡输出信号的电平值小于预设的最小电平值与预设的判决门限的差值；
    条件F为所述符号周期内的所述均衡输出信号的电平值大于预设的最大电平值与所述判决门限的和。
  13. 根据权利要求10-12任一项所述的纠错装置，其特征在于，所述纠错单元根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，具体包括：
    根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列。
  14. 根据权利要求13所述的纠错装置，其特征在于，所述纠错单元根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：
    采用最大似然序列估计的算法，根据所述输入信号和所述输出信号对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  15. 根据权利要求13所述的纠错装置，其特征在于，所述纠错单元根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：
    利用所述输入信号的差错控制码字ECC对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  16. 根据权利要求13所述的纠错装置，其特征在于，所述纠错单元根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对位于所述符号位置之前的J个判决信号进行回溯纠错，得到正确的判决信号序列，具体包括：
    采用直接检测的方式，根据所述输入信号和所述差值对所述J个判决信号进行回溯纠错，得到正确的判决信号序列。
  17. 根据权利要求10-12任一项所述的纠错装置，其特征在于，所述纠错装置还包括解码单元；
    所述解码单元，用于在所述检测单元根据对所述判决信号、所述均衡输出信号和所述差值中的至少一个信号的检测，确定所述判决信号的突发错误结束的符号位置之前，对获取到的所述判决信号进行(1+D)解码，得到解码后的所述判决信号；
    所述纠错单元根据所述输入信号、所述均衡输出信号和所述差值中的至少一个信号，对所述判决信号进行纠错，具体包括：
    对位于所述符号位置处的解码后的所述判决信号进行纠错。
  18. 根据权利要求10-17任一项所述的纠错装置，其特征在于，
    所述输入信号为脉冲振幅调制PAM信号、正交相移键控QPSK信号或者正交振幅调制QAM信号。
  19. 一种计算机可读存储介质，其特征在于，包括指令，当其在计算机上运行时，使得计算机执行如权利要求1至9中任一项所述的方法。
  20. 一种计算机程序产品，其特征在于，当其在计算机上运行时，使得计算机执 行如权利要求1至9中任一项所述的方法。
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