WO2019105085A1 - Heterojunction solar cell and method for fabrication thereof - Google Patents

Heterojunction solar cell and method for fabrication thereof Download PDF

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Publication number
WO2019105085A1
WO2019105085A1 PCT/CN2018/103606 CN2018103606W WO2019105085A1 WO 2019105085 A1 WO2019105085 A1 WO 2019105085A1 CN 2018103606 W CN2018103606 W CN 2018103606W WO 2019105085 A1 WO2019105085 A1 WO 2019105085A1
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layer
type doped
doped layer
intrinsic
type
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PCT/CN2018/103606
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French (fr)
Chinese (zh)
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杨苗
郁操
徐希翔
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君泰创新（北京）科技有限公司
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Publication of WO2019105085A1 publication Critical patent/WO2019105085A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the present application relates to, but is not limited to, the field of solar cell technology, and in particular, but not limited to, a heterojunction solar cell and a method of fabricating the same.
  • Silicon-based heterojunction solar cells have excellent power generation performance.
  • Existing silicon-based heterojunction solar cells are usually composed of a plurality of battery chips connected in series, and adjacent battery chips are connected in series by a solder ribbon.
  • the application provides a heterojunction solar cell, the heterojunction solar cell comprising:
  • the front surface of the crystalline silicon substrate is provided with a first intrinsic layer
  • a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;
  • a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate
  • a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
  • the present application provides a method for preparing a heterojunction solar cell, the method comprising the following steps:
  • An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
  • FIG. 1 is a schematic structural view of a heterojunction solar cell according to an embodiment of the present application.
  • FIG. 2 is a schematic view of two heterojunction solar cells provided in an embodiment of the present application in series;
  • FIG. 3 is a flow chart of a method for preparing a heterojunction solar cell according to an embodiment of the present application.
  • the positive and negative electrodes on the existing battery chip are respectively disposed on the front and back sides of the battery chip, when two adjacent battery chips are arranged, the positive electrode of one battery chip is above the battery chip, and the negative electrode of the other battery chip is at the battery chip.
  • the solder ribbon is on the two battery chips.
  • the position may be bent, which may easily cause chipping of the battery chip; and in order to be able to connect the opposite poles on the two battery chips, the size of the ribbon is required to be long, which undoubtedly increases the resistance of the ribbon, resulting in The power generation capacity of the assembled heterojunction solar cell is weakened.
  • the embodiment of the present application provides a heterojunction solar cell and a preparation method thereof, which reduce the series resistance and improve the conversion efficiency of the photovoltaic module.
  • the embodiment of the present application provides a heterojunction solar cell, and the heterojunction solar cell includes:
  • the front surface of the crystalline silicon substrate is provided with a first intrinsic layer
  • a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;
  • a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate
  • a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
  • the first N-type doped layer and the first P-type doped layer may be insulated from each other; the second N-type doped layer and the second P-type doped layer may be The insulation can be set between the two.
  • the first N-type doped layer and the second P-type doped layer correspond to positions on the front side and the back side of the crystalline silicon substrate, and the first P-type doped layer and The positions of the second N-type doped layer on the front and back sides of the crystalline silicon substrate are corresponding.
  • the heterojunction solar cell may further include:
  • a first transparent conductive layer disposed on the first N-type doped layer and the first P-type doped layer;
  • a second transparent conductive layer disposed on the second N-type doped layer and the second P-type doped layer;
  • the first negative electrode and the first positive electrode are both disposed on the first transparent conductive layer;
  • the second negative electrode and the second positive electrode are both disposed on the second transparent conductive layer.
  • the first negative electrode and the first positive electrode or between the second negative electrode and the second positive electrode may be connected by a solder ribbon.
  • an edge of the first N-type doping layer and an edge of the second P-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate; the first P-type The edges of the doped layer and the edges of the second N-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate.
  • the first positive electrode, the first negative electrode, the second positive electrode, and the second negative electrode may each include a fine gate line and a main gate line.
  • the diameter of the fine grid line may range from 20 ⁇ to 60 ⁇ m.
  • the number of the main gate lines is 2 to 6.
  • the first intrinsic layer and the second intrinsic layer may be intrinsic amorphous silicon layers.
  • the first P-type doped layer and the second P-type doped layer may be a P-type amorphous silicon layer, a P-type polysilicon layer, or a P-type microcrystalline silicon layer.
  • the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer, an N-type polysilicon layer, or an N-type microcrystalline silicon layer.
  • the embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:
  • An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
  • the method may further include: after depositing the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, Before the electrodes are formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer,
  • An electrode is then formed on the transparent conductive layer.
  • a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited
  • Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
  • a second P-type doped layer is deposited on the second intrinsic doped layer on the reverse side of the crystalline silicon substrate.
  • a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited
  • Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
  • a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited
  • Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
  • the method may further include: the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P Before the transparent conductive layer is deposited on the doped layer,
  • the method may further include: after depositing the first intrinsic doped layer and the second intrinsic doped layer on the front side and the back side of the crystalline silicon substrate, respectively, on the front side of the crystalline silicon substrate Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic doped layer, respectively depositing on the second intrinsic doped layer on the opposite side of the crystalline silicon substrate Before the two N-type doped layers and the second P-type doped layer,
  • masking the first intrinsic doped layer and the second intrinsic doped layer may include:
  • a mask or mask tape is disposed on the first intrinsic doped layer and the second intrinsic doped layer.
  • the method may further include: after forming an electrode on the transparent conductive layer,
  • the mask or the mask tape disposed on the first intrinsic doped layer and the second intrinsic doped layer is removed.
  • the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers
  • the first P-type doped layer and the second P-type doped layer are both a P-type amorphous silicon layer, a P-type polysilicon layer or a P-type microcrystalline silicon layer;
  • the first N-type doped layer and the second N-type doped layer may each be an N-type amorphous silicon layer, an N-type polysilicon layer or an N-type microcrystalline silicon layer.
  • the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers
  • the first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers;
  • Each of the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer.
  • the electrode may be formed by screen printing.
  • an embodiment of the present application provides a heterojunction solar cell including a crystalline silicon substrate 100, and a front surface of the crystalline silicon substrate 100 is provided with a first intrinsic amorphous silicon layer 110; A first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300 are disposed on the amorphous silicon layer 110; a first negative electrode 40 is disposed on the first N-type amorphous silicon layer 200, and the first P The first amorphous electrode 50 is disposed on the amorphous silicon layer 300; the second intrinsic amorphous silicon layer 120 is disposed on the reverse side of the crystalline silicon substrate 100; and the second N-type non-shaped is disposed on the second intrinsic amorphous silicon layer 120.
  • a crystalline silicon layer 400 and a second P-type amorphous silicon layer 500 a second negative electrode 70 disposed on the second N-type amorphous silicon layer 400, and a second positive electrode 60 disposed on the second P-type amorphous silicon layer 500 .
  • the front side and the back side of the crystalline silicon substrate 100 can respectively form a positive electrode and
  • the negative electrode is equivalent to forming two battery chips, that is, the first battery chip 10 and the second battery chip 20, on the same crystalline silicon substrate 100, as shown in FIG.
  • the first battery chip 10 and the second battery chip 20 can be independently powered, but the battery chip assembly composed of one crystalline silicon substrate 100 is generally used as a whole, so that the first battery chip 10 and the second battery chip 20 can be connected in series .
  • the positive electrode and the negative electrode are disposed on both the front side and the back side of the crystalline silicon substrate 100, only the small solder ribbon 30 is required to connect the positive electrode on the front side or the back side of the crystalline silicon substrate 100 to the negative electrode to achieve the first
  • the series connection of the battery chip 10 and the second battery chip 20 is as shown in FIG. If it is necessary to use two battery chip assemblies composed of two crystalline silicon substrates 100 in series, the second battery chip 20 on one battery chip assembly and the first battery chip 10 on the other battery chip assembly may be disposed in The position to be connected in series, since the polarity of the lower side of the second battery chip 20 in one battery chip assembly (as viewed in FIG. 2) is opposite to the polarity below the first battery chip 10 of another battery chip assembly to be connected in series Therefore, the second battery chip 20 on one battery chip assembly can be directly connected to the first battery chip 10 on the other battery chip assembly by the solder ribbon 30, as shown in FIG.
  • solder ribbons 30 are required to achieve a series connection of the two battery chip assemblies. Therefore, in the heterojunction solar cell provided by the embodiment of the present application, by providing a positive electrode and a negative electrode on both the front side and the back side of a crystalline silicon substrate 100, the adjacent two battery chip assemblies pass through the smaller solder ribbon 30. The series connection can be realized, and the solder ribbon 30 does not need to be bent, which solves the problem that the battery chip is chipped when it is used.
  • the drawings of the present application clearly show the various layer structures of the heterojunction solar cell, and the thicknesses of the layers in Figures 1 and 2 are not drawn to scale.
  • the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 are insulated from each other, and the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 are The insulation is arranged to prevent the N-type amorphous silicon layer and the P-type amorphous silicon layer on the front or back side of the crystalline silicon substrate 100 from sticking during the deposition process, thereby causing deposition precision at the adhesion and electronic movement difficult to control, affecting the conductive performance.
  • an insulator may be disposed between the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 to implement the first N-type amorphous silicon layer 200 and the first P-type. Insulation between the amorphous silicon layers 300; or separating the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 from each other to achieve the first N-type amorphous silicon layer 200 and The insulation between the first P-type amorphous silicon layer 300; the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 may also be separated by a distance by providing an insulator or separating the two To achieve insulation.
  • the positions of the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 on the front and back sides of the crystalline silicon substrate are Correspondingly, the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 are respectively located on the front side and the reverse side of the same first battery chip 10; the first P-type amorphous silicon The layer 300 and the second N-type amorphous silicon layer 400 correspond to positions on the front and back sides of the crystalline silicon substrate, that is, the first P-type amorphous silicon layer 300 and the second N-type amorphous silicon The layers 400 are respectively located on the front and back sides of the same first battery chip 20.
  • the edge of the first N-type amorphous silicon layer 200 and the edge of the second P-type amorphous silicon layer 500 may be aligned in a direction perpendicular to the crystalline silicon substrate 100.
  • the edge of the first P-type amorphous silicon layer 300 and the edge of the second N-type amorphous silicon layer 400 may be aligned in a direction perpendicular to the crystalline silicon substrate 100, thereby avoiding aligning the end faces of the amorphous silicon layer, and subsequently
  • the laser cutting process is required to perform the cutting process of the amorphous silicon layer, thereby ensuring the alignment of the edges of the film during the deposition process, eliminating the need for cutting the edge by the subsequent laser cutting process, simplifying the process, and improving the battery chip. Yield.
  • the first battery chip 10 and the second battery chip 20 are connected in series, since the first battery chip 10 is above (as shown in FIG.
  • the first negative electrode 40, the second battery chip Above the 20 is a first positive electrode 50, whereby the first negative electrode 40 and the first positive electrode 50 can be connected by the solder ribbon 30 to realize the series connection of the first battery chip 10 and the second battery chip 20;
  • the second positive electrode 60 below the battery chip 10 and the second negative electrode 70 below the second battery chip 20 are connected to realize the series connection of the first battery chip 10 and the second battery chip 20.
  • the second negative electrode 70 and the other battery under the second battery chip 20 on the bottom of one battery chip assembly (as shown in FIG. 2) may be used.
  • the second positive electrode 60 under the first battery chip 10 on the chip assembly is electrically connected by the solder ribbon 30, whereby the series connection of the two battery chip assemblies can be achieved.
  • the heterojunction solar cell may further include a first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300. a first transparent conductive layer 600; and a second transparent conductive layer 700 disposed on the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500.
  • the first negative electrode 40 and the first positive electrode 50 are both disposed on the first transparent conductive layer 600; the second negative electrode 70 and the second positive electrode 60 are both disposed on the second transparent conductive layer 700.
  • the first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each be formed by screen printing.
  • the first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each include a thin gate line and a main gate line.
  • both the fine gate line and the main gate line are deposited on the transparent conductive layer, wherein the fine gate line is for receiving the light excited by the electron and the external output current, and the fine gate line is transparent
  • the distribution on the conductive layer is relatively dense, and the diameter of the single fine grid line is generally 20 ⁇ to 60 ⁇ m. In the embodiment of the present application, the diameter of the single fine grid line may be 35 ⁇ m to increase the distribution density of the fine grid lines and increase the output. Current.
  • the current output is realized by the main gate line, and the number of the main gate lines is generally 2 to 6.
  • the combination of the main gate line and the fine gate line is enhanced. Intensity, the number of main grid lines can be four.
  • the solder ribbon 30 can be soldered only on the main gate line, thereby requiring only a smaller size solder ribbon 30 to achieve the connection of the main gate lines on the adjacent two battery chips, thereby reducing the resistance of the solder ribbon 30. Improve the conversion efficiency of photovoltaic modules.
  • the embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:
  • the crystalline silicon layer can be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the N-type amorphous silicon layer and the P-type amorphous silicon layer are respectively deposited on the front side and the reverse side of the crystalline silicon substrate, so that the front and back sides of the crystalline silicon substrate respectively have Positive and negative electrodes.
  • the series connection can be realized by the soldering strip only on the same side of the two battery chip assemblies, and the size of the soldering strip can be effectively reduced, thereby reducing the two battery chips.
  • the series resistance of the assembly; in addition, the welding strip does not need to be bent, thereby solving the problem that the welding strip is bent and easily causes chipping.
  • the deposition of the N-type amorphous silicon layer and the P-type amorphous silicon layer may all be in the same deposition chamber, but the parameters such as temperature and pressure during the deposition process are generally different if the front surface of the crystalline silicon substrate is deposited first.
  • the first N-type amorphous silicon layer and the first P-type amorphous silicon layer after depositing the first N-type amorphous silicon layer, before depositing the first P-type amorphous silicon layer, it is necessary to readjust the deposition chamber Various parameters to meet the deposition requirements of the first P-type amorphous silicon layer; then, when depositing the second N-type amorphous silicon layer and the second P-type amorphous silicon layer on the reverse side of the crystalline silicon substrate, it is necessary to adjust again Various parameters in the chamber are deposited to meet the deposition requirements of the second N-type amorphous silicon layer. Repeating the adjustment of the parameters of the deposition chamber may cause errors in the adjustment of the deposition parameters, thereby affecting the deposition precision of the film layer.
  • step S200 may include:
  • deposition parameters of the first N-type amorphous silicon layer and the second N-type amorphous silicon layer may be the same, and deposition parameters of the first P-type amorphous silicon layer and the second P-type amorphous silicon layer It can also be the same.
  • the deposition of the second N-type amorphous silicon layer before the deposition of the first P-type amorphous silicon layer, only one adjustment of each parameter in the deposition chamber is required, thereby achieving two N-type non-
  • the deposition of the crystalline silicon layer and the two P-type amorphous silicon layers enhances the deposition efficiency while ensuring the consistency of the deposition parameters of the two N-type amorphous silicon layers and the deposition parameters of the two P-type amorphous silicon layers. The consistency ensures the accuracy of film deposition.
  • step S200 may further include:
  • a second P-type amorphous silicon layer is deposited on a region of the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate for depositing the second P-type amorphous silicon layer.
  • the method may further include: after step S200, before step S300,
  • the method may further include: after step S100, before step S200,
  • the intrinsic amorphous silicon layer and the N, P-type amorphous silicon layer are easily deposited on the side of the crystalline silicon substrate. Therefore, after deposition of each film layer, a film removal process is usually employed to eliminate the side of the battery chip.
  • the film layer avoids the side conduction phenomenon of the battery chip.
  • the side edges of the battery chip are usually cut or polished by a laser process or a manual sanding process to insulate the sides of the battery chip.
  • the laser cutting process has high requirements on the equipment for realizing the process, and the cost is high, and when cutting, the cutting size can not be too small for convenient operation, which may reduce the effective area of the battery chip and reduce The power generation efficiency, and the manual grinding process requires experienced personnel to operate, otherwise it will easily cause the battery to rupture.
  • the first intrinsic amorphous silicon layer and the second portion may be deposited before depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • the amorphous silicon layer is masked to shield the area where the film layer is not required to be deposited, thereby completely solving the problem of deposition of the film layer to the non-deposited area, and also eliminating the film removing process, thereby effectively improving the preparation of the battery chip. effectiveness.
  • Step S110 may include:
  • a mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, and the mask or mask tape may be placed on the film layer during the masking operation.
  • the position of the film can be deposited, which ensures the accuracy of the deposition position of the film layer, and is also convenient for personnel operation.
  • the mask or mask tape when a mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, the mask or mask tape may be placed in the first A portion other than a region on the amorphous silicon layer and the second intrinsic amorphous silicon layer for depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer.
  • the method may further include: after step S200, before step S300, in order to prevent the transparent conductive layer from being deposited on the side of the two N-type amorphous silicon layers or the two P-type amorphous silicon layers.
  • the method may further include: after step S400,
  • a mask or mask tape disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is removed to complete the preparation of the battery chip.
  • the heterojunction solar cell and the preparation method thereof are provided by the embodiments of the present application, and the positive electrode and the negative electrode are disposed on the front and back sides of a crystalline silicon substrate, so that the adjacent two battery chip assemblies can be realized by a small solder ribbon.
  • the series connection reduces the series resistance, improves the photoelectric conversion efficiency, and the solder ribbon does not need to be bent, thereby solving the problem that the battery chip is broken during use.
  • the deposition of the upper film layer to the edge of the underlying film layer is avoided, thereby eliminating the risk of damage to the battery chip by the film removal process, and effectively improving the preparation efficiency of the battery chip.

Abstract

Provided are a heterojunction solar cell and a method for fabrication thereof; said cell comprises a crystalline silicon substrate, the front side of the crystalline silicon substrate is provided with a first intrinsic layer; the first intrinsic layer is provided with a first n-type doped layer and a first p-type doped layer; the first n-type doped layer is provided with a first negative electrode, and the first p-type doped layer is provided with a first positive electrode; the reverse side of the crystalline silicon substrate is provided with a second intrinsic layer; the second intrinsic layer is provided with a second n-type doped layer and a second p-type doped layer; the second n-type doped layer is provided with a second negative electrode, and the second p-type doped layer is provided with a second positive electrode.

Description

异质结太阳能电池及其制备方法Heterojunction solar cell and preparation method thereof 技术领域Technical field
本申请涉及但不限于太阳能电池技术领域，尤其涉及但不限于一种异质结太阳能电池及其制备方法。The present application relates to, but is not limited to, the field of solar cell technology, and in particular, but not limited to, a heterojunction solar cell and a method of fabricating the same.
背景技术Background technique
硅基异质结太阳能电池具有优异的发电性能。现有硅基异质结太阳能电池通常由多个电池芯片串联组成，而相邻电池芯片之间则通过焊带实现串联。Silicon-based heterojunction solar cells have excellent power generation performance. Existing silicon-based heterojunction solar cells are usually composed of a plurality of battery chips connected in series, and adjacent battery chips are connected in series by a solder ribbon.
发明概述Summary of invention
以下是对本文详细描述主题的概述。本概述并非是为了限制权利要求的保护范围。The following is an overview of the topics detailed in this article. This Summary is not intended to limit the scope of the claims.
本申请提供了一种异质结太阳能电池，所述异质结太阳能电池包括：The application provides a heterojunction solar cell, the heterojunction solar cell comprising:
晶硅基底；Crystalline silicon substrate;
所述晶硅基底的正面设置有第一本征层；The front surface of the crystalline silicon substrate is provided with a first intrinsic layer;
所述第一本征层上设置有第一N型掺杂层和第一P型掺杂层；所述第一N型掺杂层上设置有第一负电极，所述第一P型掺杂层上设置有第一正电极；a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;
所述晶硅基底的反面设置有第二本征层；a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate;
所述第二本征层上设置有第二N型掺杂层和第二P型掺杂层；所述第二N型掺杂层上设置有第二负电极，所述第二P型掺杂层上设置有第二正电极。a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
本申请提供了一种异质结太阳能电池的制备方法，所述方法包括如下步骤：The present application provides a method for preparing a heterojunction solar cell, the method comprising the following steps:
在晶硅基底的正面和反面分别沉积第一本征层和第二本征层；Depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate;
在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层；Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second intrinsic on the opposite side of the crystalline silicon substrate Depositing a second N-type doped layer and a second P-type doped layer on the layer;
在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上形成电极。An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
在阅读并理解了附图和详细描述后，可以明白其他方面。Other aspects will be apparent upon reading and understanding the drawings and detailed description.
附图概述BRIEF abstract
附图用来提供对本申请技术方案的进一步理解，并且构成说明书的一部分，与本申请的实施例一起用于解释本申请的技术方案，并不构成对本申请技术方案的限制。The drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, which is used together with the embodiments of the present application to explain the technical solutions of the present application, and does not constitute a limitation of the technical solutions of the present application.
图1为本申请实施例提供的异质结太阳能电池的结构示意图；1 is a schematic structural view of a heterojunction solar cell according to an embodiment of the present application;
图2为两个本申请实施例提供的异质结太阳能电池在串联时的示意图；2 is a schematic view of two heterojunction solar cells provided in an embodiment of the present application in series;
图3为本申请实施例提供的异质结太阳能电池的制备方法的流程图。3 is a flow chart of a method for preparing a heterojunction solar cell according to an embodiment of the present application.
附图标记说明：Description of the reference signs:
10-第一电池芯片         20-第二电池芯片10-first battery chip 20-second battery chip
30-焊带                 100-晶硅基底30-weld tape 100-crystalline silicon substrate
110-第一本征非晶硅层    120-第二本征非晶硅层110-first intrinsic amorphous silicon layer 120-second intrinsic amorphous silicon layer
200-第一N型非晶硅层     300-第一P型非晶硅层200-first N-type amorphous silicon layer 300-first P-type amorphous silicon layer
400-第二N型非晶硅层     500-第二P型非晶硅层400-second N-type amorphous silicon layer 500-second P-type amorphous silicon layer
600-第一透明导电层      700-第二透明导电层600-first transparent conductive layer 700-second transparent conductive layer
40-第一负电极           50-第一正电极40-first negative electrode 50-first positive electrode
60-第二正电极           70-第二负电极60-second positive electrode 70-second negative electrode
详述Detailed
下面详细描述本申请的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似 功能的元件。下面通过参考附图描述的实施例是示例性的，仅用于解释本申请，而不能解释为对本申请的限制。The embodiments of the present application are described in detail below, and the examples of the embodiments are illustrated in the drawings, wherein the same or similar reference numerals are used to refer to the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are intended to be illustrative only, and are not to be construed as limiting.
由于现有电池芯片上的正负极分别设置在电池芯片的正面和反面，当相邻两个电池芯片排列后，一个电池芯片的正极处于电池芯片的上方，另一个电池芯片的负极处于电池芯片的下方，当需要通过焊带串联两个电池芯片时，焊带的一端需要与一个电池芯片的正极连接，而焊带的另一端需要与电池芯片的负极连接，那么焊带在两个电池芯片之间的位置可能会发生弯折，极易导致电池芯片的碎裂；而为了能够连接两个电池芯片上相反的两极，焊带的尺寸要求较长，这无疑增加了焊带的电阻，导致组装后的异质结太阳能电池的发电能力减弱。Since the positive and negative electrodes on the existing battery chip are respectively disposed on the front and back sides of the battery chip, when two adjacent battery chips are arranged, the positive electrode of one battery chip is above the battery chip, and the negative electrode of the other battery chip is at the battery chip. Below, when two battery chips need to be connected in series by a solder ribbon, one end of the solder ribbon needs to be connected to the positive pole of one battery chip, and the other end of the solder ribbon needs to be connected to the negative pole of the battery chip, then the solder ribbon is on the two battery chips. The position may be bent, which may easily cause chipping of the battery chip; and in order to be able to connect the opposite poles on the two battery chips, the size of the ribbon is required to be long, which undoubtedly increases the resistance of the ribbon, resulting in The power generation capacity of the assembled heterojunction solar cell is weakened.
本申请实施例提供了一种异质结太阳能电池及其制备方法，减少了串联电阻，提高了光伏组件的转化效率。The embodiment of the present application provides a heterojunction solar cell and a preparation method thereof, which reduce the series resistance and improve the conversion efficiency of the photovoltaic module.
本申请实施例提供了一种异质结太阳能电池，所述异质结太阳能电池包括：The embodiment of the present application provides a heterojunction solar cell, and the heterojunction solar cell includes:
晶硅基底；Crystalline silicon substrate;
所述晶硅基底的正面设置有第一本征层；The front surface of the crystalline silicon substrate is provided with a first intrinsic layer;
所述第一本征层上设置有第一N型掺杂层和第一P型掺杂层；所述第一N型掺杂层上设置有第一负电极，所述第一P型掺杂层上设置有第一正电极；a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;
所述晶硅基底的反面设置有第二本征层；a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate;
所述第二本征层上设置有第二N型掺杂层和第二P型掺杂层；所述第二N型掺杂层上设置有第二负电极，所述第二P型掺杂层上设置有第二正电极。a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
在本申请实施例中，所述第一N型掺杂层和所述第一P型掺杂层之间可以绝缘设置；所述第二N型掺杂层和第二P型掺杂层之间可以绝缘设置。In the embodiment of the present application, the first N-type doped layer and the first P-type doped layer may be insulated from each other; the second N-type doped layer and the second P-type doped layer may be The insulation can be set between the two.
在本申请实施例中，所述第一N型掺杂层与所述第二P型掺杂层在晶硅基底的正面和反面的位置是对应的，所述第一P型掺杂层与所述第二N型掺杂层在晶硅基底的正面和反面的位置是对应的。In the embodiment of the present application, the first N-type doped layer and the second P-type doped layer correspond to positions on the front side and the back side of the crystalline silicon substrate, and the first P-type doped layer and The positions of the second N-type doped layer on the front and back sides of the crystalline silicon substrate are corresponding.
在本申请实施例中，所述异质结太阳能电池还可以包括：In the embodiment of the present application, the heterojunction solar cell may further include:
设置在所述第一N型掺杂层和所述第一P型掺杂层上的第一透明导电层；a first transparent conductive layer disposed on the first N-type doped layer and the first P-type doped layer;
设置在所述第二N型掺杂层和所述第二P型掺杂层上的第二透明导电层；a second transparent conductive layer disposed on the second N-type doped layer and the second P-type doped layer;
所述第一负电极和所述第一正电极均设置在所述第一透明导电层上；The first negative electrode and the first positive electrode are both disposed on the first transparent conductive layer;
所述第二负电极和所述第二正电极均设置在所述第二透明导电层上。The second negative electrode and the second positive electrode are both disposed on the second transparent conductive layer.
在本申请实施例中，所述第一负电极和所述第一正电极之间或所述第二负电极和所述第二正电极之间可以通过焊带连接。In an embodiment of the present application, the first negative electrode and the first positive electrode or between the second negative electrode and the second positive electrode may be connected by a solder ribbon.
在本申请实施例中，所述第一N型掺杂层的边缘与所述第二P型掺杂层的边缘可以在垂直于所述晶硅基底的方向上对齐；所述第一P型掺杂层的边缘与所述第二N型掺杂层的边缘可以在垂直于所述晶硅基底的方向上对齐。In an embodiment of the present application, an edge of the first N-type doping layer and an edge of the second P-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate; the first P-type The edges of the doped layer and the edges of the second N-type doped layer may be aligned in a direction perpendicular to the crystalline silicon substrate.
在本申请实施例中，所述第一正电极、所述第一负电极、所述第二正电极和所述第二负电极可以均包括细栅线和主栅线。In an embodiment of the present application, the first positive electrode, the first negative electrode, the second positive electrode, and the second negative electrode may each include a fine gate line and a main gate line.
在本申请实施例中，所述细栅线的直径的范围值可以为20μ至60μm。In the embodiment of the present application, the diameter of the fine grid line may range from 20 μ to 60 μm.
在本申请实施例中，任选地，所述主栅线的数量为2根至6根。In the embodiment of the present application, optionally, the number of the main gate lines is 2 to 6.
在本申请实施例中，所述第一本征层和第二本征层可为本征非晶硅层。In the embodiment of the present application, the first intrinsic layer and the second intrinsic layer may be intrinsic amorphous silicon layers.
在本申请实施例中，所述第一P型掺杂层和第二P型掺杂层可为P型非晶硅层、P型多晶硅层或P型微晶硅层。In the embodiment of the present application, the first P-type doped layer and the second P-type doped layer may be a P-type amorphous silicon layer, a P-type polysilicon layer, or a P-type microcrystalline silicon layer.
在本申请实施例中，第一N型掺杂层和第二N型掺杂层可为N型非晶硅层、N型多晶硅层或N型微晶硅层。In the embodiment of the present application, the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer, an N-type polysilicon layer, or an N-type microcrystalline silicon layer.
本申请实施例还提供了一种异质结太阳能电池的制备方法，所述方法包括如下步骤：The embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:
在晶硅基底的正面和反面分别沉积第一本征层和第二本征层；Depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate;
在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层；Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second intrinsic on the opposite side of the crystalline silicon substrate Depositing a second N-type doped layer and a second P-type doped layer on the layer;
在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂 层和所述第二P型掺杂层上形成电极。An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
在本申请实施例中，所述方法还可以包括：在沉积第一N型掺杂层、第一P型掺杂层、第二N型掺杂层和第二P型掺杂层之后，在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上形成电极之前，In an embodiment of the present application, the method may further include: after depositing the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, Before the electrodes are formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer,
在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上分别沉积透明导电层；Depositing a transparent conductive layer on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, respectively;
然后在所述透明导电层上形成电极。An electrode is then formed on the transparent conductive layer.
在本申请实施例中，在所述晶硅基底的正面的所述第一本征掺杂层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征掺杂层上分别沉积第二N型掺杂层和第二P型掺杂层可以包括：In the embodiment of the present application, a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
在所述晶硅基底的正面的所述第一本征掺杂层上沉积第一N型掺杂层；Depositing a first N-type doped layer on the first intrinsic doped layer of the front side of the crystalline silicon substrate;
在所述晶硅基底的反面的所述第二本征掺杂层上沉积第二N型掺杂层；Depositing a second N-type doped layer on the second intrinsic doped layer on the reverse side of the crystalline silicon substrate;
在所述晶硅基底的正面的所述第一本征掺杂层上沉积第一P型掺杂层；Depositing a first P-type doped layer on the first intrinsic doped layer of the front side of the crystalline silicon substrate;
在所述晶硅基底的反面的所述第二本征掺杂层上沉积第二P型掺杂层。A second P-type doped layer is deposited on the second intrinsic doped layer on the reverse side of the crystalline silicon substrate.
在本申请实施例中，在所述晶硅基底的正面的所述第一本征掺杂层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征掺杂层上分别沉积第二N型掺杂层和第二P型掺杂层可以包括：In the embodiment of the present application, a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
对所述晶硅基底的正面的所述第一本征掺杂层上用于沉积所述第一N型掺杂层的区域以外的部分进行掩膜；Masking a portion of the first intrinsic doped layer on the front surface of the crystalline silicon substrate other than the region for depositing the first N-type doped layer;
在所述晶硅基底的正面的所述第一本征掺杂层上用于沉积所述第一N型掺杂层的区域上沉积所述第一N型掺杂层；Depositing the first N-type doped layer on a region of the first intrinsic doped layer on the front side of the crystalline silicon substrate for depositing the first N-type doped layer;
对所述晶硅基底的反面的所述第二本征掺杂层上用于沉积所述第二 N型掺杂层的区域以外的部分进行掩膜；Masking a portion of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second N-type doped layer;
在所述晶硅基底的反面的所述第二本征掺杂层上用于沉积所述第二N型掺杂层的区域上沉积所述第二N型掺杂层；Depositing the second N-type doped layer on a region of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate for depositing the second N-type doped layer;
对所述晶硅基底的正面的所述第一本征掺杂层上用于沉积所述第一P型掺杂层的区域以外的部分进行掩膜；Masking a portion of the first intrinsic doped layer on the front surface of the crystalline silicon substrate other than the region for depositing the first P-type doped layer;
在所述晶硅基底的正面的所述第一本征掺杂层上用于沉积所述第一P型掺杂层的区域上沉积所述第一P型掺杂层；Depositing the first P-type doped layer on a region of the first intrinsic doped layer on the front side of the crystalline silicon substrate for depositing the first P-type doped layer;
对所述晶硅基底的反面的所述第二本征掺杂层上用于沉积所述第二P型掺杂层的区域以外的部分进行掩膜；Masking a portion of the second intrinsic doped layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second P-type doped layer;
在所述晶硅基底的反面的所述第二本征掺杂层上用于沉积所述第二P型掺杂层的区域上沉积所述第二P型掺杂层。Depositing the second P-type doped layer on a region of the second intrinsic doped layer on the reverse side of the crystalline silicon substrate for depositing the second P-type doped layer.
在本申请实施例中，在所述晶硅基底的正面的所述第一本征掺杂层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征掺杂层上分别沉积第二N型掺杂层和第二P型掺杂层可以包括：In the embodiment of the present application, a first N-type doped layer and a first P-type doped layer are respectively deposited on the first intrinsic doped layer on the front surface of the crystalline silicon substrate, where the crystalline silicon substrate is deposited Depositing the second N-type doped layer and the second P-type doped layer respectively on the second intrinsic doped layer on the reverse side may include:
在所述晶硅基底的正面的所述第一本征掺杂层和所述晶硅基底的反面的所述第二本征掺杂层的对应位置处分别沉积第一N型掺杂层和第二P型掺杂层；Depositing a first N-type doped layer at a corresponding position of the first intrinsic doped layer on the front side of the crystalline silicon substrate and the second intrinsic doped layer on the opposite side of the crystalline silicon substrate, respectively a second P-type doped layer;
在所述晶硅基底的正面的所述第一本征掺杂层和所述晶硅基底的反面的所述第二本征掺杂层的对应位置处分别沉积第一P型掺杂层与所述第二N型掺杂层。Depositing a first P-type doped layer at a corresponding position of the first intrinsic doped layer on the front side of the crystalline silicon substrate and the second intrinsic doped layer on the opposite side of the crystalline silicon substrate The second N-type doped layer.
在本申请实施例中，所述方法还可以包括：在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上分别沉积透明导电层之前，In an embodiment of the present application, the method may further include: the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P Before the transparent conductive layer is deposited on the doped layer,
对所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层以外的区域进行掩膜。Masking a region other than the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
在本申请实施例中，所述方法还可以包括：在晶硅基底的正面和反面分别沉积第一本征掺杂层和第二本征掺杂层之后，在所述晶硅基底的正面的所述第一本征掺杂层上分别沉积第一N型掺杂层和第一P型掺杂层， 在所述晶硅基底的反面的所述第二本征掺杂层上分别沉积第二N型掺杂层和第二P型掺杂层之前，In an embodiment of the present application, the method may further include: after depositing the first intrinsic doped layer and the second intrinsic doped layer on the front side and the back side of the crystalline silicon substrate, respectively, on the front side of the crystalline silicon substrate Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic doped layer, respectively depositing on the second intrinsic doped layer on the opposite side of the crystalline silicon substrate Before the two N-type doped layers and the second P-type doped layer,
对所述第一本征掺杂层和所述第二本征掺杂层进行掩膜。Masking the first intrinsic doped layer and the second intrinsic doped layer.
在本申请实施例中，对所述第一本征掺杂层和所述第二本征掺杂层进行掩膜可以包括：In the embodiment of the present application, masking the first intrinsic doped layer and the second intrinsic doped layer may include:
在所述第一本征掺杂层和所述第二本征掺杂层上设置掩膜版或掩膜胶带。A mask or mask tape is disposed on the first intrinsic doped layer and the second intrinsic doped layer.
在本申请实施例中，所述方法还可以包括：在所述透明导电层上形成电极之后，In an embodiment of the present application, the method may further include: after forming an electrode on the transparent conductive layer,
取走设置在所述第一本征掺杂层和所述第二本征掺杂层上的所述掩膜版或所述掩膜胶带。The mask or the mask tape disposed on the first intrinsic doped layer and the second intrinsic doped layer is removed.
在本申请实施例中，所述方法中所述第一本征层和所述第二本征层均为本征非晶硅层；In the embodiment of the present application, the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers;
所述第一P型掺杂层和所述第二P型掺杂层均为P型非晶硅层、P型多晶硅层或P型微晶硅层；和The first P-type doped layer and the second P-type doped layer are both a P-type amorphous silicon layer, a P-type polysilicon layer or a P-type microcrystalline silicon layer;
所述第一N型掺杂层和所述第二N型掺杂层均可为N型非晶硅层、N型多晶硅层或N型微晶硅层。The first N-type doped layer and the second N-type doped layer may each be an N-type amorphous silicon layer, an N-type polysilicon layer or an N-type microcrystalline silicon layer.
在本申请实施例中，所述方法中所述第一本征层和所述第二本征层均为本征非晶硅层；In the embodiment of the present application, the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers;
所述第一P型掺杂层和所述第二P型掺杂层均为P型非晶硅层；和The first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers;
所述第一N型掺杂层和所述第二N型掺杂层均可为N型非晶硅层。Each of the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer.
在本申请实施例中，可以通过丝网印刷形成所述电极。In the embodiment of the present application, the electrode may be formed by screen printing.
请参照图1和图2，本申请实施例提供了一种异质结太阳能电池，其包括晶硅基底100，晶硅基底100的正面设置有第一本征非晶硅层110；第一本征非晶硅层110上设置有第一N型非晶硅层200和第一P型非晶硅层300；第一N型非晶硅层200上设置有第一负电极40，第一P型非晶硅层300上设置有第一正电极50；晶硅基底100的反面设置有第二本征非晶硅层120；第二本征非晶硅层120上设置有第二N型非晶硅层400 和第二P型非晶硅层500；第二N型非晶硅层400上设置有第二负电极70，第二P型非晶硅层500上设置有第二正电极60。Referring to FIG. 1 and FIG. 2, an embodiment of the present application provides a heterojunction solar cell including a crystalline silicon substrate 100, and a front surface of the crystalline silicon substrate 100 is provided with a first intrinsic amorphous silicon layer 110; A first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300 are disposed on the amorphous silicon layer 110; a first negative electrode 40 is disposed on the first N-type amorphous silicon layer 200, and the first P The first amorphous electrode 50 is disposed on the amorphous silicon layer 300; the second intrinsic amorphous silicon layer 120 is disposed on the reverse side of the crystalline silicon substrate 100; and the second N-type non-shaped is disposed on the second intrinsic amorphous silicon layer 120. a crystalline silicon layer 400 and a second P-type amorphous silicon layer 500; a second negative electrode 70 disposed on the second N-type amorphous silicon layer 400, and a second positive electrode 60 disposed on the second P-type amorphous silicon layer 500 .
在本申请实施例中，通过在晶硅基底100的正面和反面均分别沉积N型非晶硅层和P型非晶硅层，使得晶硅基底100的正面和反面均能够分别形成正电极和负电极，相当于在同一个晶硅基底100上形成了两个电池芯片，即第一电池芯片10和第二电池芯片20，如图1所示。第一电池芯片10和第二电池芯片20可以独立供电，但由一个晶硅基底100构成的电池芯片总成通常作为一个整体使用，故第一电池芯片10和第二电池芯片20之间可以串联。由于在晶硅基底100的正面和反面均设置有正电极和负电极，故仅需较小的焊带30即可将晶硅基底100正面或反面的正电极与负电极相连，以实现第一电池芯片10和第二电池芯片20的串联，如图2所示。若需要将两个晶硅基底100构成的两个电池芯片总成串联使用，可以使一个电池芯片总成上的第二电池芯片20和另一个电池芯片总成上的第一电池芯片10设置在待串联的位置，由于一个电池芯片总成中的第二电池芯片20下方(如图2视角)的极性与与待串联的另一个电池芯片总成的第一电池芯片10下方的极性相反，故可以通过焊带30直接将一个电池芯片总成上的第二电池芯片20与另一个电池芯片总成上的第一电池芯片10相连，如图2所示。In the embodiment of the present application, by depositing an N-type amorphous silicon layer and a P-type amorphous silicon layer on the front side and the back side of the crystalline silicon substrate 100, respectively, the front side and the back side of the crystalline silicon substrate 100 can respectively form a positive electrode and The negative electrode is equivalent to forming two battery chips, that is, the first battery chip 10 and the second battery chip 20, on the same crystalline silicon substrate 100, as shown in FIG. The first battery chip 10 and the second battery chip 20 can be independently powered, but the battery chip assembly composed of one crystalline silicon substrate 100 is generally used as a whole, so that the first battery chip 10 and the second battery chip 20 can be connected in series . Since the positive electrode and the negative electrode are disposed on both the front side and the back side of the crystalline silicon substrate 100, only the small solder ribbon 30 is required to connect the positive electrode on the front side or the back side of the crystalline silicon substrate 100 to the negative electrode to achieve the first The series connection of the battery chip 10 and the second battery chip 20 is as shown in FIG. If it is necessary to use two battery chip assemblies composed of two crystalline silicon substrates 100 in series, the second battery chip 20 on one battery chip assembly and the first battery chip 10 on the other battery chip assembly may be disposed in The position to be connected in series, since the polarity of the lower side of the second battery chip 20 in one battery chip assembly (as viewed in FIG. 2) is opposite to the polarity below the first battery chip 10 of another battery chip assembly to be connected in series Therefore, the second battery chip 20 on one battery chip assembly can be directly connected to the first battery chip 10 on the other battery chip assembly by the solder ribbon 30, as shown in FIG.
由于两个电池芯片总成之间的距离较小，故仅需较小的焊带30即可实现两个电池芯片总成的串联。因此，本申请实施例提供的异质结太阳能电池，通过在一个晶硅基底100的正面和反面均设置正电极和负电极，使相邻两个电池芯片总成通过较小的焊带30即可实现串联，且焊带30无需弯折，解决了电池芯片在使用时发生碎裂的问题。Since the distance between the two battery chip assemblies is small, only a small number of solder ribbons 30 are required to achieve a series connection of the two battery chip assemblies. Therefore, in the heterojunction solar cell provided by the embodiment of the present application, by providing a positive electrode and a negative electrode on both the front side and the back side of a crystalline silicon substrate 100, the adjacent two battery chip assemblies pass through the smaller solder ribbon 30. The series connection can be realized, and the solder ribbon 30 does not need to be bent, which solves the problem that the battery chip is chipped when it is used.
本申请的附图清晰地示出了该异质结太阳能电池的各层结构，图1和图2中各层的厚度并不是按照比例绘制。如图1所示，第一N型非晶硅层200和第一P型非晶硅层300之间绝缘设置，第二N型非晶硅层400和第二P型非晶硅层500之间绝缘设置，从而可以防止晶硅基底100正面或反面的N型非晶硅层和P型非晶硅层在沉积过程中发生粘连，而导致粘连处的沉积精度以及电子运动难以控制，影响导电性能。The drawings of the present application clearly show the various layer structures of the heterojunction solar cell, and the thicknesses of the layers in Figures 1 and 2 are not drawn to scale. As shown in FIG. 1, the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 are insulated from each other, and the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 are The insulation is arranged to prevent the N-type amorphous silicon layer and the P-type amorphous silicon layer on the front or back side of the crystalline silicon substrate 100 from sticking during the deposition process, thereby causing deposition precision at the adhesion and electronic movement difficult to control, affecting the conductive performance.
在本申请实施例中，可以在第一N型非晶硅层200和第一P型非晶硅层300之间设置绝缘物，以实现第一N型非晶硅层200和第一P型非晶硅层300之间的绝缘性；或者使第一N型非晶硅层200和第一P型非晶硅层300相互分隔有一定距离，以实现第一N型非晶硅层200和第一P型非晶硅层300之间的绝缘性；第二N型非晶硅层400和第二P型非晶硅层500之间也可以通过设置绝缘物或者使两者相互分离一定距离来实现绝缘性。In the embodiment of the present application, an insulator may be disposed between the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 to implement the first N-type amorphous silicon layer 200 and the first P-type. Insulation between the amorphous silicon layers 300; or separating the first N-type amorphous silicon layer 200 and the first P-type amorphous silicon layer 300 from each other to achieve the first N-type amorphous silicon layer 200 and The insulation between the first P-type amorphous silicon layer 300; the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500 may also be separated by a distance by providing an insulator or separating the two To achieve insulation.
如图1和图2所示，在本申请实施例中，所述第一N型非晶硅层200与所述第二P型非晶硅层500在晶硅基底的正面和反面的位置是对应的，即所述第一N型非晶硅层200与所述第二P型非晶硅层500分别位于同一个第一电池芯片10的正面和反面；所述第一P型非晶硅层300与所述第二N型非晶硅层400在晶硅基底的正面和反面的位置是对应的，即所述第一P型非晶硅层300与所述第二N型非晶硅层400分别位于同一个第一电池芯片20的正面和反面。As shown in FIG. 1 and FIG. 2, in the embodiment of the present application, the positions of the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 on the front and back sides of the crystalline silicon substrate are Correspondingly, the first N-type amorphous silicon layer 200 and the second P-type amorphous silicon layer 500 are respectively located on the front side and the reverse side of the same first battery chip 10; the first P-type amorphous silicon The layer 300 and the second N-type amorphous silicon layer 400 correspond to positions on the front and back sides of the crystalline silicon substrate, that is, the first P-type amorphous silicon layer 300 and the second N-type amorphous silicon The layers 400 are respectively located on the front and back sides of the same first battery chip 20.
为了简化加工工艺，降低生产成本，如图1所示，第一N型非晶硅层200的边缘与第二P型非晶硅层500的边缘可以在垂直于晶硅基底100的方向上对齐，第一P型非晶硅层300的边缘与第二N型非晶硅层400的边缘可以在垂直于晶硅基底100的方向上对齐，避免了若不将非晶硅层端面对齐，后续需要激光切割工艺进行非晶硅层的裁切工序，由此，可以在沉积过程中保证膜层边缘对齐，无需通过后续的激光裁切工艺对边缘进行裁切，简化了工艺，提高了电池芯片的良率。对于同一个电池芯片总成而言，在第一电池芯片10和第二电池芯片20串联时，由于第一电池芯片10的上方(如图1视角)为第一负电极40，第二电池芯片20的上方为第一正电极50，由此可以通过焊带30将第一负电极40和第一正电极50相连，以实现串联第一电池芯片10和第二电池芯片20；或者，将第一电池芯片10下方的第二正电极60和第二电池芯片20下方的第二负电极70相连，以实现串联第一电池芯片10和第二电池芯片20。而在将两个电池芯片总成进行串联时，如图2所示，可以将一个电池芯片总成上的第二电池芯片20下方(如图2视角)的第二负电极70与另一个电池芯片总成上的 第一电池芯片10下方的第二正电极60通过焊带30电连接，由此可以实现两个电池芯片总成的串联。In order to simplify the processing process and reduce the production cost, as shown in FIG. 1, the edge of the first N-type amorphous silicon layer 200 and the edge of the second P-type amorphous silicon layer 500 may be aligned in a direction perpendicular to the crystalline silicon substrate 100. The edge of the first P-type amorphous silicon layer 300 and the edge of the second N-type amorphous silicon layer 400 may be aligned in a direction perpendicular to the crystalline silicon substrate 100, thereby avoiding aligning the end faces of the amorphous silicon layer, and subsequently The laser cutting process is required to perform the cutting process of the amorphous silicon layer, thereby ensuring the alignment of the edges of the film during the deposition process, eliminating the need for cutting the edge by the subsequent laser cutting process, simplifying the process, and improving the battery chip. Yield. For the same battery chip assembly, when the first battery chip 10 and the second battery chip 20 are connected in series, since the first battery chip 10 is above (as shown in FIG. 1), the first negative electrode 40, the second battery chip Above the 20 is a first positive electrode 50, whereby the first negative electrode 40 and the first positive electrode 50 can be connected by the solder ribbon 30 to realize the series connection of the first battery chip 10 and the second battery chip 20; The second positive electrode 60 below the battery chip 10 and the second negative electrode 70 below the second battery chip 20 are connected to realize the series connection of the first battery chip 10 and the second battery chip 20. When the two battery chip assemblies are connected in series, as shown in FIG. 2, the second negative electrode 70 and the other battery under the second battery chip 20 on the bottom of one battery chip assembly (as shown in FIG. 2) may be used. The second positive electrode 60 under the first battery chip 10 on the chip assembly is electrically connected by the solder ribbon 30, whereby the series connection of the two battery chip assemblies can be achieved.
如图1所示，为了增强该异质结太阳能电池的导电性能，该异质结太阳能电池还可以包括设置在第一N型非晶硅层200和第一P型非晶硅层300上的第一透明导电层600；以及设置在第二N型非晶硅层400和第二P型非晶硅层500上的第二透明导电层700。第一负电极40和第一正电极50均设置在第一透明导电层600上；第二负电极70和第二正电极60均设置在第二透明导电层700上。As shown in FIG. 1 , in order to enhance the conductivity of the heterojunction solar cell, the heterojunction solar cell may further include a first N-type amorphous silicon layer 200 and a first P-type amorphous silicon layer 300. a first transparent conductive layer 600; and a second transparent conductive layer 700 disposed on the second N-type amorphous silicon layer 400 and the second P-type amorphous silicon layer 500. The first negative electrode 40 and the first positive electrode 50 are both disposed on the first transparent conductive layer 600; the second negative electrode 70 and the second positive electrode 60 are both disposed on the second transparent conductive layer 700.
所述第一正电极50、所述第一负电极40、所述第二正电极60和所述第二负电极70均可以通过丝网印刷形成。The first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each be formed by screen printing.
第一正电极50、第一负电极40、第二正电极60和第二负电极70均可以包括细栅线和主栅线。在通过丝网印刷形成银栅线的过程中，细栅线和主栅线均沉积在透明导电层上，其中细栅线用以接收光激发的电子和对外输出的电流，细栅线在透明导电层上的分布较为密集，单根细栅线的直径一般为20μ至60μm，在本申请实施例中，单根细栅线的直径可以为35μm，以增大细栅线分布密度，提高输出的电流。将电流输出是通过主栅线来实现，主栅线的数量一般为2根至6根，在本申请实施例中，为了避免银浆料的浪费，同时增强主栅线和细栅线的结合强度，主栅线的数量可以为4根。The first positive electrode 50, the first negative electrode 40, the second positive electrode 60, and the second negative electrode 70 may each include a thin gate line and a main gate line. In the process of forming a silver gate line by screen printing, both the fine gate line and the main gate line are deposited on the transparent conductive layer, wherein the fine gate line is for receiving the light excited by the electron and the external output current, and the fine gate line is transparent The distribution on the conductive layer is relatively dense, and the diameter of the single fine grid line is generally 20 μ to 60 μm. In the embodiment of the present application, the diameter of the single fine grid line may be 35 μm to increase the distribution density of the fine grid lines and increase the output. Current. The current output is realized by the main gate line, and the number of the main gate lines is generally 2 to 6. In the embodiment of the present application, in order to avoid waste of the silver paste, the combination of the main gate line and the fine gate line is enhanced. Intensity, the number of main grid lines can be four.
焊带30可以仅焊接在主栅线上，由此仅需要较小尺寸的焊带30即可实现相邻两个电池芯片上的主栅线的连接，进而减小了焊带30的电阻，提高了光伏组件的转化效率。The solder ribbon 30 can be soldered only on the main gate line, thereby requiring only a smaller size solder ribbon 30 to achieve the connection of the main gate lines on the adjacent two battery chips, thereby reducing the resistance of the solder ribbon 30. Improve the conversion efficiency of photovoltaic modules.
如图3所示，本申请实施例还提供了一种异质结太阳能电池的制备方法，所述方法包括如下步骤：As shown in FIG. 3, the embodiment of the present application further provides a method for preparing a heterojunction solar cell, and the method includes the following steps:
S100、在晶硅基底的正面和反面分别沉积第一本征非晶硅层和第二本征非晶硅层。S100, depositing a first intrinsic amorphous silicon layer and a second intrinsic amorphous silicon layer on the front side and the back side of the crystalline silicon substrate, respectively.
S200、在晶硅基底的正面的第一本征非晶硅层上分别沉积第一N型非晶硅层和第一P型非晶硅层，在晶硅基底的反面的第二本征非晶硅层上分别沉积第二N型非晶硅层和第二P型非晶硅层。S200, depositing a first N-type amorphous silicon layer and a first P-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate, respectively, and a second intrinsic non-positive surface on the opposite side of the crystalline silicon substrate A second N-type amorphous silicon layer and a second P-type amorphous silicon layer are respectively deposited on the crystalline silicon layer.
第一本征非晶硅层、第二本征非晶硅层、第一N型非晶硅层、第一P型非晶硅层、第二N型非晶硅层以及第二P型非晶硅层均可以采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)技术进行沉积。a first intrinsic amorphous silicon layer, a second intrinsic amorphous silicon layer, a first N-type amorphous silicon layer, a first P-type amorphous silicon layer, a second N-type amorphous silicon layer, and a second P-type non- The crystalline silicon layer can be deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD).
S300、在第一N型非晶硅层、第一P型非晶硅层、第二N型非晶硅层和第二P型非晶硅层上分别沉积透明导电层。S300, respectively depositing a transparent conductive layer on the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer.
S400、在透明导电层上通过丝网印刷形成电极。S400, forming an electrode by screen printing on the transparent conductive layer.
本申请实施例提供的异质结太阳能电池中，通过在晶硅基底的正面和反面均分别沉积N型非晶硅层和P型非晶硅层，使晶硅基底的正反两面均分别具有正极和负极。当两个电池芯片总成通过焊带串联时，仅在两个电池芯片总成的同一侧即可通过焊带实现串联，且焊带的尺寸可以有效减小，进而减小了两个电池芯片总成的串联电阻；此外，焊带无需弯折，从而解决了因焊带弯折而易导致发生碎裂的问题。In the heterojunction solar cell provided by the embodiment of the present application, the N-type amorphous silicon layer and the P-type amorphous silicon layer are respectively deposited on the front side and the reverse side of the crystalline silicon substrate, so that the front and back sides of the crystalline silicon substrate respectively have Positive and negative electrodes. When the two battery chip assemblies are connected in series by the soldering strip, the series connection can be realized by the soldering strip only on the same side of the two battery chip assemblies, and the size of the soldering strip can be effectively reduced, thereby reducing the two battery chips. The series resistance of the assembly; in addition, the welding strip does not need to be bent, thereby solving the problem that the welding strip is bent and easily causes chipping.
N型非晶硅层和P型非晶硅层的沉积均可以在同一个沉积腔室中，但是两者在沉积过程中的温度、压力等参数一般不同，如果先沉积晶硅基底的正面的第一N型非晶硅层和第一P型非晶硅层，那么在沉积第一N型非晶硅层后，在沉积第一P型非晶硅层前，需要重新调整沉积腔室中的各个参数，以满足对第一P型非晶硅层的沉积要求；然后在沉积晶硅基底的反面的第二N型非晶硅层和第二P型非晶硅层时，需要再次调整沉积腔室中的各个参数，以满足第二N型非晶硅层的沉积要求。如此反复调整沉积腔室的参数，易导致沉积参数的调节出现误差，进而影响膜层的沉积精度。The deposition of the N-type amorphous silicon layer and the P-type amorphous silicon layer may all be in the same deposition chamber, but the parameters such as temperature and pressure during the deposition process are generally different if the front surface of the crystalline silicon substrate is deposited first. The first N-type amorphous silicon layer and the first P-type amorphous silicon layer, after depositing the first N-type amorphous silicon layer, before depositing the first P-type amorphous silicon layer, it is necessary to readjust the deposition chamber Various parameters to meet the deposition requirements of the first P-type amorphous silicon layer; then, when depositing the second N-type amorphous silicon layer and the second P-type amorphous silicon layer on the reverse side of the crystalline silicon substrate, it is necessary to adjust again Various parameters in the chamber are deposited to meet the deposition requirements of the second N-type amorphous silicon layer. Repeating the adjustment of the parameters of the deposition chamber may cause errors in the adjustment of the deposition parameters, thereby affecting the deposition precision of the film layer.
因此，在本申请实施例中，步骤S200可以包括：Therefore, in the embodiment of the present application, step S200 may include:
S210、在晶硅基底的正面的第一本征非晶硅层上沉积第一N型非晶硅层。S210, depositing a first N-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate.
S220、在晶硅基底的反面的第二本征非晶硅层上沉积第二N型非晶硅层。S220, depositing a second N-type amorphous silicon layer on the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate.
S230、在晶硅基底的正面的第一本征非晶硅层上沉积第一P型非晶硅层。S230, depositing a first P-type amorphous silicon layer on the first intrinsic amorphous silicon layer on the front surface of the crystalline silicon substrate.
S240、在晶硅基底的反面的第二本征非晶硅层上沉积第二P型非晶硅层。S240, depositing a second P-type amorphous silicon layer on the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate.
在步骤S210至S240中，第一N型非晶硅层和第二N型非晶硅层的沉积参数可以相同，第一P型非晶硅层和第二P型非晶硅层的沉积参数也可以相同。由此，在第二N型非晶硅层沉积之后，在第一P型非晶硅层沉积前，仅需对沉积腔室中的各参数进行一次调整，即可实现对两个N型非晶硅层和两个P型非晶硅层的沉积，提升了沉积效率，同时可以保证两个N型非晶硅层的沉积参数的一致性，以及两个P型非晶硅层的沉积参数的一致性，进而保证了膜层沉积的精度。In steps S210 to S240, deposition parameters of the first N-type amorphous silicon layer and the second N-type amorphous silicon layer may be the same, and deposition parameters of the first P-type amorphous silicon layer and the second P-type amorphous silicon layer It can also be the same. Therefore, after the deposition of the second N-type amorphous silicon layer, before the deposition of the first P-type amorphous silicon layer, only one adjustment of each parameter in the deposition chamber is required, thereby achieving two N-type non- The deposition of the crystalline silicon layer and the two P-type amorphous silicon layers enhances the deposition efficiency while ensuring the consistency of the deposition parameters of the two N-type amorphous silicon layers and the deposition parameters of the two P-type amorphous silicon layers. The consistency ensures the accuracy of film deposition.
在本申请实施例中，步骤S200还可以包括：In the embodiment of the present application, step S200 may further include:
对晶硅基底的正面的第一本征非晶硅层上用于沉积第一N型非晶硅层的区域以外的部分进行掩膜，由此可以避免在沉积第一N型非晶硅层时将第一N型非晶硅层沉积到其它区域；Masking a portion of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first N-type amorphous silicon layer, thereby preventing deposition of the first N-type amorphous silicon layer Depositing a first N-type amorphous silicon layer to other regions;
在晶硅基底的正面的第一本征非晶硅层上用于沉积第一N型非晶硅层的区域上沉积第一N型非晶硅层；Depositing a first N-type amorphous silicon layer on a region of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first N-type amorphous silicon layer;
对晶硅基底的反面的第二本征非晶硅层上用于沉积第二N型非晶硅层的区域以外的部分进行掩膜，由此可以避免在沉积第二N型非晶硅层时将第二N型非晶硅层沉积到其它区域；Masking a portion of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second N-type amorphous silicon layer, thereby preventing deposition of the second N-type amorphous silicon layer Depositing a second N-type amorphous silicon layer to other regions;
在晶硅基底的反面的第二本征非晶硅层上用于沉积第二N型非晶硅层的区域上沉积第二N型非晶硅层；Depositing a second N-type amorphous silicon layer on a region of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second N-type amorphous silicon layer;
对晶硅基底的正面的第一本征非晶硅层上用于沉积第一P型非晶硅层的区域以外的部分进行掩膜，由此可以避免在沉积第一P型非晶硅层时将第一P型非晶硅层沉积到其它区域，避免将第一P型非晶硅层沉积到第一N型非晶硅层上；Masking a portion of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate other than the region for depositing the first P-type amorphous silicon layer, thereby preventing deposition of the first P-type amorphous silicon layer Depositing the first P-type amorphous silicon layer to other regions to avoid depositing the first P-type amorphous silicon layer on the first N-type amorphous silicon layer;
在晶硅基底的正面的第一本征非晶硅层上用于沉积第一P型非晶硅层的区域沉积上第一P型非晶硅层；Depositing a first P-type amorphous silicon layer on a region of the first intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate for depositing the first P-type amorphous silicon layer;
对晶硅基底的反面的第二本征非晶硅层上用于沉积第二P型非晶硅层的区域以外的部分进行掩膜，由此可以避免在沉积第二P型非晶硅层时将第二P型非晶硅层沉积到其它区域，避免将第二P型非晶硅层沉积到第 二N型非晶硅层上；以及Masking a portion of the second intrinsic amorphous silicon layer on the opposite side of the crystalline silicon substrate for depositing the second P-type amorphous silicon layer, thereby preventing deposition of the second P-type amorphous silicon layer Depositing a second P-type amorphous silicon layer to other regions to avoid depositing a second P-type amorphous silicon layer on the second N-type amorphous silicon layer;
在晶硅基底的反面的第二本征非晶硅层上用于沉积第二P型非晶硅层的区域上沉积第二P型非晶硅层。A second P-type amorphous silicon layer is deposited on a region of the second intrinsic amorphous silicon layer on the reverse side of the crystalline silicon substrate for depositing the second P-type amorphous silicon layer.
在本申请实施例中，所述方法还可以包括：在步骤S200之后，步骤S300之前，In the embodiment of the present application, the method may further include: after step S200, before step S300,
对第一N型非晶硅层、第一P型非晶硅层、第二N型非晶硅层和第二P型非晶硅层以外的区域进行掩膜，以防止透明导电层沉积到各个N型和P型非晶硅层以外的区域，影响异质结太阳能电池的光电转换性能。Masking a region other than the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer to prevent deposition of the transparent conductive layer The regions other than the respective N-type and P-type amorphous silicon layers affect the photoelectric conversion performance of the heterojunction solar cell.
在本申请实施例中，所述方法还可以包括：在步骤S100之后，步骤S200之前，In the embodiment of the present application, the method may further include: after step S100, before step S200,
S110、对第一本征非晶硅层和第二本征非晶硅层进行掩膜。S110, masking the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer.
在沉积过程中，本征非晶硅层及N、P型非晶硅层易沉积到晶硅基底的侧面，因此，在各膜层均沉积完成后，通常采用除膜工艺以消除电池芯片侧面的膜层，避免电池芯片侧面导电现象。为了达到上述效果，通常会采用激光工艺或手动打磨工艺对电池芯片的侧面边缘进行裁切或打磨，以使电池芯片的侧面绝缘。但是，激光裁切工艺对实现该工艺的设备具有较高的要求，成本较高，且裁切时，为了方便操作，裁切尺寸不能太小，从而可能会减小电池芯片的有效面积，降低了发电效率，而手动打磨工艺需要经验丰富人员操作，否则容易导致电池片破裂。During the deposition process, the intrinsic amorphous silicon layer and the N, P-type amorphous silicon layer are easily deposited on the side of the crystalline silicon substrate. Therefore, after deposition of each film layer, a film removal process is usually employed to eliminate the side of the battery chip. The film layer avoids the side conduction phenomenon of the battery chip. In order to achieve the above effects, the side edges of the battery chip are usually cut or polished by a laser process or a manual sanding process to insulate the sides of the battery chip. However, the laser cutting process has high requirements on the equipment for realizing the process, and the cost is high, and when cutting, the cutting size can not be too small for convenient operation, which may reduce the effective area of the battery chip and reduce The power generation efficiency, and the manual grinding process requires experienced personnel to operate, otherwise it will easily cause the battery to rupture.
因此，在本申请实施例提供的异质结太阳能电池的制备方法中，可以在沉积N型非晶硅层和P型非晶硅层之前，对第一本征非晶硅层和第二本征非晶硅层进行掩膜，对不需要沉积膜层的区域进行遮挡，由此彻底解决了膜层沉积到非沉积区域的问题，同时也取消了除膜工艺，有效提高了电池芯片的制备效率。Therefore, in the method for fabricating a heterojunction solar cell provided by the embodiment of the present application, the first intrinsic amorphous silicon layer and the second portion may be deposited before depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer. The amorphous silicon layer is masked to shield the area where the film layer is not required to be deposited, thereby completely solving the problem of deposition of the film layer to the non-deposited area, and also eliminating the film removing process, thereby effectively improving the preparation of the battery chip. effectiveness.
步骤S110可以包括：Step S110 may include:
在第一本征非晶硅层和第二本征非晶硅层上设置掩膜版或掩膜胶带，在进行掩膜操作时，可以将掩膜版或掩膜胶带放置到膜层上设定的位置，然后可以进行膜层的沉积，保证了膜层沉积位置的精确性，同时也方便了人员操作。A mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, and the mask or mask tape may be placed on the film layer during the masking operation. The position of the film can be deposited, which ensures the accuracy of the deposition position of the film layer, and is also convenient for personnel operation.
在本申请实施例中，在第一本征非晶硅层和第二本征非晶硅层上设置掩膜版或掩膜胶带时，可以将掩膜版或掩膜胶带放置到第一本征非晶硅层和第二本征非晶硅层上用于沉积N型非晶硅层和P型非晶硅层的区域以外的部分。In the embodiment of the present application, when a mask or mask tape is disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer, the mask or mask tape may be placed in the first A portion other than a region on the amorphous silicon layer and the second intrinsic amorphous silicon layer for depositing the N-type amorphous silicon layer and the P-type amorphous silicon layer.
为了防止透明导电层沉积到两个N型非晶硅层或两个P型非晶硅层的侧面，在本申请实施例中，所述方法还可以包括：在步骤S200之后，步骤S300之前，In the embodiment of the present application, the method may further include: after step S200, before step S300, in order to prevent the transparent conductive layer from being deposited on the side of the two N-type amorphous silicon layers or the two P-type amorphous silicon layers.
S30、对第一N型非晶硅层、第一P型非晶硅层、第二N型非晶硅层和第二P型非晶硅层进行掩膜。S30, masking the first N-type amorphous silicon layer, the first P-type amorphous silicon layer, the second N-type amorphous silicon layer, and the second P-type amorphous silicon layer.
在本申请实施例中，所述方法还可以包括：在步骤S400之后，In the embodiment of the present application, the method may further include: after step S400,
取走设置在所述第一本征非晶硅层和所述第二本征非晶硅层上的掩膜版或掩膜胶带，以完成电池芯片的制备。A mask or mask tape disposed on the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer is removed to complete the preparation of the battery chip.
本申请实施例提供的异质结太阳能电池及其制备方法，通过在一个晶硅基底的正面和反面均设置正极和负极，使相邻两个电池芯片总成通过较小的焊带即可实现串联，减小了串联电阻，提升了光电转化效率，且焊带无需弯折，解决了电池芯片在使用时发生碎裂的问题。另外，通过在膜层沉积前进行掩膜，避免了上层膜层沉积到下层膜层的边缘，由此消除了除膜工艺对电池芯片造成损伤的风险，有效提高了电池芯片的制备效率。The heterojunction solar cell and the preparation method thereof are provided by the embodiments of the present application, and the positive electrode and the negative electrode are disposed on the front and back sides of a crystalline silicon substrate, so that the adjacent two battery chip assemblies can be realized by a small solder ribbon. The series connection reduces the series resistance, improves the photoelectric conversion efficiency, and the solder ribbon does not need to be bent, thereby solving the problem that the battery chip is broken during use. In addition, by masking before deposition of the film layer, the deposition of the upper film layer to the edge of the underlying film layer is avoided, thereby eliminating the risk of damage to the battery chip by the film removal process, and effectively improving the preparation efficiency of the battery chip.
本公开内容是本申请实施例的原则的示例，并非对本申请作出任何形式上或实质上的限定，或将本申请限定到具体的实施方案。对本领域的技术人员而言，很显然本申请实施例的技术方案的要素、方法和***等，可以进行变动、改变、改动、演变，而不背离如上所述的本申请的实施例、技术方案的，如权利要求中所定义的原理、精神和范围。这些变动、改变、改动、演变的实施方案均包括在本申请的等同实施例内，这些等同实施例均包括在本申请的由权利要求界定的范围内。虽然可以许多不同形式来使本申请实施例具体化，但此处详细描述的是本申请的一些实施方案。此外，本申请的实施例包括此处所述的各种实施方案的一些或全部的任意可能的组合，也包括在本申请的由权利要求界定的范围内。在本申请中或在任一个引用的专利、引用的专利申请或其它引用的资料中任何地方所提及的所有专利、专利申请和 其它引用资料据此通过引用以其整体并入。The disclosure is an exemplification of the principles of the embodiments of the present application, and is not intended to limit the scope of the present application. It is obvious to those skilled in the art that the elements, methods, systems, and the like of the technical solutions of the embodiments of the present application can be changed, changed, modified, and evolved without departing from the embodiments and technical solutions of the present application as described above. The principles, spirit and scope as defined in the claims. The implementations of the present invention are intended to be included within the scope of the present invention as defined by the appended claims. While the embodiments of the present application can be embodied in many different forms, the embodiments of the present application are described in detail herein. Furthermore, the embodiments of the present application include any possible combinations of some or all of the various embodiments described herein, and are included within the scope of the claims as defined by the claims. All of the patents, patent applications, and other references cited in this application, or in the entirety of each of the entire entire entire entire entire entire entire entire entire entire entire entireties
以上公开内容规定为说明性的而不是穷尽性的。对于本领域技术人员来说，本说明书会暗示许多变化和可选择方案。所有这些可选择方案和变化旨在被包括在本权利要求的范围内，其中术语“包括”意思是“包括，但不限于”。在此完成了对本申请可选择的实施方案的描述。本领域技术人员可认识到此处所述的实施方案的其它等效变换，这些等效变换也为由附于本文的权利要求所包括。The above disclosure is intended to be illustrative rather than exhaustive. This description will suggest many variations and alternatives to those skilled in the art. All such alternatives and modifications are intended to be included within the scope of the claims, wherein the term "comprising" means "including, but not limited to." A description of alternative embodiments of the present application is completed herein. Other equivalents to the embodiments described herein will be recognized by those skilled in the art, and these equivalents are also included in the claims appended hereto.

Claims (24)

  1. 一种异质结太阳能电池，所述异质结太阳能电池包括：A heterojunction solar cell, the heterojunction solar cell comprising:
    晶硅基底；Crystalline silicon substrate;
    所述晶硅基底的正面设置有第一本征层；The front surface of the crystalline silicon substrate is provided with a first intrinsic layer;
    所述第一本征层上设置有第一N型掺杂层和第一P型掺杂层；所述第一N型掺杂层上设置有第一负电极，所述第一P型掺杂层上设置有第一正电极；a first N-type doped layer and a first P-type doped layer are disposed on the first intrinsic layer; a first negative electrode is disposed on the first N-type doped layer, and the first P-type doped a first positive electrode is disposed on the impurity layer;
    所述晶硅基底的反面设置有第二本征层；a second intrinsic layer is disposed on a reverse side of the crystalline silicon substrate;
    所述第二本征层上设置有第二N型掺杂层和第二P型掺杂层；所述第二N型掺杂层上设置有第二负电极，所述第二P型掺杂层上设置有第二正电极。a second N-type doped layer and a second P-type doped layer are disposed on the second intrinsic layer; a second negative electrode is disposed on the second N-type doped layer, and the second P-type doped A second positive electrode is disposed on the hybrid layer.
  2. 根据权利要求1所述的异质结太阳能电池，其中，所述第一N型掺杂层和所述第一P型掺杂层之间绝缘设置；所述第二N型掺杂层和所述第二P型掺杂层之间绝缘设置。The heterojunction solar cell according to claim 1, wherein said first N-type doped layer and said first P-type doped layer are insulated from each other; said second N-type doped layer and said An insulating arrangement between the second P-type doped layers is described.
  3. 根据权利要求1或2所述的异质结太阳能电池，其中，所述第一N型掺杂层与所述第二P型掺杂层在晶硅基底的正面和反面的位置是对应的，所述第一P型掺杂层与所述第二N型掺杂层在晶硅基底的正面和反面的位置是对应的。The heterojunction solar cell according to claim 1 or 2, wherein the positions of the first N-type doped layer and the second P-type doped layer on the front and back sides of the crystalline silicon substrate are corresponding, The positions of the first P-type doped layer and the second N-type doped layer on the front and back sides of the crystalline silicon substrate correspond.
  4. 根据权利要求1至3中任一项所述的异质结太阳能电池，所述异质结太阳能电池还包括：The heterojunction solar cell according to any one of claims 1 to 3, further comprising:
    设置在所述第一N型掺杂层和所述第一P型掺杂层上的第一透明导电层；a first transparent conductive layer disposed on the first N-type doped layer and the first P-type doped layer;
    设置在所述第二N型掺杂层和所述第二P型掺杂层上的第二透明导电层；a second transparent conductive layer disposed on the second N-type doped layer and the second P-type doped layer;
    所述第一负电极和所述第一正电极均设置在所述第一透明导电层上；The first negative electrode and the first positive electrode are both disposed on the first transparent conductive layer;
    所述第二负电极和所述第二正电极均设置在所述第二透明导电层上。The second negative electrode and the second positive electrode are both disposed on the second transparent conductive layer.
  5. 根据权利要求1至4中任一项所述的异质结太阳能电池，其中，所述第一负电极和所述第一正电极之间或所述第二负电极和所述第二正 电极之间通过焊带连接。The heterojunction solar cell according to any one of claims 1 to 4, wherein the first negative electrode and the first positive electrode or the second negative electrode and the second positive electrode Connected by a solder ribbon.
  6. 根据权利要求1至5中任一项所述的异质结太阳能电池，其中，所述第一N型掺杂层的边缘与所述第二P型掺杂层的边缘在垂直于所述晶硅基底的方向上对齐；所述第一P型掺杂层的边缘与所述第二N型掺杂层的边缘在垂直于所述晶硅基底的方向上对齐。The heterojunction solar cell according to any one of claims 1 to 5, wherein an edge of the first N-type doping layer and an edge of the second P-type doped layer are perpendicular to the crystal The silicon substrate is aligned in a direction; an edge of the first P-type doped layer is aligned with an edge of the second N-type doped layer in a direction perpendicular to the crystalline silicon substrate.
  7. 根据权利要求1至6中任一项所述的异质结太阳能电池，其中，所述第一正电极、所述第一负电极、所述第二正电极和所述第二负电极均包括细栅线和主栅线。The heterojunction solar cell according to any one of claims 1 to 6, wherein the first positive electrode, the first negative electrode, the second positive electrode, and the second negative electrode are each included Fine gate line and main gate line.
  8. 根据权利要求7所述的异质结太阳能电池，其中，所述细栅线的直径的范围值为20μ至60μm。The heterojunction solar cell according to claim 7, wherein the fine gate line has a diameter ranging from 20 μ to 60 μm.
  9. 根据权利要求7或8所述的异质结太阳能电池，其中，所述主栅线的数量为2根至6根。The heterojunction solar cell according to claim 7 or 8, wherein the number of the main gate lines is 2 to 6.
  10. 根据权利要求1至9中任一项所述的异质结太阳能电池，其中，所述第一本征层和所述第二本征层均为本征非晶硅层。The heterojunction solar cell according to any one of claims 1 to 9, wherein the first intrinsic layer and the second intrinsic layer are both intrinsic amorphous silicon layers.
  11. 根据权利要求1至10中任一项所述的异质结太阳能电池，其中，所述第一P型掺杂层和所述第二P型掺杂层均为P型非晶硅层、P型多晶硅层或P型微晶硅层。The heterojunction solar cell according to any one of claims 1 to 10, wherein the first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers, P Type polysilicon layer or P type microcrystalline silicon layer.
  12. 根据权利要求1至11中任一项所述的异质结太阳能电池，其中，所述第一N型掺杂层和所述第二N型掺杂层均为N型非晶硅层、N型多晶硅层或N型微晶硅层。The heterojunction solar cell according to any one of claims 1 to 11, wherein the first N-type doped layer and the second N-type doped layer are both N-type amorphous silicon layers, N A type of polysilicon layer or an N type microcrystalline silicon layer.
  13. 一种异质结太阳能电池的制备方法，所述方法包括如下步骤：A method of preparing a heterojunction solar cell, the method comprising the steps of:
    在晶硅基底的正面和反面分别沉积第一本征层和第二本征层；Depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate;
    在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层；Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second intrinsic on the opposite side of the crystalline silicon substrate Depositing a second N-type doped layer and a second P-type doped layer on the layer;
    在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上形成电极。An electrode is formed on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
  14. 根据权利要求13所述的异质结太阳能电池的制备方法，所述方法还包括：在沉积所述第一N型掺杂层、所述第一P型掺杂层、所述第 二N型掺杂层和所述第二P型掺杂层之后，在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上形成电极之前，The method of fabricating a heterojunction solar cell according to claim 13, further comprising: depositing said first N-type doped layer, said first P-type doped layer, said second N-type After the doped layer and the second P-type doped layer, the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second Before forming an electrode on the P-type doped layer,
    在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上分别沉积透明导电层；Depositing a transparent conductive layer on the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer, respectively;
    然后在所述透明导电层上形成电极。An electrode is then formed on the transparent conductive layer.
  15. 根据权利要求13或14所述的异质结太阳能电池的制备方法，其中，所述在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层包括：The method of fabricating a heterojunction solar cell according to claim 13 or 14, wherein the first N-type doped layer and the first layer are respectively deposited on the first intrinsic layer of the front surface of the crystalline silicon substrate a P-type doped layer, respectively depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate comprises:
    在所述晶硅基底的正面的所述第一本征层上沉积所述第一N型掺杂层；Depositing the first N-type doped layer on the first intrinsic layer of the front side of the crystalline silicon substrate;
    在所述晶硅基底的反面的所述第二本征层上沉积所述第二N型掺杂层；Depositing the second N-type doped layer on the second intrinsic layer on the reverse side of the crystalline silicon substrate;
    在所述晶硅基底的正面的所述第一本征层上沉积所述第一P型掺杂层；Depositing the first P-type doped layer on the first intrinsic layer of the front side of the crystalline silicon substrate;
    在所述晶硅基底的反面的所述第二本征层上沉积所述第二P型掺杂层。Depositing the second P-type doped layer on the second intrinsic layer on the reverse side of the crystalline silicon substrate.
  16. 根据权利要求13至15中任一项所述的异质结太阳能电池的制备方法，其中，所述在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层包括：The method of producing a heterojunction solar cell according to any one of claims 13 to 15, wherein said first N-type doping is deposited on said first intrinsic layer of a front surface of said crystalline silicon substrate And depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate, respectively:
    对所述晶硅基底的正面的所述第一本征层上用于沉积所述第一N型掺杂层的区域以外的部分进行掩膜；Masking a portion of the first intrinsic layer of the front surface of the crystalline silicon substrate other than the region for depositing the first N-type doped layer;
    在所述晶硅基底的正面的所述第一本征层上用于沉积所述第一N型掺杂层的区域上沉积所述第一N型掺杂层；Depositing the first N-type doped layer on a region of the first intrinsic layer of the front side of the crystalline silicon substrate for depositing the first N-type doped layer;
    对所述晶硅基底的反面的所述第二本征层上用于沉积所述第二N型掺杂层的区域以外的部分进行掩膜；Masking a portion of the second intrinsic layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second N-type doped layer;
    在所述晶硅基底的反面的所述第二本征层上用于沉积所述第二N型 掺杂层的区域上沉积所述第二N型掺杂层；Depositing the second N-type doped layer on a region of the second intrinsic layer on the reverse side of the crystalline silicon substrate for depositing the second N-type doped layer;
    对所述晶硅基底的正面的所述第一本征层上用于沉积所述第一P型掺杂层的区域以外的部分进行掩膜；Masking a portion of the first intrinsic layer of the front surface of the crystalline silicon substrate other than the region for depositing the first P-type doped layer;
    在所述晶硅基底的正面的所述第一本征层上用于沉积所述第一P型掺杂层的区域上沉积所述第一P型掺杂层；Depositing the first P-type doped layer on a region of the first intrinsic layer of the front side of the crystalline silicon substrate for depositing the first P-type doped layer;
    对所述晶硅基底的反面的所述第二本征层上用于沉积所述第二P型掺杂层的区域以外的部分进行掩膜；Masking a portion of the second intrinsic layer on the opposite side of the crystalline silicon substrate other than the region for depositing the second P-type doped layer;
    在所述晶硅基底的反面的所述第二本征层上用于沉积所述第二P型掺杂层的区域上沉积所述第二P型掺杂层。Depositing the second P-type doped layer on a region of the second intrinsic layer on the reverse side of the crystalline silicon substrate for depositing the second P-type doped layer.
  17. 根据权利要求13至16中任一项所述的异质结太阳能电池的制备方法，其中，所述在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层包括：The method of producing a heterojunction solar cell according to any one of claims 13 to 16, wherein said first N-type doping is deposited on said first intrinsic layer of a front surface of said crystalline silicon substrate And depositing a second N-type doped layer and a second P-type doped layer on the second intrinsic layer on the opposite side of the crystalline silicon substrate, respectively:
    在所述晶硅基底的正面的所述第一本征层和所述晶硅基底的反面的所述第二本征层的对应位置处分别沉积第一N型掺杂层和第二P型掺杂层；Depositing a first N-type doped layer and a second P-type, respectively, at corresponding positions of the first intrinsic layer on the front side of the crystalline silicon substrate and the second intrinsic layer on the reverse side of the crystalline silicon substrate Doped layer
    在所述晶硅基底的正面的所述第一本征层和所述晶硅基底的反面的所述第二本征层的对应位置处分别沉积第一P型掺杂层与所述第二N型掺杂层。Depositing a first P-type doped layer and the second portion respectively at corresponding positions of the first intrinsic layer of the front surface of the crystalline silicon substrate and the second intrinsic layer of the reverse side of the crystalline silicon substrate N-type doped layer.
  18. 根据权利要求14至17中任一项所述的异质结太阳能电池的制备方法，所述方法还包括：在所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层上分别沉积透明导电层之前，The method of fabricating a heterojunction solar cell according to any one of claims 14 to 17, further comprising: said first N-type doped layer, said first P-type doped layer, said Before the transparent conductive layer is deposited on the second N-type doped layer and the second P-type doped layer, respectively.
    对所述第一N型掺杂层、所述第一P型掺杂层、所述第二N型掺杂层和所述第二P型掺杂层以外的区域进行掩膜。Masking a region other than the first N-type doped layer, the first P-type doped layer, the second N-type doped layer, and the second P-type doped layer.
  19. 根据权利要求13至18中任一项所述的异质结太阳能电池的制备方法，所述方法还包括：在晶硅基底的正面和反面分别沉积第一本征层和第二本征层之后，在所述晶硅基底的正面的所述第一本征层上分别沉积第一N型掺杂层和第一P型掺杂层，在所述晶硅基底的反面的所述第二本征层上分别沉积第二N型掺杂层和第二P型掺杂层之前，The method of producing a heterojunction solar cell according to any one of claims 13 to 18, further comprising: depositing a first intrinsic layer and a second intrinsic layer on the front side and the back side of the crystalline silicon substrate, respectively Depositing a first N-type doped layer and a first P-type doped layer on the first intrinsic layer of the front surface of the crystalline silicon substrate, the second portion on the reverse side of the crystalline silicon substrate Before depositing the second N-type doped layer and the second P-type doped layer respectively on the acquisition layer,
    对所述第一本征层和所述第二本征层进行掩膜。Masking the first intrinsic layer and the second intrinsic layer.
  20. 根据权利要求19所述的异质结太阳能电池的制备方法，其中，对所述第一本征层和所述第二本征层进行掩膜包括：The method of fabricating a heterojunction solar cell according to claim 19, wherein masking the first intrinsic layer and the second intrinsic layer comprises:
    在所述第一本征层和所述第二本征层上设置掩膜版或掩膜胶带。A mask or mask tape is disposed on the first intrinsic layer and the second intrinsic layer.
  21. 根据权利要求19或20所述的异质结太阳能电池的制备方法，所述方法还包括：在形成电极之后，The method of preparing a heterojunction solar cell according to claim 19 or 20, further comprising: after forming the electrode,
    取走设置在所述第一本征层和所述第二本征层上的所述掩膜版或所述掩膜胶带。The mask or the mask tape disposed on the first intrinsic layer and the second intrinsic layer is removed.
  22. 根据权利要求13至21中任一项所述的异质结太阳能电池的制备方法，其中，通过丝网印刷形成所述电极。The method of producing a heterojunction solar cell according to any one of claims 13 to 21, wherein the electrode is formed by screen printing.
  23. 根据权利要求13至22中任一项所述的异质结太阳能电池的制备方法，其中，所述第一本征层和所述第二本征层均为本征非晶硅层；The method for producing a heterojunction solar cell according to any one of claims 13 to 22, wherein the first intrinsic layer and the second intrinsic layer are intrinsic amorphous silicon layers;
    所述第一P型掺杂层和所述第二P型掺杂层均为P型非晶硅层、P型多晶硅层或P型微晶硅层；和The first P-type doped layer and the second P-type doped layer are both a P-type amorphous silicon layer, a P-type polysilicon layer or a P-type microcrystalline silicon layer;
    所述第一N型掺杂层和所述第二N型掺杂层均可为N型非晶硅层、N型多晶硅层或N型微晶硅层。The first N-type doped layer and the second N-type doped layer may each be an N-type amorphous silicon layer, an N-type polysilicon layer or an N-type microcrystalline silicon layer.
  24. 根据权利要求13至23中任一项所述的异质结太阳能电池的制备方法，其中，所述第一本征层和所述第二本征层均为本征非晶硅层；The method for producing a heterojunction solar cell according to any one of claims 13 to 23, wherein the first intrinsic layer and the second intrinsic layer are intrinsic amorphous silicon layers;
    所述第一P型掺杂层和所述第二P型掺杂层均为P型非晶硅层；和The first P-type doped layer and the second P-type doped layer are both P-type amorphous silicon layers;
    所述第一N型掺杂层和所述第二N型掺杂层均可为N型非晶硅层。Each of the first N-type doped layer and the second N-type doped layer may be an N-type amorphous silicon layer.
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Publication number Priority date Publication date Assignee Title
CN108110079A (en) * 2017-11-30 2018-06-01 君泰创新（北京）科技有限公司 Heterojunction solar battery and preparation method thereof
CN108963009B (en) * 2018-07-23 2020-04-03 英利能源（中国）有限公司 Preparation method of solar cell and solar cell module
CN109037375B (en) * 2018-07-23 2020-04-03 英利能源（中国）有限公司 Solar cell and solar cell module
CN111653643A (en) * 2020-06-19 2020-09-11 苏州大学 Heterojunction battery, preparation method and heterojunction battery assembly
CN113451439A (en) * 2021-06-09 2021-09-28 中威新能源(成都)有限公司 Heterojunction battery production method
CN113594278B (en) * 2021-09-28 2021-12-31 中国华能集团清洁能源技术研究院有限公司 Manufacturing method of internal series-connection type battery piece photovoltaic assembly and packaging structure
CN113594288B (en) * 2021-09-28 2021-12-21 中国华能集团清洁能源技术研究院有限公司 Internal series-connection type heterojunction battery and manufacturing method thereof
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601759A (en) * 2003-09-24 2005-03-30 三洋电机株式会社 Photovoltaic cell and method of fabricating the same
JP2013055294A (en) * 2011-09-06 2013-03-21 Mitsubishi Electric Corp Solar cell module and method of manufacturing the same
CN103199143A (en) * 2013-04-28 2013-07-10 常州天合光能有限公司 N-type hydrogen-doped crystalline silicon passivated heterojunction solar cell
CN205960005U (en) * 2016-08-23 2017-02-15 福建金石能源有限公司 Heterojunction solar cell
CN207441731U (en) * 2017-11-30 2018-06-01 君泰创新（北京）科技有限公司 Heterojunction solar battery
CN108110079A (en) * 2017-11-30 2018-06-01 君泰创新（北京）科技有限公司 Heterojunction solar battery and preparation method thereof

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1601759A (en) * 2003-09-24 2005-03-30 三洋电机株式会社 Photovoltaic cell and method of fabricating the same
JP2013055294A (en) * 2011-09-06 2013-03-21 Mitsubishi Electric Corp Solar cell module and method of manufacturing the same
CN103199143A (en) * 2013-04-28 2013-07-10 常州天合光能有限公司 N-type hydrogen-doped crystalline silicon passivated heterojunction solar cell
CN205960005U (en) * 2016-08-23 2017-02-15 福建金石能源有限公司 Heterojunction solar cell
CN207441731U (en) * 2017-11-30 2018-06-01 君泰创新（北京）科技有限公司 Heterojunction solar battery
CN108110079A (en) * 2017-11-30 2018-06-01 君泰创新（北京）科技有限公司 Heterojunction solar battery and preparation method thereof

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