WO2019098151A1 - Reflective liquid crystal display device - Google Patents

Reflective liquid crystal display device Download PDF

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Publication number
WO2019098151A1
WO2019098151A1 PCT/JP2018/041791 JP2018041791W WO2019098151A1 WO 2019098151 A1 WO2019098151 A1 WO 2019098151A1 JP 2018041791 W JP2018041791 W JP 2018041791W WO 2019098151 A1 WO2019098151 A1 WO 2019098151A1
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Prior art keywords
frame
electrode
liquid crystal
pixel
reflective
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PCT/JP2018/041791
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French (fr)
Japanese (ja)
Inventor
隆行 岩佐
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株式会社Ｊｖｃケンウッド
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Publication of WO2019098151A1 publication Critical patent/WO2019098151A1/en

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/302—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements characterised by the form or geometrical disposition of the individual elements

Definitions

  • the present invention relates to a reflective liquid crystal display device, and more particularly to a reflective liquid crystal display device suitable for improving the quality of black display.
  • a sub-frame driving method is known as one of the halftone display methods in liquid crystal display devices.
  • the sub-frame driving method which is a type of time-axis modulation method
  • a predetermined period for example, one frame which is a display unit of one image in the case of a moving image
  • the pixel is driven by the combination of the corresponding subframes.
  • the gradation to be displayed is determined by the ratio of the driving period of the pixel to the predetermined period, and this ratio is specified by the combination of subframes.
  • each pixel is configured by a master latch and a slave latch, a liquid crystal display element, and a plurality of switching transistors.
  • the first switching transistor when the first data of 1 bit is applied to the input terminal of the master latch through the first switching transistor and the row selection signal applied through the row scanning line becomes active, the first switching transistor is turned on. When turned on, the first data is written to the master latch.
  • each pixel can perform desired gray scale display by a combination of a plurality of subframes constituting one frame.
  • periods of a plurality of subframes constituting one frame are allocated in advance to the same or different predetermined periods. For example, in the case where maximum gradation display is performed (white is displayed) in each pixel, display is performed in all of a plurality of subframes constituting one frame, and minimum gradation display is performed (black is displayed). In the case of not performing display in all of the plurality of sub-frames constituting one frame, in the case of performing gradation display other than that, the subframe to be displayed is selected according to the gradation to be displayed.
  • a liquid crystal display device adopting this conventional method uses, as input data, digital data representing gradation, and also adopts a digital driving method of a two-stage latch configuration (see, for example, Patent Document 1).
  • the frame electrode of the frame portion provided so as to surround the outer periphery of the image display portion is considered to be a solid electrode, and the effect is that the image display portion is provided.
  • the level of black displayed by each pixel may be different from the level of black displayed by the frame portion. Therefore, there is a possibility that black displayed by the frame portion may be emphasized more black than black displayed by each pixel provided in the image display unit.
  • black displayed by the frame portion is overemphasized more than black displayed by the image display portion.
  • there is a problem that the quality of the image is degraded.
  • the present invention has been made in view of the above points, and an object thereof is to provide a reflective liquid crystal display device capable of improving the quality of black display.
  • the reflective liquid crystal display device is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. And a frame portion in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement areas partitioned in a matrix, and in each of the electrode arrangement areas, a reflective electrode of the pixels occupying each pixel arrangement area
  • the frame electrode is disposed such that the difference in area ratio is 5% or less based on the area ratio of.
  • the reflective liquid crystal display device is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. And a frame portion in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement areas partitioned in a matrix, and in each of the electrode arrangement areas, a reflective electrode of the pixels occupying each pixel arrangement area
  • the frame electrode is disposed such that the difference is within 30% of the peripheral length with respect to the peripheral length of the frame.
  • FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment. It is a circuit diagram which shows the specific structure of the pixel provided in the liquid crystal display device shown in FIG. It is a circuit diagram which shows the specific structure of the inverter which comprises the 1st data holding part provided in the pixel shown in FIG. It is a schematic sectional drawing of the pixel shown in FIG. It is a timing chart which shows operation
  • RMS voltage applied voltage
  • FIG. 7 is a schematic plan view of a reflective electrode of a pixel and a frame electrode provided in a liquid crystal display device according to Embodiment 2. It is a schematic sectional drawing of the reflective electrode of the pixel shown in FIG. 14, and a frame electrode. It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 14, and a frame electrode.
  • FIG. 18 is a schematic plan view of a reflective electrode of a pixel and a frame electrode provided in a liquid crystal display device according to a third embodiment.
  • FIG. 17 It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 17, and a frame electrode. It is a figure which shows the relationship of the difference of the perimeter length of each of a reflective electrode and a frame electrode, and the difference of the black level displayed by each of an image display part and a frame part.
  • FIG. 1 is a block diagram showing a reflective liquid crystal display device 10 according to the first embodiment.
  • the reflective liquid crystal display device 10 includes an image display unit 11, a timing generator 13, a vertical shift register 14, a data latch circuit 15, and a horizontal driver 16.
  • the horizontal driver 16 includes a horizontal shift register 161, a latch unit 162, and a level shifter / pixel driver 163.
  • the image display unit 11 has a plurality of pixels 12 regularly arranged in each of a plurality of pixel arrangement regions partitioned in a matrix.
  • the plurality of pixels 12 are connected to one end of the vertical shift register 14 and extend in the row direction (X direction) by m (m is a natural number of 2 or more) row scanning lines g1 to gm; Are arranged in a two-dimensional matrix at a plurality of intersections where n (n is a natural number of 2 or more) column data lines d1 to dn each having one end connected thereto and extending in the column direction (Y direction) It is done. All the pixels 12 in the image display unit 11 are commonly connected to trigger lines trig and trigb whose one ends are connected to the timing generator 13.
  • the timing generator 13 receives external signals such as the vertical synchronization signal Vst, the horizontal synchronization signal Hst, and the basic clock CLK output from the higher-level device 20 as input signals, and generates alternating current signals FR and V based on these external signals.
  • Various internal signals such as the start pulse VST, the H start pulse HST, the clock signals VCK and HCK, the latch pulse LT, and the trigger pulses TRI and TRIB are generated.
  • the alternating signal FR is a signal whose polarity is inverted every one sub-frame, and is supplied as a common electrode voltage Vcom to be described later to a common electrode of the liquid crystal display element in the pixel 12 constituting the image display unit 11.
  • the start pulse VST is a pulse signal that is output at the start timing of each subframe to be described later, and the switching of subframes is controlled by the start pulse VST.
  • the start pulse HST is a pulse signal output to the horizontal shift register 161 at the start timing of the horizontal shift register 161.
  • the clock signal VCK is a shift clock defining one horizontal scanning period (1H) in the vertical shift register 14.
  • the vertical shift register 14 performs a shift operation at the timing of the clock signal VCK.
  • the clock signal HCK is a shift clock in the horizontal shift register 161, and is a signal for shifting data with a 32-bit width.
  • the latch pulse LT is a pulse signal that is output at the timing when the horizontal shift register 161 has finished shifting the data for the number of pixels in one row in the horizontal direction.
  • the non-inverted trigger pulse TRI and the inverted trigger pulse TRIB are pulse signals supplied to all the pixels 12 in the image display unit 11 via the trigger lines trig and trigb, respectively.
  • the normal rotation trigger pulse TRI and the inversion trigger pulse TRIB are output from the timing generator 13 after data is written to the first data holding unit in all the pixels 12 in the image display unit 11 in a certain subframe period. Be done. As a result, in the sub-frame period, the data held in the first data holding units in all the pixels 12 in the image display unit 11 are simultaneously transferred to the second data holding units in the corresponding pixels 12. Ru.
  • Vertical shift register 14 transfers V start pulse VST supplied at the start timing of each sub-frame in accordance with clock signal VCK, and sequentially and exclusively supplies the row scanning signal to row scanning lines g1 to gm in 1 H units. .
  • the row scanning lines are sequentially selected one by one in units of 1H from the uppermost row scanning line g1 to the lowermost row scanning line gm of the image display unit 11.
  • Data latch circuit 15 latches 32-bit wide data in units of one subframe supplied from an external circuit (not shown) based on basic clock CLK from host device 20, and then horizontally shifts in synchronization with basic clock CLK. Output to the register 161.
  • the reflective liquid crystal display device 10 divides one frame of a video signal into a plurality of subframes having a display period shorter than one frame period of the video signal, and performs gradation display by a combination of these subframes. ing. Therefore, the above external circuit converts gradation data indicating the gradation of each pixel into a plurality of 1-bit subframe data corresponding to a plurality of subframes. Furthermore, the above external circuit collectively supplies subframe data for 32 pixels belonging to the same subframe to the data latch circuit 15 as data of 32 bits width.
  • the horizontal shift register 161 When viewed as a processing system of 1-bit serial data, the horizontal shift register 161 starts shifting by the start pulse HST supplied from the timing generator 13 at the initial stage of 1H, and data of 32-bit width supplied from the data latch circuit 15 In synchronization with the clock signal HCK.
  • the latch unit 162 synchronizes with the latch pulse LT supplied from the timing generator 13 when the horizontal shift register 161 finishes shifting data of n bits equal to the number n of pixels in one row of the image display unit 11.
  • Data of n bits supplied in parallel from the horizontal shift register 161 (that is, subframe data of n pixels) is latched and output to the level shifter of the level shifter / pixel driver 163.
  • the start pulse HST is output again from the timing generator 13, and the horizontal shift register 161 resumes the shift of 32-bit data from the data latch circuit 15 according to the clock signal HCK.
  • the level shifter of the level shifter / pixel driver 163 shifts the signal levels of n pieces of subframe data corresponding to n pixels in one row transferred from the latch unit 162 to the liquid crystal drive voltage amplitude.
  • the pixel driver of the level shifter / pixel driver 163 outputs n pieces of subframe data corresponding to n pixels in one row after level shift in parallel to n column data lines d1 to dn.
  • the horizontal driver 16 outputs the sub-frame data directed to the pixels of the row selected as the data writing target in one horizontal scanning period and the pixels of the row selected as the data writing target in the next one horizontal scanning period. Shifting of subframe data in parallel is performed. Then, in a horizontal scanning period, n sub-frame data corresponding to n pixels in one row are simultaneously output in parallel to n column data lines d1 to dn as data signals.
  • n pixels 12 in one row selected by the row scanning signal from the vertical shift register 14 among the plurality of pixels 12 constituting the image display unit 11 are one row output simultaneously from the level shifter / pixel driver 163.
  • a portion of n sub-frame data is sampled via n column data lines d1 to dn and written to a first data holding unit described later in each pixel 12.
  • inverted data of the input data held in the storage unit SM1 is applied to the reflective electrode PE. That is, the pixel 12 has a function of inverting input data supplied from the level shifter / pixel driver 163.
  • FIG. 2 is a circuit diagram showing a specific configuration of the pixel 12.
  • the pixel 12 may be any of row scan lines g1 to gm (hereinafter referred to as row scan line g) and any of column data lines d1 to dn (hereinafter referred to as column data line d). And are provided at the intersections where they intersect.
  • the pixel 12 includes an SRAM cell 201, a DRAM cell 202, and a liquid crystal display element LC.
  • the SRAM cell 201 is configured of a switch SW1 which is a first switch, and a storage unit SM1 which is a first data holding unit.
  • the DRAM cell 202 includes a switch SW2 which is a second switch, and a storage unit DM2 which is a second data holding unit.
  • the liquid crystal display element LC has a well-known structure in which a liquid crystal LCM is filled and sealed in a space between a reflective electrode PE which is a pixel electrode having light reflection characteristics and disposed to be separated and opposed, and a common electrode CE having light transparency. It is.
  • the switch SW1 is configured of, for example, an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) MN1.
  • NMOS transistor MN1 N-channel MOS transistor
  • the source is connected to the input terminal (node a) of the storage unit SM1
  • the drain is connected to the column data line d
  • the gate is connected to the row scanning line g.
  • the storage unit SM1 is a self-holding memory including two inverters INV11 and INV12 in which one output terminal is connected to the other input terminal. More specifically, the input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NMOS transistor MN1 forming the switch SW1. The input terminal of the inverter INV12 is connected to the switch SW2 and the output terminal of the inverter INV11.
  • FIG. 3 is a circuit diagram showing a specific configuration of the inverter INV11.
  • the inverter INV11 includes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) MP11 and an NMOS transistor MN11 connected in series, and inverts the input signals supplied to the respective gates.
  • a PMOS transistor P-channel MOS transistor
  • MN11 NMOS transistor
  • Is a known CMOS inverter that outputs from the drain of
  • the inverter INV12 is a known CMOS inverter that includes a PMOS transistor MP12 and an NMOS transistor MN12 connected in series, and inverts an input signal supplied to each gate and outputs the inverted signal from each drain.
  • the drive capabilities of the inverters INV11 and INV12 are different. Specifically, among the inverters INV11 and INV12 that constitute the storage unit SM1, the drivability of the transistors MP11 and MN11 in the inverter INV11 on the input side as viewed from the switch SW1 is the inverter on the output side as viewed from the switch SW1. It is larger than the driving capability of the transistors MP12 and MN12 in the INV12. As a result, data easily propagates from the column data line d to the storage unit SM1 via the switch SW1, while data hardly propagates from the storage unit DM2 to the storage unit SM1 via the switch SW2.
  • the drive capability of the NMOS transistor MN1 configuring the switch SW1 is larger than the drive capability of the NMOS transistor MN12 configuring the inverter INV12.
  • a current flowing from column data line d to the input terminal (node a) of storage unit SM1 via switch SW1 is Since the current flowing from the input terminal of the storage unit SM1 to the ground voltage terminal GND via the NMOS transistor MN12 is larger than the current, data can be accurately stored in the storage unit SM1.
  • the switch SW2 is a known transmission gate composed of an NMOS transistor MN2 and a PMOS transistor MP2 connected in parallel. More specifically, in the NMOS transistor MN2 and the PMOS transistor MP2, their respective sources are commonly connected to the output terminal of the storage unit SM1, and their respective drains are the input terminal of the storage unit DM2 and the reflective electrode PE of the liquid crystal display element LC. Commonly connected.
  • the gate of the NMOS transistor MN2 is connected to the non-inversion trigger pulse trigger line trig, and the gate of the PMOS transistor MP2 is connected to the inversion trigger pulse trigger line trigb.
  • the switch SW2 is turned on when the forward rotation trigger pulse supplied via the trigger line trig is at the H level (the inversion trigger pulse supplied via the trigger line trigb is at the L level), and from the storage unit SM1 The read data is transferred to the storage unit DM2 and the reflective electrode PE.
  • the switch SW2 is turned off when the forward rotation trigger pulse supplied via the trigger line trig is at L level (the inversion trigger pulse supplied via the trigger line trigb is at H level), and the switch SW2 Reading stored data is not performed.
  • switch SW2 Since switch SW2 is a known transmission gate, it can transfer a wide range of voltage from ground voltage GND to power supply voltage VDD in the on state. More specifically, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the ground voltage GND level (L level), instead of the source / drain of the PMOS transistor MP2 not conducting, The source and drain can be conducted with low resistance. On the other hand, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the power supply voltage VDD level (H level), the source and drain of the PMOS transistor MP2 are It can be conducted with low resistance. As described above, in the switch SW2, since the source and drain of the transmission gate can be conducted with low resistance, a wide range of voltages from the ground voltage GND to the power supply voltage VDD can be transferred in the on state.
  • the storage unit DM2 is configured of a capacity C1.
  • the capacitance C1 may be, for example, an MIM (Metal Insulator Metal) capacitance that forms a capacitance between interconnections, a Diffusion capacitance that forms a capacitance between the substrate and polysilicon, or a PIP (Poly) that forms a capacitance between two-layer polysilicon. Insulator Poly) capacity etc. can be used.
  • the switch SW2 When the switch SW2 is turned on, the data stored in the storage unit SM1 is read out and transferred to the capacitance C1 and the reflective electrode PE in the storage unit DM2 via the switch SW2. Thereby, the data stored in the storage unit DM2 is rewritten.
  • the data held in the capacitor C1 also affects the input gate of the inverter INV12 that configures the storage unit SM1.
  • the inverter INV11 since the drive capacity of the inverter INV11 is larger than the drive capacity of the inverter INV12, the inverter INV11 rewrites the data of the capacity C1 before the inverter INV12 is affected by the data of the capacity C1. Therefore, the data stored in the storage unit SM1 is not unintentionally rewritten due to the stored data of the capacity C1.
  • the reflective liquid crystal display device 10 uses the pixel 12 including one SRAM cell and one DRAM cell, as compared to the case where a pixel including two SRAM cells is used, By reducing the number of transistors constituting a pixel, miniaturization of the pixel is realized.
  • the present invention is not limited to this.
  • the switch SW2 can be appropriately changed to a configuration in which any one of the PMOS transistor MP2 and the NMOS transistor MN2 is provided. In that case, only one of the trigger lines trig and trigb is provided.
  • the storage portions SM1 and DM2 and the reflective electrode PE are elements. Pixels can be miniaturized also by arranging them effectively in the height direction. Hereinafter, this will be described in detail with reference to FIG.
  • FIG. 4 is a schematic cross-sectional view showing the main part of the pixel 12. Further, in FIG. 4, a case where the capacitor C1 is formed by an MIM which forms a capacitor between the wirings will be described as an example.
  • an N well 101 and a P well 102 are formed on a silicon substrate 100.
  • the PMOS transistor MP2 of the switch SW2 and the PMOS transistor MP11 of the inverter INV11 are formed on the N well 101. More specifically, a common diffusion layer serving as the source of each of the PMOS transistors MP2 and MP11 and two diffusion layers serving as the drain are formed on the N well 101, and the common diffusion layer and the two diffusion layers are formed. On the channel region between them, polysilicon serving as the gate of each of the PMOS transistors MP2 and MP11 is formed via the gate oxide film.
  • an NMOS transistor MN2 of the switch SW2 and an NMOS transistor MN11 of the inverter INV11 are formed on the P well 102. More specifically, a common diffusion layer serving as the source of each of the NMOS transistors MN2 and MN11 and two diffusion layers serving as the drain are formed on the P well 102, and the common diffusion layer and the two diffusion layers are formed. On the channel region between them, polysilicon serving as the gate of each of the NMOS transistors MN2 and MN11 is formed via the gate oxide film.
  • a device isolation oxide film 103 is formed between the active region (diffusion layer and channel region) on the N well and the active region on the P well.
  • An interlayer insulating film 105 is interposed between metals above the transistors MP2, MP11, MN2, and MN11, and the first metal 106, the second metal 108, the third metal 110, the MIM electrode 112, the fourth metal 114, and The fifth metal 116 is stacked.
  • the fifth metal 116 constitutes a reflective electrode PE formed for each pixel.
  • the diffusion layers constituting the drains of the transistors MN2 and MP2 are the contact 118, the first metal 106, the through hole 119a, the second metal 108, the through hole 119b, the third metal 110, the through hole 119c, the fourth metal 114, And, the through holes 119 e are electrically connected to the fifth metal 116. Further, the diffusion layers constituting the drains of the transistors MN2 and MP2 are the contact 118, the first metal 106, the through hole 119a, the second metal 108, the through hole 119b, the third metal 110, the through hole 119c, the fourth metal It is electrically connected to the MIM electrode 112 through the through hole 119 d and the through hole 119 d. That is, the sources of the transistors MN2 and MP2 constituting the switch SW2 are electrically connected to the reflective electrode PE and the MIM electrode 112.
  • the reflective electrode PE (fifth metal 116) is disposed to face the common electrode CE, which is a transparent electrode, through a passivation film (PSV) 117, which is a protective film formed on the upper surface of the reflective electrode PE.
  • a liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE.
  • a liquid crystal display element LC is configured by the reflective electrode PE, the common electrode CE, and the liquid crystal LCM between them.
  • the MIM electrode 112 is formed on the third metal 110 via the interlayer insulating film 105.
  • a capacitance C1 is formed by the MIM electrode 112, the third metal 110, and the interlayer insulating film 105 between them. Therefore, while the switches SW1 and SW2 and the storage unit SM1 are formed using the first metal 106 and the second metal 108, which are the first and second layer wirings, and the transistor, the storage unit DM2 Is formed using the third metal 110 and the MIM electrode 112 which are upper layers of That is, the switches SW1 and SW2, the storage unit SM1, and the storage unit DM2 are formed in different layers.
  • Light from a light source is transmitted through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 116) and is reflected, and travels backward along the original incident path and is emitted through the common electrode CE .
  • the reflective liquid crystal display device 10 uses the fifth metal 116, which is the fifth layer wiring, as the reflective electrode PE, and uses the third metal 110, which is the third layer wiring, as a part of the storage unit DM2.
  • the first metal 106 and the second metal 108, which are the first and second layer wiring, and the transistor as the memory unit SM1 or the like
  • the memory unit SM1, the memory unit DM2 and the reflective electrode PE are effectively arranged in the height direction. This makes it possible to further miniaturize the pixel.
  • a pixel with a pitch of 3 ⁇ m or less can be configured by a transistor with a power supply voltage of 3.3V.
  • the pixels with a pitch of 3 ⁇ m or less it is possible to realize a liquid crystal display panel having a diagonal length of 0.55 inch, 4000 horizontal pixels and 2000 vertical pixels.
  • FIG. 5 is a timing chart showing the operation of the reflective liquid crystal display device 10.
  • the row scanning signals g1 to gm are sequentially selected one by one in units of 1 H by the row scanning signal from the vertical shift register 14. Therefore, the image display unit 11 is configured. Data is written to the plurality of pixels 12 in units of n pixels in one row commonly connected to the selected row scanning line. Then, when data is written to all of the plurality of pixels 12 constituting the image display unit 11, thereafter, the data of all the pixels 12 are read out simultaneously based on the trigger pulses TRI and TRIB (more specifically, The data of the storage unit SM1 in all the pixels 12 are simultaneously transferred to the storage unit DM2 and the reflective electrode PE).
  • FIG. 5 shows a change of subframe data stored in each pixel 12.
  • the vertical axis represents line numbers, and the horizontal axis represents time.
  • the boundary line of the sub-frame data is downward to the right. This means that the subframe data is written later as the row number of the pixel is larger.
  • a period from one end of the boundary to the other end corresponds to a writing period of subframe data.
  • B0b, B1b, and B2b indicate inverted data of subframe data of bits B0, B1, and B2, respectively.
  • FIG. 5 shows the output timing (rising timing) of the trigger pulse TRI.
  • the trigger pulse TRIB is omitted because it always indicates a value obtained by logically inverting the trigger pulse TRI.
  • FIG. 5C schematically shows bits of subframe data applied to the reflective electrode PE.
  • D) of FIG. 5 shows the change of the value of the common electrode voltage Vcom.
  • E) of FIG. 5 shows the change of the voltage applied to the liquid crystal LCM.
  • the non-inverted subframe data of bit B0 output from the horizontal driver 16 to the column data line d is sampled by the switch SW1 and stored Written to SM1.
  • normal subframe data of bit B0 is written to the storage units SM1 of all the pixels 12 constituting the image display unit 11.
  • the trigger pulse TRI at the H level (and the trigger pulse TRIB at the L level) is simultaneously supplied to all the pixels 12 constituting the image display unit 11 (time T1).
  • a holding period of non-inverted subframe data of bit B0 by storage unit DM2 Is one subframe period of time (time T2) until trigger signal TRI becomes H level (time T1) and then becomes H level again next time.
  • the power supply voltage VDD (here, 3.3 V) is applied to the reflective electrode PE
  • the bit value is "0" that is, L level
  • the ground voltage GND (0 V) is applied to the reflective electrode PE.
  • a free voltage can be applied to the common electrode CE as the common electrode voltage Vcom without being limited to the ground voltage GND and the power supply voltage VDD, and an H level normal rotation trigger pulse TRI is input.
  • the common electrode voltage Vcom is controlled to be switched to a predetermined voltage in synchronization.
  • the common electrode voltage Vcom is the threshold voltage Vtt of the liquid crystal more than 0 V as shown in FIG. 5D during the sub-frame period in which the non-inverted sub-frame data of bit B0 is applied to the reflective electrode PE. It is set to a low voltage.
  • the liquid crystal display element LC performs gradation display according to the applied voltage of the liquid crystal LCM, which is the absolute value of the difference voltage between the applied voltage of the reflective electrode PE and the common electrode voltage Vcom. Therefore, in the sub-frame period (time T1 to T2) in which the non-inverted sub-frame data of bit B0 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is, as shown in FIG.
  • FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal and the gray scale value of the liquid crystal.
  • the gray scale value of black corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal
  • the storage portion SM1 of all the pixels 12 constituting the image display portion 11 is Writing of the inverted subframe data of bit B0 is sequentially started. Then, when the inverted subframe data of bit B0 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, the H level is then applied to all the pixels 12 constituting the image display unit 11.
  • the trigger pulse TRI (and the L level trigger pulse TRIB) are simultaneously supplied (time T2).
  • the inverted subframe data of the bit B0 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held.
  • Inverted subframe data is applied to the reflective electrode PE.
  • the holding period of the inverted subframe data of bit B0 by storage unit DM2 is This is one subframe period (time T3) from when the trigger pulse TRI turns to H level (time T2) to next time it turns to H level again (time T3).
  • the inverted subframe data of bit B0 since the inverted subframe data of bit B0 always has an inverse logical value relationship with the non-inverted subframe data of bit B0, “0” when the non-inverted subframe data of bit B0 is “1”. It is "1" when the non-inverted subframe data of B0 is "0".
  • the common electrode voltage Vcom is higher than 3.3 V by the threshold voltage Vtt of the liquid crystal during the sub-frame period in which the inverted sub-frame data of the bit B0 is applied to the reflective electrode PE.
  • the bit value of the non-inverted subframe data of bit B0 is "1"
  • the bit value of the inverted subframe data of bit B0 applied subsequently is "0".
  • the voltage applied to the liquid crystal LCM is ⁇ (3.3 V + Vtt), and the direction of the potential is opposite but the absolute value is the same as compared with the case where the non-inverted subframe data of bit B0 is applied. . Therefore, also when the inverted subframe data of bit B0 is applied, the pixel 12 displays white in the same manner as when the non-inverted frame data of bit B0 is applied.
  • the bit value of the non-inverted subframe data of bit B0 is "0"
  • the bit value of the inverted subframe data of bit B0 applied subsequently is "1".
  • the voltage applied to the liquid crystal LCM is ⁇ Vtt, and the direction of the potential is opposite but the absolute value is the same as compared with the case where the non-inverted subframe data of bit B0 is applied. Therefore, also when the inverted subframe data of bit B0 is applied, the pixel 12 displays black in the same manner as when the non-inverted frame data of bit B0 is applied.
  • the pixel 12 displays the same gradation with the bit B0 and the complementary bit B0b of the bit B0 during two sub-frame periods from time T1 to T3, and Since AC driving is performed in which the potential direction is reversed every subframe, burn-in of the liquid crystal LCM can be prevented.
  • the common electrode voltage Vcom is a voltage lower than 0 V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal subframe data of bit B1 is applied to the reflective electrode PE.
  • the voltage applied to the liquid crystal LCM is, as shown in FIG.
  • the bit B1 for the storage part SM1 of all the pixels 12 constituting the image display part 11 Writing of the inverted subframe data of is sequentially started. Then, when the inverted subframe data of bit B1 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, then, H level is applied to all the pixels 12 constituting the image display unit 11
  • the trigger pulse TRI (and the L level trigger pulse TRIB) are simultaneously supplied (time T4).
  • the inverted subframe data of the bit B1 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held.
  • Inverted subframe data is applied to the reflective electrode PE.
  • the holding period of the inverted subframe data of bit B1 by storage unit DM2 is This is one subframe period (time T5) from when the trigger pulse TRI turns to H level (time T4) to next time it turns to H level again (time T5).
  • the inverted subframe data of bit B1 is always in a reverse logical value relationship with the non-inverted subframe data of bit B1.
  • the common electrode voltage Vcom is higher than 3.3 V by the threshold voltage Vtt of the liquid crystal during the sub-frame period in which the inverted sub-frame data of the bit B1 is applied to the reflective electrode PE.
  • the pixel 12 displays the same gradation with the bit B1 and the complementary bit B1b of the bit B1 during two sub-frame periods from time T3 to T5, and the liquid crystal LCM Since the potential drive direction of the liquid crystal is reversed drive every subframe, burn-in of the liquid crystal LCM can be prevented. The same operation is repeated for bit B2 and thereafter.
  • the reflective liquid crystal display device 10 performs gradation display by combining a plurality of sub-frames.
  • each display period of bit B0 and complementary bit B0b is the same first subframe period, and each display period of bit B1 and complementary bit B1b is also the same second subframe period, but the first display period is the same.
  • the subframe period and the second subframe period are not necessarily the same.
  • the second subframe period is set to twice the first subframe period.
  • the third sub-frame period which is each display period of the bit B2 and the complementary bit B2 b is set to be twice as long as the second sub-frame period. The same is true for the other subframe periods.
  • the length of each subframe period and the number of subframes can be arbitrarily set according to the specification of the system and the like.
  • the frame unit 21 is a unit that displays black in the outer frame area (frame area) of the image displayed by the image display unit 11 when the image is enlarged and projected by, for example, a projector or the like.
  • FIG. 7 is a schematic plan view of the reflective liquid crystal display device 10.
  • the image display unit 11 is provided on the chip CHP 1
  • the frame unit 21 is provided so as to surround the outer periphery of the image display unit 11.
  • a horizontal driver 16 for driving each pixel 12, a vertical shift register 14, a timing generator 13, a data latch circuit 15 and the like are formed in the lower hierarchy of the frame electrode G1 of the frame portion 21.
  • a plurality of pads PD1 are provided around the periphery of the chip CHP1.
  • Each functional block on the chip CHP1 is connected to, for example, a flexible printed circuit (FPC) via a plurality of pads PD1 and bonding wires, and the image display unit 11 is controlled by a control signal from a host device configured by the FPC. To display an image or to display black by the frame portion 21.
  • FPC flexible printed circuit
  • FIG. 8 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device according to the comparative example, and the frame electrode G5 of the frame portion 51.
  • the reflective electrode PE of each of the plurality of pixels 12 provided at the corner of the image display unit 11 and the frame electrode G5 of the frame 51 provided at the periphery thereof are shown.
  • the frame electrode G ⁇ b> 5 is a solid electrode that spreads without a gap over the entire surface of the frame portion 51 and is formed in the same layer as the reflective electrode PE of the pixel 12.
  • the common electrode CE is disposed to be separated and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and the frame electrode G5.
  • a liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G5, and the liquid crystal LCM.
  • the same voltage Vcom as that of the common electrode CE is applied to the frame electrode G5.
  • the potential difference between the frame electrode G5 and the common electrode CE becomes 0 V, so black is displayed on the frame portion 51.
  • the level of black displayed by the frame unit 51 is the same as the level of black displayed by the image display unit 11 so as not to hinder the improvement of the quality of the image displayed by the image display unit 11 preferable.
  • the black displayed by the frame 51 is displayed more black than the black displayed by the image display unit 11. Therefore, in the reflection type liquid crystal display device in which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated due to, for example, the black displayed by the frame portion 51 being overemphasized.
  • the problem is that the aperture ratio of the reflective electrode PE of the pixel 12 (the ratio of the arrangement area of the reflective electrode PE to occupy in the pixel arrangement region A1) and the aperture ratio of the frame electrode G5 of the frame 51 (an electrode equivalent to the pixel arrangement region A1) This is because the ratio of the arrangement area of the frame electrode G5 to the arrangement area A5 is different. This will be described below with reference to FIG.
  • the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrodes PE. As a result, the aperture ratio of the reflective electrode PE of the pixel 12 is reduced. Specifically, the aperture ratio of the reflective electrode PE of the pixel 12 is such that the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 ⁇ m and the pixel gap L2 is 0.2 ⁇ m. , 89.75% (see the left figure in FIG. 9).
  • the frame electrode G5 of the frame portion 51 is a solid electrode which spreads without a gap over the entire frame portion 51 as described above. Therefore, the aperture ratio of the frame electrode G5 is 100% (see the right of FIG. 9).
  • FIG. 10 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G1 of the frame unit 21. Note that, in the example of FIG. 10, only the reflection electrodes PE of the plurality of pixels 12 provided at the corner of the image display unit 11 and the plurality of frame electrodes G1 of the frame portion 21 provided around the same are shown. It is done.
  • the frame portion 21 has a plurality of frame electrodes G1 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix.
  • the electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged.
  • the plurality of frame electrodes G1 are formed in the same layer as the reflective electrode PE of the pixel 12.
  • each frame electrode G1 In the upper layer of each frame electrode G1, a common electrode CE is disposed so as to be spaced apart and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G1.
  • a liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G1, and the liquid crystal LCM.
  • Each frame electrode G1 is configured by a rectangular main body portion G1a in plan view, and two connecting portions G1b provided so as to protrude from one side of the main body portion and the other side orthogonal thereto. There is.
  • Each frame electrode G1 is electrically connected to the adjacent frame electrode G1 by the connecting portion G1b. Thereby, the application voltage of all the frame electrodes G1 of the frame part 21 can be made the same.
  • each frame electrode G1 the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G1.
  • the potential difference between each frame electrode G1 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 21.
  • FIG. 11 is a schematic cross-sectional view of a portion XI-XI of the schematic plan view shown in FIG.
  • a liquid crystal display element including the frame electrode G1 and a circuit portion in a lower layer than the frame electrode G1 are electrically separated. Therefore, the same voltage Vcom as that of the common electrode CE can be supplied to the frame electrode G1 regardless of the circuit portion in the lower layer than the frame electrode G1.
  • the other cross-sectional structures are the same as the contents described in FIG.
  • the level of black displayed by the frame unit 21 is as close as possible to the level of black displayed by the image display unit 11 (ideally, so as not to hinder the improvement of the quality of the image displayed by the image display unit 11). Is the same).
  • the aperture ratio of the frame electrode G1 (the ratio of the arrangement area of the frame electrode G1 occupied in the electrode arrangement region A2 equivalent to the pixel arrangement region A1) It is as close as possible to the ratio of the arrangement area of the reflective electrode PE occupied in the pixel arrangement area A1 (ideally the same). This will be described below with reference to FIG.
  • the aperture ratio of the reflective electrode PE of the pixel 12 is 3.8 ⁇ m for the length of one side of the square pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 ⁇ m for the pixel gap L2, 89.75. % (See the left figure in FIG. 12).
  • the aperture ratio of the frame electrode G1 is 89.68, assuming that the length L1 of one side of the square electrode arrangement region A2 is 3.8 ⁇ m, the gap L3 is 0.28 ⁇ m, and the width L4 of the connecting portion G1 b is 1 ⁇ m. % (See the right figure in FIG. 12). This is close to the aperture ratio 89.75% of the reflective electrode PE of the pixel 12.
  • the aperture ratio of each frame electrode G1 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12.
  • the reflective liquid crystal display device 10 according to the present embodiment can bring the level of black displayed by the frame portion 21 closer to the level of black displayed by the image display unit 11, so Deterioration can be prevented.
  • the reflective liquid crystal display device 10 according to the present embodiment can equalize the level of black displayed by each of the frame portion 21 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
  • FIG. 13 shows experimental results showing the relationship between the difference in the aperture ratio of each of the reflective electrode PE and the frame electrode G1, and the difference in the black level displayed by each of the image display unit 11 and the frame unit 21.
  • the difference in the aperture ratio between the reflective electrode PE and the frame electrode G1 decreases, the difference in the black level displayed by the image display unit 11 and the frame unit 21 decreases.
  • the difference in the aperture ratio between the reflective electrode PE and the frame electrode G1 becomes 5% or less, the image display unit 11 and The difference in black level displayed by each of the frame portions 21 apparently disappeared.
  • FIG. 14 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 according to the second embodiment and a plurality of frame electrodes G2 of the frame portion 31.
  • the frame portion 31 corresponds to the frame portion 21 and the frame electrode G2 corresponds to the frame electrode G1.
  • only the reflection electrodes PE of the plurality of pixels 12 provided at the corner of the image display unit 11 and the plurality of frame electrodes G2 of the frame portion 31 provided around the same are shown. It is done.
  • the frame portion 31 has a plurality of frame electrodes G2 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix.
  • the electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged.
  • the plurality of frame electrodes G2 are formed in the same layer as the reflective electrode PE of the pixel 12.
  • each frame electrode G2 a common electrode CE is disposed so as to be separated and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G2.
  • a liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G2, and the liquid crystal LCM.
  • Each frame electrode G2 has the same shape as the reflective electrode PE of the pixel 12 in plan view.
  • Each frame electrode G2 is electrically connected to the adjacent frame electrode G2 by the wiring of the circuit portion formed in the lower layer of these frame electrodes G2. Thereby, the applied voltage of all the frame electrodes G2 of the frame part 31 can be made the same.
  • each frame electrode G2 the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G2.
  • the potential difference between each frame electrode G2 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 31.
  • FIG. 15 is a schematic cross-sectional view of the XV-XV portion of the schematic plan view shown in FIG.
  • the adjacent frame electrodes G2 are electrically connected to each other through the fourth metal 114 and the through holes 119e formed in the lower layer of the frame electrodes G2. .
  • the applied voltage of all the frame electrodes G2 of the frame part 31 can be made the same.
  • the other cross-sectional structures are the same as the contents described in FIG.
  • the level of black displayed by the frame section 31 is as close as possible to the level of black displayed by the image display section 11 (ideally, so as not to hinder the improvement of the quality of the image displayed by the image display section 11). Is the same).
  • the aperture ratio of the frame electrode G2 (the ratio of the arrangement area of the frame electrode G2 occupied in the electrode arrangement region A2 equivalent to the pixel arrangement region A1) It is as close as possible to the ratio of the arrangement area of the reflective electrode PE occupied in the pixel arrangement area A1 (ideally the same). This will be described below with reference to FIG.
  • the aperture ratio of the reflective electrode PE of the pixel 12 is 3.8 ⁇ m for the length of one side of the square pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 ⁇ m for the pixel gap L2, 89.75. % (See the left figure in FIG. 16).
  • the aperture ratio of the frame electrode G2 is 89.75% when the length L1 of one side of the square electrode arrangement region A2 is 3.8 ⁇ m and the pixel gap L2 is 0.2 ⁇ m (right view in FIG. 16). reference). This is the same as the aperture ratio 89.75% of the reflective electrode PE of the pixel 12.
  • the aperture ratio of each frame electrode G2 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12.
  • the reflective liquid crystal display device 10 according to the second embodiment can bring the level of black displayed by the frame portion 31 closer to the level of black displayed by the image display portion 11, Deterioration can be prevented.
  • the reflective liquid crystal display device 10 according to the second embodiment can equalize the level of black displayed by each of the frame portion 31 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
  • the level of black displayed by the frame unit 51 is the level of black displayed by the image display unit 11 so as not to hinder the improvement of the quality of the image displayed by the image display unit 11. Is preferably the same as
  • the black displayed by the frame 51 is displayed more black than the black displayed by the image display unit 11. Therefore, in the liquid crystal display device in which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated due to, for example, the black displayed by the frame portion 51 being overemphasized.
  • the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrodes PE of the pixel 12.
  • the perimeter of the reflective electrode PE of the pixel 12 is increased.
  • the peripheral length of the edge portion of the reflective electrode PE of the pixel 12 is 3.8 ⁇ m for the length of one side of the square-shaped pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 ⁇ m for the pixel gap L2 If it is, it becomes 14.44 ⁇ m (see the left figure of FIG. 9).
  • the frame electrode G5 of the frame portion 51 is a solid electrode which spreads without a gap over the entire frame portion 51 as described above. Therefore, the perimeter of the edge portion of the frame electrode G5 is 0 ⁇ m (see the right of FIG. 9).
  • the amount of diffuse reflection increases, so that the amount of reflected light different from the light deflection direction increases, and as a result, the displayed black becomes bright.
  • the amount of diffuse reflection decreases, so that the reflected light different from the light deflection direction decreases, and as a result, the displayed black becomes dark.
  • FIG. 17 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G3 of the frame unit 41. Note that, in the example of FIG. 17, only the reflection electrodes PE of the plurality of pixels 12 provided in the corner of the image display unit 11 and the plurality of frame electrodes G3 of the frame portion 41 provided in the periphery thereof are shown. It is done.
  • the frame portion 41 has a plurality of frame electrodes G3 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix.
  • the electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged.
  • the plurality of frame electrodes G3 are formed in the same layer as the reflective electrode PE of the pixel 12.
  • each frame electrode G3 a common electrode CE is disposed so as to be spaced apart and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G3.
  • a liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G3, and the liquid crystal LCM.
  • Each frame electrode G3 is configured by a rectangular main body portion G3a in plan view, and two connecting portions G3b provided so as to respectively project from one side of the main body portion and the other side orthogonal thereto. There is.
  • Each frame electrode G3 is electrically connected to the adjacent frame electrode G3 by the connecting portion G3b. Thereby, the applied voltage of all the frame electrodes G3 of the frame part 41 can be made the same.
  • each frame electrode G3 the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G3.
  • the potential difference between each frame electrode G3 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 41.
  • the level of black displayed by the frame section 41 is as close as possible to the level of black displayed by the image display section 11 so as not to hinder the improvement of the quality of the image displayed by the image display section 11 (ideally Is the same).
  • the peripheral length of the frame electrode G3 is as close as possible to the peripheral length of the reflective electrode PE of each pixel 12 (they are ideally the same). This will be described below with reference to FIG.
  • the peripheral length of the reflective electrode PE of the pixel 12 is 14.44 ⁇ m, assuming that the length of one side (that is, pixel pitch) L1 of the square pixel arrangement region A1 is 3.8 ⁇ m and the pixel gap L2 is 0.2 ⁇ m. (See the left figure of FIG. 18).
  • the aperture ratio of the frame electrode G1 is 14.44 ⁇ m, assuming that the length L1 of one side of the square electrode arrangement region A2 is 3.8 ⁇ m, the gap L3 is 0.28 ⁇ m, and the width L4 of the connecting portion G1 b is 1 ⁇ m. (See the right side of FIG. 18). This is the same length as the peripheral length of the reflective electrode PE of the pixel 12.
  • the peripheral length (the length of the edge portion) of each frame electrode G3 is as close as possible to the peripheral length of the reflective electrode PE of each pixel 12.
  • the reflective liquid crystal display device 10 according to the third embodiment can bring the level of black displayed by the frame portion 41 closer to the level of black displayed by the image display unit 11, and Deterioration can be prevented.
  • the reflective liquid crystal display device 10 according to the third embodiment can equalize the level of black displayed by each of the frame portion 31 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
  • FIG. 19 is an experimental result showing the relationship between the difference in perimeter of each of the reflective electrode PE and the frame electrode G3 and the difference in black level displayed by each of the image display unit 11 and the frame unit 41.
  • the difference between the black levels displayed by the image display unit 11 and the frame portion 41 decreases as the difference between the perimeters of the reflective electrode PE and the frame electrode G3 decreases.
  • the difference in peripheral length between the reflective electrode PE and the frame electrode G3 difference in peripheral length of the frame electrode G3 based on the peripheral length of the reflective electrode PE
  • the image display unit 11 and The difference in black level displayed by each of the frame portions 41 apparently disappeared.
  • the aperture ratio of each frame electrode is made as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12.
  • the reflective liquid crystal display device 10 according to the third embodiment can bring the level of black displayed by the frame portion closer to the level of black displayed by the image display unit. It can prevent.
  • the reflective liquid crystal display device 10 according to the third embodiment can equalize the level of black displayed by each of the frame portion and the image display portion, a video with no sense of incongruity is displayed for the user. be able to.
  • the present invention can be suitably applied to a liquid crystal display device mounted on a projector or the like.

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Abstract

According to one embodiment, a reflective liquid crystal display device (10) is provided with: an image display part (11) in which a plurality of pixels (12) are respectively disposed in a plurality of pixel disposition regions (A1) divided in a matrix; and a frame part (21) which is provided so as to surround the outer periphery of the image display part (11) and in which a plurality of frame electrodes (G1) are respectively disposed in a plurality of electrode disposition regions (A2) divided in a matrix, wherein in each of the electrode disposition regions (A2), the frame electrode (G1) is disposed such that the area ratio thereof has a difference of 5% or less with reference to the area ratio of a reflecting electrode (PE) of the pixel (12) to each of the pixel disposition regions (A1).

Description

反射型液晶表示装置Reflective liquid crystal display
　本発明は、反射型液晶表示装置に関し、黒表示の品質を向上させるのに適した反射型液晶表示装置に関する。 The present invention relates to a reflective liquid crystal display device, and more particularly to a reflective liquid crystal display device suitable for improving the quality of black display.
　液晶表示装置における中間調表示方式の１つとして、サブフレーム駆動方式が知られている。時間軸変調方式の一種であるサブフレーム駆動方式では、所定の期間（例えば、動画の場合には１画像の表示単位である１フレーム）を複数のサブフレームに分割し、表示すべき階調に応じたサブフレームの組み合わせにより画素を駆動する。表示される階調は、所定の期間に占める画素の駆動期間の割合によって決まり、この割合は、サブフレームの組み合わせによって特定される。 A sub-frame driving method is known as one of the halftone display methods in liquid crystal display devices. In the sub-frame driving method, which is a type of time-axis modulation method, a predetermined period (for example, one frame which is a display unit of one image in the case of a moving image) is divided into a plurality of sub-frames. The pixel is driven by the combination of the corresponding subframes. The gradation to be displayed is determined by the ratio of the driving period of the pixel to the predetermined period, and this ratio is specified by the combination of subframes.
　サブフレーム駆動方式が採用された液晶表示装置の中には、各画素が、マスターラッチ及びスレーブラッチと、液晶表示素子と、複数のスイッチングトランジスタと、によって構成されているものがある。 Among liquid crystal display devices in which the sub-frame driving method is adopted, there is one in which each pixel is configured by a master latch and a slave latch, a liquid crystal display element, and a plurality of switching transistors.
　この画素では、マスターラッチの入力端子に１ビットの第１のデータが第１のスイッチングトランジスタを通して印加され、行走査線を介して印加される行選択信号がアクティブになると、第１のスイッチングトランジスタがオン状態になり、第１のデータがマスターラッチに書き込まれる。 In this pixel, when the first data of 1 bit is applied to the input terminal of the master latch through the first switching transistor and the row selection signal applied through the row scanning line becomes active, the first switching transistor is turned on. When turned on, the first data is written to the master latch.
　全ての画素に設けられたマスターラッチへのデータの書き込みが完了すると、そのサブフレーム期間内において、全ての画素に設けられた第２のスイッチングトランジスタがオン状態になる。それにより、全ての画素に設けられたマスターラッチのデータが一斉に読み出されてスレーブラッチに書き込まれるとともに、当該スレーブラッチに書き込まれたデータが液晶表示素子の画素電極に印加される。各サブフレーム期間において、全ての画素に対して同様の処理が行われる。その結果、各画素は、１フレームを構成する複数のサブフレームの組み合わせにより所望の階調表示を行うことができる。 When the writing of data to the master latch provided in all the pixels is completed, the second switching transistors provided in all the pixels are turned on within the sub-frame period. As a result, data of the master latch provided in all the pixels is simultaneously read and written to the slave latch, and the data written to the slave latch is applied to the pixel electrode of the liquid crystal display element. The same processing is performed on all pixels in each subframe period. As a result, each pixel can perform desired gray scale display by a combination of a plurality of subframes constituting one frame.
　なお、１フレームを構成する複数のサブフレームの期間は、それぞれ同一又は異なる所定の期間に予め割り当てられている。例えば、各画素において、最大階調表示を行う（白を表示させる）場合には１フレームを構成する複数のサブフレームの全てにおいて表示を行い、最小階調表示を行う（黒を表示させる）場合には１フレームを構成する複数のサブフレームの全てにおいて表示を行わず、それ以外の階調表示を行う場合には、表示する階調に応じて表示するサブフレームを選択する。この従来からの手法を採用した液晶表示装置は、階調を示すデジタルデータを入力データとしており、また、２段ラッチ構成のデジタル駆動方式を採用している（例えば、特許文献１参照）。 Note that periods of a plurality of subframes constituting one frame are allocated in advance to the same or different predetermined periods. For example, in the case where maximum gradation display is performed (white is displayed) in each pixel, display is performed in all of a plurality of subframes constituting one frame, and minimum gradation display is performed (black is displayed). In the case of not performing display in all of the plurality of sub-frames constituting one frame, in the case of performing gradation display other than that, the subframe to be displayed is selected according to the gradation to be displayed. A liquid crystal display device adopting this conventional method uses, as input data, digital data representing gradation, and also adopts a digital driving method of a two-stage latch configuration (see, for example, Patent Document 1).
特許第５７３３１５４号公報Patent No. 5733154 gazette
　しかしながら、特許文献１に開示された液晶表示装置では、画像表示部の外周を囲むように設けられた額縁部の額縁電極がベタ電極であると考えられ、その影響で、画像表示部に設けられた各画素によって表示される黒のレベルと、額縁部によって表示される黒のレベルと、が異なってしまう可能性があった。そのため、額縁部によって表示される黒が、画像表示部に設けられた各画素によって表示される黒よりも黒く強調されてしまう可能性があった。それにより、例えばプロジェクターを視聴している場合、同じレベルの黒を表示しているつもりでも、額縁部によって表示される黒が、画像表示部によって表示される黒よりも強調され過ぎてしまい、その結果、映像の品質が低下してしまう、という問題があった。 However, in the liquid crystal display device disclosed in Patent Document 1, the frame electrode of the frame portion provided so as to surround the outer periphery of the image display portion is considered to be a solid electrode, and the effect is that the image display portion is provided. There is a possibility that the level of black displayed by each pixel may be different from the level of black displayed by the frame portion. Therefore, there is a possibility that black displayed by the frame portion may be emphasized more black than black displayed by each pixel provided in the image display unit. As a result, for example, when viewing a projector, even if black of the same level is intended to be displayed, black displayed by the frame portion is overemphasized more than black displayed by the image display portion. As a result, there is a problem that the quality of the image is degraded.
　本発明は以上の点に鑑みなされたもので、黒表示の品質を向上させることが可能な反射型液晶表示装置を提供することを目的とする。 The present invention has been made in view of the above points, and an object thereof is to provide a reflective liquid crystal display device capable of improving the quality of black display.
　本実施形態の一態様にかかる反射型液晶表示装置は、行列状に区画された複数の画素配置領域に複数の画素がそれぞれ配置された画像表示部と、前記画像表示部の外周を囲むようにして設けられ、行列状に区画された複数の電極配置領域に複数の額縁電極がそれぞれ配置された額縁部と、を備え、各前記電極配置領域には、各前記画素配置領域に占める前記画素の反射電極の面積率を基準にして、差分が５％以内の面積率となるように前記額縁電極が配置されている。 The reflective liquid crystal display device according to one aspect of the present embodiment is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. And a frame portion in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement areas partitioned in a matrix, and in each of the electrode arrangement areas, a reflective electrode of the pixels occupying each pixel arrangement area The frame electrode is disposed such that the difference in area ratio is 5% or less based on the area ratio of.
　本実施形態の一態様にかかる反射型液晶表示装置は、行列状に区画された複数の画素配置領域に複数の画素がそれぞれ配置された画像表示部と、前記画像表示部の外周を囲むようにして設けられ、行列状に区画された複数の電極配置領域に複数の額縁電極がそれぞれ配置された額縁部と、を備え、各前記電極配置領域には、各前記画素配置領域に占める前記画素の反射電極の周囲長を基準にして、差分が３０％以内の周囲長となるように前記額縁電極が配置されている。 The reflective liquid crystal display device according to one aspect of the present embodiment is provided so as to surround an image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions partitioned in a matrix and an outer periphery of the image display unit. And a frame portion in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement areas partitioned in a matrix, and in each of the electrode arrangement areas, a reflective electrode of the pixels occupying each pixel arrangement area The frame electrode is disposed such that the difference is within 30% of the peripheral length with respect to the peripheral length of the frame.
　本実施形態によれば、黒表示の品質を向上させることが可能な反射型液晶表示装置を提供することができる。 According to the present embodiment, it is possible to provide a reflective liquid crystal display device capable of improving the quality of black display.
実施の形態１にかかる液晶表示装置を示すブロック図である。FIG. 1 is a block diagram showing a liquid crystal display device according to a first embodiment. 図１に示す液晶表示装置に設けられた画素の具体的構成を示す回路図である。It is a circuit diagram which shows the specific structure of the pixel provided in the liquid crystal display device shown in FIG. 図２に示す画素に設けられた第１データ保持部を構成するインバータの具体的構成を示す回路図である。It is a circuit diagram which shows the specific structure of the inverter which comprises the 1st data holding part provided in the pixel shown in FIG. 図２に示す画素の概略断面図である。It is a schematic sectional drawing of the pixel shown in FIG. 図１に示す液晶表示装置の動作を示すタイミングチャートである。It is a timing chart which shows operation | movement of the liquid crystal display device shown in FIG. 液晶の印加電圧（ＲＭＳ電圧）と液晶のグレースケール値との関係を示す図である。It is a figure which shows the relationship between the applied voltage (RMS voltage) of a liquid crystal, and the gray scale value of a liquid crystal. 図１に示す液晶表示装置の概略平面図である。It is a schematic plan view of the liquid crystal display device shown in FIG. 比較例にかかる液晶表示装置に設けられた画素の反射電極、及び、額縁電極の概略平面図である。It is a schematic plan view of the reflective electrode of the pixel provided in the liquid crystal display device concerning a comparative example, and a frame electrode. 図８に示す画素の反射電電極、及び、額縁電極を拡大した概略平面図である。It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 8, and a frame electrode. 図１に示す液晶表示装置に設けられた画素の反射電極、及び、額縁電極の概略平面図である。It is a schematic plan view of the reflective electrode of the pixel provided in the liquid crystal display device shown in FIG. 1, and a frame electrode. 図１０に示す画素の反射電極、及び、額縁電極の概略断面図である。It is a schematic sectional drawing of the reflective electrode of the pixel shown in FIG. 10, and a frame electrode. 図１０に示す画素の反射電極、及び、額縁電極を拡大した概略平面図である。It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 10, and a frame electrode. 反射電極及び額縁電極のそれぞれの開口率の差と、画像表示部及び額縁部のそれぞれによって表示される黒レベルの差と、の関係を示す図である。It is a figure which shows the relationship of the difference of the aperture ratio of each of a reflective electrode and a frame electrode, and the difference of the black level displayed by each of an image display part and a frame part. 実施の形態２にかかる液晶表示装置に設けられた画素の反射電極、及び、額縁電極の概略平面図である。FIG. 7 is a schematic plan view of a reflective electrode of a pixel and a frame electrode provided in a liquid crystal display device according to Embodiment 2. 図１４に示す画素の反射電極、及び、額縁電極の概略断面図である。It is a schematic sectional drawing of the reflective electrode of the pixel shown in FIG. 14, and a frame electrode. 図１４に示す画素の反射電極、及び、額縁電極を拡大した概略平面図である。It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 14, and a frame electrode. 実施の形態３にかかる液晶表示装置に設けられた画素の反射電極、及び、額縁電極の概略平面図である。FIG. 18 is a schematic plan view of a reflective electrode of a pixel and a frame electrode provided in a liquid crystal display device according to a third embodiment. 図１７に示す画素の反射電極、及び、額縁電極を拡大した概略平面図である。It is the schematic plan view which expanded the reflective electrode of the pixel shown in FIG. 17, and a frame electrode. 反射電極及び額縁電極のそれぞれの周囲長の差と、画像表示部及び額縁部のそれぞれによって表示される黒レベルの差と、の関係を示す図である。It is a figure which shows the relationship of the difference of the perimeter length of each of a reflective electrode and a frame electrode, and the difference of the black level displayed by each of an image display part and a frame part.
＜実施の形態１＞
　以下、図面を用いて本発明の実施形態について説明する。 Embodiment 1
Hereinafter, embodiments of the present invention will be described using the drawings.
　図１は、実施の形態１に係る反射型液晶表示装置１０を示すブロック図である。
　図１に示すように、反射型液晶表示装置１０は、画像表示部１１と、タイミングジェネレータ１３と、垂直シフトレジスタ１４と、データラッチ回路１５と、水平ドライバ１６と、を備える。水平ドライバ１６は、水平シフトレジスタ１６１と、ラッチ部１６２と、レベルシフタ／画素ドライバ１６３と、により構成される。 FIG. 1 is a block diagram showing a reflective liquid crystal display device 10 according to the first embodiment.
As shown in FIG. 1, the reflective liquid crystal display device 10 includes an image display unit 11, a timing generator 13, a vertical shift register 14, a data latch circuit 15, and a horizontal driver 16. The horizontal driver 16 includes a horizontal shift register 161, a latch unit 162, and a level shifter / pixel driver 163.
　画像表示部１１は、行列状に区画された複数の画素配置領域のそれぞれに規則的に配置された複数の画素１２を有する。 The image display unit 11 has a plurality of pixels 12 regularly arranged in each of a plurality of pixel arrangement regions partitioned in a matrix.
　複数の画素１２は、垂直シフトレジスタ１４に一端が接続されて行方向（Ｘ方向）に延在するｍ本（ｍは２以上の自然数）の行走査線ｇ１～ｇｍと、レベルシフタ／画素ドライバ１６３に一端が接続されて列方向（Ｙ方向）に延在するｎ本（ｎは２以上の自然数）の列データ線ｄ１～ｄｎと、がそれぞれ交差する複数の交差部に二次元マトリクス状に配置されている。画像表示部１１内の全ての画素１２は、一端がタイミングジェネレータ１３に接続されたトリガ線ｔｒｉｇ，ｔｒｉｇｂに共通接続されている。 The plurality of pixels 12 are connected to one end of the vertical shift register 14 and extend in the row direction (X direction) by m (m is a natural number of 2 or more) row scanning lines g1 to gm; Are arranged in a two-dimensional matrix at a plurality of intersections where n (n is a natural number of 2 or more) column data lines d1 to dn each having one end connected thereto and extending in the column direction (Y direction) It is done. All the pixels 12 in the image display unit 11 are commonly connected to trigger lines trig and trigb whose one ends are connected to the timing generator 13.
　なお、正転トリガパルス用トリガ線ｔｒｉｇが伝送する正転トリガパルスＴＲＩと、反転トリガパルス用トリガ線ｔｒｉｇｂが伝送する反転トリガパルスＴＲＩＢとは、常に逆論理値の関係（相補的な関係）にある。 It should be noted that the relation (complementary relation) between the non-inverted trigger pulse TRI transmitted by the non-inverted trigger pulse trigger line trig and the inverted trigger pulse TRIB transmitted by the inverted trigger pulse trigger line trigb is always reverse logic value. is there.
　タイミングジェネレータ１３は、上位装置２０から出力された垂直同期信号Ｖｓｔ、水平同期信号Ｈｓｔ、及び、基本クロックＣＬＫ等の外部信号を入力信号として受け取り、これら外部信号に基づいて、交流化信号ＦＲ、ＶスタートパルスＶＳＴ、ＨスタートパルスＨＳＴ、クロック信号ＶＣＫ，ＨＣＫ、ラッチパルスＬＴ、及び、トリガパルスＴＲＩ，ＴＲＩＢ等の各種の内部信号を生成する。 The timing generator 13 receives external signals such as the vertical synchronization signal Vst, the horizontal synchronization signal Hst, and the basic clock CLK output from the higher-level device 20 as input signals, and generates alternating current signals FR and V based on these external signals. Various internal signals such as the start pulse VST, the H start pulse HST, the clock signals VCK and HCK, the latch pulse LT, and the trigger pulses TRI and TRIB are generated.
　交流化信号ＦＲは、１サブフレーム毎に極性反転する信号であり、画像表示部１１を構成する画素１２内の液晶表示素子の共通電極に、後述する共通電極電圧Ｖｃｏｍとして供給される。 The alternating signal FR is a signal whose polarity is inverted every one sub-frame, and is supplied as a common electrode voltage Vcom to be described later to a common electrode of the liquid crystal display element in the pixel 12 constituting the image display unit 11.
　スタートパルスＶＳＴは、後述する各サブフレームの開始タイミングで出力されるパルス信号であり、このスタートパルスＶＳＴによって、サブフレームの切替わりが制御される。 The start pulse VST is a pulse signal that is output at the start timing of each subframe to be described later, and the switching of subframes is controlled by the start pulse VST.
　スタートパルスＨＳＴは、水平シフトレジスタ１６１の開始タイミングで当該水平シフトレジスタ１６１に対して出力されるパルス信号である。 The start pulse HST is a pulse signal output to the horizontal shift register 161 at the start timing of the horizontal shift register 161.
　クロック信号ＶＣＫは、垂直シフトレジスタ１４における１水平走査期間（１Ｈ）を規定するシフトクロックであり、クロック信号ＶＣＫのタイミングで垂直シフトレジスタ１４がシフト動作を行う。 The clock signal VCK is a shift clock defining one horizontal scanning period (1H) in the vertical shift register 14. The vertical shift register 14 performs a shift operation at the timing of the clock signal VCK.
　クロック信号ＨＣＫは、水平シフトレジスタ１６１におけるシフトクロックであり、３２ビット幅でデータをシフトさせるための信号である。 The clock signal HCK is a shift clock in the horizontal shift register 161, and is a signal for shifting data with a 32-bit width.
　ラッチパルスＬＴは、水平シフトレジスタ１６１が水平方向の１行の画素数分のデータをシフトし終わったタイミングで出力されるパルス信号である。 The latch pulse LT is a pulse signal that is output at the timing when the horizontal shift register 161 has finished shifting the data for the number of pixels in one row in the horizontal direction.
　正転トリガパルスＴＲＩ及び反転トリガパルスＴＲＩＢは、それぞれトリガ線ｔｒｉｇ，ｔｒｉｇｂを介して、画像表示部１１内の全ての画素１２に供給されるパルス信号である。 The non-inverted trigger pulse TRI and the inverted trigger pulse TRIB are pulse signals supplied to all the pixels 12 in the image display unit 11 via the trigger lines trig and trigb, respectively.
　ここで、正転トリガパルスＴＲＩ及び反転トリガパルスＴＲＩＢは、あるサブフレーム期間において、画像表示部１１内の全ての画素１２内の第１データ保持部にデータが書き込まれた後にタイミングジェネレータ１３から出力される。それにより、そのサブフレーム期間において、画像表示部１１内の全ての画素１２内の第１データ保持部に保持されたデータが、それぞれ対応する画素１２内の第２データ保持部に一斉に転送される。 Here, the normal rotation trigger pulse TRI and the inversion trigger pulse TRIB are output from the timing generator 13 after data is written to the first data holding unit in all the pixels 12 in the image display unit 11 in a certain subframe period. Be done. As a result, in the sub-frame period, the data held in the first data holding units in all the pixels 12 in the image display unit 11 are simultaneously transferred to the second data holding units in the corresponding pixels 12. Ru.
　垂直シフトレジスタ１４は、各サブフレームの開始タイミングで供給されるＶスタートパルスＶＳＴをクロック信号ＶＣＫに従って転送し、行走査信号を行走査線ｇ１～ｇｍに対して１Ｈ単位で順次排他的に供給する。それにより、画像表示部１１の最も上にある行走査線ｇ１から最も下にある行走査線ｇｍにかけて、行走査線が１本ずつ１Ｈ単位で順次選択されていく。 Vertical shift register 14 transfers V start pulse VST supplied at the start timing of each sub-frame in accordance with clock signal VCK, and sequentially and exclusively supplies the row scanning signal to row scanning lines g1 to gm in 1 H units. . Thus, the row scanning lines are sequentially selected one by one in units of 1H from the uppermost row scanning line g1 to the lowermost row scanning line gm of the image display unit 11.
　データラッチ回路１５は、図示しない外部回路から供給される１サブフレーム単位の３２ビット幅のデータを、上位装置２０からの基本クロックＣＬＫに基づいてラッチした後、基本クロックＣＬＫに同期して水平シフトレジスタ１６１へ出力する。 Data latch circuit 15 latches 32-bit wide data in units of one subframe supplied from an external circuit (not shown) based on basic clock CLK from host device 20, and then horizontally shifts in synchronization with basic clock CLK. Output to the register 161.
　なお、反射型液晶表示装置１０は、映像信号の１フレームを、その映像信号の１フレーム期間より短い表示期間を持つ複数のサブフレームに分割し、これらサブフレームの組み合わせにて階調表示を行っている。そのため、上記の外部回路は、各画素の階調を示す階調データを、複数のサブフレームに対応する複数の１ビットのサブフレームデータに変換している。さらに、上記の外部回路は、同じサブフレームに属する３２画素分のサブフレームデータをまとめて３２ビット幅のデータとしてデータラッチ回路１５に供給している。 The reflective liquid crystal display device 10 divides one frame of a video signal into a plurality of subframes having a display period shorter than one frame period of the video signal, and performs gradation display by a combination of these subframes. ing. Therefore, the above external circuit converts gradation data indicating the gradation of each pixel into a plurality of 1-bit subframe data corresponding to a plurality of subframes. Furthermore, the above external circuit collectively supplies subframe data for 32 pixels belonging to the same subframe to the data latch circuit 15 as data of 32 bits width.
　水平シフトレジスタ１６１は、１ビットシリアルデータの処理系としてみた場合、タイミングジェネレータ１３から１Ｈの初期に供給されるスタートパルスＨＳＴによりシフトを開始し、データラッチ回路１５から供給される３２ビット幅のデータをクロック信号ＨＣＫに同期してシフトする。 When viewed as a processing system of 1-bit serial data, the horizontal shift register 161 starts shifting by the start pulse HST supplied from the timing generator 13 at the initial stage of 1H, and data of 32-bit width supplied from the data latch circuit 15 In synchronization with the clock signal HCK.
　ラッチ部１６２は、水平シフトレジスタ１６１が画像表示部１１の１行分の画素数ｎと同じｎビット分のデータをシフトし終わると、タイミングジェネレータ１３から供給されるラッチパルスＬＴに同期して、水平シフトレジスタ１６１から並列に供給されるｎビット分のデータ（即ち、ｎ画素分のサブフレームデータ）をラッチし、レベルシフタ／画素ドライバ１６３のレベルシフタへ出力する。なお、ラッチ部１６２のデータ転送が終了すると、タイミングジェネレータ１３からスタートパルスＨＳＴが再び出力され、水平シフトレジスタ１６１はクロック信号ＨＣＫに従ってデータラッチ回路１５からの３２ビット幅のデータのシフトを再開する。 The latch unit 162 synchronizes with the latch pulse LT supplied from the timing generator 13 when the horizontal shift register 161 finishes shifting data of n bits equal to the number n of pixels in one row of the image display unit 11. Data of n bits supplied in parallel from the horizontal shift register 161 (that is, subframe data of n pixels) is latched and output to the level shifter of the level shifter / pixel driver 163. When the data transfer of the latch unit 162 is completed, the start pulse HST is output again from the timing generator 13, and the horizontal shift register 161 resumes the shift of 32-bit data from the data latch circuit 15 according to the clock signal HCK.
　レベルシフタ／画素ドライバ１６３のレベルシフタは、ラッチ部１６２から転送された１行のｎ画素に対応するｎ個のサブフレームデータの信号レベルを液晶駆動電圧振幅までレベルシフトする。レベルシフタ／画素ドライバ１６３の画素ドライバは、レベルシフト後の１行のｎ画素に対応したｎ個のサブフレームデータをｎ本の列データ線ｄ１～ｄｎに並列に出力する。 The level shifter of the level shifter / pixel driver 163 shifts the signal levels of n pieces of subframe data corresponding to n pixels in one row transferred from the latch unit 162 to the liquid crystal drive voltage amplitude. The pixel driver of the level shifter / pixel driver 163 outputs n pieces of subframe data corresponding to n pixels in one row after level shift in parallel to n column data lines d1 to dn.
　水平ドライバ１６は、１水平走査期間において、データ書き込み対象として選択されている行の画素に向けたサブフレームデータの出力と、次の１水平走査期間にデータ書き込み対象として選択される行の画素のためのサブフレームデータのシフトと、を並行して行っている。そして、ある水平走査期間において、１行のｎ画素に対応するｎ個のサブフレームデータが、データ信号としてそれぞれｎ本の列データ線ｄ１～ｄｎに並列に、かつ、一斉に出力される。 The horizontal driver 16 outputs the sub-frame data directed to the pixels of the row selected as the data writing target in one horizontal scanning period and the pixels of the row selected as the data writing target in the next one horizontal scanning period. Shifting of subframe data in parallel is performed. Then, in a horizontal scanning period, n sub-frame data corresponding to n pixels in one row are simultaneously output in parallel to n column data lines d1 to dn as data signals.
　画像表示部１１を構成する複数の画素１２のうち、垂直シフトレジスタ１４からの行走査信号により選択された１行のｎ個の画素１２は、レベルシフタ／画素ドライバ１６３から一斉に出力された１行分のｎ個のサブフレームデータをｎ本の列データ線ｄ１～ｄｎを介してサンプリングして各画素１２内の後述する第１データ保持部に書き込む。 The n pixels 12 in one row selected by the row scanning signal from the vertical shift register 14 among the plurality of pixels 12 constituting the image display unit 11 are one row output simultaneously from the level shifter / pixel driver 163. A portion of n sub-frame data is sampled via n column data lines d1 to dn and written to a first data holding unit described later in each pixel 12.
　画素１２の詳細については後述するが、画素１２では、記憶部ＳＭ１に保持された入力データの反転データが反射電極ＰＥに印加される。つまり、画素１２は、レベルシフタ／画素ドライバ１６３から供給された入力データを反転する機能を有している。 Although the details of the pixel 12 will be described later, in the pixel 12, inverted data of the input data held in the storage unit SM1 is applied to the reflective electrode PE. That is, the pixel 12 has a function of inverting input data supplied from the level shifter / pixel driver 163.
（画素１２の具体的構成）
　続いて、画素１２の具体的構成について説明する。
　図２は、画素１２の具体的構成を示す回路図である。 (Specific configuration of the pixel 12)
Subsequently, a specific configuration of the pixel 12 will be described.
FIG. 2 is a circuit diagram showing a specific configuration of the pixel 12.
　図２に示すように、画素１２は、行走査線ｇ１～ｇｍの何れか（以下、行走査線ｇと称す）と、列データ線ｄ１～ｄｎの何れか（以下、列データ線ｄと称す）と、が交差する交差部分に設けられている。 As shown in FIG. 2, the pixel 12 may be any of row scan lines g1 to gm (hereinafter referred to as row scan line g) and any of column data lines d1 to dn (hereinafter referred to as column data line d). And are provided at the intersections where they intersect.
　画素１２は、ＳＲＡＭセル２０１と、ＤＲＡＭセル２０２と、液晶表示素子ＬＣと、を備える。ＳＲＡＭセル２０１は、第１スイッチであるスイッチＳＷ１と、第１データ保持部である記憶部ＳＭ１と、により構成されている。ＤＲＡＭセル２０２は、第２スイッチであるスイッチＳＷ２と、第２データ保持部である記憶部ＤＭ２と、により構成されている。液晶表示素子ＬＣは、離間対向配置された光反射特性を有する画素電極である反射電極ＰＥと、光透過性を有する共通電極ＣＥとの間の空間に、液晶ＬＣＭが充填封入された公知の構造である。 The pixel 12 includes an SRAM cell 201, a DRAM cell 202, and a liquid crystal display element LC. The SRAM cell 201 is configured of a switch SW1 which is a first switch, and a storage unit SM1 which is a first data holding unit. The DRAM cell 202 includes a switch SW2 which is a second switch, and a storage unit DM2 which is a second data holding unit. The liquid crystal display element LC has a well-known structure in which a liquid crystal LCM is filled and sealed in a space between a reflective electrode PE which is a pixel electrode having light reflection characteristics and disposed to be separated and opposed, and a common electrode CE having light transparency. It is.
（ＳＲＡＭセル２０１の構成）
　スイッチＳＷ１は、例えばＮチャネルＭＯＳ型トランジスタ（以下、ＮＭＯＳトランジスタという）ＭＮ１により構成されている。スイッチＳＷ１を構成するＮＭＯＳトランジスタＭＮ１では、ソースが記憶部ＳＭ１の入力端子（ノードａ）に接続され、ドレインが列データ線ｄに接続され、ゲートが行走査線ｇに接続されている。 (Configuration of SRAM cell 201)
The switch SW1 is configured of, for example, an N-channel MOS transistor (hereinafter, referred to as an NMOS transistor) MN1. In the NMOS transistor MN1 configuring the switch SW1, the source is connected to the input terminal (node a) of the storage unit SM1, the drain is connected to the column data line d, and the gate is connected to the row scanning line g.
　記憶部ＳＭ１は、一方の出力端子が他方の入力端子に接続された２つのインバータＩＮＶ１１，ＩＮＶ１２からなる自己保持型メモリである。より具体的には、インバータＩＮＶ１１の入力端子は、インバータＩＮＶ１２の出力端子及びスイッチＳＷ１を構成するＮＭＯＳトランジスタＭＮ１のソースに接続されている。インバータＩＮＶ１２の入力端子は、スイッチＳＷ２及びインバータＩＮＶ１１の出力端子に接続されている。 The storage unit SM1 is a self-holding memory including two inverters INV11 and INV12 in which one output terminal is connected to the other input terminal. More specifically, the input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the source of the NMOS transistor MN1 forming the switch SW1. The input terminal of the inverter INV12 is connected to the switch SW2 and the output terminal of the inverter INV11.
　図３は、インバータＩＮＶ１１の具体的構成を示す回路図である。
　図３に示すように、インバータＩＮＶ１１は、直列接続されたＰチャネルＭＯＳ型トランジスタ（以下、ＰＭＯＳトランジスタという）ＭＰ１１及びＮＭＯＳトランジスタＭＮ１１を有し、それぞれのゲートに供給された入力信号を反転してそれぞれのドレインから出力する公知のＣＭＯＳインバータである。同じく、インバータＩＮＶ１２は、直列接続されたＰＭＯＳトランジスタＭＰ１２及びＮＭＯＳトランジスタＭＮ１２を有し、それぞれのゲートに供給された入力信号を反転してそれぞれのドレインから出力する公知のＣＭＯＳインバータである。 FIG. 3 is a circuit diagram showing a specific configuration of the inverter INV11.
As shown in FIG. 3, the inverter INV11 includes a P-channel MOS transistor (hereinafter referred to as a PMOS transistor) MP11 and an NMOS transistor MN11 connected in series, and inverts the input signals supplied to the respective gates. Is a known CMOS inverter that outputs from the drain of Similarly, the inverter INV12 is a known CMOS inverter that includes a PMOS transistor MP12 and an NMOS transistor MN12 connected in series, and inverts an input signal supplied to each gate and outputs the inverted signal from each drain.
　ここで、インバータＩＮＶ１１，ＩＮＶ１２の駆動能力は異なる。具体的には、記憶部ＳＭ１を構成するインバータＩＮＶ１１，ＩＮＶ１２のうち、スイッチＳＷ１から見て入力側となるインバータＩＮＶ１１内のトランジスタＭＰ１１，ＭＮ１１の駆動能力は、スイッチＳＷ１から見て出力側となるインバータＩＮＶ１２内のトランジスタＭＰ１２，ＭＮ１２の駆動能力よりも大きい。それにより、列データ線ｄからスイッチＳＷ１を介して記憶部ＳＭ１にデータが伝搬しやすくなり、一方で、スイッチＳＷ２を介して記憶部ＤＭ２から記憶部ＳＭ１にデータが伝搬しにくくなる。 Here, the drive capabilities of the inverters INV11 and INV12 are different. Specifically, among the inverters INV11 and INV12 that constitute the storage unit SM1, the drivability of the transistors MP11 and MN11 in the inverter INV11 on the input side as viewed from the switch SW1 is the inverter on the output side as viewed from the switch SW1. It is larger than the driving capability of the transistors MP12 and MN12 in the INV12. As a result, data easily propagates from the column data line d to the storage unit SM1 via the switch SW1, while data hardly propagates from the storage unit DM2 to the storage unit SM1 via the switch SW2.
　さらに、スイッチＳＷ１を構成するＮＭＯＳトランジスタＭＮ１の駆動能力は、インバータＩＮＶ１２を構成するＮＭＯＳトランジスタＭＮ１２の駆動能力よりも大きい。それにより、例えば、列データ線ｄ上でＨレベルを示すデータを記憶部ＳＭ１に記憶させる場合、列データ線ｄからスイッチＳＷ１を介して記憶部ＳＭ１の入力端子（ノードａ）に流れる電流が、記憶部ＳＭ１の入力端子からＮＭＯＳトランジスタＭＮ１２を介して接地電圧端子ＧＮＤに流れる電流よりも大きくなるため、データを正確に記憶部ＳＭ１に記憶させることができる。 Further, the drive capability of the NMOS transistor MN1 configuring the switch SW1 is larger than the drive capability of the NMOS transistor MN12 configuring the inverter INV12. Thus, for example, when storing data indicating H level on column data line d in storage unit SM1, a current flowing from column data line d to the input terminal (node a) of storage unit SM1 via switch SW1 is Since the current flowing from the input terminal of the storage unit SM1 to the ground voltage terminal GND via the NMOS transistor MN12 is larger than the current, data can be accurately stored in the storage unit SM1.
（ＤＲＡＭセル２０２の構成）
　スイッチＳＷ２は、並列接続されたＮＭＯＳトランジスタＭＮ２及びＰＭＯＳトランジスタＭＰ２からなる公知のトランスミッションゲートである。より具体的には、ＮＭＯＳトランジスタＭＮ２及びＰＭＯＳトランジスタＭＰ２では、それぞれのソースが記憶部ＳＭ１の出力端子に共通接続され、それぞれのドレインが記憶部ＤＭ２の入力端子及び液晶表示素子ＬＣの反射電極ＰＥに共通接続されている。そして、ＮＭＯＳトランジスタＭＮ２のゲートは、正転トリガパルス用トリガ線ｔｒｉｇに接続され、ＰＭＯＳトランジスタＭＰ２のゲートは、反転トリガパルス用トリガ線ｔｒｉｇｂに接続されている。 (Configuration of DRAM Cell 202)
The switch SW2 is a known transmission gate composed of an NMOS transistor MN2 and a PMOS transistor MP2 connected in parallel. More specifically, in the NMOS transistor MN2 and the PMOS transistor MP2, their respective sources are commonly connected to the output terminal of the storage unit SM1, and their respective drains are the input terminal of the storage unit DM2 and the reflective electrode PE of the liquid crystal display element LC. Commonly connected. The gate of the NMOS transistor MN2 is connected to the non-inversion trigger pulse trigger line trig, and the gate of the PMOS transistor MP2 is connected to the inversion trigger pulse trigger line trigb.
　例えば、スイッチＳＷ２は、トリガ線ｔｒｉｇを介して供給される正転トリガパルスがＨレベル（トリガ線ｔｒｉｇｂを介して供給される反転トリガパルスがＬレベル）の場合にオン状態となり、記憶部ＳＭ１から読み出されたデータを記憶部ＤＭ２及び反射電極ＰＥへ転送する。また、スイッチＳＷ２は、トリガ線ｔｒｉｇを介して供給される正転トリガパルスがＬレベル（トリガ線ｔｒｉｇｂを介して供給される反転トリガパルスがＨレベル）の場合にオフ状態となり、記憶部ＳＭ１の記憶データの読み出しは行わない。 For example, the switch SW2 is turned on when the forward rotation trigger pulse supplied via the trigger line trig is at the H level (the inversion trigger pulse supplied via the trigger line trigb is at the L level), and from the storage unit SM1 The read data is transferred to the storage unit DM2 and the reflective electrode PE. The switch SW2 is turned off when the forward rotation trigger pulse supplied via the trigger line trig is at L level (the inversion trigger pulse supplied via the trigger line trigb is at H level), and the switch SW2 Reading stored data is not performed.
　スイッチＳＷ２は、公知のトランスミッションゲートであるため、オン状態において接地電圧ＧＮＤから電源電圧ＶＤＤまでの広範囲の電圧を転送することができる。より具体的には、記憶部ＳＭ１からトランジスタＭＮ２，ＭＰ２のソースに印加される電圧が接地電圧ＧＮＤレベル（Ｌレベル）の場合、ＰＭＯＳトランジスタＭＰ２のソース・ドレインが導通しない代わりに、ＮＭＯＳトランジスタＭＮ２のソース・ドレインは低抵抗で導通することができる。一方、記憶部ＳＭ１からトランジスタＭＮ２，ＭＰ２のソースに印加される電圧が電源電圧ＶＤＤレベル（Ｈレベル）の場合、ＮＭＯＳトランジスタＭＮ２のソース・ドレインが導通しない代わりに、ＰＭＯＳトランジスタＭＰ２のソース・ドレインは低抵抗で導通することができる。このように、スイッチＳＷ２では、トランスミッションゲートのソース・ドレインが低抵抗で導通することができるため、オン状態において接地電圧ＧＮＤから電源電圧ＶＤＤまでの広範囲の電圧を転送することができる。 Since switch SW2 is a known transmission gate, it can transfer a wide range of voltage from ground voltage GND to power supply voltage VDD in the on state. More specifically, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the ground voltage GND level (L level), instead of the source / drain of the PMOS transistor MP2 not conducting, The source and drain can be conducted with low resistance. On the other hand, when the voltage applied from the storage unit SM1 to the sources of the transistors MN2 and MP2 is at the power supply voltage VDD level (H level), the source and drain of the PMOS transistor MP2 are It can be conducted with low resistance. As described above, in the switch SW2, since the source and drain of the transmission gate can be conducted with low resistance, a wide range of voltages from the ground voltage GND to the power supply voltage VDD can be transferred in the on state.
　記憶部ＤＭ２は、容量Ｃ１により構成されている。容量Ｃ１には、例えば、配線間で容量を形成するＭＩＭ（Ｍｅｔａｌ　Ｉｎｓｕｌａｔｏｒ　Ｍｅｔａｌ）容量、基板－ポリシリコン間で容量を形成するＤｉｆｆｕｓｉｏｎ容量、又は、２層ポリシリコン間で容量を形成するＰＩＰ（Ｐｏｌｙ　Ｉｎｓｕｌａｔｏｒ　Ｐｏｌｙ）容量等を用いることができる。 The storage unit DM2 is configured of a capacity C1. The capacitance C1 may be, for example, an MIM (Metal Insulator Metal) capacitance that forms a capacitance between interconnections, a Diffusion capacitance that forms a capacitance between the substrate and polysilicon, or a PIP (Poly) that forms a capacitance between two-layer polysilicon. Insulator Poly) capacity etc. can be used.
　スイッチＳＷ２がオンすると、記憶部ＳＭ１に記憶されたデータが読み出され、スイッチＳＷ２を介して、記憶部ＤＭ２内の容量Ｃ１及び反射電極ＰＥへ転送される。それにより、記憶部ＤＭ２に記憶されたデータが書き換えられる。 When the switch SW2 is turned on, the data stored in the storage unit SM1 is read out and transferred to the capacitance C1 and the reflective electrode PE in the storage unit DM2 via the switch SW2. Thereby, the data stored in the storage unit DM2 is rewritten.
　ここで、スイッチＳＷ２がオンしている場合、容量Ｃ１に保持されたデータは記憶部ＳＭ１を構成するインバータＩＮＶ１２の入力ゲートにも影響を与える。しかしながら、インバータＩＮＶ１１の駆動能力をインバータＩＮＶ１２の駆動能力より大きくしているため、インバータＩＮＶ１２が容量Ｃ１のデータの影響を受ける前に、インバータＩＮＶ１１が容量Ｃ１のデータを書き換えてしまう。したがって、容量Ｃ１の保持データによって記憶部ＳＭ１のデータが意図せず書き換えられてしまうことはない。 Here, when the switch SW2 is turned on, the data held in the capacitor C1 also affects the input gate of the inverter INV12 that configures the storage unit SM1. However, since the drive capacity of the inverter INV11 is larger than the drive capacity of the inverter INV12, the inverter INV11 rewrites the data of the capacity C1 before the inverter INV12 is affected by the data of the capacity C1. Therefore, the data stored in the storage unit SM1 is not unintentionally rewritten due to the stored data of the capacity C1.
　このように、本実施の形態に係る反射型液晶表示装置１０は、ＳＲＡＭセル及びＤＲＡＭセルを１つずつ備えた画素１２を用いることにより、ＳＲＡＭセルを２つ備えた画素を用いる場合よりも、画素を構成するトランジスタの数を少なくして、画素の小型化を実現している。 Thus, the reflective liquid crystal display device 10 according to the present embodiment uses the pixel 12 including one SRAM cell and one DRAM cell, as compared to the case where a pixel including two SRAM cells is used, By reducing the number of transistors constituting a pixel, miniaturization of the pixel is realized.
　本実施の形態では、スイッチＳＷ２がＰＭＯＳトランジスタＭＰ２及びＮＭＯＳトランジスタＭＮ２により構成される場合について説明したが、これに限られない。スイッチＳＷ２は、ＰＭＯＳトランジスタＭＰ２及びＮＭＯＳトランジスタＭＮ２の何れか一つが設けられた構成に適宜変更可能である。その場合、トリガ線ｔｒｉｇ，ｔｒｉｇｂの一方のみが設けられることとなる。 Although the case where the switch SW2 is configured by the PMOS transistor MP2 and the NMOS transistor MN2 has been described in the present embodiment, the present invention is not limited to this. The switch SW2 can be appropriately changed to a configuration in which any one of the PMOS transistor MP2 and the NMOS transistor MN2 is provided. In that case, only one of the trigger lines trig and trigb is provided.
　なお、反射型液晶表示装置１０は、画素を構成するトランジスタの数を少なくすることで画素の小型化を実現できるだけでなく、以下に説明するように記憶部ＳＭ１，ＤＭ２及び反射電極ＰＥを素子の高さ方向に有効に配置することによっても画素の小型化を実現することができる。以下、図４を用いて、詳細に説明する。 In the reflective liquid crystal display device 10, not only can the miniaturization of the pixel be realized by reducing the number of transistors constituting the pixel, but as will be described below, the storage portions SM1 and DM2 and the reflective electrode PE are elements. Pixels can be miniaturized also by arranging them effectively in the height direction. Hereinafter, this will be described in detail with reference to FIG.
（画素１２の断面構造）
　図４は、画素１２の要部を示す概略断面図である。また、図４では、容量Ｃ１が配線間で容量を形成するＭＩＭにより構成された場合を例に説明する。 (Sectional structure of pixel 12)
FIG. 4 is a schematic cross-sectional view showing the main part of the pixel 12. Further, in FIG. 4, a case where the capacitor C1 is formed by an MIM which forms a capacitor between the wirings will be described as an example.
　図４に示すように、シリコン基板１００上にはＮウエル１０１及びＰウエル１０２が形成されている。 As shown in FIG. 4, an N well 101 and a P well 102 are formed on a silicon substrate 100.
　Ｎウエル１０１上には、スイッチＳＷ２のＰＭＯＳトランジスタＭＰ２、及び、インバータＩＮＶ１１のＰＭＯＳトランジスタＭＰ１１が形成されている。より具体的には、Ｎウエル１０１上には、ＰＭＯＳトランジスタＭＰ２，ＭＰ１１のそれぞれのソースとなる共通拡散層、及び、ドレインとなる２つの拡散層が形成され、共通拡散層と２つの拡散層との間のチャネル領域上には、ＰＭＯＳトランジスタＭＰ２，ＭＰ１１のそれぞれのゲートとなるポリシリコンがゲート酸化膜を介して形成されている。 On the N well 101, the PMOS transistor MP2 of the switch SW2 and the PMOS transistor MP11 of the inverter INV11 are formed. More specifically, a common diffusion layer serving as the source of each of the PMOS transistors MP2 and MP11 and two diffusion layers serving as the drain are formed on the N well 101, and the common diffusion layer and the two diffusion layers are formed. On the channel region between them, polysilicon serving as the gate of each of the PMOS transistors MP2 and MP11 is formed via the gate oxide film.
　Ｐウエル１０２上には、スイッチＳＷ２のＮＭＯＳトランジスタＭＮ２、及び、インバータＩＮＶ１１のＮＭＯＳトランジスタＭＮ１１が形成されている。より具体的には、Ｐウエル１０２上には、ＮＭＯＳトランジスタＭＮ２，ＭＮ１１のそれぞれのソースとなる共通拡散層、及び、ドレインとなる２つの拡散層が形成され、共通拡散層と２つの拡散層との間のチャネル領域上には、ＮＭＯＳトランジスタＭＮ２，ＭＮ１１のそれぞれのゲートとなるポリシリコンがゲート酸化膜を介して形成されている。 On the P well 102, an NMOS transistor MN2 of the switch SW2 and an NMOS transistor MN11 of the inverter INV11 are formed. More specifically, a common diffusion layer serving as the source of each of the NMOS transistors MN2 and MN11 and two diffusion layers serving as the drain are formed on the P well 102, and the common diffusion layer and the two diffusion layers are formed. On the channel region between them, polysilicon serving as the gate of each of the NMOS transistors MN2 and MN11 is formed via the gate oxide film.
　なお、Ｎウエル上の活性領域（拡散層及びチャネル領域）と、Ｐウエル上の活性領域と、の間には、素子分離酸化膜１０３が形成されている。 A device isolation oxide film 103 is formed between the active region (diffusion layer and channel region) on the N well and the active region on the P well.
　トランジスタＭＰ２，ＭＰ１１，ＭＮ２，ＭＮ１１の上方には、層間絶縁膜１０５をメタル間に介在させて第１メタル１０６、第２メタル１０８、第３メタル１１０、ＭＩＭ電極１１２、第４メタル１１４、及び、第５メタル１１６が積層されている。 An interlayer insulating film 105 is interposed between metals above the transistors MP2, MP11, MN2, and MN11, and the first metal 106, the second metal 108, the third metal 110, the MIM electrode 112, the fourth metal 114, and The fifth metal 116 is stacked.
　第５メタル１１６は、画素毎に形成される反射電極ＰＥを構成している。 The fifth metal 116 constitutes a reflective electrode PE formed for each pixel.
　トランジスタＭＮ２，ＭＰ２の各ドレインを構成する各拡散層は、コンタクト１１８、第１メタル１０６、スルーホール１１９ａ、第２メタル１０８、スルーホール１１９ｂ、第３メタル１１０、スルーホール１１９ｃ、第４メタル１１４、及び、スルーホール１１９ｅを介して、第５メタル１１６に電気的に接続されている。さらに、トランジスタＭＮ２，ＭＰ２の各ドレインを構成する各拡散層は、コンタクト１１８、第１メタル１０６、スルーホール１１９ａ、第２メタル１０８、スルーホール１１９ｂ、第３メタル１１０、スルーホール１１９ｃ、第４メタル１１４、及び、スルーホール１１９ｄを介してＭＩＭ電極１１２に電気的に接続されている。即ち、スイッチＳＷ２を構成するトランジスタＭＮ２，ＭＰ２の各ソースは、反射電極ＰＥ及びＭＩＭ電極１１２に電気的に接続されている。 The diffusion layers constituting the drains of the transistors MN2 and MP2 are the contact 118, the first metal 106, the through hole 119a, the second metal 108, the through hole 119b, the third metal 110, the through hole 119c, the fourth metal 114, And, the through holes 119 e are electrically connected to the fifth metal 116. Further, the diffusion layers constituting the drains of the transistors MN2 and MP2 are the contact 118, the first metal 106, the through hole 119a, the second metal 108, the through hole 119b, the third metal 110, the through hole 119c, the fourth metal It is electrically connected to the MIM electrode 112 through the through hole 119 d and the through hole 119 d. That is, the sources of the transistors MN2 and MP2 constituting the switch SW2 are electrically connected to the reflective electrode PE and the MIM electrode 112.
　反射電極ＰＥ（第５メタル１１６）は、その上面に形成された保護膜であるパッシベーション膜（ＰＳＶ）１１７を介して、透明電極である共通電極ＣＥに離間対向配置されている。反射電極ＰＥと共通電極ＣＥとの間には、液晶ＬＣＭが充填封止されている。反射電極ＰＥ、共通電極ＣＥ、及び、それらの間の液晶ＬＣＭによって液晶表示素子ＬＣが構成される。 The reflective electrode PE (fifth metal 116) is disposed to face the common electrode CE, which is a transparent electrode, through a passivation film (PSV) 117, which is a protective film formed on the upper surface of the reflective electrode PE. A liquid crystal LCM is filled and sealed between the reflective electrode PE and the common electrode CE. A liquid crystal display element LC is configured by the reflective electrode PE, the common electrode CE, and the liquid crystal LCM between them.
　ここで、ＭＩＭ電極１１２は、第３メタル１１０上に層間絶縁膜１０５を介して形成されている。このＭＩＭ電極１１２、第３メタル１１０、及び、それらの間の層間絶縁膜１０５によって容量Ｃ１が構成される。そのため、スイッチＳＷ１，ＳＷ２及び記憶部ＳＭ１が、第１，２層配線である第１メタル１０６及び第２メタル１０８と、トランジスタと、を用いて形成されるのに対し、記憶部ＤＭ２は、それらの上層である第３メタル１１０及びＭＩＭ電極１１２を用いて形成されることとなる。つまり、スイッチＳＷ１，ＳＷ２及び記憶部ＳＭ１と、記憶部ＤＭ２とは、それぞれ異なる層にて形成されることとなる。 Here, the MIM electrode 112 is formed on the third metal 110 via the interlayer insulating film 105. A capacitance C1 is formed by the MIM electrode 112, the third metal 110, and the interlayer insulating film 105 between them. Therefore, while the switches SW1 and SW2 and the storage unit SM1 are formed using the first metal 106 and the second metal 108, which are the first and second layer wirings, and the transistor, the storage unit DM2 Is formed using the third metal 110 and the MIM electrode 112 which are upper layers of That is, the switches SW1 and SW2, the storage unit SM1, and the storage unit DM2 are formed in different layers.
　図示しない光源からの光は、共通電極ＣＥ及び液晶ＬＣＭを透過して反射電極ＰＥ（第５メタル１１６）に入射して反射され、元の入射経路を逆進して共通電極ＣＥを通して出射される。 Light from a light source (not shown) is transmitted through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE (fifth metal 116) and is reflected, and travels backward along the original incident path and is emitted through the common electrode CE .
　このように、反射型液晶表示装置１０は、第５層配線である第５メタル１１６を反射電極ＰＥとして用い、第３層配線である第３メタル１１０を記憶部ＤＭ２の一部として用い、第１，２層配線である第１メタル１０６及び第２メタル１０８とトランジスタとを記憶部ＳＭ１等として用いることで、記憶部ＳＭ１、記憶部ＤＭ２及び反射電極ＰＥを高さ方向に有効に配置することが可能になるため、画素をさらに小型化することができる。それにより、例えば、３μｍ以下のピッチの画素を電源電圧３．３Ｖのトランジスタで構成できる。この３μｍ以下のピッチの画素を用いることで、対角の長さ０．５５インチの横方向４０００画素、縦方向２０００画素の液晶表示パネルを実現できる。 Thus, the reflective liquid crystal display device 10 uses the fifth metal 116, which is the fifth layer wiring, as the reflective electrode PE, and uses the third metal 110, which is the third layer wiring, as a part of the storage unit DM2. By using the first metal 106 and the second metal 108, which are the first and second layer wiring, and the transistor as the memory unit SM1 or the like, the memory unit SM1, the memory unit DM2 and the reflective electrode PE are effectively arranged in the height direction. This makes it possible to further miniaturize the pixel. Thus, for example, a pixel with a pitch of 3 μm or less can be configured by a transistor with a power supply voltage of 3.3V. By using the pixels with a pitch of 3 μm or less, it is possible to realize a liquid crystal display panel having a diagonal length of 0.55 inch, 4000 horizontal pixels and 2000 vertical pixels.
（反射型液晶表示装置１０の動作）
　次に、図５を用いて、反射型液晶表示装置１０の動作について説明する。
　図５は、反射型液晶表示装置１０の動作を示すタイミングチャートである。 (Operation of reflective liquid crystal display device 10)
Next, the operation of the reflective liquid crystal display device 10 will be described with reference to FIG.
FIG. 5 is a timing chart showing the operation of the reflective liquid crystal display device 10.
　前述したように、反射型液晶表示装置１０では、垂直シフトレジスタ１４からの行走査信号により、行走査線ｇ１～ｇｍが１本ずつ１Ｈ単位で順次選択されていくため、画像表示部１１を構成する複数の画素１２には、選択された行走査線に共通に接続された１行のｎ個の画素単位でデータが書き込まれる。そして、画像表示部１１を構成する複数の画素１２の全てにデータが書き込まれると、その後、トリガパルスＴＲＩ，ＴＲＩＢに基づき、全ての画素１２のデータが一斉に読み出される（より具体的には、全ての画素１２内の記憶部ＳＭ１のデータが一斉に記憶部ＤＭ２及び反射電極ＰＥに転送される）。 As described above, in the reflective liquid crystal display device 10, the row scanning signals g1 to gm are sequentially selected one by one in units of 1 H by the row scanning signal from the vertical shift register 14. Therefore, the image display unit 11 is configured. Data is written to the plurality of pixels 12 in units of n pixels in one row commonly connected to the selected row scanning line. Then, when data is written to all of the plurality of pixels 12 constituting the image display unit 11, thereafter, the data of all the pixels 12 are read out simultaneously based on the trigger pulses TRI and TRIB (more specifically, The data of the storage unit SM1 in all the pixels 12 are simultaneously transferred to the storage unit DM2 and the reflective electrode PE).
　図５の（Ａ）は、各画素１２に記憶されるサブフレームデータの変化を示している。なお、縦軸が行番号を表し、横軸が時間を表している。図５の（Ａ）に示すように、サブフレームデータの境界線は右下がりとなっている。これは、行番号の大きな画素ほどサブフレームデータが遅れて書き込まれることを表している。この境界線の一端から他端までの期間がサブフレームデータの書き込み期間に相当する。なお、Ｂ０ｂ，Ｂ１ｂ，Ｂ２ｂは、それぞれビットＢ０，Ｂ１，Ｂ２のサブフレームデータの反転データを示している。 (A) of FIG. 5 shows a change of subframe data stored in each pixel 12. The vertical axis represents line numbers, and the horizontal axis represents time. As shown in (A) of FIG. 5, the boundary line of the sub-frame data is downward to the right. This means that the subframe data is written later as the row number of the pixel is larger. A period from one end of the boundary to the other end corresponds to a writing period of subframe data. B0b, B1b, and B2b indicate inverted data of subframe data of bits B0, B1, and B2, respectively.
　図５の（Ｂ）は、トリガパルスＴＲＩの出力タイミング（立ち上がりタイミング）を示している。なお、トリガパルスＴＲＩＢは、常にトリガパルスＴＲＩを論理反転した値を示すため、省略されている。図５の（Ｃ）は、反射電極ＰＥに印加されるサブフレームデータのビットを模式的に示している。図５の（Ｄ）は、共通電極電圧Ｖｃｏｍの値の変化を示している。図５の（Ｅ）は、液晶ＬＣＭに印加される電圧の変化を示している。 (B) of FIG. 5 shows the output timing (rising timing) of the trigger pulse TRI. The trigger pulse TRIB is omitted because it always indicates a value obtained by logically inverting the trigger pulse TRI. FIG. 5C schematically shows bits of subframe data applied to the reflective electrode PE. (D) of FIG. 5 shows the change of the value of the common electrode voltage Vcom. (E) of FIG. 5 shows the change of the voltage applied to the liquid crystal LCM.
　まず、行走査信号により選択された画素１２では、スイッチＳＷ１がオンするため、水平ドライバ１６から列データ線ｄに出力されたビットＢ０の正転サブフレームデータが、スイッチＳＷ１によりサンプリングされて記憶部ＳＭ１に書き込まれる。同様にして、画像表示部１１を構成する全ての画素１２の記憶部ＳＭ１に対してビットＢ０の正転サブフレームデータが書き込まれる。その後、画像表示部１１を構成する全ての画素１２に対してＨレベルのトリガパルスＴＲＩ（及びＬレベルのトリガパルスＴＲＩＢ）が同時に供給される（時刻Ｔ１）。 First, in the pixel 12 selected by the row scanning signal, since the switch SW1 is turned on, the non-inverted subframe data of bit B0 output from the horizontal driver 16 to the column data line d is sampled by the switch SW1 and stored Written to SM1. Similarly, normal subframe data of bit B0 is written to the storage units SM1 of all the pixels 12 constituting the image display unit 11. Thereafter, the trigger pulse TRI at the H level (and the trigger pulse TRIB at the L level) is simultaneously supplied to all the pixels 12 constituting the image display unit 11 (time T1).
　これにより、全ての画素１２のスイッチＳＷ２がオンするため、記憶部ＳＭ１に記憶されているビットＢ０の正転サブフレームデータがスイッチＳＷ２を通して記憶部ＤＭ２に一斉に転送されて保持されるとともに、ビットＢ０の正転サブフレームデータが反射電極ＰＥに印加される。ここで、図５の（Ｃ）を見てもわかるように、記憶部ＤＭ２によるビットＢ０の正転サブフレームデータの保持期間（反射電極ＰＥへのビットＢ０の正転サブフレームデータの印加期間）は、トリガパルスＴＲＩがＨレベルとなってから（時刻Ｔ１）、次に再びＨレベルとなるまで（時刻Ｔ２）の１サブフレーム期間である。 As a result, since the switches SW2 of all the pixels 12 are turned on, the forward subframe data of the bit B0 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held. The forward subframe data of B0 is applied to the reflective electrode PE. Here, as can be understood also from FIG. 5C, a holding period of non-inverted subframe data of bit B0 by storage unit DM2 (application period of non-inverted subframe data of bit B0 to reflective electrode PE) Is one subframe period of time (time T2) until trigger signal TRI becomes H level (time T1) and then becomes H level again next time.
　ここで、サブフレームデータのビット値が「１」、すなわちＨレベルのときには反射電極ＰＥには電源電圧ＶＤＤ（ここでは３．３Ｖ）が印加され、ビット値が「０」、すなわちＬレベルのときには反射電極ＰＥには接地電圧ＧＮＤ（０Ｖ）が印加される。一方、共通電極ＣＥには、接地電圧ＧＮＤ及び電源電圧ＶＤＤに制限されることなく、自由な電圧が共通電極電圧Ｖｃｏｍとして印加できるようになっており、Ｈレベルの正転トリガパルスＴＲＩの入力に同期して共通電極電圧Ｖｃｏｍが所定電圧に切り替わるように制御される。本例では、共通電極電圧Ｖｃｏｍは、ビットＢ０の正転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間中、図５（Ｄ）に示すように、０Ｖよりも液晶の閾値電圧Ｖｔｔだけ低い電圧に設定される。 Here, when the bit value of subframe data is "1", that is, H level, the power supply voltage VDD (here, 3.3 V) is applied to the reflective electrode PE, and when the bit value is "0", that is, L level The ground voltage GND (0 V) is applied to the reflective electrode PE. On the other hand, a free voltage can be applied to the common electrode CE as the common electrode voltage Vcom without being limited to the ground voltage GND and the power supply voltage VDD, and an H level normal rotation trigger pulse TRI is input. The common electrode voltage Vcom is controlled to be switched to a predetermined voltage in synchronization. In this example, the common electrode voltage Vcom is the threshold voltage Vtt of the liquid crystal more than 0 V as shown in FIG. 5D during the sub-frame period in which the non-inverted sub-frame data of bit B0 is applied to the reflective electrode PE. It is set to a low voltage.
　液晶表示素子ＬＣは、反射電極ＰＥの印加電圧と共通電極電圧Ｖｃｏｍとの差電圧の絶対値である液晶ＬＣＭの印加電圧に応じた階調表示を行う。したがって、ビットＢ０の正転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間（時刻Ｔ１～Ｔ２）では、液晶ＬＣＭの印加電圧は、図５（Ｅ）に示すように、サブフレームデータのビット値が「１」のときは３．３Ｖ＋Ｖｔｔ（＝３．３Ｖ－（－Ｖｔｔ））となり、サブフレームデータのビット値が「０」のときは＋Ｖｔｔ（＝０Ｖ－（－Ｖｔｔ））となる。 The liquid crystal display element LC performs gradation display according to the applied voltage of the liquid crystal LCM, which is the absolute value of the difference voltage between the applied voltage of the reflective electrode PE and the common electrode voltage Vcom. Therefore, in the sub-frame period (time T1 to T2) in which the non-inverted sub-frame data of bit B0 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is, as shown in FIG. When the bit value is “1”, it is 3.3V + Vtt (= 3.3V − (− Vtt)), and when the bit value of subframe data is “0”, it is + Vtt (= 0V − (− Vtt)) .
　図６は、液晶の印加電圧（ＲＭＳ電圧）と液晶のグレースケール値との関係を示す。
　図６を参照すると、グレースケール値曲線は、黒のグレースケール値が液晶の閾値電圧ＶｔｔのＲＭＳ電圧に対応し、かつ、白のグレースケール値が液晶の飽和電圧Ｖｓａｔ（＝３．３Ｖ＋Ｖｔｔ）のＲＭＳ電圧に対応するようにシフトされる。グレースケール値を液晶応答曲線の有効部分に一致させることが可能である。したがって、液晶表示素子ＬＣは上記のように液晶ＬＣＭの印加電圧が（３．３Ｖ＋Ｖｔｔ）のときは白を表示し、＋Ｖｔｔのときは黒を表示する。 FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal and the gray scale value of the liquid crystal.
Referring to FIG. 6, in the gray scale value curve, the gray scale value of black corresponds to the RMS voltage of the threshold voltage Vtt of the liquid crystal, and the gray scale value of white is the saturation voltage Vsat of the liquid crystal (= 3.3 V + Vtt). It is shifted to correspond to the RMS voltage. It is possible to match the gray scale values to the active part of the liquid crystal response curve. Therefore, as described above, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3 V + Vtt), and displays black when + Vtt.
　図５に戻り、液晶表示素子ＬＣがビットＢ０の正転サブフレームデータを表示しているサブフレーム期間（時刻Ｔ１～Ｔ２）において、画像表示部１１を構成する全ての画素１２の記憶部ＳＭ１に対するビットＢ０の反転サブフレームデータの書き込みが順次開始される。そして、画像表示部１１を構成する全ての画素１２の記憶部ＳＭ１に対してビットＢ０の反転サブフレームデータが書き込まれると、その後、画像表示部１１を構成する全ての画素１２に対してＨレベルのトリガパルスＴＲＩ（及びＬレベルのトリガパルスＴＲＩＢ）が同時に供給される（時刻Ｔ２）。 Returning to FIG. 5, in the sub-frame period (time T1 to T2) in which the liquid crystal display element LC is displaying the non-inverted sub-frame data of bit B0, the storage portion SM1 of all the pixels 12 constituting the image display portion 11 is Writing of the inverted subframe data of bit B0 is sequentially started. Then, when the inverted subframe data of bit B0 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, the H level is then applied to all the pixels 12 constituting the image display unit 11. The trigger pulse TRI (and the L level trigger pulse TRIB) are simultaneously supplied (time T2).
　これにより、全ての画素１２のスイッチＳＷ２がオンするため、記憶部ＳＭ１に記憶されているビットＢ０の反転サブフレームデータがスイッチＳＷ２を通して記憶部ＤＭ２に一斉に転送されて保持されるとともに、ビットＢ０の反転サブフレームデータが反射電極ＰＥに印加される。ここで、図５の（Ｃ）を見てもわかるように、記憶部ＤＭ２によるビットＢ０の反転サブフレームデータの保持期間（反射電極ＰＥへのビットＢ０の反転サブフレームデータの印加期間）は、トリガパルスＴＲＩがＨレベルとなってから（時刻Ｔ２）、次に再びＨレベルとなるまで（時刻Ｔ３）の１サブフレーム期間である。ここで、ビットＢ０の反転サブフレームデータはビットＢ０の正転サブフレームデータと常に逆論理値の関係にあるため、ビットＢ０の正転サブフレームデータが「１」のときは「０」、ビットＢ０の正転サブフレームデータが「０」のときは「１」である。 As a result, since the switches SW2 of all the pixels 12 are turned on, the inverted subframe data of the bit B0 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held. Inverted subframe data is applied to the reflective electrode PE. Here, as can be understood also from FIG. 5C, the holding period of the inverted subframe data of bit B0 by storage unit DM2 (the application period of the inverted subframe data of bit B0 to reflective electrode PE) is This is one subframe period (time T3) from when the trigger pulse TRI turns to H level (time T2) to next time it turns to H level again (time T3). Here, since the inverted subframe data of bit B0 always has an inverse logical value relationship with the non-inverted subframe data of bit B0, “0” when the non-inverted subframe data of bit B0 is “1”. It is "1" when the non-inverted subframe data of B0 is "0".
　一方、共通電極電圧Ｖｃｏｍは、ビットＢ０の反転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間中、図５（Ｄ）に示すように、３．３Ｖよりも液晶の閾値電圧Ｖｔｔだけ高い電圧に設定される。したがって、ビットＢ０の反転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間（時刻Ｔ２～Ｔ３）では、液晶ＬＣＭの印加電圧は、サブフレームデータのビット値が「１」のときは－Ｖｔｔ（＝３．３Ｖ－（３．３Ｖ＋Ｖｔｔ））となり、サブフレームデータのビット値が「０」のときは－３．３Ｖ－Ｖｔｔ（＝０Ｖ－（３．３Ｖ＋Ｖｔｔ））となる。 On the other hand, as shown in FIG. 5D, the common electrode voltage Vcom is higher than 3.3 V by the threshold voltage Vtt of the liquid crystal during the sub-frame period in which the inverted sub-frame data of the bit B0 is applied to the reflective electrode PE. Set to voltage. Therefore, in the sub-frame period (time T2 to T3) in which the inverted sub-frame data of bit B0 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is -Vtt when the bit value of the sub-frame data is "1". (= 3.3 V-(3.3 V + Vtt)), and when the bit value of subframe data is "0",-3.3 V-Vtt (= 0 V-(3.3 V + Vtt)).
　例えば、ビットＢ０の正転サブフレームデータのビット値が「１」であった場合には続いて印加されるビットＢ０の反転サブフレームデータのビット値は「０」となる。このとき、液晶ＬＣＭの印加電圧は、－（３．３Ｖ＋Ｖｔｔ）となり、ビットＢ０の正転サブフレームデータが印加されたときと比較して、電位の方向が逆になるが絶対値が同じになる。そのため、画素１２は、ビットＢ０の反転サブフレームデータが印加されたときも、ビットＢ０の正転フレームデータが印加されたときと同様に、白を表示する。また、ビットＢ０の正転サブフレームデータのビット値が「０」であった場合には続いて印加されるビットＢ０の反転サブフレームデータのビット値は「１」となる。このとき、液晶ＬＣＭの印加電圧は、－Ｖｔｔとなり、ビットＢ０の正転サブフレームデータが印加されたときと比較して、電位の方向が逆になるが絶対値が同じになる。そのため、画素１２は、ビットＢ０の反転サブフレームデータが印加されたときも、ビットＢ０の正転フレームデータが印加されたときと同様に、黒を表示する。 For example, when the bit value of the non-inverted subframe data of bit B0 is "1", the bit value of the inverted subframe data of bit B0 applied subsequently is "0". At this time, the voltage applied to the liquid crystal LCM is − (3.3 V + Vtt), and the direction of the potential is opposite but the absolute value is the same as compared with the case where the non-inverted subframe data of bit B0 is applied. . Therefore, also when the inverted subframe data of bit B0 is applied, the pixel 12 displays white in the same manner as when the non-inverted frame data of bit B0 is applied. When the bit value of the non-inverted subframe data of bit B0 is "0", the bit value of the inverted subframe data of bit B0 applied subsequently is "1". At this time, the voltage applied to the liquid crystal LCM is −Vtt, and the direction of the potential is opposite but the absolute value is the same as compared with the case where the non-inverted subframe data of bit B0 is applied. Therefore, also when the inverted subframe data of bit B0 is applied, the pixel 12 displays black in the same manner as when the non-inverted frame data of bit B0 is applied.
　したがって、画素１２は、図５の（Ｅ）に示すように、時刻Ｔ１～Ｔ３の２サブフレーム期間中、ビットＢ０とビットＢ０の相補ビットＢ０ｂとで同じ階調を表示するとともに、液晶ＬＣＭの電位方向がサブフレーム毎に反転する交流駆動を行うため、液晶ＬＣＭの焼き付きを防止することができる。 Therefore, as shown in (E) of FIG. 5, the pixel 12 displays the same gradation with the bit B0 and the complementary bit B0b of the bit B0 during two sub-frame periods from time T1 to T3, and Since AC driving is performed in which the potential direction is reversed every subframe, burn-in of the liquid crystal LCM can be prevented.
　続いて、液晶表示素子ＬＣがビットＢ０の反転サブフレームデータを表示しているサブフレーム期間（時刻Ｔ２～Ｔ３）において、全ての画素１２の記憶部ＳＭ１に対するビットＢ１の正転サブフレームデータの書き込みが順次開始される。そして、画像表示部１１の全画素１２の記憶部ＳＭ１に対してビットＢ１の正転サブフレームデータが書き込まれると、その後、画像表示部１１を構成するすべての画素１２に対してＨレベルのトリガパルスＴＲＩ（及びＬレベルのトリガパルスＴＲＩＢ）が同時に供給される（時刻Ｔ３）。 Subsequently, in the subframe period (time T2 to T3) in which the liquid crystal display element LC is displaying inverted subframe data of the bit B0, writing of normal subframe data of bit B1 to the storage unit SM1 of all the pixels 12 Are sequentially started. Then, when the non-inverted subframe data of bit B1 is written in the storage unit SM1 of all the pixels 12 of the image display unit 11, then, trigger of H level for all the pixels 12 constituting the image display unit 11 is performed. The pulse TRI (and the trigger pulse TRIB at L level) are simultaneously supplied (time T3).
　これにより、全ての画素１２のスイッチＳＷ２がオンするため、記憶部ＳＭ１に記憶されているビットＢ１の正転サブフレームデータがスイッチＳＷ２を通して記憶部ＤＭ２に一斉に転送されて保持されるととともに、ビットＢ１の正転サブフレームデータが反射電極ＰＥに印加される。ここで、図５の（Ｃ）を見てもわかるように、記憶部ＤＭ２によるビットＢ１の正転サブフレームデータの保持期間（反射電極ＰＥへのビットＢ１の正転サブフレームデータの印加期間）は、トリガパルスＴＲＩがＨレベルとなってから（時刻Ｔ３）、次に再びＨレベルとなるまで（時刻Ｔ４）の１サブフレーム期間である。 As a result, since the switches SW2 of all the pixels 12 are turned on, the forward subframe data of the bit B1 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held. Normal subframe data of bit B1 is applied to the reflective electrode PE. Here, as can be seen also from FIG. 5C, a holding period of non-inverted subframe data of bit B1 by storage unit DM2 (application period of non-inverted subframe data of bit B1 to reflective electrode PE) Is one subframe period of time (time T4) until trigger signal TRI becomes H level next time (time T3) and then becomes H level again.
　一方、共通電極電圧Ｖｃｏｍは、ビットＢ１の正転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間は、図５（Ｄ）に示すように、０Ｖよりも液晶の閾値電圧Ｖｔｔだけ低い電圧に設定される。したがって、ビットＢ１の正転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間（時刻Ｔ３～Ｔ４）では、液晶ＬＣＭの印加電圧は、図５（Ｅ）に示すように、サブフレームデータのビット値が「１」のときは３．３Ｖ＋Ｖｔｔ（＝３．３Ｖ－（－Ｖｔｔ））となり、サブフレームデータのビット値が「０」のときは＋Ｖｔｔ（＝０Ｖ－（－Ｖｔｔ））となる。 On the other hand, as shown in FIG. 5D, the common electrode voltage Vcom is a voltage lower than 0 V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal subframe data of bit B1 is applied to the reflective electrode PE. Set to Therefore, in the subframe period (time T3 to T4) in which the normal subframe data of bit B1 is applied to the reflective electrode PE, the voltage applied to the liquid crystal LCM is, as shown in FIG. When the bit value is “1”, it is 3.3V + Vtt (= 3.3V − (− Vtt)), and when the bit value of subframe data is “0”, it is + Vtt (= 0V − (− Vtt)) .
　続いて、液晶表示素子ＬＣがビットＢ１の正転サブフレームデータを表示しているサブフレーム期間（時刻Ｔ３～Ｔ４）において、画像表示部１１を構成する全ての画素１２の記憶部ＳＭ１に対するビットＢ１の反転サブフレームデータの書き込みが順次開始される。そして、画像表示部１１を構成する全ての画素１２の記憶部ＳＭ１に対してビットＢ１の反転サブフレームデータが書き込まれると、その後、画像表示部１１を構成する全ての画素１２に対してＨレベルのトリガパルスＴＲＩ（及びＬレベルのトリガパルスＴＲＩＢ）が同時に供給される（時刻Ｔ４）。 Subsequently, in the sub-frame period (time T3 to T4) in which the liquid crystal display element LC is displaying the non-inverted sub-frame data of bit B1, the bit B1 for the storage part SM1 of all the pixels 12 constituting the image display part 11 Writing of the inverted subframe data of is sequentially started. Then, when the inverted subframe data of bit B1 is written to the storage unit SM1 of all the pixels 12 constituting the image display unit 11, then, H level is applied to all the pixels 12 constituting the image display unit 11 The trigger pulse TRI (and the L level trigger pulse TRIB) are simultaneously supplied (time T4).
　これにより、全ての画素１２のスイッチＳＷ２がオンするため、記憶部ＳＭ１に記憶されているビットＢ１の反転サブフレームデータがスイッチＳＷ２を通して記憶部ＤＭ２に一斉に転送されて保持されるとともに、ビットＢ１の反転サブフレームデータが反射電極ＰＥに印加される。ここで、図５の（Ｃ）を見てもわかるように、記憶部ＤＭ２によるビットＢ１の反転サブフレームデータの保持期間（反射電極ＰＥへのビットＢ１の反転サブフレームデータの印加期間）は、トリガパルスＴＲＩがＨレベルとなってから（時刻Ｔ４）、次に再びＨレベルとなるまで（時刻Ｔ５）の１サブフレーム期間である。ここで、ビットＢ１の反転サブフレームデータはビットＢ１の正転サブフレームデータと常に逆論理値の関係にある。 As a result, since the switches SW2 of all the pixels 12 are turned on, the inverted subframe data of the bit B1 stored in the storage unit SM1 is simultaneously transferred to the storage unit DM2 through the switch SW2 and held. Inverted subframe data is applied to the reflective electrode PE. Here, as can be seen also from FIG. 5C, the holding period of the inverted subframe data of bit B1 by storage unit DM2 (the application period of the inverted subframe data of bit B1 to reflective electrode PE) is This is one subframe period (time T5) from when the trigger pulse TRI turns to H level (time T4) to next time it turns to H level again (time T5). Here, the inverted subframe data of bit B1 is always in a reverse logical value relationship with the non-inverted subframe data of bit B1.
　一方、共通電極電圧Ｖｃｏｍは、ビットＢ１の反転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間中、図５（Ｄ）に示すように、３．３Ｖよりも液晶の閾値電圧Ｖｔｔだけ高い電圧に設定される。したがって、ビットＢ１の反転サブフレームデータが反射電極ＰＥに印加されるサブフレーム期間（時刻Ｔ４～Ｔ５）では、液晶ＬＣＭの印加電圧は、サブフレームデータのビット値が「１」のときは－Ｖｔｔ（＝３．３Ｖ－（３．３Ｖ＋Ｖｔｔ））となり、サブフレームデータのビット値が「０」のときは－３．３Ｖ－Ｖｔｔ（＝０Ｖ－（３．３Ｖ＋Ｖｔｔ））となる。 On the other hand, as shown in FIG. 5D, the common electrode voltage Vcom is higher than 3.3 V by the threshold voltage Vtt of the liquid crystal during the sub-frame period in which the inverted sub-frame data of the bit B1 is applied to the reflective electrode PE. Set to voltage. Therefore, in the sub-frame period (time T4 to T5) in which the inverted sub-frame data of bit B1 is applied to the reflective electrode PE, the applied voltage of the liquid crystal LCM is -Vtt when the bit value of the sub-frame data is "1". (= 3.3 V-(3.3 V + Vtt)), and when the bit value of subframe data is "0",-3.3 V-Vtt (= 0 V-(3.3 V + Vtt)).
　これにより、画素１２は、図５の（Ｅ）に示すように、時刻Ｔ３～Ｔ５の２サブフレーム期間中、ビットＢ１とビットＢ１の相補ビットＢ１ｂとで同じ階調を表示するとともに、液晶ＬＣＭの電位方向がサブフレーム毎に反転する交流駆動を行うため、液晶ＬＣＭの焼き付きを防止することができる。ビットＢ２以降についても同様の動作が繰り返される。 As a result, as shown in FIG. 5E, the pixel 12 displays the same gradation with the bit B1 and the complementary bit B1b of the bit B1 during two sub-frame periods from time T3 to T5, and the liquid crystal LCM Since the potential drive direction of the liquid crystal is reversed drive every subframe, burn-in of the liquid crystal LCM can be prevented. The same operation is repeated for bit B2 and thereafter.
　このようにして、反射型液晶表示装置１０は、複数のサブフレームの組み合わせにて階調表示を行っている。 Thus, the reflective liquid crystal display device 10 performs gradation display by combining a plurality of sub-frames.
　なお、ビットＢ０と相補ビットＢ０ｂの各表示期間は同じ第１のサブフレーム期間であり、また、ビットＢ１と相補ビットＢ１ｂの各表示期間も同じ第２のサブフレーム期間であるが、第１のサブフレーム期間と第２のサブフレーム期間とは同一であるとは限らない。ここでは、一例として第２のサブフレーム期間は第１のサブフレーム期間の２倍に設定されている。また、図５（Ｅ）に示すように、ビットＢ２と相補ビットＢ２ｂの各表示期間である第３のサブフレーム期間は、第２のサブフレーム期間の２倍に設定されている。他のサブフレーム期間についても同様のことが言える。システムの仕様等に応じて、各サブフレーム期間の長さ、及び、サブフレーム数を任意に設定することができる。 Note that each display period of bit B0 and complementary bit B0b is the same first subframe period, and each display period of bit B1 and complementary bit B1b is also the same second subframe period, but the first display period is the same. The subframe period and the second subframe period are not necessarily the same. Here, as an example, the second subframe period is set to twice the first subframe period. Further, as shown in FIG. 5E, the third sub-frame period which is each display period of the bit B2 and the complementary bit B2 b is set to be twice as long as the second sub-frame period. The same is true for the other subframe periods. The length of each subframe period and the number of subframes can be arbitrarily set according to the specification of the system and the like.
（額縁部２１の詳細な説明）
　続いて、額縁部２１について説明する。額縁部２１は、例えばプロジェクター等によって画像を拡大投影する場合において、画像表示部１１によって表示される画像の外枠領域（額縁領域）に黒を表示する部である。 (Detailed Description of the Frame 21)
Subsequently, the frame portion 21 will be described. The frame unit 21 is a unit that displays black in the outer frame area (frame area) of the image displayed by the image display unit 11 when the image is enlarged and projected by, for example, a projector or the like.
　図７は、反射型液晶表示装置１０の概略平面図である。図７に示すように、反射型液晶表示装置１０では、チップＣＨＰ１上に、画像表示部１１が設けられるとともに、画像表示部１１の外周を囲むようにして額縁部２１が設けられている。なお、図示されていないが、額縁部２１の額縁電極Ｇ１の下位階層には、各画素１２を駆動する水平ドライバ１６、垂直シフトレジスタ１４、タイミングジェネレータ１３、データラッチ回路１５等が形成されている。また、チップＣＨＰ１の外周辺には、複数のパッドＰＤ１が設けられている。チップＣＨＰ１上の各機能ブロックは、複数のパッドＰＤ１及びボンディングワイヤを介して、例えばＦＰＣ(Flexible Printed Circuit)に接続されており、ＦＰＣによって構成された上位装置からの制御信号により、画像表示部１１によって映像を表示したり、額縁部２１によって黒を表示したりする。 FIG. 7 is a schematic plan view of the reflective liquid crystal display device 10. As shown in FIG. 7, in the reflective liquid crystal display device 10, the image display unit 11 is provided on the chip CHP 1, and the frame unit 21 is provided so as to surround the outer periphery of the image display unit 11. Although not shown, a horizontal driver 16 for driving each pixel 12, a vertical shift register 14, a timing generator 13, a data latch circuit 15 and the like are formed in the lower hierarchy of the frame electrode G1 of the frame portion 21. . Further, a plurality of pads PD1 are provided around the periphery of the chip CHP1. Each functional block on the chip CHP1 is connected to, for example, a flexible printed circuit (FPC) via a plurality of pads PD1 and bonding wires, and the image display unit 11 is controlled by a control signal from a host device configured by the FPC. To display an image or to display black by the frame portion 21.
　まず、額縁部２１の比較例である額縁部５１について説明する。
　図８は、比較例にかかる反射型液晶表示装置に設けられた画像表示部１１の各画素１２の反射電極ＰＥ、及び、額縁部５１の額縁電極Ｇ５の概略平面図である。図８の例では、画像表示部１１の角部に設けられた複数の画素１２のそれぞれの反射電極ＰＥ、及び、その周辺に設けられた額縁部５１の額縁電極Ｇ５のみが示されている。 First, the frame portion 51 which is a comparative example of the frame portion 21 will be described.
FIG. 8 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device according to the comparative example, and the frame electrode G5 of the frame portion 51. In the example of FIG. 8, only the reflective electrode PE of each of the plurality of pixels 12 provided at the corner of the image display unit 11 and the frame electrode G5 of the frame 51 provided at the periphery thereof are shown.
　図８に示すように、額縁電極Ｇ５は、額縁部５１の全面にわたって隙間なく広がるベタ電極であって、画素１２の反射電極ＰＥと同一階層に形成されている。なお、額縁電極Ｇ５の上層には、共通電極ＣＥが離間対向配置され、共通電極ＣＥと額縁電極Ｇ５との間には液晶ＬＣＭが充填封止されている。これら共通電極ＣＥ、額縁電極Ｇ５、及び、液晶ＬＣＭによって液晶表示素子ＬＣ＿Ｂが構成されている。 As shown in FIG. 8, the frame electrode G <b> 5 is a solid electrode that spreads without a gap over the entire surface of the frame portion 51 and is formed in the same layer as the reflective electrode PE of the pixel 12. In the upper layer of the frame electrode G5, the common electrode CE is disposed to be separated and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and the frame electrode G5. A liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G5, and the liquid crystal LCM.
　ここで、額縁電極Ｇ５には、共通電極ＣＥと同じ電圧Ｖｃｏｍが印加されている。それにより、額縁電極Ｇ５と共通電極ＣＥとの間の電位差が０Ｖになるため、額縁部５１には黒が表示される。 Here, the same voltage Vcom as that of the common electrode CE is applied to the frame electrode G5. As a result, the potential difference between the frame electrode G5 and the common electrode CE becomes 0 V, so black is displayed on the frame portion 51.
　なお、画像表示部１１によって表示される画像の品質向上の妨げとならないように、額縁部５１によって表示される黒のレベルは、画像表示部１１によって表示される黒のレベルと同じであることが好ましい。しかしながら、実際には、額縁部５１によって表示される黒は、画像表示部１１によって表示される黒よりも黒く表示されてしまう。そのため、額縁部５１が搭載された反射型液晶表示装置では、例えば額縁部５１によって表示される黒が強調され過ぎてしまう等の理由により、映像品質が劣化してしまうという問題があった。 Note that the level of black displayed by the frame unit 51 is the same as the level of black displayed by the image display unit 11 so as not to hinder the improvement of the quality of the image displayed by the image display unit 11 preferable. However, in practice, the black displayed by the frame 51 is displayed more black than the black displayed by the image display unit 11. Therefore, in the reflection type liquid crystal display device in which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated due to, for example, the black displayed by the frame portion 51 being overemphasized.
　この問題は、画素１２の反射電極ＰＥの開口率（画素配置領域Ａ１に占める反射電極ＰＥの配置面積の割合）と、額縁部５１の額縁電極Ｇ５の開口率（画素配置領域Ａ１と等価の電極配置領域Ａ５に占める額縁電極Ｇ５の配置面積の割合）と、が違うことに起因する。以下、図９を参照しつつ説明する。 The problem is that the aperture ratio of the reflective electrode PE of the pixel 12 (the ratio of the arrangement area of the reflective electrode PE to occupy in the pixel arrangement region A1) and the aperture ratio of the frame electrode G5 of the frame 51 (an electrode equivalent to the pixel arrangement region A1) This is because the ratio of the arrangement area of the frame electrode G5 to the arrangement area A5 is different. This will be described below with reference to FIG.
　まず、画素１２の反射電極ＰＥは、隣接する画素１２の反射電極ＰＥと分離して形成される必要があるため、反射電極ＰＥ間には画素間隙が形成される。それにより、画素１２の反射電極ＰＥの開口率は低下する。具体的には、画素１２の反射電極ＰＥの開口率は、正方形状の画素配置領域Ａ１の一辺の長さ（即ち、画素ピッチ）Ｌ１が３．８μｍ、画素間隙Ｌ２が０．２μｍである場合、８９．７５％となる（図９の左図参照）。 First, since the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrodes PE. As a result, the aperture ratio of the reflective electrode PE of the pixel 12 is reduced. Specifically, the aperture ratio of the reflective electrode PE of the pixel 12 is such that the length of one side of the square pixel arrangement region A1 (that is, the pixel pitch) L1 is 3.8 μm and the pixel gap L2 is 0.2 μm. , 89.75% (see the left figure in FIG. 9).
　それに対し、額縁部５１の額縁電極Ｇ５は、既に説明したように、額縁部５１の全体にわたって隙間なく広がるベタ電極である。そのため、額縁電極Ｇ５の開口率は、１００％になる（図９の右図参照）。 On the other hand, the frame electrode G5 of the frame portion 51 is a solid electrode which spreads without a gap over the entire frame portion 51 as described above. Therefore, the aperture ratio of the frame electrode G5 is 100% (see the right of FIG. 9).
　そのため、反射電極ＰＥ及び額縁電極Ｇ５のそれぞれに同じレベルの黒階調の電圧を印加した場合でも、開口率の違いにより、画像表示部１１の各画素１２によって表示される黒のレベルと、額縁部５１によって表示される黒のレベルと、が異なってしまう。 Therefore, even when black gradation voltage of the same level is applied to each of the reflective electrode PE and the frame electrode G5, the black level displayed by each pixel 12 of the image display unit 11 and the frame due to the difference in aperture ratio The level of black displayed by the unit 51 is different.
　より具体的には、液晶表示素子ＬＣ，ＬＣ＿Ｂに垂直に入射された光は、液晶ＬＣＭを通過して、反射電極ＰＥや額縁電極Ｇ５において垂直に反射し、液晶ＬＣＭによって変調された後、出射される。例えば、黒の表示を行う場合、液晶ＬＣＭによる変調によって、光の偏向方向を位相差にして９０度ずらす。それにより、光の進行が遮られるため、黒が表示される。ここで、画像表示部１１の各画素１２と額縁部５１とでは、光を反射する反射電極ＰＥ及び額縁電極Ｇ５のそれぞれの開口率が異なるため、液晶ＬＣＭによって変調される光の量が異なってしまい、その結果、表示される黒のレベルが互いに異なってしまう。 More specifically, light vertically incident on the liquid crystal display elements LC and LC_B passes through the liquid crystal LCM, is vertically reflected by the reflective electrode PE and the frame electrode G5, is modulated by the liquid crystal LCM, and then exits. Be done. For example, in the case of displaying in black, the polarization direction of light is shifted by 90 degrees as a phase difference by modulation by the liquid crystal LCM. As a result, the progress of light is blocked, so black is displayed. Here, in each pixel 12 of the image display unit 11 and the frame portion 51, the aperture ratio of the reflective electrode PE that reflects light and the frame electrode G5 are different, so the amount of light modulated by the liquid crystal LCM is different. As a result, the displayed black levels will differ from one another.
　次に、本実施の形態にかかる額縁部２１について具体的に説明する。
　図１０は、反射型液晶表示装置１０に設けられた画像表示部１１の各画素１２の反射電極ＰＥ、及び、額縁部２１の複数の額縁電極Ｇ１の概略平面図である。なお、図１０の例では、画像表示部１１の角部に設けられた複数の画素１２のそれぞれの反射電極ＰＥ、及び、その周辺に設けられた額縁部２１の複数の額縁電極Ｇ１のみが示されている。 Next, the frame portion 21 according to the present embodiment will be specifically described.
FIG. 10 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G1 of the frame unit 21. Note that, in the example of FIG. 10, only the reflection electrodes PE of the plurality of pixels 12 provided at the corner of the image display unit 11 and the plurality of frame electrodes G1 of the frame portion 21 provided around the same are shown. It is done.
　図１０に示すように、額縁部２１は、行列状に区画された複数の電極配置領域Ａ２のそれぞれに規則的に配置された複数の額縁電極Ｇ１を有する。なお、電極配置領域Ａ２は、画素１２が配置される画素配置領域Ａ１と同一サイズ（ピッチ）である。これら複数の額縁電極Ｇ１は、画素１２の反射電極ＰＥと同一階層に形成されている。 As shown in FIG. 10, the frame portion 21 has a plurality of frame electrodes G1 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. The plurality of frame electrodes G1 are formed in the same layer as the reflective electrode PE of the pixel 12.
　なお、各額縁電極Ｇ１の上層には、共通電極ＣＥが離間対向配置され、共通電極ＣＥと各額縁電極Ｇ１との間には液晶ＬＣＭが充填封止されている。これら共通電極ＣＥ、額縁電極Ｇ１、及び、液晶ＬＣＭによって液晶表示素子ＬＣ＿Ｂが構成されている。 In the upper layer of each frame electrode G1, a common electrode CE is disposed so as to be spaced apart and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G1. A liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G1, and the liquid crystal LCM.
　各額縁電極Ｇ１は、平面視上、矩形状の本体部Ｇ１ａと、本体部の一辺及びそれに直交する他の一辺からそれぞれ突出するようにして設けられた２つの連結部Ｇ１ｂと、によって構成されている。各額縁電極Ｇ１は、隣接する額縁電極Ｇ１と、連結部Ｇ１ｂにより電気的に接続されている。それにより、額縁部２１の全ての額縁電極Ｇ１の印加電圧を同じにすることができる。 Each frame electrode G1 is configured by a rectangular main body portion G1a in plan view, and two connecting portions G1b provided so as to protrude from one side of the main body portion and the other side orthogonal thereto. There is. Each frame electrode G1 is electrically connected to the adjacent frame electrode G1 by the connecting portion G1b. Thereby, the application voltage of all the frame electrodes G1 of the frame part 21 can be made the same.
　ここで、各額縁電極Ｇ１には、共通電極ＣＥと同じ電圧Ｖｃｏｍが印加されている。それにより、各額縁電極Ｇ１と共通電極ＣＥとの間の電位差が０Ｖになるため、額縁部２１には黒が表示される。 Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G1. As a result, the potential difference between each frame electrode G1 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 21.
　図１１は、図１０に示す概略平面図のＸＩ－ＸＩ部分を切り出した概略断面図である。
　図１１に示すように、額縁部２１では、額縁電極Ｇ１を含む液晶表示素子と、額縁電極Ｇ１より下位階層の回路部分とが、電気的に分離して形成されている。そのため、額縁電極Ｇ１には、額縁電極Ｇ１より下位階層の回路部分に関係なく、共通電極ＣＥと同じ電圧Ｖｃｏｍを供給することができる。その他の断面構造については、図４で説明した内容と同様であるため、その説明を省略する。 11 is a schematic cross-sectional view of a portion XI-XI of the schematic plan view shown in FIG.
As shown in FIG. 11, in the frame portion 21, a liquid crystal display element including the frame electrode G1 and a circuit portion in a lower layer than the frame electrode G1 are electrically separated. Therefore, the same voltage Vcom as that of the common electrode CE can be supplied to the frame electrode G1 regardless of the circuit portion in the lower layer than the frame electrode G1. The other cross-sectional structures are the same as the contents described in FIG.
　なお、画像表示部１１によって表示される画像の品質向上の妨げとならないように、額縁部２１によって表示される黒のレベルは、画像表示部１１によって表示される黒のレベルにできるだけ近い（理想的には同じ）ことが好ましい。 Note that the level of black displayed by the frame unit 21 is as close as possible to the level of black displayed by the image display unit 11 (ideally, so as not to hinder the improvement of the quality of the image displayed by the image display unit 11). Is the same).
　そこで、本実施の形態では、額縁電極Ｇ１の開口率（画素配置領域Ａ１と等価の電極配置領域Ａ２に占める額縁電極Ｇ１の配置面積の割合）を、各画素１２の反射電極ＰＥの開口率（画素配置領域Ａ１に占める反射電極ＰＥの配置面積の割合）にできるだけ近づけている（理想的には同じにしている）。以下、図１２を参照しつつ説明する。 Therefore, in the present embodiment, the aperture ratio of the frame electrode G1 (the ratio of the arrangement area of the frame electrode G1 occupied in the electrode arrangement region A2 equivalent to the pixel arrangement region A1) It is as close as possible to the ratio of the arrangement area of the reflective electrode PE occupied in the pixel arrangement area A1 (ideally the same). This will be described below with reference to FIG.
　まず、画素１２の反射電極ＰＥの開口率は、正方形状の画素配置領域Ａ１の一辺の長さ（即ち、画素ピッチ）Ｌ１が３．８μｍ、画素間隙Ｌ２が０．２μｍとすると、８９．７５％となる（図１２の左図参照）。 First, assuming that the aperture ratio of the reflective electrode PE of the pixel 12 is 3.8 μm for the length of one side of the square pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 μm for the pixel gap L2, 89.75. % (See the left figure in FIG. 12).
　それに対し、額縁電極Ｇ１の開口率は、正方形状の電極配置領域Ａ２の一辺の長さＬ１が３．８μｍ、間隙Ｌ３が０．２８μｍ、連結部Ｇ１ｂの幅Ｌ４が１μｍとすると、８９．６８％となる（図１２の右図参照）。これは、画素１２の反射電極ＰＥの開口率８９．７５％に近い。 On the other hand, the aperture ratio of the frame electrode G1 is 89.68, assuming that the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm, the gap L3 is 0.28 μm, and the width L4 of the connecting portion G1 b is 1 μm. % (See the right figure in FIG. 12). This is close to the aperture ratio 89.75% of the reflective electrode PE of the pixel 12.
　このように、本実施の形態にかかる反射型液晶表示装置１０は、各額縁電極Ｇ１の開口率を、各画素１２の反射電極ＰＥの開口率にできるだけ近づけている。それにより、本実施の形態にかかる反射型液晶表示装置１０は、額縁部２１によって表示される黒のレベルを、画像表示部１１によって表示される黒のレベルに近づけることができるため、映像品質の劣化を防ぐことができる。換言すると、本実施の形態にかかる反射型液晶表示装置１０は、額縁部２１及び画像表示部１１のそれぞれによって表示される黒のレベルを均一化することができるため、ユーザにとって違和感のない映像を表示させることができる。 As described above, in the reflective liquid crystal display device 10 according to the present embodiment, the aperture ratio of each frame electrode G1 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the present embodiment can bring the level of black displayed by the frame portion 21 closer to the level of black displayed by the image display unit 11, so Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the present embodiment can equalize the level of black displayed by each of the frame portion 21 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
（実験結果）
　図１３は、反射電極ＰＥ及び額縁電極Ｇ１のそれぞれの開口率の差と、画像表示部１１及び額縁部２１のそれぞれによって表示される黒レベルの差と、の関係を示す実験結果である。図１３の実験結果に示すように、反射電極ＰＥ及び額縁電極Ｇ１のそれぞれの開口率の差が小さくなるほど、画像表示部１１及び額縁部２１のそれぞれによって表示される黒レベルの差は小さくなる。そして、反射電極ＰＥ及び額縁電極Ｇ１のそれぞれの開口率の差（反射電極ＰＥの開口率を基準にした場合の額縁電極Ｇ１の開口率の差分）が５％以下になると、画像表示部１１及び額縁部２１のそれぞれによって表示される黒レベルの差は、見かけ上、無くなった。 (Experimental result)
FIG. 13 shows experimental results showing the relationship between the difference in the aperture ratio of each of the reflective electrode PE and the frame electrode G1, and the difference in the black level displayed by each of the image display unit 11 and the frame unit 21. As shown in the experimental result of FIG. 13, as the difference in the aperture ratio between the reflective electrode PE and the frame electrode G1 decreases, the difference in the black level displayed by the image display unit 11 and the frame unit 21 decreases. When the difference in the aperture ratio between the reflective electrode PE and the frame electrode G1 (the difference in the aperture ratio of the frame electrode G1 based on the aperture ratio of the reflective electrode PE) becomes 5% or less, the image display unit 11 and The difference in black level displayed by each of the frame portions 21 apparently disappeared.
＜実施の形態２＞
　図１４は、実施の形態２に係る反射型液晶表示装置１０に設けられた画像表示部１１の各画素１２の反射電極ＰＥ、及び、額縁部３１の複数の額縁電極Ｇ２の概略平面図である。額縁部３１は、額縁部２１に対応し、額縁電極Ｇ２は、額縁電極Ｇ１に対応する。なお、図１４の例では、画像表示部１１の角部に設けられた複数の画素１２のそれぞれの反射電極ＰＥ、及び、その周辺に設けられた額縁部３１の複数の額縁電極Ｇ２のみが示されている。 Second Embodiment
FIG. 14 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 according to the second embodiment and a plurality of frame electrodes G2 of the frame portion 31. . The frame portion 31 corresponds to the frame portion 21 and the frame electrode G2 corresponds to the frame electrode G1. In the example of FIG. 14, only the reflection electrodes PE of the plurality of pixels 12 provided at the corner of the image display unit 11 and the plurality of frame electrodes G2 of the frame portion 31 provided around the same are shown. It is done.
　図１４に示すように、額縁部３１は、行列状に区画された複数の電極配置領域Ａ２のそれぞれに規則的に配置された複数の額縁電極Ｇ２を有する。なお、電極配置領域Ａ２は、画素１２が配置される画素配置領域Ａ１と同一サイズ（ピッチ）である。これら複数の額縁電極Ｇ２は、画素１２の反射電極ＰＥと同一階層に形成されている。 As shown in FIG. 14, the frame portion 31 has a plurality of frame electrodes G2 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. The plurality of frame electrodes G2 are formed in the same layer as the reflective electrode PE of the pixel 12.
　なお、各額縁電極Ｇ２の上層には、共通電極ＣＥが離間対向配置され、共通電極ＣＥと各額縁電極Ｇ２との間には液晶ＬＣＭが充填封止されている。これら共通電極ＣＥ、額縁電極Ｇ２、及び、液晶ＬＣＭによって液晶表示素子ＬＣ＿Ｂが構成されている。 In the upper layer of each frame electrode G2, a common electrode CE is disposed so as to be separated and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G2. A liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G2, and the liquid crystal LCM.
　各額縁電極Ｇ２は、平面視上、画素１２の反射電極ＰＥと同一形状を有している。各額縁電極Ｇ２は、隣接する額縁電極Ｇ２と、これら額縁電極Ｇ２の下位階層に形成された回路部の配線によって電気的に接続されている。それにより、額縁部３１の全ての額縁電極Ｇ２の印加電圧を同じにすることができる。 Each frame electrode G2 has the same shape as the reflective electrode PE of the pixel 12 in plan view. Each frame electrode G2 is electrically connected to the adjacent frame electrode G2 by the wiring of the circuit portion formed in the lower layer of these frame electrodes G2. Thereby, the applied voltage of all the frame electrodes G2 of the frame part 31 can be made the same.
　ここで、各額縁電極Ｇ２には、共通電極ＣＥと同じ電圧Ｖｃｏｍが印加されている。それにより、各額縁電極Ｇ２と共通電極ＣＥとの間の電位差が０Ｖになるため、額縁部３１には黒が表示される。 Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G2. As a result, the potential difference between each frame electrode G2 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 31.
　図１５は、図１４に示す概略平面図のＸＶ－ＸＶ部分を切り出した概略断面図である。
　図１５に示すように、額縁部３１では、隣接する額縁電極Ｇ２同士が、これら額縁電極Ｇ２の下位階層に形成された第４メタル１１４及びスルーホール１１９ｅを介して、電気的に接続されている。それにより、額縁部３１の全ての額縁電極Ｇ２の印加電圧を同じにすることができる。なお、第４メタル１１４とそれより下位階層の回路部分とは、電気的に分離して形成されている。そのため、額縁電極Ｇ２には、下位階層の回路部分に関係なく、共通電極ＣＥと同じ電圧Ｖｃｏｍを供給することができる。その他の断面構造については、図４で説明した内容と同様であるため、その説明を省略する。 FIG. 15 is a schematic cross-sectional view of the XV-XV portion of the schematic plan view shown in FIG.
As shown in FIG. 15, in the frame portion 31, the adjacent frame electrodes G2 are electrically connected to each other through the fourth metal 114 and the through holes 119e formed in the lower layer of the frame electrodes G2. . Thereby, the applied voltage of all the frame electrodes G2 of the frame part 31 can be made the same. Note that the fourth metal 114 and the circuit portion in the lower hierarchy than that are electrically separated. Therefore, the same voltage Vcom as that of the common electrode CE can be supplied to the frame electrode G2 regardless of the circuit portion of the lower layer. The other cross-sectional structures are the same as the contents described in FIG.
　なお、画像表示部１１によって表示される画像の品質向上の妨げとならないように、額縁部３１によって表示される黒のレベルは、画像表示部１１によって表示される黒のレベルにできるだけ近い（理想的には同じ）ことが好ましい。 Note that the level of black displayed by the frame section 31 is as close as possible to the level of black displayed by the image display section 11 (ideally, so as not to hinder the improvement of the quality of the image displayed by the image display section 11). Is the same).
　そこで、本実施の形態では、額縁電極Ｇ２の開口率（画素配置領域Ａ１と等価の電極配置領域Ａ２に占める額縁電極Ｇ２の配置面積の割合）を、各画素１２の反射電極ＰＥの開口率（画素配置領域Ａ１に占める反射電極ＰＥの配置面積の割合）にできるだけ近づけている（理想的には同じにしている）。以下、図１６を参照しつつ説明する。 Therefore, in the present embodiment, the aperture ratio of the frame electrode G2 (the ratio of the arrangement area of the frame electrode G2 occupied in the electrode arrangement region A2 equivalent to the pixel arrangement region A1) It is as close as possible to the ratio of the arrangement area of the reflective electrode PE occupied in the pixel arrangement area A1 (ideally the same). This will be described below with reference to FIG.
　まず、画素１２の反射電極ＰＥの開口率は、正方形状の画素配置領域Ａ１の一辺の長さ（即ち、画素ピッチ）Ｌ１が３．８μｍ、画素間隙Ｌ２が０．２μｍとすると、８９．７５％となる（図１６の左図参照）。 First, assuming that the aperture ratio of the reflective electrode PE of the pixel 12 is 3.8 μm for the length of one side of the square pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 μm for the pixel gap L2, 89.75. % (See the left figure in FIG. 16).
　また、額縁電極Ｇ２の開口率は、正方形状の電極配置領域Ａ２の一辺の長さＬ１が３．８μｍ、画素間隙Ｌ２が０．２μｍとすると、８９．７５％となる（図１６の右図参照）。これは、画素１２の反射電極ＰＥの開口率８９．７５％と同じである。 In addition, the aperture ratio of the frame electrode G2 is 89.75% when the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm and the pixel gap L2 is 0.2 μm (right view in FIG. 16). reference). This is the same as the aperture ratio 89.75% of the reflective electrode PE of the pixel 12.
　このように、実施の形態２にかかる反射型液晶表示装置１０は、各額縁電極Ｇ２の開口率を、各画素１２の反射電極ＰＥの開口率にできるだけ近づけている。それにより、実施の形態２にかかる反射型液晶表示装置１０は、額縁部３１によって表示される黒のレベルを、画像表示部１１によって表示される黒のレベルに近づけることができるため、映像品質の劣化を防ぐことができる。換言すると、実施の形態２にかかる反射型液晶表示装置１０は、額縁部３１及び画像表示部１１のそれぞれによって表示される黒のレベルを均一化することができるため、ユーザにとって違和感のない映像を表示させることができる。 Thus, in the reflective liquid crystal display device 10 according to the second embodiment, the aperture ratio of each frame electrode G2 is as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, since the reflective liquid crystal display device 10 according to the second embodiment can bring the level of black displayed by the frame portion 31 closer to the level of black displayed by the image display portion 11, Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the second embodiment can equalize the level of black displayed by each of the frame portion 31 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
＜実施の形態３＞
　実施の形態３にかかる反射型液晶表示装置１０に設けられた額縁部４１について説明する前に、再び額縁部５１について説明する。 Embodiment 3
Before describing the frame portion 41 provided in the reflective liquid crystal display device 10 according to the third embodiment, the frame portion 51 will be described again.
　既に説明しているように、画像表示部１１によって表示される画像の品質向上の妨げとならないように、額縁部５１によって表示される黒のレベルは、画像表示部１１によって表示される黒のレベルと同じであることが好ましい。しかしながら、実際には、額縁部５１によって表示される黒は、画像表示部１１によって表示される黒よりも黒く表示されてしまう。そのため、額縁部５１が搭載された液晶表示装置では、例えば額縁部５１によって表示される黒が強調され過ぎてしまう等の理由により、映像品質が劣化してしまうという問題があった。 As already described, the level of black displayed by the frame unit 51 is the level of black displayed by the image display unit 11 so as not to hinder the improvement of the quality of the image displayed by the image display unit 11. Is preferably the same as However, in practice, the black displayed by the frame 51 is displayed more black than the black displayed by the image display unit 11. Therefore, in the liquid crystal display device in which the frame portion 51 is mounted, there is a problem that the image quality is deteriorated due to, for example, the black displayed by the frame portion 51 being overemphasized.
　この問題は、画素１２の反射電極ＰＥの開口率と、額縁部５１の額縁電極Ｇ５の開口率と、が違うことに起因するだけでなく、画素配置領域Ａ１当たりの反射電極ＰＥの周囲長（エッジ部分の長さ）と、電極配置領域Ａ５当たりの額縁電極Ｇ５の周囲長と、が違うことに起因する。以下、図９を参照しつつ説明する。 This problem is caused not only because the aperture ratio of the reflective electrode PE of the pixel 12 and the aperture ratio of the frame electrode G5 of the frame portion 51 are different, but also the peripheral length of the reflective electrode PE per pixel arrangement region A1 This is because the length of the edge portion is different from the peripheral length of the frame electrode G5 per electrode arrangement area A5. This will be described below with reference to FIG.
　まず、画素１２の反射電極ＰＥは、隣接する画素１２の反射電極ＰＥと分離して形成される必要があるため、画素１２の反射電極ＰＥ間には画素間隙が形成される。それにより、画素１２の反射電極ＰＥの周囲長は増加する。具体的には、画素１２の反射電極ＰＥのエッジ部分の周囲長は、正方形状の画素配置領域Ａ１の一辺の長さ（即ち、画素ピッチ）Ｌ１が３．８μｍ、画素間隙Ｌ２が０．２μｍである場合、１４．４４μｍとなる（図９の左図参照）。 First, since the reflective electrode PE of the pixel 12 needs to be formed separately from the reflective electrode PE of the adjacent pixel 12, a pixel gap is formed between the reflective electrodes PE of the pixel 12. Thus, the perimeter of the reflective electrode PE of the pixel 12 is increased. Specifically, the peripheral length of the edge portion of the reflective electrode PE of the pixel 12 is 3.8 μm for the length of one side of the square-shaped pixel arrangement area A1 (that is, pixel pitch) L1 and 0.2 μm for the pixel gap L2 If it is, it becomes 14.44 μm (see the left figure of FIG. 9).
　それに対し、額縁部５１の額縁電極Ｇ５は、既に説明したように、額縁部５１の全体にわたって隙間なく広がるベタ電極である。そのため、額縁電極Ｇ５のエッジ部分の周囲長は、０μｍである（図９の右図参照）。 On the other hand, the frame electrode G5 of the frame portion 51 is a solid electrode which spreads without a gap over the entire frame portion 51 as described above. Therefore, the perimeter of the edge portion of the frame electrode G5 is 0 μm (see the right of FIG. 9).
　そのため、反射電極ＰＥ及び額縁電極Ｇ５のそれぞれに同じレベルの黒階調の電圧を印加した場合でも、周囲長の違いにより、画像表示部１１の各画素１２によって表示される黒のレベルと、額縁部５１によって表示される黒のレベルと、が異なってしまう。 Therefore, even when black gradation voltage of the same level is applied to each of the reflective electrode PE and the frame electrode G5, the black level displayed by each pixel 12 of the image display unit 11 and the frame due to the difference in peripheral length. The level of black displayed by the unit 51 is different.
　より具体的には、液晶表示素子ＬＣ，ＬＣ＿Ｂに垂直に入射された光は、液晶ＬＣＭを通過して、反射電極ＰＥや額縁電極Ｇ５において垂直に反射し、液晶ＬＣＭによって変調された後、出射される。例えば、黒の表示を行う場合、液晶ＬＣＭによる変調によって、光の偏向方向を位相差にして９０度ずらす。それにより、光の進行が遮られるため、黒が表示される。ここで、画像表示部１１の各画素１２と額縁部５１とでは、光を反射する反射電極ＰＥ及び額縁電極Ｇ５のそれぞれの周囲長（エッジ部分の長さ）が異なるため、エッジ部分における乱反射の度合いが異なってしまい、その結果、表示される黒のレベルが互いに異なってしまう。例えば、エッジ部分の長さが長いと、乱反射の量が多くなるため、光の偏向方向とは異なる反射光が増加し、その結果、表示される黒は明るくなる。他方、エッジ部分の長さが短いと、乱反射の量が少なくなるため、光の偏向方向とは異なる反射光が減少し、その結果、表示される黒は暗くなる。 More specifically, light vertically incident on the liquid crystal display elements LC and LC_B passes through the liquid crystal LCM, is vertically reflected by the reflective electrode PE and the frame electrode G5, is modulated by the liquid crystal LCM, and then exits. Be done. For example, in the case of displaying in black, the polarization direction of light is shifted by 90 degrees as a phase difference by modulation by the liquid crystal LCM. As a result, the progress of light is blocked, so black is displayed. Here, since peripheral lengths (lengths of edge portions) of the reflective electrode PE that reflects light and the frame electrodes G5 are different between each pixel 12 of the image display unit 11 and the frame portion 51, irregular reflection at the edge portion As a result, the displayed black levels are different from one another. For example, when the length of the edge portion is long, the amount of diffuse reflection increases, so that the amount of reflected light different from the light deflection direction increases, and as a result, the displayed black becomes bright. On the other hand, when the length of the edge portion is short, the amount of diffuse reflection decreases, so that the reflected light different from the light deflection direction decreases, and as a result, the displayed black becomes dark.
　次に、本実施の形態にかかる額縁部４１について具体的に説明する。
　図１７は、反射型液晶表示装置１０に設けられた画像表示部１１の各画素１２の反射電極ＰＥ、及び、額縁部４１の複数の額縁電極Ｇ３の概略平面図である。なお、図１７の例では、画像表示部１１の角部に設けられた複数の画素１２のそれぞれの反射電極ＰＥ、及び、その周辺に設けられた額縁部４１の複数の額縁電極Ｇ３のみが示されている。 Next, the frame portion 41 according to the present embodiment will be specifically described.
FIG. 17 is a schematic plan view of the reflective electrode PE of each pixel 12 of the image display unit 11 provided in the reflective liquid crystal display device 10 and the plurality of frame electrodes G3 of the frame unit 41. Note that, in the example of FIG. 17, only the reflection electrodes PE of the plurality of pixels 12 provided in the corner of the image display unit 11 and the plurality of frame electrodes G3 of the frame portion 41 provided in the periphery thereof are shown. It is done.
　図１７に示すように、額縁部４１は、行列状に区画された複数の電極配置領域Ａ２のそれぞれに規則的に配置された複数の額縁電極Ｇ３を有する。なお、電極配置領域Ａ２は、画素１２が配置される画素配置領域Ａ１と同一サイズ（ピッチ）である。これら複数の額縁電極Ｇ３は、画素１２の反射電極ＰＥと同一階層に形成されている。 As shown in FIG. 17, the frame portion 41 has a plurality of frame electrodes G3 regularly arranged in each of the plurality of electrode arrangement areas A2 partitioned in a matrix. The electrode arrangement area A2 has the same size (pitch) as the pixel arrangement area A1 in which the pixels 12 are arranged. The plurality of frame electrodes G3 are formed in the same layer as the reflective electrode PE of the pixel 12.
　なお、各額縁電極Ｇ３の上層には、共通電極ＣＥが離間対向配置され、共通電極ＣＥと各額縁電極Ｇ３との間には液晶ＬＣＭが充填封止されている。これら共通電極ＣＥ、額縁電極Ｇ３、及び、液晶ＬＣＭによって液晶表示素子ＬＣ＿Ｂが構成されている。 In the upper layer of each frame electrode G3, a common electrode CE is disposed so as to be spaced apart and opposed, and a liquid crystal LCM is filled and sealed between the common electrode CE and each frame electrode G3. A liquid crystal display element LC_B is configured by the common electrode CE, the frame electrode G3, and the liquid crystal LCM.
　各額縁電極Ｇ３は、平面視上、矩形状の本体部Ｇ３ａと、本体部の一辺及びそれに直交する他の一辺からそれぞれ突出するようにして設けられた２つの連結部Ｇ３ｂと、によって構成されている。各額縁電極Ｇ３は、隣接する額縁電極Ｇ３と、連結部Ｇ３ｂにより電気的に接続されている。それにより、額縁部４１の全ての額縁電極Ｇ３の印加電圧を同じにすることができる。 Each frame electrode G3 is configured by a rectangular main body portion G3a in plan view, and two connecting portions G3b provided so as to respectively project from one side of the main body portion and the other side orthogonal thereto. There is. Each frame electrode G3 is electrically connected to the adjacent frame electrode G3 by the connecting portion G3b. Thereby, the applied voltage of all the frame electrodes G3 of the frame part 41 can be made the same.
　ここで、各額縁電極Ｇ３には、共通電極ＣＥと同じ電圧Ｖｃｏｍが印加されている。それにより、各額縁電極Ｇ３と共通電極ＣＥとの間の電位差が０Ｖになるため、額縁部４１には黒が表示される。 Here, the same voltage Vcom as that of the common electrode CE is applied to each frame electrode G3. As a result, the potential difference between each frame electrode G3 and the common electrode CE becomes 0 V, so black is displayed in the frame portion 41.
　なお、画像表示部１１によって表示される画像の品質向上の妨げとならないように、額縁部４１によって表示される黒のレベルは、画像表示部１１によって表示される黒のレベルにできるだけ近い（理想的には同じ）ことが好ましい。 It should be noted that the level of black displayed by the frame section 41 is as close as possible to the level of black displayed by the image display section 11 so as not to hinder the improvement of the quality of the image displayed by the image display section 11 (ideally Is the same).
　そこで、本実施の形態では、額縁電極Ｇ３の周囲長を、各画素１２の反射電極ＰＥの周囲長にできるだけ近づけている（理想的には同じにしている）。以下、図１８を参照しつつ説明する。 Therefore, in the present embodiment, the peripheral length of the frame electrode G3 is as close as possible to the peripheral length of the reflective electrode PE of each pixel 12 (they are ideally the same). This will be described below with reference to FIG.
　まず、画素１２の反射電極ＰＥの周囲長は、正方形状の画素配置領域Ａ１の一辺の長さ（即ち、画素ピッチ）Ｌ１が３．８μｍ、画素間隙Ｌ２が０．２μｍとすると、１４．４４μｍとなる（図１８の左図参照）。 First, the peripheral length of the reflective electrode PE of the pixel 12 is 14.44 μm, assuming that the length of one side (that is, pixel pitch) L1 of the square pixel arrangement region A1 is 3.8 μm and the pixel gap L2 is 0.2 μm. (See the left figure of FIG. 18).
　それに対し、額縁電極Ｇ１の開口率は、正方形状の電極配置領域Ａ２の一辺の長さＬ１が３．８μｍ、間隙Ｌ３が０．２８μｍ、連結部Ｇ１ｂの幅Ｌ４が１μｍとすると、１４．４４μｍとなる（図１８の右図参照）。これは、画素１２の反射電極ＰＥの周囲長と同じ長さである。 On the other hand, the aperture ratio of the frame electrode G1 is 14.44 μm, assuming that the length L1 of one side of the square electrode arrangement region A2 is 3.8 μm, the gap L3 is 0.28 μm, and the width L4 of the connecting portion G1 b is 1 μm. (See the right side of FIG. 18). This is the same length as the peripheral length of the reflective electrode PE of the pixel 12.
　このように、実施の形態３にかかる反射型液晶表示装置１０は、各額縁電極Ｇ３の周囲長（エッジ部分の長さ）を、各画素１２の反射電極ＰＥの周囲長にできるだけ近づけている。それにより、実施の形態３にかかる反射型液晶表示装置１０は、額縁部４１によって表示される黒のレベルを、画像表示部１１によって表示される黒のレベルに近づけることができるため、映像品質の劣化を防ぐことができる。換言すると、実施の形態３にかかる反射型液晶表示装置１０は、額縁部３１及び画像表示部１１のそれぞれによって表示される黒のレベルを均一化することができるため、ユーザにとって違和感のない映像を表示させることができる。 As described above, in the reflective liquid crystal display device 10 according to the third embodiment, the peripheral length (the length of the edge portion) of each frame electrode G3 is as close as possible to the peripheral length of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the third embodiment can bring the level of black displayed by the frame portion 41 closer to the level of black displayed by the image display unit 11, and Deterioration can be prevented. In other words, the reflective liquid crystal display device 10 according to the third embodiment can equalize the level of black displayed by each of the frame portion 31 and the image display portion 11, so that the user does not feel uncomfortable for the user. It can be displayed.
（実験結果）
　図１９は、反射電極ＰＥ及び額縁電極Ｇ３のそれぞれの周囲長の差と、画像表示部１１及び額縁部４１のそれぞれによって表示される黒レベルの差と、の関係を示す実験結果である。図１９の実験結果に示すように、反射電極ＰＥ及び額縁電極Ｇ３のそれぞれの周囲長の差が小さくなるほど、画像表示部１１及び額縁部４１のそれぞれによって表示される黒レベルの差は小さくなる。そして、反射電極ＰＥ及び額縁電極Ｇ３のそれぞれの周囲長の差（反射電極ＰＥの周囲長を基準にした場合の額縁電極Ｇ３の周囲長の差分）が３０％以下になると、画像表示部１１及び額縁部４１のそれぞれによって表示される黒レベルの差は、見かけ上、無くなった。 (Experimental result)
FIG. 19 is an experimental result showing the relationship between the difference in perimeter of each of the reflective electrode PE and the frame electrode G3 and the difference in black level displayed by each of the image display unit 11 and the frame unit 41. As shown in the experimental result of FIG. 19, the difference between the black levels displayed by the image display unit 11 and the frame portion 41 decreases as the difference between the perimeters of the reflective electrode PE and the frame electrode G3 decreases. When the difference in peripheral length between the reflective electrode PE and the frame electrode G3 (difference in peripheral length of the frame electrode G3 based on the peripheral length of the reflective electrode PE) becomes 30% or less, the image display unit 11 and The difference in black level displayed by each of the frame portions 41 apparently disappeared.
　以上のように、実施の形態１～３にかかる反射型液晶表示装置１０は、各額縁電極の開口率を、各画素１２の反射電極ＰＥの開口率にできるだけ近づけている。それにより、実施の形態３にかかる反射型液晶表示装置１０は、額縁部によって表示される黒のレベルを、画像表示部によって表示される黒のレベルに近づけることができるため、映像品質の劣化を防ぐことができる。換言すると、実施の形態３にかかる反射型液晶表示装置１０は、額縁部及び画像表示部のそれぞれによって表示される黒のレベルを均一化することができるため、ユーザにとって違和感のない映像を表示させることができる。 As described above, in the reflective liquid crystal display device 10 according to the first to third embodiments, the aperture ratio of each frame electrode is made as close as possible to the aperture ratio of the reflective electrode PE of each pixel 12. As a result, the reflective liquid crystal display device 10 according to the third embodiment can bring the level of black displayed by the frame portion closer to the level of black displayed by the image display unit. It can prevent. In other words, since the reflective liquid crystal display device 10 according to the third embodiment can equalize the level of black displayed by each of the frame portion and the image display portion, a video with no sense of incongruity is displayed for the user. be able to.
　この出願は、２０１７年１１月１５日に出願された日本出願特願２０１７－２１９８５７を基礎とする優先権を主張し、その開示の全てをここに取り込む。 This application claims priority based on Japanese Patent Application No. 2017-219857 filed on Nov. 15, 2017, the entire disclosure of which is incorporated herein.
　本発明は、プロジェクター等に搭載される液晶表示装置に好適に適用することができる。 The present invention can be suitably applied to a liquid crystal display device mounted on a projector or the like.
　１０　反射型液晶表示装置
　１１　画像表示部
　１２　画素
　１３　タイミングジェネレータ
　１４　垂直シフトレジスタ
　１５　データラッチ回路
　１６　水平ドライバ
　２０　上位装置
　２１　額縁部
　３１　額縁部
　４１　額縁部
　１００　シリコン基板
　１０１　Ｎウエル
　１０２　Ｐウエル
　１０３　素子分離酸化膜
　１０５　層間絶縁膜
　１０６　第１メタル
　１０８　第２メタル
　１１０　第３メタル
　１１２　ＭＩＭ電極
　１１４　第４メタル
　１１６　第５メタル
　１１７　パッシベーション膜（ＰＳＶ）
　１１８　コンタクト
　１１９ａ～１１９ｅ　スルーホール
　１６１　水平シフトレジスタ
　１６２　ラッチ部
　１６３　レベルシフタ／画素ドライバ
　１６４　ラッチ回路
　１６４１～１６４３　ラッチ回路群
　２０１　ＳＲＡＭセル
　２０２　ＤＲＡＭセル
　ｄ１～ｄｎ　列データ線
　ｄＬ，ｄＭ，ｄＲ　列データ線群
　ｇ１～ｇｍ　行走査線
　ｔｒｉｇ，ｔｒｉｇｂ　トリガ線
　ＢＦ１　バッファ
　Ｃ１　容量
　ＣＥ　共通電極
　ＣＨＰ１　チップ
　ＤＭ２　記憶部
　Ｇ１～Ｇ３　額縁電極
　Ｇ１ａ，Ｇ３ａ　本体部
　Ｇ１ｂ，Ｇ３ｂ　連結部
　ＩＮＶ１１，ＩＮＶ１２　インバータ
　ＬＣ，ＬＣ＿Ｂ　液晶表示素子
　ＬＣＭ　液晶
　ＭＮ１，ＭＮ２　ＮＭＯＳトランジスタ
　ＭＮ１１，ＭＮ１２　ＮＭＯＳトランジスタ
　ＭＮ２１，ＭＮ２２　ＮＭＯＳトランジスタ
　ＭＰ２　ＰＭＯＳトランジスタ
　ＭＰ１１，ＭＰ１２　ＰＭＯＳトランジスタ
　ＭＰ２１，ＭＰ２２　ＰＭＯＳトランジスタ
　ＰＥ　反射電極
　ＳＭ１　記憶部
　ＳＷ１，ＳＷ２　スイッチ
　ＳＷ２１，ＳＷ２２　スイッチ DESCRIPTION OF SYMBOLS 10 reflection type liquid crystal display device 11 image display part 12 pixel 13 timing generator 14 vertical shift register 15 data latch circuit 16 horizontal driver 20 host device 21 frame part 31 frame part 41 frame part 100 silicon substrate 101 N well 102 P well 103 isolation Oxide film 105 Interlayer insulating film 106 First metal 108 Second metal 110 Third metal 112 MIM electrode 114 Fourth metal 116 Fifth metal 117 Passivation film (PSV)
118 contacts 119a to 119e through holes 161 horizontal shift register 162 latch section 163 level shifter / pixel driver 164 latch circuit 1641 to 1643 latch circuit group 201 SRAM cell 202 DRAM cell d1 to dn column data line dL, dM, dR column data line group g1 Gm gm line scan line trig, trigb trigger line BF1 buffer C1 capacity CE common electrode CHP1 chip DM2 storage unit G1 to G3 frame electrode G1a, G3a main unit G1b, G3b connection unit INV11, INV12 inverter LC, LC_B liquid crystal display element LCM liquid crystal liquid crystal MN1 , MN2 NMOS transistor MN11, MN12 NMOS transistor MN21, MN22 NMOS transistor MP2 PMOS transistor MP11, MP 2 PMOS transistors MP21, MP22 PMOS transistors PE reflective electrode SM1 storage unit SW1, SW2 switches SW21, SW22 switch

Claims (6)

  1. 　行列状に区画された複数の画素配置領域に複数の画素がそれぞれ配置された画像表示部と、
    　前記画像表示部の外周を囲むようにして設けられ、行列状に区画された複数の電極配置領域に複数の額縁電極がそれぞれ配置された額縁部と、
    　を備え、
    　各前記電極配置領域には、各前記画素配置領域に占める前記画素の反射電極の面積率を基準にして、差分が５％以内の面積率となるように前記額縁電極が配置されている、
    　反射型液晶表示装置。     An image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions divided in a matrix;
    A frame portion provided so as to surround the outer periphery of the image display portion, in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement regions partitioned in a matrix shape;
    Equipped with
    In each of the electrode arrangement regions, the frame electrodes are arranged such that the difference in area ratio is 5% or less on the basis of the area ratio of the reflective electrode of the pixel occupied in each of the pixel arrangement regions.
    Reflective liquid crystal display.
  2. 　各前記額縁電極は、各前記反射電極の面積率と同一の面積率となるように形成されている、
    　請求項１に記載の反射型液晶表示装置。     Each of the frame electrodes is formed to have the same area ratio as the area ratio of each of the reflective electrodes.
    The reflective liquid crystal display device according to claim 1.
  3. 　行列状に区画された複数の画素配置領域に複数の画素がそれぞれ配置された画像表示部と、
    　前記画像表示部の外周を囲むようにして設けられ、行列状に区画された複数の電極配置領域に複数の額縁電極がそれぞれ配置された額縁部と、
    　を備え、
    　各前記電極配置領域には、各前記画素配置領域に占める前記画素の反射電極の周囲長を基準にして、差分が３０％以内の周囲長となるように前記額縁電極が配置されている、
    　反射型液晶表示装置。     An image display unit in which a plurality of pixels are arranged in a plurality of pixel arrangement regions divided in a matrix;
    A frame portion provided so as to surround the outer periphery of the image display portion, in which a plurality of frame electrodes are respectively arranged in a plurality of electrode arrangement regions partitioned in a matrix shape;
    Equipped with
    In each of the electrode arrangement regions, the frame electrodes are arranged such that the difference is within 30% of the peripheral length of the reflective electrode of the pixel in each of the pixel arrangement regions.
    Reflective liquid crystal display.
  4. 　各前記額縁電極は、各前記反射電極の周囲長と同一の周囲長となるように形成されている、
    　請求項３に記載の反射型液晶表示装置。     Each of the frame electrodes is formed to have the same peripheral length as the peripheral length of each of the reflective electrodes.
    The reflective liquid crystal display device according to claim 3.
  5. 　各前記額縁電極は、
    　矩形状の本体部と、
    　前記本体部の外周辺の一部から突出するようにして設けられた連結部と、
    　を有し、
    　前記連結部によって、隣接する他の前記額縁電極と電気的に接続されている、
    　請求項１～４の何れか一項に記載の反射型液晶表示装置。     Each of the frame electrodes is
    A rectangular main body,
    A connecting portion provided to protrude from a part of the outer periphery of the main body portion;
    Have
    It is electrically connected to the other adjacent frame electrode by the connecting portion,
    A reflective liquid crystal display device according to any one of claims 1 to 4.
  6. 　各前記額縁電極は、
    　前記反射電極と同じ平面形状を有し、
    　下位階層に形成された配線によって、隣接する他の前記額縁電極と電気的に接続されている、
    　請求項１～４の何れか一項に記載の反射型液晶表示装置。     Each of the frame electrodes is
    It has the same planar shape as the reflective electrode,
    It is electrically connected to the other adjacent frame electrode by the wiring formed in the lower layer,
    A reflective liquid crystal display device according to any one of claims 1 to 4.
PCT/JP2018/041791 2017-11-15 2018-11-12 Reflective liquid crystal display device WO2019098151A1 (en)

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