WO2019085849A1 - 一种存储设备及存储*** - Google Patents

一种存储设备及存储*** Download PDF

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Publication number
WO2019085849A1
WO2019085849A1 PCT/CN2018/112336 CN2018112336W WO2019085849A1 WO 2019085849 A1 WO2019085849 A1 WO 2019085849A1 CN 2018112336 W CN2018112336 W CN 2018112336W WO 2019085849 A1 WO2019085849 A1 WO 2019085849A1
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Prior art keywords
input
output interface
storage device
card
backplane
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PCT/CN2018/112336
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English (en)
French (fr)
Inventor
戴庆军
高振中
陈业嘉
黄利兵
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中兴通讯股份有限公司
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Priority to EP18873497.4A priority Critical patent/EP3709176A1/en
Publication of WO2019085849A1 publication Critical patent/WO2019085849A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/14—Mounting supporting structure in casing or on frame or rack
    • H05K7/1438—Back panels or connecting means therefor; Terminals; Coding means to avoid wrong insertion
    • H05K7/1459—Circuit configuration, e.g. routing signals

Definitions

  • the present application relates to the field of storage, for example, to a storage device and a storage system.
  • an independent IO interface card is used to provide an external IO interface, and the IO interface card is interconnected with the control board through the backplane.
  • the width is up to 447mm.
  • one storage device can have up to 16 IO interface cards in one row, and one main control board can support up to 8 IO interface card.
  • the related main control board uses a central processing unit (CPU) to provide an interface link.
  • CPU central processing unit
  • PCIE serial computer interconnect Express
  • Link and each IO interface card generally requires 8 PCIE interface links. If you need to support 8 IO interface cards, you must add a PCIE bridge between the CPU and the IO interface card.
  • the traffic of the multiple IO interface cards needs to be sent to the CPU through the centralized scheduling of the PCIE bridge.
  • the switching is centralized. When the traffic is large, the processing delay is caused, and the switching bottleneck is formed. , affect system performance indicators.
  • the embodiment of the present application provides a storage device and a storage system to avoid a situation in which a related storage device needs to add a PCI bottle bridge between a CPU and an IO interface card.
  • the embodiment of the present application provides a storage device, including: a backboard, a plurality of input and output interface cards disposed on a first mounting surface of the backplane, and a plurality of main control boards disposed on the second mounting surface of the backplane, and an input/output interface
  • the card is mounted on the backboard through the backplane connector; at least one main control panel is provided with at least two central processors, and the interface links of at least two central processors are directly connected to the backplane.
  • the embodiment of the present application further provides a storage system, including: a mounting rack, and a storage device provided by the embodiment of the present application installed on the mounting rack.
  • FIG. 1 is a schematic structural diagram of a related storage device
  • FIG. 2 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a storage device according to an embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram of a basic IO interface card according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a stacking IO interface card according to an embodiment of the present application.
  • FIG. 7 is a schematic diagram of a combined IO interface card according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a first application of a storage device according to an embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of a second application of a storage device according to an embodiment of the present disclosure.
  • the storage device provided in this embodiment includes: a backboard 21, a plurality of input/output interface cards 22 disposed on the first mounting surface of the backboard 21, and a plurality of mains disposed on the second mounting surface of the backboard.
  • the control board 23, the input/output interface card 22 is mounted on the backboard 21 through the backplane connector; the at least one main control board 23 is provided with at least two central processing units 231, and the interface links of the at least two central processing units 231 are directly connected
  • the backboard 21 is connected.
  • Figure 2 is a plan view of the storage device, not showing all of the main control boards.
  • the number of the plurality of input/output interface cards is 16, and the number of the plurality of main control boards is two; one main control board is connected to the eight input/output interface cards through the backplane connector.
  • the two main control boards are respectively provided with at least two central processing units, and the total number of interface links of at least two central processing units is greater than or equal to the total number of interface links of the eight input/output interface cards.
  • At least two of the central processors have the same specifications.
  • FIG. 3 there are two central processors.
  • a plurality of input and output interface cards are formed from a plurality of combined input and output interface cards, each combined input and output interface card including at least two input and output interface cards.
  • the input and output interface cards within the combined input and output interface card are coupled to the backplane by a common backplane connector.
  • the combined input/output interface card includes a basic input/output interface card and a stack input/output interface card, and the basic input/output interface card is provided with a backplane connector, and the stack input/output interface card passes The backplane connector of the basic I/O interface card is connected to the backplane.
  • the basic input/output interface card includes a first input/output interface, a first input/output processing chip, a first daughter card connector, and a backplane connector, and the backplane connector passes The first interface link is connected to the first input/output processing chip, and the first sub-card connector is connected through the second interface link;
  • the stack input and output interface card comprises a second input/output interface, a second input/output processing chip and a second sub- a card connector; the second daughter card connector is coupled to the first daughter card connector.
  • the present application further provides a storage system, including: a mounting rack, and a storage device provided by the embodiment of the present application installed on the mounting rack.
  • the IO interface card of the storage device is mounted on the backplane through the backplane connector, the main control board is provided with at least two central processors, and the interface links of the at least two central processors are directly connected to the backplane. .
  • the main control board is provided with at least two central processors, and the interface links of the at least two central processors are directly connected to the backplane.
  • the IO interface card is used as a conventional interface card.
  • the storage device provided in this embodiment includes a backplane and 16 IO interfaces disposed on the first mounting surface of the backplane.
  • the card and the two main control boards are disposed on the second mounting surface of the backboard.
  • Figure 3 is a plan view of the storage device. Half of the number of IO interface cards and the main control board are invisible, and the main control board is provided with two CPUs.
  • the interface links of the two CPUs 231 are directly connected to the backplane. This mode is compatible with related IO interface cards.
  • the IO interface card is used as an example of the improved IO interface card provided by the present application.
  • the storage device provided in this embodiment includes a backplane and is disposed on the backplane. 8 combined IO interface cards on the mounting surface and 2 main control boards on the second mounting surface of the backplane.
  • Figure 4 is a plan view of the storage device. Half of the IO interface cards and main control boards are not visible. The control board is provided with two CPUs, and the interface links of the two CPUs 231 are directly connected to the backplane, which can save half of the number of backplane connectors.
  • two CPUs 1 and 2 are disposed on the main control board, wherein CPU1 must be configured to be valid, and the CPU 2 can select whether to take effect according to requirements.
  • CPU1 divides its PCIE device into four IO interface cards through the backplane according to the X8 mode.
  • this application is called the basic IO interface card;
  • CPU2 uses its PCIE device.
  • the four IO interface cards are designed as sub-cards that can be installed on the basic IO interface card.
  • the IO interface card is a stacking IO interface card; the IO interface card of the stack is inserted into a basic IO interface card and combined into an IO card providing two sets of IO ports.
  • this application is called a combined IO card.
  • one main control board can provide an interface of up to eight IO cards.
  • the basic IO interface card is configured with a backplane connector that supports two X8PCIE links.
  • One of the X8PCIEs is connected to the IO processing chip on the base IO interface card, and the IO processing chip is connected to the IO interface module via serdes.
  • the X8PCIE is connected to the daughter card connector on the basic interface card.
  • the daughter card connector is used to connect the stacking IO interface card.
  • the basic IO interface card is configured with the box body, and the corresponding IO interface is sent out through the box panel.
  • the stack IO interface card is configured with a daughter card connector that supports one X8 PCIE link.
  • the X8PCIE is connected to the IO processing chip on the stack IO interface card, and the IO processing chip is connected to the IO interface module through the serdes.
  • the stack IO interface card is only used with the basic IO interface card, and the box is not separately configured.
  • the stack IO interface card is installed on the base IO interface card to form a combined IO interface card.
  • the basic IO interface card is configured on the backplane connector.
  • the other X8PCIE is finally connected to the IO processing chip on the stack IO interface card through the daughter card connector of the board and the daughter card connector of the stack IO interface card.
  • the combination IO interface card configuration box body, the basic IO interface card and the stack IO interface card through the box panel to the corresponding IO interface, the combination interface card provides twice the IO interface of the basic IO interface card.
  • control board only configures CPU1 to take effect.
  • CPU1 sends out four X8PCIE links, which are connected to four basic IO interface cards through the backplane.
  • the PCIE link between the CPU and the IO card is exactly the same. There is no exchange bottleneck.
  • the next control board can provide 4 IO card interfaces.
  • control board is configured with CPU1 and CPU2, and the CPU1 sends out four PCIE X8 links, which are connected to the four basic IO interface cards through the backplane.
  • the CPU2 sends out four PCIE X8 links through the backplane.
  • the PCIE link between the CPU and the IO card is completely consistent, and there is no exchange bottleneck.
  • the next control board can provide 8 IO card interfaces.
  • the CPU configuration of the basic IO interface card, the IO interface card, the combined IO interface card, and the control board can effectively avoid the situation that the disk array in the storage domain needs multiple IO interfaces, and one control board can be in the case of no exchange bottleneck.
  • the interface of 8 IO cards is provided externally.
  • the IO interface card of the storage device is installed on the backboard through the backplane connector, and the main control board is provided with at least two central processors, interfaces of at least two central processors
  • the link is directly connected to the backplane.
  • a main control board can support a larger number.
  • the IO interface card at the same time, because the CPU is directly connected to the IO interface card, there is no need to set the PCIE bridge, which avoids the need for the storage bottleneck caused by the PCIE bridge between the CPU and the IO interface card.
  • each of the modules or steps of the above-described embodiments of the present application can be implemented with a general purpose computing device. They can be centralized on a single computing device or distributed across a network of multiple computing devices. For example, they may be implemented by program code executable by a computing device so that they can be stored in a computer storage medium such as a (Read Only Memory/Random Access Memory, ROM/RAM), a magnetic disk, or an optical disk. . And in some cases, the steps shown or described may be performed in an order different from that herein, or they may be separately fabricated into a plurality of integrated circuit modules, or a plurality of modules or steps thereof may be A single integrated circuit module is implemented. Therefore, the application is not limited to any particular combination of hardware and software.

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Abstract

本申请实施例提供一种存储设备及存储***，存储设备包括：背板、设置在所述背板第一安装面的多个输入输出接口卡、以及设置在所述背板第二安装面的多个主控板，所述输入输出接口卡通过背板连接器安装在所述背板上；至少一个主控板设置有至少两个中央处理器，所述至少两个中央处理器的接口链路直接与所述背板连接。

Description

一种存储设备及存储***
本申请要求在2017年11月06日提交中国专利局、申请号为201711080057.7的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请涉及存储领域，例如涉及一种存储设备及存储***。
背景技术
在相关存储***中，为了支持更多的输入输出(Input Output，IO)接口，采用独立IO接口卡来提供对外IO接口，IO接口卡通过背板与控制板互联。
在实际应用中，由于存储设备需要支持标准机架安装，因此宽度最多为447mm，在这个尺寸限制下，一个存储设备一排最多可以布放16个IO接口卡，一个主控板最多可以支持8个IO接口卡。
如图1所示，相关主控板采用中央处理器(Central Processing Unit，CPU)提供接口链路，现在主流的X86CPU一般有40个高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，PCIE)接口链路，而每个IO接口卡一般需要8个PCIE接口链路，如果需要支持8个IO接口卡的话就必须在CPU和IO接口卡之间加PCIE桥片。
在CPU和IO接口卡之间加PCIE桥片后，多个IO接口卡的流量需要经过PCIE桥片的集中调度后发给CPU，交换集中，在流量大时会造成处理延时，形成交换瓶颈，影响***性能指标。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请实施例提供了一种存储设备及存储***，以避免相关存储设备需要在CPU和IO接口卡之间加PCIE桥片导致的交换瓶颈的情况。
本申请实施例提供一种存储设备，包括：背板、设置在背板第一安装面的多个输入输出接口卡、以及设置在背板第二安装面的多个主控板，输入输出接口卡通过背板连接器安装在背板上；至少一个主控板设置有至少两个中央处理 器，至少两个中央处理器的接口链路直接与背板连接。
本申请实施例还提供一种存储***，包括：安装机架，以及安装在安装机架上的本申请实施例提供的存储设备。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
图1为相关存储设备的结构示意图；
图2为本申请实施例提供的存储设备的结构示意图；
图3为本申请实施例提供的存储设备的结构示意图；
图4为本申请实施例提供的存储设备的结构示意图；
图5为本申请实施例提供的基础IO接口卡的示意图；
图6为本申请实施例提供的叠楼IO接口卡的示意图；
图7为本申请实施例提供的组合IO接口卡的示意图；
图8为本申请实施例提供的存储设备的第一种应用示意图；
图9为本申请实施例提供的存储设备的第二种应用示意图。
具体实施方式
下面通过实施方式结合附图对本申请实施例作进一步详细说明。应当理解，此处所描述的实施例仅仅用以解释本申请，并不用于限定本申请。
请参见图2，本实施例提供的存储设备，包括：背板21、设置在背板21第一安装面的多个输入输出接口卡22、以及设置在背板第二安装面的多个主控板23，输入输出接口卡22通过背板连接器安装在背板21上；至少一个主控板23设置有至少两个中央处理器231，至少两个中央处理器231的接口链路直接与背板21连接。图2为存储设备的平面图，并未示出所有主控板。
在一些实施例中，多个输入输出接口卡的数目为16个，多个主控板的数目为2个；1个主控板通过背板连接器连接8个输入输出接口卡。
在一些实施例中，2个主控板分别设置有至少两个中央处理器，至少两个中央处理器的接口链路总数大于或等于8个输入输出接口卡的接口链路总数。
在一些实施例中，至少两个中央处理器的规格相同。
在一些实施例中，如图3所示，中央处理器为2个。
在一些实施例中，如图9所示，多个输入输出接口卡由多个组合输入输出 接口卡形成，每个组合输入输出接口卡包括至少两个输入输出接口卡。
在一些实施例中，如图7所示，组合输入输出接口卡内的输入输出接口卡通过共用的一个背板连接器与所述背板连接。
在一些实施例中，如图7所示，组合输入输出接口卡包括基础输入输出接口卡和叠楼输入输出接口卡，基础输入输出接口卡设置有背板连接器，叠楼输入输出接口卡通过基础输入输出接口卡的背板连接器连接背板。
在一些实施例中，如图5及6所示，基础输入输出接口卡包括第一输入输出接口、第一输入输出处理芯片、第一子卡连接器及背板连接器，背板连接器通过第一接口链路连接第一输入输出处理芯片，通过第二接口链路连接第一子卡连接器；叠楼输入输出接口卡包括第二输入输出接口、第二输入输出处理芯片及第二子卡连接器；第二子卡连接器与第一子卡连接器连接。
同时，本申请还提供了一种存储***，其包括：安装机架，以及安装在安装机架上的本申请实施例提供的存储设备。
在一实施例中，存储设备的IO接口卡通过背板连接器安装在背板上，主控板设置有至少两个中央处理器，至少两个中央处理器的接口链路直接与背板连接。在该方式中，通过在主控板上设置多个CPU、使用这多个CPU的接口链路与IO接口卡连接，保证了一个主控板可以支持更多数量的IO接口卡，同时，由于CPU直接与IO接口卡连接，不需要设置PCIE桥片，避免了相关存储设备需要在CPU和IO接口卡之间加PCIE桥片导致的交换瓶颈的情况。
现结合运用场景对本申请做进一步的说明。
在一实施例中，以IO接口卡为常规接口卡为例，如图3所示的平面图可知，本实施例提供的存储设备包括背板、设置在背板第一安装面的16个IO接口卡、以及设置在背板第二安装面的2个主控板，图3为存储设备的平面图，有一半数量的IO接口卡和主控板看不到，主控板设置有两个CPU，两个CPU 231的接口链路直接与背板连接。该方式兼容相关IO接口卡。
在一实施例中，以IO接口卡为本申请提供的改进后的IO接口卡为例，如图4所示的平面图可知，本实施例提供的存储设备包括背板、设置在背板第一安装面的8个组合IO接口卡、以及设置在背板第二安装面的2个主控板，图4为存储设备的平面图，有一半数量的IO接口卡和主控板看不到，主控板设置有 两个CPU，两个CPU 231的接口链路直接与背板连接，该方式可以节省一半数量的背板连接器。
在一实施例中，如图9所示，主控板上布放两路CPU1和CPU2，其中，必须配置CPU1生效，CPU2可以根据需求选择是否生效。
CPU1将其PCIE设备按照X8的方式通过背板均分给4路IO接口卡，对于这种只使用CPU1的PCIE链路的IO接口卡，本申请称为基础IO接口卡；CPU2将其PCIE设备按照X8的方式均分给4路IO接口卡，这4路IO接口卡设计成可以安装在基础IO接口卡上的子卡，对于这种只和CPU2的PCIE连接的IO接口卡，本申请称为叠楼IO接口卡；叠楼IO接口卡***基础IO接口卡后组合为一个提供2组IO端口的IO卡，对于这种IO接口卡，本申请称为组合IO卡。
这样，当控制板同时配置CPU1和CPU2生效时，且配置组合IO卡时一个主控板最多可对外提供8块IO卡的接口。
如图5所示，基础IO接口卡配置背板连接器，支持2路X8PCIE链路，其中一路X8PCIE连接到基础IO接口卡上的IO处理芯片，IO处理芯片通过serdes连接IO接口模块，另一路X8PCIE连接到基础接口卡上子卡连接器，此子卡连接器用于连接叠楼IO接口卡；同时，基础IO接口卡配置盒体，通过盒体面板对外出相应的IO接口。
如图6所示，叠楼IO接口卡配置一个子卡连接器，支持1路X8PCIE链路，此X8PCIE连接到叠楼IO接口卡上的IO处理芯片，IO处理芯片通过serdes连接IO接口模块，叠楼IO接口卡只配合基础IO接口卡使用，不单独配置盒体。
如图7所示，叠楼IO接口卡安装在基础IO接口卡上，组成组合IO接口卡。基础IO接口卡配置背板连接器上另一路X8PCIE通过本板的子卡连接器、叠楼IO接口卡的子卡连接器最终连接到叠楼IO接口卡上的IO处理芯片。组合IO接口卡配置盒体，基础IO接口卡和叠楼IO接口卡通过此盒体面板对外出相应的IO接口，组合接口卡外提供2倍于基础IO接口卡的IO接口。
如图8所示，控制板只配置CPU1生效，CPU1出4路X8PCIE的链路，通过背板分别连接到4个基础IO接口卡，此时CPU和IO卡之间的PCIE链路是完全一致的，没有交换瓶颈，此配置下一个控制板可对外提供4块IO卡接口。
如图9所示，控制板配置CPU1和CPU2生效，CPU1出4路PCIE X8的链路，通过背板分别连接到4个基础IO接口卡；CPU2出4路PCIE X8的链路，通过背板分别连接到4个叠楼IO接口卡，此时CPU和IO卡之间的PCIE链路 是完全一致的，没有交换瓶颈，此配置下一个控制板可对外提供8块IO卡的接口。
根据上述描述可知，基础IO接口卡、叠楼IO接口卡、组合IO接口卡以及控制板的CPU配置可有效避免存储领域磁盘阵列需要多IO接口的情况，一个控制板可在无交换瓶颈的情况下对外提供8块IO卡的接口。
根据本申请实施例提供的存储设备及存储***，存储设备的IO接口卡通过背板连接器安装在背板上，主控板设置有至少两个中央处理器，至少两个中央处理器的接口链路直接与背板连接，在该方式中，通过在主控板上设置多个CPU、使用这多个CPU的接口链路与IO接口卡连接，保证了一个主控板可以支持更多数量的IO接口卡，同时，由于CPU直接与IO接口卡连接，不需要设置PCIE桥片，避免了相关存储设备需要在CPU和IO接口卡之间加PCIE桥片导致的交换瓶颈的情况。
本领域的技术人员应该明白，上述本申请实施例的每个模块或每个步骤可以用通用的计算装置来实现。它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上。例如，它们可以用计算装置可执行的程序代码来实现，从而可以将它们存储在计算机存储介质，例如(Read Only Memory/Random Access Memory，ROM/RAM)、磁碟、光盘中由计算装置来执行。并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，也可以将它们分别制作成多个集成电路模块，也可以将它们中的多个模块或步骤制作成单个集成电路模块来实现。所以，本申请不限制于任何特定的硬件和软件结合。

Claims (10)

  1. 一种存储设备，包括：背板、设置在所述背板第一安装面的多个输入输出接口卡，以及设置在所述背板第二安装面的多个主控板，所述输入输出接口卡通过背板连接器安装在所述背板上；所述多个主控板中的至少一个主控板设置有至少两个中央处理器，所述至少两个中央处理器的接口链路直接与所述背板连接。
  2. 如权利要求1所述的存储设备，其中，所述多个输入输出接口卡的数目为16个，所述多个主控板的数目为2个；一个所述主控板通过所述背板连接器连接8个所述输入输出接口卡。
  3. 如权利要求2所述的存储设备，其中，2个所述主控板分别设置有至少两个中央处理器，所述至少两个中央处理器的接口链路总数大于或等于所述8个输入输出接口卡的接口链路总数。
  4. 如权利要求1所述的存储设备，其中，所述至少两个中央处理器的规格相同。
  5. 如权利要求1所述的存储设备，其中，所述至少两个中央处理器的数目为2个。
  6. 如权利要求1至5任一项所述的存储设备，其中，所述多个输入输出接口卡由多个组合输入输出接口卡形成，每个所述组合输入输出接口卡包括至少两个输入输出接口卡。
  7. 如权利要求6所述的存储设备，其中，每个所述组合输入输出接口卡内的输入输出接口卡通过共用的一个背板连接器与所述背板连接。
  8. 如权利要求7所述的存储设备，其中，所述组合输入输出接口卡包括基础输入输出接口卡和叠楼输入输出接口卡，所述基础输入输出接口卡设置有背板连接器，所述叠楼输入输出接口卡通过所述基础输入输出接口卡的背板连接器连接背板。
  9. 如权利要求8所述的存储设备，其中，所述基础输入输出接口卡包括第一输入输出接口、第一输入输出处理芯片、第一子卡连接器及背板连接器，所述背板连接器通过第一接口链路连接所述第一输入输出处理芯片，通过第二接口链路连接所述第一子卡连接器；所述叠楼输入输出接口卡包括第二输入输出接口、第二输入输出处理芯片及第二子卡连接器；所述第二子卡连接器与所述第一子卡连接器连接。
  10. 一种存储***，包括：安装机架，以及安装在所述安装机架上的如权利要求1至9任一项所述的存储设备。
PCT/CN2018/112336 2017-11-06 2018-10-29 一种存储设备及存储*** WO2019085849A1 (zh)

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