WO2019085835A1 - 一种适用于功率半导体器件的超级场板结构及其应用 - Google Patents
一种适用于功率半导体器件的超级场板结构及其应用 Download PDFInfo
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- WO2019085835A1 WO2019085835A1 PCT/CN2018/112150 CN2018112150W WO2019085835A1 WO 2019085835 A1 WO2019085835 A1 WO 2019085835A1 CN 2018112150 W CN2018112150 W CN 2018112150W WO 2019085835 A1 WO2019085835 A1 WO 2019085835A1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 239000003990 capacitor Substances 0.000 claims abstract description 168
- 229910052751 metal Inorganic materials 0.000 claims abstract description 117
- 239000002184 metal Substances 0.000 claims abstract description 117
- 230000005684 electric field Effects 0.000 claims abstract description 54
- 230000001105 regulatory effect Effects 0.000 claims abstract description 38
- 230000008878 coupling Effects 0.000 claims description 37
- 238000010168 coupling process Methods 0.000 claims description 37
- 238000005859 coupling reaction Methods 0.000 claims description 37
- 238000007667 floating Methods 0.000 claims description 37
- 230000004888 barrier function Effects 0.000 claims description 19
- 230000005669 field effect Effects 0.000 claims description 19
- 229910044991 metal oxide Inorganic materials 0.000 claims description 19
- 150000004706 metal oxides Chemical class 0.000 claims description 19
- 239000000758 substrate Substances 0.000 claims description 13
- 230000001808 coupling effect Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 claims description 5
- 230000003247 decreasing effect Effects 0.000 claims description 3
- 230000001939 inductive effect Effects 0.000 abstract description 3
- 230000003071 parasitic effect Effects 0.000 description 22
- 230000000694 effects Effects 0.000 description 17
- 230000015556 catabolic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
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- 239000000969 carrier Substances 0.000 description 3
- 230000001965 increasing effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Definitions
- the present disclosure relates to the field of power semiconductor devices and, more particularly, to a super field plate structure suitable for use in power semiconductor devices and applications thereof.
- Power semiconductor devices include lateral double-diffused metal oxide semiconductor field effect transistors (LDMOS), lateral insulated gate bipolar transistors (LIGBTs), high electron mobility transistors (HEMTs), and high voltage diodes. They are characterized by high breakdown voltage and high current capability, and are widely used in power management systems for electrical equipment such as mobile phones, computers and motors. Power management systems require power semiconductor devices to have as high a breakdown voltage as possible and as much current as possible, and there is a contradiction between the breakdown voltage and current capability of power semiconductor devices. Therefore, technicians in the field of power semiconductor devices are There is a conflict between efforts to address the breakdown voltage and current capability of power semiconductor devices.
- LDMOS lateral double-diffused metal oxide semiconductor field effect transistors
- LIGBTs lateral insulated gate bipolar transistors
- HEMTs high electron mobility transistors
- Field plate technology is a technology that can effectively alleviate the contradiction between the breakdown voltage and current capability of power semiconductor devices.
- the traditional field plate structure mainly includes the source field plate and the floating field plate.
- the source field plate structure is shown in Figure 1.
- the source field plate is connected to the source metal of the device and has a fixed potential.
- the surface potential of the drift region is continuously along the source to the drain. Therefore, the effect of the source field plate increases along the direction of the source and the drain, which results in a uniform lateral electric field distribution on the device surface, which is not conducive to the breakdown voltage optimization of the device, and at the same time, to avoid the source field.
- the plate is too strong, and its length cannot be too long. It can only be placed in a part of the drift region close to the source, and cannot cover the entire drift region. Therefore, the source field plate cannot act on the entire drift region of the device.
- the structure of the floating field plate is shown in Figure 2.
- the potential of the floating field plate is obtained by the inductive coupling of the potential of the drift region of the device.
- the potential is the average potential of the drift surface below the field plate, and the induced potential cannot be adjusted according to the needs of the design personnel. Therefore, the potential of the floating field plate (reference numeral 17 in Fig. 2) is very close to the surface potential of the drift region, and the adjustment of the electric field on the surface of the drift region is very small, and only local electric field adjustment can be performed, and the entire device cannot be drifted.
- the zone obtains a uniform transverse electric field distribution.
- the conventional source field plate and the floating field plate cannot obtain a uniform lateral electric field distribution in the device drift region, and the device withstand voltage capability cannot be optimized.
- the present disclosure proposes a super field plate structure suitable for a power semiconductor device and its application, which can improve the lateral electric field distribution of the surface of the power semiconductor device, improve the lateral withstand voltage capability of the power semiconductor device, and reduce the on-resistance of the device.
- a super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments comprising: an adjustable field plate and an adjustment capacitor, one of the electrodes of the adjustment capacitor being connected to the adjustable field plate or
- the adjustable field plate is directly used as an electrode for adjusting the capacitance, which is called a positive electrode; the other electrode of the regulating capacitor is connected to the electrode which is always at the lowest potential in the power semiconductor device through a metal interconnection, which is called a negative electrode;
- the adjustable field plate is disposed on a surface of the dielectric layer of the power semiconductor device;
- the amount of induced charge and the induced potential on the adjustable field plate can be adjusted so that a uniform lateral electric field distribution is obtained in the drift region corresponding to the position of the super field plate structure.
- the super field plates are spaced apart in the longitudinal direction of the power semiconductor device such that the effect covers the entire drift region of the power semiconductor device, so that the entire drift region obtains a uniform lateral electric field distribution.
- the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate
- a uniform transverse electric field distribution is obtained in the region, and a plurality of super field plates are laterally spaced apart on the surface of the dielectric layer of the power semiconductor device, so that the effect of the super field plate covers the entire drift region, so that a uniform lateral electric field can be obtained in the entire drift region of the power semiconductor device. distributed. Therefore, the super field plate can achieve the best lateral withstand voltage capability of the power semiconductor device.
- the adjustable field plate is intermittently disposed along the width direction of the power semiconductor device, and the adjustable field plate in the width direction is divided into a plurality of adjustable field plate units, and each adjustable field plate unit is connected correspondingly Adjust the capacitance.
- the metal interconnections for connecting the adjustment capacitors and the electrodes which are always at the lowest potential in the power semiconductor device are arranged in a misaligned manner in the length direction. In order to prevent the field plate effect brought by the metal interconnections from overlapping each other in the length direction, the metal interconnection line is prevented from lowering the lateral withstand voltage capability of the power semiconductor device.
- an adjustable field plate is disposed on at least two dielectric layers of the power semiconductor device, and each of the adjustable field plates is connected to one of the electrodes of the adjustment capacitor, and is adjusted.
- the other electrode of the capacitor is connected to an electrode that is always at the lowest potential in the power semiconductor device.
- a lateral double-diffused metal oxide semiconductor field effect transistor comprising: a source metal, a field oxide layer, and a drift region under the field oxide layer, further comprising: the above for power The super field plate structure of the semiconductor device; specifically: setting a plurality of adjustable field plates on the surface of the field oxide layer, and setting a distance between two adjacent adjustable field plates;
- Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal
- the interconnect is connected to the source metal;
- the amount of induced charge and the induced potential on the adjustable field plate can be adjusted, so that a uniform surface transverse electric field distribution is obtained in the drift region.
- the areas covered by the positive and negative electrodes of the adjusting capacitor are successively decreased.
- a gap between the source metal and the drain metal is filled with an insulating dielectric layer.
- a high voltage diode disclosed in one or more embodiments comprising: a cathode metal, a field oxide layer and a drift region under the field oxide layer, further comprising: the above-described super field plate structure suitable for a power semiconductor device; a plurality of adjustable field plates are disposed on the surface of the field oxide layer, and a distance is set between two adjacent adjustable field plates;
- Each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate is connected to the positive electrode of the adjustment capacitor, and the negative electrode of the adjustment capacitor is disposed above the positive electrode of the adjustment capacitor; the negative electrode of all the adjustment capacitors passes through the metal
- the interconnect is connected to the cathode metal;
- the induced potential and the amount of induced charge on the adjustable field plate can be adjusted, so that a uniform surface electric field distribution is obtained in the drift region.
- the gap of the surface of the device is filled with an insulating dielectric layer.
- a high electron mobility transistor comprising: a substrate; a buffer layer disposed above the substrate; a channel layer disposed above the buffer layer; a source metal and a drain layer disposed above the channel layer a metal and a barrier layer, and a source metal and a drain metal are located at both ends of the barrier layer; a dielectric layer and a gate electrode are disposed over the barrier layer; and the super field plate structure suitable for the power semiconductor device is further included Specifically, a plurality of adjustable field plates are disposed on a surface of the dielectric layer between the gate electrode and the drain metal, and a distance is set between two adjacent adjustable field plates; each adjustable field A coupling electrode is disposed above the board, and all the coupling electrodes are connected to the source metal through the metal interconnection;
- the adjustable field plate is the coupled field plate, the coupling electrode is used as the negative electrode of the adjusting capacitor, and the adjustable field plate is used as the positive electrode of the adjusting capacitor, and can be changed by setting the coverage area between the coupling electrode and the corresponding adjustable field plate.
- the coupling effect of the coupling electrode on the corresponding coupling field plate changes the coupling potential of the corresponding coupling field plate, thereby adjusting the transverse electric field in the barrier layer below the corresponding coupling field plate, and finally optimizing the lateral direction between the gate electrode and the drain metal of the device.
- the electric field distribution increases the lateral withstand voltage capability of the device.
- the area covered by the coupling electrode and the corresponding adjustable field plate is successively decreased.
- the metal interconnection between the coupling electrodes and the metal interconnection between the coupling electrode and the source electrode are spaced apart from each other by a set distance in the width direction.
- a potential floating type super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments comprising: an adjustment capacitor and an adjustable field plate; the adjustable field plate being disposed in a power semiconductor device medium The surface of the layer;
- One of the electrodes of the adjustment capacitor is connected to the adjustable field plate, and the other electrode of the adjustment capacitor is used as a field plate potential adjustment electrode of the power semiconductor device, and the potential thereof is provided by an external circuit;
- the external circuit supplies the field plate potential adjustment electrode with the same potential as the electrode having the lowest potential of the power semiconductor device;
- the size of the regulating capacitor in the potential floating type super field plate can change the sensing potential of the adjustable field plate in the potential floating type super field plate, thereby changing the electric field adjustment of the potential floating type super field plate in the drift region of the power semiconductor device.
- the size of the action enables a uniform lateral electric field distribution in the drift region of the power semiconductor device, so that the power semiconductor device can obtain the best lateral withstand voltage capability;
- the external circuit When the power semiconductor device is in an on state, the external circuit provides a potential for the field plate potential adjustment electrode that is higher than the potential of the lowest potential electrode of the power semiconductor device.
- the field plate potential adjusting electrode will make the adjustable field plate potential in the potential floating type super field plate higher than the potential of the drift region of the power semiconductor device through the coupling effect of the adjusting capacitor in the potential floating type super field plate, therefore, the potential The adjustable field plate in the floating super field plate will induce additional carriers on the surface of the drift region of the power semiconductor device to improve the current capability of the power semiconductor device.
- At least two potential floating type super field plate structures are disposed on the surface of the lateral double-diffused metal oxide semiconductor field effect transistor dielectric layer; the electrode of the adjusting capacitor as a power semiconductor device field plate potential adjusting electrode is completely covered with another One electrode.
- a power management chip disclosed in one or more embodiments includes any of the above-described super field plate structures or any of the above-described potential floating type super field plate structures.
- the size of the adjustment capacitor in the super field plate can adjust the sensing potential of the adjustable field plate in the super field plate under the withstand voltage state of the power semiconductor device, By adjusting the size of the capacitor in the super field plate, the sensing potential and the amount of induced charge of the adjustable field plate in the super field plate can be changed, thereby changing the electric field adjustment effect of the super field plate on the drift region of the power semiconductor device, so that the super field
- the drift region under the plate obtains a uniform transverse electric field distribution, and a plurality of super field plates are laterally spaced along the drift region of the power semiconductor device, so that the effect of the super field plate completely covers the entire drift region of the power semiconductor device, so that the entire power semiconductor device can be made.
- a uniform transverse electric field distribution is obtained in the drift region, so that the power semiconductor device can obtain the best lateral withstand voltage capability. Therefore, the super field plate structure proposed by the present disclosure can provide the power semiconductor device with an optimum lateral
- the magnitude of the electric field adjustment effect of the super field plate structure proposed by the present disclosure on the drift region of the power semiconductor device can be adjusted by design. Therefore, by increasing the doping concentration of the drift region of the power semiconductor device, the design of the super field plate can still be adopted.
- the drift region of the power semiconductor device achieves a uniform transverse electric field distribution so as not to degrade the lateral withstand capability of the device. Therefore, the super field plate structure proposed by the present disclosure can enable the power semiconductor device to increase the drift region doping concentration, reduce the on-resistance, and increase the current capability without reducing the lateral withstand voltage capability.
- the adjustment capacitor in the super field plate proposed by the present invention can be realized by using parasitic capacitance between interconnect metals, parasitic capacitance between interconnect metal and polysilicon, or separately fabricated capacitors outside the device, and is compatible with conventional processes. Strong, will not increase the cost of the process;
- the super field plate structure is fully compatible with conventional processes and does not increase the area of the power semiconductor device;
- the super field plate does not increase the area of the power semiconductor device, and only needs to occupy one layer of interconnect metal;
- the size of the adjustment capacitor is not limited by the size of the power semiconductor device, and the selectable range is large, and the selectable range of the electric field adjustment effect of the super field plate on the drift region of the power semiconductor device is correspondingly increased. Big.
- the adjustable field plate in the super field plate structure proposed by the present disclosure may be disposed on different dielectric layers, and the adjustable field plate may be disposed on different dielectric layers to change the adjustable field plate and the power semiconductor device.
- the size of the parasitic capacitance between the drift regions changes the size of the super field plate adjustment, so that the super field plate can meet the needs of different situations and increase the application range of the super field plate.
- the field plate potential adjusting electrode of the potential floating type super field plate is applied with the same potential as the low potential electrode of the power semiconductor device under the withstand voltage state of the power semiconductor device.
- the time-potential floating type field plate has the same effect as the above-mentioned super field plate, and can obtain the optimum lateral withstand voltage capability of the power semiconductor device, and the field plate potential adjustment of the potential floating type super field plate under the conduction state of the power semiconductor device
- the potential applied by the electrode is higher than the potential of the lowest potential electrode of the power semiconductor device, so that the coupling potential of the adjustable field plate in the potential floating type super field plate is higher than the drift region potential of the power semiconductor device, and therefore, the potential floating field plate field plate Additional carriers will be induced in the drift region of the power semiconductor device, increasing the current capability of the power semiconductor device. Therefore, the potential floating type super field plate can achieve the best lateral voltage withstand capability and greater current capability of the power semiconductor device.
- FIG. 1 is a schematic diagram of a three-dimensional structure of an LDMOS with a conventional source field plate
- FIG. 2 is a schematic diagram of a three-dimensional structure of an LDMOS with a conventional floating field plate
- Example 3(a) is a three-dimensional structural diagram of an LDMOS with a super field plate in Example 1;
- Figure 3 (b) is a two-dimensional cross-sectional view of the LDMOS with the super field plate in the first embodiment along the length direction and the thickness direction;
- 3(c) is a top plan view of the LDMOS with the super field plate in the first example
- Example 4 is a schematic view showing a three-dimensional structure of a high voltage diode with a super field plate in Example 2;
- Example 5 is a three-dimensional structural diagram of a high voltage diode terminal structure with a super field plate in Example 3;
- FIG. 6 is a schematic diagram of a three-dimensional structure of a HEMT with a super field plate in Example 4.
- Example 7 is a schematic structural view of an LIGBT with a super field plate in Example 5;
- Example 8 is a schematic structural view of an LDMOS with a potential floating type super field plate in Example 6;
- Fig. 9 is a view showing the potential change of the field plate potential adjusting electrode and the gate electrode of the sixth embodiment with the potential floating type super field plate LDMOS.
- a super field plate structure suitable for a power semiconductor device comprising: an adjustable field plate and an adjustment capacitor, one of the electrodes of the adjustment capacitor being connected to the adjustable field plate, adjusted The other electrode of the capacitor is connected to the electrode having the lowest potential in the power semiconductor device through the metal interconnection 16, and the adjustable field plate is disposed on the surface of the dielectric layer 8 of the power semiconductor device.
- the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate
- the region obtains a uniform transverse electric field distribution
- the metal interconnections 16 for connecting the adjustment capacitor and the low potential electrode of the power semiconductor device may be arranged along the same line in the longitudinal direction or may be arranged in a misalignment; when the metal interconnections 16 are arranged in a misaligned manner, it can be prevented.
- the field plate effects brought about by the metal interconnections 16 are superimposed on each other in the length direction, thereby preventing the metal interconnections 16 from lowering the lateral withstand voltage capability of the power semiconductor device.
- LDMOS metal oxide semiconductor field effect transistor
- the lateral double-diffused metal oxide semiconductor field effect transistor includes: a P-type semiconductor substrate 1 on which a buried oxide layer 2 is provided, and an N-type drift region 3 and a P-type are provided on the buried oxide layer 2.
- the well 4 is provided with a P-type contact region 5 and an N-type source region 6 on the P-type well 4, and a source metal 7 is connected to the P-type contact region 5 and the N-type source region 6, on the N-type drift region 3.
- a field oxide layer and an N-type contact region 9 are provided, a drain metal 10 is connected to the N-type contact region 9, a gate oxide layer 11 is disposed over a portion of the N-type drift region 3 and a portion of the P-type well 4, and gate oxide is formed.
- One end of the layer 11 is opposite to the boundary of the N-type source region 6, the other end of the gate oxide layer 11 is opposite to the boundary of the field oxide layer, the gate electrode 12 is disposed above the gate oxide layer 11, and the gate electrode 12 is extended to the field oxide layer. Above.
- the field oxide layer of the lateral double-diffused metal oxide semiconductor field effect transistor is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be set in the field. Oxide layer surface.
- a plurality of adjustable field plates are disposed on the surface of the field oxide layer, and a distance is set between two adjacent adjustable field plates; each adjustable field plate is connected with an adjustment capacitor;
- the adjustable field plate is connected to the positive electrode of the adjusting capacitor, and the adjusting capacitor negative electrode is arranged above the adjusting capacitor positive electrode;
- the source is the electrode with the lowest potential in the lateral double-diffused metal oxide semiconductor field effect transistor, and the negative electrode of all adjusting capacitors It is connected to the source metal 7 through a metal interconnection 16.
- the number of adjustable field plates is set according to actual needs.
- adjustable field plates shown in Figures 3(a)-(c) is three, respectively: first adjustable field plate 131, second adjustable field plate 132, and third adjustable type Field plate 133;
- a first adjustable capacitor positive electrode 141 is connected to the first adjustable field plate 131, a second adjustable capacitor positive electrode 142 is connected to the second adjustable field plate 132, and a third adjustable field plate 133 is connected to the first adjustable field plate 133.
- a first adjustment capacitor negative electrode 151 is disposed above the first adjustment capacitor positive electrode 141, a second adjustment capacitor negative electrode 152 is disposed above the second adjustment capacitor positive electrode 142, and a third adjustment capacitor is disposed above the third adjustment capacitor positive electrode 143.
- the negative electrode 153, the first adjustment capacitor negative electrode 151, the second adjustment capacitor negative electrode 152, and the third adjustment capacitor negative electrode 153 are connected to the source metal 7 through the metal interconnection 16.
- the adjustment capacitor positive electrode and the adjustment capacitor negative electrode are equal in size and perfectly aligned.
- the area of the third adjustment capacitor negative electrode 153 and the third adjustment capacitor positive electrode 143 covering each other is smaller than the area covered by the second adjustment capacitor negative electrode 152 and the second adjustment capacitor positive electrode 142; the second adjustment capacitor negative electrode 152 and the second
- the area of the adjustment capacitor positive electrode 142 covering each other is smaller than the area covered by the first adjustment capacitor negative electrode 151 and the first adjustment capacitor positive electrode 141.
- the voids in the surface of the lateral double-diffused metal oxide semiconductor field effect device device may be filled with an insulating dielectric layer.
- the positive and negative electrodes of the first regulating capacitor, the positive and negative electrodes of the second regulating capacitor, and the dimensions of the positive and negative electrodes of the third regulating capacitor in the length direction and the width direction can be designed according to the needs of the device.
- the adjustable field plate and adjusting the size of the positive and negative electrodes of the capacitor By setting the adjustable field plate and adjusting the size of the positive and negative electrodes of the capacitor, the amount of induced charge and the induced potential on the adjustable field plate can be adjusted, so that a uniform surface transverse electric field distribution is obtained in the drift region.
- the adjustable field plates are intermittently disposed in the width direction, and each of the segmented adjustable field plate units is connected to the positive plate of the regulating capacitor, and the regulating capacitors on the adjacent two segments are The positive plate of the capacitor is also disconnected, and the negative plate of the regulating capacitor can be disconnected or not.
- the size of the parasitic capacitance between the adjustable field plate and the drift region and the size of the parasitic capacitance between the positive and negative plates of the capacitor can be adjusted.
- the parasitic capacitance between the first adjustable field plate 131 and the N-type drift region 3 is named C131
- the parasitic capacitance between the first adjustment capacitor positive electrode 141 and the first adjustment capacitor negative electrode 151 is Named C141, since the first adjustable field plate 131 is connected to the first regulating capacitor positive electrode 141, the parasitic capacitances C131 and C141 form a series relationship, and when the device is in the off voltage withstand state, the first regulating capacitor negative electrode 151 is at Low potential, and the N-type drift region 3 is at a high potential, according to the voltage division relationship of the series capacitor, the potential of the first adjustable field plate 131 is between the potential of the N-type drift region 3 and the first adjustment capacitor negative electrode Between the potentials of 151, and the potential of the first tunable field plate 131 is affected by the magnitude of the parasitic capacitances C131 and C141.
- the size of the parasitic capacitances C131 and C141 can be adjusted, thereby adjusting the first adjustable type.
- the potential of the field plate 131 can adjust the amount of induced charge on the first adjustable field plate 131 by adjusting the potential of the first adjustable field plate 131, thereby adjusting the magnitude of the action of the first adjustable field plate 131.
- the N-type drift region 3 below the tunable field plate 131 achieves a uniform surface lateral (i.e., lengthwise) electric field distribution.
- the potential of the second adjustable field plate 132 can be adjusted by the length and width design of the second adjustable field plate 132, the second adjusting capacitor positive electrode 142 and the second adjusting electrode negative electrode, thereby making the second
- the N-type drift region 3 under the adjustable field plate 132 obtains a uniform surface transverse electric field distribution, and is designed by the length and width of the third adjustable field plate 133, the third regulating capacitor positive electrode 143, and the third regulating electrode negative electrode.
- the potential of the third adjustable field plate 133 can be adjusted such that the N-type drift region 3 under the third adjustable field plate 133 obtains a uniform surface transverse electric field distribution.
- the super-field plate structure at different lateral positions has different potentials under the device understand voltage state, and the device can obtain uniform surface transverse electric field distribution throughout the drift region, so that the device has the best lateral withstand voltage capability.
- the structure of the high voltage diode includes: a P type semiconductor substrate 1, at P The semiconductor substrate 1 is provided with a buried oxide layer 2, and the buried oxide layer 2 is provided with an N-type drift region 3 and a P-type well 4, and a P-type contact region 5 is provided on the P-type well 4, in a P-type contact.
- a cathode metal 18 is connected to the region 5, a field oxide layer and an N-type contact region 9 are provided on the N-type drift region 3, and an anode metal 19 is connected to the N-type contact region 9.
- the field oxide layer of the high voltage diode is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be disposed on the surface of the field oxide layer.
- a plurality of adjustable field plates are arranged on the surface of the field oxide layer, and the distance between adjacent two adjustable field plates is set; each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate and the adjustable capacitance are The positive electrodes are connected, and a negative electrode of the regulating capacitor is disposed above the positive electrode of the adjusting capacitor; the cathode is an electrode of the high voltage diode which is always at the lowest potential, and the negative electrodes of all the adjusting capacitors are connected to the cathode metal 18 through the metal interconnection 16.
- the voids in the surface of the high voltage diode device with the adjustable field plate may be filled with an insulating dielectric layer.
- the structure of the high voltage diode includes: an anode metal 19, An anode contact region 9 is provided on the anode metal 19, an N-type drift region 3 and a P-type well 4 are provided on the N-type contact region 9, and a P-type contact region 5 is provided on the P-type well 4 in the P-type contact.
- a cathode metal 18 is connected to the region 5, and a field oxide layer is provided on the N-type drift region 3.
- the field oxide layer of the termination structure of the high voltage diode is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be disposed on the surface of the field oxide layer.
- a plurality of adjustable field plates are arranged on the surface of the field oxide layer, and the distance between adjacent two adjustable field plates is set; each adjustable field plate is connected with an adjustment capacitor; the adjustable field plate and the adjustable capacitance are The positive electrodes are connected, and a negative electrode of the regulating capacitor is disposed above the positive electrode of the adjusting capacitor; the cathode is an electrode having the lowest potential in the terminal structure of the high voltage diode, and the negative electrodes of all the adjusting capacitors are connected to the cathode metal 18 through the metal interconnection 16.
- the voids in the surface of the termination structure of the high voltage diode with the adjustable field plate may be filled with an insulating dielectric layer.
- the above-mentioned super field plate structure is also applicable to other power semiconductor devices, such as: insulated gate bipolar transistors and High electron mobility transistors, etc.
- a super field plate structure suitable for a power semiconductor device including: an adjustable field plate and an adjustment capacitor, wherein, as a conventional variation of the adjustment capacitor in the first embodiment, directly An adjustable field plate is used as one of the electrodes for adjusting the capacitance, and the other electrode of the adjustment capacitor is connected to the electrode having the lowest potential in the power semiconductor device through the metal interconnection 16 , and the adjustable field plate is disposed on the dielectric layer 8 of the power semiconductor device s surface.
- the sensing potential of the adjustable field plate in the super field plate can be changed, thereby changing the adjustment effect of the super field plate on the electric field in the drift region of the power semiconductor device, and the drift under the super field plate
- the region obtains a uniform transverse electric field distribution
- Fig. 6 shows an example of the structure in which the super field plate structure of the present embodiment is applied to a high electron mobility transistor.
- the structure of the high electron mobility transistor includes: a substrate 20; a buffer layer 21 disposed above the substrate 20; a channel layer 22 disposed above the buffer layer 21; and a source metal 7 (source electrode) disposed above the channel layer 22, a drain metal 10 (drain electrode) and a barrier layer 23, and a source metal 7 and a drain metal 10 are located at both ends of the barrier layer 23, and a barrier layer 23 is located between the source metal 7 and the drain metal 10; A dielectric layer 8 and a gate electrode 12 are provided above the barrier layer 23.
- the barrier layer of the high electron mobility transistor is also referred to as a drift region according to a conventional understanding by those skilled in the art.
- a plurality of coupled field plates are disposed on the surface of the dielectric layer 8, and a distance is set between adjacent two coupled field plates; each of the coupled field plates is disposed above There is a coupling electrode (ie, the negative electrode of the adjustment capacitor).
- the coupling field plate simultaneously functions as a positive electrode for adjusting the capacitance in the super field plate, and forms an adjustment capacitor in the super field plate with the coupling electrode;
- the source metal 7 It is an electrode that is always at the lowest potential in the high electron mobility transistor. Therefore, all the coupling electrodes are connected to the source metal 7 through the metal interconnection 16; the coverage area between the coupling electrode and the corresponding coupling field plate can be changed.
- the coupling effect of the coupling electrode on the corresponding coupling field plate changes the coupling potential of the corresponding coupling field plate, thereby adjusting the transverse electric field in the barrier layer 23 under the corresponding coupling field plate, and finally optimizing the device gate electrode 12 and the drain metal 10
- the transverse electric field distribution between the devices improves the lateral withstand voltage capability of the device.
- the number of adjustable field plates is three, namely: a first adjustable field plate 131 and a second adjustable field plate 132. And a third adjustable field plate 133;
- a first adjustable capacitor negative electrode 151 is disposed above the first adjustable field plate 131, a second adjustable capacitor negative electrode 152 is disposed above the second adjustable field plate 132, and a third adjustable field plate 133 is disposed above
- the three adjustment capacitor negative electrode 153, the first adjustment capacitor negative electrode 151, the second adjustment capacitor negative electrode 152, the third adjustment capacitor negative electrode 153 and the source metal 7 are connected by a metal interconnection 16; as can be seen from FIG.
- the metal interconnections 16 between the negative electrodes of the respective adjustment capacitors are offset in the length direction, so that the first metal interconnection 16, the second metal interconnection 16 and the third metal interconnection 16 can be avoided.
- the field plate effects appear at the same width position and overlap each other, thereby alleviating the influence of the introduction of the metal interconnection 16 on the lateral withstand voltage capability of the device.
- the voids in the surface of the high electron mobility transistor device with the tunable field plate may be filled with an insulating dielectric layer.
- the parasitic capacitance between the first adjustable field plate 131 and the barrier layer 23 is named C91
- the parasitic capacitance between the first adjustment capacitor negative electrode 151 and the first adjustable field plate 131 is named C101 due to
- the parasitic capacitances C91 and C101 are in series relationship.
- the potential of the first adjustable field plate 131 will be determined by the size of the parasitic capacitances C91 and C101.
- the design of the first adjustable type field plate 131 and the first adjusting capacitor negative electrode 151 can adjust the size of the parasitic capacitances C91 and C101, thereby adjusting the coupling potential of the first adjustable field plate 131, and changing the first adjustable
- the effect of the field plate 131 on the transverse electric field in the lower barrier layer 23 is such that the barrier layer 23 under the first adjustable field plate 131 has a uniform transverse electric field distribution.
- the second adjustable field plate 132 and the barrier layer 23 under the third adjustable field plate 133 also have a uniform transverse electric field distribution, so that the high electron mobility transistor has a near-ideal lateral withstand voltage capability.
- the above super field plate structure is applicable to other power semiconductor devices, such as a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS), in addition to the high electron mobility transistor given in this embodiment. , horizontal insulated gate bipolar transistor (LIGBT) and high voltage diode.
- LDMOS metal oxide semiconductor field effect transistor
- LIGBT horizontal insulated gate bipolar transistor
- a super field plate structure suitable for a power semiconductor device disclosed in one or more embodiments comprising: an adjustable field plate and an adjustment capacitor, wherein, as a conventional deformation of the adjustment capacitor in the first embodiment, adjustment One of the electrodes of the capacitor is connected to the adjustable field plate, the other electrode of the regulating capacitor is realized by the P-well 4, and the P-well 4 is connected to the electrode whose power semiconductor device is always at the lowest potential.
- Fig. 7 shows an example of the structure in which the super field plate structure of the present embodiment is applied to a lateral insulated gate bipolar transistor.
- the structure of the lateral insulated gate bipolar transistor includes: a P-type semiconductor substrate 1 on which an N-type drift region 3 and a P-type well 4 are provided, and an N-type contact is provided on the P-type well 4
- the region 9, the P-type contact region 5 and the first dielectric layer 8-1 are provided with a P-type anode contact region 24 and a second dielectric layer 8-2 on the N-type drift region 3, and are connected on the P-type anode contact region 24.
- a cathode metal 18 is connected to the N-type contact region 9 and the P-type contact region 5, and a gate oxide layer 11 is provided over a portion of the N-type drift region 3 and a portion of the P-type well 4, and the gate oxide layer 11
- One end of the gate oxide layer 11 abuts against the boundary of the N-type contact region 9, and the other end of the gate oxide layer 11 abuts the boundary of the second dielectric layer 8-2 (ie, the second field oxide layer), and a gate is provided on the surface of the gate oxide layer 11.
- Electrode 12 (polysilicon gate), and gate electrode 12 extends above second dielectric layer, in first dielectric layer 8-1 (ie, first field oxide layer), P-type contact region 5, N-type contact region 9, gate A third dielectric layer 25 is disposed above the electrode 12, the second field oxide layer, and the P-type anode contact region 24.
- At least one adjustable field plate is respectively disposed on the surfaces of the second dielectric layer 8-2 and the third dielectric layer 25, and the adjusting capacitance corresponding to the adjustable field plate is respectively disposed on the surface of the first dielectric layer 8-1.
- the positive electrode uses a P-well 4 as a negative electrode for adjusting the capacitance.
- Each of the tunable field plates is connected to a corresponding modulating positive electrode via a heavily doped polysilicon or metal interconnect.
- the adjustable field plate and the adjusting capacitor are all adjustable in size, and the number of adjustable field plates can be set according to actual needs, and the number of positive electrodes of the adjusting capacitor is equal to the total number of adjustable field plates.
- two adjustable field plates are respectively disposed on the surface of the second dielectric layer 8-2 and the surface of the third dielectric layer 25, respectively: a first adjustable field plate 131 and a second adjustable field plate 132. a third adjustable field plate 133 and a fourth adjustable field plate 134; four adjustable capacitor positive electrodes are disposed on the surface of the first dielectric layer 8-1, respectively: a first regulating capacitor positive electrode 141, and a second adjustment The capacitor positive electrode 142, the third adjustment capacitor positive electrode 143, and the fourth adjustment capacitor positive electrode 144.
- the field plate 131 is connected to the first adjusting capacitor positive plate, and the parasitic capacitances C121 and C141 form a series relationship.
- the N-type drift region 3 is at a high potential
- the P-type well 4 is at a low potential
- the potential of the first adjustable field plate 131 is between the potentials of the N-type drift region 3 and the P-type well 4, and the potential of the first adjustable field plate 131 is affected by the parasitic capacitance C121 and The size of the C141 is affected.
- the size of the parasitic capacitances C121 and C141 can be adjusted by adjusting the sizes of the first adjustable field plate 131 and the first adjustment capacitor positive electrode 141, thereby adjusting the induced potential and the induced charge of the first adjustable field plate 131.
- the induced charge on the first tunable field plate 131 is balanced with the positive space charge in the N-type drift region 3, thereby obtaining a uniform surface transverse electric field distribution in the drift region below the first tunable field plate 131.
- the induced potential and the induced charge of the second adjustable field plate 132 can be adjusted to be below the second adjustable field plate 132.
- a uniform surface transverse electric field distribution is obtained in the drift region.
- a uniform surface transverse electric field distribution can be obtained in the drift region below the third adjustable field plate 133 and the fourth adjustable field plate 134.
- the device parameters are designed so that different adjustable field plates have different potentials under the withstand voltage state, so that a uniform surface lateral electric field distribution is obtained in the entire drift region, and the lateral withstand voltage capability of the device is improved.
- the voids in the surface of the laterally insulated gate bipolar transistor device with the tunable field plate may be filled with an insulating dielectric layer.
- the above super field plate structure is applicable to other power semiconductor devices, such as a lateral double-diffused metal oxide semiconductor field effect transistor, in addition to the lateral insulated gate bipolar transistor given in this embodiment.
- LDMOS low-diffused metal oxide semiconductor field effect transistor
- HEMT high electron mobility transistor
- a potential floating type super field plate structure suitable for a power semiconductor device comprising: an adjustment capacitor and an adjustable field plate; the adjustable field plate is disposed on the dielectric layer of the power semiconductor device 8 s surface;
- One of the electrodes of the adjustment capacitor is connected to the adjustable field plate, and the other electrode of the adjustment capacitor is used as the field plate potential adjustment electrode 26 of the power semiconductor device, the potential of which is provided by an external circuit; the field plate potential adjustment electrode 26 is disposed in the third medium The surface of layer 25.
- the external circuit supplies the field plate potential adjustment electrode 26 with the same potential as the low potential electrode of the power semiconductor device;
- the size of the regulating capacitor in the potential floating type super field plate can change the sensing potential of the adjustable field plate in the potential floating type super field plate, thereby changing the electric field adjustment of the potential floating type super field plate in the drift region of the power semiconductor device.
- the size of the action enables a uniform lateral electric field distribution in the drift region of the power semiconductor device, so that the power semiconductor device can obtain the best lateral withstand voltage capability.
- the external circuit supplies the potential of the field plate potential adjustment electrode 26 to be higher than the potential of the lowest potential electrode of the power semiconductor device;
- the field plate potential adjusting electrode 26 causes the adjustable field plate potential in the potential floating type super field plate to be higher than the potential of the drift region of the power semiconductor device by the coupling effect of the adjusting capacitance in the potential floating type super field plate, thereby
- the adjustable field plate in the potential floating super field plate induces additional carriers on the surface of the drift region of the power semiconductor device to improve the current capability of the power semiconductor device.
- Fig. 8 shows an example of the structure in which the potential floating type super field plate structure of the present embodiment is applied to a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOS).
- LDMOS metal oxide semiconductor field effect transistor
- the field oxide layer of the lateral double-diffused metal oxide semiconductor field effect transistor is a dielectric layer, and therefore, the adjustable field plate in the super field plate can be set in the field. Oxide layer surface.
- the structure of the lateral double-diffused metal oxide semiconductor field effect transistor includes: a P-type semiconductor substrate 1 on which an N-type drift region 3 and a P-type well 4 are disposed, and a P-type well 4 is provided
- the N-type source region 6 and the P-type contact region 5 are provided with an N-type contact region 9 (N-type drain region) and a field oxide layer on the N-type drift region 3, and a portion of the N-type drift region 3 and a portion of the P-type well 4
- a gate oxide layer 11 is disposed thereon, and one end of the gate oxide layer 11 and the boundary of the N-type source region 6 are offset, and the other end of the gate oxide layer 11 is opposite to the boundary of the field oxide layer, and a gate electrode is disposed on the surface of the gate oxide layer 11.
- the gate electrode 12 extends above the field oxide layer, and is disposed on a surface of a portion of the P-type well 4, the P-type contact region 5, the N-type source region 6, the gate electrode 12, the N-type contact region 9, and a portion of the field oxide layer a third dielectric layer 25, a drain metal 10 is connected to the N-type contact region 9, and a source metal 7 is connected to the P-type contact region 5 and the N-type source region 6;
- the surface of the field oxide layer (ie, the dielectric layer) is provided with at least two adjustable field plates, each of which is connected to one of the electrodes of the regulating capacitor, and the surface of the third dielectric layer 25 is provided with a regulating capacitor.
- the field plate potential adjusting electrode 26 completely covers the first metal sensing layer 271 and the second metal sensing layer respectively connected to the first adjustable field plate 131, the second adjustable field plate 132 and the third adjustable field plate 133. 272 and a third metal sensing layer 273.
- first adjustable field plate 131 the second adjustable field plate 132, the third adjustable field plate 133, the first metal sensing layer 271, the second metal sensing layer 272, and the third metal sensing
- the size of layer 273 can be adjusted separately depending on the design needs.
- the voids in the surface of the lateral double-diffused metal oxide semiconductor field effect transistor device with the tunable field plate may be filled with an insulating dielectric layer.
- the above super field plate structure is applicable to other power semiconductor devices, such as a lateral insulated gate bipolar transistor, in addition to the lateral double-diffused metal oxide semiconductor field effect transistor given in this embodiment. LIGBT), high electron mobility transistor (HEMT) and high voltage diodes.
- LIGBT high electron mobility transistor
- HEMT high electron mobility transistor
- a super field plate structure and a power semiconductor with a super field plate structure in Embodiment 1, Embodiment 2, Embodiment 3, Embodiment 4, Embodiment 5 or Embodiment 6 are disclosed.
- the field plate structure disclosed in the above embodiments and the power semiconductor device with the super field plate structure may be applied to the driving chip;
- the above-described driver chip is applied to a power management chip, or a device such as a printer, an electric motor, and a flat panel display.
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Abstract
一种适用于功率半导体器件的超级场板结构及其应用,包括:可调型场板(131-133)和调节电容,调节电容的其中一个电极(141-413)与可调型场板(131-133)相连或者直接采用可调型场板(131-133)作为电极,调节电容的另一个电极(151-153)通过金属互连线(16)与功率半导体器件中电位最低的电极相连,可调型场板(131-133)设置于功率半导体器件介质层(8)的表面;通过设置调节电容电极的尺寸,能够调节可调型场板(131-133)上的感应电荷量和感应电位,使得与超级场板结构相对应位置的漂移区(3)内获得均匀的横向电场分布。通过超级场板中调节电容的大小设计可以改变超级场板中可调型场板(131-133)的感应电位和感应电荷量,进而改变超级场板对功率半导体器件漂移区(3)的电场调节作用大小,使漂移区(3)获得均匀的横向电场分布。
Description
本公开涉及功率半导体器件领域,更具体的说,是涉及一种适用于功率半导体器件的超级场板结构及其应用。
功率半导体器件包括横向双扩散金属氧化物半导体场效应管(LDMOS)、横向绝缘栅双极型晶体管(LIGBT)、高电子迁移率晶体管(HEMT)和高压二极管等。它们都具有击穿电压高、电流能力强的特点,广泛应用于手机、计算机和电机等电气设备的电源管理***。电源管理***要求功率半导体器件具有尽量高的击穿电压和尽量大的电流能力,而功率半导体器件的击穿电压和电流能力之间存在相互制约的矛盾,因此,功率半导体器件领域的技术人员都在致力于解决功率半导体器件击穿电压和电流能力之间的矛盾。
场板技术是一种可以有效缓解功率半导体器件击穿电压和电流能力之间矛盾的技术,传统的场板结构主要包括源极场板和浮空场板。
源极场板结构如图1所示,源极场板与器件的源极金属相连,具有固定电位,然而,器件在耐压状态下其漂移区表面电位沿着源极到漏极的方向不断变化,因此,源极场板的作用沿着源极与漏极的方向不断增加,进而导致器件表面无法获得均匀的横向电场分布,不利于器件的击穿电压优化,同时,为了避免源极场板作用过强,其长度不能过长,只能设置在漂移区靠近源极的部分区域,无法覆盖整个漂移区,因此,源极场板无法作用于器件的整个漂移区范围。
浮空场板结构如图2所示,浮空场板的电位由器件漂移区电位感应耦合得到,其电位为场板下方漂移表面的平均电位,其感应电位不能根据设计要员的需要进行调节,因此,浮空场板(图2中的标号17)的电位与漂移区表面电位非常接近,对漂移区表面电场的调节作用非常小,而且只能进行局部的电场调节,无法使器件整个漂移区获得均匀的横向电场分布。
所以,传统的源极场板和浮空场板无法使器件漂移区获得均匀的横向电场分布,不能使器件的耐压能力达到最佳状态。
发明内容
本公开提出了一种适用于功率半导体器件的超级场板结构及其应用,可以改善功率半导体器件表面的横向电场分布,提高功率半导体器件的横向耐压能力,减小器件的导通电阻。
在一个或多个实施方式中公开的一种适用于功率半导体器件的超级场板结构,包括:可调型场板和调节电容,所述调节电容的其中一个电极与可调型场板相连或者直接采用可调型场板作为调节电容的一个电极,称为正电极;调节电容的另一个电极通过金属互连线与功率半导体器件中始终处于最低电位的电极相连,称为负电极;所述可调型场板设置于功率半导体器件介质层的表面;
通过设置调节电容电极的尺寸,能够调节可调型场板上的感应电荷量和感应电位,使得与超级场板结构相对应位置的漂移区内获得均匀的横向电场分布。
进一步地,所述超级场板在功率半导体器件的长度方向上间隔设置多个,使其效果覆盖功率半导体器件的整个漂移区,从而使得整个漂移区获得均匀的横向电场分布。
通过设计超级场板中调节电容的尺寸可以改变超级场板中可调型场板的感应电位,从而改变超级场板对功率半导体器件漂移区中电场的调节作用大小,使超级场板下方的漂移区获得均匀的横向电场分布,通过在功率半导体器件介质层表面横向间隔设置多个超级场板,使超级场板的效果覆盖整个漂移区,即可使功率半导体器件整个漂移区获得均匀的横向电场分布。因此超级场板可以使功率半导体器件获得最佳的横向耐压能力。
进一步地,所述可调型场板沿功率半导体器件宽度方向间断设置,将宽度方向上的可调型场板分成若干个可调型场板单元,每一个可调型场板单元均连接相应的调节电容。
进一步地,用于连接调节电容和功率半导体器件中始终处于最低电位的电极的金属互连线在长度方向上错位排列。以防止金属互连线带来的场板效应在长度方向上相互叠加,从而避免金属互连线降低功率半导体器件的横向耐压能力。
进一步地,功率半导体器件具有至少两层介质层时,在功率半导体器件的至少两层介质层表面均设置可调型场板,每一个可调型场板均连接调节电容的其中一个电极,调节电容的另一个电极与功率半导体器件中始终处于最低电位的电极 相连。
在一个或多个实施方式中公开的一种横向双扩散金属氧化物半导体场效应管,包括:源极金属,场氧化层和位于场氧化层下方的漂移区,还包括:上述的适用于功率半导体器件的超级场板结构;具体为:在所述场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;
每一个可调型场板均连接调节电容;所述可调型场板与调节电容的正电极相连接,在所述调节电容正电极上方设置调节电容负电极;所有调节电容的负电极通过金属互连线与源极金属连接;
通过设置可调型场板和调节电容的正负电极的尺寸,能够调节可调型场板上的感应电荷量和感应电位,使得漂移区内获得均匀的表面横向电场分布。
进一步地,在源极金属到漏极金属的方向上,所述调节电容的正、负电极之间相互覆盖的面积依次递减。
进一步地,所述源极金属和漏极金属之间的空隙采用绝缘介质层填充。
在一个或多个实施方式中公开的一种高压二极管,包括:阴极金属,场氧化层和位于场氧化层下方的漂移区,还包括:上述的适用于功率半导体器件的超级场板结构;具体为:在所述场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;
每一个可调型场板均连接调节电容;所述可调型场板与调节电容的正电极相连接,在所述调节电容正电极上方设置调节电容负电极;所有调节电容的负电极通过金属互连线与阴极金属连接;
通过设置可调型场板和调节电容的正负电极的尺寸,能够调节可调型场板上的感应电位和感应电荷量,使得漂移区内获得均匀的表面电场分布。
进一步地,所述器件表面的空隙采用绝缘介质层填充。
在一个或多个实施方式中公开的一种高电子迁移率晶体管,包括衬底;衬底上方设有缓冲层;缓冲层上方设有沟道层;沟道层上方设有源极金属、漏极金属和势垒层,且源极金属和漏极金属位于势垒层的两端;势垒层上方设有介质层和栅电极;还包括:上述的适用于功率半导体器件的超级场板结构;具体为:在所述栅电极和漏极金属之间的介质层表面设有若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板上方设有一个耦合电极,所有耦合电极 通过金属互连线与源极金属相互连接;
可调型场板即耦合场板,耦合电极作为调节电容的负电极,可调型场板作为调节电容的正电极,通过设置耦合电极与相应可调型场板之间的覆盖面积,能够改变耦合电极对相应耦合场板的耦合作用大小,从而改变相应耦合场板的耦合电位,进而调节相应耦合场板下方势垒层中的横向电场,最终优化器件栅电极与漏极金属之间的横向电场分布,提高器件的横向耐压能力。
进一步地,在源极金属到漏极金属的方向上,所述耦合电极与相应可调型场板之间相互覆盖的面积依次递减。
进一步地,所述耦合电极之间的金属互连线以及耦合电极与源电极之间的金属互连线在宽度方向上相互间隔设定距离。
在一个或多个实施方式中公开的一种适用于功率半导体器件的电位浮动型超级场板结构,包括:调节电容和可调型场板;所述可调型场板设置于功率半导体器件介质层的表面;
调节电容的其中一个电极与可调型场板相连,调节电容的另一个电极作为功率半导体器件的场板电位调节电极,其电位由外部电路提供;
当功率半导体器件处于耐压状态时,外部电路为场板电位调节电极提供与功率半导体器件电位最低的电极相同的电位;
通过电位浮动型超级场板中的调节电容的尺寸设计可以改变电位浮动型超级场板中可调型场板的感应电位,从而改变电位浮动型超级场板对功率半导体器件漂移区中电场的调节作用大小,使功率半导体器件漂移区获得均匀的横向电场分布,使功率半导体器件获得最佳的横向耐压能力;
当功率半导体器件处于导通状态时,外部电路为场板电位调节电极提供的电位高于功率半导体器件最低电位电极的电位。
此时,场板电位调节电极将通过电位浮动型超级场板中调节电容的耦合作用使电位浮动型超级场板中的可调型场板电位高于功率半导体器件漂移区的电位,因此,电位浮动型超级场板中的可调型场板将在功率半导体器件漂移区表面感应出额外的载流子,提高功率半导体器件的电流能力。
进一步地,在横向双扩散金属氧化物半导体场效应管介质层的表面间隔设置至少两个电位浮动型超级场板结构;所述调节电容中作为功率半导体器件场板电 位调节电极的电极完全覆盖另一个电极。
在一个或多个实施方式中公开的一种电源管理芯片,包括上述的任一种超级场板结构或者上述的任一种电位浮动型超级场板结构。
本公开的有益效果:
(1)本公开提出的超级场板结构应用于功率半导体器件时,超级场板中调节电容的大小可以调节超级场板中可调型场板在功率半导体器件耐压状态下的感应电位,因此,通过超级场板中调节电容的大小设计可以改变超级场板中可调型场板的感应电位和感应电荷量,进而改变超级场板对功率半导体器件漂移区的电场调节作用大小,使超级场板下方的漂移区获得均匀的横向电场分布,沿功率半导体器件漂移区横向间隔设置多个超级场板,使超级场板的效果完全覆盖功率半导体器件的整个漂移区,即可使功率半导体器件整个漂移区内获得均匀的横向电场分布,从而使功率半导体器件获得最佳的横向耐压能力。所以,本公开提出的超级场板结构可以使功率半导体器件获得最佳的横向耐压能力。
(2)本公开提出的超级场板结构对功率半导体器件漂移区的电场调节作用大小可以通过设计进行调节,因此,增加功率半导体器件的漂移区掺杂浓度后依然可以通过超级场板的设计使功率半导体器件漂移区获得均匀的横向电场分布,从而不降低器件的横向耐压能力。所以,本公开提出的超级场板结构可以使功率半导体器件在不降低横向耐压能力的情况下提高漂移区掺杂浓度,减小导通电阻,增加电流能力。
(3)本发明提出的超级场板中的调节电容可以采用互连金属之间的寄生电容、互连金属与多晶硅之间的寄生电容或者器件外部单独制作的电容来实现,与传统工艺的兼容性强,不会增加工艺成本;
当调节电容采用互连金属之间的寄生电容实现时,超级场板结构与传统工艺完全兼容,并且不会增加功率半导体器件的面积;
当调节电容采用互连金属与多晶硅之间的寄生电容实现时,超级场板不会增加功率半导体器件的面积,并且只需要占用一层互连金属;
当调节电容采用器件外部单独制作的电容实现时,调节电容的大小不受功率半导体器件尺寸限制,可选择的范围大,超级场板对功率半导体器件漂移区电场调节作用的可选择范围也相应增大。
(4)本公开提出的超级场板结构中的可调型场板可以设置在不同介质层上,将可调型场板设置在不同的介质层上可以改变可调型场板与功率半导体器件漂移区之间的寄生电容大小,进而改变超级场板的调节作用大小,使超级场板可以满足不同情况的需求,增加超级场板的适用范围。
(5)功率半导体器件漂移区横向设置多个超级场板时,用于连接超级场板与功率半导体器件中最低电位电极的金属互连线在器件长度方向上错位排列,防止了金属互连线带来的额外场板作用在长度方向上相互叠加,有效降低了金属互连线对器件横向耐压能力的不利影响。
(6)电位浮动型超级场板应用于功率半导体器件时,在功率半导体器件耐压状态下,电位浮动型超级场板的场板电位调节电极施加与功率半导体器件低电位电极相同的电位,此时电位浮动型场板具有与前述超级场板相同的效果,可以使功率半导体器件获得最佳的横向耐压能力,在功率半导体器件导通状态下,电位浮动型超级场板的场板电位调节电极施加的电位高于功率半导体器件最低电位电极的电位,使得电位浮动型超级场板中可调型场板的耦合电位高于功率半导体器件的漂移区电位,因此,电位浮动型场板场板将在功率半导体器件漂移区感应出额外的载流子,增加功率半导体器件的电流能力。所以,电位浮动型超级场板可以使功率半导体器件获得最佳的横向耐压能力以及更大的电流能力。
说明书附图
构成本公开的一部分的说明书附图用来提供对本公开的进一步理解,本公开的示意性实施例及其说明用于解释本公开,并不构成对本公开的不当限定。
图1是带有传统源极场板的LDMOS三维结构示意图;
图2是带有传统浮空场板的LDMOS三维结构示意图;
图3(a)是实例一中带有超级场板的LDMOS三维结构示意图;
图3(b)是实例一中带有超级场板的LDMOS沿长度方向和厚度方向的二维截面示意图;
图3(c)是实例一中带有超级场板的LDMOS俯视示意图;
图4是实例二中带有超级场板的高压二极管三维结构示意图;
图5是实例三中带有超级场板的高压二极管终端结构的三维结构示意图;
图6是实例四中带有超级场板的HEMT三维结构示意图;
图7是实例五中带有超级场板的LIGBT结构示意图;
图8是实例六中带有电位浮动型超级场板的LDMOS结构示意图;
图9是实例六中带有电位浮动型超级场板LDMOS的场板电位调节电极和栅电极的电位变化示意图。
其中,1.P型半导体衬底,2.埋氧化层,3.N型漂移区,4.P型阱,5.P型接触区,6.N型源区,7.源极金属,8.介质层,8-1.第一介质层,8-2.第二介质层,9.N型接触区,10.漏极金属,11.栅氧化层,12.栅电极,131.第一可调型场板,132.第二可调型场板,133.第三可调型场板,134.第四可调型场板,141.第一调节电容正电极,142.第二调节电容正电极,143.第三调节电容正电极,144.第四调节电容正电极,151.第一调节电容负电极,152.第二调节电容负电极,153.第三调节电容负电极,16.金属互连线,17.浮空场板,18.阴极金属,19.阳极金属,20.衬底,21.缓冲层,22.沟道层,23.势垒层,24.P型阳极接触区,25.第三介质层,26.场板电位调节电极,271.第一金属感应层,272.第二金属感应层,273.第三金属感应层。
应该指出,以下详细说明都是例示性的,旨在对本公开提供进一步的说明。除非另有指明,本公开使用的所有技术和科学术语具有与本公开所属技术领域的普通技术人员通常理解的相同含义。
需要注意的是,这里所使用的术语仅是为了描述具体实施方式,而非意图限制根据本公开的示例性实施方式。如在这里所使用的,除非上下文另外明确指出,否则单数形式也意图包括复数形式,此外,还应当理解的是,当在本说明书中使用术语“包含”和/或“包括”时,其指明存在特征、步骤、操作、器件、组件和/或它们的组合。
实施例一
在一个或多个实施方式中,公开了一种适用于功率半导体器件的超级场板结构,包括:可调型场板和调节电容,调节电容的其中一个电极与可调型场板相连,调节电容的另一个电极通过金属互连线16与功率半导体器件中电位最低的电极相连,可调型场板设置于功率半导体器件介质层8的表面。
通过设计超级场板中调节电容的尺寸可以改变超级场板中可调型场板的感应电位,从而改变超级场板对功率半导体器件漂移区中电场的调节作用大小,使超级场板下方的漂移区获得均匀的横向电场分布;
通过在功率半导体器件介质层8表面横向间隔设置多个超级场板结构即可使功率半导体器件整个漂移区获得均匀的横向电场分布,从而使功率半导体器件获得最佳的横向耐压能力。
需要说明的是,用于连接调节电容和功率半导体器件低电位电极的金属互连线16在长度方向上可以沿同一直线排列,也可以错位排列;当金属互连线16错位排列时,能够防止金属互连线16带来的场板效应在长度方向上相互叠加,从而避免金属互连线16降低功率半导体器件的横向耐压能力。
图3(a)-(c)给出了上述超级场板结构应用于横向双扩散金属氧化物半导体场效应管(LDMOS)的结构实例。
横向双扩散金属氧化物半导体场效应管包括:P型半导体衬底1,在P型半导体衬底1上设有埋氧化层2,在埋氧化层2上设有N型漂移区3和P型阱4,在P型阱4上设有P型接触区5和N型源区6,在P型接触区5和N型源区6上连接有源极金属7,在N型漂移区3上设有场氧化层和N型接触区9,在N型接触区9上连接有漏极金属10,在部分N型漂移区3和部分P型阱4上方设有栅氧化层11,且栅氧化层11的一端和N型源区6的边界相抵,栅氧化层11的另一端与场氧化层的边界相抵,在栅氧化层11上方设有栅电极12,且栅电极12延伸至场氧化层的上方。
需要说明的是,根据本领域技术人员的常规理解,横向双扩散金属氧化物半导体场效应管的场氧化层是一层介质层,因此,超级场板中的可调型场板可以设置于场氧化层表面。
如图3(a)所示,在场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板均连接调节电容;可调型场板与调节电容的正电极相连接,在调节电容正电极上方设置调节电容负电极;源极为横向双扩散金属氧化物半导体场效应管中电位最低的电极,所有调节电容的负电极通过金属互连线16与源极金属7连接。
可调型场板的数量根据实际需要进行设置。
图3(a)-(c)中所示的可调型场板的数量为三个,分别为:第一可调型场板131、第二可调型场板132和第三可调型场板133;
第一可调型场板131上连接有第一调节电容正电极141,第二可调型场板132上连接有第二调节电容正电极142,第三可调型场板133上连接有第三调节电容正电极143;
第一调节电容正电极141上方设有第一调节电容负电极151,第二调节电容正电极142上方设有第二调节电容负电极152,第三调节电容正电极143上方设有第三调节电容负电极153,第一调节电容负电极151、第二调节电容负电极152和第三调节电容负电极153通过金属互连线16与源极金属7相连。
如图3(c)所示,调节电容正电极和调节电容负电极的大小相等,完全对齐。第三调节电容负电极153与第三调节电容正电极143相互覆盖的面积小于第二调节电容负电极152与第二调节电容正电极142相互覆盖的面积;第二调节电容负电极152与第二调节电容正电极142相互覆盖的面积小于第一调节电容负电极151与第一调节电容正电极141相互覆盖的面积。
或者,根据实际需要调整每一个调节电容的覆盖面积。
在另外一些实施方式中,横向双扩散金属氧化物半导体场效应管器件表面的空隙中可以填充绝缘介质层。
第一调节电容正、负电极、第二调节电容正、负电极以及第三调节电容正、负电极在长度方向和宽度方向的尺寸均可以根据器件需要进行设计。通过设置可调型场板以及调节电容的正负电极的尺寸,能够调节可调型场板上的感应电荷量和感应电位,使得漂移区内获得均匀的表面横向电场分布。
在一个或多个实施方式中,将可调型场板沿宽度方向上间断设置,每一个分段的可调型场板单元均连接调节电容的正极板,相邻两分段上的调节电容的正极板也是相应的断开的,调节电容的负极板可以断开也可以不断开。通过上述方式可以调节可调型场板与漂移区之间的寄生电容的大小以及调节电容的正负极板之间的寄生电容的大小。
本实施例中,第一可调型场板131与N型漂移区3之间具有寄生电容,命名为C131,第一调节电容正电极141与第一调节电容负电极151之间具有寄生电容,命名为C141,由于第一可调型场板131与第一调节电容正电极141相连,寄生电 容C131和C141形成串联关系,当器件处于关断耐压状态时,第一调节电容负电极151处于低电位,而N型漂移区3处于高电位,根据串联电容的分压关系可得出,第一可调型场板131的电位介于N型漂移区3的电位和第一调节电容负电极151的电位之间,且第一可调型场板131的电位受寄生电容C131和C141的大小影响。
因此,通过设计第一可调型场板131、第一调节电容正电极141和第一调节电容负电极151的长度和宽度,可以调节寄生电容C131和C141的大小,进而调节第一可调型场板131的电位,通过调节第一可调型场板131的电位可以调节第一可调型场板131上的感应电荷量,进而调节第一可调型场板131的作用大小,使得第一可调型场板131下方的N型漂移区3获得均匀的表面横向(即长度方向)电场分布。
同理,通过第二可调型场板132、第二调节电容正电极142和第二调节电极负电极的长度以及宽度设计,可以调节第二可调型场板132的电位,从而使第二可调型场板132下方的N型漂移区3获得均匀的表面横向电场分布,通过第三可调型场板133、第三调节电容正电极143和第三调节电极负电极的长度以及宽度设计,可以调节第三可调型场板133的电位,从而使第三可调型场板133下方的N型漂移区3获得均匀的表面横向电场分布。
不同横向位置处的超级场板结构在器件关断耐压状态下具有不同的电位,器件可以在整个漂移区内获得均匀的表面横向电场分布,使得器件具有最佳的横向耐压能力。
实施例二
在一个或多个实施方式中,公开了将实施例一中的超级场板结构应用于高压二极管的结构实例,如图4所示,高压二极管的结构包括:P型半导体衬底1,在P型半导体衬底1上设有埋氧化层2,在埋氧化层2上设有N型漂移区3和P型阱4,在P型阱4上设有P型接触区5,在P型接触区5上连接有阴极金属18,在N型漂移区3上设有场氧化层和N型接触区9,在N型接触区9上连接有阳极金属19。
需要说明的是,根据本领域技术人员的常规理解,高压二极管的场氧化层是一层介质层,因此,超级场板中的可调型场板可以设置于场氧化层表面。
在场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板均连接调节电容;可调型场板与调节电容的正电极相连接,在调节电容正电极上方设置调节电容负电极;阴极为高压二极管中一直处于 最低电位的电极,所有调节电容的负电极通过金属互连线16与阴极金属18连接。
超级场板的其余结构与实施例一中的结构相同,不再赘述。
在另外一些实施方式中,带有可调型场板的高压二极管器件表面的空隙中可以填充绝缘介质层。
实施例三
在一个或多个实施方式中,公开了将实施例一中的超级场板结构应用于高压二极管的终端结构的结构实例,如图5中所示,高压二极管的结构包括:阳极金属19,在阳极金属19上设有N型接触区9,在N型接触区9上设有N型漂移区3和P型阱4,在P型阱4上设有P型接触区5,在P型接触区5上连接有阴极金属18,在N型漂移区3上设有场氧化层。
需要说明的是,根据本领域技术人员的常规理解,高压二极管的终端结构的场氧化层是一层介质层,因此,超级场板中的可调型场板可以设置于场氧化层表面。
在场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板均连接调节电容;可调型场板与调节电容的正电极相连接,在调节电容正电极上方设置调节电容负电极;阴极为高压二极管的终端结构中一直处于最低电位的电极,所有调节电容的负电极通过金属互连线16与阴极金属18连接。
超级场板的其余结构与实施例一中的结构相同,不再赘述。
在另外一些实施方式中,带有可调型场板的高压二极管的终端结构表面的空隙中可以填充绝缘介质层。
需要说明的是,上述超级场板结构除了适用于实施例一、实施例二和实施例三中给出的功率半导体器件以外,同样适用于其他功率半导体器件,比如:绝缘栅双极型晶体管和高电子迁移率晶体管等。
实施例四
在一个或多个实施方式中公开了一种适用于功率半导体器件的超级场板结构,包括:可调型场板和调节电容,其中,作为实施例一中调节电容的一种常规变形,直接采用可调型场板作为调节电容的其中一个电极,调节电容的另一个电极通过金属互连线16与功率半导体器件中电位最低的电极相连,可调型场板设 置于功率半导体器件介质层8的表面。
通过设计超级场板中调节电容的尺寸可以改变超级场板中可调型场板的感应电位,从而改变超级场板对功率半导体器件漂移区中电场的调节作用大小,使超级场板下方的漂移区获得均匀的横向电场分布;
通过在功率半导体器件介质层8表面横向间隔设置多个超级场板结构即可使功率半导体器件整个漂移区获得均匀的横向电场分布,从而使功率半导体器件获得最佳的横向耐压能力。
图6给出了本实施方式超级场板结构应用于高电子迁移率晶体管的结构实例。
高电子迁移率晶体管的结构包括:衬底20;衬底20上方设有缓冲层21;缓冲层21上方设有沟道层22;沟道层22上方设有源极金属7(源电极)、漏极金属10(漏电极)和势垒层23,且源极金属7和漏极金属10位于势垒层23的两端,势垒层23位于源极金属7和漏极金属10的中间;势垒层23上方设有介质层8和栅电极12。
需要说明的是,根据本领域技术人员的常规理解,高电子迁移率晶体管的势垒层也被称为漂移区。
如图6所示,在介质层8表面设有若干耦合场板(即可调型场板,下面相同),相邻两个耦合场板之间间隔设定距离;每一个耦合场板上方设有一个耦合电极(即调节电容的负极),在本实施例中耦合场板同时起到超级场板中调节电容正电极的作用,与耦合电极形成超级场板中的调节电容;源极金属7是高电子迁移率晶体管中始终处于最低电位的电极,因此,所有耦合电极通过金属互连线16与源极金属7相互连接;通过设置耦合电极与相应耦合场板之间的覆盖面积,能够改变耦合电极对相应耦合场板的耦合作用大小,从而改变相应耦合场板的耦合电位,进而调节相应耦合场板下方势垒层23中的横向电场,最终优化器件栅电极12与漏极金属10之间的横向电场分布,提高器件的横向耐压能力。
需要说明的是,耦合场板的数量根据实际需要进行设置。
图6给出的带有超级场板结构的高电子迁移率晶体管中,可调型场板的数量为三个,分别为:第一可调型场板131、第二可调型场板132和第三可调型场板133;
第一可调型场板131上方设有第一调节电容负电极151,第二可调型场板132上方设有第二调节电容负电极152,第三可调型场板133上方设有第三调节电容负 电极153,第一调节电容负电极151、第二调节电容负电极152、第三调节电容负电极153和源极金属7之间通过金属互连线16连接;由图6可以看出,各个调节电容负电极之间的金属互连线16在长度方向上错位设置,这样可以避免第一金属互连线16、第二金属互连线16和第三金属互连线16带来的场板效应出现在同一个宽度位置上而相互叠加,从而缓解金属互连线16的引入对器件横向耐压能力的影响。
在另外一些实施方式中,带有可调型场板的高电子迁移率晶体管器件表面的空隙中可以填充绝缘介质层。
第一可调型场板131与势垒层23之间具有寄生电容,命名为C91,第一调节电容负电极151与第一可调型场板131之间具有寄生电容,命名为C101,由于寄生电容C91和C101为串联关系,当器件处于关断耐压状态时,第一可调型场板131的电位将由寄生电容C91和C101的大小共同决定。
因此,通过第一可调型场板131和第一调节电容负电极151的设计可以调节寄生电容C91和C101的大小,进而调节第一可调型场板131的耦合电位,改变第一可调型场板131对其下方势垒层23中横向电场的作用大小,使第一可调型场板131下方的势垒层23中具有均匀的横向电场分布。
同理,第二可调型场板132和第三可调型场板133下方的势垒层23中也具有均匀的横向电场分布,使得高电子迁移率晶体管具有接近理想的横向耐压能力。
需要说明的是,上述超级场板结构除了适用于本实施例中给出的高电子迁移率晶体管以外,同样适用于其他功率半导体器件,比如:横向双扩散金属氧化物半导体场效应管(LDMOS)、横向绝缘栅双极型晶体管(LIGBT)和高压二极管等。
实施例五
在一个或多个实施方式中公开的一种适用于功率半导体器件的超级场板结构,包括:可调型场板和调节电容,其中,作为实施例一中调节电容的一种常规变形,调节电容的其中一个电极与可调型场板相连,调节电容的另一个电极采用P型阱4实现,并且该P型阱4与功率半导体器件始终处于最低电位的电极相连。
图7给出了本实施方式超级场板结构应用于横向绝缘栅双极型晶体管的结构实例。横向绝缘栅双极型晶体管的结构包括:P型半导体衬底1,在P型半导体衬底1上设置有N型漂移区3和P型阱4,在P型阱4上设有N型接触区9、P型接触区5和第一介质层8-1,在N型漂移区3上设有P型阳极接触区24和第二介质层8-2,在P 型阳极接触区24上连接有阳极金属19,在N型接触区9和P型接触区5上连接有阴极金属18,在部分N型漂移区3和部分P型阱4上方设有栅氧化层11,且栅氧化层11的一端和N型接触区9的边界相抵,所述栅氧化层11的另一端与第二介质层8-2(即第二场氧化层)的边界相抵,在栅氧化层11表面设有栅电极12(多晶硅栅),且栅电极12延伸至第二介质层的上方,在第一介质层8-1(即第一场氧化层)、P型接触区5、N型接触区9、栅电极12、第二场氧化层和P型阳极接触区24的上方设有第三介质层25。
在第二介质层8-2和第三介质层25的表面分别设有至少一个可调型场板,在第一介质层8-1表面分别设有与可调型场板相对应的调节电容的正电极,采用P型阱4作为调节电容的负电极。每一个可调型场板均通过重掺杂的多晶硅或金属互连线与与之相对应的调节电容正电极相连。
可调型场板和调节电容的尺寸均可调,可调型场板的数量可以根据实际需要进行设置,调节电容正电极的数量等于可调型场板的总数量。
图7中,在第二介质层8-2表面和第三介质层25表面分别设置两个可调型场板,分别为:第一可调型场板131、第二可调型场板132、第三可调型场板133和第四可调型场板134;在第一介质层8-1表面设置四个调节电容正电极,分别为:第一调节电容正电极141、第二调节电容正电极142、第三调节电容正电极143和第四调节电容正电极144。
第一可调型场板131与N型漂移区3之间存在寄生电容,命名为C121;第一调节电容正极板与P型阱4之间存在寄生电容命名为C141;由于第一可调型场板131和第一调节电容正极板相连,寄生电容C121和C141之间形成串联关系,在器件关断耐压条件下,N型漂移区3处于高电位,P型阱4处于低电位,根据串联电容的分压关系,第一可调型场板131的电位介于N型漂移区3和P型阱4的电位之间,且第一可调型场板131的电位受寄生电容C121和C141的大小影响。
因此,通过调节第一可调型场板131和第一调节电容正电极141的尺寸即可调节寄生电容C121和C141的大小,进而调节第一可调型场板131的感应电位和感应电荷,使得第一可调型场板131上的感应电荷与N型漂移区3中的正空间电荷达到平衡,从而使第一可调型场板131下方的漂移区内获得均匀的表面横向电场分布。
同理,通过调节第二可调型场板132和第二调节电容正电极142的尺寸可以调 节第二可调型场板132的感应电位和感应电荷,使第二可调型场板132下方的漂移区内获得均匀的表面横向电场分布。
同理,也可以使第三可调型场板133和第四可调型场板134下方的漂移区内获得均匀的表面横向电场分布。
因此,通过器件参数设计使不同的可调型场板在关断耐压状态下具有不同的电位,从而使整个漂移区内获得均匀的表面横向电场分布,提高器件的横向耐压能力。
在另外一些实施方式中,带有可调型场板的横向绝缘栅双极型晶体管器件表面的空隙中可以填充绝缘介质层。
需要说明的是,上述超级场板结构除了适用于本实施例中给出的横向绝缘栅双极型晶体管以外,同样适用于其他功率半导体器件,比如:横向双扩散金属氧化物半导体场效应管(LDMOS)、高电子迁移率晶体管(HEMT)和高压二极管等。
实施例六
在一个或多个实施方式中公开了一种适用于功率半导体器件的电位浮动型超级场板结构,包括:调节电容和可调型场板;可调型场板设置于功率半导体器件介质层8的表面;
调节电容的其中一个电极与可调型场板相连,调节电容的另一个电极作为功率半导体器件的场板电位调节电极26,其电位由外部电路提供;场板电位调节电极26设置在第三介质层25的表面。
如图9所示,当功率半导体器件处于耐压状态时,外部电路为场板电位调节电极26提供与功率半导体器件低电位电极相同的电位;
通过电位浮动型超级场板中的调节电容的尺寸设计可以改变电位浮动型超级场板中可调型场板的感应电位,从而改变电位浮动型超级场板对功率半导体器件漂移区中电场的调节作用大小,使功率半导体器件漂移区获得均匀的横向电场分布,使功率半导体器件获得最佳的横向耐压能力。
当功率半导体器件处于导通状态时,外部电路为场板电位调节电极26提供的电位高于功率半导体器件最低电位电极的电位;
此时,场板电位调节电极26将通过电位浮动型超级场板中调节电容的耦合作用使电位浮动型超级场板中的可调型场板电位高于功率半导体器件漂移区的电 位,进而使电位浮动型超级场板中的可调型场板在功率半导体器件漂移区表面感应出额外的载流子,提高功率半导体器件的电流能力。
图8给出了将本实施方式的电位浮动型超级场板结构应用于横向双扩散金属氧化物半导体场效应管(LDMOS)的结构实例。
需要说明的是,根据本领域技术人员的常规理解,横向双扩散金属氧化物半导体场效应管的场氧化层是一层介质层,因此,超级场板中的可调型场板可以设置于场氧化层表面。
横向双扩散金属氧化物半导体场效应管的结构包括:P型半导体衬底1,在P型半导体衬底1上设置有N型漂移区3和P型阱4,在P型阱4上设有N型源区6和P型接触区5,在N型漂移区3上设有N型接触区9(N型漏区)和场氧化层,在部分N型漂移区3和部分P型阱4上方设有栅氧化层11,且栅氧化层11的一端和N型源区6的边界相抵,栅氧化层11的另一端与场氧化层的边界相抵,在栅氧化层11表面设有栅电极12,且栅电极12延伸至场氧化层的上方,在部分P型阱4、P型接触区5、N型源区6、栅电极12、N型接触区9及部分场氧化层的表面设有第三介质层25,在N型接触区9上连接有漏极金属10,在P型接触区5和N型源区6上连接有源极金属7;
场氧化层(即介质层)表面设有至少两个可调型场板,每一个可调型场板均连接调节电容的其中一个电极,在第三介质层25的表面设有调节电容的另一个电极,即场板电位调节电极26;图8中,场氧化层表面分别设有第一可调型场板131、第二可调型场板132和第三可调型场板133;并且场板电位调节电极26完全覆盖分别与第一可调型场板131、第二可调型场板132和第三可调型场板133连接的第一金属感应层271、第二金属感应层272和第三金属感应层273。
需要说明的是,第一可调型场板131、第二可调型场板132、第三可调型场板133、第一金属感应层271、第二金属感应层272和第三金属感应层273的尺寸可以根据设计需要分别进行调节。
在另外一些实施方式中,带有可调型场板的横向双扩散金属氧化物半导体场效应管器件表面的空隙中可以填充绝缘介质层。
需要说明的是,上述超级场板结构除了适用于本实施例中给出的横向双扩散金属氧化物半导体场效应管以外,同样适用于其他功率半导体器件,比如:横向 绝缘栅双极型晶体管(LIGBT)、高电子迁移率晶体管(HEMT)和高压二极管等。
实施例七
在一个或多个实施方式中,公开了实施例一、实施例二、实施例三、实施例四、实施例五或者实施例六中的超级场板结构以及带有超级场板结构的功率半导体器件的具体应用。
在一些实施方式中,可以将上述实施例中公开的场板结构以及带有超级场板结构的功率半导体器件应用于驱动芯片中;
在另外一些实施方式中,将上述的驱动芯片应用于电源管理芯片,或者打印机、电动机以及平板显示器等设备中。
上述虽然结合附图对本公开的具体实施方式进行了描述,但并非对本公开保护范围的限制,所属领域技术人员应该明白,在本公开的技术方案的基础上,本领域技术人员不需要付出创造性劳动即可做出的各种修改或变形仍在本公开的保护范围以内。
Claims (16)
- 一种适用于功率半导体器件的超级场板结构,其特征在于,包括:可调型场板和调节电容,所述调节电容的其中一个电极与可调型场板相连或者直接采用可调型场板作为调节电容的一个电极,称为正电极;调节电容的另一个电极通过金属互连线与功率半导体器件中始终处于最低电位的电极相连,称为负电极;所述可调型场板设置于功率半导体器件介质层的表面;通过设置调节电容电极的尺寸能够设置调节电容的大小,进而调节可调型场板上的感应电荷量和感应电位,使得与超级场板结构相对应位置的漂移区内获得均匀的横向电场分布。
- 如权利要求1所述的一种适用于功率半导体器件的超级场板结构,其特征在于,所述超级场板在功率半导体器件的长度方向上间隔设置至少2个超级场板,以使得整个漂移区获得均匀的横向电场分布。
- 如权利要求2所述的一种适用于功率半导体器件的超级场板结构,其特征在于,所述可调型场板沿功率半导体器件宽度方向间断设置,将宽度方向上的可调型场板分成若干个可调型场板单元,每一个可调型场板单元均连接相应的调节电容。
- 如权利要求2所述的一种适用于功率半导体器件的超级场板结构,其特征在于,用于连接调节电容和功率半导体器件中始终处于最低电位的电极的金属互连线在长度方向上错位排列。
- 如权利要求1所述的一种适用于功率半导体器件的超级场板结构,其特征在于,功率半导体器件具有至少两层介质层时,在功率半导体器件的至少两层介质层表面均设置可调型场板,每一个可调型场板均连接调节电容的其中一个电极,调节电容的另一个电极与功率半导体器件中始终处于最低电位的电极相连。
- 一种横向双扩散金属氧化物半导体场效应管,包括:源极金属,场氧化层和位于场氧化层下方的漂移区,其特征在于,还包括:权利要求1所述的适用于功率半导体器件的超级场板结构;具体为:在所述场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板均连接调节电容;所述可调型场板与调节电容的正电极相连接,在所述调节电容正电极上方设置调节电容负电极;所有调节电容的负电极通过金属互连线与源极金属连接;通过设置可调型场板和调节电容的正负电极的尺寸,能够调节可调型场板上的感应电荷量和感应电位,使得漂移区内获得均匀的表面横向电场分布。
- 如权利要求6所述的横向双扩散金属氧化物半导体场效应管,其特征在于,在源极金属到漏极金属的方向上,所述调节电容的正、负电极之间相互覆盖的面积依次递减。
- 如权利要求6所述的横向双扩散金属氧化物半导体场效应管,其特征在于,所述源极金属和漏极金属之间的空隙采用绝缘介质层填充。
- 一种高压二极管,包括:阴极金属,场氧化层和位于场氧化层下方的漂移区,其特征在于,还包括:权利要求1所述的适用于功率半导体器件的超级场板结构;具体为:在所述场氧化层的表面设置若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板均连接调节电容;所述可调型场板与调节电容的正电极相连接,在所述调节电容正电极上方设置调节电容负电极;所有调节电容的负电极通过金属互连线与阴极金属连接;通过设置可调型场板和调节电容的正负电极的尺寸,能够调节可调型场板上的感应电位和感应电荷量,使得漂移区内获得均匀的表面电场分布。
- 如权利要求9所述的高压二极管,其特征在于,所述器件表面的空隙采用绝缘介质层填充。
- 一种高电子迁移率晶体管,其特征在于,包括:衬底;衬底上方设有缓冲层;缓冲层上方设有沟道层;沟道层上方设有源极金属、漏极金属和势垒层,且源极金属和漏极金属位于势垒层的两端;势垒层上方设有介质层和栅电极;其特征在于,还包括:权利要求1所述的适用于功率半导体器件的超级场板结构;具体为:在所述栅电极和漏极金属之间的介质层表面设有若干可调型场板,相邻两个可调型场板之间间隔设定距离;每一个可调型场板上方设有一个耦合电极,所有耦合电极通过金属互连线与源极金属相互连接;通过设置耦合电极与相应可调型场板之间的覆盖面积,能够改变耦合电极对相应耦合场板的耦合作用大小,从而改变相应耦合场板的耦合电位,进而调节相应耦合场板下方势垒层中的横向电场,最终优化器件栅电极与漏极金属之间的横向电场分布,提高器件的横向耐压能力。
- 如权利要求11所述的高电子迁移率晶体管,其特征在于,在源极金属到漏极金属的方向上,所述耦合电极与相应可调型场板之间相互覆盖的面积依次递减。
- 如权利要求11所述的高电子迁移率晶体管,其特征在于,所述耦合电极之间的金属互连线以及耦合电极与源电极之间的金属互连线在宽度方向上相互间隔设定距离。
- 一种适用于功率半导体器件的电位浮动型超级场板结构,其特征在于,包括:调节电容和可调型场板;所述可调型场板设置于功率半导体器件介质层的表面;调节电容的其中一个电极与可调型场板相连,调节电容的另一个电极作为功率半导体器件的场板电位调节电极,其电位由外部电路提供;当功率半导体器件处于耐压状态时,外部电路为场板电位调节电极提供与功率半导体器件电位最低的电极相同的电位;当功率半导体器件处于导通状态时,外部电路为场板电位调节电极提供的电位高于功率半导体器件最低电位电极的电位。
- 如权利要求14所述的一种适用于功率半导体器件的电位浮动型超级场板结构,其特征在于,在横向双扩散金属氧化物半导体场效应管介质层的表面间隔设置三个电位浮动型超级场板结构;所述调节电容中作为功率半导体器件场板电位调节电极的电极完全覆盖另一个电极。
- 一种电源管理芯片,基特征在于,包括权利要求1-5任一种所述的超级场板结构或者权利要求14-15任一项所述的电位浮动型超级场板结构。
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CN201711036397.XA CN107887427B (zh) | 2017-10-30 | 2017-10-30 | 一种带有可调型场板的高压二极管 |
CN201711040993.5A CN107887432B (zh) | 2017-10-30 | 2017-10-30 | 一种带有电荷可调型场板的横向绝缘栅双极型晶体管 |
CN201711032851.4 | 2017-10-30 | ||
CN201711040993.5 | 2017-10-30 | ||
CN201711036397.X | 2017-10-30 | ||
CN201711032799.2A CN107871778B (zh) | 2017-10-30 | 2017-10-30 | 带有电位浮动型场板的横向双扩散金属氧化物半导体场效应管 |
CN201711032851.4A CN107680997B (zh) | 2017-10-30 | 2017-10-30 | 带有可调型场板的横向双扩散金属氧化物半导体场效应管 |
CN201711034819.XA CN107887426B (zh) | 2017-10-30 | 2017-10-30 | 一种带有电荷可调型场板的p型ldmos结构 |
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CN201810620591.0A CN108847422B (zh) | 2018-06-15 | 2018-06-15 | 带有耦合场板的高电子迁移率晶体管 |
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7709908B2 (en) * | 2007-08-10 | 2010-05-04 | United Microelectronics Corp. | High-voltage MOS transistor device |
CN102790088A (zh) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | 一个击穿电压可以调整rf-ldmos器件 |
CN103515438A (zh) * | 2012-06-20 | 2014-01-15 | 株式会社东芝 | 半导体装置 |
CN106653830A (zh) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | 半导体器件耐压结构 |
CN107680997A (zh) * | 2017-10-30 | 2018-02-09 | 济南大学 | 带有可调型场板的横向双扩散金属氧化物半导体场效应管 |
CN107871778A (zh) * | 2017-10-30 | 2018-04-03 | 济南大学 | 带有电位浮动型场板的横向双扩散金属氧化物半导体场效应管 |
CN107887426A (zh) * | 2017-10-30 | 2018-04-06 | 济南大学 | 一种带有电荷可调型场板的p型ldmos结构 |
CN107887427A (zh) * | 2017-10-30 | 2018-04-06 | 济南大学 | 一种带有可调型场板的高压二极管 |
-
2018
- 2018-10-26 WO PCT/CN2018/112150 patent/WO2019085835A1/zh active Application Filing
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7709908B2 (en) * | 2007-08-10 | 2010-05-04 | United Microelectronics Corp. | High-voltage MOS transistor device |
CN103515438A (zh) * | 2012-06-20 | 2014-01-15 | 株式会社东芝 | 半导体装置 |
CN102790088A (zh) * | 2012-07-20 | 2012-11-21 | 昆山华太电子技术有限公司 | 一个击穿电压可以调整rf-ldmos器件 |
CN106653830A (zh) * | 2015-10-28 | 2017-05-10 | 无锡华润上华半导体有限公司 | 半导体器件耐压结构 |
CN107680997A (zh) * | 2017-10-30 | 2018-02-09 | 济南大学 | 带有可调型场板的横向双扩散金属氧化物半导体场效应管 |
CN107871778A (zh) * | 2017-10-30 | 2018-04-03 | 济南大学 | 带有电位浮动型场板的横向双扩散金属氧化物半导体场效应管 |
CN107887426A (zh) * | 2017-10-30 | 2018-04-06 | 济南大学 | 一种带有电荷可调型场板的p型ldmos结构 |
CN107887427A (zh) * | 2017-10-30 | 2018-04-06 | 济南大学 | 一种带有可调型场板的高压二极管 |
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