WO2019077994A1 - Terahertz device - Google Patents

Terahertz device Download PDF

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Publication number
WO2019077994A1
WO2019077994A1 PCT/JP2018/036842 JP2018036842W WO2019077994A1 WO 2019077994 A1 WO2019077994 A1 WO 2019077994A1 JP 2018036842 W JP2018036842 W JP 2018036842W WO 2019077994 A1 WO2019077994 A1 WO 2019077994A1
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Prior art keywords
terahertz
conductive
rectifying
terminal
disposed
Prior art date
Application number
PCT/JP2018/036842
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French (fr)
Japanese (ja)
Inventor
俊和 向井
在瑛 金
一魁 鶴田
Original Assignee
ローム株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2018155898A external-priority patent/JP7192188B2/en
Application filed by ローム株式会社 filed Critical ローム株式会社
Priority to CN201880067881.5A priority Critical patent/CN111226305B/en
Priority to US16/755,839 priority patent/US10957598B2/en
Publication of WO2019077994A1 publication Critical patent/WO2019077994A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/866—Zener diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/88—Tunnel-effect diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B7/00—Generation of oscillations using active element having a negative resistance between two of its electrodes
    • H03B7/02—Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance
    • H03B7/06—Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device
    • H03B7/08—Generation of oscillations using active element having a negative resistance between two of its electrodes with frequency-determining element comprising lumped inductance and capacitance active element being semiconductor device being a tunnel diode

Definitions

  • the present disclosure relates to a terahertz device.
  • the present disclosure has as its main object to provide a more preferable terahertz device.
  • a terahertz device includes a semiconductor substrate, a terahertz element, and a first rectifying element.
  • the terahertz element is disposed on the semiconductor substrate.
  • the first rectifying element is electrically connected in parallel to the terahertz element.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 2;
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. FIG.
  • FIG. 9 is another cross-sectional view along the line IX-IX in FIG. 2;
  • FIG. 3 is a cross-sectional view taken along the line XI-XI in FIG.
  • FIG. 3 is a cross-sectional view taken along the line XII-XII in FIG.
  • FIG. 5 is another cross-sectional view along the line XII-XII in FIG. 2; It is sectional drawing in alignment with the XIV-XIV line of FIG.
  • It is a circuit diagram of the terahertz element of the first embodiment, a first rectifying element, and a second rectifying element. It is sectional drawing of the 1st rectifier of 1st Embodiment. It is sectional drawing of the 2nd rectifier of 1st Embodiment.
  • FIG. 23 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element, including two cross-sectional views along the line XXIII-XXIII in FIG. 22.
  • FIG. 2 is a cross-sectional view of the terahertz device of the first embodiment. It is a top view of the semiconductor component of the 1st modification of a 1st embodiment. It is a top view of the terahertz device of the 1st modification of a 1st embodiment. It is a top view of the terahertz device of the 2nd modification of a 1st embodiment. It is a top view of the terahertz device of the 3rd modification of a 1st embodiment.
  • FIG. 2 is a cross-sectional view of the terahertz device of the first embodiment. It is a top view of the semiconductor component of the 1st modification of a 1st embodiment. It is a top view of the terahertz device of the 1s
  • FIG. 7 is a cross-sectional view of a terahertz device of another modification of the first embodiment. It is a figure which shows an example of the shape of planar view of a 2nd part. It is a figure which shows an example of the shape of planar view of a 2nd part. It is a figure which shows an example of the shape of planar view of a 2nd part. It is a figure which shows an example of the shape of planar view of a 2nd part. It is a figure which shows an example of the shape of planar view of a 2nd part. It is a figure which shows an example of the shape of planar view of a 2nd part.
  • FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29.
  • FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29.
  • FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29.
  • FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29.
  • FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29.
  • It is a perspective view of the terahertz device of the modification of a 1st embodiment. It is a perspective view of the terahertz device of the modification of a 1st embodiment. It is a top view of the terahertz device of the modification of a 1st embodiment. It is a top view of the terahertz device of the modification of a 1st embodiment.
  • a certain thing A is located on a certain thing B means "a certain thing A is in contact with a certain thing B", and "a certain thing A and "Intermediate thing with another thing B” is included.
  • the terms “some A is laminated to some B” and “some A is laminated onto some B” refer to “some A as being unless otherwise noted. And “being laminated to a certain thing B while being interposed with another thing between a certain thing A and a certain thing B”.
  • FIGS. 1 to 24 A first embodiment of the present disclosure will be described using FIGS. 1 to 24.
  • FIG. 1 is a perspective view of the terahertz device of the first embodiment.
  • the terahertz device A1 shown in the figure includes a semiconductor component B1, a support 8, a resin portion 85, and wires 871 and 872.
  • FIG. 2 is a plan view of the semiconductor component of the first embodiment.
  • the semiconductor component B1 shown in the figure oscillates a high frequency electromagnetic wave of a frequency in the terahertz band.
  • the semiconductor component B1 does not oscillate, but may receive, high frequency electromagnetic waves in the terahertz band.
  • the semiconductor component B1 may be one that oscillates and receives high frequency electromagnetic waves in the terahertz band.
  • the semiconductor component B1 includes the semiconductor substrate 1, the first conductive layer 2, the second conductive layer 3, the insulating layer 4 (see FIG. 5 and the like), the terahertz element 5, the first rectifying element 61, the first And a second rectifying element 62.
  • the semiconductor substrate 1 is made of a semiconductor and has a semi-insulating property.
  • the semiconductor constituting the semiconductor substrate 1 is, for example, InP, but may be a semiconductor other than InP.
  • the semiconductor substrate 1 has a surface 11. The surface 11 faces in the thickness direction Z1 (see FIG. 5 etc.) of the semiconductor substrate 1.
  • the semiconductor substrate 1 includes edges 131-134.
  • the edge 131 and the edge 133 are spaced apart from each other in the first direction X1.
  • the edge 131 and the edge 133 both extend along the second direction X2.
  • the second direction X2 is orthogonal to the first direction X1.
  • the edge 132 and the edge 134 are spaced apart from each other in the second direction X2. Both the edge 132 and the edge 134 extend along the first direction X1.
  • Edge 131 is connected to edge 132
  • edge 132 is connected to edge 133
  • edge 133 is connected to edge 134
  • edge 134 is connected to edge 131.
  • FIG. 4 is a partially enlarged view of region IV of FIG.
  • FIG. 5 is a cross-sectional view showing the details of the terahertz element of the first embodiment.
  • the terahertz element 5 shown in FIGS. 2, 4 and 5 is formed on a semiconductor substrate 1.
  • the terahertz element 5 is electrically connected to the first conductor layer 2 and the second conductor layer 3.
  • the electromagnetic wave emitted from the terahertz element 5 is reflected by the back reflector metal layer 88, and the terahertz element 5 has a surface emission radiation pattern in a direction (thickness direction Z1) perpendicular to the semiconductor substrate 1.
  • the terahertz element 5 is typically an RTD.
  • the terahertz element 5 may be configured by a diode other than the RTD or a transistor.
  • a Tannet (Tunnet T: Tunnel Transit Time) diode an IMP ATT (Impact Ionization Avalanche Transit Time) diode, a GaAs based field effect transistor (FET: Field Effect Transistor), a GaN based FET, a high electron A mobility transistor (HEMT: High Electron Mobility Transistor) or a heterojunction bipolar transistor (HBT) can be comprised.
  • FIG. 6 is a partial enlarged view of FIG.
  • the GaInAs layer 92a is disposed in the semiconductor layer 91a (made of, for example, GaInAs) and is doped with an n-type impurity.
  • the GaInAs layer 93a is disposed on the GaInAs layer 92a and is not doped with impurities.
  • An AlAs layer 94 a is disposed on the GaInAs layer 93 a, an InGaAs layer 95 is disposed on the AlAs layer 94 a, and an AlAs layer 94 b is located on the InGaAs layer 95.
  • the AlAs layer 94a, the InGaAs layer 95, and the AlAs layer 94b constitute an RTD portion.
  • the GaInAs layer 93b is disposed on the AlAs layer 94b and is not doped with impurities.
  • the GaInAs layer 92b is disposed on the GaInAs layer 93b and is doped with an n-type impurity.
  • a GaInAs layer 91b is disposed on the GaInAs layer 92b and is heavily doped with n-type impurities. Then, the first conductor layer 2 is located on the GaInAs layer 91 b.
  • a GaInAs layer heavily doped with an n-type impurity may be interposed between the GaInAs layer 91 b and the first conductor layer 2, unlike FIG. 6. Thereby, the contact between the first conductor layer 2 and the GaInAs layer 91 b can be improved.
  • the region R11 is a region for oscillating the terahertz wave.
  • FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG.
  • FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG.
  • FIG. 10 is another cross-sectional view along the line IX-IX in FIG.
  • FIG. 13 is another cross-sectional view along the line XII-XII in FIG.
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG.
  • the insulating layer 4 shown in FIG. 8 is formed on the semiconductor substrate 1.
  • the insulating layer 4 is made of, for example, SiO 2 .
  • the material forming the insulating layer 4 may be Si 3 N 4 , SiON, HfO 2 , or Al 2 O 3 .
  • the thickness of the insulating layer 4 is, for example, 10 nm to 1000 nm.
  • the insulating layer 4 can be formed by, for example, a CVD method or a sputtering method.
  • the first conductive layer 2 and the second conductive layer 3 are respectively formed on the semiconductor substrate 1.
  • the first conductor layer 2 and the second conductor layer 3 are insulated from each other.
  • the terahertz element 5 is separated from the second conductor layer 3 in the first direction X1 orthogonal to the thickness direction Z1 of the semiconductor substrate 1.
  • the first conductor layer 2 and the second conductor layer 3 each have a laminated structure of metal.
  • the laminated structure of each of the first conductor layer 2 and the second conductor layer 3 is, for example, a structure in which Au, Pd, and Ti are laminated.
  • each of the first conductor layer 2 and the second conductor layer 3 is, for example, a structure in which Au and Ti are laminated.
  • the thickness of each of the first conductor layer 2 and the second conductor layer 3 is, for example, 10 to 2000 nm.
  • Each of the first conductor layer 2 and the second conductor layer 3 can be formed by vacuum evaporation, sputtering, or the like.
  • the first conductive layer 2 includes a first portion 21, a first inductance portion 22, a first capacitor portion 23, and a first electrode 25.
  • the second conductor layer 3 includes a second portion 31, a second inductance portion 32, a second capacitor portion 33, and a second electrode 35.
  • the first portion 21 extends along the first direction X1.
  • the first portion 21 includes a first conductive portion 214 and a second conductive portion 215.
  • the first conductive portion 214 is a long rectangular portion.
  • the first conductive portion 214 may extend along the first direction X1 and function as an antenna.
  • the second conductive portion 215 extends from the first conductive portion 214 toward the second conductive layer 3 in the thickness direction Z1.
  • the second conductive portion 215 overlaps the terahertz element 5 in the thickness direction Z1.
  • the first inductance portion 22 shown in FIGS. 2 and 4 is connected to the first portion 21 and the first capacitor portion 23 and extends from the first portion 21 to the first capacitor portion 23 along the second direction X2.
  • the first inductance unit 22 functions as an inductance.
  • the length L1 (see FIG. 4) in the second direction X2 of the first inductance portion 22 is, for example, 5 ⁇ m to 100 ⁇ m.
  • the width of the first inductance portion 22 is, for example, 1 ⁇ m to 10 ⁇ m.
  • the second portion 31 extends along the third direction X3.
  • the third direction X3 is the direction opposite to the first direction X1.
  • the second portion 31 can function as an antenna.
  • the second inductance portion 32 is connected to the second portion 31 and the second capacitor portion 33, and extends from the second portion 31 to the second capacitor portion 33 along the second direction X2.
  • the second inductance unit 32 functions as an inductance.
  • the length L2 (see FIG. 4) in the second direction X2 of the second inductance portion 32 is, for example, 5 ⁇ m to 100 ⁇ m.
  • the width of the second inductance portion 32 is, for example, 1 ⁇ m to 10 ⁇ m.
  • the first capacitor portion 23 is located on the side of the terahertz element 5 in the second direction X2.
  • the first capacitor portion 23 is rectangular in the thickness direction Z1.
  • FIG. 3 is a view in which the first conductive layer 2 is omitted from FIG.
  • the second capacitor unit 33 is located on the side of the terahertz element 5 in the second direction X2. As shown in FIGS. 12 and 13, the first capacitor portion 23 is interposed between the second capacitor portion 33 and the semiconductor substrate 1. Unlike the present embodiment, the second capacitor unit 33 may be interposed between the first capacitor unit 23 and the semiconductor substrate 1. The second capacitor portion 33 is stacked on the first capacitor portion 23 and is insulated from the first capacitor portion 23 via the insulating layer 4. The second capacitor unit 33 and the first capacitor unit 23 constitute a capacitor. In the present embodiment, the second capacitor portion 33 is rectangular in the thickness direction Z1.
  • the first electrode 25 is connected to the first capacitor unit 23.
  • the first electrode 25 is rectangular.
  • the first electrode 25 is a pad portion to which the wire 871 (see FIG. 11) is bonded.
  • the first electrode 25 has a portion in direct contact with the semiconductor substrate 1. The contact portion overlaps the wire bonding portion in which the wire 871 and the first electrode 25 are in contact in the thickness direction Z1.
  • the first electrode 25 in the thickness direction Z1, includes edges 251 to 254.
  • the edge 251 and the edge 253 both extend along the second direction X2.
  • the edge 252 and the edge 254 are spaced apart from each other in the second direction X2.
  • the edge 252 and the edge 254 both extend along the first direction X1.
  • Edge 251 connects to edge 252, which connects to edge 253, which is spaced apart from edge 254, which connects to edge 251.
  • the edge 251 and the edge 252 respectively extend to the edge 131 and the edge 132 in the thickness direction Z1.
  • the edge 251 and the edge 252 may not extend to the edge 131 and the edge 132 in the thickness direction Z1, respectively.
  • the second electrode 35 is connected to the second capacitor unit 33.
  • the second electrode 35 is rectangular.
  • the second electrode 35 is a pad portion to which the wire 872 (see FIG. 14) is bonded.
  • the second electrode 35 has a portion in direct contact with the semiconductor substrate 1. The contact portion overlaps the wire bonding portion in which the wire 872 and the second electrode 35 are in contact in the thickness direction Z1.
  • the second electrode 35 extends to the edge 133 and the edge 132 in the thickness direction Z1. Unlike the present embodiment, the second electrode 35 may not reach the edge 133 and the edge 132 in the thickness direction Z1. In this case, when dicing the semiconductor substrate 1 in the manufacturing process of the semiconductor component B1, it is possible to suppress the generation of burrs that may be generated by cutting the second electrode 35.
  • the second electrode 35 includes edges 351 to 354 in the thickness direction Z1.
  • the edge 351 and the edge 353 both extend along the second direction X2.
  • the edge 352 and the edge 354 are spaced apart from each other in the second direction X2.
  • Both the edge 352 and the edge 354 extend along the first direction X1.
  • Edge 351 connects to edge 352
  • edge 352 connects to edge 353
  • edge 353 connects to edge 354 and edge 354 is spaced from edge 351.
  • the edge 352 and the edge 353 respectively extend to the edge 132 and the edge 133 in the thickness direction Z1.
  • the edge 352 and the edge 353 may not extend to the edge 132 and the edge 133, respectively, in the thickness direction Z1.
  • FIG. 15 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element of the first embodiment.
  • the first rectifying element 61 is electrically connected in parallel to the terahertz element 5.
  • the first rectifying element 61 is, for example, a diode. Examples of such diodes include zener diodes, Schottky diodes, and light emitting diodes.
  • the first rectifying element 61 includes a first terminal 61A and a second terminal 61B. In the first rectifying element 61, the electrical direction from the first terminal 61A to the second terminal 61B is the forward direction. In normal use, in the first rectifying element 61, current easily flows from the first terminal 61A to the second terminal 61B, and current hardly flows from the second terminal 61B to the first terminal 61A.
  • FIG. 16 is a cross-sectional view of an example of the first rectifying element of the first embodiment.
  • the first rectifying element 61 includes a first semiconductor layer 611 and a second semiconductor layer 612.
  • the first semiconductor layer 611 and the second semiconductor layer 612 are stacked on each other.
  • the first semiconductor layer 611 has a first conductivity type
  • the second semiconductor layer 612 has a second conductivity type opposite to the first conductivity type.
  • the first conductivity type is p-type
  • the second conductivity type is n-type.
  • the first conductivity type is p-type.
  • FIG. 18 shows the current-voltage characteristics of the first rectifying element 61.
  • the direction in which current flows from the first terminal 61A to the second terminal 61B is positive.
  • the absolute value of the first rising voltage value V611 of the first rectifying element 61 is smaller than the absolute value of the first breakdown voltage value V612 of the first rectifying element 61.
  • the first rising voltage value V611 may be larger than the lower limit (the absolute value of the voltage value V11, see FIG. 20) of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave.
  • the first rising voltage value V611 may be larger than the upper limit (the absolute value of the voltage value V12, see FIG.
  • the absolute value of voltage value V11 is, for example, 0.3 to 0.5 V
  • the absolute value of voltage value V12 is, for example, 0.5 to 0.7 V.
  • the absolute value of the first rising voltage value V611 is, for example, 0.4 to 0.9 V.
  • the absolute value of the first breakdown voltage value V612 is, for example, 2 to 8V.
  • the second rectifying element 62 is electrically connected in parallel to the terahertz element 5.
  • the second rectifying element 62 is, for example, a diode. Examples of such diodes include zener diodes, Schottky diodes, and light emitting diodes.
  • the second rectifying element 62 includes a first terminal 62A and a second terminal 62B. In the second rectifying element 62, the electrical direction from the first terminal 62A to the second terminal 62B is the forward direction. In normal use, in the second rectifying element 62, current easily flows from the first terminal 62A to the second terminal 62B, and current hardly flows from the second terminal 62B to the first terminal 62A.
  • FIG. 17 is a cross-sectional view of an example of the second rectifying element of the first embodiment.
  • the second rectifying element 62 includes a first semiconductor layer 621 and a second semiconductor layer 622.
  • the second semiconductor layer 621 and the second semiconductor layer 622 are stacked on each other.
  • the first semiconductor layer 621 has a first conductivity type
  • the second semiconductor layer 622 has a second conductivity type opposite to the first conductivity type.
  • the first conductivity type is p-type
  • the second conductivity type is n-type.
  • the first conductivity type is p-type.
  • FIG. 18 shows the current-voltage characteristics of the second rectifying element 62.
  • the direction in which current flows from the first terminal 62A to the second terminal 62B is positive.
  • the absolute value of the second rising voltage value V621 of the second rectifying element 62 is smaller than the absolute value of the second breakdown voltage value V622 of the second rectifying element 62.
  • the second rising voltage value V621 may be larger than the lower limit (the absolute value of the voltage value V11, see FIG. 20) of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave.
  • the second rising voltage value V621 may be larger than the upper limit (the absolute value of the voltage value V12, see FIG.
  • the absolute value of the second rising voltage value V621 is, for example, 0.4 to 0.9 V.
  • the absolute value of the second breakdown voltage value V622 is, for example, 2 to 8V.
  • the first terminal 61 ⁇ / b> A of the first rectifier element 61 is electrically connected to the second terminal 62 ⁇ / b> B of the second rectifier element 62.
  • the second terminal 61 B of the first rectifying element 61 is electrically connected to the first terminal 62 A of the second rectifying element 62. Therefore, the current-voltage characteristics of the combined element including the first and second rectifying elements 61 and 62 are as shown in FIG. As shown in FIG.
  • FIG. 22 is a partially enlarged view of a region XXII of FIG.
  • FIG. 23 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element, including two cross-sectional views along line XXIII-XXIII in FIG.
  • each of the first rectifier element 61 and the second rectifier element 62 is formed on the semiconductor substrate 1.
  • the first rectifying element 61 and the second rectifying element 62 respectively show the first conductive layer 2 (the first electrode 25 in the example shown in FIGS. 22 and 23) and the second conductive layer 3 (the FIGS. 22 and 23). In the example, it is electrically interposed between the second electrodes 35).
  • a semiconductor layer 71 (first semiconductor layer) and a semiconductor layer 72 (second semiconductor layer) are formed on the semiconductor substrate 1.
  • the semiconductor layer 71 and the semiconductor layer 72 are stacked on each other.
  • the semiconductor layer 71 has a first conductivity type, and the semiconductor layer 72 has a second conductivity type opposite to the first conductivity type.
  • the semiconductor layer 71 can constitute, for example, the first semiconductor layer 611 of the first rectifying element 61 and the first semiconductor layer 621 of the second rectifying element 62.
  • the semiconductor layer 72 can constitute the second semiconductor layer 612 of the first rectifying element 61 and the second semiconductor layer 622 of the second rectifying element 62.
  • the first conductive layer 2 (more specifically, the first electrode 25) has portions 256 and 257, and the second conductive layer 3 (more specifically, the second electrode 35). ) Have sites 356, 357.
  • the portions 256 and 357 are in contact with the semiconductor layer 71, and the portions 257 and 356 are in contact with the semiconductor layer 72.
  • the portion 256 can constitute the first terminal 61A of the first rectifying element 61
  • the second electrode 356 can constitute the second terminal 61B of the first rectifying element 61.
  • the portion 257 can constitute the second terminal 62B of the second rectifying element 62
  • the portion 357 can constitute the first terminal 62A of the second rectifying element 62.
  • FIG. 22 and FIG. 23 show an example in which the first rectifying element 61 and the second rectifying element 62 are formed between the first electrode 25 and the second electrode 35, the first electrode in the first conductive layer 2 is shown.
  • the first rectifying element 61 and the second electrode 35 may be formed between the portion other than 25 and the portion of the second conductor layer 3 other than the second electrode 35.
  • the present disclosure shows an example in which two rectifying elements of the first rectifying element 61 and the second rectifying element 62 are formed, only one of the first rectifying element 61 and the second rectifying element 62 is formed. It is also good.
  • the present disclosure shows an example in which two rectification elements of the first rectification element 61 and the second rectification element 62 are formed, in addition to the first rectification element 61 and the second rectification element 62, the terahertz element 5 is electrically There may be additional elements connected in series or in parallel.
  • FIG. 24 is a cross-sectional view of the terahertz device of the first embodiment.
  • a semiconductor component B1 is disposed on a support 8 shown in FIG.
  • the support 8 includes a substrate 81 and a conductor layer 82.
  • Wiring board 81 is, for example, a glass epoxy board.
  • a semiconductor component B1 is disposed on the wiring substrate 81.
  • the conductor layer 82 is formed on the wiring substrate 81.
  • the conductor layer 82 includes a first conductive element 821 and a second conductive element 822.
  • the first conductive element 821 and the second conductive element 822 are spaced apart from one another.
  • the support 8 may not have a glass epoxy substrate.
  • the support 8 may comprise one or more leads derived from a lead frame.
  • the resin portion 85 is disposed on the wiring board 81.
  • Resin portion 85 is made of, for example, an epoxy resin.
  • the resin portion 85 has a surface 853.
  • the surface 853 faces one side in the thickness direction of the wiring substrate 81 (which coincides with the thickness direction Z1 of the semiconductor substrate 1 in the present embodiment).
  • a space 851 in which the semiconductor component B1 is accommodated is formed in the resin portion 85.
  • the space 851 has a first side 851A and a second side 851B.
  • the first side surface 851A is inclined with respect to the direction Z1.
  • the second side surface 851B is located between the first side surface 851A and the wiring board 81 in the thickness direction Z1.
  • the second side surface 851 B extends along the thickness direction Z 1 of the wiring substrate 81.
  • the dimension of the second side surface 851B in the thickness direction Z1 is larger than the dimension of the terahertz element B1 in the thickness direction Z1.
  • the metal layer 86 may be disposed on the first side surface 851A.
  • the metal layer 86 may also be disposed on the second side surface 851B.
  • the metal layer 86 may be a metal plated layer.
  • the metal layer 86 reflects the terahertz wave more efficiently.
  • the wires 871 and 872 are bonded to the semiconductor component B1 and the wiring board 81 (more strictly, the conductor layer 82).
  • the wire 871 is bonded to the first electrode 25 of the semiconductor component B1 and the first conductive element 822 in the conductive layer 82.
  • the wire 872 is bonded to the second electrode 35 of the semiconductor component B1 and the second conductive element 821 in the conductive layer 82.
  • the first side surface 851A and the second side surface 851B may be made of metal.
  • the terahertz device A1 includes a first rectifying element 61 electrically connected in parallel to the terahertz element 5. According to such a configuration, even if a large voltage is applied to both ends of the terahertz element 5 by, for example, static electricity or the like, it becomes possible to cause current to flow through the first rectifying element 61. As a result, the flow of a large current to the terahertz element 5 can be suppressed, so that the terahertz element 5 can be prevented from breakdown due to static electricity or the like.
  • the terahertz device A1 includes a second rectifying element 62 electrically connected in parallel to both the terahertz element 5 and the first rectifying element 61. According to such a configuration, the terahertz element 5 can be prevented from breakdown due to static electricity or the like for the same reason as described above.
  • the electrical direction from the first terminal 61A to the second terminal 61B is the forward direction.
  • the electrical direction from the first terminal 62A to the second terminal 62B is the forward direction.
  • the first terminal 61 ⁇ / b> A of the first rectifying element 61 is electrically connected to the second terminal 62 ⁇ / b> B of the second rectifying element 62.
  • each of the first rectifier element 61 and the second rectifier element 62 is formed on the semiconductor substrate 1.
  • Such a configuration can be realized while avoiding the increase in size of the semiconductor substrate 1 as much as possible. Therefore, the present embodiment is suitable for avoiding the upsizing of the terahertz device A1.
  • Each configuration of the following modification differs from the configuration shown in FIG. 2 in that the first rectifier element 61 and the second rectifier element 62 are not formed on the semiconductor substrate 1 as shown in FIG. Since the other points are substantially the same, the description will be omitted.
  • the electrical arrangement of the terahertz element 5, the first rectifying element 61, and the second rectifying element 62 is as shown in FIG.
  • Each structure of the following modification can apply the description regarding drawings other than FIG. 22, FIG. 23 in the said embodiment.
  • FIG. 26 is a plan view of the terahertz device of the first modified example of the first embodiment.
  • the first conductive element 821 includes a first portion 821A and a second portion 821B.
  • the imaginary boundaries of the first portion 821A and the second portion 821B are indicated by the two-dot chain lines extending vertically in FIG.
  • the first portion 821A includes an edge 821E.
  • the first portion 821A extends in the longitudinal direction in FIG.
  • the second portion 821 B extends from the first portion 821 A toward the second conductive element 822.
  • the second portion 821B includes an edge 821F. Edge 821F is connected to edge 821E.
  • the 1st rectification element 61 is arranged at the 1st part 821A.
  • the terahertz element 5 is disposed in the first portion 821A and the second portion 821B.
  • the second conductive element 822 includes a first portion 822A and two second portions 822B.
  • the imaginary boundaries of the first portion 822A and the second portion 822B are indicated by the two-dot chain lines extending longitudinally in FIG.
  • a portion of the first portion 822A faces the second portion 821B.
  • the first portion 822A includes an edge 822E.
  • the second portion 822B extends from the first portion 822A toward the first conductive element 821.
  • the second portion 822B includes an edge 822F.
  • a portion of each second portion 822B faces the first portion 821A.
  • Edge 822F is connected to edge 822E.
  • the recess 822R is formed by the first portion 822A and the two second portions 822B.
  • the second portion 821 B of the first conductive element 821 is disposed in the recess 822 R.
  • the 2nd rectification element 62 is arranged at the 1st part 822A and the 2nd part 822B
  • the wire 861 is bonded to the first rectifying element 61 and the second portion 822 B of the second conductive element 822.
  • the wire 862 is bonded to the second rectifying element 62 and the second portion 822 B of the second conductive element 822.
  • the wire 871 is bonded to the semiconductor component B1 and the first portion 821A of the first conductive element 821.
  • the wire 872 is bonded to the semiconductor component B1 and the first portion 822A of the second conductive element 822.
  • the wires 861, 862, 871, 872 are all formed in a plan view avoiding the virtual straight line LL extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment). ing.
  • each of the wires 861, 862, 871, 872 is a virtual straight line extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment) in plan view. Do not cross to LL. In plan view, the first rectifier element 61 and the second rectifier element 62 are disposed on opposite sides of the virtual straight line LL.
  • all of the wires 861, 862, 871, 872 are virtual straight lines LL extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment) in plan view. It is formed avoiding the. According to such a configuration, the wires 861, 862, 871, 872 can hardly affect the oscillation (or reception) of the terahertz wave.
  • the first rectifier element 61 and the second rectifier element 62 are disposed on opposite sides of the virtual straight line LL.
  • the semiconductor component B ⁇ b> 1 can be easily disposed on the center side in plan view of the support 8. It is possible to further reduce the area of the support 8 in plan view while making it difficult to affect the oscillation (or reception) of the terahertz wave.
  • the shapes of the first conductive element 821 and the second conductive element 822 are partially different.
  • the first rectifying element 61 is disposed at the second portion 821B.
  • the semiconductor component B1 is disposed in the first portion 821A and the second portion 821B. According to such a configuration, since the first rectifying element 61 can be disposed further to the right in FIG. 27, the area reduction of the support 8 in a plan view can be realized as compared with the modification shown in FIG.
  • the first rectifier element 61 and the second rectifier element 62 may be arranged.
  • the present disclosure shows an example in which the terahertz device includes the support and the resin portion, but the terahertz device may be a chip type equivalent to the semiconductor device of the present disclosure.
  • FIG. 29 shows another modification.
  • the terahertz device A12 illustrated in FIG. 29 differs from the terahertz device A1 illustrated in FIG. 24 in that the terahertz device A12 further includes a member G10.
  • the configuration of this modification may be combined with a terahertz device other than the terahertz device A1 shown in FIG.
  • the member G ⁇ b> 10 is disposed in the resin portion 85.
  • the member G10 is exposed to the space 851.
  • the space 851 is defined by the resin portion 85 and the member G10.
  • the space 851 formed in the resin portion 85 is filled with a gas. Examples of such gases include, for example, inert gases (eg, nitrogen) and air.
  • the member G10 has a plate shape, but may have another shape.
  • the member G10 may be formed in the resin portion 85 via the bonding layer G12.
  • the space 851 may be sealed by the member G10 (and the bonding layer G12).
  • at least one portion for inserting the member G10 into the resin portion 85 in order to facilitate the arrangement of the member G10 in the resin portion 85 portions 888A to 888D in FIG. 39, FIG. The site 888 may be formed.
  • the member G10 includes a first portion G11, a second portion G13, and a third portion G15.
  • the first portion G11 is made of, for example, an insulating material.
  • the first portion G11 may be, for example, a substrate (including a sheet or a film). It is preferable that the material forming the first portion G11 be, for example, one having a low absorption loss with respect to the terahertz wave and a high transmittance of the terahertz wave.
  • a thin film sheet with a low dielectric constant, a Si substrate with high resistance, or the like can be used as a substrate constituting the first portion G11. When a Si substrate is used, it is easy to form a laminated structure.
  • Other examples of the material constituting the first portion G11 include, for example, a polymer and MgO.
  • the first portion G11 can be formed by transferring a pattern to a sheet-like material.
  • MgO MgO
  • the merit that the absorption loss of the terahertz wave can be reduced can be enjoyed.
  • a compound semiconductor SiC, GaN, GaAs, InP, sapphire, or the like
  • the resistivity may be increased by adjusting the dopant to the compound semiconductor.
  • the second portion G13 is made of, for example, a conductive material (for example, a metal (for example, Cu, Al, Au or the like)).
  • the second portion G13 can exhibit a desired function for terahertz waves.
  • the second portion G13 can exhibit, for example, at least one of the polarization function of the terahertz wave band, the frequency filter function, and the planar lens function.
  • the second portion G13 may include a plurality of layers.
  • the second portion G13 includes G131 and G132.
  • the plurality of layers G131 and G132 are disposed at different positions in the direction Z1 of FIG. 29 (ie, at different height positions).
  • Each of the layers G131 and G132 may exhibit a desired function.
  • the shapes and functions of the layers G131 and G132 in plan view may be different from each other, or may be identical to each other.
  • the second portion G13 may have a structure of only one layer (for example, only the layer G131).
  • the second portion G13 may include three or more layers.
  • the second portion G13 may include at least one band portion, at least one annular portion, and / or at least one dot in a plan view.
  • 30 to 34 show specific examples of the shape of the second portion G13 in plan view.
  • Each layer G131, G132 shown in FIG. 29 may have any of the shapes shown in FIGS. 30 to 34 described later.
  • the second portion G13 shown in FIG. 30 has a plurality of strip portions (i.e., slit structures) in a plan view.
  • the function that can be exhibited by the second portion G13 shown in FIG. 30 is, for example, the polarization function of the terahertz wave band or the frequency filter function.
  • the second portion G13 shown in FIG. 31 has a plurality of annular portions (ie, ring structures) in a plan view.
  • the function that can be exhibited by the second portion G13 shown in FIG. 31 is, for example, an antenna function or a light collecting function.
  • the second portion G13 shown in FIG. 32 has a plurality of dots (that is, a dot structure) in a plan view.
  • the function that can be exerted by the second portion G13 shown in FIG. 32 is, for example, a beam pattern control function or a two-dimensional resonator function.
  • the shape of planar view of 2nd part G13 may be shown in FIG.33 and FIG.34.
  • the third portion G15 is disposed on the second portion G13.
  • the third portion G15 is made of, for example, an insulating material. Examples of such insulating materials include, for example, SiO 2 , SiN, resins, and polymers.
  • the third portion G15 may include a plurality of layers G151 and G152. The plurality of layers G151 and G152 are stacked on one another.
  • the separation distance LL between the member G10 and the semiconductor component B1 shown in FIG. 29 may be smaller than, for example, one wavelength of the terahertz wave from the semiconductor component B1 (effective wavelength in the existing space).
  • the separation distance LL is smaller than one wavelength of the terahertz wave from the semiconductor component B1 (the effective wavelength in the existing space)
  • the terahertz wave from the semiconductor component B1 is appropriately transferred to the outside by using near field coupling. Can be released.
  • the separation distance LL may be smaller than 1 mm.
  • the layer G131 of the second portion G13 is formed in the first portion G11.
  • the layer G131 may be made of metal.
  • Layer G131 can be formed, for example, by patterning.
  • a layer G151 of the third portion G15 is formed.
  • the layer G151 can be formed, for example, by polishing the surface after forming an insulating material on the layer G131. In addition, the said surface grinding
  • polishing does not need to be performed.
  • a layer G132 and a layer G152 are sequentially formed. Thereafter, dicing is performed to manufacture a member G10 shown in FIG.
  • FIG. 41 shows a plan view of the device of this modification.
  • the apparatus shown in the figure is a combination of the configuration shown in FIG. 26 and the configuration shown in FIG.
  • the central point C11 of the semiconductor device B1 coincides with the symmetry point C12 of the second portion G13 (the second portion G13 is symmetrical with respect to the symmetry point C12 in plan view).
  • the configuration shown in FIG. 26 may be combined with the configuration shown in any of FIGS. FIGS. 42 to 45 each show a combination of the configuration shown in FIG. 26 and the configurations shown in FIGS. 31 to 34. Also in FIGS. 42 to 45, the central point C11 of the semiconductor device B1 coincides with the symmetry point C12 of the second portion G13 (the second portion G13 is symmetrical with respect to the symmetry point C12 in plan view). ing.
  • the space 851 formed in the resin portion 85 is filled with a gas. According to such a configuration, it is possible to suppress that the terahertz wave attenuates when passing through the resin, as compared with the case where the space 851 is filled with the resin. Further, according to this modification, the resin adhering to the semiconductor component B1 can reduce or prevent the occurrence of the problem that the boundary conditions change and the resonance mode in the chip substrate is affected.
  • the second portion G13 is made of a conductive material. According to such a configuration, it is possible to cause the second portion G13 to exhibit a desired function for the terahertz wave. Thereby, a more suitable terahertz device can be provided.
  • the second portion G13 may include a plurality of layers G131. In this case, for example, different functions can be exhibited in the plurality of layers G131.
  • the present disclosure includes embodiments regarding the following appendices.
  • Each of the first and second rectifying elements includes a first terminal and a second terminal, and in each of the first and second rectifying elements, the first terminal is directed to the second terminal.
  • the electrical direction is forward,
  • the first rectifying device has a first rising voltage value and a first breakdown voltage value
  • the second rectifying device has a second rising voltage value and a second breakdown voltage value.
  • the absolute value of the first rising voltage value is smaller than the absolute value of the first breakdown voltage value
  • the absolute value of the second rising voltage value is smaller than the absolute value of the second breakdown voltage value
  • the terahertz device according to Appendix 2 or 3 wherein the first rising voltage value and the second rising voltage value are larger than the lower limit of the absolute value of the value in the voltage range where the terahertz element oscillates the terahertz wave.
  • the terahertz device according to claim 4 wherein the first rising voltage value and the second rising voltage value are larger than an upper limit of an absolute value of values in a voltage region where the terahertz element oscillates a terahertz wave.
  • the semiconductor device further comprises a first conductor layer and a second conductor layer which are respectively formed on the semiconductor substrate and insulated from each other.
  • the first rectifying element and the second rectifying element are both formed on the semiconductor substrate, and are electrically interposed between the first conductor layer and the second conductor layer.
  • the terahertz device according to any one of 2 to 5.
  • the semiconductor device further includes a first semiconductor layer and a second semiconductor layer formed on the semiconductor substrate and stacked on each other.
  • the first semiconductor layer has a first conductivity type
  • the second semiconductor layer has a second conductivity type opposite to the first conductivity type.
  • the first terminal of the first rectifying element and the second terminal of the second rectifying element are constituted by the first conductive layer
  • [Supplementary Note 8] Further comprising first and second conductive portions insulated from each other; The terahertz element is electrically interposed between the first conductive site and the second conductive site, The first conductive portion extends in the first direction from the side where the terahertz element is located in a plan view, and the second conductive portion is first side when the terahertz element is located in a plan view. 5.
  • the terahertz device according to any of appendices 2 to 5, extending along a direction opposite to the direction.
  • the semiconductor device further comprises a support on which the semiconductor substrate is disposed, The terahertz element and a first wire bonded to the support, further comprising: The terahertz device according to claim 8, wherein the first wire is formed to avoid an imaginary straight line extending along the first conductive portion in a plan view.
  • the terahertz element and a second wire bonded to the support further comprising: The terahertz device according to claim 9, wherein the second wire is formed avoiding the virtual straight line in a plan view.
  • the terahertz device according to Appendix 9 or 10, wherein the first rectifying element and the second rectifying element are disposed on opposite sides of the virtual straight line in plan view.
  • the support includes a first conductive element and a second conductive element insulated from each other, The terahertz device and the first rectifying element are disposed in the first conductive element, and the second rectifying element is disposed in the second conductive element. Terahertz device.
  • the first conductive element includes a first portion, and a second portion extending from the first portion toward the second conductive element, The terahertz device according to claim 12, wherein the terahertz device is disposed at the second portion of the first conductive element.
  • the terahertz device according to appendix 13 wherein the first rectifying element is arranged at the second portion of the first conductive element.
  • the terahertz device according to Appendix 13 or 14 wherein the second conductive element includes a portion facing the first portion, and the second rectifying element is disposed at the portion in the second conductive element.
  • [Supplementary Note 16] A resin portion in which a space surrounding the terahertz element is formed; A member disposed in the resin portion and exposed to the air gap; 15. The terahertz device according to any one of appendices 1 to 15, wherein the space is filled with a gas.
  • the member includes a first portion disposed in the resin portion and a second portion disposed in the first portion, The terahertz device according to claim 16, wherein the second portion is made of a conductive material.

Abstract

According to one aspect of the present disclosure, a terahertz device is provided. The terahertz device includes a semiconductor substrate, a terahertz element, and a first rectifying element. The terahertz element is disposed on the semiconductor substrate. The first rectifying element is electrically connected in parallel to the terahertz element.

Description

テラヘルツ装置Terahertz device
　本開示は、テラヘルツ装置に関する。 The present disclosure relates to a terahertz device.
　近年、トランジスタなどの電子デバイスの微細化が進み、その大きさがナノサイズになってきたため、量子効果と呼ばれる新しい現象が観測されるようになっている。そして、この量子効果を利用した超高速デバイスや新機能デバイスの実現を目指した開発が進められている。そのような環境の中で、特に、テラヘルツ帯と呼ばれる、周波数が０．１ＴＨｚ～１０ＴＨｚの周波数領域を利用して大容量通信や情報処理、あるいはイメージングや計測などを行う試みが行われている。この周波数領域は、光と電波の中間の未開拓領域であり、この周波数帯で動作するデバイスが実現されれば、上述したイメージング、大容量通信・情報処理のほか、物性、天文、生物などのさまざまな分野における計測など、多くの用途に利用されることが期待されている。 In recent years, miniaturization of electronic devices such as transistors has progressed, and their size has become nano-sized, so a new phenomenon called quantum effect is being observed. Then, development aimed at realizing ultra-high-speed devices and new functional devices utilizing this quantum effect is in progress. In such an environment, in particular, attempts are being made to perform large-capacity communication, information processing, imaging, measurement, etc. using a frequency range of 0.1 THz to 10 THz, which is called a terahertz band. This frequency range is an unexplored range between light and radio waves, and if a device operating in this frequency range is realized, physical properties, astronomy, organisms, etc. as well as the imaging, mass communication, and information processing described above. It is expected to be used for many applications, such as measurement in various fields.
　本開示は、より好ましいテラヘルツ装置を提供することをその主たる課題とする。 The present disclosure has as its main object to provide a more preferable terahertz device.
　本開示の第１の側面によると、テラヘルツ装置が提供される。前記テラヘルツ装置は、半導体基板と、テラヘルツ素子と、第１整流素子と、を含む。前記テラヘルツ素子は、前記半導体基板上に配置されている。前記第１整流素子は、前記テラヘルツ素子と電気的に並列接続されている。 According to a first aspect of the present disclosure, a terahertz device is provided. The terahertz device includes a semiconductor substrate, a terahertz element, and a first rectifying element. The terahertz element is disposed on the semiconductor substrate. The first rectifying element is electrically connected in parallel to the terahertz element.
　本開示のその他の特徴および利点は、添付図面を参照して以下に行う詳細な説明によって、より明らかとなろう。 Other features and advantages of the present disclosure will become more apparent from the detailed description given below with reference to the accompanying drawings.
第１実施形態のテラヘルツ装置の斜視図である。It is a perspective view of the terahertz device of a 1st embodiment. 第１実施形態の半導体部品の平面図である。It is a top view of the semiconductor component of a 1st embodiment. 図２から第１導電体層を省略した図である。It is the figure which abbreviate | omitted the 1st conductor layer from FIG. 図２の領域ＩＶの部分拡大図である。It is the elements on larger scale of the area | region IV of FIG. 第１実施形態のテラヘルツ素子の詳細を示す断面図である。It is sectional drawing which shows the detail of the terahertz element of 1st Embodiment. 図５の部分拡大図である。It is the elements on larger scale of FIG. 図２のＶＩＩ－ＶＩＩ線に沿う断面図である。FIG. 7 is a cross-sectional view taken along the line VII-VII of FIG. 2; 図２のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG. 図２のＩＸ－ＩＸ線に沿う断面図である。FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. 図２のＩＸ－ＩＸ線に沿う他の断面図である。FIG. 9 is another cross-sectional view along the line IX-IX in FIG. 2; 図２のＸＩ－ＸＩ線に沿う断面図である。FIG. 3 is a cross-sectional view taken along the line XI-XI in FIG. 図２のＸＩＩ－ＸＩＩ線に沿う断面図である。FIG. 3 is a cross-sectional view taken along the line XII-XII in FIG. 図２のＸＩＩ－ＸＩＩ線に沿う他の断面図である。FIG. 5 is another cross-sectional view along the line XII-XII in FIG. 2; 図２のＸＩＶ－ＸＩＶ線に沿う断面図である。It is sectional drawing in alignment with the XIV-XIV line of FIG. 第１実施形態のテラヘルツ素子、第１整流素子、第２整流素子の回路図である。It is a circuit diagram of the terahertz element of the first embodiment, a first rectifying element, and a second rectifying element. 第１実施形態の第１整流素子の断面図である。It is sectional drawing of the 1st rectifier of 1st Embodiment. 第１実施形態の第２整流素子の断面図である。It is sectional drawing of the 2nd rectifier of 1st Embodiment. 第１実施形態の第１整流素子の電流電圧特性の一例を示すグラフである。It is a graph which shows an example of the current voltage characteristic of the 1st rectifier of a 1st embodiment. 第１実施形態の第２整流素子の電流電圧特性の一例を示すグラフである。It is a graph which shows an example of the current voltage characteristic of the 2nd rectification element of a 1st embodiment. 第１実施形態のテラヘルツ素子の電流電圧特性の一例を示すグラフである。It is a graph which shows an example of the current-voltage characteristic of the terahertz element of 1st Embodiment. 第１実施形態の第１整流素子と第２整流素子とからなる合成素子の電流電圧特性の一例を示すグラフである。It is a graph which shows an example of the current-voltage characteristic of the synthetic | combination element which consists of a 1st rectification element of 1st Embodiment, and a 2nd rectification element. 図２の領域ＸＸＩＩの部分拡大図である。It is the elements on larger scale of area | region XXII of FIG. 図２２のＸＸＩＩＩ－ＸＸＩＩＩ線に沿う２つの断面図を含む、テラヘルツ素子、第１整流素子、第２整流素子の回路図である。FIG. 23 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element, including two cross-sectional views along the line XXIII-XXIII in FIG. 22. 第１実施形態のテラヘルツ装置の断面図である。FIG. 2 is a cross-sectional view of the terahertz device of the first embodiment. 第１実施形態の第１変形例の半導体部品の平面図である。It is a top view of the semiconductor component of the 1st modification of a 1st embodiment. 第１実施形態の第１変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the 1st modification of a 1st embodiment. 第１実施形態の第２変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the 2nd modification of a 1st embodiment. 第１実施形態の第３変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the 3rd modification of a 1st embodiment. 第１実施形態の他の変形例のテラヘルツ装置の断面図である。FIG. 7 is a cross-sectional view of a terahertz device of another modification of the first embodiment. 第２部分の平面視の形状の一例を示す図である。It is a figure which shows an example of the shape of planar view of a 2nd part. 第２部分の平面視の形状の一例を示す図である。It is a figure which shows an example of the shape of planar view of a 2nd part. 第２部分の平面視の形状の一例を示す図である。It is a figure which shows an example of the shape of planar view of a 2nd part. 第２部分の平面視の形状の一例を示す図である。It is a figure which shows an example of the shape of planar view of a 2nd part. 第２部分の平面視の形状の一例を示す図である。It is a figure which shows an example of the shape of planar view of a 2nd part. 図２９に示した第１部分を製造する際の一時点における構造の断面図である。FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29. 図２９に示した第１部分を製造する際の一時点における構造の断面図である。FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29. 図２９に示した第１部分を製造する際の一時点における構造の断面図である。FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29. 図２９に示した第１部分を製造する際の一時点における構造の断面図である。FIG. 30 is a cross-sectional view of the structure at one time in manufacturing the first portion shown in FIG. 29. 第１実施形態の変形例のテラヘルツ装置の斜視図である。It is a perspective view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の斜視図である。It is a perspective view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the modification of a 1st embodiment. 第１実施形態の変形例のテラヘルツ装置の平面図である。It is a top view of the terahertz device of the modification of a 1st embodiment.
　以下、本開示の実施の形態につき、図面を参照して具体的に説明する。 Hereinafter, embodiments of the present disclosure will be specifically described with reference to the drawings.
　「ある物Ａがある物Ｂに形成されている」および「ある物Ａがある物Ｂ上に形成されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接形成されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに形成されていること」を含む。同様に、「ある物Ａがある物Ｂに配置されている」および「ある物Ａがある物Ｂ上に配置されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接配置されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに配置されていること」を含む。同様に、「ある物Ａがある物Ｂ上に位置している」とは、特段の断りのない限り、「ある物Ａがある物Ｂに接していること」、および、「ある物Ａとある物Ｂとの間に他の物を介在していること」を含む。同様に、「ある物Ａがある物Ｂに積層されている」および「ある物Ａがある物Ｂ上に積層されている」とは、特段の断りのない限り、「ある物Ａがある物Ｂに直接積層されていること」、および、「ある物Ａとある物Ｂとの間に他の物を介在させつつ、ある物Ａがある物Ｂに積層されていること」を含む。 The terms "some A is formed on some B" and "the some A is formed on some B" are defined as "if some A has some A directly "Being formed" and "being formed in a certain thing B while being in the middle of a certain thing A while interposing another thing between a certain thing A and a certain thing B". Similarly, the terms "an item A is located on an item B" and "an item A is located on an item B" mean "an item A is located unless otherwise specified." It is included that it is disposed directly to B, and that "an object A is disposed to an object B while interposing another object between the object A and the object B". Similarly, "a certain thing A is located on a certain thing B" means "a certain thing A is in contact with a certain thing B", and "a certain thing A and "Intermediate thing with another thing B" is included. Similarly, the terms “some A is laminated to some B” and “some A is laminated onto some B” refer to “some A as being unless otherwise noted. And “being laminated to a certain thing B while being interposed with another thing between a certain thing A and a certain thing B”.
＜第１実施形態＞
　図１～図２４を用いて、本開示の第１実施形態について説明する。 First Embodiment
A first embodiment of the present disclosure will be described using FIGS. 1 to 24.
　図１は、第１実施形態のテラヘルツ装置の斜視図である。 FIG. 1 is a perspective view of the terahertz device of the first embodiment.
　同図に示すテラヘルツ装置Ａ１は、半導体部品Ｂ１と、支持体８と、樹脂部８５と、ワイヤ８７１、８７２と、を備える。 The terahertz device A1 shown in the figure includes a semiconductor component B1, a support 8, a resin portion 85, and wires 871 and 872.
　図２は、第１実施形態の半導体部品の平面図である。 FIG. 2 is a plan view of the semiconductor component of the first embodiment.
　同図に示す半導体部品Ｂ１は、テラヘルツ帯の周波数の高周波電磁波を発振する。半導体部品Ｂ１はテラヘルツ帯の高周波電磁波を発振するものではなく、受信するものであってもよい。半導体部品Ｂ１はテラヘルツ帯の高周波電磁波を発振および受信するものであってもよい。半導体部品Ｂ１は、半導体基板１と、第１導電体層２と、第２導電体層３と、絶縁層４（図５等参照）と、テラヘルツ素子５と、第１整流素子６１と、第２整流素子６２と、を備える。 The semiconductor component B1 shown in the figure oscillates a high frequency electromagnetic wave of a frequency in the terahertz band. The semiconductor component B1 does not oscillate, but may receive, high frequency electromagnetic waves in the terahertz band. The semiconductor component B1 may be one that oscillates and receives high frequency electromagnetic waves in the terahertz band. The semiconductor component B1 includes the semiconductor substrate 1, the first conductive layer 2, the second conductive layer 3, the insulating layer 4 (see FIG. 5 and the like), the terahertz element 5, the first rectifying element 61, the first And a second rectifying element 62.
　半導体基板１は、半導体よりなり、半絶縁性を有する。半導体基板１を構成する半導体は、たとえば、ＩｎＰであるが、ＩｎＰ以外の半導体であってもよい。半導体基板１は、表面１１を有する。表面１１は半導体基板１の厚さ方向Ｚ１（図５等参照）を向いている。 The semiconductor substrate 1 is made of a semiconductor and has a semi-insulating property. The semiconductor constituting the semiconductor substrate 1 is, for example, InP, but may be a semiconductor other than InP. The semiconductor substrate 1 has a surface 11. The surface 11 faces in the thickness direction Z1 (see FIG. 5 etc.) of the semiconductor substrate 1.
　図２に示すように、半導体基板１は、縁１３１～１３４を含む。縁１３１および縁１３３は互いに第１方向Ｘ１に離間している。縁１３１および縁１３３はいずれも、第２方向Ｘ２に沿って延びている。第２方向Ｘ２は、第１方向Ｘ１に直交している。縁１３２および縁１３４は互いに第２方向Ｘ２に離間している。縁１３２および縁１３４はいずれも、第１方向Ｘ１に沿って延びている。縁１３１は縁１３２につながり、縁１３２は縁１３３につながり、縁１３３は縁１３４につながり、縁１３４は縁１３１につながっている。 As shown in FIG. 2, the semiconductor substrate 1 includes edges 131-134. The edge 131 and the edge 133 are spaced apart from each other in the first direction X1. The edge 131 and the edge 133 both extend along the second direction X2. The second direction X2 is orthogonal to the first direction X1. The edge 132 and the edge 134 are spaced apart from each other in the second direction X2. Both the edge 132 and the edge 134 extend along the first direction X1. Edge 131 is connected to edge 132, edge 132 is connected to edge 133, edge 133 is connected to edge 134, and edge 134 is connected to edge 131.
　図４は、図２の領域ＩＶの部分拡大図である。図５は、第１実施形態のテラヘルツ素子の詳細を示す断面図である。 FIG. 4 is a partially enlarged view of region IV of FIG. FIG. 5 is a cross-sectional view showing the details of the terahertz element of the first embodiment.
　図２、図４、図５に示すテラヘルツ素子５は、半導体基板１に形成されている。テラヘルツ素子５は、第１導電体層２および第２導電体層３に導通している。テラヘルツ素子５は、テラヘルツ素子５から放射された電磁波は、裏面反射体金属層８８に反射されて、半導体基板１に対して垂直方向（厚さ方向Ｚ１）の面発光放射パターンを有する。 The terahertz element 5 shown in FIGS. 2, 4 and 5 is formed on a semiconductor substrate 1. The terahertz element 5 is electrically connected to the first conductor layer 2 and the second conductor layer 3. The electromagnetic wave emitted from the terahertz element 5 is reflected by the back reflector metal layer 88, and the terahertz element 5 has a surface emission radiation pattern in a direction (thickness direction Z1) perpendicular to the semiconductor substrate 1.
　テラヘルツ素子５は典型的にはＲＴＤである。テラヘルツ素子５は、ＲＴＤ以外のダイオードや、トランジスタによって構成されていてもよい。テラヘルツ素子５としては、例えば、タンネット（ＴＵＮＮＥＴＴ：Ｔｕｎｎｅｌ　Ｔｒａｎｓｉｔ　Ｔｉｍｅ）ダイオード、インパット（ＩＭＰＡＴＴ：Ｉｍｐａｃｔ　Ｉｏｎｉｚａｔｉｏｎ　Ａｖａｌａｎｃｈｅ　Ｔｒａｎｓｉｔ　Ｔｉｍｅ）ダイオード、ＧａＡｓ系電界効果トランジスタ（ＦＥＴ：Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）、ＧａＮ系ＦＥＴ、高電子移動度トランジスタ（ＨＥＭＴ：Ｈｉｇｈ　Ｅｌｅｃｔｒｏｎ　Ｍｏｂｉｌｉｔｙ　Ｔｒａｎｓｉｓｔｏｒ）、あるいは、ヘテロ接合バイポーラトランジスタ（ＨＢＴ：Ｈｅｔｅｒｏｊｕｎｃｔｉｏｎ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）により構成されうる。 The terahertz element 5 is typically an RTD. The terahertz element 5 may be configured by a diode other than the RTD or a transistor. As the terahertz element 5, for example, a Tannet (Tunnet T: Tunnel Transit Time) diode, an IMP ATT (Impact Ionization Avalanche Transit Time) diode, a GaAs based field effect transistor (FET: Field Effect Transistor), a GaN based FET, a high electron A mobility transistor (HEMT: High Electron Mobility Transistor) or a heterojunction bipolar transistor (HBT) can be comprised.
　テラヘルツ素子５を実現するための一例を、図６を用いて説明する。図６は、図５の部分拡大図である。ＧａＩｎＡｓ層９２ａが、半導体層９１ａ（たとえばＧａＩｎＡｓよりなる）に配置され、ｎ型不純物がドープされている。ＧａＩｎＡｓ層９３ａは、ＧａＩｎＡｓ層９２ａに配置され、不純物がドープされていない。ＡｌＡｓ層９４ａがＧａＩｎＡｓ層９３ａに配置され、ＩｎＧａＡｓ層９５が、ＡｌＡｓ層９４ａに配置され、ＡｌＡｓ層９４ｂがＩｎＧａＡｓ層９５上に位置している。ＡｌＡｓ層９４ａとＩｎＧａＡｓ層９５とＡｌＡｓ層９４ｂはＲＴＤ部を構成する。ＧａＩｎＡｓ層９３ｂは、ＡｌＡｓ層９４ｂに配置され、不純物がドープされていない。ＧａＩｎＡｓ層９２ｂは、ＧａＩｎＡｓ層９３ｂに配置され、ｎ型不純物がドープされている。ＧａＩｎＡｓ層９１ｂがＧａＩｎＡｓ層９２ｂに配置され、ｎ型不純物が高濃度にドープされている。そして、第１導電体層２がＧａＩｎＡｓ層９１ｂ上に位置している。 An example for realizing the terahertz element 5 will be described with reference to FIG. FIG. 6 is a partial enlarged view of FIG. The GaInAs layer 92a is disposed in the semiconductor layer 91a (made of, for example, GaInAs) and is doped with an n-type impurity. The GaInAs layer 93a is disposed on the GaInAs layer 92a and is not doped with impurities. An AlAs layer 94 a is disposed on the GaInAs layer 93 a, an InGaAs layer 95 is disposed on the AlAs layer 94 a, and an AlAs layer 94 b is located on the InGaAs layer 95. The AlAs layer 94a, the InGaAs layer 95, and the AlAs layer 94b constitute an RTD portion. The GaInAs layer 93b is disposed on the AlAs layer 94b and is not doped with impurities. The GaInAs layer 92b is disposed on the GaInAs layer 93b and is doped with an n-type impurity. A GaInAs layer 91b is disposed on the GaInAs layer 92b and is heavily doped with n-type impurities. Then, the first conductor layer 2 is located on the GaInAs layer 91 b.
　図示は省略するが、図６とは異なり、ｎ型不純物を高濃度にドープされたＧａＩｎＡｓ層が、ＧａＩｎＡｓ層９１ｂおよび第１導電体層２の間に介在していてもよい。これにより、第１導電体層２とＧａＩｎＡｓ層９１ｂとのコンタクトが良好になりうる。 Although not shown, a GaInAs layer heavily doped with an n-type impurity may be interposed between the GaInAs layer 91 b and the first conductor layer 2, unlike FIG. 6. Thereby, the contact between the first conductor layer 2 and the GaInAs layer 91 b can be improved.
　図２０に示すように、テラヘルツ素子５の電流電圧特性を示すグラフにおいて、傾きが負の値となる領域Ｒ１１が存在する。領域Ｒ１１がテラヘルツ波を発振する領域である。 As shown in FIG. 20, in the graph showing the current-voltage characteristics of the terahertz element 5, there is a region R11 where the slope has a negative value. The region R11 is a region for oscillating the terahertz wave.
　図７は、図２のＶＩＩ－ＶＩＩ線に沿う断面図である。図８は、図２のＶＩＩＩ－ＶＩＩＩ線に沿う断面図である。図９は、図２のＩＸ－ＩＸ線に沿う断面図である。図１０は、図２のＩＸ－ＩＸ線に沿う他の断面図である。図１１は、図２のＸＩ－ＸＩ線に沿う断面図である。図１２は、図２のＸＩＩ－ＸＩＩ線に沿う断面図である。図１３は、図２のＸＩＩ－ＸＩＩ線に沿う他の断面図である。図１４は、図２のＸＩＶ－ＸＩＶ線に沿う断面図である。 7 is a cross-sectional view taken along the line VII-VII in FIG. FIG. 8 is a cross-sectional view taken along the line VIII-VIII in FIG. FIG. 9 is a cross-sectional view taken along the line IX-IX in FIG. FIG. 10 is another cross-sectional view along the line IX-IX in FIG. FIG. 11 is a cross-sectional view taken along the line XI-XI of FIG. 12 is a cross-sectional view taken along the line XII-XII of FIG. FIG. 13 is another cross-sectional view along the line XII-XII in FIG. FIG. 14 is a cross-sectional view taken along line XIV-XIV of FIG.
　図８に示す絶縁層４は、半導体基板１上に形成されている。絶縁層４は、たとえば、ＳｉＯ2よりなる。あるいは、絶縁層４を構成する材料は、Ｓｉ3Ｎ4、ＳｉＯＮ、ＨｆＯ2、あるいはＡｌ2Ｏ3であってもよい。絶縁層４の厚さは、たとえば、１０ｎｍ～１０００ｎｍである。絶縁層４は、たとえば、ＣＶＤ法、あるいはスパッタリング法によって形成されうる。 The insulating layer 4 shown in FIG. 8 is formed on the semiconductor substrate 1. The insulating layer 4 is made of, for example, SiO 2 . Alternatively, the material forming the insulating layer 4 may be Si 3 N 4 , SiON, HfO 2 , or Al 2 O 3 . The thickness of the insulating layer 4 is, for example, 10 nm to 1000 nm. The insulating layer 4 can be formed by, for example, a CVD method or a sputtering method.
　図２等に示すように、第１導電体層２および第２導電体層３は各々、半導体基板１上に各々形成されている。第１導電体層２および第２導電体層３は互いに絶縁されている。半導体基板１の厚さ方向Ｚ１視において、半導体基板１の厚さ方向Ｚ１に直交する第１方向Ｘ１に第２導電体層３からテラヘルツ素子５が離間している。第１導電体層２および第２導電体層３は各々、金属の積層構造を有する。第１導電体層２および第２導電体層３の各々の積層構造は、たとえば、Ａｕ、Ｐｄ、およびＴｉが積層された構造である。あるいは、第１導電体層２および第２導電体層３の各々の積層構造は、たとえば、ＡｕおよびＴｉが積層された構造である。第１導電体層２および第２導電体層３の各々の厚さは、例えば、１０～２０００ｎｍである。第１導電体層２および第２導電体層３は各々、いずれも真空蒸着法、あるいはスパッタリング法などによって形成されうる。 As shown in FIG. 2 and the like, the first conductive layer 2 and the second conductive layer 3 are respectively formed on the semiconductor substrate 1. The first conductor layer 2 and the second conductor layer 3 are insulated from each other. In the thickness direction Z1 of the semiconductor substrate 1, the terahertz element 5 is separated from the second conductor layer 3 in the first direction X1 orthogonal to the thickness direction Z1 of the semiconductor substrate 1. The first conductor layer 2 and the second conductor layer 3 each have a laminated structure of metal. The laminated structure of each of the first conductor layer 2 and the second conductor layer 3 is, for example, a structure in which Au, Pd, and Ti are laminated. Alternatively, the laminated structure of each of the first conductor layer 2 and the second conductor layer 3 is, for example, a structure in which Au and Ti are laminated. The thickness of each of the first conductor layer 2 and the second conductor layer 3 is, for example, 10 to 2000 nm. Each of the first conductor layer 2 and the second conductor layer 3 can be formed by vacuum evaporation, sputtering, or the like.
　第１導電体層２は、第１部位２１と、第１インダクタンス部２２と、第１キャパシタ部２３と、第１電極２５と、を含む。第２導電体層３は、第２部位３１と、第２インダクタンス部３２と、第２キャパシタ部３３と、第２電極３５と、を含む。 The first conductive layer 2 includes a first portion 21, a first inductance portion 22, a first capacitor portion 23, and a first electrode 25. The second conductor layer 3 includes a second portion 31, a second inductance portion 32, a second capacitor portion 33, and a second electrode 35.
　図２、図４、図５に示すように、第１部位２１は、第１方向Ｘ１に沿って延びる。第１部位２１は、第１導電部２１４と、第２導電部２１５と、を含む。 As shown in FIG. 2, FIG. 4 and FIG. 5, the first portion 21 extends along the first direction X1. The first portion 21 includes a first conductive portion 214 and a second conductive portion 215.
　図２、図４においては、第１導電部２１４は長矩形状の部位である。第１導電部２１４は、第１方向Ｘ１に沿って延び、アンテナとして機能しうる。第２導電部２１５は、厚さ方向Ｚ１視において、第１導電部２１４から第２導電体層３に向かって延び出ている。第２導電部２１５は、厚さ方向Ｚ１視において、テラヘルツ素子５に重なっている。 In FIG. 2 and FIG. 4, the first conductive portion 214 is a long rectangular portion. The first conductive portion 214 may extend along the first direction X1 and function as an antenna. The second conductive portion 215 extends from the first conductive portion 214 toward the second conductive layer 3 in the thickness direction Z1. The second conductive portion 215 overlaps the terahertz element 5 in the thickness direction Z1.
　図２、図４等に示す第１インダクタンス部２２は、第１部位２１および第１キャパシタ部２３につながり且つ第１部位２１から第１キャパシタ部２３まで第２方向Ｘ２に沿って延びている。第１インダクタンス部２２は、インダクタンスとして機能する。第１インダクタンス部２２の第２方向Ｘ２の長さＬ１（図４参照）は、たとえば、５μｍ～１００μｍである。第１インダクタンス部２２の幅は、たとえば、１μｍ～１０μｍである。 The first inductance portion 22 shown in FIGS. 2 and 4 is connected to the first portion 21 and the first capacitor portion 23 and extends from the first portion 21 to the first capacitor portion 23 along the second direction X2. The first inductance unit 22 functions as an inductance. The length L1 (see FIG. 4) in the second direction X2 of the first inductance portion 22 is, for example, 5 μm to 100 μm. The width of the first inductance portion 22 is, for example, 1 μm to 10 μm.
　第２部位３１は、第３方向Ｘ３に沿って延びる。第３方向Ｘ３は第１方向Ｘ１とは反対の方向である。第２部位３１は、アンテナとして機能しうる。第２インダクタンス部３２は、第２部位３１および第２キャパシタ部３３につながり且つ第２部位３１から第２キャパシタ部３３まで第２方向Ｘ２に沿って延びている。第２インダクタンス部３２は、インダクタンスとして機能する。第２インダクタンス部３２の第２方向Ｘ２の長さＬ２（図４参照）は、たとえば、５μｍ～１００μｍである。第２インダクタンス部３２の幅は、たとえば、１μｍ～１０μｍである。 The second portion 31 extends along the third direction X3. The third direction X3 is the direction opposite to the first direction X1. The second portion 31 can function as an antenna. The second inductance portion 32 is connected to the second portion 31 and the second capacitor portion 33, and extends from the second portion 31 to the second capacitor portion 33 along the second direction X2. The second inductance unit 32 functions as an inductance. The length L2 (see FIG. 4) in the second direction X2 of the second inductance portion 32 is, for example, 5 μm to 100 μm. The width of the second inductance portion 32 is, for example, 1 μm to 10 μm.
　図２、図４等に示すように、第１キャパシタ部２３は、テラヘルツ素子５に対し第２方向Ｘ２側に位置する。本実施形態では、第１キャパシタ部２３は厚さ方向Ｚ１視において矩形状である。 As shown in FIG. 2, FIG. 4, etc., the first capacitor portion 23 is located on the side of the terahertz element 5 in the second direction X2. In the present embodiment, the first capacitor portion 23 is rectangular in the thickness direction Z1.
　図３は、図２から第１導電体層２を省略した図である。 FIG. 3 is a view in which the first conductive layer 2 is omitted from FIG.
　第２キャパシタ部３３は、テラヘルツ素子５に対し第２方向Ｘ２側に位置する。図１２、図１３に示すように、第２キャパシタ部３３と半導体基板１との間に、第１キャパシタ部２３が介在している。本実施形態とは異なり、第１キャパシタ部２３と半導体基板１との間に第２キャパシタ部３３が介在していてもよい。第２キャパシタ部３３は、第１キャパシタ部２３に積層され、且つ、絶縁層４を介して第１キャパシタ部２３から絶縁されている。第２キャパシタ部３３と第１キャパシタ部２３とが、キャパシタを構成する。本実施形態では、第２キャパシタ部３３は厚さ方向Ｚ１視において矩形状である。 The second capacitor unit 33 is located on the side of the terahertz element 5 in the second direction X2. As shown in FIGS. 12 and 13, the first capacitor portion 23 is interposed between the second capacitor portion 33 and the semiconductor substrate 1. Unlike the present embodiment, the second capacitor unit 33 may be interposed between the first capacitor unit 23 and the semiconductor substrate 1. The second capacitor portion 33 is stacked on the first capacitor portion 23 and is insulated from the first capacitor portion 23 via the insulating layer 4. The second capacitor unit 33 and the first capacitor unit 23 constitute a capacitor. In the present embodiment, the second capacitor portion 33 is rectangular in the thickness direction Z1.
　第１電極２５は、第１キャパシタ部２３につながっている。本実施形態では、第１電極２５は矩形状である。本実施形態では、第１電極２５は、ワイヤ８７１（図１１参照）がボンディングされるパッド部である。図１１に示すように、第１電極２５は、半導体基板１に直接接する部位を有する。当該接する部位は、厚さ方向Ｚ１視において、ワイヤ８７１と第１電極２５とが接するワイヤボンディング部に重なっている。 The first electrode 25 is connected to the first capacitor unit 23. In the present embodiment, the first electrode 25 is rectangular. In the present embodiment, the first electrode 25 is a pad portion to which the wire 871 (see FIG. 11) is bonded. As shown in FIG. 11, the first electrode 25 has a portion in direct contact with the semiconductor substrate 1. The contact portion overlaps the wire bonding portion in which the wire 871 and the first electrode 25 are in contact in the thickness direction Z1.
　本実施形態では、図２に示すように、厚さ方向Ｚ１視において、第１電極２５は、縁２５１～２５４を含む。縁２５１および縁２５３はいずれも、第２方向Ｘ２に沿って延びている。縁２５２および縁２５４は互いに第２方向Ｘ２に離間している。縁２５２および縁２５４はいずれも、第１方向Ｘ１に沿って延びている。縁２５１は縁２５２につながり、縁２５２は縁２５３につながり、縁２５３は縁２５４から離間し、縁２５４は縁２５１につながっている。縁２５１および縁２５２は、厚さ方向Ｚ１視において、縁１３１および縁１３２にそれぞれ至っている。本実施形態とは異なり、縁２５１および縁２５２が、厚さ方向Ｚ１視において、縁１３１および縁１３２にそれぞれ至っていなくてもよい。 In the present embodiment, as shown in FIG. 2, in the thickness direction Z1, the first electrode 25 includes edges 251 to 254. The edge 251 and the edge 253 both extend along the second direction X2. The edge 252 and the edge 254 are spaced apart from each other in the second direction X2. The edge 252 and the edge 254 both extend along the first direction X1. Edge 251 connects to edge 252, which connects to edge 253, which is spaced apart from edge 254, which connects to edge 251. The edge 251 and the edge 252 respectively extend to the edge 131 and the edge 132 in the thickness direction Z1. Unlike the present embodiment, the edge 251 and the edge 252 may not extend to the edge 131 and the edge 132 in the thickness direction Z1, respectively.
　第２電極３５は、第２キャパシタ部３３につながっている。本実施形態では、第２電極３５は矩形状である。本実施形態では、第２電極３５は、ワイヤ８７２（図１４参照）がボンディングされるパッド部である。図１２に示すように、第２電極３５は、半導体基板１に直接接する部位を有する。当該接する部位は、厚さ方向Ｚ１視において、ワイヤ８７２と第２電極３５とが接するワイヤボンディング部に重なっている。 The second electrode 35 is connected to the second capacitor unit 33. In the present embodiment, the second electrode 35 is rectangular. In the present embodiment, the second electrode 35 is a pad portion to which the wire 872 (see FIG. 14) is bonded. As shown in FIG. 12, the second electrode 35 has a portion in direct contact with the semiconductor substrate 1. The contact portion overlaps the wire bonding portion in which the wire 872 and the second electrode 35 are in contact in the thickness direction Z1.
　本実施形態では、図２に示すように、厚さ方向Ｚ１視において、第２電極３５は、縁１３３および縁１３２に至っている。本実施形態とは異なり、厚さ方向Ｚ１視において、第２電極３５は、縁１３３および縁１３２に至っていなくてもよい。この場合、半導体部品Ｂ１の製造工程において、半導体基板１をダイシングする際に、第２電極３５を切断することによって生じうるバリの発生を抑制できる。 In the present embodiment, as shown in FIG. 2, the second electrode 35 extends to the edge 133 and the edge 132 in the thickness direction Z1. Unlike the present embodiment, the second electrode 35 may not reach the edge 133 and the edge 132 in the thickness direction Z1. In this case, when dicing the semiconductor substrate 1 in the manufacturing process of the semiconductor component B1, it is possible to suppress the generation of burrs that may be generated by cutting the second electrode 35.
　本実施形態では、図２に示すように、厚さ方向Ｚ１視において、第２電極３５は、縁３５１～３５４を含む。縁３５１および縁３５３はいずれも、第２方向Ｘ２に沿って延びている。縁３５２および縁３５４は互いに第２方向Ｘ２に離間している。縁３５２および縁３５４はいずれも、第１方向Ｘ１に沿って延びている。縁３５１は縁３５２につながり、縁３５２は縁３５３につながり、縁３５３は縁３５４につながり、縁３５４は縁３５１から離間している。縁３５２および縁３５３は、厚さ方向Ｚ１視において、縁１３２および縁１３３にそれぞれ至っている。本実施形態とは異なり、縁３５２および縁３５３が、厚さ方向Ｚ１視において、縁１３２および縁１３３にそれぞれ至っていなくてもよい。 In the present embodiment, as shown in FIG. 2, the second electrode 35 includes edges 351 to 354 in the thickness direction Z1. The edge 351 and the edge 353 both extend along the second direction X2. The edge 352 and the edge 354 are spaced apart from each other in the second direction X2. Both the edge 352 and the edge 354 extend along the first direction X1. Edge 351 connects to edge 352, edge 352 connects to edge 353, edge 353 connects to edge 354 and edge 354 is spaced from edge 351. The edge 352 and the edge 353 respectively extend to the edge 132 and the edge 133 in the thickness direction Z1. Unlike the present embodiment, the edge 352 and the edge 353 may not extend to the edge 132 and the edge 133, respectively, in the thickness direction Z1.
　図１５は、第１実施形態のテラヘルツ素子、第１整流素子、第２整流素子の回路図である。図１５に示すように、第１整流素子６１は、テラヘルツ素子５と電気的に並列接続されている。第１整流素子６１は、たとえばダイオードである。このようなダイオードの具体例は、ツェナーダイオード、ショットキーダイオード、および発光ダイオードを含む。第１整流素子６１は、第１端子６１Ａおよび第２端子６１Ｂを含む。第１整流素子６１において、第１端子６１Ａから第２端子６１Ｂに向かう電気的な方向が順方向である。通常の使用では、第１整流素子６１において、第１端子６１Ａから第２端子６１Ｂに向かって電流が流れやすく、第２端子６１Ｂから第１端子６１Ａに向かって電流は流れにくい。 FIG. 15 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element of the first embodiment. As shown in FIG. 15, the first rectifying element 61 is electrically connected in parallel to the terahertz element 5. The first rectifying element 61 is, for example, a diode. Examples of such diodes include zener diodes, Schottky diodes, and light emitting diodes. The first rectifying element 61 includes a first terminal 61A and a second terminal 61B. In the first rectifying element 61, the electrical direction from the first terminal 61A to the second terminal 61B is the forward direction. In normal use, in the first rectifying element 61, current easily flows from the first terminal 61A to the second terminal 61B, and current hardly flows from the second terminal 61B to the first terminal 61A.
　図１６は、第１実施形態の第１整流素子の一例の断面図である。図１６に示すように、第１整流素子６１は、第１半導体層６１１および第２半導体層６１２を含む。第１半導体層６１１および第２半導体層６１２は互いに積層されている。第１半導体層６１１は第１の導電型を有し、第２半導体層６１２は第１の導電型とは反対の第２の導電型を有する。第１の導電型がｐ型であるとき第２の導電型はｎ型である。第２の導電型がｎ型であるとき第１の導電型はｐ型である。 FIG. 16 is a cross-sectional view of an example of the first rectifying element of the first embodiment. As shown in FIG. 16, the first rectifying element 61 includes a first semiconductor layer 611 and a second semiconductor layer 612. The first semiconductor layer 611 and the second semiconductor layer 612 are stacked on each other. The first semiconductor layer 611 has a first conductivity type, and the second semiconductor layer 612 has a second conductivity type opposite to the first conductivity type. When the first conductivity type is p-type, the second conductivity type is n-type. When the second conductivity type is n-type, the first conductivity type is p-type.
　図１８は、第１整流素子６１の電流電圧特性を示す。同図では、第１端子６１Ａから第２端子６１Ｂに電流が流れる方向を正方向としている。同図に示すように、第１整流素子６１の第１立ち上がり電圧値Ｖ６１１の絶対値は、第１整流素子６１の第１降伏電圧値Ｖ６１２の絶対値よりも小さい。第１立ち上がり電圧値Ｖ６１１は、テラヘルツ素子５がテラヘルツ波を発振する電圧領域Ｒ１１における値の絶対値の下限（電圧値Ｖ１１の絶対値であり、図２０参照）よりも大きくてもよい。第１立ち上がり電圧値Ｖ６１１は、テラヘルツ素子５がテラヘルツ波を発振する電圧領域Ｒ１１における値の絶対値の上限（電圧値Ｖ１２の絶対値であり、図２０参照）よりも大きくてもよい。電圧値Ｖ１１の絶対値は、たとえば、０．３～０．５Ｖであり、電圧値Ｖ１２の絶対値は、たとえば、０．５～０．７Ｖである。第１立ち上がり電圧値Ｖ６１１の絶対値は、たとえば、０．４～０．９Ｖである。第１降伏電圧値Ｖ６１２の絶対値は、たとえば、２～８Ｖである。 FIG. 18 shows the current-voltage characteristics of the first rectifying element 61. In the figure, the direction in which current flows from the first terminal 61A to the second terminal 61B is positive. As shown in the figure, the absolute value of the first rising voltage value V611 of the first rectifying element 61 is smaller than the absolute value of the first breakdown voltage value V612 of the first rectifying element 61. The first rising voltage value V611 may be larger than the lower limit (the absolute value of the voltage value V11, see FIG. 20) of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave. The first rising voltage value V611 may be larger than the upper limit (the absolute value of the voltage value V12, see FIG. 20) of the absolute value of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave. The absolute value of voltage value V11 is, for example, 0.3 to 0.5 V, and the absolute value of voltage value V12 is, for example, 0.5 to 0.7 V. The absolute value of the first rising voltage value V611 is, for example, 0.4 to 0.9 V. The absolute value of the first breakdown voltage value V612 is, for example, 2 to 8V.
　図１５に示すように、第２整流素子６２は、テラヘルツ素子５と電気的に並列接続されている。第２整流素子６２は、たとえばダイオードである。このようなダイオードの具体例は、ツェナーダイオード、ショットキーダイオード、および発光ダイオードを含む。第２整流素子６２は、第１端子６２Ａおよび第２端子６２Ｂを含む。第２整流素子６２において、第１端子６２Ａから第２端子６２Ｂに向かう電気的な方向が順方向である。通常の使用では、第２整流素子６２において、第１端子６２Ａから第２端子６２Ｂに向かって電流が流れやすく、第２端子６２Ｂから第１端子６２Ａに向かって電流は流れにくい。 As shown in FIG. 15, the second rectifying element 62 is electrically connected in parallel to the terahertz element 5. The second rectifying element 62 is, for example, a diode. Examples of such diodes include zener diodes, Schottky diodes, and light emitting diodes. The second rectifying element 62 includes a first terminal 62A and a second terminal 62B. In the second rectifying element 62, the electrical direction from the first terminal 62A to the second terminal 62B is the forward direction. In normal use, in the second rectifying element 62, current easily flows from the first terminal 62A to the second terminal 62B, and current hardly flows from the second terminal 62B to the first terminal 62A.
　図１７は、第１実施形態の第２整流素子の一例の断面図である。図１７に示すように、第２整流素子６２は、第１半導体層６２１および第２半導体層６２２を含む。第２半導体層６２１および第２半導体層６２２は互いに積層されている。第１半導体層６２１は第１の導電型を有し、第２半導体層６２２は第１の導電型とは反対の第２の導電型を有する。第１の導電型がｐ型であるとき第２の導電型はｎ型である。第２の導電型がｎ型であるとき第１の導電型はｐ型である。 FIG. 17 is a cross-sectional view of an example of the second rectifying element of the first embodiment. As shown in FIG. 17, the second rectifying element 62 includes a first semiconductor layer 621 and a second semiconductor layer 622. The second semiconductor layer 621 and the second semiconductor layer 622 are stacked on each other. The first semiconductor layer 621 has a first conductivity type, and the second semiconductor layer 622 has a second conductivity type opposite to the first conductivity type. When the first conductivity type is p-type, the second conductivity type is n-type. When the second conductivity type is n-type, the first conductivity type is p-type.
　図１８は、第２整流素子６２の電流電圧特性を示す。同図では、第１端子６２Ａから第２端子６２Ｂに電流が流れる方向を正方向としている。同図に示すように、第２整流素子６２の第２立ち上がり電圧値Ｖ６２１の絶対値は、第２整流素子６２の第２降伏電圧値Ｖ６２２の絶対値よりも小さい。第２立ち上がり電圧値Ｖ６２１は、テラヘルツ素子５がテラヘルツ波を発振する電圧領域Ｒ１１における値の絶対値の下限（電圧値Ｖ１１の絶対値であり、図２０参照）よりも大きくてもよい。第２立ち上がり電圧値Ｖ６２１は、テラヘルツ素子５がテラヘルツ波を発振する電圧領域Ｒ１１における値の絶対値の上限（電圧値Ｖ１２の絶対値であり、図２０参照）よりも大きくてもよい。第２立ち上がり電圧値Ｖ６２１の絶対値は、たとえば、０．４～０．９Ｖである。第２降伏電圧値Ｖ６２２の絶対値は、たとえば、２～８Ｖである。 FIG. 18 shows the current-voltage characteristics of the second rectifying element 62. In the figure, the direction in which current flows from the first terminal 62A to the second terminal 62B is positive. As shown in the figure, the absolute value of the second rising voltage value V621 of the second rectifying element 62 is smaller than the absolute value of the second breakdown voltage value V622 of the second rectifying element 62. The second rising voltage value V621 may be larger than the lower limit (the absolute value of the voltage value V11, see FIG. 20) of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave. The second rising voltage value V621 may be larger than the upper limit (the absolute value of the voltage value V12, see FIG. 20) of the absolute value of the value in the voltage region R11 in which the terahertz element 5 oscillates the terahertz wave. The absolute value of the second rising voltage value V621 is, for example, 0.4 to 0.9 V. The absolute value of the second breakdown voltage value V622 is, for example, 2 to 8V.
　図１５に示すように、第１整流素子６１の第１端子６１Ａは、第２整流素子６２の第２端子６２Ｂに導通している。第１整流素子６１の第２端子６１Ｂは、第２整流素子６２の第１端子６２Ａに導通している。したがって、第１整流素子６１および第２整流素子６２からなる合成素子の電流電圧特性は、図２１に示すようになる。図２１に示すように、第１端子６１Ａから第２端子６１Ｂに電流が向かう方向を正方向とした場合、第１立ち上がり電圧値Ｖ６１１において、電流電圧曲線が急激に立ち上り、また、第２立ち上がり電圧値Ｖ６２１の絶対値の負の値において、電流電圧曲線は急激に降下する。 As shown in FIG. 15, the first terminal 61 </ b> A of the first rectifier element 61 is electrically connected to the second terminal 62 </ b> B of the second rectifier element 62. The second terminal 61 B of the first rectifying element 61 is electrically connected to the first terminal 62 A of the second rectifying element 62. Therefore, the current-voltage characteristics of the combined element including the first and second rectifying elements 61 and 62 are as shown in FIG. As shown in FIG. 21, when the direction from the first terminal 61A to the second terminal 61B is a positive direction, the current-voltage curve rises sharply at the first rising voltage value V611, and the second rising voltage At negative values of the absolute value of the value V 621, the current-voltage curve drops sharply.
　第１整流素子６１および第２整流素子６２の具体例構造の一例について説明する。図２２は、図２の領域ＸＸＩＩの部分拡大図である。図２３は、図２２のＸＸＩＩＩ－ＸＸＩＩＩ線に沿う２つの断面図を含む、テラヘルツ素子、第１整流素子、第２整流素子の回路図である。 An example of the specific example structure of the 1st rectification element 61 and the 2nd rectification element 62 is explained. FIG. 22 is a partially enlarged view of a region XXII of FIG. FIG. 23 is a circuit diagram of the terahertz element, the first rectifying element, and the second rectifying element, including two cross-sectional views along line XXIII-XXIII in FIG.
　図２、図２２、図２３に示す例においては、第１整流素子６１および第２整流素子６２はいずれも、半導体基板１上に形成されている。第１整流素子６１および第２整流素子６２は各々、第１導電体層２（図２２、図２３に示す例では第１電極２５）および第２導電体層３（図２２、図２３に示す例では第２電極３５）の間に電気的に介在している。図２３に示すように、半導体基板１上には、半導体層７１（第１半導体層）および半導体層７２（第２半導体層）が形成されている。半導体層７１および半導体層７２は互いに積層されている。半導体層７１は第１導電型を有し、半導体層７２は第１導電型とは反対の第２導電型を有する。半導体層７１は、たとえば、第１整流素子６１の第１半導体層６１１、および、第２整流素子６２の第１半導体層６２１を構成しうる。半導体層７２は、第１整流素子６１の第２半導体層６１２、および、第２整流素子６２の第２半導体層６２２を構成しうる。 In the example shown in FIG. 2, FIG. 22 and FIG. 23, each of the first rectifier element 61 and the second rectifier element 62 is formed on the semiconductor substrate 1. The first rectifying element 61 and the second rectifying element 62 respectively show the first conductive layer 2 (the first electrode 25 in the example shown in FIGS. 22 and 23) and the second conductive layer 3 (the FIGS. 22 and 23). In the example, it is electrically interposed between the second electrodes 35). As shown in FIG. 23, on the semiconductor substrate 1, a semiconductor layer 71 (first semiconductor layer) and a semiconductor layer 72 (second semiconductor layer) are formed. The semiconductor layer 71 and the semiconductor layer 72 are stacked on each other. The semiconductor layer 71 has a first conductivity type, and the semiconductor layer 72 has a second conductivity type opposite to the first conductivity type. The semiconductor layer 71 can constitute, for example, the first semiconductor layer 611 of the first rectifying element 61 and the first semiconductor layer 621 of the second rectifying element 62. The semiconductor layer 72 can constitute the second semiconductor layer 612 of the first rectifying element 61 and the second semiconductor layer 622 of the second rectifying element 62.
　図２３に示すように、第１導電体層２（より具体的には第１電極２５）は、部位２５６、２５７を有し、第２導電体層３（より具体的には第２電極３５）は部位３５６、３５７を有する。部位２５６、３５７は、半導体層７１に接しており、部位２５７、３５６は、半導体層７２に接している。そして、同図に示す例においては、部位２５６が、第１整流素子６１の第１端子６１Ａを構成し、第２電極３５６が第１整流素子６１の第２端子６１Ｂを構成しうる。同図に示す例においては、部位２５７が第２整流素子６２の第２端子６２Ｂを構成し、部位３５７が第２整流素子６２の第１端子６２Ａを構成しうる。 As shown in FIG. 23, the first conductive layer 2 (more specifically, the first electrode 25) has portions 256 and 257, and the second conductive layer 3 (more specifically, the second electrode 35). ) Have sites 356, 357. The portions 256 and 357 are in contact with the semiconductor layer 71, and the portions 257 and 356 are in contact with the semiconductor layer 72. Then, in the example shown in the figure, the portion 256 can constitute the first terminal 61A of the first rectifying element 61, and the second electrode 356 can constitute the second terminal 61B of the first rectifying element 61. In the example shown in the figure, the portion 257 can constitute the second terminal 62B of the second rectifying element 62, and the portion 357 can constitute the first terminal 62A of the second rectifying element 62.
　図２２、図２３では、第１電極２５および第２電極３５の間に第１整流素子６１および第２整流素子６２が形成された例を示したが、第１導電体層２における第１電極２５以外の部位と、第２導電体層３における第２電極３５以外の部位との間に、第１整流素子６１および第２電極３５が形成されていてもよい。本開示では第１整流素子６１および第２整流素子６２の２つの整流素子が形成された例を示しているが、第１整流素子６１および第２整流素子６２の１つのみが形成されていてもよい。本開示では第１整流素子６１および第２整流素子６２の２つの整流素子が形成された例を示しているが、第１整流素子６１および第２整流素子６２に加え、テラヘルツ素子５に電気的に直列あるいは並列に接続された追加の素子が配置されていてもよい。 Although FIG. 22 and FIG. 23 show an example in which the first rectifying element 61 and the second rectifying element 62 are formed between the first electrode 25 and the second electrode 35, the first electrode in the first conductive layer 2 is shown. The first rectifying element 61 and the second electrode 35 may be formed between the portion other than 25 and the portion of the second conductor layer 3 other than the second electrode 35. Although the present disclosure shows an example in which two rectifying elements of the first rectifying element 61 and the second rectifying element 62 are formed, only one of the first rectifying element 61 and the second rectifying element 62 is formed. It is also good. Although the present disclosure shows an example in which two rectification elements of the first rectification element 61 and the second rectification element 62 are formed, in addition to the first rectification element 61 and the second rectification element 62, the terahertz element 5 is electrically There may be additional elements connected in series or in parallel.
　図２４は、第１実施形態のテラヘルツ装置の断面図である。図２４に示す支持体８には半導体部品Ｂ１が配置されている。支持体８は、基板８１および導電体層８２を含む。配線基板８１は、たとえばガラスエポキシ基板である。配線基板８１には、半導体部品Ｂ１が配置されている。導電体層８２は、配線基板８１に形成されている。導電体層８２は、第１導電エレメント８２１および第２導電エレメント８２２を含む。第１導電エレメント８２１および第２導電エレメント８２２は互いに離間している。支持体８は、ガラスエポキシ基板を備えていなくてもよい。支持体８は、リードフレームに由来する１または複数のリードを備えていてもよい。 FIG. 24 is a cross-sectional view of the terahertz device of the first embodiment. A semiconductor component B1 is disposed on a support 8 shown in FIG. The support 8 includes a substrate 81 and a conductor layer 82. Wiring board 81 is, for example, a glass epoxy board. A semiconductor component B1 is disposed on the wiring substrate 81. The conductor layer 82 is formed on the wiring substrate 81. The conductor layer 82 includes a first conductive element 821 and a second conductive element 822. The first conductive element 821 and the second conductive element 822 are spaced apart from one another. The support 8 may not have a glass epoxy substrate. The support 8 may comprise one or more leads derived from a lead frame.
　樹脂部８５は、配線基板８１に配置されている。樹脂部８５は、たとえばエポキシ樹脂よりなる。樹脂部８５は、表面８５３を有する。表面８５３は、配線基板８１の厚さ方向（本実施形態では半導体基板１の厚さ方向Ｚ１と一致する）の一方を向いている。樹脂部８５には、半導体部品Ｂ１が収容された空間８５１が形成されている。空間８５１は、第１側面８５１Ａおよび第２側面８５１Ｂを有する。第１側面８５１Ａは、方向Ｚ１に対し傾斜している。第２側面８５１Ｂは、厚さ方向Ｚ１において、第１側面８５１Ａおよび配線基板８１の間に位置する。第２側面８５１Ｂは配線基板８１の厚さ方向Ｚ１に沿って延びている。厚さ方向Ｚ１における、第２側面８５１Ｂの寸法は、厚さ方向Ｚ１における、テラヘルツ素子Ｂ１の寸法よりも、大きい。 The resin portion 85 is disposed on the wiring board 81. Resin portion 85 is made of, for example, an epoxy resin. The resin portion 85 has a surface 853. The surface 853 faces one side in the thickness direction of the wiring substrate 81 (which coincides with the thickness direction Z1 of the semiconductor substrate 1 in the present embodiment). In the resin portion 85, a space 851 in which the semiconductor component B1 is accommodated is formed. The space 851 has a first side 851A and a second side 851B. The first side surface 851A is inclined with respect to the direction Z1. The second side surface 851B is located between the first side surface 851A and the wiring board 81 in the thickness direction Z1. The second side surface 851 B extends along the thickness direction Z 1 of the wiring substrate 81. The dimension of the second side surface 851B in the thickness direction Z1 is larger than the dimension of the terahertz element B1 in the thickness direction Z1.
　金属層８６は、第１側面８５１Ａに配置されているとよい。金属層８６は、第２側面８５１Ｂにも配置されていてもよい。金属層８６は、金属がめっきされた層であるとよい。金属層８６は、テラヘルツ波をより効率的に反射する。ワイヤ８７１，８７２は、半導体部品Ｂ１と配線基板８１（より厳密には導電体層８２）に接合されている。ワイヤ８７１は、半導体部品Ｂ１の第１電極２５と、導電体層８２における第１導電エレメント８２２とに接合されている。ワイヤ８７２は、半導体部品Ｂ１の第２電極３５と、導電体層８２における第２導電エレメント８２１とに接合されている。図示した例とは異なり、第１側面８５１Ａおよび第２側面８５１Ｂは金属により構成されていてもよい。 The metal layer 86 may be disposed on the first side surface 851A. The metal layer 86 may also be disposed on the second side surface 851B. The metal layer 86 may be a metal plated layer. The metal layer 86 reflects the terahertz wave more efficiently. The wires 871 and 872 are bonded to the semiconductor component B1 and the wiring board 81 (more strictly, the conductor layer 82). The wire 871 is bonded to the first electrode 25 of the semiconductor component B1 and the first conductive element 822 in the conductive layer 82. The wire 872 is bonded to the second electrode 35 of the semiconductor component B1 and the second conductive element 821 in the conductive layer 82. Unlike the illustrated example, the first side surface 851A and the second side surface 851B may be made of metal.
　次に、本実施形態の作用効果について説明する。 Next, the operation and effect of the present embodiment will be described.
　本実施形態においては、図１５に示したように、テラヘルツ装置Ａ１は、テラヘルツ素子５と電気的に並列接続された第１整流素子６１を備える。このような構成によると、テラヘルツ素子５の両端に、たとえば静電気等によって大電圧が印加されたとしても、第１整流素子６１を経由して電流を流すことが可能となる。これにより、テラヘルツ素子５に大電流が流れることを抑制できるため、テラヘルツ素子５が静電気等によって故障することを回避しうる。 In the present embodiment, as shown in FIG. 15, the terahertz device A1 includes a first rectifying element 61 electrically connected in parallel to the terahertz element 5. According to such a configuration, even if a large voltage is applied to both ends of the terahertz element 5 by, for example, static electricity or the like, it becomes possible to cause current to flow through the first rectifying element 61. As a result, the flow of a large current to the terahertz element 5 can be suppressed, so that the terahertz element 5 can be prevented from breakdown due to static electricity or the like.
　本実施形態においては、図１５に示したように、テラヘルツ装置Ａ１は、テラヘルツ素子５と第１整流素子６１とのいずれにも電気的に並列接続された第２整流素子６２を備える。このような構成によると、上述したのと同様の理由により、テラヘルツ素子５が静電気等によって故障することを回避しうる。 In the present embodiment, as shown in FIG. 15, the terahertz device A1 includes a second rectifying element 62 electrically connected in parallel to both the terahertz element 5 and the first rectifying element 61. According to such a configuration, the terahertz element 5 can be prevented from breakdown due to static electricity or the like for the same reason as described above.
　本実施形態においては、第１整流素子６１において、第１端子６１Ａから第２端子６１Ｂに向かう電気的な方向が順方向である。第２整流素子６２において、第１端子６２Ａから第２端子６２Ｂに向かう電気的な方向が順方向である。第１整流素子６１の第１端子６１Ａは、第２整流素子６２の第２端子６２Ｂに導通している。このような構成によると、第２端子６１Ｂに対する第１端子６１Ａの電圧が正となる非常に高い電圧が、テラヘルツ素子５の両端に印加された場合には、第１端子６１Ａから第２端子６１Ｂに向かって第１整流素子６１を介して電流が流れる。第２端子６１Ｂに対する第１端子６１Ａの電圧が負となる非常に高い電圧が、テラヘルツ素子５の両端に印加された場合には、第１端子６２Ａから第２端子６２Ｂに向かって第２整流素子６２を介して電流が流れる。これにより、テラヘルツ素子５に印加されうる電圧の正負に関わらず、テラヘルツ素子５に過大な電流が流れる可能性を低減できる。したがって、より効果的に、テラヘルツ素子５が静電気等によって故障することを回避しうる。 In the present embodiment, in the first rectifying element 61, the electrical direction from the first terminal 61A to the second terminal 61B is the forward direction. In the second rectifying element 62, the electrical direction from the first terminal 62A to the second terminal 62B is the forward direction. The first terminal 61 </ b> A of the first rectifying element 61 is electrically connected to the second terminal 62 </ b> B of the second rectifying element 62. According to such a configuration, when a very high voltage at which the voltage of the first terminal 61A with respect to the second terminal 61B is positive is applied to both ends of the terahertz element 5, the first terminal 61A to the second terminal 61B Current flows through the first rectifying element 61 toward the When a very high voltage that the voltage of the first terminal 61A is negative with respect to the second terminal 61B is applied to both ends of the terahertz element 5, the second rectifying element from the first terminal 62A to the second terminal 62B A current flows through 62. Thus, regardless of whether the voltage that can be applied to the terahertz element 5 is positive or negative, the possibility of an excessive current flowing in the terahertz element 5 can be reduced. Therefore, it is possible to more effectively avoid the failure of the terahertz element 5 due to static electricity or the like.
　本実施形態においては、第１整流素子６１および第２整流素子６２はいずれも、半導体基板１上に形成されている。このような構成は、半導体基板１の大型化を招くことを極力回避しつつ実現しうる。したがって、本実施形態は、テラヘルツ装置Ａ１の大型化を回避するのに適する。 In the present embodiment, each of the first rectifier element 61 and the second rectifier element 62 is formed on the semiconductor substrate 1. Such a configuration can be realized while avoiding the increase in size of the semiconductor substrate 1 as much as possible. Therefore, the present embodiment is suitable for avoiding the upsizing of the terahertz device A1.
＜変形例＞
　以下の説明では、上記と同一または類似の構成については上記と同一の符号を付し、説明を適宜省略する。 <Modification>
In the following description, the same or similar components as those described above are denoted by the same reference numerals as those described above, and the description will be appropriately omitted.
　以下の変形例の各構成は、図２５に示すように、第１整流素子６１および第２整流素子６２が、半導体基板１上に形成されていない点において、図２に示した構成と異なり、その他の点は略同様であるから説明を省略する。テラヘルツ素子５、第１整流素子６１、および第２整流素子６２の電気的な配置は、図１５に示したものである。以下の変形例の各構成は、上記実施形態における、図２２、図２３以外の図面に関する説明を適用できる。 Each configuration of the following modification differs from the configuration shown in FIG. 2 in that the first rectifier element 61 and the second rectifier element 62 are not formed on the semiconductor substrate 1 as shown in FIG. Since the other points are substantially the same, the description will be omitted. The electrical arrangement of the terahertz element 5, the first rectifying element 61, and the second rectifying element 62 is as shown in FIG. Each structure of the following modification can apply the description regarding drawings other than FIG. 22, FIG. 23 in the said embodiment.
　図２６は、第１実施形態の第１変形例のテラヘルツ装置の平面図である。図２６のテラヘルツ装置Ａ２では、第１導電エレメント８２１は、第１部位８２１Ａおよび第２部位８２１Ｂを含む。第１部位８２１Ａおよび第２部位８２１Ｂの仮想上の境界を、図２６にて縦に延びる二点鎖線で示している。第１部位８２１Ａは、縁８２１Ｅを含む。第１部位８２１Ａは、図２６における縦方向に沿って延びている。第２部位８２１Ｂは、第２導電エレメント８２２に向かって第１部位８２１Ａから延び出ている。第２部位８２１Ｂは、縁８２１Ｆを含む。縁８２１Ｆは、縁８２１Ｅにつながっている。同図では、第１部位８２１Ａに、第１整流素子６１が配置されている。また、第１部位８２１Ａおよび第２部位８２１Ｂに、テラヘルツ素子５が配置されている。 FIG. 26 is a plan view of the terahertz device of the first modified example of the first embodiment. In the terahertz device A2 of FIG. 26, the first conductive element 821 includes a first portion 821A and a second portion 821B. The imaginary boundaries of the first portion 821A and the second portion 821B are indicated by the two-dot chain lines extending vertically in FIG. The first portion 821A includes an edge 821E. The first portion 821A extends in the longitudinal direction in FIG. The second portion 821 B extends from the first portion 821 A toward the second conductive element 822. The second portion 821B includes an edge 821F. Edge 821F is connected to edge 821E. In the same figure, the 1st rectification element 61 is arranged at the 1st part 821A. In addition, the terahertz element 5 is disposed in the first portion 821A and the second portion 821B.
　図２６では、第２導電エレメント８２２は、第１部位８２２Ａおよび２つの第２部位８２２Ｂを含む。第１部位８２２Ａおよび第２部位８２２Ｂの仮想上の境界を、図２６にて縦に延びる二点鎖線で示している。第１部位８２２Ａの一部は、第２部位８２１Ｂに対向している。第１部位８２２Ａは、縁８２２Ｅを含む。第２部位８２２Ｂは、第１部位８２２Ａから第１導電エレメント８２１に向かって延び出ている。第２部位８２２Ｂは、縁８２２Ｆを含む。各第２部位８２２Ｂの一部は、第１部位８２１Ａに対向している。縁８２２Ｆは縁８２２Ｅにつながっている。図２６では、第１部位８２２Ａと２つの第２部位８２２Ｂとによって、凹部８２２Ｒが形成されている。凹部８２２Ｒには、第１導電エレメント８２１の第２部位８２１Ｂが配置されている。同図では、第１部位８２２Ａと第２部位８２２Ｂとに第２整流素子６２が配置されている。 In FIG. 26, the second conductive element 822 includes a first portion 822A and two second portions 822B. The imaginary boundaries of the first portion 822A and the second portion 822B are indicated by the two-dot chain lines extending longitudinally in FIG. A portion of the first portion 822A faces the second portion 821B. The first portion 822A includes an edge 822E. The second portion 822B extends from the first portion 822A toward the first conductive element 821. The second portion 822B includes an edge 822F. A portion of each second portion 822B faces the first portion 821A. Edge 822F is connected to edge 822E. In FIG. 26, the recess 822R is formed by the first portion 822A and the two second portions 822B. The second portion 821 B of the first conductive element 821 is disposed in the recess 822 R. In the same figure, the 2nd rectification element 62 is arranged at the 1st part 822A and the 2nd part 822B.
　ワイヤ８６１は、第１整流素子６１と、第２導電エレメント８２２における第２部位８２２Ｂと、に接合されている。ワイヤ８６２は、第２整流素子６２と、第２導電エレメント８２２における第２部位８２２Ｂと、に接合されている。ワイヤ８７１は、半導体部品Ｂ１と、第１導電エレメント８２１における第１部位８２１Ａと、に接合されている。ワイヤ８７２は、半導体部品Ｂ１と、第２導電エレメント８２２における第１部位８２２Ａと、に接合されている。ワイヤ８６１、８６２、８７１、８７２はいずれも、平面視において、第１部位２１および第２部位３１（本実施形態ではいずれもアンテナとして機能しうる）に沿って延びる仮想直線ＬＬを避けて形成されている。図示の例においては、ワイヤ８６１、８６２、８７１、８７２はいずれも、平面視において、第１部位２１および第２部位３１（本実施形態ではいずれもアンテナとして機能しうる）に沿って延びる仮想直線ＬＬに交差しない。平面視において、仮想直線ＬＬを挟んで互いに反対側に、第１整流素子６１および第２整流素子６２が配置されている。 The wire 861 is bonded to the first rectifying element 61 and the second portion 822 B of the second conductive element 822. The wire 862 is bonded to the second rectifying element 62 and the second portion 822 B of the second conductive element 822. The wire 871 is bonded to the semiconductor component B1 and the first portion 821A of the first conductive element 821. The wire 872 is bonded to the semiconductor component B1 and the first portion 822A of the second conductive element 822. The wires 861, 862, 871, 872 are all formed in a plan view avoiding the virtual straight line LL extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment). ing. In the illustrated example, each of the wires 861, 862, 871, 872 is a virtual straight line extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment) in plan view. Do not cross to LL. In plan view, the first rectifier element 61 and the second rectifier element 62 are disposed on opposite sides of the virtual straight line LL.
　本変形例では、ワイヤ８６１、８６２、８７１、８７２はいずれも、平面視において、第１部位２１および第２部位３１（本実施形態ではいずれもアンテナとして機能しうる）に沿って延びる仮想直線ＬＬを避けて形成されている。このような構成によると、ワイヤ８６１、８６２、８７１、８７２が、テラヘルツの発振（あるいは受信）に影響を与えにくくできる。影響を与えにくくできる理由の一つとしては、たとえば、導体（すなわちワイヤ）が、第１部位２１および第２部位３１（本実施形態ではいずれもアンテナとして機能しうる）に関して形成される電磁場に影響しにくいことが、考えられる。 In this modification, all of the wires 861, 862, 871, 872 are virtual straight lines LL extending along the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment) in plan view. It is formed avoiding the. According to such a configuration, the wires 861, 862, 871, 872 can hardly affect the oscillation (or reception) of the terahertz wave. One of the reasons why the influence can be made difficult is, for example, the influence of the electromagnetic field formed by the conductor (that is, the wire) on the first portion 21 and the second portion 31 (both can function as an antenna in this embodiment) It is thought that it is difficult to do.
　本変形例では、平面視において、仮想直線ＬＬを挟んで互いに反対側に、第１整流素子６１および第２整流素子６２が配置されている。このような構成によると、半導体部品Ｂ１を支持体８の平面視におけるより中心側に配置しやすい。テラヘルツの発振（あるいは受信）に影響を与えにくくしつつ、平面視における支持体８の面積をより小さくすることが可能となる。 In the present modification, in plan view, the first rectifier element 61 and the second rectifier element 62 are disposed on opposite sides of the virtual straight line LL. According to such a configuration, the semiconductor component B <b> 1 can be easily disposed on the center side in plan view of the support 8. It is possible to further reduce the area of the support 8 in plan view while making it difficult to affect the oscillation (or reception) of the terahertz wave.
　図２７に示す変形例では、第１導電エレメント８２１および第２導電エレメント８２２の形状が一部異なる。図２７では、第２部位８２１Ｂに、第１整流素子６１が配置されている。第１部位８２１Ａおよび第２部位８２１Ｂに、半導体部品Ｂ１が配置されている。このような構成によると、第１整流素子６１を図２７におけるより右側に配置できるので、図２６に示す変形例と比較して、支持体８の平面視における小面積化を実現しうる。 In the modification shown in FIG. 27, the shapes of the first conductive element 821 and the second conductive element 822 are partially different. In FIG. 27, the first rectifying element 61 is disposed at the second portion 821B. The semiconductor component B1 is disposed in the first portion 821A and the second portion 821B. According to such a configuration, since the first rectifying element 61 can be disposed further to the right in FIG. 27, the area reduction of the support 8 in a plan view can be realized as compared with the modification shown in FIG.
　図２８に示す変形例のように、第１整流素子６１および第２整流素子６２を配置してもよい。 As in the modification shown in FIG. 28, the first rectifier element 61 and the second rectifier element 62 may be arranged.
　本開示では、テラヘルツ装置が支持体および樹脂部を含むものである例を示したが、テラヘルツ装置は、本開示の半導体装置に相当するチップタイプのものであってもよい。 The present disclosure shows an example in which the terahertz device includes the support and the resin portion, but the terahertz device may be a chip type equivalent to the semiconductor device of the present disclosure.
　図２９には、別の変形例を示している。図２９に示すテラヘルツ装置Ａ１２は、部材Ｇ１０を更に備える点において、図２４に示したテラヘルツ装置Ａ１とは異なる。本変形例の構成は、図２４に示したテラヘルツ装置Ａ１以外のテラヘルツ装置と組み合わせてもよい。 FIG. 29 shows another modification. The terahertz device A12 illustrated in FIG. 29 differs from the terahertz device A1 illustrated in FIG. 24 in that the terahertz device A12 further includes a member G10. The configuration of this modification may be combined with a terahertz device other than the terahertz device A1 shown in FIG.
　図２９に示すように、部材Ｇ１０は、樹脂部８５に配置されている。部材Ｇ１０は、空間８５１に露出している。本変形例では、空間８５１は、樹脂部８５および部材Ｇ１０に規定されている。本変形例においては、樹脂部８５に形成された空間８５１には、気体が充填されている。当該気体の具体例は、たとえば、不活性気体（たとえば窒素）および空気を含む。本変形例では、部材Ｇ１０は、板状であるが、他の形状であってもよい。部材Ｇ１０は、たとえば、接合層Ｇ１２を介して、樹脂部８５に形成されていてもよい。空間８５１は、部材Ｇ１０（および接合層Ｇ１２）によって、密閉されていてもよい。図３９、図４０に示すように、部材Ｇ１０を樹脂部８５に配置しやすくするために、樹脂部８５に部材Ｇ１０をはめ込むための少なくとも１つの部位（図３９では部位８８８Ａ～８８８Ｄ、図４０では部位８８８）を形成してもよい。 As shown in FIG. 29, the member G <b> 10 is disposed in the resin portion 85. The member G10 is exposed to the space 851. In the present modification, the space 851 is defined by the resin portion 85 and the member G10. In the present modification, the space 851 formed in the resin portion 85 is filled with a gas. Examples of such gases include, for example, inert gases (eg, nitrogen) and air. In the present modification, the member G10 has a plate shape, but may have another shape. For example, the member G10 may be formed in the resin portion 85 via the bonding layer G12. The space 851 may be sealed by the member G10 (and the bonding layer G12). As shown in FIGS. 39 and 40, at least one portion for inserting the member G10 into the resin portion 85 in order to facilitate the arrangement of the member G10 in the resin portion 85 (portions 888A to 888D in FIG. 39, FIG. The site 888) may be formed.
　図２９に示すように、本変形例においては、部材Ｇ１０は、第１部分Ｇ１１と、第２部分Ｇ１３と、第３部分Ｇ１５とを含む。 As shown in FIG. 29, in the present modification, the member G10 includes a first portion G11, a second portion G13, and a third portion G15.
　第１部分Ｇ１１は、たとえば絶縁材料よりなる。第１部分Ｇ１１は、たとえば、基板（シートやフィルム状のものも含む）であってもよい。第１部分Ｇ１１を構成する材料は、たとえば、テラヘルツ波に対する吸収損失が低く、かつ、テラヘルツ波の透過率が高いものであることが、好ましい。たとえば、第１部分Ｇ１１を構成する基板として、低誘電率の薄膜シートや高抵抗のＳｉ基板等を用いることができる。Ｓｉ基板を用いた場合、積層構造を形成しやすい。第１部分Ｇ１１を構成する材料の他の例は、たとえば、ポリマーおよびＭｇＯを含む。ポリマーを用いる場合、たとえば、シート状に加工したものにパターンを転写することにより、第１部分Ｇ１１を形成できる。ＭｇＯを用いた場合、テラヘルツ波の吸収損失を小さく出来るメリットを享受しうる。あるいは、第１部分Ｇ１１を構成する材料として、化合物半導体（ＳｉＣ、ＧａＮ、ＧａＡｓ、ＩｎＰ、サファイヤ等）を用いてもよい。化合物半導体にドーパントを調整して、抵抗率を大きくしてもよい。 The first portion G11 is made of, for example, an insulating material. The first portion G11 may be, for example, a substrate (including a sheet or a film). It is preferable that the material forming the first portion G11 be, for example, one having a low absorption loss with respect to the terahertz wave and a high transmittance of the terahertz wave. For example, a thin film sheet with a low dielectric constant, a Si substrate with high resistance, or the like can be used as a substrate constituting the first portion G11. When a Si substrate is used, it is easy to form a laminated structure. Other examples of the material constituting the first portion G11 include, for example, a polymer and MgO. In the case of using a polymer, for example, the first portion G11 can be formed by transferring a pattern to a sheet-like material. When MgO is used, the merit that the absorption loss of the terahertz wave can be reduced can be enjoyed. Alternatively, a compound semiconductor (SiC, GaN, GaAs, InP, sapphire, or the like) may be used as a material forming the first portion G11. The resistivity may be increased by adjusting the dopant to the compound semiconductor.
　第２部分Ｇ１３は、たとえば、導電材料（たとえば金属（たとえば、Ｃｕ、Ａｌ、あるいはＡｕ等））よりなる。第２部分Ｇ１３は、テラヘルツ波に対する所望の機能を発揮しうる。具体的には、第２部分Ｇ１３は、たとえば、テラヘルツ波帯の偏光機能、周波数フィルター機能、および平面レンズ機能の少なくとも１つの機能を発揮しうる。 The second portion G13 is made of, for example, a conductive material (for example, a metal (for example, Cu, Al, Au or the like)). The second portion G13 can exhibit a desired function for terahertz waves. Specifically, the second portion G13 can exhibit, for example, at least one of the polarization function of the terahertz wave band, the frequency filter function, and the planar lens function.
　第２部分Ｇ１３は、複数の層を含んでいてもよい。図２９に示す例では、第２部分Ｇ１３は、Ｇ１３１、Ｇ１３２を含んでいる。複数の層Ｇ１３１、Ｇ１３２は、互いに図２９の方向Ｚ１において異なる位置に（すなわち異なる高さ位置に）配置されている。各層Ｇ１３１、Ｇ１３２が、所望の機能を発揮するとよい。また、各層Ｇ１３１、Ｇ１３２の平面視の形状や機能が互いに異なっていてもよいし、互いに同一であってもよい。図２９とは異なり、第２部分Ｇ１３が一層のみ（たとえば層Ｇ１３１のみ）の構造であってもよい。また、第２部分Ｇ１３が、３以上の層を含んでいてもよい。 The second portion G13 may include a plurality of layers. In the example shown in FIG. 29, the second portion G13 includes G131 and G132. The plurality of layers G131 and G132 are disposed at different positions in the direction Z1 of FIG. 29 (ie, at different height positions). Each of the layers G131 and G132 may exhibit a desired function. Further, the shapes and functions of the layers G131 and G132 in plan view may be different from each other, or may be identical to each other. Unlike FIG. 29, the second portion G13 may have a structure of only one layer (for example, only the layer G131). In addition, the second portion G13 may include three or more layers.
　第２部分Ｇ１３は、平面視において、少なくとも１つの帯状部分、少なくとも１つの環状部分、および少なくとも１つのドットの少なくともいずれかを含んでいてもよい。図３０～図３４に、平面視の第２部分Ｇ１３の形状の具体例を示す。図２９に示す各層Ｇ１３１、Ｇ１３２が、後述の図３０～図３４のいずれかの形状を有していてもよい。 The second portion G13 may include at least one band portion, at least one annular portion, and / or at least one dot in a plan view. 30 to 34 show specific examples of the shape of the second portion G13 in plan view. Each layer G131, G132 shown in FIG. 29 may have any of the shapes shown in FIGS. 30 to 34 described later.
　図３０に示す第２部分Ｇ１３は、平面視において、複数の帯状部分（すなわち、スリット構造）を有している。図３０に示す第２部分Ｇ１３により発揮されうる機能は、たとえば、テラヘルツ波帯の偏光機能や周波数フィルター機能である。図３１に示す第２部分Ｇ１３は、平面視において、複数の環状部分（すなわち、リング構造）を有している。図３１に示す第２部分Ｇ１３により発揮されうる機能は、たとえば、アンテナ機能や集光機能である。図３２に示す第２部分Ｇ１３は、平面視において、複数のドット（すなわち、ドット構造）を有している。図３２に示す第２部分Ｇ１３により発揮されうる機能は、たとえば、ビームパターン制御機能や二次元共振器機能である。その他、第２部分Ｇ１３の平面視の形状が、図３３や図３４に示すものであってもよい。 The second portion G13 shown in FIG. 30 has a plurality of strip portions (i.e., slit structures) in a plan view. The function that can be exhibited by the second portion G13 shown in FIG. 30 is, for example, the polarization function of the terahertz wave band or the frequency filter function. The second portion G13 shown in FIG. 31 has a plurality of annular portions (ie, ring structures) in a plan view. The function that can be exhibited by the second portion G13 shown in FIG. 31 is, for example, an antenna function or a light collecting function. The second portion G13 shown in FIG. 32 has a plurality of dots (that is, a dot structure) in a plan view. The function that can be exerted by the second portion G13 shown in FIG. 32 is, for example, a beam pattern control function or a two-dimensional resonator function. In addition, the shape of planar view of 2nd part G13 may be shown in FIG.33 and FIG.34.
　図２９に示すように、第３部分Ｇ１５は、第２部分Ｇ１３上に配置されている。第３部分Ｇ１５は、たとえば絶縁材料よりなる。このような絶縁材料の具体例は、たとえば、ＳｉＯ2、ＳｉＮ、樹脂、および、ポリマーを含む。図２９に示すように、第３部分Ｇ１５は、複数の層Ｇ１５１、Ｇ１５２を含んでいてもよい。複数の層Ｇ１５１、Ｇ１５２は互いに積層されている。 As shown in FIG. 29, the third portion G15 is disposed on the second portion G13. The third portion G15 is made of, for example, an insulating material. Examples of such insulating materials include, for example, SiO 2 , SiN, resins, and polymers. As shown in FIG. 29, the third portion G15 may include a plurality of layers G151 and G152. The plurality of layers G151 and G152 are stacked on one another.
　図２９に示す、部材Ｇ１０と半導体部品Ｂ１との離間距離ＬＬは、たとえば、半導体部品Ｂ１からのテラヘルツ波の１波長（存在する空間中の実効波長）よりも小さくてもよい。離間距離ＬＬが半導体部品Ｂ１からのテラヘルツ波の１波長（存在する空間中の実効波長）よりも小さい場合、近接場のカップリングを用いることで、半導体部品Ｂ１からのテラヘルツ波を適切に外部へと放出させうる。たとえば、半導体部品Ｂ１が空気中に存在する場合には、１波長は１ｍｍ程度であるため、離間距離ＬＬは１ｍｍよりも小さくてもよい。 The separation distance LL between the member G10 and the semiconductor component B1 shown in FIG. 29 may be smaller than, for example, one wavelength of the terahertz wave from the semiconductor component B1 (effective wavelength in the existing space). When the separation distance LL is smaller than one wavelength of the terahertz wave from the semiconductor component B1 (the effective wavelength in the existing space), the terahertz wave from the semiconductor component B1 is appropriately transferred to the outside by using near field coupling. Can be released. For example, when the semiconductor component B1 is present in the air, since one wavelength is about 1 mm, the separation distance LL may be smaller than 1 mm.
　図３５～図３８を用いて、部材Ｇ１０の製造方法につき簡単に説明する。まず、図３５に示すように、第１部分Ｇ１１に、第２部分Ｇ１３の層Ｇ１３１を形成する。層Ｇ１３１は金属よりなっていてもよい。層Ｇ１３１は、たとえばパターンニングにより形成されうる。次に、図３６に示すように、第３部分Ｇ１５の層Ｇ１５１を形成する。層Ｇ１５１は、たとえば、絶縁材料を層Ｇ１３１上に形成した後に、表面研磨することにより形成されうる。なお、当該表面研磨が行われなくてもよい。次に、図３５および図３６を用いて説明したのと同様に、図３７、図３８に示すように、層Ｇ１３２および層Ｇ１５２を順次形成する。その後、ダイシングを行うことにより、図３８に示す部材Ｇ１０が製造される。 The method of manufacturing the member G10 will be briefly described with reference to FIGS. First, as shown in FIG. 35, the layer G131 of the second portion G13 is formed in the first portion G11. The layer G131 may be made of metal. Layer G131 can be formed, for example, by patterning. Next, as shown in FIG. 36, a layer G151 of the third portion G15 is formed. The layer G151 can be formed, for example, by polishing the surface after forming an insulating material on the layer G131. In addition, the said surface grinding | polishing does not need to be performed. Next, as described with reference to FIGS. 35 and 36, as shown in FIGS. 37 and 38, a layer G132 and a layer G152 are sequentially formed. Thereafter, dicing is performed to manufacture a member G10 shown in FIG.
　図４１には、本変形例の装置の平面図を示している。同図に示す装置は、図２６に示した構成と、図３０に示した構成と、を組み合わせたものである。図４１においては、半導体装置Ｂ１の中心点Ｃ１１と、第２部分Ｇ１３の対称点Ｃ１２（平面視において、対称点Ｃ１２について第２部分Ｇ１３が点対称となっている）とが一致している。 FIG. 41 shows a plan view of the device of this modification. The apparatus shown in the figure is a combination of the configuration shown in FIG. 26 and the configuration shown in FIG. In FIG. 41, the central point C11 of the semiconductor device B1 coincides with the symmetry point C12 of the second portion G13 (the second portion G13 is symmetrical with respect to the symmetry point C12 in plan view).
　図４１に示したものとは異なり、図２６に示した構成と、図３１～３４のいずれかに示した構成と、を組み合わせてもよい。図４２～図４５は、それぞれ、図２６に示した構成と、図３１～３４に示した構成と、を組み合わせたものである。図４２～図４５においても、半導体装置Ｂ１の中心点Ｃ１１と、第２部分Ｇ１３の対称点Ｃ１２（平面視において、対称点Ｃ１２について第２部分Ｇ１３が点対称となっている）とが一致している。 Unlike the configuration shown in FIG. 41, the configuration shown in FIG. 26 may be combined with the configuration shown in any of FIGS. FIGS. 42 to 45 each show a combination of the configuration shown in FIG. 26 and the configurations shown in FIGS. 31 to 34. Also in FIGS. 42 to 45, the central point C11 of the semiconductor device B1 coincides with the symmetry point C12 of the second portion G13 (the second portion G13 is symmetrical with respect to the symmetry point C12 in plan view). ing.
　図２９に示す変形例では、樹脂部８５に形成された空間８５１には、気体が充填されている。このような構成によると、空間８５１に樹脂が充填されている場合と比べて、テラヘルツ波が樹脂を透過する際に減衰することを、抑制できる。また、本変形例によると、樹脂が半導体部品Ｂ１に付着することにより、境界条件が変化してしまいチップ基板内での共振モードに影響する問題の発生を低減あるいは防止できる。 In the modified example shown in FIG. 29, the space 851 formed in the resin portion 85 is filled with a gas. According to such a configuration, it is possible to suppress that the terahertz wave attenuates when passing through the resin, as compared with the case where the space 851 is filled with the resin. Further, according to this modification, the resin adhering to the semiconductor component B1 can reduce or prevent the occurrence of the problem that the boundary conditions change and the resonance mode in the chip substrate is affected.
　本変形例においては、第２部分Ｇ１３は導電材料よりなる。このような構成によると、第２部分Ｇ１３に、テラヘルツ波に対する所望の機能を発揮させることが可能となる。これにより、より好適なテラヘルツ装置が提供されうる。また、第２部分Ｇ１３は、複数の層Ｇ１３１を含んでいてもよい。この場合には、複数の層Ｇ１３１に、たとえば、異なる機能を発揮させることが可能となる。 In the present modification, the second portion G13 is made of a conductive material. According to such a configuration, it is possible to cause the second portion G13 to exhibit a desired function for the terahertz wave. Thereby, a more suitable terahertz device can be provided. The second portion G13 may include a plurality of layers G131. In this case, for example, different functions can be exhibited in the plurality of layers G131.
　本開示は、上述した実施形態に限定されるものではない。本開示の各部の具体的な構成は、種々に設計変更自在である。 The present disclosure is not limited to the embodiments described above. The specific configuration of each part of the present disclosure can be varied in design in many ways.
　本開示は以下の付記に関する実施形態を含む。
　　［付記１］
　半導体基板と、
　前記半導体基板上に配置されたテラヘルツ素子と、
　前記テラヘルツ素子と電気的に並列接続された第１整流素子と、を備える、テラヘルツ装置。
　　［付記２］
　前記テラヘルツ素子と前記第１整流素子とのいずれにも電気的に並列接続された第２整流素子を更に備える、付記１に記載のテラヘルツ装置。
　　［付記３］
　前記第１整流素子および前記第２整流素子は各々、第１端子および第２端子を含み、前記第１整流素子および前記第２整流素子の各々において、前記第１端子から前記第２端子に向かう電気的な方向が順方向であり、
　前記第１整流素子の前記第１端子は、前記第２整流素子の前記第２端子に導通している、付記２に記載のテラヘルツ装置。
　　［付記４］
　前記第１整流素子は、第１立ち上がり電圧値および第１降伏電圧値を有し、前記第２整流素子は、第２立ち上がり電圧値および第２降伏電圧値を有し、
　前記第１立ち上がり電圧値の絶対値は、前記第１降伏電圧値の絶対値よりも小さく、
　前記第２立ち上がり電圧値の絶対値は、前記第２降伏電圧値の絶対値よりも小さく、
　前記第１立ち上がり電圧値および前記第２立ち上がり電圧値は、前記テラヘルツ素子がテラヘルツ波を発振する電圧領域における値の絶対値の下限よりも、大きい、付記２または付記３に記載のテラヘルツ装置。
　　［付記５］
　前記第１立ち上がり電圧値および前記第２立ち上がり電圧値は、前記テラヘルツ素子がテラヘルツ波を発振する電圧領域における値の絶対値の上限よりも、大きい、付記４に記載のテラヘルツ装置。
　　［付記６］
　前記半導体基板上に各々形成され、互いに絶縁された第１導電体層および第２導電体層を更に備え、
　前記第１整流素子および前記第２整流素子はいずれも、前記半導体基板上に形成され、且つ、前記第１導電体層および前記第２導電体層の間に電気的に介在している、付記２ないし付記５のいずれかに記載のテラヘルツ装置。
　　［付記７］
　前記半導体基板上に各々形成され、且つ、互いに積層された第１半導体層および第２半導体層を更に備え、
　前記第１半導体層は、第１導電型を有し、前記第２半導体層は、前記第１導電型とは反対の第２導電型を有し、
　前記第１整流素子の前記第１端子と、前記第２整流素子の前記第２端子とは、前記第１導電体層によって構成され、
　前記第１整流素子の前記第２端子と、前記第２整流素子の前記第１端子とは、前記第２導電体層によって構成されている、付記６に記載のテラヘルツ装置。
　　［付記８］
　互いに絶縁された第１導電部位および第２導電部位を更に備え、
　前記テラヘルツ素子は、前記第１導電部位および前記第２導電部位の間に電気的に介在しており、
　前記第１導電部位は、平面視において、前記テラヘルツ素子の位置する側から第１方向に沿って延びており、前記第２導電部位は、平面視において、前記テラヘルツ素子の位置する側から第１方向とは反対方向に沿って延びている、付記２ないし付記５のいずれかに記載のテラヘルツ装置。
　　［付記９］
　前記半導体基板が配置された支持体を更に備え、
　前記テラヘルツ素子および前記支持体に接合された第１ワイヤを更に備え、
　前記第１ワイヤは、平面視において、前記第１導電部位に沿って延びる仮想直線を避けて形成されている、付記８に記載のテラヘルツ装置。
　　［付記１０］
　前記テラヘルツ素子および前記支持体に接合された第２ワイヤを更に備え、
　前記第２ワイヤは、平面視において、前記仮想直線を避けて形成されている、付記９に記載のテラヘルツ装置。
　　［付記１１］
　前記第１整流素子および前記第２整流素子は、平面視において、前記仮想直線を挟んで互いに反対側に配置されている、付記９または付記１０に記載のテラヘルツ装置。
　　［付記１２］
　前記支持体は、互いに絶縁された第１導電エレメントおよび第２導電エレメントを含み、
　前記テラヘルツ装置および前記第１整流素子は、前記第１導電エレメントに配置されており、前記第２整流素子は、前記第２導電エレメントに配置されている、付記８ないし付記１１のいずれかに記載のテラヘルツ装置。
　　［付記１３］
　前記第１導電エレメントは、第１部位と、前記第２導電エレメントに向かって前記第１部位から延び出る第２部位と、を含み、
　前記テラヘルツ装置は、前記第１導電エレメントにおける前記第２部位に配置されている、付記１２に記載のテラヘルツ装置。
　　［付記１４］
　前記第１整流素子は、前記第１導電エレメントの前記第２部位に配置されている、付記１３に記載のテラヘルツ装置。
　　［付記１５］
　前記第２導電エレメントは、前記第１部位に対向する部位を含み、前記第２整流素子は、前記第２導電エレメントにおける前記部位に配置されている、付記１３または付記１４に記載のテラヘルツ装置。
　　［付記１６］
　前記テラヘルツ素子を包囲する空間が形成された樹脂部と、
　前記樹脂部に配置され、前記空隙に露出した部材と、を更に備え、
　前記空間には、気体が充填されている、付記１ないし付記１５のいずれかに記載のテラヘルツ装置。
　　［付記１７］
　前記部材は、前記樹脂部に配置された第１部分と、前記第１部分に配置された第２部分と、を含み、
　前記第２部分は、導電材料よりなる、付記１６に記載のテラヘルツ装置。
　　［付記１８］
　前記第２部分は、少なくとも１つの帯状部分、少なくとも１つの環状部分、および少なくとも１つのドットの少なくともいずれかを含む、付記１７に記載のテラヘルツ装置。 The present disclosure includes embodiments regarding the following appendices.
[Supplementary Note 1]
A semiconductor substrate,
A terahertz element disposed on the semiconductor substrate;
A terahertz device, comprising: a first rectifying element electrically connected in parallel to the terahertz element.
[Supplementary Note 2]
The terahertz device according to claim 1, further comprising a second rectifying element electrically connected in parallel to both the terahertz element and the first rectifying element.
[Supplementary Note 3]
Each of the first and second rectifying elements includes a first terminal and a second terminal, and in each of the first and second rectifying elements, the first terminal is directed to the second terminal. The electrical direction is forward,
The terahertz device according to claim 2, wherein the first terminal of the first rectifying element is electrically connected to the second terminal of the second rectifying element.
[Supplementary Note 4]
The first rectifying device has a first rising voltage value and a first breakdown voltage value, and the second rectifying device has a second rising voltage value and a second breakdown voltage value.
The absolute value of the first rising voltage value is smaller than the absolute value of the first breakdown voltage value,
The absolute value of the second rising voltage value is smaller than the absolute value of the second breakdown voltage value,
The terahertz device according to Appendix 2 or 3, wherein the first rising voltage value and the second rising voltage value are larger than the lower limit of the absolute value of the value in the voltage range where the terahertz element oscillates the terahertz wave.
[Supplementary Note 5]
The terahertz device according to claim 4, wherein the first rising voltage value and the second rising voltage value are larger than an upper limit of an absolute value of values in a voltage region where the terahertz element oscillates a terahertz wave.
[Supplementary Note 6]
The semiconductor device further comprises a first conductor layer and a second conductor layer which are respectively formed on the semiconductor substrate and insulated from each other.
The first rectifying element and the second rectifying element are both formed on the semiconductor substrate, and are electrically interposed between the first conductor layer and the second conductor layer. The terahertz device according to any one of 2 to 5.
[Supplementary Note 7]
The semiconductor device further includes a first semiconductor layer and a second semiconductor layer formed on the semiconductor substrate and stacked on each other.
The first semiconductor layer has a first conductivity type, and the second semiconductor layer has a second conductivity type opposite to the first conductivity type.
The first terminal of the first rectifying element and the second terminal of the second rectifying element are constituted by the first conductive layer,
The terahertz device according to claim 6, wherein the second terminal of the first rectifying element and the first terminal of the second rectifying element are configured by the second conductive layer.
[Supplementary Note 8]
Further comprising first and second conductive portions insulated from each other;
The terahertz element is electrically interposed between the first conductive site and the second conductive site,
The first conductive portion extends in the first direction from the side where the terahertz element is located in a plan view, and the second conductive portion is first side when the terahertz element is located in a plan view. 5. The terahertz device according to any of appendices 2 to 5, extending along a direction opposite to the direction.
[Supplementary Note 9]
The semiconductor device further comprises a support on which the semiconductor substrate is disposed,
The terahertz element and a first wire bonded to the support, further comprising:
The terahertz device according to claim 8, wherein the first wire is formed to avoid an imaginary straight line extending along the first conductive portion in a plan view.
[Supplementary Note 10]
The terahertz element and a second wire bonded to the support, further comprising:
The terahertz device according to claim 9, wherein the second wire is formed avoiding the virtual straight line in a plan view.
[Supplementary Note 11]
The terahertz device according to Appendix 9 or 10, wherein the first rectifying element and the second rectifying element are disposed on opposite sides of the virtual straight line in plan view.
[Supplementary Note 12]
The support includes a first conductive element and a second conductive element insulated from each other,
The terahertz device and the first rectifying element are disposed in the first conductive element, and the second rectifying element is disposed in the second conductive element. Terahertz device.
[Supplementary Note 13]
The first conductive element includes a first portion, and a second portion extending from the first portion toward the second conductive element,
The terahertz device according to claim 12, wherein the terahertz device is disposed at the second portion of the first conductive element.
[Supplementary Note 14]
15. The terahertz device according to appendix 13, wherein the first rectifying element is arranged at the second portion of the first conductive element.
[Supplementary Note 15]
The terahertz device according to Appendix 13 or 14, wherein the second conductive element includes a portion facing the first portion, and the second rectifying element is disposed at the portion in the second conductive element.
[Supplementary Note 16]
A resin portion in which a space surrounding the terahertz element is formed;
A member disposed in the resin portion and exposed to the air gap;
15. The terahertz device according to any one of appendices 1 to 15, wherein the space is filled with a gas.
[Supplementary Note 17]
The member includes a first portion disposed in the resin portion and a second portion disposed in the first portion,
The terahertz device according to claim 16, wherein the second portion is made of a conductive material.
[Supplementary Note 18]
20. The terahertz device of paragraph 17, wherein the second portion comprises at least one band portion, at least one annular portion, and / or at least one dot.

Claims (18)

  1. 　半導体基板と、
    　前記半導体基板上に配置されたテラヘルツ素子と、
    　前記テラヘルツ素子と電気的に並列接続された第１整流素子と、を備える、テラヘルツ装置。     A semiconductor substrate,
    A terahertz element disposed on the semiconductor substrate;
    A terahertz device, comprising: a first rectifying element electrically connected in parallel to the terahertz element.
  2. 　前記テラヘルツ素子と前記第１整流素子とのいずれにも電気的に並列接続された第２整流素子を更に備える、請求項１に記載のテラヘルツ装置。 The terahertz device according to claim 1, further comprising a second rectifying device electrically connected in parallel to both the terahertz device and the first rectifying device.
  3. 　前記第１整流素子および前記第２整流素子は各々、第１端子および第２端子を含み、前記第１整流素子および前記第２整流素子の各々において、前記第１端子から前記第２端子に向かう電気的な方向が順方向であり、
    　前記第１整流素子の前記第１端子は、前記第２整流素子の前記第２端子に導通している、請求項２に記載のテラヘルツ装置。     Each of the first and second rectifying elements includes a first terminal and a second terminal, and in each of the first and second rectifying elements, the first terminal is directed to the second terminal. The electrical direction is forward,
    The terahertz device according to claim 2, wherein the first terminal of the first rectifying element is electrically connected to the second terminal of the second rectifying element.
  4. 　前記第１整流素子は、第１立ち上がり電圧値および第１降伏電圧値を有し、前記第２整流素子は、第２立ち上がり電圧値および第２降伏電圧値を有し、
    　前記第１立ち上がり電圧値の絶対値は、前記第１降伏電圧値の絶対値よりも小さく、
    　前記第２立ち上がり電圧値の絶対値は、前記第２降伏電圧値の絶対値よりも小さく、
    　前記第１立ち上がり電圧値および前記第２立ち上がり電圧値は、前記テラヘルツ素子がテラヘルツ波を発振する電圧領域における値の絶対値の下限よりも、大きい、請求項２または請求項３に記載のテラヘルツ装置。     The first rectifying device has a first rising voltage value and a first breakdown voltage value, and the second rectifying device has a second rising voltage value and a second breakdown voltage value.
    The absolute value of the first rising voltage value is smaller than the absolute value of the first breakdown voltage value,
    The absolute value of the second rising voltage value is smaller than the absolute value of the second breakdown voltage value,
    The terahertz device according to claim 2 or 3, wherein the first rising voltage value and the second rising voltage value are larger than the lower limit of the absolute value of the value in the voltage range where the terahertz element oscillates the terahertz wave. .
  5. 　前記第１立ち上がり電圧値および前記第２立ち上がり電圧値は、前記テラヘルツ素子がテラヘルツ波を発振する電圧領域における値の絶対値の上限よりも、大きい、請求項４に記載のテラヘルツ装置。 The terahertz device according to claim 4, wherein the first rising voltage value and the second rising voltage value are larger than an upper limit of an absolute value of values in a voltage region where the terahertz element oscillates a terahertz wave.
  6. 　前記半導体基板上に各々形成され、互いに絶縁された第１導電体層および第２導電体層を更に備え、
    　前記第１整流素子および前記第２整流素子はいずれも、前記半導体基板上に形成され、且つ、前記第１導電体層および前記第２導電体層の間に電気的に介在している、請求項２ないし請求項５のいずれかに記載のテラヘルツ装置。     The semiconductor device further comprises a first conductor layer and a second conductor layer which are respectively formed on the semiconductor substrate and insulated from each other.
    The first rectifier element and the second rectifier element are both formed on the semiconductor substrate, and are electrically interposed between the first conductor layer and the second conductor layer. A terahertz device according to any one of claims 2 to 5.
  7. 　前記半導体基板上に各々形成され、且つ、互いに積層された第１半導体層および第２半導体層を更に備え、
    　前記第１半導体層は、第１導電型を有し、前記第２半導体層は、前記第１導電型とは反対の第２導電型を有し、
    　前記第１整流素子の前記第１端子と、前記第２整流素子の前記第２端子とは、前記第１導電体層によって構成され、
    　前記第１整流素子の前記第２端子と、前記第２整流素子の前記第１端子とは、前記第２導電体層によって構成されている、請求項６に記載のテラヘルツ装置。     The semiconductor device further includes a first semiconductor layer and a second semiconductor layer formed on the semiconductor substrate and stacked on each other.
    The first semiconductor layer has a first conductivity type, and the second semiconductor layer has a second conductivity type opposite to the first conductivity type.
    The first terminal of the first rectifying element and the second terminal of the second rectifying element are constituted by the first conductive layer,
    The terahertz device according to claim 6, wherein the second terminal of the first rectifying element and the first terminal of the second rectifying element are configured by the second conductive layer.
  8. 　互いに絶縁された第１導電部位および第２導電部位を更に備え、
    　前記テラヘルツ素子は、前記第１導電部位および前記第２導電部位の間に電気的に介在しており、
    　前記第１導電部位は、平面視において、前記テラヘルツ素子の位置する側から第１方向に沿って延びており、前記第２導電部位は、平面視において、前記テラヘルツ素子の位置する側から第１方向とは反対方向に沿って延びている、請求項２ないし請求項５のいずれかに記載のテラヘルツ装置。
    Further comprising first and second conductive portions insulated from each other;
    The terahertz element is electrically interposed between the first conductive site and the second conductive site,
    The first conductive portion extends in the first direction from the side where the terahertz element is located in a plan view, and the second conductive portion is first side when the terahertz element is located in a plan view. The terahertz device according to any one of claims 2 to 5, extending along a direction opposite to the direction.
  9. 　前記半導体基板が配置された支持体を更に備え、
    　前記テラヘルツ素子および前記支持体に接合された第１ワイヤを更に備え、
    　前記第１ワイヤは、平面視において、前記第１導電部位に沿って延びる仮想直線を避けて形成されている、請求項８に記載のテラヘルツ装置。     The semiconductor device further comprises a support on which the semiconductor substrate is disposed,
    The terahertz element and a first wire bonded to the support, further comprising:
    The terahertz device according to claim 8, wherein the first wire is formed to avoid an imaginary straight line extending along the first conductive portion in a plan view.
  10. 　前記テラヘルツ素子および前記支持体に接合された第２ワイヤを更に備え、
    　前記第２ワイヤは、平面視において、前記仮想直線を避けて形成されている、請求項９に記載のテラヘルツ装置。     The terahertz element and a second wire bonded to the support, further comprising:
    The terahertz device according to claim 9, wherein the second wire is formed to avoid the virtual straight line in a plan view.
  11. 　前記第１整流素子および前記第２整流素子は、平面視において、前記仮想直線を挟んで互いに反対側に配置されている、請求項９または請求項１０に記載のテラヘルツ装置。 The terahertz device according to claim 9, wherein the first rectifying element and the second rectifying element are disposed on opposite sides of the virtual straight line in a plan view.
  12. 　前記支持体は、互いに絶縁された第１導電エレメントおよび第２導電エレメントを含み、
    　前記テラヘルツ装置および前記第１整流素子は、前記第１導電エレメントに配置されており、前記第２整流素子は、前記第２導電エレメントに配置されている、請求項８ないし請求項１１のいずれかに記載のテラヘルツ装置。     The support includes a first conductive element and a second conductive element insulated from each other,
    12. The terahertz device and the first rectifying element are disposed in the first conductive element, and the second rectifying element is disposed in the second conductive element. The terahertz device described in.
  13. 　前記第１導電エレメントは、第１部位と、前記第２導電エレメントに向かって前記第１部位から延び出る第２部位と、を含み、
    　前記テラヘルツ装置は、前記第１導電エレメントにおける前記第２部位に配置されている、請求項１２に記載のテラヘルツ装置。     The first conductive element includes a first portion, and a second portion extending from the first portion toward the second conductive element,
    The terahertz device according to claim 12, wherein the terahertz device is disposed at the second portion of the first conductive element.
  14. 　前記第１整流素子は、前記第１導電エレメントの前記第２部位に配置されている、請求項１３に記載のテラヘルツ装置。 The terahertz device according to claim 13, wherein the first rectifying element is disposed at the second portion of the first conductive element.
  15. 　前記第２導電エレメントは、前記第１部位に対向する部位を含み、前記第２整流素子は、前記第２導電エレメントにおける前記部位に配置されている、請求項１３または請求項１４に記載のテラヘルツ装置。 The terahertz wave according to claim 13 or 14, wherein the second conductive element includes a portion facing the first portion, and the second rectifying element is disposed at the portion in the second conductive element. apparatus.
  16. 　前記テラヘルツ素子を包囲する空間が形成された樹脂部と、
    　前記樹脂部に配置され、前記空隙に露出した部材と、を更に備え、
    　前記空間には、気体が充填されている、請求項１ないし請求項１５のいずれかに記載のテラヘルツ装置。     A resin portion in which a space surrounding the terahertz element is formed;
    A member disposed in the resin portion and exposed to the air gap;
    The terahertz device according to any one of claims 1 to 15, wherein the space is filled with a gas.
  17. 　前記部材は、前記樹脂部に配置された第１部分と、前記第１部分に配置された第２部分と、を含み、
    　前記第２部分は、導電材料よりなる、請求項１６に記載のテラヘルツ装置。     The member includes a first portion disposed in the resin portion and a second portion disposed in the first portion,
    The terahertz device according to claim 16, wherein the second portion is made of a conductive material.
  18. 　前記第２部分は、少なくとも１つの帯状部分、少なくとも１つの環状部分、および少なくとも１つのドットの少なくともいずれかを含む、請求項１７に記載のテラヘルツ装置。 18. The terahertz device of claim 17, wherein the second portion comprises at least one band portion, at least one annular portion, and / or at least one dot.
PCT/JP2018/036842 2017-10-18 2018-10-02 Terahertz device WO2019077994A1 (en)

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