WO2019057052A1 - 电容阵列、逐次逼近型模数转换器以及电容阵列板 - Google Patents
电容阵列、逐次逼近型模数转换器以及电容阵列板 Download PDFInfo
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- WO2019057052A1 WO2019057052A1 PCT/CN2018/106387 CN2018106387W WO2019057052A1 WO 2019057052 A1 WO2019057052 A1 WO 2019057052A1 CN 2018106387 W CN2018106387 W CN 2018106387W WO 2019057052 A1 WO2019057052 A1 WO 2019057052A1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M1/687—Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
- H03M1/80—Simultaneous conversion using weighted impedances
- H03M1/802—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices
- H03M1/804—Simultaneous conversion using weighted impedances using capacitors, e.g. neuron-mos transistors, charge coupled devices with charge redistribution
Definitions
- the present application relates to the field of semiconductor integrated circuits, and in particular, to a capacitor array, a successive approximation analog-to-digital converter, and a capacitor array board.
- SAR ADC The full name of SAR ADC is a successive approximation analog-to-digital converter, which is one of the most popular low-power analog-to-digital converters.
- SAR One of the core modules of the ADC is a CDAC-digital-to-analog converter capacitor array; SAR As a key component of the interface between the analog module and the digital module, the ADC is widely used in mobile devices, wireless sensors and other devices. Due to the volume problem and battery life of the device, the analog-to-digital converter is required to have small size and low power consumption. Easy to integrate in the circuits of various devices.
- an ADC converting an analog signal to a digital signal is done in four steps: sample, hold, quantize, and encode. This step of quantification is done by CDAC.
- CDAC CDAC
- an LSB of a digital code corresponds to an analog signal of 1 mV size, and 0 mV corresponds to 00000, that is, 1 mV corresponds to 00001, 2 mV corresponds to 00010, 3 mV corresponds to 00011, ... 16 mV corresponds to 10000, and 31 mV corresponds to 11111.
- the abscissa is an analog signal XX mV
- the ordinate is the digital code YYYYY, which connects the points corresponding to each horizontal and vertical coordinate. This line represents the linearity.
- the main purpose of the present application is to propose a capacitor array for an analog-to-digital converter, a successive approximation analog-to-digital converter, and a capacitor array board, which are intended to improve the conversion accuracy of an analog-to-digital converter.
- the present application provides a capacitor array for an analog-to-digital converter, the capacitor array including a control logic generating circuit, a control code logic conversion circuit, a first sub-capacitor array for composing different high and low segment bits, and Second sub-capacitor array;
- the first sub-capacitor array includes a plurality of first capacitor units and a plurality of first switches.
- the plurality of first capacitor units are sequentially disposed from a low level to a high level in a capacitance and a binary weight manner, and the plurality of the first capacitor units are mutually a parallel relationship; each of the first capacitor units is connected to the control logic generating circuit via a first switch; the control logic generating circuit outputs a first binary code corresponding to the first sub-capacitor array Depressing a first switch to control a switching state of the first switch;
- the second sub-capacitor array includes a plurality of second capacitor units sequentially connected in parallel and a plurality of second switches, each of the second capacitor units being connected to the control code logic conversion circuit via a first switch, a control code logic conversion circuit is coupled to the control logic generation circuit; the capacitance of the second capacitance unit is equal;
- the control logic generating circuit outputs a second binary code corresponding to the second sub-capacitor array, and the control code logic converting circuit converts the second binary code into a thermometer code, and outputs the second binary code to the second switch. To control the switching state of the second switch.
- the first sub-capacitor array is a low-level capacitor array
- the second sub-capacitor array is a high-level capacitor array
- the capacitance of the lowest-position second capacitor unit is twice the maximum capacitance in the first capacitor unit.
- the first sub-capacitor array and the second sub-capacitor array are sequentially connected in parallel; the corresponding binary code of the first capacitor unit and the second capacitor unit has M bits, and the first capacitor
- the sum of the capacitances of the unit and the second capacitor unit is 2 M -1 unit capacitance; the number of the first capacitor units is N, and the total capacitance of the first capacitor unit is 2 N -1 times unit capacitance
- the number of the second capacitor units is 2 MN -1 , and the total capacitance of the second capacitor unit is 2 M -2 N times unit capacitance.
- the number of the second capacitor units is 15, 31, or 63.
- the first sub-capacitor array has two first capacitor units, and the second sub-capacitor array has 31 second capacitor units.
- the present application also proposes a successive approximation analog-to-digital converter comprising a comparator, a register connected to the output of the comparator, and a capacitor array of the analog-to-digital converter;
- a capacitor array of the analog to digital converter is coupled to an input of the comparator.
- the digital signal output by the successive approximation analog-to-digital converter is 12 bits, and the 12-bit digital signal is divided into a high 7 bits and a lower five bits;
- the capacitor array corresponding to the high seven digit digital signal is the capacitor array for the analog to digital converter.
- the present application further provides a capacitor array board, wherein the capacitor array board is provided with the second sub-capacitor array for the capacitor array of the analog-to-digital converter;
- the capacitor array board includes a substrate having a plurality of second capacitor units of the second sub-capacitor array sequentially arranged in a lateral direction; each of the second capacitor units includes four serially connected capacitors in a longitudinal direction a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor that are 1 unit capacitance;
- the upper plate of the first capacitor of the second capacitor unit is connected in series, the second switch of the second sub-capacitor array is disposed in one-to-one correspondence with the second capacitor unit, and the first capacitor and the second capacitor are respectively arranged
- the third capacitor and the lower plate of the fourth capacitor are electrically connected to the corresponding second switch.
- the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor of each of the second capacitor units are arranged in a straight line with the corresponding second switch; and the plurality of the second capacitor units are arranged in parallel On the substrate.
- the control code logic conversion circuit outputs a corresponding thermometer code, and controls a corresponding second switch to switch. Regardless of which bit jumps in the thermometer code, no matter which bit of the second binary code is hopped, a large number of second capacitor units are not switched together, so that no large conversion error is caused. Further, in view of the fact that there are many parallel branches in the second sub-capacitor array, the technical solution of the present application adopts a setting method using a segmented capacitor array, wherein the capacitance setting of the first capacitor unit in the first sub-capacitor array adopts binary weighting.
- FIG. 1 is a block diagram of a capacitor array control for an analog-to-digital converter of the present application
- FIG. 2 is a schematic diagram showing the conversion of the control code logic conversion circuit of FIG. 2;
- Figure 3 is a map of a 5-digit second binary code and a thermometer code
- FIG. 5 is a schematic diagram of physical simulation of the capacitor array version of FIG. 4.
- the directional indication is only used to explain in a certain posture (as shown in the drawing)
- first”, “second”, etc. in the embodiments of the present application, the description of "first”, “second”, etc. is used for descriptive purposes only, and is not to be construed as an Its relative importance or implicit indication of the number of technical features indicated.
- features defining “first” and “second” may include at least one of the features, either explicitly or implicitly.
- the technical solutions between the various embodiments may be combined with each other, but must be based on the realization of those skilled in the art, and when the combination of the technical solutions is contradictory or impossible to implement, it should be considered that the combination of the technical solutions does not exist. Nor is it within the scope of protection required by this application.
- the present application proposes a capacitor array for an analog-to-digital converter for successive approximation of an analog-to-digital converter; the digital-to-analog converter plays a key role in divising the reference voltage.
- the pure capacitance type digital-to-analog converter is widely used because of its low noise and high production precision.
- most of the conventional digital-to-analog converter capacitor arrays use a binary weighted capacitor array, that is, the adjacent high-order capacitor is twice the capacitance of the low-level capacitor; therefore, the binary control code jumps from 0111111 to 1000000 or jumps from 0011111.
- this application proposes a simple and effective method to eliminate the switching error of the digital-to-analog converter capacitor array caused by the process deviation from the mathematical level, mainly by re-coding the control code of the digital-to-analog converter capacitor array, so that the CDAC When the control code jumps at any position, it will not cause a large number of capacitor arrays to switch, which will only cause a corresponding unit capacitor to be switched, so as not to cause large conversion errors.
- the function of the digital-to-analog converter capacitor array is to correspond the digital code to an analog signal through the switching of the capacitor array.
- the capacitor array is a binary-weighted capacitor array to illustrate the correspondence between the digital code and the capacitor array switching: 5-bit binary
- the control code XXXXX has five parallel branches, and the capacitances of the five parallel branches are set in a binary weighted manner.
- the leftmost high bit controls the switching of 16 unit capacitors
- the rightmost low bit controls the switching of one unit capacitor
- 0 and 1 indicate whether the corresponding controlled unit capacitor array is switched.
- the digital code is 10000, it indicates the highest bit control.
- the 16 unit capacitors are switched, and the remaining capacitors are not switched; if the digital code is 01111, the 16-unit capacitor controlled by the highest bit does not switch, and the remaining 8 + 4 + 2 + 1 unit capacitors are switched.
- the capacitor array proposed by the present application includes a control logic generating circuit 30, a control code logic converting circuit 40, a first sub-capacitor array 10 and a second sub-capacitor array 20 for composing different levels of high and low segments;
- the first sub-capacitor array 10 includes a plurality of first capacitor units 11 and a plurality of first switches 12, and the plurality of first capacitor units 11 are sequentially disposed from a low level to a high level in a capacitance and a binary weighting manner, and the plurality of first capacitors are sequentially disposed.
- the units 11 are in parallel relationship with each other; each of the first capacitor units 11 is connected to the control logic generating circuit 30 via a first switch 12; the control logic generating circuit 30 corresponds to the output of the first sub-capacitor array 10.
- a first binary code to the first switch 12 to control a switching state of the first switch 12;
- the second sub-capacitor array 20 includes a plurality of second capacitor units 21 and a plurality of second in parallel a switch 22, each of the second capacitor units 21 is connected to the control code logic conversion circuit 40 via a first switch 12, and the control code logic conversion circuit 40 is connected to the control logic generating circuit 30;
- First The capacitances of the two capacitor units 21 are all equal;
- the control logic generating circuit 30 outputs a second binary code corresponding to the second sub-capacitor array 20, and the control code logic converting circuit 40 converts the second binary code After the thermometer code is output to the second switch 22 to control the switching state of the second switch 22;
- the control code logic conversion circuit 40 output
- the switching of the second capacitor unit 21 herein refers to the switching between the closing/opening of the second switch 22 corresponding to the second capacitor unit 21.
- the lower plate of the two capacitor unit 21 is connected to the analog signal input terminal or the reference signal input terminal, thereby causing a change in the state of the second capacitor unit 21, where the state change of the second capacitor unit 21 is referred to as Switching of the two capacitor units 21.
- the switching of the first capacitor unit 11 here also has a similar process, which is not described here.
- the upper plates of all the capacitors in the first sub-capacitor array 10 and the second sub-capacitor array 20 are connected to the comparator through a control switch, and the first capacitor in the first sub-capacitor array 10
- the lower plate of the unit 11 is connected to the reference voltage or ground through the first switch 12. It will be understood by those skilled in the art that when the first switch 12 is closed or opened, the representative 0 or 1 is relative, and the conversion result is not There will be an impact.
- the lower plate of the second capacitor unit 21 in the second sub-capacitor array 20 is connected to the reference voltage, the analog signal input terminal or the ground through the second switch 22.
- the control logic generating circuit 30 is configured to control states of the first switch 12 and the second switch 22 to cause the capacitor array to complete a process of charge redistribution.
- the first switch 12 controls whether the first capacitor unit 11 of the branch is switched.
- the first sub-capacitor array 10 has five parallel branches as an example.
- the parallel branches respectively have a first switch 12 and a first capacitor unit 11, when the control logic generating circuit 30 outputs the first binary code, and when a certain position of the first binary code is 1, The state of the first switch 12 corresponding to the bit is changed, and the first capacitor unit 11 corresponding to the first switch 12 is switched. Since the first capacitor unit 11 in the first sub-capacitor array 10 is set as a binary weighted capacitor, the weights corresponding to each of the first capacitor units 11 are different, that is, when the first binary code is in binary mode. A jump is performed to change the state of the first switch 12 corresponding to the jump position.
- the second switch 22 controls whether the second capacitor unit 21 of the branch is switched.
- the second sub-capacitor array 20 has five parallel branches as an example.
- the parallel branches respectively have a second switch 22 and a second capacitor unit 21.
- the weights corresponding to each of the second capacitor units 21 are the same, so when the control logic generating circuit 30 outputs the first Each of the two binary codes is incremented, and the corresponding thermometer code is outputted by the control code logic conversion circuit 40, so that the second capacitor unit 21 in the second sub-capacitor array 20 is also switched in sequence; Therefore, no matter which bit of the second binary code is hopped, a large number of second capacitor units 21 are not switched together.
- the first sub-capacitor array 10 is controlled by the first binary code.
- the second sub-capacitor array 20 is controlled by a thermometer code; in order to improve the compatibility of the capacitor array of the technical solution of the present application, the capacitor array can be adapted to an existing control logic generating circuit that performs control code design according to a binary encoding manner. 30. Therefore, setting the capacitor array for the analog-to-digital converter further includes a control code logic conversion circuit 40; so that the control code logic generation circuit outputs the second second for controlling the second sub-capacitor array 20 according to the binary code output.
- the hexadecimal code, and further the second binary code is converted into the thermometer code by the control code logic conversion circuit 40, thereby controlling the second sub-capacitor array 20.
- the 31-digit thermometer code is S30, S29, S28, S27, ..., S0 from high to low respectively; as can be seen from the figure, each time the thermometer code is added, only one control bit changes, That is, the state of only one second switch 22 is changed, and a second capacitor unit 21 is switched.
- the second capacitor unit 21 of the second capacitor array is sequentially switched from the low position to the high level.
- the second capacitor unit 21 of the lowest bit switches, and when 00000 jumps to 00010, the second capacitor unit 21 of the lower two bits. Switching, ... When 00000 jumps to 10000, the lower sixteen-bit second capacitor unit 21 switches, and when 00000 jumps to 10001, the lower seventeen switches the second capacitor unit 21.
- the technical solution of the present application sets the second sub-capacitor array 20, and the capacitance settings of the second capacitor unit 21 are all equal, the control code logic conversion circuit 40 outputs a corresponding thermometer code, and controls the corresponding second switch 22 to switch. In order to make the thermometer code jump regardless of which bit, the second capacitor unit 21 is not switched together, so that no large conversion error is caused. Further, in view of the fact that there are many parallel branches in the second sub-capacitor array 20, the technical solution of the present application adopts a setting mode using a segmented capacitor array, wherein the capacitance setting of the first capacitor unit 11 in the first sub-capacitor array 10 is adopted.
- Binary-weighted setting method avoiding the problem that the number of parallel branches caused by using the second sub-capacitor array 20 is large; the technical solution of the present application is based on the premise that the analog-to-digital converter outputs the same number of bits compared with the prior art.
- the conversion error of the capacitor array is effectively reduced, and the conversion precision of the analog-to-digital converter is improved.
- the technical solution of the present application can properly set the number of the second capacitor units 21 to balance the conversion precision of the analog-to-digital converter and the parallel branch of the capacitor array.
- the second capacitor The number of the units 21 is 31, 15 or 63
- the thermometer codes correspond to 31 bits, 15 bits, and 63 bits, respectively
- the corresponding second binary code corresponding to the output of the control logic generating circuit 30 is 5. Bit, 4 bits, 6 bits.
- the first sub-capacitor array 10 is set as a low-level capacitor array; the second sub-capacitor array 20 is a high-level capacitor array; to utilize the second sub-capacitor array 20 to only affect one when the thermometer code jumps
- the switching of the second capacitance unit 21 is therefore set at a high level to reduce the interference of noise to the capacitance jump by reducing the number of capacitance switching.
- the capacitance of the second capacitor unit 21 that sets the lowest bit is twice the maximum capacitance in the first capacitor unit 11.
- the first sub-capacitor array 10 and the second sub-capacitor array 20 are sequentially connected in parallel; the corresponding binary code of the first capacitor unit and the second capacitor unit has M bits, and the first capacitor unit and The sum of the capacitances of the second capacitor unit is 2 M -1 times unit capacitance; the number of the first capacitor units is N, and the total capacitance of the first capacitor unit is 2 N -1 times unit capacitance; The number of the second capacitor units is 2 MN -1 , and the total capacitance of the second capacitor unit is 2 M -2 N times unit capacitance.
- the usual analog-to-digital converter structure the high 7-bit precision is often less than ideal, and it is also one of the biggest limiting factors of the current analog-to-digital converter performance;
- set the SAR The capacitor array corresponding to the digital output (binary) of the 7-bit high ADC is the capacitor array for the analog-to-digital converter proposed in the present application, and the second sub-capacitor array 20 is disposed corresponding to the 7-bit digital quantity.
- the present application also proposes a successive approximation analog-to-digital converter comprising a comparator, a register connected to the output of the comparator, and the capacitor array for the analog-to-digital converter; A capacitor array of the analog to digital converter is coupled to the input of the comparator.
- the approximate working process of the successive approximation analog-to-digital converter is given: first, the analog input signal is sampled and held, and sent to one end of the comparator, and then the control logic generating circuit 30 presets the highest bit of the register to 1, other bits. All cleared, the analog-to-digital converter is fed to the other end of the comparator by one-half of the output reference voltage under the control of the reference voltage and the register. If the analog input signal voltage is greater than one-half of the reference voltage, the comparator output is 1 and the highest register bit is set to 1; otherwise, if the analog input signal voltage is less than one-half of the reference voltage, the comparator output is 0, register The highest bit is set to 0.
- the highest bit of the successive approximation analog-to-digital converter is determined; and then the next highest bit is determined, that is, the second highest bit of the pre-register is 1; if the most significant bit determined by the previous conversion cycle is 1, then the modulus is The converter outputs three-quarters of the reference voltage. The analog input signal voltage is compared with three-quarters of the reference voltage to determine the second highest register. If the most significant bit determined by the previous conversion cycle is 0, then the modulus is The converter outputs a quarter of the reference voltage, and the analog input signal voltage is compared to a quarter of the reference voltage to determine the second highest register. And so on, until the lowest bit of the register is determined, the value of such a register is the final output of the successive approximation analog-to-digital converter.
- the present application further provides a capacitor array board, wherein the capacitor array board is provided with the second sub-capacitor array 20 for a capacitor array of an analog-to-digital converter; the capacitor array board includes a substrate a plurality of second capacitor units 21 of the second sub-capacitor array 20 sequentially arranged in the lateral direction; each of the second capacitor units 21 includes four serially connected in series and having a capacitance of 1 time.
- first capacitor, a second capacitor, a third capacitor, and a fourth capacitor of the unit capacitor an upper plate of the first capacitor of each of the second capacitor units 21 is connected in series, and a second switch of the second sub-capacitor array 20 22 is disposed in one-to-one correspondence with the second capacitor unit 21, and the lower plates of the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are electrically connected to the corresponding second switch 22.
- the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor of each of the second capacitor units 21 are aligned in a line with the second switch 22 corresponding thereto and the plurality of the second capacitor units 21 are parallel. Arranged on the substrate.
- FIG. 5 is a schematic diagram of physical simulation of the capacitor array version of FIG. 4, wherein FIG. 4 has at least 31 columns of capacitor groups, and the middle 4 of each column of capacitor groups are connected in parallel to form the second capacitor unit 21, Each column of capacitors corresponds to a switch. It can be seen that, due to the capacitor array of the technical solution of the present application, the layout of the original analog-to-digital converter capacitor array is replaced by a complicated switch control network, and the capacitor array of the present application has a capacitor. The traces between the lines are simple, so the parasitic capacitance of the traces can be greatly reduced, thereby further improving the conversion accuracy of the analog-to-digital converter.
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Abstract
本申请公开一种用于模数转换器的电容阵列、逐次逼近型模数转换器以及电容阵列板。所述用于模数转换器的电容阵列包括控制逻辑产生电路、控制码逻辑转换电路、用于组成高低不同段位的第一子电容阵列和第二子电容阵列;本申请技术方案通过设第二电容单元的电容量设置均相等,以使所述第二子电容阵列中的第二电容单元也依次对应进行切换;因此无论第二二进制码在哪一位进行跳变,都不会造成大量第二电容单元一同切换,从而不会引起大的转换误差。进一步地,本申请技术方案采用采用分段电容阵列的设置方式,避免了全部使用第二子电容阵列所造成并联分支数量较多的问题。
Description
技术领域
本申请涉及半导体集成电路领域,特别涉及一种电容阵列、逐次逼近型模数转换器以及电容阵列板。
背景技术
SAR ADC的全称是逐次逼近型模数转换器,是一种当前最为主流的低功耗模数转换器。SAR
ADC其中的一个核心模块CDAC—数模转换器电容阵列;SAR
ADC作为模拟模块和数字模块之间接口的关键部件,广泛应用于移动设备、无线传感器等设备中,由于设备的体积问题以及续航问题,要求模数转换器具有体积小,低功耗的特点,便于集成在各种设备的电路中。由于工艺的限制,CDAC的失配与误差反比于CDAC的面积,这会导致SAR
ADC的转换精度和转换速度之间相互制约,这是限制SAR
ADC性能的一个主要因素。特别是进入28nm工艺之后,这种失配和误差变得更加严重,工程师们需要花费较大的代价去降低它对ADC(模数转换器)性能的影响。
具体地,对于一个ADC来说,将一个模拟信号转换为数字信号分为4步完成:采样,保持,量化,编码。而量化这一步骤由CDAC来完成。为方便理解,在此举例说明,例如一个数字码的LSB对应1mV大小的模拟信号,而0mV对应00000,即1mV对应00001,2mV对应00010,3mV对应00011,……16mV对应10000,31mV对应11111。如果横坐标是模拟信号XX
mV,纵坐标是数字码YYYYY,将每个横纵坐标对应的点连起来,这条线就代表着线性度。
CDAC对SAR
ADC的转换精度的影响主要通过以下方式体现:当CDAC的二进制控制码从0111111跳变到1000000或者是从0011111跳变到0100000时,这些情况下只是一个LSB(最低有效位)的变化,却会导致大量(2的N次方个,N取决于跳变的位)单位电容的切换,因此会在0111111跳变至1000000,X011111跳变至X100000,XX01111跳变至XX10000等类似的情况,会导致大量单位电容切换,(具体表现为0111111到1000000会导致127个单位电容切换,X011111到X1000000会导致63个单位电容切换),而越多的单位电容切换则会导致引入更多的误差,导致转换过程产生非线性,从而造成转换误差,进而影响SAR
ADC的转换精度。
对于CDAC的失配与误差当前主要的解决路径包括2种,一种是工程师根据自己的经验通过优秀的版图设计来降低整体的失配和误差,但这种办法本质上无法改变工艺误差对ADC转换精度的影响,因此效果不明显;另一种是通过数字后端校准,测量出失配和误差后,再经过数字后端将非线性校准回去,这种方法实现起来非常复杂,需要消耗大量的数字电路,同时测量的精度亦很难保证。
发明内容
本申请的主要目的是提出一种用于模数转换器的电容阵列、逐次逼近型模数转换器以及电容阵列板,旨在提高模数转换器的转换精度。
为实现上述目的,本申请提出的一种用于模数转换器的电容阵列,所述电容阵列包括控制逻辑产生电路、控制码逻辑转换电路、用于组成高低不同段位的第一子电容阵列和第二子电容阵列;
所述第一子电容阵列包括多个第一电容单元以及多个第一开关,多个第一电容单元按电容量及二进制加权方式由低位到高位依次设置,多个所述第一电容单元互为并联关系;每所述第一电容单元经一所述第一开关与所述控制逻辑产生电路连接;所述控制逻辑产生电路对应所述第一子电容阵列输出第一二进制码至所述第一开关,以控制所述第一开关的切换状态;
所述第二子电容阵列包括多个依次并联的第二电容单元以及多个第二开关,每所述第二电容单元经一所述第一开关与所述控制码逻辑转换电路连接,所述控制码逻辑转换电路与所述控制逻辑产生电路连接;所述第二电容单元的电容量均相等;
所述控制逻辑产生电路对应第二子电容阵列输出第二二进制码,所述控制码逻辑转换电路将所述第二二进制码转换为温度计码后,输出至所述第二开关,以控制所述第二开关的切换状态。
可选地,所述第一子电容阵列为低位电容阵列;所述第二子电容阵列为高位电容阵列;
最低位的第二电容单元的电容量是第一电容单元中最大电容量的两倍。
可选地,所述第一子电容阵列与第二子电容阵列依次并联;所述第一电容单元和第二电容单元的所对应的二进制码的位数为M位,且所述第一电容单元和第二电容单元的电容量之和为2M-1倍单位电容;所述第一电容单元的数量为N个,所述第一电容单元的总容值为2N-1倍单位电容;所述第二电容单元的数量有2M-N-1个,且所述第二电容单元的总容值为2M-2N倍单位电容。
可选地,所述第二电容单元的数量为15个、31个、或63个。
可选地,所述第一子电容阵列有2个第一电容单元,所述第二子电容阵列有31个第二电容单元。
本申请还提出一种逐次逼近型模数转换器,包括比较器、连接于所述比较器输出端的寄存器以及所述模数转换器的电容阵列;
所述模数转换器的电容阵列与所述比较器的输入端连接。
可选地,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;
所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
本申请还提出一种电容阵列板,所述电容阵列板上设有所述的用于模数转换器的电容阵列的第二子电容阵列;
所述电容阵列板包括基板,所述基板上具有依次沿横向排列的所述第二子电容阵列的多个第二电容单元;每所述第二电容单元包括4个沿纵向依次串联且电容量均为1倍单位电容的第一电容、第二电容、第三电容、以及第四电容;
每所述第二电容单元的第一电容的上极板串联,所述第二子电容阵列的第二开关与所述第二电容单元一一对应设置,且所述第一电容、第二电容、第三电容、以及第四电容的下极板与其对应的第二开关电连接。
可选地,每所述第二电容单元的第一电容、第二电容、第三电容、以及第四电容与其对应的第二开关沿直线排列;且多个所述第二电容单元平行排布于所述基板上。
本申请技术方案通过设置第二子电容阵列,且所述第二电容单元的电容量设置均相等,所述控制码逻辑转换电路输出对应的温度计码,控制对应的第二开关切换,以使所述温度计码无论在哪一位跳变,因此无论第二二进制码在哪一位进行跳变,都不会造成大量第二电容单元一同切换,从而不会引起大的转换误差。进一步地,考虑到第二子电容阵列中并联分支较多,因此本申请技术方案采用采用分段电容阵列的设置方式,其中第一子电容阵列中第一电容单元的电容量设置采用二进制加权的设置方式;避免了全部使用第二子电容阵列所造成并联分支数量较多的问题;本申请技术方案与现有技术相比,在所述模数转换器输出相同位数的前提下,有效地减小了电容阵列的转换误差,提高了模数转换器的转换精度。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图示出的结构获得其他的附图。
图1为本申请用于模数转换器的电容阵列控制框图;
图2为图2中控制码逻辑转换电路的转换示意图;
图3为5位第二二进制码与温度计码的映射图;
图4为本申请电容阵列版的电路连接原理图;
图5为图4中电容阵列版的实物模拟示意图。
附图标号说明 :
标号 | 名称 | 标号 | 名称 |
10 | 第一子电容阵列 | 21 | 第二电容单元 |
11 | 第一电容单元 | 22 | 第一开关 |
12 | 第一开关 | 30 | 控制逻辑产生电路 |
20 | 第二子电容阵列 | 40 | 控制码逻辑转换电路 |
本申请目的的实现、功能特点及优点将结合实施例,参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请的一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。
需要说明,若本申请实施例中有涉及方向性指示(诸如上、下、左、右、前、后……),则该方向性指示仅用于解释在某一特定姿态(如附图所示)下各部件之间的相对位置关系、运动情况等,如果该特定姿态发生改变时,则该方向性指示也相应地随之改变。
另外,若本申请实施例中有涉及“第一”、“第二”等的描述,则该“第一”、“第二”等的描述仅用于描述目的,而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外,各个实施例之间的技术方案可以相互结合,但是必须是以本领域普通技术人员能够实现为基础,当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在,也不在本申请要求的保护范围之内。
本申请提出一种用于模数转换器的电容阵列,用于逐次逼近模数转换器;数模转换器起着将参考电压进行二分的关键性作用。纯电容型数模转换器因为其噪声小,制作精度高,而被广泛使用。目前传统的数模转换器电容阵列所用的大部分为二进制权重的电容阵列,即相邻高位电容是低位电容容值的两倍;因此在二进制控制码从0111111跳变到1000000或者是从0011111跳变到0100000时,这些情况下只是一个LSB(最低有效位)的变化,却会导致大量(2的N次方减1个,N取决于跳变的位)单位电容的切换。本申请基于此,提出一种简单有效的方法从数学层面消除工艺偏差导致的数模转换器电容阵列的切换误差,主要是通过重新对数模转换器电容阵列的控制码进行编码,使得CDAC的控制码在任意位置跳变的时候,都不会引起大量电容阵列的切换,只会引起一个对应单位电容的切换,从而不会引起大的转换误差。
数模转换器电容阵列的作用就是通过电容阵列的切换将数字码对应到一个模拟信号,在此以电容阵列为二进制加权电容阵列举例说明数字码与电容阵列切换的对应关系:以5位的二进制控制码XXXXX为例,电容阵列具有5条并联支路,所述5条并联支路上的电容量按照二进制加权方式设置。最左边的高位控制着16个单位电容的切换,最右边的低位控制着1个单位电容的切换,0和1表示对应控制的单位电容阵列是否切换,如果数字码为10000,则表示最高位控制的16个单位电容切换,余下的电容不切换;如果数字码为01111,最高位控制的16个单位电容不切换,剩下的8个+4个+2个+1个单位电容切换。
请参阅图1,本申请提出的所述电容阵列包括控制逻辑产生电路30、控制码逻辑转换电路40、用于组成高低不同段位的第一子电容阵列10和第二子电容阵列20;所述第一子电容阵列10包括多个第一电容单元11以及多个第一开关12,多个第一电容单元11按电容量及二进制加权方式由低位到高位依次设置,多个所述第一电容单元11互为并联关系;每所述第一电容单元11经一所述第一开关12与所述控制逻辑产生电路30连接;所述控制逻辑产生电路30对应所述第一子电容阵列10输出第一二进制码至所述第一开关12,以控制所述第一开关12的切换状态;所述第二子电容阵列20包括多个依次并联的第二电容单元21以及多个第二开关22,每所述第二电容单元21经一所述第一开关12与所述控制码逻辑转换电路40连接,所述控制码逻辑转换电路40与所述控制逻辑产生电路30连接;所述第二电容单元21的电容量均相等;所述控制逻辑产生电路30对应第二子电容阵列20输出第二二进制码,所述控制码逻辑转换电路40将所述第二二进制码转换为温度计码后,输出至所述第二开关22,以控制所述第二开关22的切换状态;所述控制码逻辑转换电路40输出对应的温度计码,控制对应的第二开关22切换,以使所述温度计码无论在哪一位跳变,都只会对应一个第二电容单元21进行切换。
本领域技术人员可以理解的是,在此所述第二电容单元21的切换是指当该第二电容单元21所对应的第二开关22进行闭合/断开之间的切换时,所述第二电容单元21的下极板会与模拟信号输入端或者参考信号输入端连接,因而会造成第二电容单元21的状态发生改变,在此将所述第二电容单元21的状态改变称作第二电容单元21的切换。在此对第一电容单元11的切换也具有类似过程,在此不赘述。
在一实施例中,所述第一子电容阵列10和第二子电容阵列20中的所有电容的上极板通过一控制开关与比较器连接,所述第一子电容阵列10中第一电容单元11的下极板通过第一开关12与参考电压或地连接,本领域技术人员可以理解的是,当第一开关12闭合或打开时,所代表0或1是相对的,对转换结果不会有影响。同样的,所述第二子电容阵列20中第二电容单元21的下极板通过第二开关22与参考电压、模拟信号输入端或地连接。所述控制逻辑产生电路30用于控制所述第一开关12和第二开关22的状态,以使所述电容阵列完成电荷再分配的过程。
在第一子电容阵列10中,所述第一开关12控制其所在支路第一电容单元11是否进行切换,在此以第一子电容阵列10有五条并联支路为例说明,所述五条并联支路分别对应有一第一开关12以及第一电容单元11,当所述控制逻辑产生电路30输出第一二进制码时,且当第一二进制码的某一位置1时,则表示该位所对应的第一开关12的状态发生改变,进而使得该第一开关12所对应的第一电容单元11发生切换。由于第一子电容阵列10中的第一电容单元11的设置为二进制加权电容,因此每个第一电容单元11对应的权值是不同的,即当所述第一二进制码按照二进制方式进行跳变,以改变跳变位所对应的第一开关12的状态。
在第二子电容阵列20中,所述第二开关22控制其所在支路第二电容单元21是否进行切换,在此以第二子电容阵列20有五条并联支路为例说明,所述五条并联支路分别对应有一第二开关22以及第二电容单元21,当所述控制逻辑产生电路30经过所述控制码逻辑转换电路40输出温度计码时,当该温度计码的某一位置1时,表示该位所对应的第二开关22的状态发生改变,进而使得该第二开关22所对应的第二电容单元21发生切换。由于所述第二子电容阵列20的第二电容单元21的电容量均相等,因此每个第二电容单元21所对应的权值是相同的,因此当所述控制逻辑产生电路30输出的第二二进制码每加一,所述控制码逻辑转换电路40输出对应的温度计码会依次置一,以使所述第二子电容阵列20中的第二电容单元21也依次对应进行切换;因此无论第二二进制码在哪一位进行跳变,都不会造成大量第二电容单元21一同切换。
请参阅图2,基于上述实施例可知,由于第一子电容阵列10和第二子电容阵列20的电容设置是不同的,所述第一子电容阵列10受第一二进制码控制,所述第二子电容阵列20受温度计码控制;为了提高本申请技术方案的电容阵列的可兼容性,使所述电容阵列可以适配于现有按照二进制编码方式进行控制码设计的控制逻辑产生电路30,因此设置所述用于模数转换器的电容阵列还包括控制码逻辑转换电路40;以使所述控制码逻辑产生电路按照二进制码输出用于控制第二子电容阵列20的第二二进制码,进而该第二二进制码经过所述控制码逻辑转换电路40转换为所述温度计码,从而控制所述第二子电容阵列20。
图3示出了所述第二子电容阵列20所接收到的温度计码与第二二进制码的映射关系,其中第二二进制码有5位,由高位到低位分别为M4、M3、M3、M2、M1;由于5位二进制数字量中包含31个(16+8+4+2+1=31)种不同的数字量,因此对应温度计码有31位,所述第二子电容阵列20的第二电容单元21也对应具有31个。所述31位温度计码由高位到低位分别为S30、S29、S28、S27、……、S0;由图中可以看出,所述温度计码每加1,只会有一个控制位发生改变,也就是代表只有一个第二开关22的状态发生改变,一个第二电容单元21发生切换。
在此需要说明的是,所述第二电容阵列的第二电容单元21从低位到高位是依次进行切换的。在此以5位二进制码为例说明,当二进制码由00000跳变为00001时,最低位的一个第二电容单元21切换,当00000跳变为00010时,低两位的第二电容单元21切换,……当00000跳变为10000时,低十六位第二电容单元21切换,当00000跳变为10001时,低十七为第二电容单元21切换。
本申请技术方案通过设置第二子电容阵列20,且所述第二电容单元21的电容量设置均相等,所述控制码逻辑转换电路40输出对应的温度计码,控制对应的第二开关22切换,以使所述温度计码无论在哪一位跳变,都不会造成大量第二电容单元21一同切换,从而不会引起大的转换误差。进一步地,考虑到第二子电容阵列20中并联分支较多,因此本申请技术方案采用采用分段电容阵列的设置方式,其中第一子电容阵列10中第一电容单元11的电容量设置采用二进制加权的设置方式;避免了全部使用第二子电容阵列20所造成并联分支数量较多的问题;本申请技术方案与现有技术相比,在所述模数转换器输出相同位数的前提下,有效地减小了电容阵列的转换误差,提高了模数转换器的转换精度。
基于上述实施例,本申请技术方案通过合理设置所述第二电容单元21的数量,以兼顾模数转换器的转换精度以及电容阵列并联分支较多的问题,可选地,所述第二电容单元21的数量为31个、15个或63个,所述温度计码对应分别为31位、15位、63位,对应至所述控制逻辑产生电路30输出对应的第二二进制码为5位、4位、6位。
在所述电容阵列工作过程中,主要的噪声来源是高位,即从高到低,它们的噪声容限是成倍增加的;因此本方案中,为了进一步减小噪声对电容阵列工作时的干扰,因此设置所述第一子电容阵列10为低位电容阵列;所述第二子电容阵列20为高位电容阵列;以利用所述第二子电容阵列20在温度计码跳变时,只会影响一个第二电容单元21的切换,因此将其设置在高位,以通过减少电容切换数量,从而减少噪声对电容跳变时的干扰。进一步地,由于第一子电容阵列10和第二子电容阵列20相邻接,因此设置最低位的第二电容单元21的电容量是第一电容单元11中最大电容量的两倍。
所述第一子电容阵列10与第二子电容阵列20依次并联;所述第一电容单元和第二电容单元的所对应的二进制码的位数为M位,且所述第一电容单元和第二电容单元的电容量之和为2M-1倍单位电容;所述第一电容单元的数量为N个,所述第一电容单元的总容值为2N-1倍单位电容;所述第二电容单元的数量有2M-N-1个,且所述第二电容单元的总容值为2M-2N倍单位电容。在此以M=7,N=2为例说明,所述第一电容单元和第二电容单元的电容量之和为27-1=127倍单位电容;所述第一电容单元的电容量之和为22-1=3倍单位电容,所述第二电容单元的数量有27-2-1=31个,所述第二电容单元的电容量之和为27-
22=124倍单位电容。
通常来说,对于高精度的SAR ADC,大多是12位,而对于12位的SAR
ADC,它的模数转换器电容阵列结构通常是7+5型,其中7代表高七位,5代表低5位;当然也有6+6型或者8+4型;根据设计人员的经验,设计以7+5型最合适的。模数转换器的精度主要由高7位决定,而通常的模数转换器结构,高7位的精度往往不那么理想,也成为现在模数转换器性能的一个最大的限制因素之一;因此本申请技术方案的优选实施例中,对于7+5型SAR
ADC,设置所述SAR
ADC输出高7位的数字量(二进制)所对应的电容阵列为本申请所提出的用于模数转换器的电容阵列,并且设置第二子电容阵列20对应为所述7位数字量中的高五位,第一子电容阵列10对应为所述7位数字量中的低两位;因此第一子电容阵列10的第一电容单元11的电容量自低位到高位分别为1倍单位电容、2倍单位电容。由于5位二进制数字量中包含31个(16+8+4+2+1=31)种不同的数字量,因此所述第二子电容阵列20的第二电容单元21共具有31个,且31个第二电容单元21的电容量均为4倍单位电容。
本申请还提出一种逐次逼近型模数转换器,所述逐次逼近型模数转换器包括比较器、连接于所述比较器输出端的寄存器以及所述用于模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
本实施例中给出了逐次逼近型模数转换器的大致工作过程:首先模拟输入信号被采样保持,送入比较器的一端,然后控制逻辑产生电路30将寄存器最高位预置1,其他位全部清零,模数转换器在参考电压和寄存器的控制下输出参考电压的二分之一送入比较器的另一端。如果模拟输入信号电压大于参考电压的二分之一,那么比较器输出1,寄存器最高位定为1;否则,如果模拟输入信号电压小于参考电压的二分之一,那么比较器输出0,寄存器最高位定为0。这样,逐逐次逼近型模数转换器最高位就确定了;进而再确定次高位,即先预置寄存器次高位为1,如果前一个转换周期确定的最高有效位为1,那么此时模数转换器输出参考电压的四分之三,模拟输入信号电压与参考电压的四分之三比较大小,从而确定寄存器次高位;如果前一个转换周期确定的最高有效位为0,那么此时模数转换器输出参考电压的四分之一,模拟输入信号电压与参考电压的四分之一比较大小,从而确定寄存器次高位。依此类推,直到寄存器的最低位确定为止,这样寄存器的值即逐次逼近型模数转换器的最终输出。
请参阅图4,本申请还提出一种电容阵列板,所述电容阵列板上设有所述的用于模数转换器的电容阵列的第二子电容阵列20;所述电容阵列板包括基板,所述基板上具有依次沿横向排列的所述第二子电容阵列20的多个第二电容单元21;每所述第二电容单元21包括4个沿纵向依次串联且电容量均为1倍单位电容的第一电容、第二电容、第三电容、以及第四电容;每所述第二电容单元21的第一电容的上极板串联,所述第二子电容阵列20的第二开关22与所述第二电容单元21一一对应设置,且所述第一电容、第二电容、第三电容、以及第四电容的下极板与其对应的第二开关22电连接。可选地,每所述第二电容单元21的第一电容、第二电容、第三电容、以及第四电容与其对应的第二开关22沿直线排列且多个所述第二电容单元21平行排布于所述基板上。
请参阅图5,图5为图4中电容阵列版的实物模拟示意图,其中,图4中至少具有31列电容组,每一列电容组的中间4个并联连接形成所述第二电容单元21,每一列电容组对应有一开关。可以看出,由于采用了本申请技术方案的电容阵列,以使原有模数转换器电容阵列复杂的版图走线连接通过***复杂的开关控制网络去取代,本申请的电容阵列版上电容之间的走线简单,因此可以大大减小走线寄生电容,因此进一步提高了所述模数转换器的转换精度。
以上所述仅为本申请的优选实施例,并非因此限制本申请的专利范围,凡是在本申请的发明构思下,利用本申请说明书及附图内容所作的等效结构变换,或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。
Claims (17)
- 一种用于模数转换器的电容阵列,其中,所述电容阵列包括控制逻辑产生电路、控制码逻辑转换电路、用于组成高低不同段位的第一子电容阵列和第二子电容阵列;所述第一子电容阵列包括多个第一电容单元以及多个第一开关,多个第一电容单元按电容量以二进制加权方式由低位到高位依次设置,多个所述第一电容单元互为并联关系;每所述第一电容单元经一所述第一开关与所述控制逻辑产生电路连接;所述控制逻辑产生电路对应所述第一子电容阵列输出第一二进制码至所述第一开关,以控制所述第一开关的切换状态;所述第二子电容阵列包括多个依次并联的第二电容单元以及多个第二开关,每所述第二电容单元经一所述第二开关与所述控制码逻辑转换电路连接,所述控制码逻辑转换电路与所述控制逻辑产生电路连接;所述第二电容单元的电容量均相等;所述控制逻辑产生电路对应第二子电容阵列输出第二二进制码,所述控制码逻辑转换电路将所述第二二进制码转换为温度计码后,输出至所述第二开关,以控制所述第二开关的切换状态。
- 如权利要求1所述的用于模数转换器的电容阵列,其中,所述第一子电容阵列为低位电容阵列;所述第二子电容阵列为高位电容阵列;最低位的第二电容单元的电容量是第一电容单元中最大电容量的两倍。
- 如权利要求2所述的用于模数转换器的电容阵列,其中,所述第一子电容阵列与第二子电容阵列依次并联;所述第一电容单元和第二电容单元的所对应的二进制码的位数为M位,且所述第一电容单元和第二电容单元的电容量之和为2M-1倍单位电容;所述第一电容单元的数量为N个,所述第一电容单元的总容值为2N-1倍单位电容;所述第二电容单元的数量有2M-N-1个,且所述第二电容单元的总容值为2M-2N倍单位电容。
- 如权利要求1所述的用于模数转换器的电容阵列,其中,所述第二电容单元的数量为15个、31个或63个。
- 如权利要求3所述的用于模数转换器的电容阵列,其中,可选地,所述第一子电容阵列有2个第一电容单元,所述第二子电容阵列有31个第二电容单元。
- 一种逐次逼近型模数转换器,其中,包括比较器、连接于所述比较器输出端的寄存器以及如权利要求1所述的模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
- 一种逐次逼近型模数转换器,其中,包括比较器、连接于所述比较器输出端的寄存器以及如权利要求2所述的模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
- 一种逐次逼近型模数转换器,其中,包括比较器、连接于所述比较器输出端的寄存器以及如权利要求3所述的模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
- 一种逐次逼近型模数转换器,其中,包括比较器、连接于所述比较器输出端的寄存器以及如权利要求4所述的模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
- 一种逐次逼近型模数转换器,其中,包括比较器、连接于所述比较器输出端的寄存器以及如权利要求5所述的模数转换器的电容阵列;所述模数转换器的电容阵列与所述比较器的输入端连接。
- 如权利要求6所述的逐次逼近型模数转换器,其中,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
- 如权利要求7所述的逐次逼近型模数转换器,其中,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
- 如权利要求8所述的逐次逼近型模数转换器,其中,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
- 如权利要求9所述的逐次逼近型模数转换器,其中,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
- 如权利要求10所述的逐次逼近型模数转换器,其中,所述逐次逼近型模数转换器输出的数字信号为12位,所述12位数字信号分为高7位以及低五位;所述高七位数字信号对应的电容阵列为所述用于模数转换器的电容阵列。
- 一种电容阵列板,其中,所述电容阵列板上设有如权利要求1至5任意一项所述的用于模数转换器的电容阵列的第二子电容阵列;所述电容阵列板包括基板,所述基板上具有依次沿横向排列的所述第二子电容阵列的多个第二电容单元;每所述第二电容单元包括4个沿纵向依次串联且电容量均为1倍单位电容的第一电容、第二电容、第三电容、以及第四电容;每所述第二电容单元的第一电容的上极板串联,所述第二子电容阵列的第二开关与所述第二电容单元一一对应设置,且所述第一电容、第二电容、第三电容、以及第四电容的下极板与其对应的第二开关电连接。
- 如权利要求8所述的电容阵列板,其中,每所述第二电容单元的第一电容、第二电容、第三电容、以及第四电容与其对应的第二开关沿直线排列;且多个所述第二电容单元平行排布于所述基板上。
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