WO2019047121A1 - 衬底及其制备方法 - Google Patents

衬底及其制备方法 Download PDF

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Publication number
WO2019047121A1
WO2019047121A1 PCT/CN2017/100946 CN2017100946W WO2019047121A1 WO 2019047121 A1 WO2019047121 A1 WO 2019047121A1 CN 2017100946 W CN2017100946 W CN 2017100946W WO 2019047121 A1 WO2019047121 A1 WO 2019047121A1
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substrate
base substrate
film layer
preparing
silicon
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PCT/CN2017/100946
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English (en)
French (fr)
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张丽旸
程凯
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苏州晶湛半导体有限公司
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Priority to PCT/CN2017/100946 priority Critical patent/WO2019047121A1/zh
Priority to CN201780094736.1A priority patent/CN111052306B/zh
Priority to TW107128745A priority patent/TWI752256B/zh
Publication of WO2019047121A1 publication Critical patent/WO2019047121A1/zh
Priority to US16/653,038 priority patent/US20200043867A1/en
Priority to US17/552,755 priority patent/US20220108890A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
    • H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular to a substrate and a method of fabricating the same.
  • III-V compound semiconductors such as GaAs, InP, GaN, etc. have advantages such as high electron mobility and large forbidden band width with respect to conventional semiconductors such as Ge and Si, and are widely used in the fields of microwaves and photovoltaic devices.
  • substrates commonly used for growing III-V compound semiconductors include sapphire substrates, silicon substrates, silicon carbide substrates, and the like.
  • the above substrate has problems such as lattice mismatch and thermal stress mismatch in the growth of a III-V compound semiconductor such as GaN, which may cause warpage or even cracking in the grown GaN epitaxial layer, and may cause
  • the GaN epitaxial layer has a high density of threading dislocations, which affects the performance of materials and devices, which causes difficulties in subsequent processing of the device and increases production costs.
  • the substrate is lithographically patterned to form a pattern, or a buffer layer is added in the middle of the epitaxial layer to solve the related problem.
  • a buffer layer in the middle of the epitaxial layer such as multilayer AlGaN, can accumulate stress, balance the thermal tensile stress applied by the substrate in the epitaxial layer, and realize the warpage control of the epitaxial layer on the substrate.
  • this structure still has a high density of threading dislocations, and the stress release becomes faster, limiting the growth thickness of the epitaxial layer.
  • An embodiment of the invention discloses a substrate comprising: a base substrate; a film layer, wherein the film layer covers a portion of the surface of the base substrate such that the base substrate has a layer that is not covered by the film layer a bare surface; and a recessed hole on at least a portion of the exposed surface.
  • the recess has a diameter of less than 500 nm.
  • the base substrate is silicon or silicon carbide or gallium nitride.
  • the film layer is Al or Fe or Mg or In.
  • An embodiment of the invention discloses a method for preparing a substrate, comprising the following steps:
  • a metal source is introduced into the reaction container, and a thin film layer is formed on a surface of the base substrate, wherein the thin film layer covers a portion of the surface of the base substrate, and the base substrate has no a bare surface covered by a film layer;
  • the diameter of the recessed hole is less than 500 nm.
  • the base substrate is silicon or silicon carbide or gallium nitride.
  • the reaction vessel is an organometallic chemical vapor deposition reactor or an atomic deposition reactor or a chemical beam epitaxy reactor.
  • the corrosive gas is NH3 or H2 or HCl or Cl2.
  • step S3 a Ga source is introduced or a Ga-containing compound is prepared on the film layer.
  • the invention has the beneficial effects that the substrate disclosed in the present invention can form a recessed hole on the surface of a part of the substrate, thereby releasing the lattice mismatch and thermal stress when the epitaxial layer is grown on the substrate in the subsequent semiconductor process.
  • the stress generated by the mismatch reduces the risk of defects and cracks in the epitaxial layer caused by excessive pressure, thereby reducing the warpage of the semiconductor prepared on the substrate, resulting in better quality.
  • the method for preparing the substrate disclosed by the invention is simple, high-efficiency and low in cost, and can form a concave hole on the substrate without a complicated etching process, and can be in the same reaction container as the subsequent epitaxial growth process This is done continuously while also releasing stresses due to lattice mismatch and thermal stress mismatch when growing the epitaxial layer on the substrate.
  • FIG. 1 is a schematic structural view of a semiconductor device to which a substrate according to an embodiment of the present invention is applied;
  • FIG. 2 is a TEM characterization of a semiconductor device to which a substrate as shown in an embodiment of the present invention is applied.
  • the main equipment for carrying out the invention is an organometallic chemical vapor deposition reactor or an atomic deposition reactor or a chemical beam epitaxy reactor.
  • various growth parameters are adjusted according to specific conditions.
  • the substrate shown in one embodiment of the present invention includes a base substrate 10, a film layer 11, and a recess 101.
  • the film layer 11 covers a part of the surface of the base substrate 10, that is, the base substrate 10 has a bare surface 100 that is not covered by the film layer 11. Therein, at least a portion of the exposed surface 100 is randomly formed with a recess 101.
  • the illustrated form in FIG. 1 is not the only form of the present invention, the bare drain surface 101 is randomly distributed on the surface of the base substrate 10, and the size is variable; the recessed holes 101 are also randomly distributed on the bare drain surface 100.
  • the size of the recess 101 is preferably less than 500 nm.
  • the base substrate 10 is preferably silicon.
  • the base substrate 10 may also be silicon carbide, gallium nitride or the like.
  • the film layer 11 is a metal film, and is preferably an aluminum film.
  • the thin film layer 11 may also be other metal thin films such as magnesium, iron, and indium.
  • a semiconductor device to which a substrate of an embodiment of the present invention is applied includes an epitaxial layer 12 disposed on a substrate.
  • the epitaxial layer 12 may include AlN, GaN, AlGaN, or the like.
  • This embodiment of the present invention has the beneficial effects that the substrate disclosed in the present invention can be released from the surface of a portion of the substrate by randomly forming a recessed hole, thereby releasing the cause of growth of the epitaxial layer on the substrate in the subsequent semiconductor process.
  • the stress generated by lattice mismatch and thermal stress mismatch reduces the risk of defects and cracks in the epitaxial layer caused by excessive pressure, thereby reducing the warpage of the semiconductor prepared on the substrate. Make it better quality and performance.
  • the disclosed invention can be used as a flexible substrate.
  • the present invention also discloses a method for preparing a substrate, as follows:
  • a metal source is introduced into the reaction container, and a film layer 11 is formed on the surface of the base substrate 10.
  • the film layer 11 partially covers the surface of the base substrate 10 so that the base substrate 10 has no film. The exposed surface 100 covered by the layer 11;
  • the diameter of the recess 101 is preferably less than 500 nm.
  • the temperature of the reaction vessel may be raised to the temperature of the epitaxial layer 12 of the semiconductor device to which the substrate of the present invention is subsequently applied (for example, the growth temperature of the III-V compound AlN is 500 ° C - 1400 ° C), and then A corrosive gas is introduced into the reaction vessel, and thus, the epitaxial layer 12 can be grown in the reaction vessel after the recess 101 is formed on the exposed surface of the base substrate 10.
  • the reaction vessel is preferably an organometallic chemical vapor deposition reactor.
  • the reaction vessel may also be an atomic deposition reactor or a chemical beam epitaxy reactor according to the needs of the process. Wait.
  • the substrate 20 is a silicon substrate.
  • the substrate 20 may also be a silicon carbide substrate and a gallium nitride substrate;
  • the metal source is an aluminum source, of course, in other embodiments.
  • the metal source may also be other metal sources such as magnesium, iron, and indium.
  • the corrosive gas is NH3.
  • the corrosive gas may also be HCl or H2 or Cl2.
  • FIG. 2 is a TEM characterization diagram of a semiconductor device to which a substrate according to an embodiment of the present invention is applied.
  • the base substrate 30 is silicon, and a portion of the base substrate 30 is covered with a thin film layer (not labeled).
  • a plurality of recessed holes 300 are formed on the exposed surface (not numbered) of the silicon substrate 30 partially covered by the thin film layer, and then an epitaxial layer 31 (AlN) is formed thereon.
  • AlN epitaxial layer
  • the formation of the recessed holes 300 on the partially exposed surface of the base substrate 30 can release the stress generated by the lattice mismatch and thermal mismatch between the base substrate 30 and the GaN epitaxial layer when the GaN epitaxial layer is grown, thereby avoiding growth.
  • the GaN epitaxial layer has a high degree of warpage and even cracks.
  • the embodiment of the present invention has the beneficial effects that the preparation method of the substrate is simple, high-efficiency, and low in cost, and a recessed hole can be formed on the substrate without a complicated etching process, and can be followed by an epitaxial growth process.
  • the same reaction vessel is continuously carried out while also releasing stress caused by lattice mismatch and thermal stress mismatch when the epitaxial layer is grown on the substrate.
  • a method of enlarging the diameter of the recessed hole 101 is also disclosed in another embodiment of the present invention.
  • the base substrate 10 is silicon
  • a corrosive gas is introduced into the reaction vessel to form a recessed hole 101 in at least part of the exposed surface
  • the Ga source is introduced or the Ga layer is epitaxially grown on the thin film layer 11.
  • a compound such as GaN, AlGaN, AlINGaN, etc.
  • a reflow reaction between a Ga atom and a silicon substrate to a recessed hole 101 is further etched to increase the diameter of the recess 101.
  • This embodiment of the invention has the advantageous effect that the diameter of the recessed hole 101 can be enlarged by the remelting reaction of Ga and silicon.

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Abstract

一种衬底及其制备方法，属于半导体领域。衬底包括：基础衬底(10)；薄膜层(11)，其中所述薄膜层(11)覆盖部分所述基础衬底(10)的表面，使所述基础衬底(10)具有未被所述薄膜层(11)覆盖的裸露表面(100)；以及凹孔(101)，位于至少部分所述裸露表面(100)上。该衬底具有凹孔，可以释放当在衬底上生长外延层时由于晶格失配和热失配所产生的应力，降低因压力过大而导致产生缺陷和裂纹的风险，从而减小后续在该衬底上制备得到的半导体的翘曲度，使其具有更好的质量与性能。

Description

衬底及其制备方法 技术领域
本发明涉及半导体技术领域，具体涉及一种衬底及其制备方法。
背景技术
Ⅲ-Ⅴ族化合物半导体如GaAs、InP、GaN等相对于Ge、Si等传统的半导体而言，具有电子迁移率高、禁带宽度大等优点，在微波及光电器件领域有广泛的应用。目前，生长Ⅲ-Ⅴ族化合物半导体常用的衬底有蓝宝石衬底、硅衬底和碳化硅衬底等。但上述衬底在生长Ⅲ-Ⅴ族化合物半导体(如GaN)时存在如晶格失配和热应力失配等问题，会在生长出的GaN外延层中产生翘曲甚至龟裂，同时会导致GaN外延层的穿透位错密度高，影响材料及器件的性能，给后续的器件加工工艺造成困难，提高生产成本。已知的现有技术中通过对衬底进行光刻，制作图形化，或者在外延层中间加入缓冲层来解决相关问题。
在实现本发明过程中，发明人发现现有技术中至少存在如下问题：
在衬底上低成本生长高质量的III-Ⅴ族化合物半导体结构是较困难的，
1)对衬底进行光刻或刻蚀，制作图形化的衬底，但其工艺复杂，生产成本高，还可能对后续生长的外延层造成沾污。
2)在外延层中间加入缓冲层，如多层AlGaN等，可以积聚应力，平衡外延层中由衬底施加的热张应力，实现衬底上外延层的翘曲控制。但是此结构依然存在很高的穿透位错密度，应力释放变快，限制外延层的生长厚度。
发明内容
本发明的目的在于提供一种衬底及其制造方法，其可解决在制备过程中因晶格失配和热应力失配会产生的应力的问题。
本发明的一实施例公开了一种衬底，包括：基础衬底；薄膜层，其中所述薄膜层覆盖部分所述基础衬底的表面，使基础衬底具有未被所述薄膜层覆盖的裸露表面；以及凹孔，位于至少部分所述裸露表面上。
优选地，所述凹孔的直径小于500nm。
优选地，所述基础衬底为硅或碳化硅或氮化镓。
优选地，所述薄膜层为Al或Fe或Mg或In。
本发明的一实施例公开了一种衬底的制备方法，包括以下步骤：
S1、提供安装有基础衬底的反应容器；
S2、向所述反应容器中通入金属源，在所述基础衬底的表面上形成薄膜层，其中所述薄膜层覆盖部分所述基础衬底表面，所述基础衬底具有未被所述薄膜层覆盖的裸露表面；以及
S3、向所述反应容器中通入腐蚀性气体以在至少部分所述裸露表面上形成凹孔。
优选地，步骤S3中，所述凹孔的直径小于500nm。
优选地，步骤S1中，所述基础衬底为硅或碳化硅或氮化镓。
优选地，步骤S1中，所述反应容器为有机金属化学气相沉积反应器或原子沉积反应器或化学束外延反应器。
优选地，所述腐蚀性气体为NH3或H2或HCl或Cl2。
优选地，当所述基础衬底为硅时，在步骤S3后，通入Ga源或在所述薄膜层上制备含Ga的化合物。
本发明的有益效果在于：本发明公开的衬底，由于部分衬底表面上形成有凹孔，从而能释放后续半导体工艺中当在衬底上生长外延层时由因晶格失配和热应力失配所产生的应力，降低因压力过大而导致生长的外延层产生缺陷和裂纹的风险，从而减小后续在该衬底上制备得到的半导体的翘曲度，使其具有更好的质量与性能；本发明公开的衬底的制备方法，简单、高效、成本低，无需通过复杂的刻蚀工艺，就可以在衬底上形成凹孔，且可以与后续的外延生长工艺在同一反应容器连续进行，同时还能释放当在衬底上生长外延层时由因晶格失配和热应力失配所产生的应力。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，并可依照说明书的内容予以实施，以下以本发明的较佳实施例并配合附图详细说明如后。
附图说明
下面参考附图结合实施例说明本发明。在附图中：
图1为应用本发明一实施例所示的衬底的半导体器件的结构示意图；
图2为应用本发明一实施例所示的衬底的半导体器件的TEM表征图。
具体实施方式
附图仅用于示例说明，不能理解为对本专利的限制；下面结合附图和实施例对本发明的技术方案做进一步的说明。在本发明实施例的描述中，将理解的是：当一元件被称作在另一元件“上”或“下”时，除非特别限定，一元件可以是“直接地”位于另一元件“上”或“下”(两者直接接触)，也可以是一元件“间接地”位于另一元件“上”或“下”(两者之间有其他元件)。出于方便或清楚的目的，附图中所示出的每个元件的厚度和尺寸可能被放大、缩小或示意性地绘制，元件的尺寸不完全反映实际尺寸。
实施本发明主要的设备为有机金属化学气相沉积反应器或原子沉积反应器或化学束外延反应器，对不同的半导体结构的制备，各种生长参数根据具体情况进行调整。
请参见图1应用本发明一实施例的衬底的半导体器件的结构示意图。本发明一实施例所示的衬底包括基础衬底10、薄膜层11和凹孔101。所述薄膜层11覆盖所述基础衬底10的部分表面，即所述基础衬底10具有未被所述薄膜层11覆盖的裸露表面100。其中，至少部分裸露表面100上，随机地形成有凹孔101。应当知晓，图1中的所示的形态并不是本发明的唯一形态，裸漏表面101是随机分布在基础衬底10的表面的，大小不定；凹孔101也是随机分布在裸漏表面100上的，大小不定，凹孔101的直径较佳地小于500nm。
基础衬底10较佳地为硅，当然，基础衬底10还可为碳化硅和氮化镓等。
薄膜层11为金属薄膜，且较佳的为铝薄膜。当然，在其他实施例中，薄膜层11还可为镁、铁、铟等其他金属薄膜。
应用本发明一实施例的衬底的半导体器件包括外延层12设置于衬底上。以基础衬底为Si的衬底上的GaN器件为例，外延层12可包括AlN、GaN、AlGaN等。
本发明的该实施例具有的有益效果：本发明所揭示的衬底，由于部分衬底表面上随机地形成有凹孔，从而能释放后续半导体工艺中当在衬底上生长外延层时由因晶格失配和热应力失配所产生的应力，降低因压力过大而导致生长的外延层产生缺陷和裂纹的风险，从而减小后续在该衬底上制备得到的半导体的翘曲度，使其具有更好的质量与性能。此外本发明所揭示的可作为柔性衬底。
结合图1，本发明还揭示了一种衬底的制备方法，如下：
S1、提供安装有基础衬底10的反应容器；
S2、向所述反应容器中通入金属源，在所述基础衬底10表面上形成薄膜层11，所述薄膜层11部分覆盖基础衬底10表面，使基础衬底10具有未被该薄膜层11覆盖的裸露表面100；
S3、向反应容器中通入腐蚀性气体以在至少部分所述裸露表面上形成凹孔101。所述凹孔101的直径较佳地小于500nm。
在本实施例步骤S3中，可先将反应容器升温至随后应用本发明的衬底的半导体器件的外延层12的温度(例如Ⅲ-Ⅴ族化合物AlN的生长温度500℃-1400℃)，再向反应容器中通入腐蚀性气体，如此，可在基础衬底10的裸露表面上形成凹孔101后，即在反应容器中生长外延层12。
上述制备方法中，所述反应容器较佳地为有机金属化学气相沉积反应器，当然，在其他实施例中，根据工艺的需要，该反应容器还可为原子沉积反应器或化学束外延反应器等。所述衬底20为硅衬底，当然，在其他实施例中，该衬底20还可为碳化硅衬底和氮化镓衬底；所述金属源为铝源，当然，在其他实施例中，该金属源还可为镁、铁、铟等其他金属源。所述腐蚀性气体为NH3，当然，在其他实施例中，该腐蚀性气体还可为HCl或H2或Cl2。
请参见图2，图2为应用本发明一实施例所示的衬底的半导体器件的TEM表征图，基础衬底30为硅，部分基础衬底30上覆盖有薄膜层(未标号)，在部分未被薄膜层覆盖的硅衬底30的裸露表面(未标号)上形成有许多凹孔300，然后再在上面形成了外延层31(AlN)。基础衬底30的部分裸露表面上形成凹孔300可以释放生长GaN外延层时由于基础衬底30和GaN外延层之间的晶格失配和热失配所产生的应力，所以避免了生长出的GaN外延层翘曲度较高甚至产生裂纹。
本发明的该实施例具有的有益效果：该衬底的制备方法简单、高效、成本低，无需通过复杂的刻蚀工艺，就可以在衬底上形成凹孔，且可以与后续的外延生长工艺在同一反应容器连续进行，同时还能释放当在衬底上生长外延层时由因晶格失配和热应力失配所产生的应力。
本发明另一实施例中还公开了一种扩大凹孔101的直径的方法。基础衬底10为硅时，在【S3、向反应容器中通入腐蚀性气体以在至少部分所述裸露表面上形成凹孔101】后，通入Ga源或在薄膜层11外延生长含Ga的化合物(例如GaN、AlGaN、AlINGaN等)，通过Ga原子与硅衬底之间的回熔反应，对凹孔 101进行进一步的刻蚀，从而增加凹孔101的直径。
本发明的该实施例具有的有益效果：通过Ga和硅的回熔反应，可扩大凹孔101的直径。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，当然，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。

Claims (10)

  1. 一种衬底，其特征在于，包括：
    基础衬底；
    薄膜层，其中所述薄膜层覆盖部分所述基础衬底的表面，使所述基础衬底具有未被所述薄膜层覆盖的裸露表面；以及
    凹孔，位于至少部分所述裸露表面上。
  2. 如权利要求1所述的衬底，其特征在于，所述凹孔的直径小于500nm。
  3. 如权利要求1所述的衬底，其特征在于，所述基础衬底为硅或碳化硅或氮化镓。
  4. 如权利要求1所述的衬底，其特征在于，所述薄膜层为Al或Fe或Mg或In。
  5. 一种衬底的制备方法，其特征在于：包括以下步骤：
    S1、提供安装有基础衬底的反应容器；
    S2、向所述反应容器中通入金属源，在所述基础衬底的表面上形成薄膜层，其中所述薄膜层覆盖部分所述基础衬底表面，所述基础衬底具有未被所述薄膜层覆盖的裸露表面；以及
    S3、向所述反应容器中通入腐蚀性气体以在至少部分所述裸露表面上形成凹孔。
  6. 如权利要求5所述的衬底的制备方法，其特征在于，步骤S3中，所述凹孔的直径小于500nm。
  7. 如权利要求5所述的衬底的制备方法，其特征在于，步骤S1中，所述基础衬底为硅或碳化硅或氮化镓。
  8. 如权利要求5所述的衬底的制备方法，其特征在于，步骤S1中，所述反应容器为有机金属化学气相沉积反应器或原子沉积反应器或化学束外延反应器。
  9. 如权利要求5所述的衬底的制备方法，其特征在于，步骤S3中，所述腐蚀性气体为NH3或H2或HCl或Cl2。
  10. 如权利要求7所述的衬底的制备方法，其特征在于，当所述基础衬底为硅时，在步骤S3后，通入Ga源或在所述薄膜层上制备含Ga的化合物。
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