WO2018233455A1 - 偏压调制方法、偏压调制***和等离子体处理设备 - Google Patents

偏压调制方法、偏压调制***和等离子体处理设备 Download PDF

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Publication number
WO2018233455A1
WO2018233455A1 PCT/CN2018/088818 CN2018088818W WO2018233455A1 WO 2018233455 A1 WO2018233455 A1 WO 2018233455A1 CN 2018088818 W CN2018088818 W CN 2018088818W WO 2018233455 A1 WO2018233455 A1 WO 2018233455A1
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Prior art keywords
bias
voltage
source
time
pulse
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PCT/CN2018/088818
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English (en)
French (fr)
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苏恒毅
韦刚
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北京北方华创微电子装备有限公司
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Publication of WO2018233455A1 publication Critical patent/WO2018233455A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00—Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/32—Processing objects by plasma generation
    • H01J2237/33—Processing objects by plasma generation characterised by the type of processing
    • H01J2237/334—Etching
    • H01J2237/3343—Problems associated with etching
    • H01J2237/3348—Problems associated with etching control of ion bombardment energy

Definitions

  • the present invention relates to the field of semiconductors, and in particular to a bias modulation method, a bias modulation system, and a plasma processing apparatus.
  • a plasma etching or deposition system by introducing various reaction gases (such as Cl2, SF6, C4F8, O2, etc.) into a vacuum reaction chamber, the reaction gas is completely dissociated by an external electromagnetic field (direct current or alternating current) to form a plasma. body.
  • the plasma contains a large amount of active particles of electrons, ions (including positive ions and negative ions), excited atoms, molecules, and radicals. These active particles interact with the surface of the wafer placed in the cavity and exposed to the plasma.
  • ICP Inductive Coupled Plasma Emission Spectrometer
  • FIG. 1 it is a schematic structural view of a typical ICP semiconductor etching apparatus.
  • a dielectric window 2 (quartz or ceramic) is disposed at the top of the vacuum chamber 3, and a planar RF antenna 1 is disposed above the dielectric window 2, and the RF energy output from the upper RF source 8 passes through the RF antenna 1 in the form of an induced discharge.
  • Energy is coupled into the vacuum chamber 3 to excite the reactive gases within the chamber to produce a high density plasma.
  • the plasma distributed in the vicinity of the dielectric window 2 is diffused from top to bottom to the surface of the wafer 4 for a specific process.
  • a typical lower electrode structure is provided in the vacuum chamber 3, which includes a stage 6, a metal electrode 5, and a bias RF source 7 and an impedance matching network electrically connected thereto.
  • the carrier 6 is used to carry the wafer 4; the metal electrode 5 is embedded in the carrier 6; the bias RF source 7 provides RF energy through the metal electrode 5 to generate a negative bias on the surface of the wafer, thereby controlling The ion energy bombarded to the surface of the wafer.
  • the bias RF source 7 supplies RF energy
  • positive ions accumulate on the surface of the wafer, generating a positive potential
  • the generated positive potential reduces the negative bias of the wafer surface.
  • the pressure which causes the attraction of positive ions in the plasma to be weakened, reduces the number and rate of positive ions reaching the surface of the wafer, thereby reducing the etching rate of the wafer surface, reducing the productivity, and possibly the workpiece to be processed. The condition that the surface cannot be adequately treated, thereby affecting the electrical properties of the workpiece.
  • the present invention is directed to the above technical problems existing in the prior art, and provides a bias modulation method, a bias modulation system, and a plasma processing apparatus, which can avoid a negative bias of a wafer surface during loading of a bias power to a susceptor.
  • the pressure is reduced, so that not only the plasma processing rate can be reduced, the productivity is ensured, but also the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance.
  • the invention provides a bias modulation method, comprising:
  • the difference between the target voltage value and the initial voltage value is equal to a negative bias loss value
  • the negative bias loss value is the bias RF during loading bias power to the susceptor
  • the loss value of the negative bias generated on the surface of the workpiece to be processed while the output voltage of the source maintains the initial voltage value
  • the bias power is applied to the susceptor according to a pulse period
  • the pulse period includes a pulse on time and a pulse off time
  • a bias power is applied to the pedestal while increasing an output voltage of the bias RF source such that the output voltage is The initial voltage value is increased to a target voltage value; at the pulse off time, loading of the bias power to the pedestal is stopped.
  • loading the pedestal power into the pedestal at the pulse-on time includes the following steps:
  • Step S102 detecting and recording a second bias voltage Vn generated on the surface of the workpiece to be processed at time tn of the current pulse-on time;
  • N is an integer
  • 1 ⁇ n ⁇ N is an integer
  • T1 is the length of the pulse on time
  • Step S103 calculating a difference V between the second bias voltage Vn and the third bias voltage V'n-1; wherein the third bias voltage V'n-1 is after the bias compensation is completed at the previous time The bias voltage generated on the surface of the workpiece to be processed; the third bias voltage V0' is equal to the first bias voltage V0;
  • Step S104 The output voltage of the bias RF source is adjusted in real time at the time tn of the current pulse-on time to the sum of the output voltage of the bias RF source and the difference V at time tn-1;
  • Step S105 detecting and recording a third bias voltage Vn' generated on the surface of the workpiece to be processed after the completion of the bias compensation;
  • Step S106 determining whether n is equal to N; if yes, the step ends; if not, replacing n with n+1, and sequentially performing steps S102 to S106.
  • the ratio of the initial voltage value to the target voltage value ranges from 0.1 to 0.9.
  • the output voltage of the biased RF source increases linearly during loading of the bias power to the susceptor.
  • the slope of the output voltage of the bias RF source increases linearly:
  • Vt is the target voltage value
  • Vs is the initial voltage value
  • T1 is the pulse turn-on time
  • the present invention also provides a bias modulation system, including:
  • Biasing a radio frequency source the bias RF source being electrically connected to a pedestal for carrying a workpiece to be processed for loading bias power to the susceptor;
  • a voltage adjustment module electrically connected to the bias RF source for increasing an output voltage of the bias RF source during loading of the bias RF source to the pedestal And increasing the output voltage from an initial voltage value to a target voltage value such that a negative bias voltage generated on a surface of the workpiece to be processed is maintained during loading bias power of the bias RF source to the susceptor In the preset range.
  • the bias RF source is a pulse modulated RF source to be capable of loading bias power to the pedestal in a pulse period;
  • the pulse period includes a pulse on time and a pulse off time, and at the pulse on time, the bias RF source loads a bias power to the pedestal while the voltage adjustment module increases an output of the bias RF source a voltage such that the output voltage is increased from an initial voltage value to a target voltage value; at the pulse off time, the biased RF source stops loading bias power to the pedestal.
  • the voltage adjustment module includes:
  • a clock generator capable of emitting a clock signal synchronized with the biased RF source
  • a voltage sensor in communication with the clock generator to detect a negative bias generated on a surface of the workpiece to be processed during the pulse turn-on time;
  • a digital processor in communication with the voltage sensor for receiving the negative bias voltage transmitted from the voltage sensor, and obtaining an output voltage adjustment value based on the negative bias voltage calculation, and The output voltage of the biased RF source is adjusted to the output voltage adjustment value such that a negative bias voltage generated on the surface of the workpiece to be processed is maintained at a preset value during loading of the bias power to the susceptor.
  • N is an integer
  • 1 ⁇ n ⁇ N is an integer
  • T1 is the length of the pulse on time
  • the output voltage of the bias RF source is the target voltage value; and detecting and recording the third bias voltage Vn generated on the surface of the workpiece to be processed after the completion of the bias compensation '.
  • the digital processor receives and records the first bias voltage V0, the second bias voltage Vn, and the third bias voltage Vn' sent by the voltage sensor, and executes:
  • the output voltage of the bias RF source is adjusted in real time at the time tn of the current pulse-on time to the sum of the output voltage of the biased RF source and the difference V at time tn-1;
  • n is equal to N; if yes, controlling the voltage sensor to stop detecting operation, and stopping adjusting an output voltage of the biased RF source; if not, controlling the voltage sensor to continue detecting operation, and adjusting the operation in real time The output voltage of the biased RF source.
  • the present invention also provides a plasma processing apparatus including: a susceptor for carrying a workpiece to be processed,
  • bias modulation system provided by the present invention, the bias modulation system being electrically coupled to the pedestal.
  • the output voltage of the bias RF source is increased to make the output voltage from the initial The voltage value is increased to the target voltage value. Since the output voltage of the bias RF source is gradually increased, the negative bias generated on the surface of the workpiece to be processed is gradually increased, and the amount of increase in the negative bias can be fully or partially compensated for being gradually accumulated on the surface of the workpiece to be processed.
  • the bias generated by the positive potential generated by the positive ions that is, although the positive potential reduces the negative bias of the wafer surface, the reduction of the negative bias is substantially the same as the increase of the negative bias, thereby Keeping the negative bias voltage within the preset range can not only avoid the plasma processing rate reduction, ensure the productivity, but also ensure that the surface of the workpiece to be processed can be fully processed to meet the electrical performance requirements.
  • FIG. 1 is a schematic structural view of an inductively coupled semiconductor etching apparatus in the prior art
  • FIG. 2 is a waveform diagram of a modulated pulse modulated RF source output according to an embodiment of the present invention
  • FIG. 3 is a schematic flow chart of a bias modulation method according to an embodiment of the present invention.
  • FIG. 4 is a waveform diagram of a modulated pulse modulated RF source output and an actual negative bias waveform of a corresponding wafer surface according to an embodiment of the present invention
  • FIG. 5 is a schematic diagram of a bias modulation system according to an embodiment of the present invention.
  • This embodiment provides a bias modulation method, including:
  • the output voltage of the bias RF source during loading of the bias power to the susceptor for carrying the workpiece to be processed, so that the output voltage is increased from the initial voltage value to the target voltage value so as to be on the surface of the workpiece to be processed
  • the resulting negative bias is maintained within a predetermined range during the loading of the bias power to the pedestal.
  • the so-called preset range refers to a range of fluctuations in the allowable bias power, which satisfies: maintaining a certain amount and rate of positive ions reaching the surface of the workpiece to be processed, thereby ensuring that the plasma processing rate is within a suitable process range.
  • the negative bias generated on the surface of the workpiece to be processed is gradually increased, and the amount of increase in the negative bias can partially or completely compensate for the positive accumulation on the surface of the workpiece to be processed.
  • a bias that is lost by the positive potential generated by the ions, that is, although the positive potential reduces the negative bias on the surface of the wafer the amount of decrease in the negative bias is substantially equal to the increase in the negative bias, thereby enabling
  • the negative bias voltage is kept within the preset range, thereby not only avoiding the plasma processing rate reduction, ensuring the productivity, but also ensuring that the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance requirements.
  • the difference between the target voltage value and the initial voltage value is equal to a negative bias loss value, and the output voltage of the biased RF source remains during the loading of the bias power for the pedestal.
  • the loss value of the negative bias generated on the surface of the workpiece to be processed when the initial voltage value is constant.
  • the negative bias that increases the surface of the workpiece to be processed just compensates for the bias that is lost due to the positive potential generated by the positive ions accumulated on the surface of the workpiece to be processed, thereby keeping the negative bias of the surface of the workpiece to be processed constant.
  • the initial voltage level can not only avoid the plasma processing rate reduction, ensure the production capacity, but also ensure that the surface of the workpiece to be processed can be fully processed to meet the electrical performance requirements.
  • the difference between the target voltage value and the initial voltage value may also be greater than or less than the above-mentioned negative bias loss value, as long as the negative bias voltage of the surface of the workpiece to be processed is kept within a preset range.
  • the bias RF source outputs a sinusoidal continuous wave.
  • the continuous wave plasma may cause damage to the device during the etching process.
  • a solution to this problem may be to apply bias power to the pedestal in a pulse period.
  • the pulse period includes a pulse on time and a pulse off time.
  • the bias power is applied to the pedestal, and the output voltage of the bias RF source is increased to increase the output voltage from the initial voltage value to the target voltage. Value; at the pulse off time, stop loading bias power to the pedestal.
  • the bias RF source is capable of loading bias power to the pedestal in a pulse period, such as a pulse modulated RF source.
  • the bias RF source is a pulse modulation RF source, wherein the pulse period T includes a pulse on time T1 and a pulse off time T2, and the output of the biased RF source is at the pulse on time T1.
  • the voltage is increased from the initial voltage value V1 to the target voltage value V2.
  • the bias power is applied to the susceptor during the pulse-on time, which specifically includes the following steps:
  • Step S102 detecting and recording a second bias voltage Vn generated on the surface of the workpiece to be processed at time tn of the current pulse-on time;
  • N is an integer
  • 1 ⁇ n ⁇ N is an integer
  • T1 is the length of the pulse on time
  • the output voltage of the bias RF source is the target voltage value.
  • Step S103 Calculating a difference V between the second bias voltage Vn and the first bias third bias voltage V'n-1.
  • Step S104 The output voltage of the biased RF source is adjusted in real time at the time tn of the current pulse-on time to the sum of the output voltage of the biased RF source and the difference V at time tn-1.
  • Step S105 detecting and recording the third bias voltage Vn' generated on the surface of the workpiece to be processed after the completion of the bias compensation.
  • Step S106 It is judged whether n is equal to N. If yes, the step ends. If not, n is replaced by n+1, and steps S102 to S106 are sequentially performed.
  • the actual voltage at the moment before the pulse is turned off is the target voltage at the last moment of the pulse-on time.
  • electrons enter the bottom of the etch tank, neutralizing the positive charge, and restoring the wafer surface bias to 0V.
  • the method of loading bias power to the susceptor according to the pulse period can realize real-time dynamic adjustment compensation of the bias voltage generated on the surface of the wafer during the process, so that the surface of the wafer reaches the compensation effect as shown in FIG. Among them, the larger the value of N, the better the compensation effect.
  • the detection and output voltage of the second bias voltage in each of the above cycles is increased from the initial voltage value to the target voltage value under the same process condition, that is, the detection and voltage increase process is at the same pulse turn-on time.
  • the same pulse power and pulse duty cycle, and the same initial voltage value are performed to ensure that the obtained bias of the surface loss of the workpiece to be processed is exactly equal to the compensation amount of the bias of the surface loss of the workpiece to be processed, thereby
  • the negative bias voltage on the surface of the machined workpiece is maintained at a constant initial voltage level, which not only avoids a reduction in the plasma processing rate, but also ensures the production capacity, and ensures that the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance requirements.
  • the output voltage of the biased RF source increases linearly.
  • the pulse waveform output from the bias RF source is a square wave
  • the positive charge accumulation on the workpiece to be processed has a substantially linear trend. Therefore, by linearly increasing the output voltage of the bias RF source, the linear increase can be correspondingly increased. The charge is cancelled so that a desired negative bias level is obtained on the workpiece to be processed.
  • the initial voltage value of the output voltage of the bias RF source is Vs
  • the target voltage value is Vt.
  • the slope of the output voltage of the biased RF source increases linearly:
  • Vt is the target voltage value
  • Vs is the initial voltage value
  • T1 is the pulse on time.
  • an inductively coupled plasma etching device that biases a RF source output pulse is a novel pulse-modulated RF source that can output a waveform as shown in FIG.
  • the pulse modulated RF source is used to apply a negative bias to the pedestal to create a negative bias on the surface of the wafer to be etched placed on the susceptor to attract plasma to the surface of the wafer to be etched.
  • the pulse modulation RF source output pulse frequency is 50 Hz
  • the duty ratio is 60%
  • the initial voltage value Vs is 300V.
  • the duty ratio of the pulse is set to 60%
  • the surface bias of the wafer to be etched during the pulse on and off phases is lowered from 300V to 200V, that is, the bias voltage is lost by 100V. Therefore, in order to compensate for the bias loss of the surface to be etched, the target voltage value Vt of the pulse-modulated RF source output should be increased to 400V to compensate for the above-mentioned loss of 100V bias voltage, that is, the initial voltage value of the pulse-modulated RF source output Vs.
  • the voltage ratio Vr to the target voltage value Vt is 0.75.
  • the pulse modulation waveform of the bias RF source output and the corresponding negative bias of the surface of the wafer to be etched are as shown in FIG. 4 .
  • the surface bias of the wafer to be etched is maintained at the initial voltage value Vs level, so that the negative bias voltage of the surface of the workpiece to be processed is maintained at a constant initial voltage level, thereby not only avoiding a decrease in plasma processing rate, but also ensuring throughput. It can be ensured that the surface of the workpiece to be processed can be fully treated to meet the electrical performance requirements.
  • the pulse off phase free electrons enter the etched trenches in the surface of the wafer to be etched and positive charges therein, causing the surface of the wafer to be etched to return to zero potential; It can be seen from FIG. 4 that during the pulse-on time, the pulse is modulated to solve the problem of the negative bias drop caused by the positive charge accumulation on the surface of the wafer to be etched, thereby maintaining the expected etch rate compared to the prior art. This in turn ensures the throughput of the wafer.
  • the pulse voltage of the output may also increase nonlinearly during the turn-on time T1 of the pulse.
  • the non-linearly increased voltage can correspondingly cancel the non-linearly increasing accumulated positive charge, thereby achieving a desired negative bias level on the wafer to be processed.
  • the ratio of the initial voltage value Vs to the target voltage value Vt ranges from 0.1 to 0.9. Adjusting the ratio of the initial voltage value Vs to the target voltage value Vt within this range can achieve appropriate compensation for the surface bias loss of the wafer to be processed, thereby enabling processing of the wafer to be processed according to different processing target requirements of the wafer to be processed. Regulation is carried out to achieve precise control of wafer processing rate, improve wafer processing quality, and ensure wafer throughput.
  • the RF frequency of the pulse modulation RF source is 2MHz, 13.56MHz or 60MHz.
  • the bias modulation method in this embodiment is applicable not only to an inductively coupled plasma processing (ICP) but also to a capacitively coupled plasma processing (CCP), a microwave plasma processing, and a microwave electron cyclotron resonance plasma processing (ECR). ).
  • the output voltage of the bias RF source is increased. So that the output voltage is increased from the initial voltage value to the target voltage value. Since the output voltage of the bias RF source is gradually increased, the negative bias generated on the surface of the workpiece to be processed is gradually increased, and the amount of increase in the negative bias can be fully or partially compensated for being gradually accumulated on the surface of the workpiece to be processed.
  • the bias generated by the positive potential generated by the positive ions that is, although the positive potential reduces the negative bias of the wafer surface, the reduction of the negative bias is substantially the same as the increase of the negative bias, thereby Keeping the negative bias voltage within the preset range can not only avoid the plasma processing rate reduction, ensure the productivity, but also ensure that the surface of the workpiece to be processed can be fully processed to meet the electrical performance requirements.
  • the present embodiment provides a bias modulation system, as shown in FIG. 5, for modulating a negative bias voltage of a workpiece to be processed placed on the surface of the susceptor 10.
  • the bias modulation system includes a bias RF source 7 and a voltage adjustment module, wherein the bias RF source 7 is electrically coupled to a susceptor 10 for carrying a workpiece to be processed for loading bias power to the susceptor 10 such that The surface of the workpiece to be machined produces a negative bias.
  • the voltage adjustment module 9 is electrically connected to the bias RF source 7 for increasing the output voltage of the bias RF source during the biasing of the RF source to apply bias power to the pedestal to increase the output voltage from the initial voltage value. To the target voltage value, such that the negative bias generated on the surface of the workpiece to be processed is maintained within a preset range during the biasing of the bias RF source to the susceptor.
  • the negative bias generated on the surface of the workpiece to be processed can be gradually increased, and the increase of the negative bias can fully or partially compensate the positive potential generated by the positive ions gradually accumulated on the surface of the workpiece to be processed.
  • the loss of the bias voltage that is, although the positive potential reduces the negative bias of the wafer surface, the reduction of the negative bias is substantially the same as the increase of the negative bias, so that the negative bias can be maintained at Within the preset range, not only can the plasma processing rate be reduced, the production capacity can be ensured, but also the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance requirements.
  • the workpiece to be processed is the wafer 4 to be processed.
  • the voltage adjustment module 9 includes a clock generator 91, a voltage sensor 92, and a digital processor 93, wherein the clock generator 91 is capable of emitting a clock signal synchronized with the biased RF source.
  • the voltage sensor 92 is in communication with the clock generator 91 to be able to detect a negative bias generated on the surface of the workpiece to be processed during the pulse-on time.
  • the digital processor 93 is in communication with the voltage sensor 92 for receiving a negative bias voltage transmitted from the voltage sensor 92, and obtaining an output voltage adjustment value based on the negative bias voltage, and adjusting the output voltage of the bias RF source to an output voltage. The value is adjusted such that the negative bias generated on the surface of the workpiece to be machined is maintained at a preset value during the loading of the bias power to the susceptor.
  • N is an integer
  • 1 ⁇ n ⁇ N is an integer
  • T1 is the length of the pulse on time
  • the output voltage of the bias RF source is the target voltage value; and the third bias voltage Vn' generated on the surface of the workpiece to be processed after the completion of the bias compensation is detected and recorded.
  • the digital processor 93 receives and records the first bias voltage V0, the second bias voltage Vn, and the third bias voltage Vn' transmitted from the voltage sensor 92, and executes:
  • the digital processor 93 adjusts the output voltage of the biased RF source at the time tn of the current pulse-on time to the sum of the output voltage of the biased RF source and the difference V at tn-1.
  • the digital processor 93 determines whether n is equal to N, and if so, instructs the voltage sensor 92 to stop the detecting operation, and stops adjusting the output voltage of the biased RF source; if not, the control voltage sensor 82 continues to detect the operation, and adjusts in real time. The output voltage of the biased RF source.
  • the clock generator 91 is used to generate a square wave pulse, and the pulse period of the square wave pulse is T1/N.
  • the bias RF source 7 is a novel pulse modulated RF source that can output a waveform as shown in FIG.
  • the square wave pulse generated by the clock generator 91 is input to the voltage sensor 92.
  • N is an integer greater than 0, in order to ensure the timeliness and effectiveness of voltage compensation, generally N ⁇ 100, the larger the N value, the better the compensation effect.
  • the voltage sensor 92 is responsible for detecting the first bias voltage and the second bias voltage on the surface of the wafer 4, and the timing of detecting is controlled by a square wave pulse outputted by the clock generator 91, and can be set as a pulse rising edge or a falling edge triggering detection action.
  • n is the count value of the square wave pulse of the clock generator 91.
  • the digital processor 93 is responsible for receiving, recording and calculating the detected data of the voltage sensor 92, and the result of the operation is fed back to the bias RF source 7, so that the bias RF source 7 can adjust the output pulse voltage in real time according to the feedback result.
  • the specific process of loading the bias power to the susceptor by the pulse period in the voltage adjustment module 9 is: the bias RF source 7 and the clock generator 92 simultaneously output pulses, assuming the bias RF source 7
  • n is an integer greater than 0, the initial value is 1, and the value of n can be changed and stored in the digital processor 93.
  • the second bias voltage V1 is sent to the digital processor 93.
  • the voltage output from the bias voltage source 7 at the moment before the pulse is turned off is the target voltage at the last moment of the pulse on time. After the pulse is turned off, electrons enter the bottom of the etched tank, neutralizing the positive charge, and the wafer 4 is biased back to 0V.
  • the RF pulse modulation system can realize real-time dynamic compensation of the surface bias of the wafer 4 during the process, and achieve the compensation effect as shown in FIG.
  • the negative bias generated on the surface of the workpiece to be processed can be gradually increased, and the increase of the negative bias can be fully or partially compensated due to the gradual accumulation.
  • the bias voltage lost by the positive potential generated by the positive ions on the surface of the workpiece, that is, although the positive potential reduces the negative bias of the wafer surface, the reduction of the negative bias and the increase of the negative bias are basically It is flat, so that the negative bias can be kept within the preset range, thereby not only avoiding the plasma processing rate reduction, ensuring the productivity, but also ensuring that the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance.
  • the present embodiment provides a plasma processing apparatus including a susceptor for carrying a workpiece to be processed, and the bias modulation system of the above-described Embodiment 2, the bias modulation system being electrically connected to the susceptor.
  • the plasma processing apparatus further comprises a plasma generating device comprising a coil and an upper electrode radio frequency source connected to the coil, the upper electrode radio frequency source being a continuous wave radio frequency source or a pulse modulation radio frequency source.
  • the negative bias generated on the surface of the workpiece to be processed can be gradually increased, and the amount of increase in the negative bias can be fully or partially compensated for gradually accumulating to the surface of the workpiece to be processed.
  • the positive ion generated by the positive ion and the bias voltage lost that is, although the positive potential reduces the negative bias of the wafer surface, the reduction of the negative bias is substantially the same as the increase of the negative bias, thereby
  • the negative bias voltage can be kept within the preset range, thereby not only avoiding the plasma processing rate reduction, ensuring the productivity, but also ensuring that the surface of the workpiece to be processed can be sufficiently processed to meet the electrical performance. .
  • the bias modulation method, the bias modulation system, and the plasma processing apparatus including the same are not limited to inductively coupled plasma generation, negative bias occurring in capacitively coupled plasma generation.
  • the problem of pressure loss, the above-described inductively coupled plasma or capacitively coupled plasma generation is merely illustrative of specific embodiments of the invention and is not intended to limit the invention.
  • the bias modulation method of the present invention can be employed, and the bias modulation system and the plasma processing apparatus solve the technical problems.

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Abstract

本发明提供了一种偏压调制方法、偏压调制***和等离子体处理设备。该偏压调制方法包括：在向用于承载待加工工件的基座加载偏压功率期间，增大偏压射频源的输出电压，以使输出电压由初始电压值增加至目标电压值，从而使在待加工工件表面上产生的负偏压在向基座加载偏压功率期间保持在预设范围内。本发明还公开了一种偏压调制***。本发明公开的等离子体处理设备包括本发明提供的偏压调制***。本发明的偏压调制方法、偏压调制***和等离子体处理设备均可以避免在向基座加载偏压功率期间出现晶圆表面的负偏压降低的情况，从而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。

Description

偏压调制方法、偏压调制***和等离子体处理设备 技术领域
本发明涉及半导体领域，具体地，涉及一种偏压调制方法、偏压调制***和等离子体处理设备。
背景技术
随着半导体元器件制造工艺的迅速发展，对元器件性能与集成度要求越来越高，使得等离子体技术得到了极广泛的应用。在等离子体刻蚀或沉积***中，通过在真空反应腔室内引入各种反应气体(如Cl2,SF6,C4F8,O2等)，利用外加电磁场(直流或交流)使反应气体完全解离，形成等离子体。等离子体中含有大量电子、离子(包括正离子和负离子)、激发态原子、分子和自由基等的活性粒子，这些活性粒子和置于腔体并曝露在等离子体中的晶圆表面相互作用，使晶圆表面发生各种物理化学反应，从而使晶圆表面性能发生变化，完成诸如刻蚀或沉积等的工艺过程。在用于半导体制造工艺的等离子体设备的研发中，最重要的因素是提高对晶圆的加工能力，以提高产率，以及执行用于制造高度集成器件工艺的能力。
在传统的半导体制造工艺中，使用比较广泛的半导体刻蚀装置激发等离子体的方式为电感耦合等离子体(ICP，Inductive Coupled Plasma Emission Spectrometer)，这种方式可以在较低工作气压下获得高密度的等离子体，而且结构简单，造价低。
如图1所示，为典型ICP半导体刻蚀装置的结构示意图。在真空腔室3的顶部设置有介质窗2(石英或陶瓷)，且在介质窗2的上方设置有平面射频天线1，上射频源8输出的射频能量通过射频天线1，以感应放电的形式，将能量耦合至真空腔室3中，以激发腔室内的反应气体产生高密度等离子体。 分布在介质窗2附近的等离子体由上至下扩散至晶圆4表面，进行特定的工艺过程。另外，在真空腔室3中还设置有典型的下电极结构，其包括载片台6、金属电极5以及与其电连接的偏压射频源7和阻抗匹配网络。其中，载片台6用于承载晶圆4；金属电极5内嵌在载片台6中；偏压射频源7通过金属电极5提供射频能量，以在晶圆表面产生负偏压，从而控制轰击至晶圆表面的离子能量。
但是，在工艺过程中，由于晶圆不导电，在偏压射频源7提供射频能量时，会有正离子累积到晶圆表面，产生正电势，产生的正电势会降低晶圆表面的负偏压，从而导致对等离子体中正离子的吸引力减弱，降低了到达晶圆表面的正离子的数量和速率，进而不仅降低了晶圆表面的刻蚀速率，降低了产能，而且可能出现待加工工件表面不能够被充分处理的情况，从而影响工件的电学性能。
发明内容
本发明针对现有技术中存在的上述技术问题，提供一种偏压调制方法、偏压调制***和等离子体处理设备，其可以避免在向基座加载偏压功率期间出现晶圆表面的负偏压降低的情况，从而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
本发明提供一种偏压调制方法，包括：
在向用于承载待加工工件的基座加载偏压功率期间，增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值，从而使所述待加工工件表面上产生的负偏压在向所述基座加载偏压功率期间保持在预设范围内。
可选的，所述目标电压值与所述初始电压值的差值等于负偏压损失值， 所述负偏压损失值为在向所述基座加载偏压功率期间，所述偏压射频源的输出电压保持所述初始电压值不变时，在所述待加工工件表面上产生的负偏压的损失值。
可选的，按脉冲周期向所述基座加载偏压功率；
其中，所述脉冲周期包括脉冲开启时间和脉冲关闭时间，在所述脉冲开启时间，向所述基座加载偏压功率，同时增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值；在所述脉冲关闭时间，停止向所述基座加载偏压功率。
可选的，在所述脉冲开启时间向所述基座加载偏压功率，具体包括以下步骤：
步骤S101：检测并记录t＝0时，在所述待加工工件表面上产生的第一偏压V0；所述第一偏压V0等于所述初始电压值；
步骤S102：检测并记录在当前的脉冲开启时间的tn时刻，在所述待加工工件表面上产生的第二偏压Vn；其中，
tn＝n(T1/N)
N≥100，且N为整数；1≤n≤N，且n为整数；T1为所述脉冲开启时间的长度；
当n＝N时，在tn时刻，所述偏压射频源的输出电压为所述目标电压值；
步骤S103：计算所述第二偏压Vn与第三偏压V’n-1的差值V；其中，所述第三偏压V’n-1为在上一时刻完成偏压补偿后在所述待加工工件表面上产生的偏压；第三偏压V0'等于第一偏压V0；
步骤S104：将在当前的脉冲开启时间的tn时刻所述偏压射频源的输出电压实时调整为tn-1时刻所述偏压射频源的输出电压与所述差值V之和；
步骤S105：检测并记录完成偏压补偿后在所述待加工工件表面上产生的第三偏压Vn’；
步骤S106：判断n是否等于N；如果是，则步骤结束；如果否，则将n替换为n+1,并依次执行所述步骤S102至步骤S106。
可选的，所述初始电压值与所述目标电压值的比值的取值范围在0.1-0.9。
可选的，在向所述基座加载偏压功率期间，所述偏压射频源的输出电压呈线性增大。
可选的，所述偏压射频源的输出电压呈线性增大的斜率为：
K＝(Vt-Vs)/T1；
其中，Vt为所述目标电压值，Vs为所述初始电压值，T1为所述脉冲开启时间。
作为另一个技术方案，本发明还提供一种偏压调制***，包括：
偏压射频源,所述偏压射频源与用于承载待加工工件的基座电连接，用于向所述基座加载偏压功率；
电压调整模块，所述电压调整模块与所述偏压射频源电连接，用于在所述偏压射频源向所述基座加载偏压功率期间，增大所述偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值，从而使在所述待加工工件表面上产生的负偏压在所述偏压射频源向所述基座加载偏压功率期间保持在预设范围。
可选的，所述偏压射频源为脉冲调制射频源，以能够按脉冲周期向所述基座加载偏压功率；其中，
所述脉冲周期包括脉冲开启时间和脉冲关闭时间，在所述脉冲开启时间，所述偏压射频源向所述基座加载偏压功率，同时所述电压调整模块增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值；在所述脉冲关闭时间，所述偏压射频源停止向所述基座加载偏压功率。
可选的，所述电压调整模块包括：
时钟发生器，所述时钟发生器能够发出与所述偏压射频源同步的时钟信号；
电压传感器，所述电压传感器与所述时钟发生器进行通信，以能够在所述脉冲开启时间内检测在所述待加工工件表面上产生的负偏压；
数字处理器，所述数字处理器与所述电压传感器进行通信，用于接收来自所述电压传感器发送的所述负偏压，并根据该负偏压计算获得输出电压调整值，并将所述偏压射频源的输出电压调整为所述输出电压调整值，以使在所述待加工工件表面上产生的负偏压在向所述基座加载偏压功率期间保持在预设值。
可选的，所述电压传感器检测t＝0时，在所述待加工工件表面上产生的第一偏压V0；所述第一偏压V0等于所述初始电压值；和检测在当前的脉冲开启时间的tn时刻，在所述待加工工件表面上产生的第二偏压Vn；其中，
tn＝n(T1/N)
N≥100，且N为整数；1≤n≤N，且n为整数；T1为所述脉冲开启时间的长度；
当n＝N时，在tn时刻，所述偏压射频源的输出电压为所述目标电压值；以及检测并记录完成偏压补偿后在所述待加工工件表面上产生的第三偏压Vn’。
可选的，所述数字处理器接收并记录来自所述电压传感器发送的所述第一偏压V0、所述第二偏压Vn和所述第三偏压Vn’，并执行：
计算所述第二偏压Vn与第三偏压Vn-1’的差值V；其中，所述第三偏压Vn-1’为在上一时刻完成偏压补偿后在所述待加工工件表面上产生的偏压；V0'等于第一偏压V0；
将在当前的脉冲开启时间的tn时刻所述偏压射频源的输出电压实时调整为tn-1时刻所述偏压射频源的输出电压与所述差值V之和；
判断n是否等于N；如果是，则控制所述电压传感器停止检测工作，和停止调整所述偏压射频源的输出电压；如果否，则控制所述电压传感器继续检测工作，和实时调整所述偏压射频源的输出电压。
作为另一个技术方案，本发明还提供一种等离子体处理设备，包括：用于承载待加工工件的基座，
还包括本发明提供的上述偏压调制***，所述偏压调制***与所述基座电连接。
本发明的有益效果：
本发明提供的偏压调制方法、偏压调制***和等离子体处理设备的技术方案中，在向基座加载偏压功率期间，增大偏压射频源的输出电压，以使该输出电压由初始电压值增加至目标电压值。由于偏压射频源的输出电压逐渐增大，这使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够全部或部分补偿因逐渐累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
附图说明
图1为现有技术中电感耦合半导体刻蚀装置的结构示意图；
图2为本发明一种实施方式的调制后的脉冲调制射频源输出的波形图；
图3为本发明一种实施方式的偏压调制方法的流程示意图；
图4为本发明一种实施方式的调制后的脉冲调制射频源输出的波形及相应的晶片表面的实际负偏压波形图；
图5为本发明一种实施方式的偏压调制***示意图。
其中，附图标记为：
1.射频天线；2.介质窗；3.真空腔室；4.晶片；5.金属电极；6.载片台；7.偏压射频源；8.主射频源；T1.脉冲开启时间；T2.脉冲关闭时间；Vs.初始电压；Vt.目标电压；9.电压调整模块；91.时钟发生器；92.电压传感器；93.数字处理器；10.基座。
具体实施方式
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明提供的偏压调制方法、偏压调制***和等离子体处理设备作进一步详细描述。
实施例1：
本实施例提供一种偏压调制方法，包括：
在向用于承载待加工工件的基座加载偏压功率期间，增大偏压射频源的输出电压，以使该输出电压由初始电压值增加至目标电压值，从而使在待加工工件表面上产生的负偏压在向基座加载偏压功率期间保持在预设范围内。
其中，所谓预设范围，是指允许偏压功率的波动范围，满足：保持到达待加工工件表面的正离子具有一定的数量和速率，从而确保等离子体处理速率在合适的工艺范围内。
由于偏压射频源的输出电压逐渐增大，这使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够部分或全部补偿因累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
可选的，目标电压值与初始电压值的差值等于负偏压损失值，该负偏压 损失值为在向用于基座加载偏压功率期间，偏压射频源的输出电压保持所述初始电压值不变时，在待加工工件表面上产生的负偏压的损失值。如此设置，能使待加工工件表面增加的负偏压恰好补偿因累积到待加工工件表面的正离子产生的正电势而损失的偏压，从而使待加工工件表面的负偏压保持在恒定的初始电压水平，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
需要说明的是，目标电压值与初始电压值的差值也可以大于或者小于上述负偏压损失值，只要使待加工工件表面的负偏压保持在预设范围即可。
在现有技术中，偏压射频源输出的是正弦连续波，但是，当刻蚀工艺的特征尺度在20nm以下时，采用连续波的等离子体在进行刻蚀工艺时会对器件造成损伤，影响器件的电学性能。解决该问题的方案可以是按脉冲周期向基座加载偏压功率。具体地，脉冲周期包括脉冲开启时间和脉冲关闭时间，在脉冲开启时间，向基座加载偏压功率，同时增大偏压射频源的输出电压，以使输出电压由初始电压值增加至目标电压值；在脉冲关闭时间，停止向基座加载偏压功率。
由于在脉冲关闭时间，停止向基座加载偏压功率，等离子体中的电子会降落到晶片表面中和在脉冲开启时间累积的正离子，从而晶片表面累积的正电势，进而可以进一步减少偏压的损失。
偏压射频源能够按脉冲周期向基座加载偏压功率，例如脉冲调制射频源。
在本实施例中，如图2所示，偏压射频源为脉冲调制射频源，其中，脉冲周期T包括脉冲开启时间T1和脉冲关闭时间T2，在脉冲开启时间T1，偏压射频源的输出电压由初始电压值V1增加至目标电压值V2。
在本实施例中，如图3所示，在脉冲开启时间向所述基座加载偏压功率，具体包括以下步骤：
步骤S101：检测并记录t＝0时，在待加工工件表面上产生的第一偏压V0；该第一偏压V0等于初始电压值。
步骤S102：检测并记录在当前的脉冲开启时间的tn时刻，在待加工工件表面上产生的第二偏压Vn；其中，
tn＝n(T1/N)
N≥100，且N为整数；1≤n≤N，且n为整数；T1为所述脉冲开启时间的长度；
当n＝N时，在tn时刻，偏压射频源的输出电压为目标电压值。
步骤S103：计算第二偏压Vn与第一偏压第三偏压V’n-1的差值V。
其中，第三偏压V’n-1为在上一时刻完成偏压补偿后在待加工工件表面上产生的偏压；由于在执行n＝1的第一次循环时，上一时刻为t＝0时刻，未执行偏压补偿操作，故规定第三偏压V0'在数值上等于第一偏压V0。
步骤S104：将在当前的脉冲开启时间的tn时刻偏压射频源的输出电压实时调整为tn-1时刻偏压射频源的输出电压与差值V之和。
步骤S105：检测并记录完成偏压补偿后在所述待加工工件表面上产生的第三偏压Vn’。
步骤S106：判断n是否等于N。如果是，则步骤结束。如果否，则将n替换为n+1,并依次执行步骤S102至步骤S106。
由上可知。从n＝1，循环往复执行步骤S102至步骤S106，直至n＝N，上述步骤结束，即脉冲关闭。脉冲关闭前一时刻的实际电压即为脉冲开启时间最后时刻的目标电压值。脉冲关闭之后，电子进入刻蚀槽底部，中和正电荷，使晶片表面偏压恢复为0V。
上述按脉冲周期向所述基座加载偏压功率的方法可实现在工艺过程中对晶片表面上产生的偏压进行实时动态调整补偿，使晶片表面达到如图4所示的补偿效果。其中，N值越大，补偿效果越好。
其中，上述各个循环中第二偏压的检测与输出电压由初始电压值增加至目标电压值是在相同的工艺条件下进行，即，该检测与电压的增大过程是在相同的脉冲开启时间，相同的脉冲功率和脉冲占空比，以及相同的初始电压值下进行，以确保检测获得的待加工工件表面损失的偏压恰好等于待加工工件表面损失的偏压的补偿量，从而使待加工工件表面的负偏压保持在恒定的初始电压水平，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
可选地，如图2所示，在向基座加载偏压功率期间，例如，在脉冲开启时间T1内，偏压射频源的输出电压呈线性增加。当偏压射频源输出的脉冲波形为方波时，待加工工件上的正电荷积累基本呈线性趋势，因此，通过使偏压射频源的输出电压呈线性增加，能够相应地对线性增加的正电荷进行抵消，从而使待加工工件上获得满足要求的负偏压水平。
其中，偏压射频源的输出电压的初始电压值为Vs，目标电压值为Vt。偏压射频源的输出电压呈线性增大的斜率为：
K＝tanθ＝(Vt-Vs)/T1；
其中，Vt为目标电压值，Vs为初始电压值，T1为脉冲开启时间。上述斜率K越大，则说明偏压射频源的输出电压增加的速度越快；反之，上述斜率K越小，则说明偏压射频源的输出电压增加的速度越慢。
以偏压射频源输出脉冲的电感耦合等离子体刻蚀设备为例，偏压射频源为可输出如图2所示波形的新型脉冲调制射频源。脉冲调制射频源用于向基座加载负偏压，以使置于基座上的待刻蚀晶片表面产生负偏压，以吸引等离子体向待刻蚀晶片表面轰击。
如图4所示，在进行刻蚀工艺的过程中，脉冲调制射频源输出脉冲频率为50Hz，占空比为60％，初始电压值Vs为300V。当脉冲的占空比设定为60％时，脉冲开启和关闭阶段待刻蚀晶片表面偏压由300V降低至200V，即 偏压损失了100V。因此，为了对待刻蚀晶片表面的偏压损失进行补偿，脉冲调制射频源输出的目标电压值Vt应增加为400V，以补偿上述损失的100V偏压，即脉冲调制射频源输出的初始电压值Vs与目标电压值Vt的电压比Vr为0.75。此时，偏压射频源输出的脉冲调制波形及对应的待刻蚀晶片表面的负偏压如图4所示。脉冲开启阶段(Pulse on)，输出偏压由300V线性增加至400V，线性增加斜率tanθ＝(400V-300V)/12ms，从而补偿了待刻蚀晶片表面因正电荷积累造成的负偏压损失，使得待刻蚀晶片表面偏压维持在初始电压值Vs水平不变，从而使待加工工件表面的负偏压保持在恒定的初始电压水平，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
在脉冲关闭阶段(Pulse off)，自由电子进入待刻蚀晶片表面的刻蚀槽中和其中的正电荷，使得待刻蚀晶片表面恢复到零电势；如此反复。从图4中可以看出在脉冲开启时间内，对脉冲进行调制之后解决了待刻蚀晶片表面由于正电荷积累造成的负偏压下降问题，从而相对现有技术保持了预期的刻蚀速率，进而保证了晶片的产能。
需要说明的是，在脉冲的开启时间T1内，输出的脉冲电压也可以非线性增加。非线性增加的电压能够相应地对非线性增加的积累正电荷进行抵消，从而使待处理晶片上获得满足要求的负偏压水平。
可选的，如图2所示，初始电压值Vs与目标电压值Vt的比值的取值范围在0.1-0.9。在该范围内调整初始电压值Vs与目标电压值Vt的比值，可以实现对待处理晶片表面偏压损失的适当补偿，从而能够根据对待处理晶片的不同的处理工艺目标要求，对待处理晶片的处理速率进行调控，进而实现对晶片处理速率的精确调控，提升晶片处理质量，保证晶片产能。
在本实施例中，偏压射频源为脉冲调制射频源，其输出的脉冲的脉冲频率f＝1/(T1+T2)，且脉冲频率f的调整范围为10Hz-20KHz。脉冲的占空比 D＝T1/(T1+T2)调整范围为10％-90％。脉冲调制射频源的射频频率为2MHz、13.56MHz或60MHz等。本实施例中的偏压调制方法不仅适用于电感耦合等离子处理工艺(ICP)，而且适用于电容耦合等离子体处理工艺(CCP)、微波等离子体处理工艺和微波电子回旋共振等离子体处理工艺(ECR)。
综上所述，本发明实施例提供的偏压调制方法、偏压调制***和等离子体处理设备的技术方案中，在向基座加载偏压功率期间，增大偏压射频源的输出电压，以使该输出电压由初始电压值增加至目标电压值。由于偏压射频源的输出电压逐渐增大，这使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够全部或部分补偿因逐渐累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
实施例2：
本实施例提供一种偏压调制***，如图5所示，用于对放置在基座10表面的待加工工件的负偏压进行调制。该偏压调制***包括偏压射频源7和电压调整模块,其中，偏压射频源7与用于承载待加工工件的基座10电连接，用于向基座10加载偏压功率，以使待加工工件的表面产生负偏压。电压调整模块9与偏压射频源7电连接，用于在偏压射频源向所述基座加载偏压功率期间，增大偏压射频源的输出电压，以使输出电压由初始电压值增加至目标电压值，从而使在待加工工件表面上产生的负偏压在偏压射频源向基座加载偏压功率期间保持在预设范围。
借助电压调整模块9，可以使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够全部或部分补偿因逐渐累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表 面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
其中，待加工工件为待处理晶片4。
在本实施例中，如图5所示，电压调整模块9包括时钟发生器91、电压传感器92和数字处理器93，其中，时钟发生器91能够发出与偏压射频源同步的时钟信号。电压传感器92与时钟发生器91进行通信，以能够在脉冲开启时间内检测在待加工工件表面上产生的负偏压。数字处理器93与电压传感器92进行通信，用于接收来自电压传感器92发送的负偏压，并根据该负偏压计算获得输出电压调整值，并将偏压射频源的输出电压调整为输出电压调整值，以使在待加工工件表面上产生的负偏压在向基座加载偏压功率期间保持在预设值。
其中，电压传感器92检测t＝0时，在待加工工件表面上产生的第一偏压V0；该第一偏压V0等于所述初始电压值，和检测在当前的脉冲开启时间的tn时刻，在所述待加工工件表面上产生的第二偏压Vn；其中，
tn＝n(T1/N)
N≥100，且N为整数；1≤n≤N，且n为整数；T1为脉冲开启时间的长度；
当n＝N时，在tn时刻，偏压射频源的输出电压为目标电压值；以及检测并记录完成偏压补偿后在待加工工件表面上产生的第三偏压Vn’。
数字处理器93接收并记录来自电压传感器92发送的第一偏压V0、所述第二偏压Vn和所述第三偏压Vn’，并执行：
计算第二偏压Vn与第三偏压Vn-1’的差值V；其中，该第三偏压Vn-1’为在上一时刻完成偏压补偿后在待加工工件表面上产生的偏压；V0'等于第一 偏压V0。
然后，数字处理器93将在当前的脉冲开启时间的tn时刻偏压射频源的输出电压实时调整为tn-1时刻偏压射频源的输出电压与差值V之和。
之后，数字处理器93判断n是否等于N，如果是，则指令电压传感器92停止检测工作，和停止调整偏压射频源的输出电压；如果否，则控制电压传感器82继续检测工作，和实时调整偏压射频源的输出电压。
其中，时钟发生器91用于产生方波脉冲，方波脉冲的脉冲周期为T1/N。偏压射频源7为可输出如图2所示波形的新型脉冲调制射频源。时钟发生器91产生的方波脉冲输入至电压传感器92中。其中N为大于0的整数，为保证电压补偿的及时性和有效性，一般选取N≥100，N值越大，补偿效果越好。电压传感器92负责进行晶片4表面第一偏压和第二偏压的检测，其进行检测的时刻由时钟发生器91输出的方波脉冲控制，可设置为脉冲上升沿或下降沿触发检测动作，其中，n为时钟发生器91方波脉冲的计数值。数字处理器93负责对电压传感器92的检测数据进行接收、记录和运算，其运算的结果反馈至偏压射频源7，使得偏压射频源7可根据反馈的结果实时进行输出脉冲电压的调整。
在本实施例中，通过电压调整模块9中的各器件按脉冲周期向基座加载偏压功率的具体过程为：偏压射频源7与时钟发生器92同时输出脉冲，假设偏压射频源7起始输出电压为(Vs)0＝V0′，开始的瞬间(t＝0)，电压传感器92检测当前晶片4表面的第一偏压V0＝(Vs)0＝V0′，并输送到数字处理器93中进行记录保存。
假设n为大于0的整数，初始值为1，n值可以改变，并保存在数字处理器93中。时钟发生器91输出的下一个脉冲上升沿/下降沿到来时，即t＝n*(T1/N)时刻(n＝1)，电压传感器92的检测动作被触发，检测得到晶片4表面的第二偏压V1，并将此结果发送至数字处理器93中。数字处理器93 对检测结果进行运算，得到V＝V1-V0′，V即为需要补偿的电压，并将结果V反馈至偏压射频源7中，偏压射频源7根据反馈结果进行即时的输出电压调整(Vs)1＝(Vs)0+V。如此循环往复，直至n＝N，脉冲关闭。脉冲关闭前一时刻偏压射频源7输出的电压即为脉冲开启时间内最后时刻的目标电压。脉冲关闭后，电子进入刻蚀槽底部，中和正电荷，使晶片4偏压恢复为0V。
该射频脉冲调制***可实现工艺过程中晶片4表面偏压的实时动态补偿，达到如图4所示的补偿效果。
本实施例中的偏压调制***，通过设置电压调整模块，可以使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够全部或部分补偿因逐渐累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理，使其电学性能满足要求。
实施例3：
本实施例提供一种等离子体处理设备，包括用于承载待加工工件的基座，以及上述实施例2中的偏压调制***，该偏压调制***与基座电连接。
其中，等离子体处理设备还包括等离子体发生装置，其包括线圈和与该线圈连接的上电极射频源，上电极射频源为连续波射频源或脉冲调制射频源。
通过采用上述实施例2中的偏压调制***，可以使得在待加工工件表面上产生的负偏压逐渐增大，而负偏压的增大量能够全部或部分补偿因逐渐累积到待加工工件表面的正离子产生的正电势而损失的偏压，也就是说，虽然正电势会减小晶圆表面的负偏压，但是负偏压的减小量与负偏压的增大量基本持平，从而可以使负偏压保持在预设范围内，进而不仅可以避免等离子体处理速率降低，保证产能，而且可以保证使待加工工件表面能够被充分处理， 使其电学性能满足要求。。
另外,值得注意的是,本发明的偏压调制方法、偏压调制***以及包括该偏压调制***的等离子体处理设备，不限于电感耦合等离子体产生、电容耦合等离子体产生中出现的负偏压损失的问题，上述设定的电感耦合等离子体或电容耦合等离子体产生仅为了说明本发明的具体实施方式，并不用于对本发明进行限制。只要存在待加工工件表面的负偏压损失的问题，那么就可以采用本发明的偏压调制方法，偏压调制***及等离子体处理设备解决存在的技术问题。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (13)

  1. 一种偏压调制方法，其特征在于，包括：
    在向用于承载待加工工件的基座加载偏压功率期间，增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值，从而使所述待加工工件表面上产生的负偏压在向所述基座加载偏压功率期间保持在预设范围内。
  2. 根据权利要求1所述的偏压调制方法，其特征在于，所述目标电压值与所述初始电压值的差值等于负偏压损失值，所述负偏压损失值为在向所述基座加载偏压功率期间，所述偏压射频源的输出电压保持所述初始电压值不变时，在所述待加工工件表面上产生的负偏压的损失值。
  3. 根据权利要求1或2所述的偏压调制方法，其特征在于，按脉冲周期向所述基座加载偏压功率；
    其中，所述脉冲周期包括脉冲开启时间和脉冲关闭时间，在所述脉冲开启时间，向所述基座加载偏压功率，同时增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值；在所述脉冲关闭时间，停止向所述基座加载偏压功率。
  4. 根据权利要求3所述的偏压调制方法，其特征在于，在所述脉冲开启时间向所述基座加载偏压功率，具体包括以下步骤：
    步骤S101：检测并记录t＝0时，在所述待加工工件表面上产生的第一偏压V0；所述第一偏压V0等于所述初始电压值；
    步骤S102：检测并记录在当前的脉冲开启时间的tn时刻，在所述待加工工件表面上产生的第二偏压Vn；其中，
    tn＝n(T1/N)
    N≥100，且N为整数；1≤n≤N，且n为整数；T1为所述脉冲开启时间的长度；
    当n＝N时，在tn时刻，所述偏压射频源的输出电压为所述目标电压值；
    步骤S103：计算所述第二偏压Vn与第三偏压V’n-1的差值V；其中，所述第三偏压V’n-1为在上一时刻完成偏压补偿后在所述待加工工件表面上产生的偏压；第三偏压V0'等于第一偏压V0；
    步骤S104：将在当前的脉冲开启时间的tn时刻所述偏压射频源的输出电压实时调整为tn-1时刻所述偏压射频源的输出电压与所述差值V之和；
    步骤S105：检测并记录完成偏压补偿后在所述待加工工件表面上产生的第三偏压Vn’；
    步骤S106：判断n是否等于N；如果是，则步骤结束；如果否，则将n替换为n+1,并依次执行所述步骤S102至步骤S106。
  5. 根据权利要求1或2所述的调制方法，其特征在于，所述初始电压值与所述目标电压值的比值的取值范围在0.1-0.9。
  6. 根据权利要求1所述的调制方法，其特征在于，在向所述基座加载偏压功率期间，所述偏压射频源的输出电压呈线性增大。
  7. 根据权利要求6所述的调制方法，其特征在于，所述偏压射频源的输出电压呈线性增大的斜率为：
    K＝(Vt-Vs)/T1；
    其中，Vt为所述目标电压值，Vs为所述初始电压值，T1为所述脉冲开启时间。
  8. 一种偏压调制***，其特征在于，包括：
    偏压射频源,所述偏压射频源与用于承载待加工工件的基座电连接，用 于向所述基座加载偏压功率；
    电压调整模块，所述电压调整模块与所述偏压射频源电连接，用于在所述偏压射频源向所述基座加载偏压功率期间，增大所述偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值，从而使在所述待加工工件表面上产生的负偏压在所述偏压射频源向所述基座加载偏压功率期间保持在预设范围。
  9. 根据权利要求8所述的偏压调制***，其特征在于，所述偏压射频源为脉冲调制射频源，以能够按脉冲周期向所述基座加载偏压功率；其中，
    所述脉冲周期包括脉冲开启时间和脉冲关闭时间，在所述脉冲开启时间，所述偏压射频源向所述基座加载偏压功率，同时所述电压调整模块增大偏压射频源的输出电压，以使所述输出电压由初始电压值增加至目标电压值；在所述脉冲关闭时间，所述偏压射频源停止向所述基座加载偏压功率。
  10. 根据权利要求9所述的偏压调制***，其特征在于，所述电压调整模块包括：
    时钟发生器，所述时钟发生器能够发出与所述偏压射频源同步的时钟信号；
    电压传感器，所述电压传感器与所述时钟发生器进行通信，以能够在所述脉冲开启时间内检测在所述待加工工件表面上产生的负偏压；
    数字处理器，所述数字处理器与所述电压传感器进行通信，用于接收来自所述电压传感器发送的所述负偏压，并根据该负偏压计算获得输出电压调整值，并将所述偏压射频源的输出电压调整为所述输出电压调整值，以使在所述待加工工件表面上产生的负偏压在向所述基座加载偏压功率期间保持在预设值。
  11. 根据权利要求10所述的偏压调制***，其特征在于，所述电压传感 器检测t＝0时，在所述待加工工件表面上产生的第一偏压V0；所述第一偏压V0等于所述初始电压值；和检测在当前的脉冲开启时间的tn时刻，在所述待加工工件表面上产生的第二偏压Vn；其中，
    tn＝n(T1/N)
    N≥100，且N为整数；1≤n≤N，且n为整数；T1为所述脉冲开启时间的长度；
    当n＝N时，在tn时刻，所述偏压射频源的输出电压为所述目标电压值；以及检测并记录完成偏压补偿后在所述待加工工件表面上产生的第三偏压Vn’。
  12. 根据权利要求11所述的偏压调制***，其特征在于，所述数字处理器接收并记录来自所述电压传感器发送的所述第一偏压V0、所述第二偏压Vn和所述第三偏压Vn’，并执行：
    计算所述第二偏压Vn与第三偏压Vn-1’的差值V；其中，所述第三偏压Vn-1’为在上一时刻完成偏压补偿后在所述待加工工件表面上产生的偏压；V0'等于第一偏压V0；
    将在当前的脉冲开启时间的tn时刻所述偏压射频源的输出电压实时调整为tn-1时刻所述偏压射频源的输出电压与所述差值V之和；
    判断n是否等于N；如果是，则控制所述电压传感器停止检测工作，和停止调整所述偏压射频源的输出电压；如果否，则控制所述电压传感器继续检测工作，和实时调整所述偏压射频源的输出电压。
  13. 一种等离子体处理设备，包括：用于承载待加工工件的基座，其特征在于，
    还包括权利要求8-12任一项所述偏压调制***，所述偏压调制***与所述基座电连接。
PCT/CN2018/088818 2017-06-23 2018-05-29 偏压调制方法、偏压调制***和等离子体处理设备 WO2018233455A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102983099A (zh) * 2011-09-07 2013-03-20 中国科学院微电子研究所 半导体集成电路制造方法
CN105070627A (zh) * 2015-07-15 2015-11-18 大连理工大学 一种减少基片材料受高能离子轰击损伤的方法
US20160172216A1 (en) * 2014-12-15 2016-06-16 Lam Research Corporation Ion Energy Control By RF Pulse Shape

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102983099A (zh) * 2011-09-07 2013-03-20 中国科学院微电子研究所 半导体集成电路制造方法
US20160172216A1 (en) * 2014-12-15 2016-06-16 Lam Research Corporation Ion Energy Control By RF Pulse Shape
CN105070627A (zh) * 2015-07-15 2015-11-18 大连理工大学 一种减少基片材料受高能离子轰击损伤的方法

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