WO2018233368A1 - 像素电路、显示装置以及驱动方法 - Google Patents

像素电路、显示装置以及驱动方法 Download PDF

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Publication number
WO2018233368A1
WO2018233368A1 PCT/CN2018/083705 CN2018083705W WO2018233368A1 WO 2018233368 A1 WO2018233368 A1 WO 2018233368A1 CN 2018083705 W CN2018083705 W CN 2018083705W WO 2018233368 A1 WO2018233368 A1 WO 2018233368A1
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Prior art keywords
liquid crystal
gray scale
transistor
gray
crystal capacitor
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PCT/CN2018/083705
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English (en)
French (fr)
Inventor
陈鹏名
张斌
董殿正
张强
王光兴
张衎
许文鹏
郭子强
路永全
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US16/308,437 priority Critical patent/US11081040B2/en
Publication of WO2018233368A1 publication Critical patent/WO2018233368A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0248—Precharge or discharge of column electrodes before or after applying exact column voltages
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of liquid crystal display technologies, and in particular, to a pixel circuit, a display device, and a driving method.
  • the conventional pixel structure is 1T1C (ie, 1 transistor + 1 capacitor).
  • an external Gamma circuit is required to give multiple fixed binding voltages, and then pass through the internal source of the source driver.
  • the resistor string is finely divided to obtain a 6-bit voltage value, and then digital-to-analog conversion is performed to charge the liquid crystal capacitor of the pixel circuit to generate a corresponding pixel voltage, so that the logic power consumption obtained is large.
  • the gray scale voltages of the RGB sub-pixels are shared, and the control cost of implementing the 8-bit voltage value is high.
  • the source driver is divided into 6-bit voltage values, and then passed through the FRC (Frame Rate Control) of the timing controller.
  • the pixel dithering algorithm obtains the effect of 8 bit voltage value, but the FRC algorithm causes more defects and the debugging period is longer.
  • the liquid crystal display driving method is progressive scanning or interlaced scanning, and the source driving circuit writes the gray scale voltage to the pixel electrode row by row or interlaced.
  • This driving method has an RC delay (RC delay), and the delay is high resolution.
  • ultra-high resolution liquid crystal display is particularly obvious, and it has become one of the bottlenecks in designing ultra-high resolution liquid crystal display panels. As the resolution increases, there is also a problem of insufficient charging of the pixel electrode.
  • the present disclosure provides a pixel circuit, a display device, and a driving method.
  • a pixel circuit includes: a liquid crystal capacitor having a first end and a second end; and a selection unit having a first end, a second end, and an output, the first end of the selection unit For receiving a column control signal, the second end of the selecting unit is configured to receive a row control signal, and the selecting unit is configured to determine whether to charge the liquid crystal capacitor according to the row control signal and the column control signal; a step writing unit having a first end, a second end, and an output end, wherein the first end of the gray scale writing unit is connected to the output end of the selecting unit, and the second end of the gray scale writing unit is a gray scale voltage signal is connected, an output end of the gray scale writing unit is connected to a second end of the liquid crystal capacitor, and the gray scale writing unit is configured to when the selecting unit determines to charge the liquid crystal capacitor Applying the gray scale voltage signal to the liquid crystal capacitor, and an application duration of the gray scale voltage signal controls a gray scale level displayed by the liquid crystal capacitor; and
  • the selecting unit includes:
  • the first transistor and the second transistor each have a first end, a second end and a control end, the control end of the first transistor is connected to the column control signal, and the first end of the first transistor is connected to the row control a signal, a second end of the first transistor is coupled to the first end of the second transistor, and a control terminal of the second transistor is coupled to the row control signal.
  • the gray scale writing unit includes a third transistor having a first end, a second end, and a control end, and a control end of the third transistor is connected to the second transistor
  • the second end of the third transistor is connected to the gray scale voltage signal, and the second end of the third transistor is connected to the second end of the liquid crystal capacitor.
  • the reset unit includes:
  • each of the fourth transistor and the fifth transistor having a first end, a second end, and a control end, the storage capacitor having a first end and a second end,
  • the control terminals of the fourth transistor and the fifth transistor are both connected to the reset signal, and the first ends of the fourth transistor, the fifth transistor and the storage capacitor are connected to the second end of the second transistor
  • the second end of the fourth transistor is connected to the common voltage signal
  • the second end of the fifth transistor and the storage capacitor is connected to the first end of the liquid crystal capacitor, and the second end of the liquid crystal capacitor is connected The common voltage signal.
  • a display device comprising: a display panel having a plurality of pixel circuits arranged in an array; the timing controller configured to determine the image according to image information to be displayed The grayscale level to be displayed by each of the pixel circuits in the display panel, and the liquid crystal capacitor is displayed to display a corresponding grayscale level by controlling a charging duration of the liquid crystal capacitor in the pixel circuit.
  • the timing controller includes:
  • a gray scale control unit configured to sequentially apply a gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the same gray scale according to the gray scale level;
  • a charging control unit configured to simultaneously stop applying the gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits in the display panel to control a charging duration of the liquid crystal capacitors in each of the pixel circuits.
  • the grayscale control unit is specifically configured to:
  • the gray scale voltage After the gray scale voltage signals are applied to all the liquid crystal capacitors corresponding to the first gray scales, the gray scale voltage starts to be applied to the liquid crystal capacitors in all the pixel circuits corresponding to the second gray scales. The signal is applied until the liquid crystal capacitors in all of the pixel circuits corresponding to the gray level of the previous stage of the last stage start to apply the gray scale voltage signal.
  • a driving method of a pixel circuit including:
  • the gray level of the capacitor is determined by the duration of application of the gray scale voltage signal.
  • a driving method of a display device including:
  • the liquid crystal capacitor displays a corresponding gray scale level by controlling a charging duration of the liquid crystal capacitor in the pixel circuit.
  • controlling the display of the corresponding gray level by the liquid crystal capacitor by controlling the charging duration of the liquid crystal capacitor in the pixel circuit includes:
  • the gray scale voltage signal is stopped from being applied to the liquid crystal capacitors in all the pixel circuits in the display panel to control the charging duration of the liquid crystal capacitors in each of the pixel circuits.
  • the sequentially applying the grayscale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the gray level of the same level according to the grayscale level includes:
  • the gray scale voltage After the gray scale voltage signals are applied to all the liquid crystal capacitors corresponding to the first gray scales, the gray scale voltage starts to be applied to the liquid crystal capacitors in all the pixel circuits corresponding to the second gray scales. The signal is applied until the liquid crystal capacitors in all of the pixel circuits corresponding to the gray level of the previous stage of the last stage start to apply the gray scale voltage signal.
  • the display panel displays a frame time of 1/(reset rate*number of grayscale levels), wherein the number of grayscale levels is all of the picture The number of grayscale levels, the refresh rate being the number of times the display panel is refreshed in one second.
  • determining the grayscale level to be displayed by each of the pixel circuits in the display panel includes:
  • FIG. 1 is a schematic structural diagram of a pixel circuit provided in an embodiment of the present disclosure.
  • FIG. 2 shows a circuit diagram of a pixel circuit corresponding to FIG. 1 in the embodiment of the present disclosure.
  • FIG. 3 is a flow chart showing the steps of a driving method for a pixel circuit in an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a display device according to another embodiment of the present disclosure.
  • FIG. 5 is a schematic diagram showing an array structure of a display panel in another embodiment of the present disclosure.
  • FIG. 6 shows a schematic diagram of a processor in another embodiment of the present disclosure.
  • FIG. 7 is a flow chart showing a driving method of a display device according to still another embodiment of the present disclosure.
  • FIG. 8 is a timing waveform diagram showing a row control signal outputted by the timing controller Tcon in still another embodiment of the present disclosure.
  • Figure 9 shows a schematic diagram of the gray scale voltages required to display an image.
  • FIG. 10 is a timing chart showing control signals for displaying the gray scale voltage corresponding to L255 at the time of the first progressive scan of the scanning line.
  • Fig. 11 is a timing chart showing control signals for displaying the gray scale voltage corresponding to L254 when the scan line is subjected to the second progressive scan.
  • Fig. 12 is a timing chart showing the control signal for displaying the gray scale voltage corresponding to L1 when the scanning line is 255th progressive scan.
  • Fig. 13 is a timing chart showing the control signal for displaying the gray scale voltage corresponding to L0 when the scanning line is scanned for the 256th line.
  • the transistor used in the embodiment of the present invention may be a thin film transistor or a field effect transistor or the like having the same characteristics. Since the source and the drain of the transistor used are symmetrical, the source and the drain are indistinguishable. . In the embodiment of the present invention, in order to distinguish the source and the drain of the transistor, respectively referred to as a first end and a second end, the gate is referred to as a control end. In addition, according to the characteristics of the transistor, the transistor can be divided into an N-type transistor and a P-type transistor.
  • the first end is the source of the N-type transistor
  • the second end is the drain of the N-type transistor
  • the source and drain are turned on when the gate input is high; conversely, when the P-type transistor is used, The source and drain are turned on when the gate input is low.
  • the description is made with an N-type transistor. It is conceivable that the implementation of the P-type transistor can be easily conceived by those skilled in the art without requiring creative work, and thus is also within the scope of protection of the embodiments of the present invention. Within.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit 100 includes a liquid crystal capacitor Clc, a selection unit 101, a gray scale writing unit 102, and a reset unit 103.
  • the liquid crystal capacitor Clc has two ends, which are a first end and a second end, respectively.
  • the selecting unit 101 has a first end, a second end and an output end, the first end of the selecting unit 101 is for receiving the column control signal, and the second end of the selecting unit 101 is for receiving the row control signal, wherein the row control signal is the scan line The scan signal provided by S, and the column control signal is the data signal provided by data line D.
  • the selecting unit 101 is configured to determine whether to charge the liquid crystal capacitor Clc according to the row control signal and the column control signal.
  • the gray-scale writing unit 102 has a first end, a second end, and an output end, and the first end of the gray-scale writing unit 102 is connected to the output end of the selecting unit 101, and the gray-scale writing unit 102 The second end is connected to the gray scale voltage signal Von, and the output end of the gray scale writing unit 102 is connected to the first end of the liquid crystal capacitor Clc.
  • the gray scale writing unit 102 is configured to apply a gray scale voltage signal Von to the liquid crystal capacitor Clc when the selecting unit 101 determines to charge the liquid crystal capacitor Clc, and the application duration of the gray scale voltage signal controls the gray scale level displayed by the liquid crystal capacitor Clc.
  • the reset unit 103 has a first end, a second end, a third end, and a fourth end, the first end of the reset unit 103 is connected to the reset signal Voff, and the second end of the reset unit 103 is connected to the selection unit 101.
  • the output terminal is connected, the third terminal of the reset unit 103 is connected to the output terminal of the gray scale write unit 102, and the fourth terminal of the reset unit 103 is connected to the common voltage signal Vcom.
  • the reset unit 103 is configured to disconnect the gray scale writing unit 102 and the liquid crystal capacitor Clc when the reset signal Voff is received to stop charging the liquid crystal capacitor Clc and reset the voltage of the liquid crystal capacitor Clc to an initial state.
  • the reset unit 103 is configured to start the display of the next frame by the reset signal after completing the display of all the grayscale levels of one frame.
  • the pixel circuit includes transistors T1, T2, T3, T4, T5, a liquid crystal capacitor Clc, and a storage capacitor C1, in addition to which
  • the gray scale voltage signal Von, the reset signal Voff, and the common voltage signal Vcom are three electrode signals and the two control lines of the scan line S and the data line D.
  • the selection unit 101 includes: a first transistor T1 and a second transistor T2, each having a first end, a second end, and a control end, wherein the control end of the first transistor T1 is connected to the column control signal, The first end of the transistor T1 is connected to the row control signal, the second end of the first transistor T1 is connected to the first end of the second transistor T2, and the control terminal of the second transistor T2 is connected to the row control signal. If the transistors in the circuit of the embodiment are all based on an N-type transistor, when the row control signal is at a high level, the second transistor T2 is turned on, and when the corresponding column control signal is at a high level, the first transistor T1 is also turned on.
  • the gray-scale writing unit 102 includes a third transistor T3 having a first end, a second end, and a control end.
  • the control end of the third transistor T3 is connected to the second end of the second transistor T2, and the first end of the third transistor T3 is connected.
  • the gray-scale voltage signal Von, the second end of the third transistor T3 is connected to the second end of the liquid crystal capacitor Clc.
  • the gray scale voltage signal Von provides a positive/negative voltage to the pixel electrode, and the value can be 2Vcom or 0.
  • the reset unit 103 includes a fourth transistor T4, a fifth transistor T5, and a storage capacitor C1.
  • the fourth transistor T4 and the fifth transistor T5 each have a first end, a second end, and a control end.
  • the storage capacitor C has a first end and a first end.
  • the control terminals of the fourth transistor T4 and the fifth transistor T5 are both connected to the reset signal Voff, and the first ends of the fourth transistor T4, the fifth transistor T5 and the storage capacitor C1 are connected to the second end of the second transistor T2,
  • the second end of the fourth transistor T4 is connected to the common voltage signal Vcom
  • the second end of the fifth transistor T5 and the storage capacitor C1 is connected to the first end of the liquid crystal capacitor Clc
  • the second end of the liquid crystal capacitor Clc is connected to the common voltage signal Vcom.
  • the reset signal Voff is at a low level, and the fourth transistor T4 and the fifth transistor T5 are turned off. Therefore, when the first transistor T1 and the second transistor T2 are turned on, the storage capacitor C1 is also charged until all the grayscale levels are displayed.
  • the reset signal Voff is set to a high level, the fourth transistor T4 and the fifth transistor T5 are turned on, and the storage capacitor C1 and the liquid crystal capacitor Clc are discharged, and the next frame display is started.
  • the scan line is rapidly progressively scanned at the beginning of each frame, and the data signal outputted by the data line turns on the T1 of the pixel structure of the current scan line that needs to display the L255 gray scale, and C1 is charged and T3 is simultaneously charged.
  • Clc is charged to the Von voltage for display.
  • Tcon waits for t, all the pixel structures T1 that need to display the L254 gray scale are turned on by the row control signal and the column control signal, so that the Clc is charged with the Von voltage for display.
  • T1 of each gray scale pixel structure is turned on one by one in a gray scale decreasing manner, and the corresponding Clc is charged into the voltage Von for display.
  • the original progressive charging driving method is changed to charge the same voltage one by one with the control signal timing, and the Clc pixel electrode voltage holding time determines the gray scale brightness, instead of Fixed position sequential charging method, by increasing the charging time of the pixel electrode, increasing the charging rate, eliminating the design of the resistor string in the source driving circuit, the power consumption can be greatly reduced, and the gamma voltage correction can be separately performed on the RGB, It is necessary to adjust the ACC on a common voltage basis, thereby saving IC cost and making it easier to implement 8-bit and above control.
  • FIG. 3 is a flow chart showing the steps of the driving method for the above pixel circuit in the embodiment of the present disclosure.
  • step S11 it is determined whether or not to charge the liquid crystal capacitor Clc based on the row control signal and the column control signal.
  • step S12 when it is determined that the liquid crystal capacitor Clc is charged, a gray scale voltage signal is applied to the liquid crystal capacitor Clc.
  • the grayscale level of the liquid crystal capacitor in the embodiment is determined by the application duration of the grayscale level signal.
  • step S13 upon receiving the reset signal, charging of the liquid crystal capacitor Clc is stopped, and the voltage of the liquid crystal capacitor Clc is reset to the initial state. That is to say, when all the grayscale levels of the pixels are displayed, the voltage charged in the liquid crystal capacitor Clc is released by the reset signal, and the display of the next frame is turned on.
  • the pixel charging time is 1/(the refresh rate*the number of grayscale levels), and the refresh rate is usually 60-75HZ.
  • the display device 100 includes a display panel 110 and a timing controller 120, wherein the display panel 110 has a plurality of arrays arranged in an array. a pixel circuit, the timing controller 120 is configured to determine, according to the image information to be displayed, a grayscale level to be displayed by each pixel circuit in the display panel, and control a liquid crystal capacitor to display a corresponding grayscale by controlling a charging duration of the liquid crystal capacitor in the pixel circuit. grade.
  • the timing controller 120 also controls the row control signal, the column control signal, the gray scale voltage signal, and the reset signal supplied to the display panel 110 through timing control signals.
  • FIG. 5 shows A schematic diagram of an array structure of a display panel in another embodiment of the present disclosure, as shown in FIG. 5, includes three scan lines S1, S2, S3 and four data lines D1, D2, D3, and D4.
  • the display panel according to the embodiment of the present disclosure may of course include more other numbers of scan lines and data lines, and the present invention Not limited to this.
  • reset signal Voff in FIG. 5 is both controlled and provided by the timing controller 130.
  • FIG. 6 shows a schematic diagram of a processor in this embodiment.
  • the timing controller 120 includes a grayscale control unit 121 and a charging control unit 122.
  • the gray scale control unit 121 is configured to sequentially apply a gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the same gray scale according to the gray scale level.
  • the charging control unit 122 is configured to simultaneously stop applying a gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits in the display panel to control the charging duration of the liquid crystal capacitors in each pixel circuit.
  • the grayscale control unit 121 in this embodiment is specifically configured to determine location information of all pixel circuits corresponding to the grayscale corresponding to the first level in the display panel; and is further configured to generate corresponding row control signals and columns according to the location information. a control signal; and is further configured to apply a gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the first gray scale by row control by the row control signal and the column control signal; and also for all the corresponding gray scales in the first level
  • the gray scale voltage signal is started to be applied to the liquid crystal capacitors in all the pixel circuits corresponding to the second gray scale, until all the pixel circuits corresponding to the gray level of the first stage of the last stage are used.
  • the liquid crystal capacitor begins to apply a gray scale voltage signal.
  • the pixel circuit at the intersection of the scan line S1 and the data line D1 can be represented by coordinates (S1, D1) (since each pixel circuit is visible to the naked eye for the entire display panel is small
  • a bright spot which may also be referred to as a pixel point, determines the position of the pixel point to be displayed by the position module 1211, and then charges the liquid crystal capacitor to realize gray scale display of the pixel.
  • FIG. 7 is a flowchart of a driving method of a display device according to an embodiment of the present disclosure.
  • step S71 the grayscale level to be displayed by each pixel circuit in the display panel is determined.
  • the grayscale level to be displayed by each pixel circuit in the display panel may be determined according to image information to be displayed by the display device.
  • step S72 by controlling the charging duration of the liquid crystal capacitor in the pixel circuit, the liquid crystal capacitor displays the corresponding gray scale level.
  • the step of controlling the charging duration of the liquid crystal capacitor in the pixel circuit firstly, according to the gray level, sequentially applying the gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the gray level of the same level, and simultaneously The gray scale voltage signal is stopped from being applied to the liquid crystal capacitors in all the pixel circuits in the display panel to control the charging duration of the liquid crystal capacitors in each pixel circuit.
  • the step of sequentially applying a gray scale voltage signal to the liquid crystal capacitors in all the pixel circuits corresponding to the gray level corresponding to the same gray level according to the gray level first, all the corresponding gray levels of the first level are determined.
  • corresponding row control signals and column control signals are generated.
  • the gray scale voltage signal is applied to the liquid crystal capacitors in all the pixel circuits corresponding to the first-order gray scales by the row control signal and the column control signal.
  • the gray scale voltage signal is started to be applied to the liquid crystal capacitors in all the pixel circuits corresponding to the second gray scale, until the last stage is The liquid crystal capacitors in all the pixel circuits corresponding to the gray level of the previous stage start to apply the gray scale voltage signal.
  • all the grayscale levels may be displayed one by one according to the grayscale level incrementing or decrementing, and the same grayscale voltage signal is charged to the plurality of pixel circuits displaying the same grayscale level, and
  • the gray scale level of the corresponding pixel circuit is determined by controlling the length of time during which the gray scale voltage signal is applied to the liquid crystal capacitor Clc.
  • controlling the duration of applying the grayscale voltage signal to the liquid crystal capacitor includes: determining, by the row control signal and the column control signal, applying a grayscale voltage signal to the liquid crystal corresponding to the maximum grayscale level, and displaying all the grayscale voltage signals in the display panel The pixel circuits of the maximum gray level are all displayed, and then the next gray level is displayed in a grayscale decreasing manner until a gray scale voltage signal is applied to the liquid crystal capacitor corresponding to the gray level of the previous gray level of the minimum gray level. After one frame displays all grayscale levels, charging of the liquid crystal capacitor is stopped by applying a reset signal.
  • the next line of scanning may be performed without waiting for the current line liquid crystal capacitor Clc to be charged to the gray scale voltage signal.
  • the time of displaying one frame of the display panel is 1/(refresh rate*the number of grayscale levels), and the number of grayscale levels is the number of all grayscale levels of the screen.
  • the refresh rate is the number of times the display panel 110 is refreshed in one second, which can effectively increase the charging time of the pixel electrode and increase the charging rate.
  • FIG. 8 is a timing waveform diagram of a row control signal outputted by the timing controller Tcon in another embodiment of the present disclosure, and the scan lines S1, S2, . . . , Sn are turned on line by line, as shown in FIG.
  • the row control signals output by S2, ..., Sn become active high levels row by row.
  • the display panel is divided into a normal black mode and a normally white mode, and is respectively displayed in ADS (a type of IPS (In-Plane Switching) display mode) display mode and TN (Twisted Nematic) display mode.
  • ADS a type of IPS (In-Plane Switching) display mode
  • TN Transmission Nematic
  • the mode is an example.
  • the display principle of the pixel circuit and the pixel circuit array shown in FIG. 1 and FIG. 2 is introduced:
  • FIG. 9 is a schematic diagram of the gray scale voltage of the image to be displayed.
  • a part of the image to be displayed shown in FIG. 9 ie, 3 rows, 4 columns, and 12 pixel circuits from the upper left corner
  • the maximum gray level to be displayed is L255
  • the minimum gray level is L0.
  • Voff is set low to turn off T4 and T5, and Von is 2Vcom or 0 (to provide positive/negative voltage of the pixel electrode).
  • FIG. 10 is a timing chart showing control signals for displaying the gray scale voltage corresponding to L255 at the time of the first progressive scan of the scanning line.
  • the row control signal output by S1 is at a high level, and in the gray scale of the image to be displayed shown in FIG. 9, there are two L255s to be displayed in the first line.
  • the pixels of the gray scale that is, the (1, 1) and (1, 3) pixel points, so the column control signals output by the corresponding data lines D1 and D3 are active high level; the row control signal of the S2 output is high power In the gray line of the image to be displayed shown in FIG.
  • the second line has a pixel point of L255 gray scale to be displayed, that is, (2, 2) pixel points, and thus the column control signal outputted by the corresponding data line D2. It is an active high level; the row control signal of the S3 output is at a high level, and in the gray scale of the image to be displayed shown in FIG. 9, the third row has no L255 grayscale pixel points to be displayed, and thus the corresponding data line
  • the column control signals output by D1, D2 and D3 are all low level; the row control signal of S4 output is high level, and there are two L255s to be displayed in the fourth row of the gray scale of the image to be displayed shown in FIG. Grayscale pixels, ie (4, 2) and (4, 3) pixels, so the column control signals output by the corresponding data lines D2 and D3 are active high
  • Fig. 11 is a timing chart showing control signals for displaying the gray scale voltage corresponding to L254 when the scan line is subjected to the second progressive scan.
  • the line control signal output by S1 is at a high level, and in the gray line of the image to be displayed shown in FIG. 9, the first line has a L254 gray to be displayed.
  • the pixel points of the order that is, (1, 2) pixel points, so the column control signal outputted by the corresponding data line D2 is an active high level; the row control signal output by S2 is a high level, as shown in FIG.
  • the second row of the grayscale of the displayed image has two L254 grayscale pixels to be displayed, namely (2, 1) and (2, 3) pixels, so the column control signals output by the corresponding data lines D1 and D3 It is an active high level; the line control signal of the S3 output is high level, and the third line of the gray level of the image to be displayed shown in FIG. 9 has a pixel point of L254 gray scale to be displayed, that is, (3, 1) pixel point, so the column control signal outputted by the corresponding data line D1 is a valid high level; the row control signal output by S4 is a high level, and the fourth line in the gray scale of the image to be displayed shown in FIG. There is no pixel point of the L254 gray scale to be displayed, so the column control signals output by the corresponding data lines D1, D2 and D3 are all low level.
  • the times t255, t254 and t253 in the present embodiment are only used to distinguish the charging moments of different grayscale levels, and the waiting time tw is used to adjust the display duration of each grayscale level. .
  • the timing controller Tcon waits for the time tw and then the control signal for the next scan.
  • the pixel pixel electrode that needs to display the L (N) gray scale is charged with the Von voltage.
  • Fig. 12 is a timing chart showing the control signal for displaying the gray scale voltage corresponding to L1 when the scanning line is 255th progressive scan.
  • the row control signal output by S1 is at a high level, and the first row of the grayscale to be displayed as shown in FIG. 9 has no L1 grayscale to be displayed.
  • the second row and the fourth row of the gray scale also have no L1 grayscale pixel points to be displayed, so the column control signals output by the corresponding data lines D1, D2 and D3 are also low level; only the row of the S3 output
  • the control signal is at a high level, and in the gray line of the image to be displayed shown in FIG. 9, the third line has two L1 gray scale pixels to be displayed, that is, (3, 2) and (3, 3) pixel points. Therefore, the column control signals output by the corresponding data lines D2 and D3 are active high levels.
  • Fig. 13 is a timing chart showing the control signal for displaying the gray scale voltage corresponding to L0 when the scanning line is scanned for the 256th line.
  • the row control signals output by S1, S2, and S3 are at a high level, and the first row to the third in the gray scale of the image to be displayed shown in FIG.
  • Tcon waits for the time tw and sets Voff high. All T4 and T5 are turned on, all pixel electrode voltages are discharged to Vcom, and the next frame display starts.
  • next frame begins to repeat the action of the previous frame.
  • the above ADS is to apply gray scale voltage signals to the pixel capacitors corresponding to the gray scale levels according to the gray scale decreasing manner, and distinguish the different gray scale levels by decreasing the duration.
  • the following TN mode is in the normally white mode, according to the gray
  • the step-level increment method applies a gray-scale voltage signal to the pixel capacitance corresponding to each gray-scale level, and also divides the different gray-scale levels by decreasing the duration.
  • Voff is set low to turn off T4 and T5, and Von is set to 2Vcom or 0V.
  • T1 and T2 are simultaneously turned on, C1 is charged and the T3 gate is Set to high level, T3 is turned on, Clc is charged, due to the presence of C1, the T3 gate voltage will be gradually raised to T3 to open to the maximum, all line control signals can continue without waiting for the Clc pixel electrode to charge to Von Scan one line to increase the scan rate.
  • the row control signal is scanned to the last line, all pixel pixel electrodes that need to display the L2 gray level are charged to the Von voltage, which is recorded as t2;
  • Tcon waits for the time tw and sets Voff to high level. All T4 and T5 are turned on, all pixel electrode voltages are discharged to Vcom, and the next frame display starts.
  • next frame begins to repeat the action of the previous frame.
  • the T1 in each gray-scale pixel circuit is turned on one by one in a gray-scale increment manner, and the corresponding liquid crystal capacitor Clc is charged with a gray-scale voltage for display, and the timing chart of the control signal when each gray-scale voltage is displayed can be
  • the display principle is similar to that in the ADS display mode described above, and can be seen in FIG. 10 to FIG. 13 , and details are not described herein again.
  • the pixel circuit and the driving method provided by the embodiment adopt the same pixel voltage one by one gray scale, and control the Clc voltage holding time to obtain the corresponding gray level. Regardless of the resolution of the display panel, the charging time is 1/1. (Refresh rate* number of grayscale levels) s, effectively increasing the charging time and increasing the charging rate.
  • the embodiment can also solve the problem of uneven discharge caused by the progressive opening, and the Vcom electrode is connected to the pixel electrode after the shutdown, which can effectively solve the problem of poor startup sparking and drift caused by different discharge speeds of the pixel electrode and the Vcom electrode.

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Abstract

一种像素电路、显示装置（100）以及驱动方法，像素电路包括：液晶电容（Clc）、选择单元（101）、灰阶写入单元（102）和复位单元（103）；选择单元（101）用于根据行控制信号和列控制信号确定是否向液晶电容（Clc）充电；灰阶写入单元（102）用于当选择确定向液晶电容（Clc）充电时，向液晶电容（Clc）施加灰阶电压信号（Von），且灰阶电压信号（Von）的施加时长控制液晶电容（Clc）显示的灰阶等级；复位单元（103）用于在接收到复位信号（Voff）时，断开灰阶写入单元（102）和液晶电容（Clc）的连接以停止向液晶电容（Clc）充电，并使液晶电容（Clc）的电压复位到初始状态。

Description

像素电路、显示装置以及驱动方法
交叉引用
本公开要求于2017年6月23日递交的、申请号为：201710485858.5，发明创造名称为“像素电路、显示装置以及驱动方法”的中国专利申请的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及液晶显示技术领域，具体而言，涉及一种像素电路、显示装置以及驱动方法。
背景技术
对于液晶面板而言，传统的像素结构为1T1C(即1个晶体管+1个电容)，为实现不同的灰阶，需要外部Gamma电路给出多个固定的绑定电压，然后通过源驱动器内部的电阻串进行精细分压，得到6bit电压值，然后通过数模转换，为像素电路的液晶电容充电以产生相应的像素电压，这样得到的逻辑功耗就会较大。而且，RGB子像素的灰阶电压是共用的，实现8bit电压值的控制成本较高，一般源驱动器是分压得到6bit电压值，然后通过时序控制器的FRC(Frame Rate Control，帧比率控制)像素抖动算法得到8bit电压值的效果，但是FRC算法造成的不良较多，且调试周期较长。
目前液晶显示驱动方法为逐行扫描或隔行扫描，由源极驱动电路逐行或隔行对像素电极写入灰阶电压，此驱动方法会存在RC延迟(RC delay)，这种延迟对于高分辨率和超高分辨率的液晶显示尤为明显，同时也成为设计超高分辨率液晶显示面板的瓶颈之一。随着分辨率的升高，还会带来像素电极充电不足的问题。
因此，现有技术中的技术方案还存在有待改进之处。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开提供一种像素电路、显示装置以及驱动方法。
本公开的其他特性和优点将通过下面的详细描述变得清晰，或者部分地通过本公开的实践而习得。
根据本公开的一个方面，提供一种像素电路，包括：液晶电容，具有第一端和第 二端；选择单元，具有第一端、第二端和输出端，所述选择单元的第一端用于接收列控制信号，所述选择单元的第二端用于接收行控制信号，所述选择单元用于根据所述行控制信号和所述列控制信号确定是否向所述液晶电容充电；灰阶写入单元，具有第一端、第二端和输出端，所述灰阶写入单元的第一端与所述选择单元的输出端连接，所述灰阶写入单元的第二端与灰阶电压信号连接，所述灰阶写入单元的输出端与所述液晶电容的第二端连接，所述灰阶写入单元用于当所述选择单元确定向所述液晶电容充电时，向所述液晶电容施加所述灰阶电压信号，且所述灰阶电压信号的施加时长控制所述液晶电容显示的灰阶等级；复位单元，具有第一端、第二端、第三端和第四端，所述复位单元的第一端与复位信号连接，所述复位单元的第二端与所述选择单元的输出端连接，所述复位单元的第三端与所述灰阶写入单元的输出端连接，所述复位单元的第四端与公共电压信号连接，所述复位单元用于在接收到所述复位信号时，断开所述灰阶写入单元和所述液晶电容的连接以停止向所述液晶电容充电，并使所述液晶电容的电压复位到初始状态。
在本公开的一种示例性实施例中，所述选择单元包括：
第一晶体管和第二晶体管，均具有第一端、第二端和控制端，所述第一晶体管的控制端连接所述列控制信号，所述第一晶体管的第一端连接所述行控制信号，所述第一晶体管的第二端连接所述第二晶体管的第一端，所述第二晶体管的控制端连接所述行控制信号。
在本公开的一种示例性实施例中，所述灰阶写入单元包括第三晶体管，具有第一端、第二端和控制端，所述第三晶体管的控制端连接所述第二晶体管的第二端，所述第三晶体管的第一端连接所述灰阶电压信号，所述第三晶体管的第二端连接所述液晶电容的第二端。
在本公开的一种示例性实施例中，所述复位单元包括：
第四晶体管、第五晶体管和存储电容，所述第四晶体管和所述第五晶体管均具有第一端、第二端和控制端，所述存储电容具有第一端和第二端，所述第四晶体管和所述第五晶体管的控制端均连接所述复位信号，所述第四晶体管、所述第五晶体管和所述存储电容的第一端均连接所述第二晶体管的第二端，所述第四晶体管的第二端连接所述公共电压信号，所述第五晶体管和所述存储电容的第二端连接所述液晶电容的第一端，所述液晶电容的第二端连接所述公共电压信号。
根据本公开的另一个方面，还提供一种显示装置，包括：显示面板，具有多个以阵列形式排列的以上所述的像素电路；时序控制器，用于根据待显示的图像信息确定所述显示面板中各所述像素电路需显示的灰阶等级，并通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级。
在本公开的一种示例性实施例中，所述时序控制器包括：
灰阶控制单元，用于按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号；
充电控制单元，用于同时停止向所述显示面板中的全部所述像素电路中的液晶电容施加所述灰阶电压信号，以控制各所述像素电路中液晶电容的充电时长。
在本公开的一种示例性实施例中，所述灰阶控制单元具体用于：
确定第一级灰阶对应的全部所述像素电路在所述显示面板中的位置信息；
根据所述位置信息，生成相应的行控制信号和列控制信号；
通过所述行控制信号和所述列控制信号开始逐行对所述第一级灰阶对应的全部所述像素电路中的液晶电容施加所述灰阶电压信号；
在所述第一级灰阶对应的全部所述液晶电容被施加所述灰阶电压信号后，开始向第二级灰阶对应的全部所述像素电路中的液晶电容开始施加所述灰阶电压信号，直至最末一级的前一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号。
根据本公开的再一个方面，还提供一种像素电路的驱动方法，包括：
根据所述行控制信号和所述列控制信号产生确定是否向所述液晶电容充电；当确定向所述液晶电容充电时，向所述液晶电容施加所述灰阶电压信号；其中，所述液晶电容的灰阶等级是由所述灰阶电压信号的施加时长确定的。
在本公开的一种示例性实施例中，在接收到复位信号时，停止向所述液晶电容充电，并使所述液晶电容的电压复位到初始状态。
再根据本公开的一方面，还提供一种显示装置的驱动方法，包括：
确定所述显示面板中各所述像素电路需显示的灰阶等级；
通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级。
在本公开的一种示例性实施例中，所述通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级包括：
按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号；
同时停止向所述显示面板中的全部所述像素电路中的液晶电容施加所述灰阶电压信号，以控制各所述像素电路中液晶电容的充电时长。
在本公开的一种示例性实施例中，所述按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号包括：
确定第一级灰阶对应的全部所述像素电路在所述显示面板中的位置信息；
根据所述位置信息，生成相应的行控制信号和列控制信号；
通过所述行控制信号和所述列控制信号开始逐行对所述第一级灰阶对应的全部 所述像素电路中的液晶电容施加所述灰阶电压信号；
在所述第一级灰阶对应的全部所述液晶电容被施加所述灰阶电压信号后，开始向第二级灰阶对应的全部所述像素电路中的液晶电容开始施加所述灰阶电压信号，直至最末一级的前一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号。
在本公开的一种示例性实施例中，所述显示面板显示一帧画面的时间为1/(刷新率*灰阶等级的数目)，其中所述灰阶等级的数目为所述画面的全部灰阶等级的数目，所述刷新率为所述显示面板在一秒钟被刷新的次数。
在本公开的一种示例性实施例中，所述确定所述显示面板中各所述像素电路需显示的灰阶等级包括：
根据所述显示装置待显示的图像信息，确定所述显示面板中各所述像素电路需显示的灰阶等级。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出本公开实施例中提供的一种像素电路的结构示意图。
图2示出本公开实施例中与图1对应的像素电路的电路图。
图3示出本公开实施例中针对像素电路的驱动方法的步骤流程图。
图4示出本公开另一实施例中提供的一种显示装置的结构示意图。
图5示出本公开另一实施例中显示面板的阵列结构示意图。
图6示出本公开另一实施例中处理器的示意图。
图7示出本公开再一实施例中提供的一种显示装置的驱动方法的流程图。
图8示出本公开再一实施例中由时序控制器Tcon控制输出的行控制信号的时序波形图。
图9示出需要显示图像的灰阶电压示意图。
图10示出扫描线第1次逐行扫描时显示L255对应的灰阶电压的控制信号时序图。
图11示出扫描线第2次逐行扫描时显示L254对应的灰阶电压的控制信号时序图。
图12示出扫描线第255次逐行扫描时显示L1对应的灰阶电压的控制信号时序图。
图13示出扫描线第256次逐行扫描时显示L0对应的灰阶电压的控制信号时序图。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。附图仅为本公开的示意性图解，并非一定是按比例绘制。图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知结构、方法、装置、实现、材料或者操作以避免喧宾夺主而使得本公开的各方面变得模糊。
附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
本发明实施例中的所采用的晶体管可以为薄膜晶体管或场效应管或其他特性的相同器件，由于采用的晶体管的源极和漏极是对称的，所以其源极、漏极是没有区别的。在本发明实施例中，为区分晶体管的源极和漏极，分别称为第一端和第二端，栅极称为控制端。此外按照晶体管的特性区分可以将晶体管分为N型晶体管和P型晶体管。当采用N型晶体管时，第一端为N型晶体管的源极，第二端为N型晶体管的漏极，栅极输入高电平时源漏极导通；相反，当采用P型晶体管时，栅极输入低电平时源漏极导通。本文以下实施例中是以N型晶体管进行说明的，可以想到的是采用P型晶体管实现是本领域技术人员可以在不需要付出创造性劳动前提下轻易想到的，因此也是在本发明实施例保护范围之内的。
图1示出本公开实施例中提供的一种像素电路的结构示意图，如图1所示，该像素电路100包括：液晶电容Clc、选择单元101、灰阶写入单元102和复位单元103。
在本实施例中，液晶电容Clc具有两端，分别为第一端和第二端。选择单元101具有第一端、第二端和输出端，选择单元101的第一端用于接收列控制信号，选择单元101的第二端用于接收行控制信号，其中行控制信号为扫描线S提供的扫描信号，列控制信号为数据线D提供的数据信号。选择单元101用于根据行控制信号和列控制信号确定是否向液晶电容Clc充电。
在本实施例中，灰阶写入单元102具有第一端、第二端和输出端，灰阶写入单元102的第一端与选择单元101的输出端连接，灰阶写入单元102的第二端与灰阶电压 信号Von连接，灰阶写入单元102的输出端与液晶电容Clc的第一端连接。灰阶写入单元102用于当选择单元101确定向液晶电容Clc充电时，向液晶电容Clc施加灰阶电压信号Von，且灰阶电压信号的施加时长控制液晶电容Clc显示的灰阶等级。
在本实施例中，复位单元103具有第一端、第二端、第三端和第四端，复位单元103的第一端与复位信号Voff连接，复位单元103的第二端与选择单元101的输出端连接，复位单元103的第三端与灰阶写入单元102的输出端连接，复位单元103的第四端与公共电压信号Vcom连接。复位单元103用于在接收到复位信号Voff时，断开灰阶写入单元102和液晶电容Clc的连接以停止向液晶电容Clc充电，并使液晶电容Clc的电压复位到初始状态。该复位单元103用于完成一帧所有灰阶等级的显示之后通过复位信号启动下一帧显示。
图2示出与图1对应的像素电路的电路图，如图2所示，该像素电路中包括晶体管T1、T2、T3、T4、T5、液晶电容Clc和存储电容C1，除此之外还包括灰阶电压信号Von、复位信号Voff和公共电压信号Vcom三个电极信号以及扫描线S和数据线D两条控制线。
结合图1和图2所示，选择单元101包括：第一晶体管T1和第二晶体管T2，均具有第一端、第二端和控制端，第一晶体管T1的控制端连接列控制信号，第一晶体管T1的第一端连接行控制信号，第一晶体管T1的第二端连接第二晶体管T2的第一端，第二晶体管T2的控制端连接行控制信号。如果本实施例电路中的晶体管均是以N型晶体管为例，当行控制信号为高电平时第二晶体管T2导通，对应的列控制信号为高电平时第一晶体管T1也导通。
灰阶写入单元102包括第三晶体管T3，具有第一端、第二端和控制端，第三晶体管T3的控制端连接第二晶体管T2的第二端，第三晶体管T3的第一端连接灰阶电压信号Von，第三晶体管T3的第二端连接液晶电容Clc的第二端。灰阶电压信号Von为像素电极提供正/负性电压，数值可以为2Vcom或0。当第一晶体管T1和第二晶体管T2导通时，第三晶体管T3的栅极为高电平，因此第三晶体管T3也导通，液晶电容Clc被充电。
复位单元103包括：第四晶体管T4、第五晶体管T5和存储电容C1，第四晶体管T4、第五晶体管T5均具有第一端、第二端和控制端，存储电容C具有第一端和第二端，第四晶体管T4和第五晶体管T5的控制端均连接复位信号Voff，第四晶体管T4、第五晶体管T5和存储电容C1的第一端均连接第二晶体管T2的第二端，第四晶体管T4的第二端连接公共电压信号Vcom，第五晶体管T5和存储电容C1的第二端连接液晶电容Clc的第一端，液晶电容Clc的第二端连接公共电压信号Vcom。复位信号Voff为低电平，第四晶体管T4和第五晶体管T5关断，因此第一晶体管T1和第二晶体管T2导通时，存储电容C1也被充电，直到全部灰阶等级显示完成之后， 复位信号Voff置为高电平，第四晶体管T4和第五晶体管T5导通，存储电容C1和液晶电容Clc放电，再开始下一帧显示。
本实施例通过对电路进行改进，在每一帧开始时刻扫描线快速逐行扫描，数据线输出的数据信号将当前扫描行需要显示L255灰阶的像素结构的T1打开，C1被充同时将T3打开到最大，Clc被充入Von电压进行显示。Tcon等待t后，通过行控制信号和列控制信号将所有需要显示L254灰阶的像素结构T1打开，使该Clc充入Von电压进行显示。以此按灰阶递减方式逐个打开各灰阶像素结构的T1，使对应的Clc充入电压Von进行显示。当所有L1灰阶像素结构T1打开完成后，等待2t时间后Voff拉高将所有T4和T5打开，将C1和Clc中的电放出去再进行下一帧显示。
在本实施例提供的像素电路的基础上，配合控制信号时序，将原有逐行充电驱动方法改变为逐个灰阶充入相同电压，Clc像素电极电压保持时间决定了显示灰阶亮度，而非固定位置顺序充电方法，通过控制增加像素电极充电时间，提高充电率，省去源极驱动电路中电阻串的设计，可以很大程度降低功耗，并且可以分开对RGB进行伽马电压校正，不需要在共同的电压基础上通过ACC调校，从而节约IC成本，比较容易实现8bit及以上控制。
图3示出本公开实施例中针对上述像素电路的驱动方法的步骤流程图。
如图3所示，在步骤S11中，根据行控制信号和列控制信号确定是否向液晶电容Clc充电。
如图3所示，在步骤S12中，当确定向液晶电容Clc充电时，向液晶电容Clc施加灰阶电压信号。其中，本实施例中液晶电容的灰阶等级是由灰阶等级信号的施加时长确定的。
如图3所示，在步骤S13中，在接收到复位信号时，停止向液晶电容Clc充电，并使液晶电容Clc的电压复位到初始状态。也就是说当所有像素灰阶等级显示完成后，通过复位信号释放液晶电容Clc中充入的电压，开启下一帧的显示。
采用本实施例提供的驱动方法，无论显示面板的分辨率是多少，像素充电时间均为1/(刷新率*灰阶等级的数目)，刷新率通常为60～75HZ。通常8位显示的灰阶数为2 8＝256，如果显示面板的刷新率为60Hz，分辨率为1920*1080，显示面板的充电时间均为1/(60*256)＝65.10us。因此，本实施例提供的像素电路及其驱动方法对于高分辨率以及超高分辨率的显示面板尤为适用。
图4示出本公开另一实施例中提供的一种显示装置的结构示意图，该显示装置100中包括：显示面板110和时序控制器120，其中显示面板110具有多个以阵列形式排列的以上的像素电路，时序控制器120用于根据待显示的图像信息确定显示面板中各像素电路需显示的灰阶等级，并通过控制像素电路中液晶电容的充电时长，使液晶电容显示相应的灰阶等级。另外，时序控制器120还通过时序控制信号来控制提供 给显示面板110的行控制信号、列控制信号、灰阶电压信号和复位信号。
在显示面板110中，通常包含多条(n条)扫描线S和多条(m条)数据线D，同时也包含多个(m*n)图2所示的像素电路，图5示出本公开另一实施例中显示面板的阵列结构示意图，如图5所示，包含三条扫描线S1、S2、S3以及四条数据线D1、D2、D3、D4。该阵列结构中是以n＝3、m＝4为例进行说明的，本领域技术人员可以理解，根据本公开实施例的显示面板当然可以包括更多其他数目的扫描线和数据线，本发明并不限于此。
需要说明的是，图5中的复位信号Voff均是由时序控制器130控制并提供的。
图6示出本实施例中处理器的示意图，如图6所示，时序控制器120包括：灰阶控制单元121和充电控制单元122。灰阶控制单元121用于按照灰阶等级，依次向同一级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号。充电控制单元122用于同时停止向显示面板中的全部像素电路中的液晶电容施加灰阶电压信号，以控制各像素电路中液晶电容的充电时长。
另外，本实施例中的灰阶控制单元121中具体用于确定第一级灰阶对应的全部像素电路在显示面板中的位置信息；还用于根据位置信息，生成相应的行控制信号和列控制信号；还用于通过行控制信号和列控制信号开始逐行对第一级灰阶对应的全部像素电路中的液晶电容施加灰阶电压信号；还用于在第一级灰阶对应的全部液晶电容被施加灰阶电压信号后，开始向第二级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号，直至最末一级的前一级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号。
以图5所示阵列结构为例，可以利用坐标(S1，D1)表示扫描线S1与数据线D1交汇处的像素电路(由于针对整个显示面板而言每一个像素电路肉眼可见的就是一个个小亮点，也可称之为像素点)，确定位置模块1211确定需要显示的像素点的位置，再对液晶电容进行充电，实现该像素点的灰阶显示。
基于上述，图7示出本公开实施例提供的一种显示装置的驱动方法的流程图。
如图7所示，在步骤S71中，确定显示面板中各像素电路需显示的灰阶等级。具体的，在本实施例中，可以根据显示装置待显示的图像信息确定显示面板中各像素电路需显示的灰阶等级。
如图7所示，在步骤S72中，通过控制像素电路中液晶电容的充电时长，使液晶电容显示相应的灰阶等级。
在本实施例中，通过控制像素电路中液晶电容的充电时长的步骤中，首先按照灰阶等级，依次向同一级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号，并同时停止向显示面板中的全部像素电路中的液晶电容施加灰阶电压信号，以控制各像素电路中液晶电容的充电时长。
进一步的，在本实施例中，按照灰阶等级，依次向同一级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号的步骤中，首先，确定第一级灰阶对应的全部像素电路在显示面板中的位置信息。其次，根据位置信息，生成相应的行控制信号和列控制信号。然后，通过行控制信号和列控制信号开始逐行对第一级灰阶对应的全部像素电路中的液晶电容施加灰阶电压信号。最后，在第一级灰阶对应的全部液晶电容被施加灰阶电压信号后，开始向第二级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号，直至最末一级的前一级灰阶对应的全部像素电路中的液晶电容开始施加灰阶电压信号。
因此，在一帧的显示周期中，可以按照灰阶等级递增或递减的方式来逐个显示全部的灰阶等级，向显示同一灰阶等级的多个像素电路充入相同的灰阶电压信号，并通过控制向液晶电容Clc施加灰阶电压信号的时长来确定相应像素电路的灰阶等级。
以灰阶等级递减为例，控制向液晶电容施加灰阶电压信号的时长包括：由行控制信号和列控制信号共同确定向最大灰阶等级对应的液晶施加灰阶电压信号，将显示面板中所有的最大灰阶等级的像素电路全部显示完成，之后开始按照灰阶递减的方式显示下一个灰阶等级，直到向最小灰阶等级的前一级灰阶等级对应的液晶电容施加灰阶电压信号。当一帧显示全部灰阶等级之后，通过施加复位信号停止向液晶电容充电。
需要说明的是，在显示面板中显示同一灰阶等级时，无需等当前行液晶电容Clc被充电至灰阶电压信号即可进行下一行扫描。这样，无论显示面板的分辨率是多少，显示面板的显示一帧画面的时间均为1/(刷新率*灰阶等级的数目)，灰阶等级的数目为画面的全部灰阶等级的数目，刷新率为显示面板110在一秒钟被刷新的次数，这样可以有效增加像素电极的充电时间，提高充电率。
图8示出本公开另一实施例中由时序控制器Tcon控制输出的行控制信号的时序波形图，逐行打开扫描线S1、S2、……Sn，如图8所示，扫描线S1、S2、……Sn输出的行控制信号逐行变为有效的高电平。
通常显示面板分为常黑模式和常白模式，分别以ADS(为IPS(面内转换型，In-Plane Switching)显示模式的一种)显示模式和TN(扭曲向列型，Twisted Nematic)显示模式为例。针对图1和图2所示的像素电路以及像素电路阵列的显示原理进行介绍：
根据上述，以ADS显示模式为例，图9为要显示图像的灰阶电压示意图。选取图9所示的要显示图像的一部分(即从左上角选取3行4列共12个像素电路)进行说明，其中要显示的最大灰阶等级是L255，最小灰阶等级是L0。
1.ADS显示模式下，第一帧起始时，Voff置为低电平使T4和T5关闭，Von为2Vcom或0(以提供像素电极正/负极性电压)。
1)显示L255灰阶像素点：行控制信号从第一行开始至最末行逐行扫描，行控制 信号开始扫描的时刻记为ts；扫描当前行对应的像素若需要显示L255灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置高，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L255灰阶的像素点像素电极均被充入Von电压，记此时刻为t255。
图10示出扫描线第1次逐行扫描时显示L255对应的灰阶电压的控制信号时序图。如图10所示，扫描线第1次逐行扫描时，S1输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第一行有两个需要显示的L255灰阶的像素点，即(1,1)和(1,3)像素点，因此对应的数据线D1和D3输出的列控制信号为有效的高电平；S2输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第二行有一个需要显示的L255灰阶的像素点，即(2,2)像素点，因此对应的数据线D2输出的列控制信号为有效的高电平；S3输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第三行没有需要显示的L255灰阶的像素点，因此对应的数据线D1、D2和D3输出的列控制信号均为低电平；S4输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第四行有两个需要显示的L255灰阶的像素点，即(4,2)和(4,3)像素点，因此对应的数据线D2和D3输出的列控制信号为有效的高电平。
2)显示L254灰阶像素点：显示面板上所有需要显示L255灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，扫描当前行对应的像素若需要显示L254灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L254灰阶的像素点像素电极均被充入Von电压，记此时刻为t254。
图11示出扫描线第2次逐行扫描时显示L254对应的灰阶电压的控制信号时序图。如图11所示，扫描线第2次逐行扫描时，S1输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第一行有一个需要显示的L254灰阶的像素点，即(1,2)像素点，因此对应的数据线D2输出的列控制信号为有效的高电平；S2输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第二行有两个需要显示的L254灰阶的像素点，即(2,1)和(2,3)像素点，因此对应的数据线D1和D3输出的列控制信号为有效的高电平；S3输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第三行有一个需要显示的L254灰阶的像素点，即(3,1)像素点，因此对应的数据线D1输出的列控制信号为有效的高电平；S4输出的行控制信号为高电平，在图 9所示的要显示图像的灰阶中第四行没有需要显示的L254灰阶的像素点，因此对应的数据线D1、D2和D3输出的列控制信号均为低电平。
需要说明的是，本实施例中的时刻t255、t254以及下文的t253……仅仅用于区别不同灰阶等级的充电时刻，而等待时间tw用于对每一灰阶等级的显示时长进行调校。
3)显示L253灰阶像素点：显示面板上所有需要显示L254灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，扫描当前行对应的像素若需要显示L253灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L253灰阶的像素点像素电极均被充入Von电压，记此时刻为t253。
4)以此类推，所有需要显示L(N+1)(N＞1)灰阶的像素点像素电极被充入Von电压之后，时序控制器Tcon等待时间tw后行控制信号进行下一次扫描，使需要显示L(N)灰阶的像素点像素电极被充入Von电压。
5)显示L1灰阶像素点：显示面板上所有需要显示L1灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，扫描当前行对应的像素若需要显示L1灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L1灰阶的像素点像素电极均被充入Von电压，记此时刻为t1。
图12示出扫描线第255次逐行扫描时显示L1对应的灰阶电压的控制信号时序图。如图12所示，扫描线第255次逐行扫描时，S1输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第一行没有需要显示的L1灰阶的像素点，因此对应的数据线D1、D2和D3输出的列控制信号均为低电平；同理，S2和S4输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第二行和第四行也没有需要显示的L1灰阶的像素点，因此对应的数据线D1、D2和D3输出的列控制信号也均为低电平；只有S3输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第三行有两个需要显示的L1灰阶的像素点，即(3,2)和(3,3)像素点，因此对应的数据线D2和D3输出的列控制信号为有效的高电平。
6)显示L0灰阶像素点：显示面板上所有需要显示L1灰阶的像素点像素电极被 充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，此时数据线D保持低电平，使需要显示L0灰阶的像素点像素电极不被充电。或者可以显示面板上所有需要显示L1灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw+tt后为L0显示完成(tt为行控制信号从第一行扫描到最末行所需时间)。
图13示出扫描线第256次逐行扫描时显示L0对应的灰阶电压的控制信号时序图。如图13所示，扫描线第256次逐行扫描时，S1、S2和S3输出的行控制信号为高电平，在图9所示的要显示图像的灰阶中第一行至第三行都没有需要显示的L0灰阶的像素点，只有第四行有需要显示L0灰阶的像素点，但是由于是L0灰阶，因此对应的数据线D1、D2和D3输出的列控制信号一直为低电平。
7)所有灰阶显示完成后，Tcon等待时间tw后将Voff置为高电平，将所有T4和T5打开，所有像素电极电压被放电至Vcom，下一帧显示开始。
8)下一帧开始重复上一帧的动作过程。
以上ADS就是按照灰阶递减的方式对各个灰阶等级对应的像素电容施加灰阶电压信号，并因时长逐渐递减对不同的灰阶等级进行区分，以下TN模式由于是常白模式，则按照灰阶等级递增的方式对各个灰阶等级对应的像素电容施加灰阶电压信号，也是由时长递减来对不同的灰阶等级进行区分。
2.TN显示模式下，第一帧起始时，Voff置位低电平使T4和T5关闭，Von设置为2Vcom或0V。
1)显示L0灰阶像素点：行控制信号从第一行开始至最末行逐行扫描，行控制信号开始扫描的时刻记为ts；扫描当前行对应的像素若需要显示L0灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L0灰阶的像素点像素电极均被充入Von电压，记此时刻为t0；
2)显示L1灰阶像素点：显示面板上所有需要显示L0灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，扫描当前行对应的像素若需要显示L1灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L1灰阶的像素点像素电极均被充入Von电压，记此时刻为t1；
3)显示L2灰阶像素点：显示面板上所有需要显示L1灰阶的像素点像素电极被充入Von电压后时序Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，扫描当前行对应的像素若需要显示L2灰阶，则该列对应的数据线D信号置为高电平，此时T1和T2同时打开，C1被充电以及T3栅极被置为高电平，T3被打开，Clc被充电，由于C1的存在，T3栅极电压将被逐渐抬高至T3打开到最大，所有行控制信号无需等待Clc像素电极充电至Von就可以继续下一行扫描，提高扫描速率。当行控制信号扫描到最末行后，所有需要显示L2灰阶的像素点像素电极均被充入Von电压，记此时刻为t2；
4)以此类推，所有需要显示L(N-1)(N＜255)灰阶的像素点像素电极被充入Von电压后，Tcon等待时间tw后行控制信号进行下一次扫描，使需要显示L(N)灰阶的像素点像素电极被充入Von电压。
5)显示L255灰阶像素点：显示面板上所有需要显示L254灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw，行控制信号开始下一次扫描，从第一行开始至最末行逐行扫描，此时数据线D保持低电平，使需要显示L255灰阶的像素点像素电极不被充电。或者可以显示面板上所有需要显示L254灰阶的像素点像素电极被充入Von电压后Tcon等待时间tw+tt后为L255灰阶显示完成(tt为行控制信号从第一行扫描到最末行所需时间)。
6)所有灰阶显示完成后，Tcon等待时间tw后将Voff置为高电平，将所有T4和T5打开，所有像素电极电压被放电至Vcom，下一帧显示开始。
7)下一帧开始重复上一帧的动作过程。
在TN显示模式下按照灰阶递增的方式逐个打开各个灰阶像素电路中的T1，是对应的液晶电容Clc充入灰阶电压进行显示，而显示各个灰阶电压时的控制信号时序图可依照显示原理与上述ADS显示模式下类似，可参见图10-图13得到，此处不再赘述。
综上所述，本实施例提供的像素电路及驱动方法，采用逐个灰阶充相同像素电压，控制Clc电压保持时间得到相应灰阶，不管显示面板分辨率为多少，其充电时间均为1/(刷新率*灰阶等级的数目)s，有效提高充电时间，提高充电率。
另外，本实施例还可解决逐行开启造成的放电不均问题，且关机后Vcom电极与像素电极连接，可有效解决像素电极与Vcom电极放电速度不一造成的开机闪烁、漂移不良的问题。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围 和精神由所附的权利要求指出。

Claims (14)

  1. 一种像素电路，包括：
    液晶电容，具有第一端和第二端；
    选择单元，具有第一端、第二端和输出端，所述选择单元的第一端用于接收列控制信号，所述选择单元的第二端用于接收行控制信号，所述选择单元用于根据所述行控制信号和所述列控制信号确定是否向所述液晶电容充电；
    灰阶写入单元，具有第一端、第二端和输出端，所述灰阶写入单元的第一端与所述选择单元的输出端连接，所述灰阶写入单元的第二端与灰阶电压信号连接，所述灰阶写入单元的输出端与所述液晶电容的第一端连接，所述灰阶写入单元用于当所述选择单元确定向所述液晶电容充电时，向所述液晶电容施加所述灰阶电压信号，且所述灰阶电压信号的施加时长控制所述液晶电容显示的灰阶等级；
    复位单元，具有第一端、第二端、第三端和第四端，所述复位单元的第一端与复位信号连接，所述复位单元的第二端与所述选择单元的输出端连接，所述复位单元的第三端与所述灰阶写入单元的输出端连接，所述复位单元的第四端与公共电压信号连接，所述复位单元用于在接收到所述复位信号时，断开所述灰阶写入单元和所述液晶电容的连接以停止向所述液晶电容充电，并使所述液晶电容的电压复位到初始状态。
  2. 根据权利要求1所述的像素电路，所述选择单元包括：
    第一晶体管和第二晶体管，均具有第一端、第二端和控制端，所述第一晶体管的控制端连接所述列控制信号，所述第一晶体管的第一端连接所述行控制信号，所述第一晶体管的第二端连接所述第二晶体管的第一端，所述第二晶体管的控制端连接所述行控制信号。
  3. 根据权利要求2所述的像素电路，所述灰阶写入单元包括第三晶体管，具有第一端、第二端和控制端，所述第三晶体管的控制端连接所述第二晶体管的第二端，所述第三晶体管的第一端连接所述灰阶电压信号，所述第三晶体管的第二端连接所述液晶电容的第二端。
  4. 根据权利要求3所述的像素电路，所述复位单元包括：
    第四晶体管、第五晶体管和存储电容，所述第四晶体管和所述第五晶体管均具有第一端、第二端和控制端，所述存储电容具有第一端和第二端，所述第四晶体管和所述第五晶体管的控制端均连接所述复位信号，所述第四晶体管、所述第五晶体管和所述存储电容的第一端均连接所述第二晶体管的第二端，所述第四晶体管的第二端连接所述公共电压信号，所述第五晶体管和所述存储电容的第二端连接所述液晶电容的第一端，所述液晶电容的第二端连接所述公共电压信号。
  5. 一种显示装置，包括：
    显示面板，具有多个以阵列形式排列的权利要求1-4任一项所述的像素电路；
    时序控制器，用于根据待显示的图像信息确定所述显示面板中各所述像素电路需显示的灰阶等级，并通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级。
  6. 根据权利要求5所述的显示装置，所述时序控制器包括：
    灰阶控制单元，用于按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号；
    充电控制单元，用于同时停止向所述显示面板中的全部所述像素电路中的液晶电容施加所述灰阶电压信号，以控制各所述像素电路中液晶电容的充电时长。
  7. 根据权利要求6所述的显示装置，所述灰阶控制单元具体用于：
    确定第一级灰阶对应的全部所述像素电路在所述显示面板中的位置信息；
    根据所述位置信息，生成相应的行控制信号和列控制信号；
    通过所述行控制信号和所述列控制信号开始逐行对所述第一级灰阶对应的全部所述像素电路中的液晶电容施加所述灰阶电压信号；
    在所述第一级灰阶对应的全部所述液晶电容被施加所述灰阶电压信号后，开始向第二级灰阶对应的全部所述像素电路中的液晶电容开始施加所述灰阶电压信号，直至最末一级的前一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号。
  8. 一种权利要求1-4中任一项所述的像素电路的驱动方法，包括：
    根据所述行控制信号和所述列控制信号产生确定是否向所述液晶电容充电；
    当确定向所述液晶电容充电时，向所述液晶电容施加所述灰阶电压信号；
    其中，所述液晶电容的灰阶等级是由所述灰阶电压信号的施加时长确定的。
  9. 根据权利要求8所述的像素电路的驱动方法，还包括：在接收到复位信号时，停止向所述液晶电容充电，并使所述液晶电容的电压复位到初始状态。
  10. 一种权利要求5-7中任一项所述的显示装置的驱动方法，包括：
    确定所述显示面板中各所述像素电路需显示的灰阶等级；
    通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级。
  11. 根据权利要求10所述的显示装置的驱动方法，所述通过控制所述像素电路中液晶电容的充电时长，使所述液晶电容显示相应的灰阶等级包括：
    按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号；
    同时停止向所述显示面板中的全部所述像素电路中的液晶电容施加所述灰阶电压信号，以控制各所述像素电路中液晶电容的充电时长。
  12. 根据权利要求11所述的显示装置的驱动方法，所述按照所述灰阶等级，依次向同一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号包括：
    确定第一级灰阶对应的全部所述像素电路在所述显示面板中的位置信息；
    根据所述位置信息，生成相应的行控制信号和列控制信号；
    通过所述行控制信号和所述列控制信号开始逐行对所述第一级灰阶对应的全部所述像素电路中的液晶电容施加所述灰阶电压信号；
    在所述第一级灰阶对应的全部所述液晶电容被施加所述灰阶电压信号后，开始向第二级灰阶对应的全部所述像素电路中的液晶电容开始施加所述灰阶电压信号，直至最末一级的前一级灰阶对应的全部所述像素电路中的液晶电容开始施加灰阶电压信号。
  13. 根据权利要求12所述的显示装置的驱动方法，所述显示面板显示一帧画面的时间为1/(刷新率*灰阶等级的数目)，其中所述灰阶等级的数目为所述画面的全部灰阶等级的数目，所述刷新率为所述显示面板在一秒钟被刷新的次数。
  14. 根据权利要求10所述的显示装置的驱动方法，所述确定所述显示面板中各所述像素电路需显示的灰阶等级包括：
    根据所述显示装置待显示的图像信息，确定所述显示面板中各所述像素电路需显示的灰阶等级。
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