WO2018223963A1

WO2018223963A1 - Scan circuit, gate drive circuit, display panel and drive method therefor, and display device

Info

Publication number: WO2018223963A1
Application number: PCT/CN2018/089969
Authority: WO
Inventors: 王志冲
Original assignee: 京东方科技集团股份有限公司
Priority date: 2017-06-06
Filing date: 2018-06-05
Publication date: 2018-12-13
Also published as: CN106971692A; CN106971692B

Abstract

A scan circuit (310), a gate drive circuit (350), a display panel (300) and a drive method therefor, and a display device (1). The scan circuit (310) comprises a shift register circuit (311) and a first signal generation circuit (312). The shift register circuit (311) has a first signal output end (OUT1) and is configured to output a first scan signal; the first signal generation circuit (312) has a second signal output end (OUT2) and is configured to generate and output a second scan signal based on a first refresh control signal (REP1) and the first scan signal. The scan circuit (310) can provide a first scan signal for a light emission control end (EM) of the pixel circuit (321, 101, 201) and a second scan signal for selecting a control end (GAT).

Description

扫描电路、栅极驱动电路、显示面板及其驱动方法和显示装置Scanning circuit, gate driving circuit, display panel, driving method thereof and display device

本申请要求于2017年6月6日递交的中国专利申请第201710419810.4号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。The present application claims priority to Chinese Patent Application No. JP-A No. No. No. No. No. No. No. No. No. No.

技术领域Technical field

本公开的实施例涉及一种扫描电路、栅极驱动电路、显示面板及其驱动方法和显示装置。Embodiments of the present disclosure relate to a scan circuit, a gate drive circuit, a display panel, a method of driving the same, and a display device.

背景技术Background technique

有机发光二极管(Organic Light Emitting Diode，OLED)显示器件具有视角宽、对比度高、响应速度快等特点。并且，相比于无机发光显示器件，有机发光二极管显示器件具有更高的发光亮度、更低的驱动电压等优势。由于具有上述特点和优势，有机发光二极管(OLED)显示器件逐渐受到人们的广泛关注并且可以适用于手机、显示器、笔记本电脑、数码相机、仪器仪表等具有显示功能的装置。The Organic Light Emitting Diode (OLED) display device has the characteristics of wide viewing angle, high contrast, and fast response. Moreover, the organic light emitting diode display device has an advantage of higher luminance, lower driving voltage, and the like than the inorganic light emitting display device. Due to the above characteristics and advantages, organic light emitting diode (OLED) display devices have been receiving widespread attention and can be applied to devices having display functions such as mobile phones, displays, notebook computers, digital cameras, instrumentation, and the like.

发明内容Summary of the invention

本公开的至少一个实施例提供了一种扫描电路，其包括移位寄存电路和第一信号生成电路。所述移位寄存电路具有第一信号输出端且配置为输出第一扫描信号；所述第一信号生成电路具有第二信号输出端且配置为基于第一刷新控制信号与所述第一扫描信号生成并输出第二扫描信号。At least one embodiment of the present disclosure provides a scanning circuit including a shift register circuit and a first signal generating circuit. The shift register circuit has a first signal output and is configured to output a first scan signal; the first signal generation circuit has a second signal output and is configured to be based on the first refresh control signal and the first scan signal A second scan signal is generated and output.

例如，在所述扫描电路的至少一个示例中，所述扫描电路还包括第一节点；所述第一信号输出端连接至所述第一节点，且配置为输出所述第一扫描信号；所述第一信号生成电路还具有第一信号输入端和第二信号输入端，所述第一信号生成电路的第一信号输入端连接至所述第一节点，且配置为接收所述第一扫描信号，所述第一信号生成电路的第二信号输入端连接至第一刷新控制信号端，以接收所述第一刷新控制信号。For example, in at least one example of the scanning circuit, the scanning circuit further includes a first node; the first signal output is coupled to the first node and configured to output the first scan signal; The first signal generating circuit further has a first signal input end connected to the first node and a second signal input end configured to receive the first scan And a signal, the second signal input end of the first signal generating circuit is connected to the first refresh control signal end to receive the first refresh control signal.

例如，在所述扫描电路的至少一个示例中，所述第一信号生成电路包括第一与非电路；以及所述第一与非电路用于对所述第一扫描信号以及所述第一刷新控制信号进行与非运算以生成所述第二扫描信号。For example, in at least one example of the scanning circuit, the first signal generating circuit includes a first NAND circuit; and the first NAND circuit is configured to pair the first scan signal and the first refresh The control signal performs a NAND operation to generate the second scan signal.

例如，在所述扫描电路的至少一个示例中，所述第一与非电路包括用于所述第一与非电路的第一N型晶体管、用于所述第一与非电路的第二N型晶体管、用于所述第一与非电路的第一P型晶体管和用于所述第一与非电路的第二P型晶体管；所述用于所述第一与非电路的第一N型晶体管的第一端与第二电源端相连，所述用于所述第一与非电路的第一N型晶体管的控制端与所述第一信号生成电路的第二信号输入端连接；所述用于所述第一与非电路的第二N型晶体管的第一端与所述用于所述第一与非电路的第一N型晶体管的第二端相连，所述用于所述第一与非电路的第二N型晶体管的控制端配置为所述第一信号生成电路的第一信号输入端，且与所述第一节点相连，所述用于所述第一与非电路的第二N型晶体管的第二端连接至所述第二信号输出端；所述用于所述第一与非电路的第一P型晶体管的第一端与第一电源端相连，所述用于所述第一与非电路的第一P型晶体管的控制端与所述第一信号生成电路的第二信号输入端连接，所述用于所述第一与非电路的第一P型晶体管的第二端连接至所述第二信号输出端；以及所述用于所述第一与非电路的第二P型晶体管的第一端与所述第一电源端相连，所述用于所述第一与非电路的第二P型晶体管的控制端与所述第一节点相连，所述用于所述第一与非电路的第二P型晶体管的第二端与所述第二信号输出端相连。For example, in at least one example of the scanning circuit, the first NAND circuit includes a first N-type transistor for the first NAND circuit, and a second N for the first NAND circuit a transistor, a first P-type transistor for the first NAND circuit, and a second P-type transistor for the first NAND circuit; the first N for the first NAND circuit The first end of the transistor is connected to the second power terminal, and the control terminal of the first N-type transistor for the first NAND circuit is connected to the second signal input terminal of the first signal generating circuit; a first end of the second N-type transistor for the first NAND circuit is connected to the second end of the first N-type transistor for the first NAND circuit, a control end of the first N-type transistor of the first NAND circuit is configured as a first signal input end of the first signal generating circuit, and is connected to the first node, wherein the first NAND circuit is used a second end of the second N-type transistor is coupled to the second signal output; the a first end of the first P-type transistor of the circuit is coupled to the first power supply terminal, the control terminal of the first P-type transistor for the first NAND circuit and the second signal of the first signal generating circuit An input connection, a second end of the first P-type transistor for the first NAND circuit being coupled to the second signal output; and the second for the first NAND circuit a first end of the P-type transistor is connected to the first power terminal, and a control end of the second P-type transistor for the first NAND circuit is connected to the first node, A second end of the second P-type transistor of the first NAND circuit is coupled to the second signal output.

例如，在所述扫描电路的至少一个示例中，所述移位寄存电路还具有开启信号输入端、第一时钟信号输入端和第二时钟信号输入端，且包括输入电路和反相器和第二节点。所述输入电路包括第一端、第二端、第三端和输出端；所述输入电路的第一端和所述输入电路的第二端分别配置为所述第一时钟信号输入端和所述第二时钟信号输入端，且分别连接至第一时钟信号提供端和第二时钟信号提供端，以分别接收第一时钟信号和所述第二时钟信号；所述输入电路的第三端配置为所述移位寄存电路的开启信号输入端以接收开启信号；所述输入电路用于根据所述开启信号、所述第一时钟信号和所述第二时钟信号生成输入控制信号；所述输入电路的输出端连接至所述第二节点，且配置为输出所述输入控制信号。所述反相器包括输入端和输出端，所述反相器的输入端连接至所述第二节点，以接收所述输入控制信号，所述反相器用于对所述输入控制信号的电平进行反相以生成所述第一扫描信号；所述反相器的输出端连接至所述第一节点，且配置为所述第一信号输出端，以用于输出所述第一扫描信号。For example, in at least one example of the scanning circuit, the shift register circuit further has an on signal input terminal, a first clock signal input terminal, and a second clock signal input terminal, and includes an input circuit and an inverter and a Two nodes. The input circuit includes a first end, a second end, a third end, and an output end; the first end of the input circuit and the second end of the input circuit are respectively configured as the first clock signal input end and the a second clock signal input end, and is respectively connected to the first clock signal providing end and the second clock signal providing end to respectively receive the first clock signal and the second clock signal; the third end configuration of the input circuit An on signal input end of the shift register circuit to receive an on signal; the input circuit is configured to generate an input control signal according to the on signal, the first clock signal, and the second clock signal; An output of the circuit is coupled to the second node and configured to output the input control signal. The inverter includes an input end connected to the second node to receive the input control signal, and an output end, the inverter is configured to receive the input control signal Performing an inversion to generate the first scan signal; an output of the inverter is coupled to the first node, and configured as the first signal output for outputting the first scan signal .

例如，在所述扫描电路的至少一个示例中，所述输入电路包括用于所述移位寄存电路的第一N型晶体管、用于所述移位寄存电路的第二N型晶体管、用于所述移位寄存电路的第一P型晶体管、用于所述移位寄存电路的第二P型晶体管、用于所述移位寄存电路的第三N型晶体管、用于所述移位寄存电路的第四N型晶体管、用于所述移位寄存电路的第三P型晶体管和用于所述移位寄存电路的第四P型晶体管；所述用于所述移位寄存电路的第一N型晶体管的第一端与第二电源端相连，所述用于所述移位寄存电路的第一N型晶体管的控制端与所述第二时钟信号提供端相连；所述用于所述移位寄存电路的第二N型晶体管的第一端与所述用于所述移位寄存电路的第一N型晶体管的第二端相连，所述用于所述移位寄存电路的第二N型晶体管的控制端与所述移位寄存电路的开启信号输入端相连，所述用于所述移位寄存电路的第二N型晶体管的第二端与所述第二节点相连；所述用于所述移位寄存电路的第一P型晶体管的第一端与第一电源端相连，所述用于所述移位寄存电路的第一P型晶体管的控制端与所述第一时钟信号提供端相连；所述用于所述移位寄存电路的第二P型晶体管的第一端与所述用于所述移位寄存电路的第一P型晶体管的第二端相连，所述用于所述移位寄存电路的第二P型晶体管的控制端与所述移位寄存电路的开启信号输入端相连，所述用于所述移位寄存电路的第二P型晶体管的第二端与所述第二节点相连；所述用于所述移位寄存电路的第三N型晶体管的第一端与所述第二电源端相连，所述用于所述移位寄存电路的第三N型晶体管的控制端与所述第一时钟信号提供端相连；所述用于所述移位寄存电路的第四N型晶体管的第一端与所述用于所述移位寄存电路的第三N型晶体管的第二端相连，所述用于所述移位寄存电路的第四N型晶体管的控制端与所述第一节点相连，所述用于所述移位寄存电路的第四N型晶体管的第二端与所述第二节点相连；所述用于所述移位寄存电路的第三P型晶体管的第二端与所述第二节点相连，所述用于所述移位寄存电路的第三P型晶体管的控制端与所述第一节点相连；以及所述用于所述移位寄存电路的第四P型晶体管的第一端与所述第一电源端相连，所述用于所述移位寄存电路的第四P型晶体管的控制端与所述第二时钟信号提供端相连，所述用于所述移位寄存电路的第四P型晶体管的第二端与所述用于所述移位寄存电路的第三P型晶体管的第一端相连。所述反相器包括用于所述移位寄存电路的第五N型晶体管和用于所述移位寄存电路的第五P型晶体管；所述用于所述移位寄存电路的第五N型晶体管的第一端与所述第二电源端相连，所述用于所述移位寄存电路的第五N型晶体管的控制端与所述第二节点相连，所述用于所述移位寄存电路的第五N型晶体管的第二端与所述第一节点相连；所述用于所述移位寄存电路的第五P型晶体管的第一端与所述第一电源端相连，所述用于所述移位寄存电路的第五P型晶体管的控制端与所述第二节点相连，所述用于所述移位寄存电路的第五P型晶体管的第二端与所述第一节点相连。For example, in at least one example of the scan circuit, the input circuit includes a first N-type transistor for the shift register circuit, a second N-type transistor for the shift register circuit, a first P-type transistor of the shift register circuit, a second P-type transistor for the shift register circuit, a third N-type transistor for the shift register circuit, for the shift register a fourth N-type transistor of the circuit, a third P-type transistor for the shift register circuit, and a fourth P-type transistor for the shift register circuit; the first for the shift register circuit a first end of an N-type transistor is coupled to a second power supply terminal, and a control terminal of the first N-type transistor for the shift register circuit is coupled to the second clock signal supply terminal; a first end of the second N-type transistor of the shift register circuit is coupled to the second end of the first N-type transistor for the shift register circuit, the first for the shift register circuit The control terminal of the two N-type transistor and the turn-on signal of the shift register circuit Connected to the input terminal, the second end of the second N-type transistor for the shift register circuit is connected to the second node; the first P-type transistor for the shift register circuit One end is connected to the first power terminal, and the control terminal of the first P-type transistor for the shift register circuit is connected to the first clock signal supply terminal; the a first end of the second P-type transistor is coupled to the second end of the first P-type transistor for the shift register circuit, and the control of the second P-type transistor for the shift register circuit An end is connected to an open signal input end of the shift register circuit, and a second end of the second P-type transistor for the shift register circuit is connected to the second node; a first end of a third N-type transistor of the bit register circuit is coupled to the second power supply terminal, the control terminal of the third N-type transistor for the shift register circuit and the first clock signal supply terminal Connected; the first end of the fourth N-type transistor for the shift register circuit and The second end of the third N-type transistor for the shift register circuit is connected, and the control end of the fourth N-type transistor for the shift register circuit is connected to the first node. a second end of the fourth N-type transistor for the shift register circuit is connected to the second node; the second end of the third P-type transistor for the shift register circuit is a second node connected, the control terminal of the third P-type transistor for the shift register circuit being connected to the first node; and the fourth P-type transistor for the shift register circuit a first end is connected to the first power supply end, and a control end of the fourth P-type transistor for the shift register circuit is connected to the second clock signal supply end, the A second end of the fourth P-type transistor of the register circuit is coupled to the first end of the third P-type transistor for the shift register circuit. The inverter includes a fifth N-type transistor for the shift register circuit and a fifth P-type transistor for the shift register circuit; the fifth N for the shift register circuit a first end of the transistor is connected to the second power terminal, and a control end of the fifth N-type transistor for the shift register circuit is connected to the second node, the a second end of the fifth N-type transistor of the register circuit is connected to the first node; a first end of the fifth P-type transistor for the shift register circuit is connected to the first power terminal, a control terminal of a fifth P-type transistor for the shift register circuit is connected to the second node, and a second end of the fifth P-type transistor for the shift register circuit and the first A node is connected.

例如，在所述扫描电路的至少一个示例中，所述扫描电路还包括复位电路，所述复位电路连接至所述第二节点，且用于对所述第一节点进行初始化复位；以及所述复位电路包括用于所述复位电路的P型晶体管，所述用于所述复位电路的P型晶体管的第一端与第一电源端相连，所述用于所述复位电路的P型晶体管的控制端用于接收初始化复位信号，所述用于所述复位电路的P型晶体管的第二端与所述第二节点相连。For example, in at least one example of the scanning circuit, the scanning circuit further includes a reset circuit connected to the second node and configured to perform an initial reset on the first node; a reset circuit including a P-type transistor for the reset circuit, the first end of the P-type transistor for the reset circuit being connected to a first power supply terminal, the P-type transistor for the reset circuit The control terminal is configured to receive an initialization reset signal, and the second end of the P-type transistor for the reset circuit is connected to the second node.

例如，在所述扫描电路的至少一个示例中，所述扫描电路还包括还包括第二信号生成电路，所述第二信号生成电路具有第一信号输入端、第二信号输入端和第三信号输出端；所述第二信号生成电路的第一信号输入端连接至所述第一节点，且配置为接收所述第一扫描信号；所述第二信号生成电路的第二信号输入端连接至第二刷新控制信号端，以接收所述第二刷新控制信号端提供的第二刷新控制信号；所述第二信号生成电路配置为基于所述第一扫描信号和所述第二刷新控制信号生成第三扫描信号。所述第二信号生成电路包括第二与非电路，所述第二与非电路包括第一输入端、第二输入端和信号输出端，其分别配置为所述第二信号生成电路的第一信号输入端、第二信号输入端和第三信号输出端，所述第二与非电路用于对所述第一扫描信号以及所述第二刷新控制信号进行与非运算以生成所述第三扫描信号。For example, in at least one example of the scanning circuit, the scanning circuit further includes a second signal generating circuit having a first signal input terminal, a second signal input terminal, and a third signal An output terminal; a first signal input end of the second signal generating circuit is coupled to the first node, and configured to receive the first scan signal; a second signal input end of the second signal generating circuit is coupled to a second refresh control signal end to receive a second refresh control signal provided by the second refresh control signal end; the second signal generating circuit configured to generate based on the first scan signal and the second refresh control signal The third scan signal. The second signal generating circuit includes a second NAND circuit, and the second NAND circuit includes a first input end, a second input end, and a signal output end, which are respectively configured as the first of the second signal generating circuit a signal input end, a second signal input end, and a third signal output end, wherein the second NAND circuit is configured to perform NAND operation on the first scan signal and the second refresh control signal to generate the third Scan the signal.

例如，在所述扫描电路的至少一个示例中，所述第二与非电路包括用于所述第二与非电路的第一N型晶体管、用于所述第二与非电路的第二N型晶体管、用于所述第二与非电路的第一P型晶体管和用于所述第二与非电路的第二P型晶体管；所述用于所述第二与非电路的第一N型晶体管的第一端与所述第二电源端相连，所述用于所述第二与非电路的第一N型晶体管的控制端与所述第二信号生成电路的第二信号输入端相连；所述用于所述第二与非电路的第二N型晶体管的第一端与所述用于所述第二与非电路的第一N型晶体管的第二端相连，所述用于所述第二与非电路的第二N型晶体管的控制端与所述第一节点相连，所述用于所述第二与非电路的第二N型晶体管的第二端与所述第三信号输出端相连；所述用于所述第二与非电路的第一P型晶体管的第一端与所述第一电源端相连，所述用于所述第二与非电路的第一P型晶体管的控制端与所述第二信号生成电路的第二信号输入端相连，所述用于所述第二与非电路的第一P型晶体管的第二端与所述第三信号输出端相连；所述用于所述第二与非电路的第二P型晶体管的第一端与所述第一电源端相连，所述用于所述第二与非电路的第二P型晶体管的控制端与所述第一节点相连，所述用于所述第二与非电路的第二P型晶体管的第二端与所述第三信号输出端相连。For example, in at least one example of the scanning circuit, the second NAND circuit includes a first N-type transistor for the second NAND circuit and a second N for the second NAND circuit a transistor, a first P-type transistor for the second NAND circuit, and a second P-type transistor for the second NAND circuit; the first N for the second NAND circuit The first end of the transistor is connected to the second power terminal, and the control terminal of the first N-type transistor for the second NAND circuit is connected to the second signal input terminal of the second signal generating circuit The first end of the second N-type transistor for the second NAND circuit is connected to the second end of the first N-type transistor for the second NAND circuit, a control end of the second N-type transistor of the second NAND circuit is connected to the first node, and the second end of the second N-type transistor for the second NAND circuit is opposite to the third a signal output end is connected; the first end of the first P-type transistor for the second NAND circuit and the first power source Connected, the control end of the first P-type transistor for the second NAND circuit is connected to the second signal input end of the second signal generating circuit, the second NAND circuit a second end of the first P-type transistor is connected to the third signal output end; the first end of the second P-type transistor for the second NAND circuit is connected to the first power supply end, a control terminal of the second P-type transistor for the second NAND circuit is connected to the first node, and a second end of the second P-type transistor for the second NAND circuit is The third signal output is connected.

本公开的至少一个实施例还提供了一种栅极驱动电路，其包括N个级联的上述扫描电路；每级所述扫描电路的移位寄存电路具有信号输出端和开启信号输入端；第m级所述扫描电路的移位寄存电路的开启信号输入端连接至第m-1级所述扫描电路的第一信号输出端，N为大于等于1的整数，m为大于1且小于等于N的整数。At least one embodiment of the present disclosure further provides a gate driving circuit including N cascaded scanning circuits; each stage of the scanning circuit shift register circuit has a signal output end and an open signal input end; The turn-on signal input end of the shift register circuit of the m-th scanning circuit is connected to the first signal output end of the scanning circuit of the m-1th stage, N is an integer greater than or equal to 1, and m is greater than 1 and less than or equal to N The integer.

例如，在所述栅极驱动电路的至少一个示例中，第2k-1级所述扫描电路的第一信号生成电路连接的第一刷新控制信号端为第一信号源；第2k级所述扫描电路的第一信号生成电路连接的所述第一刷新控制信号端为第二信号源，k为大于等于1且小于等于N/2的整数。For example, in at least one example of the gate driving circuit, the first refresh control signal terminal connected to the first signal generating circuit of the scanning circuit of the 2k-1th stage is the first signal source; the scanning of the 2kth level The first refresh control signal end connected to the first signal generating circuit of the circuit is a second signal source, and k is an integer greater than or equal to 1 and less than or equal to N/2.

例如，在所述栅极驱动电路的至少一个示例中，每级所述扫描电路还包括第二信号生成电路；所述第2k-1级扫描电路的第二信号生成电路连接的第二刷新控制信号端为所述第二信号源，所述第2k级扫描电路的第二信号生成电路连接的所述第二刷新控制信号端为所述第一信号源。For example, in at least one example of the gate driving circuit, each stage of the scanning circuit further includes a second signal generating circuit; and a second refresh control of the second signal generating circuit connection of the 2k-1th stage scanning circuit The signal end is the second signal source, and the second refresh control signal end connected to the second signal generating circuit of the 2kth stage scanning circuit is the first signal source.

本公开的至少一个实施例又提供了一种显示面板，其包括像素电路阵列以及上述的栅极驱动电路。所述像素电路阵列包括阵列排布的多个像素电路，所述多个像素电路在列方向上排布成N行，每个所述像素电路包括发光控制端和选择控制端；第j级所述扫描电路的第一信号输出端连接至第j行的所述像素电路的发光控制端，所述第j级扫描电路的第二信号输出端连接至所述第j行像素电路的选择控制端，j为大于等于1且小于等于N的整数。At least one embodiment of the present disclosure further provides a display panel including a pixel circuit array and the above-described gate driving circuit. The pixel circuit array includes a plurality of pixel circuits arranged in an array, the plurality of pixel circuits are arranged in N rows in a column direction, and each of the pixel circuits includes a light emitting control end and a selection control end; a first signal output end of the scan circuit is connected to the light emission control end of the pixel circuit of the jth row, and a second signal output end of the jth stage scan circuit is connected to the selection control end of the pixel circuit of the jth row , j is an integer greater than or equal to 1 and less than or equal to N.

例如，在所述显示面板的至少一个示例中，每个所述像素电路还包括复位控制端；第m-1级所述扫描电路的第二信号输出端连接至第m行的所述像素电路的复位控制端。For example, in at least one example of the display panel, each of the pixel circuits further includes a reset control terminal; a second signal output of the m-1th stage of the scan circuit is coupled to the pixel circuit of the mth row Reset control terminal.

例如，在所述显示面板的至少一个示例中，每个所述像素电路还包括复位控制端；每级所述扫描电路还包括第二信号生成电路，所述第二信号生成电路包括第三信号输出端；以及所述第j级扫描电路的第三信号输出端连接至所述第j行像素电路的复位控制端。For example, in at least one example of the display panel, each of the pixel circuits further includes a reset control terminal; each stage of the scan circuit further includes a second signal generation circuit, and the second signal generation circuit includes a third signal And an output terminal; and a third signal output end of the j-th scanning circuit is connected to a reset control terminal of the pixel circuit of the jth row.

本公开的至少一个实施例又提供了一种显示装置，其包括上述的扫描电路、栅极驱动电路或显示面板。At least one embodiment of the present disclosure further provides a display device including the above-described scan circuit, gate drive circuit, or display panel.

本公开的至少一个实施例又提供了一种显示面板的驱动方法，其包括：使得所述第j级的扫描电路的移位寄存电路生成所述第一扫描信号，并将所述第一扫描信号提供给所述第j级的扫描电路的第一信号生成电路的第一信号输入端以及所述第j行的像素电路的发光控制端；以及使得所述第j级的扫描电路的第一信号生成电路基于所述第一扫描信号和第一刷新控制信号生成所述第二扫描信号，并将所述第二扫描信号提供给所述第j行的像素电路的选择控制端。At least one embodiment of the present disclosure further provides a driving method of a display panel, comprising: causing a shift register circuit of the scanning circuit of the jth stage to generate the first scan signal, and the first scan a signal supplied to a first signal input terminal of the first signal generating circuit of the scanning circuit of the jth stage and an emission control terminal of the pixel circuit of the jth row; and a first scan circuit of the jth stage The signal generating circuit generates the second scan signal based on the first scan signal and the first refresh control signal, and supplies the second scan signal to a selection control terminal of the pixel circuit of the jth row.

例如，在所述驱动方法的至少一个示例中，每个所述像素电路还包括复位控制端；所述驱动方法还包括：将所述第m-1级的扫描电路的第一信号生成电路生成的所述第二扫描信号提供给所述第m行的像素电路的复位控制端；或者将所述第j级的扫描电路的第二信号生成电路生成的第三扫描信号提供给所述第j行的像素电路的复位控制端。For example, in at least one example of the driving method, each of the pixel circuits further includes a reset control terminal; the driving method further includes: generating a first signal generating circuit of the scanning circuit of the m-1th stage The second scan signal is supplied to a reset control terminal of the pixel circuit of the mth row; or the third scan signal generated by the second signal generating circuit of the scanning circuit of the jth stage is supplied to the jth The reset control terminal of the pixel circuit of the row.

例如，在所述驱动方法的至少一个示例中，所述显示面板的显示周期包括刷新阶段和非刷新阶段；所述驱动方法包括：在所述非刷新阶段，使得所述第一信号生成电路的第二信号输入端接收低电平的刷新控制信号。For example, in at least one example of the driving method, the display period of the display panel includes a refresh phase and a non-refresh phase; the driving method includes: in the non-refresh phase, causing the first signal generating circuit The second signal input receives a low level refresh control signal.

例如，在所述驱动方法的至少一个示例中，所述移位寄存电路响应于时钟信号生成所述第一扫描信号；所述驱动方法包括：在所述刷新阶段，向所述移位寄存电路提供具有第一脉冲宽度的时钟信号，在所述非刷新阶段，向所述移位寄存电路提供具有第二脉冲宽度的时钟信号；所述第一脉冲宽度大于所述第二脉冲宽度。For example, in at least one example of the driving method, the shift register circuit generates the first scan signal in response to a clock signal; the driving method includes: in the refreshing phase, to the shift register circuit Providing a clock signal having a first pulse width, and in the non-refresh phase, providing a clock signal having a second pulse width to the shift register circuit; the first pulse width being greater than the second pulse width.

需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除作为控制端的栅极，直接描述了其中一极为第一端，另一极为第二端，所以本公开实施例中全部或部分晶体管的第一端和第二端根据需要是可以互换的。例如，本公开实施例的晶体管的第一端可以为源极，第二端可以为漏极；或者，晶体管的第一端为漏极，第二端为源极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管，本公开的实施例对晶体管的类型不作限定，本领域技术人员可以根据实际需要利用N型和/或P型晶体管实现本公开中的实施例。It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other switching devices having the same characteristics. The source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable. In the embodiment of the present disclosure, in order to distinguish the transistor from the gate as the control terminal, one of the first end and the other end are directly described. Therefore, the first end of all or part of the transistor in the embodiment of the present disclosure is The second end is interchangeable as needed. For example, the first end of the transistor of the embodiment of the present disclosure may be a source, and the second end may be a drain; or the first end of the transistor is a drain and the second end is a source. In addition, the transistor can be divided into N-type and P-type transistors according to the characteristics of the transistor. The embodiment of the present disclosure does not limit the type of the transistor, and those skilled in the art can implement the N-type and/or P-type transistor according to actual needs. Embodiments disclosed.

本公开至少一个实施例提出了一种显示面板的驱动电路，其包括奇数行GOA单元和偶数行GOA单元，其中，所述奇数行GOA单元对应驱动奇数行像素电路，所述偶数行GOA单元对应驱动偶数行像素电路，所述奇数行GOA单元和偶数行GOA单元中的每个GOA单元包括输入模块、反相器和第一与非电路。所述输入模块第一时钟信号提供端和第二时钟信号提供端相连，所述输入模块用于接收初始信号，并根据所述初始信号、所述第一时钟信号提供端提供的第一时钟信号和所述第二时钟信号提供端提供的第二时钟信号生成输入控制信号；反相器，所述反相器与所述输入模块相连，所述反相器用于对所述输入控制信号进行反相以输出第一扫描信号至本行GOA单元对应的像素电路；第一与非电路，所述第一与非电路的第一输入端与所述反相器相连，所述第一与非电路的第二输入端与刷新控制信号端相连，所述第一与非电路用于对所述第一扫描信号和所述刷新控制信号端提供的刷新控制信号进行与非运算以输出第二扫描信号至所述本行GOA单元对应的像素电路。At least one embodiment of the present disclosure provides a driving circuit for a display panel including an odd-numbered row of GOA cells and an even-numbered row of GOA cells, wherein the odd-numbered rows of GOA cells correspond to driving odd-numbered rows of pixel circuits, and the even-numbered rows of GOA cells correspond to An even row pixel circuit is driven, each of the odd row GOA unit and the even row GOA unit including an input module, an inverter, and a first NAND circuit. The input module first clock signal providing end is connected to the second clock signal providing end, and the input module is configured to receive an initial signal, and according to the initial signal, the first clock signal provided by the first clock signal providing end Generating an input control signal with a second clock signal provided by the second clock signal providing terminal; the inverter is connected to the input module, and the inverter is configured to reverse the input control signal And outputting the first scan signal to the pixel circuit corresponding to the GOA unit of the row; the first NAND circuit, the first input end of the first NAND circuit is connected to the inverter, the first NAND circuit The second input end is connected to the refresh control signal end, and the first NAND circuit is configured to perform a NAND operation on the refresh control signal provided by the first scan signal and the refresh control signal end to output a second scan signal a pixel circuit corresponding to the GOA unit of the row.

例如，在所述驱动电路的至少一个示例中，每个GOA单元都包括输入模块、反相器和第一与非电路，通过输入模块根据初始信号、第一时钟信号提供端提供的第一时钟信号和第二时钟信号提供端提供的第二时钟信号生成输入控制信号，反相器对输入控制信号进行反相以输出EM信号至本行GOA单元对应的像素电路，同时第一与非电路对第一扫描信号和刷新控制信号端提供的刷新控制信号进行与非运算以输出第二扫描信号Gate信号至本行GOA单元对应的像素电路。For example, in at least one example of the driving circuit, each GOA unit includes an input module, an inverter, and a first NAND circuit, and the first clock provided by the first clock signal providing end according to the initial signal by the input module The signal and the second clock signal provided by the second clock signal providing end generate an input control signal, and the inverter inverts the input control signal to output the EM signal to the pixel circuit corresponding to the GOA unit of the row, and the first NAND circuit pair The first scan signal and the refresh control signal provided by the refresh control signal terminal perform NAND operation to output the second scan signal Gate signal to the pixel circuit corresponding to the GOA unit of the row.

例如，在所述驱动电路的至少一个示例中，所述本行GOA单元输出的第一扫描信号作为下一行GOA单元的初始信号，所述本行GOA单元输出的第二扫描信号作为下一行GOA单元对应的像素电路的复位信号。For example, in at least one example of the driving circuit, the first scan signal output by the local GOA unit is used as an initial signal of the next row of GOA units, and the second scan signal output by the local GOA unit is used as the next row of GOA. The reset signal of the pixel circuit corresponding to the unit.

例如，在所述驱动电路的至少一个示例中，所述每个GOA单元还包括复位电路，所述复位电路用于对所述反相器输出端进行初始化复位。For example, in at least one example of the drive circuit, each of the GOA units further includes a reset circuit for initializing reset of the inverter output.

例如，在所述驱动电路的至少一个示例中，所述输入模块包括：第一NMOS管，所述第一NMOS管的第一端与第二电源端相连，所述第一NMOS管的控制端与所述第二时钟信号提供端相连；第二NMOS管，所述第二NMOS管的第一端与所述第一NMOS管的第二端相连，所述第二NMOS管的控制端与所述信号输入端相连；第一PMOS管，所述第一PMOS管的第一端与第一电源端相连，所述第一PMOS管的控制端与所述第一时钟信号提供端相连；第二PMOS管，所述第二PMOS管的第一端与所述第一PMOS管的第二端相连，所述第二PMOS管的控制端与所述信号输入端相连，所述第二PMOS管的第二端与所述第二NMOS管的第二端均与第二节点相连，所述第二节点作为所述输入模块的输出端；第三NMOS管，所述第三NMOS管的第一端与所述第二电源端相连，所述第三NMOS管的控制端与所述第一时钟信号提供端相连；第四NMOS管，所述第四NMOS管的第一端与所述第三NMOS管的第二端相连；第三PMOS管，所述第三PMOS管的第二端与所述第四NMOS管的第二端相连且与所述第二节点相连，所述第三PMOS管的控制端与所述第四NMOS管的控制端相连且与所述反相器的输出端相连；第四PMOS管，所述第四PMOS管的第一端与所述第一电源端相连，所述第四PMOS管的控制端与所述第二时钟信号提供端相连，所述第四PMOS管的第二端与所述第三PMOS管的第一端相连。For example, in at least one example of the driving circuit, the input module includes: a first NMOS transistor, a first end of the first NMOS transistor is connected to a second power terminal, and a control end of the first NMOS transistor Connected to the second clock signal supply end; the second NMOS transistor, the first end of the second NMOS transistor is connected to the second end of the first NMOS transistor, and the control end of the second NMOS transistor The signal input end is connected to the first PMOS transistor, the first end of the first PMOS transistor is connected to the first power supply end, and the control end of the first PMOS transistor is connected to the first clock signal supply end; a PMOS transistor, a first end of the second PMOS transistor is connected to a second end of the first PMOS transistor, a control end of the second PMOS transistor is connected to the signal input end, and a second PMOS transistor is connected The second end and the second end of the second NMOS transistor are both connected to the second node, the second node serves as an output end of the input module, and the third NMOS transistor, the first end of the third NMOS transistor Connected to the second power terminal, the control end of the third NMOS transistor is connected to the first clock signal providing end; a fourth NMOS transistor, the first end of the fourth NMOS transistor is connected to the second end of the third NMOS transistor; the third PMOS transistor, the second end of the third PMOS transistor and the fourth NMOS transistor The second end is connected to and connected to the second node, and the control end of the third PMOS transistor is connected to the control end of the fourth NMOS transistor and connected to the output end of the inverter; the fourth PMOS transistor, The first end of the fourth PMOS transistor is connected to the first power supply end, the control end of the fourth PMOS transistor is connected to the second clock signal supply end, and the second end of the fourth PMOS transistor is The first ends of the third PMOS transistors are connected.

例如，在所述驱动电路的至少一个示例中，所述反相器包括：第五NMOS管，所述第五NMOS管的第一端与所述第二电源端相连，所述第五NMOS 管的控制端与所述第二节点相连；第五PMOS管，所述第五PMOS管的第一端与所述第一电源端相连，所述第五PMOS管的控制端与所述第二节点相连，所述第五PMOS管的第二端与所述第五NMOS管的第二端均与第一节点相连，所述第一节点作为所述反相器的输出端。For example, in at least one example of the driving circuit, the inverter includes: a fifth NMOS transistor, a first end of the fifth NMOS transistor is connected to the second power terminal, and the fifth NMOS transistor a control terminal connected to the second node; a fifth PMOS transistor, a first end of the fifth PMOS transistor is connected to the first power terminal, and a control end of the fifth PMOS transistor and the second node Connected, the second end of the fifth PMOS transistor and the second end of the fifth NMOS transistor are both connected to the first node, and the first node serves as an output end of the inverter.

例如，在所述驱动电路的至少一个示例中，所述第一与非电路包括：第六NMOS管，所述第六NMOS管的第一端与所述第二电源端相连；第七NMOS管，所述第七NMOS管的第一端与所述第六NMOS管的第二端相连，所述第七NMOS管的控制端与所述第一节点相连；第七PMOS管，所述第七PMOS管的第一端与所述第一电源端相连，所述第七PMOS管的控制端与所述第六NMOS管的控制端相连后与所述刷新控制信号端相连，所述第七PMOS管的第二端与所述第七NMOS管的第二端均与第三节点相连，所述第三节点作为所述第一与非电路的输出端；第八PMOS管，所述第八PMOS管的第一端与所述第一电源端相连，所述第八PMOS管的控制端与所述第一节点相连，所述第八PMOS管的第二端与所述第三节点相连。For example, in at least one example of the driving circuit, the first NAND circuit includes: a sixth NMOS transistor, a first end of the sixth NMOS transistor is connected to the second power terminal; and a seventh NMOS transistor a first end of the seventh NMOS transistor is connected to a second end of the sixth NMOS transistor, a control end of the seventh NMOS transistor is connected to the first node, and a seventh PMOS transistor is in a seventh a first end of the PMOS transistor is connected to the first power supply end, and a control end of the seventh PMOS transistor is connected to the control end of the sixth NMOS transistor, and is connected to the refresh control signal end, the seventh PMOS The second end of the tube and the second end of the seventh NMOS tube are both connected to the third node, the third node is the output end of the first NAND circuit; the eighth PMOS tube, the eighth PMOS The first end of the tube is connected to the first power end, the control end of the eighth PMOS tube is connected to the first node, and the second end of the eighth PMOS tube is connected to the third node.

例如，在所述驱动电路的至少一个示例中，所述复位电路包括：第六PMOS管，所述第六PMOS管的第一端与第一电源端相连，所述第六PMOS管的控制端用于接收初始化复位信号，所述第六PMOS管的第二端与所述输入模块的输出端相连。For example, in at least one example of the driving circuit, the reset circuit includes: a sixth PMOS transistor, a first end of the sixth PMOS transistor is connected to the first power terminal, and a control terminal of the sixth PMOS transistor And receiving an initialization reset signal, and the second end of the sixth PMOS transistor is connected to an output end of the input module.

例如，在所述驱动电路的至少一个示例中，当所述本行GOA单元为奇数行GOA单元时，所述本行GOA单元还包括第二与非电路，所述第二与非电路的第一输入端与所述反相器相连，所述第二与非电路的第二输入端与第二刷新控制信号端相连，所述第二与非电路用于对所述第一扫描信号和所述第二刷新控制信号端提供的第二刷新控制信号进行与非运算以输出复位信号至所述本行GOA单元对应的像素电路。For example, in at least one example of the driving circuit, when the row GOA unit is an odd row GOA unit, the row GOA unit further includes a second NAND circuit, the second NAND circuit An input is connected to the inverter, a second input of the second NAND circuit is connected to a second refresh control signal end, and the second NAND circuit is configured to the first scan signal and the The second refresh control signal provided by the second refresh control signal terminal performs a NAND operation to output a reset signal to the pixel circuit corresponding to the LOA unit of the row.

例如，在所述驱动电路的至少一个示例中，当所述本行GOA单元为偶数行GOA单元时，所述本行GOA单元还包括第二与非电路，所述第二与非电路的第一输入端与所述反相器相连，所述第二与非电路的第二输入端与第二刷新控制信号端相连，所述第二与非电路用于对所述第一扫描信号和所述第二刷新控制信号端提供的第二刷新控制信号进行与非运算以输出复位信号至所述本行GOA单元对应的像素电路。For example, in at least one example of the driving circuit, when the row GOA unit is an even row GOA unit, the row GOA unit further includes a second NAND circuit, and the second NAND circuit An input is connected to the inverter, a second input of the second NAND circuit is connected to a second refresh control signal end, and the second NAND circuit is configured to the first scan signal and the The second refresh control signal provided by the second refresh control signal terminal performs a NAND operation to output a reset signal to the pixel circuit corresponding to the LOA unit of the row.

例如，在所述驱动电路的至少一个示例中，所述第二与非电路包括：第八NMOS管，所述第八NMOS管的第一端与所述第二电源端相连；第九NMOS管，所述第九NMOS管的第一端与所述第八NMOS管的第二端相连，所述第九NMOS管的控制端与所述第一节点相连；第九PMOS管，所述第九PMOS管的第一端与所述第一电源端相连，所述第九PMOS管的控制端与所述第八NMOS管的控制端相连后对应与所述第二刷新控制信号端或所述第二刷新控制信号端相连，所述第九PMOS管的第二端与所述第九NMOS管的第二端均与第四节点相连，所述第四节点作为所述第二与非电路的输出端；第十PMOS管，所述第十PMOS管的第一端与所述第一电源端相连，所述第十PMOS管的控制端与所述第一节点相连，所述第十PMOS管的第二端与所述第四节点相连。For example, in at least one example of the driving circuit, the second NAND circuit includes: an eighth NMOS transistor, a first end of the eighth NMOS transistor is connected to the second power terminal; and a ninth NMOS transistor a first end of the ninth NMOS transistor is connected to a second end of the eighth NMOS transistor, a control end of the ninth NMOS transistor is connected to the first node; a ninth PMOS transistor, the ninth a first end of the PMOS transistor is connected to the first power supply end, and a control end of the ninth PMOS transistor is connected to the control end of the eighth NMOS transistor, and corresponding to the second refresh control signal end or the first The second refresh control signal terminal is connected, the second end of the ninth PMOS transistor and the second end of the ninth NMOS transistor are both connected to the fourth node, and the fourth node is used as the output of the second NAND circuit. a tenth PMOS transistor, the first end of the tenth PMOS transistor is connected to the first power terminal, the control end of the tenth PMOS transistor is connected to the first node, and the tenth PMOS transistor is The second end is connected to the fourth node.

本公开至少一个实施例还提供了一种显示装置，其包括上述显示面板或上述驱动电路。At least one embodiment of the present disclosure also provides a display device including the above display panel or the above-described driving circuit.

附图说明DRAWINGS

为了更清楚地说明本公开的实施例的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，并非对本公开的限制。In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings to be used in the embodiments or the related art description will be briefly described below. Obviously, the drawings in the following description relate only to some of the present disclosure. The embodiments are not intended to limit the disclosure.

图1为一种像素电路的示意图；1 is a schematic diagram of a pixel circuit;

图2为一种用于驱动图1示出的像素电路的时序图；2 is a timing diagram for driving the pixel circuit shown in FIG. 1;

图3是用于示出本公开的一个实施例提供的扫描电路示意图；FIG. 3 is a schematic diagram of a scanning circuit for illustrating one embodiment of the present disclosure; FIG.

图4是用于示出本公开的一个实施例提供的一种扫描电路的示例性电路图；4 is an exemplary circuit diagram for illustrating a scan circuit provided by one embodiment of the present disclosure;

图5是用于示出本公开的一个实施例提供的另一种扫描电路的示例性电路图；FIG. 5 is an exemplary circuit diagram for illustrating another scanning circuit provided by one embodiment of the present disclosure; FIG.

图6为本公开的一个实施例提供的一种驱动时序图；FIG. 6 is a timing diagram of driving according to an embodiment of the present disclosure;

图7为本公开的一个实施例提供的另一种驱动时序图；FIG. 7 is another driving timing diagram provided by an embodiment of the present disclosure;

图8为本公开的至少一个实施例提供的显示面板在全面板刷新模式下的示意图；FIG. 8 is a schematic diagram of a display panel provided in a full-board refresh mode according to at least one embodiment of the present disclosure; FIG.

图9为本公开的至少一个实施例提供的显示面板在局部刷新模式下的示意图；FIG. 9 is a schematic illustration of a display panel provided in a partial refresh mode according to at least one embodiment of the present disclosure; FIG.

图10是用于示出本公开的另一个实施例提供的扫描电路的示意图；FIG. 10 is a schematic diagram for illustrating a scanning circuit provided by another embodiment of the present disclosure; FIG.

图11是用于示出本公开的另一个实施例提供的一种扫描电路的示例性电路图；11 is an exemplary circuit diagram for illustrating a scan circuit provided by another embodiment of the present disclosure;

图12是用于示出本公开的实施例提供的另一种扫描电路的示例性电路图；FIG. 12 is an exemplary circuit diagram for illustrating another scanning circuit provided by an embodiment of the present disclosure; FIG.

图13A为本公开的一个实施例提供的扫描电路的示例性框图；FIG. 13A is an exemplary block diagram of a scan circuit according to an embodiment of the present disclosure; FIG.

图13B为本公开的另一个实施例提供的扫描电路提供的示例性框图；FIG. 13B is an exemplary block diagram of a scan circuit provided by another embodiment of the present disclosure; FIG.

图13C为本公开的一个实施例提供的第二信号输出电路的一种驱动时序图；FIG. 13C is a driving timing diagram of a second signal output circuit according to an embodiment of the present disclosure; FIG.

图13D为本公开的一个实施例提供的第二信号输出电路的另一种驱动时序图；FIG. 13D is another driving timing diagram of a second signal output circuit according to an embodiment of the present disclosure; FIG.

图13E为本公开的另一个实施例提供的驱动时序图；FIG. 13E is a timing diagram of driving provided by another embodiment of the present disclosure; FIG.

图14A为本公开的至少一个实施例提供的一种栅极驱动电路的示例性框图；FIG. 14A is an exemplary block diagram of a gate driving circuit according to at least one embodiment of the present disclosure; FIG.

图14B为本公开的至少一个实施例提供的另一种栅极驱动电路的示例性框图；14B is an exemplary block diagram of another gate driving circuit provided by at least one embodiment of the present disclosure;

图15A为本公开的至少一个实施例提供的一种显示面板的示例性框图；FIG. 15A is an exemplary block diagram of a display panel according to at least one embodiment of the present disclosure; FIG.

图15B为本公开的至少一个实施例提供的另一种显示面板的示例性框图；15B is an exemplary block diagram of another display panel provided by at least one embodiment of the present disclosure;

图16为本公开的至少一个实施例提供的显示装置的示例性框图；16 is an exemplary block diagram of a display device provided by at least one embodiment of the present disclosure;

图17为本公开的至少一个实施例提供的显示装置的另一种示例性框图；FIG. 17 is another exemplary block diagram of a display device provided by at least one embodiment of the present disclosure;

图18为本公开的一个实施例提供的再一种驱动时序图。FIG. 18 is still another driving timing diagram provided by an embodiment of the present disclosure.

具体实施方式detailed description

为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。The technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. It is apparent that the described embodiments are part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the described embodiments of the present disclosure without departing from the scope of the invention are within the scope of the disclosure.

除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。Unless otherwise defined, technical terms or scientific terms used in the present disclosure are intended to be understood in the ordinary meaning of the ordinary skill of the art. The words "first," "second," and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the words "a", "an", "the" The word "comprising" or "comprises" or the like means that the element or item preceding the word is intended to be in the The words "connected" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate the relative positional relationship, and when the absolute position of the object to be described is changed, the relative positional relationship may also change accordingly.

在显示面板技术中，为了实现低成本和窄边框，可以采用GOA(Gate driver On Array)技术，即将栅极驱动电路通过半导体制备工艺制备在显示面板的阵列基板上，从而可以实现窄边框、薄厚度和降低装配成本等优势。In the display panel technology, in order to realize low cost and narrow bezel, GOA (Gate driver On Array) technology can be adopted, that is, the gate driving circuit is prepared on the array substrate of the display panel by the semiconductor fabrication process, thereby achieving narrow border and thin Thickness and reduced assembly costs.

本公开的发明人在研究中注意到，驱动当前的显示面板通常需要至少两个栅极驱动电路，由此导致了显示面板的边框较宽，并降低了用户的使用体验。此外，本公开的发明人还注意到，当前显示面板的驱动功耗较高。下面结合图1和图2做示例性说明。The inventors of the present disclosure have noted in research that driving a current display panel typically requires at least two gate drive circuits, thereby resulting in a wider frame of the display panel and a reduced user experience. Furthermore, the inventors of the present disclosure have also noticed that the driving power consumption of current display panels is high. An exemplary explanation will be given below with reference to FIGS. 1 and 2.

例如，显示面板包括阵列排布的显示像素，每个显示像素例如具有如图1示出的具有补偿功能(例如，阈值补偿功能)的像素电路。如图1所示，该像素电路具有发光控制端EM、选择控制端GAT和复位控制端RESE，且包括存储电容C1、发光元件EL、第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7。第五晶体管T5和第七晶体管T7连接至参考电源端Vref，第一晶体管T1和第四晶体管T4分别连接至数据端DAT和初始电压端Vini。For example, the display panel includes display pixels arranged in an array, each of which has, for example, a pixel circuit having a compensation function (eg, a threshold compensation function) as shown in FIG. As shown in FIG. 1 , the pixel circuit has a light-emitting control terminal EM, a selection control terminal GAT and a reset control terminal RESE, and includes a storage capacitor C1, a light-emitting element EL, a first transistor T1, a second transistor T2, and a third transistor T3. The fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The fifth transistor T5 and the seventh transistor T7 are connected to the reference power supply terminal Vref, and the first transistor T1 and the fourth transistor T4 are connected to the data terminal DAT and the initial voltage terminal Vini, respectively.

发光元件EL例如可以为OLED(Organic Light-Emitting Diode，有机发光二极管)，此种情况下，显示面板为OLED显示面板。晶体管例如可以采用LTPS(Low Temperature Poly-silicon，低温多晶硅)作为有源层的制作材料。The light emitting element EL may be, for example, an OLED (Organic Light-Emitting Diode). In this case, the display panel is an OLED display panel. The transistor can be made of, for example, LTPS (Low Temperature Poly-silicon) as a material for the active layer.

如图1所示，发光元件EL和第三晶体管T3分别连接至第一电源端VDD和第二电源端VSS，此处，第一电源端VDD和第二电源端VSS可以均输出直流电压，并且第一电源端VDD输出的电压可以大于第二电源端VSS输出的电压，第二电源端VSS例如可以为接地端，或为公共低压端，但本公开的实施例不限于此。As shown in FIG. 1, the light emitting element EL and the third transistor T3 are respectively connected to the first power terminal VDD and the second power terminal VSS, where the first power terminal VDD and the second power terminal VSS may each output a DC voltage, and The voltage outputted by the first power terminal VDD may be greater than the voltage output by the second power terminal VSS, and the second power terminal VSS may be, for example, a ground terminal or a common low voltage terminal, but embodiments of the present disclosure are not limited thereto.

例如，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7可以均为P型晶体管，也即，在第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第七晶体管T7的控制端在接收到低电平信号(脉冲信号)时处于导通状态。For example, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be P-type transistors, that is, in the first transistor. The control terminals of the T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are in an on state when receiving a low level signal (pulse signal) .

例如，在图1示出的像素电路的发光控制端EM、选择控制端GAT和复位控制端RESE分别接收到图2示出的发光控制信号、选择控制信号和复位控制信号时，第三晶体管T3可以驱动发光元件EL发光。在栅极驱动电路对显示面板的显示像素逐行施加上述发光控制信号、选择控制信号和复位控制信号时，可以实现图像的显示和刷新。For example, when the light emission control terminal EM, the selection control terminal GAT, and the reset control terminal RESE of the pixel circuit shown in FIG. 1 respectively receive the light emission control signal, the selection control signal, and the reset control signal shown in FIG. 2, the third transistor T3 The light emitting element EL can be driven to emit light. When the gate driving circuit applies the above-described light emission control signal, selection control signal, and reset control signal to the display pixels of the display panel row by row, display and refresh of the image can be realized.

本公开的发明人注意到，由于发光控制信号和选择控制信号的脉冲宽度不同，因此需要针对像素电路的发光控制端EM和选择控制端GAT分别设置一个栅极驱动电路(例如，需要设置EM GOA和Gate GOA两个GOA)，因此导致显示面板的边框(例如，显示面板的左右边框)相对较宽，这与消费者对具有显示面板的电子产品的窄边框的预期相背离。The inventors of the present disclosure have noticed that since the pulse widths of the light emission control signal and the selection control signal are different, it is necessary to separately provide a gate drive circuit for the light emission control terminal EM and the selection control terminal GAT of the pixel circuit (for example, EM GOA needs to be set) Two GOA) with Gate GOA, thus causing the border of the display panel (eg, the left and right borders of the display panel) to be relatively wide, which is contrary to the consumer's expectation of a narrow bezel of the electronic product having the display panel.

本公开的发明人还注意到，在驱动当前的显示面板时，显示面板的不同显示像素均具有相同的刷新频率，这使得显示面板的驱动功耗较高。The inventors of the present disclosure also note that when driving the current display panel, different display pixels of the display panel have the same refresh frequency, which makes the driving power consumption of the display panel higher.

本公开的实施例提供了一种扫描电路、栅极驱动电路、显示面板及其驱动方法和显示装置，该扫描电路可以为显示像素的像素电路的发光控制端EM和选择控制端GAT分别提供发光控制信号和选择控制信号，由此可以降低栅极驱动电路的尺寸以及显示面板边框的宽度。Embodiments of the present disclosure provide a scanning circuit, a gate driving circuit, a display panel, a driving method thereof, and a display device, which can respectively provide illumination for an illumination control terminal EM and a selection control terminal GAT of a pixel circuit of a display pixel The control signal and the selection control signal can thereby reduce the size of the gate drive circuit and the width of the display panel bezel.

本公开的至少一个实施例提供了一种扫描电路，其包括移位寄存电路和第一信号生成电路。移位寄存电路具有第一信号输出端且配置为输出第一扫描信号；第一信号生成电路具有第二信号输出端且配置为基于第一刷新控制信号与第一扫描信号生成并输出第二扫描信号。该扫描电路可以生成并输出具有不同脉冲宽度第一扫描信号和第二扫描信号，并因此可以为像素电路(例如，图1示出的像素电路)的发光控制端EM和选择控制端GAT分别提供发光控制信号和选择控制信号。At least one embodiment of the present disclosure provides a scanning circuit including a shift register circuit and a first signal generating circuit. The shift register circuit has a first signal output and is configured to output a first scan signal; the first signal generation circuit has a second signal output and is configured to generate and output a second scan based on the first refresh control signal and the first scan signal signal. The scanning circuit can generate and output a first scan signal and a second scan signal having different pulse widths, and thus can be respectively provided for the illumination control terminal EM and the selection control terminal GAT of the pixel circuit (for example, the pixel circuit shown in FIG. 1) Illumination control signal and selection control signal.

本公开的至少一个实施例还提供了一种栅极驱动电路，其包括N个级联的上述扫描电路，由此可以降低栅极驱动电路的尺寸。本公开的至少一个实施例又提供了一种显示面板，其包括像素电路阵列以及上述栅极驱动电路，由此可以降低显示面板边框的宽度。At least one embodiment of the present disclosure also provides a gate driving circuit including N cascaded scan circuits described above, whereby the size of the gate driving circuit can be reduced. At least one embodiment of the present disclosure further provides a display panel including a pixel circuit array and the above-described gate driving circuit, whereby the width of the display panel bezel can be reduced.

下面参照附图对本公开的实施例提供的扫描电路、栅极驱动电路和显示面板进行非限制性的说明，如下面所描述的，在不相互抵触的情况下这些具体示例中不同特征可以相互组合，从而得到新的示例，这些新的示例也都属于本公开保护的范围。The scanning circuit, the gate driving circuit and the display panel provided by the embodiments of the present disclosure are described below without limitation, with reference to the accompanying drawings. As described below, different features in these specific examples may be combined with each other without conflicting with each other. Thus, new examples are obtained, and these new examples are also within the scope of the protection of the present disclosure.

图13A是本公开的实施例提供的一种扫描电路的示意性框图。如图13A所示，扫描电路310包括移位寄存电路311、第一信号生成电路312和第一节点361。图13A示出的扫描电路可用于图14A示出的栅极驱动电路350以及图15A示出的显示面板300。FIG. 13A is a schematic block diagram of a scanning circuit provided by an embodiment of the present disclosure. As shown in FIG. 13A, the scanning circuit 310 includes a shift register circuit 311, a first signal generating circuit 312, and a first node 361. The scanning circuit shown in FIG. 13A can be used for the gate driving circuit 350 shown in FIG. 14A and the display panel 300 shown in FIG. 15A.

下面结合图13A和图6对移位寄存电路311所具有的端口和功能做示例性地说明。Ports and functions of the shift register circuit 311 will be exemplarily explained below with reference to Figs. 13A and 6.

如图13A所示，移位寄存电路311具有第一信号输出端OUT1且配置为输出第一扫描信号。移位寄存电路311还具有开启信号输入端INP、第一时钟信号输入端CLK1和第二时钟信号输入端CLK2；第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别连接至第一时钟信号提供端CLK和第二时钟信号提供端CLKB，以分别接收第一时钟信号和第二时钟信号；开启信号输入端INP配置为接收开启信号；第一信号输出端OUT1连接至第一节点361且配置为输出的第一扫描信号，且第一扫描信号相比于开启信号，在时间上向后移位一个时钟信号的脉冲宽度。As shown in FIG. 13A, the shift register circuit 311 has a first signal output terminal OUT1 and is configured to output a first scan signal. The shift register circuit 311 further has an open signal input terminal INP, a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2; the first clock signal input terminal CLK1 and the second clock signal input terminal CLK2 are respectively connected to the first clock The signal supply terminal CLK and the second clock signal supply terminal CLKB respectively receive the first clock signal and the second clock signal; the turn-on signal input terminal INP is configured to receive the turn-on signal; the first signal output terminal OUT1 is connected to the first node 361 and The first scan signal is configured to be output, and the first scan signal is shifted backward in time by a pulse width of one clock signal compared to the on signal.

例如，如图6所示，在移位寄存电路311的开启信号输入端INP接收的开启信号为STV的情况下，第一信号输出端OUT1输出的第一扫描信号为EM1；在移位寄存电路311的开启信号输入端INP接收的开启信号为EM1的情况下，第一信号输出端OUT1输出的第一扫描信号为EM2。For example, as shown in FIG. 6, in the case where the ON signal received by the ON signal input terminal INP of the shift register circuit 311 is STV, the first scan signal outputted by the first signal output terminal OUT1 is EM1; When the ON signal received by the ON signal input terminal IN 311 is EM1, the first scan signal outputted by the first signal output terminal OUT1 is EM2.

下面结合图13A、图13C和图13D对第一信号生成电路312所具有的端口和功能做示例性地说明。The ports and functions of the first signal generating circuit 312 will be exemplarily explained below with reference to Figs. 13A, 13C and 13D.

如图13A所示，第一信号生成电路312具有第一信号输入端IN1、第二信号输入端IN2和第二信号输出端OUT2；第一信号生成电路312的第一信号输入端IN1连接至第一节点361，且配置为接收第一扫描信号；第一信号生成电路312的第二信号输入端IN2连接至第一刷新控制信号端REP1，以接收第一刷新控制信号；第一信号生成电路312配置为基于第一刷新控制信号与第一扫描信号生成并输出第二扫描信号；第二信号输出端OUT2配置为输出第二扫描信号。As shown in FIG. 13A, the first signal generating circuit 312 has a first signal input terminal IN1, a second signal input terminal IN2, and a second signal output terminal OUT2; the first signal input terminal IN1 of the first signal generating circuit 312 is connected to the first signal input terminal IN1. a node 361 configured to receive the first scan signal; the second signal input terminal IN2 of the first signal generating circuit 312 is coupled to the first refresh control signal terminal REP1 to receive the first refresh control signal; the first signal generating circuit 312 The second scan signal is configured to generate and output a second scan signal based on the first refresh control signal and the first scan signal; the second signal output terminal OUT2 is configured to output the second scan signal.

第一信号生成电路312配置为，在第一信号生成电路312的第一信号输入端IN1和第一信号生成电路312的第二信号输入端IN2均接收到高电平信号的情况下，生成并输出低电平信号；第一信号生成电路312进一步地配置为，在第一信号生成电路312的第一信号输入端IN1和第一信号生成电路312的第二信号输入端IN2中的任意一个接收到低电平信号的情况下，生成并输出高电平信号。The first signal generating circuit 312 is configured to generate and generate a high level signal when both the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 receive a high level signal. The low level signal is output; the first signal generating circuit 312 is further configured to receive at any one of the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 In the case of a low level signal, a high level signal is generated and output.

例如，为清楚起见，第一信号生成电路312和移位寄存电路311的具体结构将在阐述包括该扫描电路310的栅极驱动电路350和显示面板300之后再进行阐述。For example, for the sake of clarity, the specific structure of the first signal generating circuit 312 and the shift register circuit 311 will be explained after explaining the gate driving circuit 350 including the scanning circuit 310 and the display panel 300.

下面结合图13C和图13D对本公开的实施例提供的扫描电路为像素电路的发光控制端EM和选择控制端GAT分别提供发光控制信号和选择控制信号的原理进行示例性的说明。The scanning circuit provided by the embodiment of the present disclosure is exemplarily described with reference to FIG. 13C and FIG. 13D for the principle that the illumination control terminal EM and the selection control terminal GAT of the pixel circuit respectively provide the illumination control signal and the selection control signal.

例如，如图13C和图13D所示，在第1阶段st1、第2阶段st2和第4阶段st4，第一信号生成电路312的第一信号输入端IN1(接收第一信号输出端OUT1输出的第一扫描信号)和第二信号输入端IN2(接收第一刷新控制端REP1输出的第一刷新控制信号)接收至少一个低电平信号，此种情况下，第二信号输出端OUT2输出高电平信号；在第3阶段st3，第一信号生成电路31的第一信号输入端IN1和第二信号输入端IN2均接收高电平信号，此种情况下，第二信号输出端OUT2输出低电平信号。For example, as shown in FIG. 13C and FIG. 13D, in the first stage st1, the second stage st2, and the fourth stage st4, the first signal input terminal IN1 of the first signal generating circuit 312 (receives the output of the first signal output terminal OUT1). The first scan signal) and the second signal input terminal IN2 (the first refresh control signal outputted by the first refresh control terminal REP1) receive at least one low level signal. In this case, the second signal output terminal OUT2 outputs a high voltage. a flat signal; in the third stage st3, the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 31 receive a high level signal. In this case, the second signal output terminal OUT2 outputs a low power. Flat signal.

由于图13C和图13D示出的由第二信号输出端OUT2输出的第二扫描信号可用作像素电路的选择控制信号，因此，通过使得第一信号生成电路312配置为基于第一刷新控制信号与第一扫描信号生成并输出第二扫描信号，由此扫描电路可以分别为像素电路的发光控制端EM和选择控制端GAT提供发光控制信号和选择控制信号，而无需针对像素电路的发光控制端EM和选择控制端GAT设置两个扫描电路，减少了电路数量，进而可以降低包括该扫描电路310的显示面板的边框尺寸。Since the second scan signal output by the second signal output terminal OUT2 shown in FIGS. 13C and 13D can be used as the selection control signal of the pixel circuit, by configuring the first signal generation circuit 312 to be based on the first refresh control signal Generating and outputting a second scan signal with the first scan signal, whereby the scan circuit can respectively provide an illumination control signal and a selection control signal for the illumination control terminal EM of the pixel circuit and the selection control terminal GAT, without the illumination control terminal for the pixel circuit The EM and the selection control terminal GAT set two scanning circuits, which reduces the number of circuits, and thus can reduce the frame size of the display panel including the scanning circuit 310.

需要说明的是，图13C的第1阶段st1、第2阶段st2、第3阶段st3和第4阶段st4可以分别对应于图6示出的第1阶段、第2阶段、第3阶段和第4阶段；并且，第一信号输出端OUT1输出的第一扫描信号、第一刷新控制端REP1输出的第一刷新控制信号以及第二信号输出端OUT2输出第二扫描信号可以分别对应于标识了EM1、ENBO和Gate1的曲线。It should be noted that the first stage st1, the second stage st2, the third stage st3, and the fourth stage st4 of FIG. 13C may correspond to the first stage, the second stage, the third stage, and the fourth stage shown in FIG. 6, respectively. And the first scan signal outputted by the first signal output terminal OUT1, the first refresh control signal output by the first refresh control terminal REP1, and the second scan output signal outputted by the second signal output terminal OUT2 may respectively correspond to the identifier EM1. The curve of ENBO and Gate1.

需要说明的是，第一刷新控制信号端REP1提供的第一刷新控制信号的具体结构(脉冲宽度、低电平处于哪一阶段)可以根据实际应用需求(例如，对第二信号输出端OUT2输出的第二扫描信号的需求，或像素电路对选择控制信号的需求)进行设定，本公开的实施例对此不做具体限定。It should be noted that the specific structure (the pulse width and the low level of the first refresh control signal) provided by the first refresh control signal terminal REP1 may be according to actual application requirements (for example, output to the second signal output terminal OUT2). The requirement of the second scan signal, or the requirement of the pixel circuit for selecting the control signal, is set, and the embodiment of the present disclosure does not specifically limit this.

例如，选择控制端GAT所需的选择控制信号(第二信号输出端OUT2输出的第二扫描信号)可以为图13C和13D所示第二扫描信号，也即，在第3阶段st3为低电平(例如，0V)，在其余三个阶段为高电平的第二扫描信号(例如，大于0V)。对应地，如图13C和图13D所示，第一刷新控制信号在第3阶段st3为高电平，也即，使得第一刷新控制信号在第二扫描信号需要为低电平的阶段为高电平。例如，如图13C和图13D所示，第一刷新控制信号在第2阶段st2可以为低电平，以使得第二扫描信号在第2阶段st2可以为高电平，并因此使得第二扫描信号和第一扫描信号具有不同的脉冲宽度。例如，如图13C所示，第一刷新控制信号可以在第1阶段st1和第4阶段st4均为低电平的第二扫描信号；又例如，如图13D所示，第一刷新控制信号还可以为在第1阶段st1为高电平，在第4阶段st4为低电平，此种情况下，第一刷新控制信号端REP1输出的第一刷新控制信号可以为方波信号。For example, the selection control signal required to select the control terminal GAT (the second scan signal outputted by the second signal output terminal OUT2) may be the second scan signal shown in FIGS. 13C and 13D, that is, in the third stage st3 is low. Flat (eg, 0V), a second scan signal that is high at the other three stages (eg, greater than 0V). Correspondingly, as shown in FIG. 13C and FIG. 13D, the first refresh control signal is at a high level in the third stage st3, that is, the first refresh control signal is made high in a stage where the second scan signal needs to be low. Level. For example, as shown in FIGS. 13C and 13D, the first refresh control signal may be at a low level in the second phase st2, so that the second scan signal may be at a high level in the second phase st2, and thus the second scan is made The signal and the first scan signal have different pulse widths. For example, as shown in FIG. 13C, the first refresh control signal may be a second scan signal having a low level at both the first stage st1 and the fourth stage st4; and, for example, as shown in FIG. 13D, the first refresh control signal is further It may be that the first stage st1 is at a high level and the fourth stage st4 is at a low level. In this case, the first refresh control signal output by the first refresh control signal terminal REP1 may be a square wave signal.

例如，可以通过第一刷新控制信号调节第二信号输出端OUT2输出的第二扫描信号的具体结构，以满足不同像素电路的驱动需求。例如，如图13C和13D所示，第二扫描信号的低电平脉冲的宽度等于第一刷新控制信号的高电平的脉冲宽度，因此，可以通过调节第一刷新控制信号高电平的脉冲宽度来调节第二扫描信号的低电平脉冲的宽度，而使得第二扫描信号的低电平脉冲的宽度不限于为图13C示出的第一扫描信号的高电平脉冲的宽度的一半。又例如，通过使得第一刷新控制信号在第2阶段st2为高电平，而在第3阶段st3为低电平，可以使得第二扫描信号的低电平脉冲处于第2阶段，由此可以满足不同像素电路的驱动需求。For example, the specific structure of the second scan signal output by the second signal output terminal OUT2 can be adjusted by the first refresh control signal to meet the driving requirements of different pixel circuits. For example, as shown in FIGS. 13C and 13D, the width of the low-level pulse of the second scan signal is equal to the pulse width of the high level of the first refresh control signal, and therefore, the pulse of the high level of the first refresh control signal can be adjusted. The width adjusts the width of the low-level pulse of the second scan signal such that the width of the low-level pulse of the second scan signal is not limited to half the width of the high-level pulse of the first scan signal shown in FIG. 13C. Further, for example, by setting the first refresh control signal to the high level in the second stage st2 and the low level in the third stage st3, the low-level pulse of the second scan signal can be in the second stage, whereby Meet the driving needs of different pixel circuits.

下面结合图14A对本公开的实施例提供的栅极驱动电路350做示例性说明。The gate driving circuit 350 provided by the embodiment of the present disclosure will be exemplarily described below with reference to FIG. 14A.

如图14A所示，栅极驱动电路350包括N个级联(例如，在列方向上级联)的扫描电路310，且每级扫描电路310的移位寄存电路311具有第一信号输出端OUT1和开启信号输入端INP。As shown in FIG. 14A, the gate driving circuit 350 includes N scanning circuits 310 cascaded (for example, cascaded in the column direction), and the shift register circuit 311 of each stage scanning circuit 310 has a first signal output terminal OUT1 and Turn on the signal input INP.

如图14A所示，第m级扫描电路310的移位寄存电路311的开启信号输入端INP连接至第m-1级扫描电路310的第一信号输出端OUT1，并配置为接收第m-1级扫描电路310输出的第一扫描信号，以作为第m级扫描电路310的移位寄存电路311的开启信号。此处，N为大于等于1的整数，m为大于1且小于等于N的整数。例如，位于第一行的移位寄存电路311的开启信号输入端INP配置为接收开启信号STV(参见图6)，该开启信号STV例如可以由时序控制电路330(参见图15B)提供。As shown in FIG. 14A, the turn-on signal input terminal INP of the shift register circuit 311 of the mth-th scan circuit 310 is connected to the first signal output terminal OUT1 of the m-1th-th scan circuit 310, and is configured to receive the m-1th. The first scan signal output from the stage scanning circuit 310 serves as an on signal of the shift register circuit 311 of the mth stage scanning circuit 310. Here, N is an integer greater than or equal to 1, and m is an integer greater than 1 and less than or equal to N. For example, the turn-on signal input terminal INP of the shift register circuit 311 located in the first row is configured to receive the turn-on signal STV (see FIG. 6), which may be provided, for example, by the timing control circuit 330 (see FIG. 15B).

如图6和图14A所示，第一级扫描电路310的移位寄存电路311基于开启信号STV、第一时钟信号和第二时钟信号输出第一扫描信号EM1，并将第一扫描信号EM1提供给第二级扫描电路310的移位寄存电路311的开启信号输入端INP，以输出第一扫描信号EM2，并提供给第三级扫描电路310的移位寄存电路311的开启信号输入端INP……，直至第N-1级第一级扫描电路310的移位寄存电路311输出的第一扫描信号EM(n-1)提供给第N级第一扫描电路310的移位寄存电路311的开启信号输入端INP。例如，如图6所示，每级第一级扫描电路310的移位寄存电路311输出的第一扫描信号，相比于上一级扫描电路310的移位寄存电路311输出的第一扫描信号，在时间上向后移位一个时钟信号的脉冲宽度。As shown in FIGS. 6 and 14A, the shift register circuit 311 of the first stage scanning circuit 310 outputs the first scan signal EM1 based on the turn-on signal STV, the first clock signal, and the second clock signal, and supplies the first scan signal EM1. The turn-on signal input terminal INP of the shift register circuit 311 of the second-stage scan circuit 310 is output to output the first scan signal EM2, and is supplied to the turn-on signal input terminal INP of the shift register circuit 311 of the third-stage scan circuit 310. ..., until the first scan signal EM(n-1) output from the shift register circuit 311 of the N-1th stage first stage scanning circuit 310 is supplied to the shift register circuit 311 of the Nth stage first scan circuit 310 Signal input INP. For example, as shown in FIG. 6, the first scan signal outputted by the shift register circuit 311 of each stage of the first stage scanning circuit 310 is compared with the first scan signal outputted by the shift register circuit 311 of the previous stage scan circuit 310. , shifting the pulse width of one clock signal backward in time.

如图14A所示，第2k-1级扫描电路310(也即，位于奇数行的扫描电路310，对应于图4示出的奇数行GOA单元100)的第一信号生成电路312连接的第一刷新控制信号端REP1为第一信号源ENBO；第2k级扫描电路310(也即，位于偶数行的扫描电路310，对应于图5示出的偶数行GOA单元200)的第一信号生成电路312连接的第一刷新控制信号端REP1为第二信号源ENBE(参见图6)，也即，第一信号源ENBO为奇数级扫描电路310的第一信号生成电路312提供第一刷新控制信号，第二信号源ENBE为偶数级扫描电路310的第一信号生成电路312提供第一刷新控制信号。As shown in FIG. 14A, the first signal generating circuit 312 of the 2k-1th scanning circuit 310 (that is, the scanning circuit 310 located in the odd rows, corresponding to the odd row GOA unit 100 shown in FIG. 4) is connected first. The refresh control signal terminal REP1 is the first signal source ENBO; the second signal scanning circuit 310 (that is, the scan circuit 310 located in the even row, corresponding to the even-line GOA unit 200 shown in FIG. 5) of the first signal generating circuit 312 The connected first refresh control signal terminal REP1 is a second signal source ENBE (see FIG. 6), that is, the first signal source ENBO provides a first refresh control signal for the first signal generating circuit 312 of the odd-numbered scanning circuit 310, The second signal source ENBE provides a first refresh control signal to the first signal generation circuit 312 of the even-numbered scanning circuit 310.

此处，k为大于等于1且小于等于N/2的整数。需要说明的是，在N为奇数的情况下，第N级扫描电路310连接的第一刷新控制信号端REP1为第一信号源ENBO。Here, k is an integer greater than or equal to 1 and less than or equal to N/2. It should be noted that, when N is an odd number, the first refresh control signal terminal REP1 connected to the Nth stage scanning circuit 310 is the first signal source ENBO.

通过将第2k-1级扫描电路310的第一信号生成电路312的第二信号输入端IN2均连接至第一信号源ENBO，并将通过将第2k级扫描电路310的第一信号生成电路312的第二信号输入端IN2均连接至第二信号源ENBE，可以无需针对每行扫描电路设置一个第一刷新控制信号端REP1，由此可以简化电路结构，并降低栅极驱动电路350的尺寸。By connecting the second signal input terminal IN2 of the first signal generating circuit 312 of the 2k-1th stage scanning circuit 310 to the first signal source ENBO, and passing the first signal generating circuit 312 of the 2kth stage scanning circuit 310 The second signal input terminal IN2 is connected to the second signal source ENBE, and it is not necessary to provide a first refresh control signal terminal REP1 for each row of scanning circuits, whereby the circuit structure can be simplified and the size of the gate driving circuit 350 can be reduced.

例如，如图6所示，第一信号源ENBO和第二信号源ENBE提供的第一刷新控制信号的高电平脉冲的个数取决于栅极驱动电路350的扫描电路310的级数。例如，第一信号源ENBO提供的高电平脉冲的个数以及第二信号源ENBE提供的第一刷新控制信号的高电平脉冲的个数之和可以等于栅极驱动电路350的扫描电路310的级数N，由此，第一信号源ENBO和第二信号源ENBE相互配合可以使得N级扫描电路的包括的第二信号输出端OUT2输出N个低脉冲信号，但本公开的实施例不限于此。例如，在不设置空行(dummy行)的情况下，第二信号源ENBE提供的刷新信号的高电平脉冲的个数为k个，第一信号源ENBO提供的刷新信号的高电平脉冲的个数为k或k+1个(在N为奇数的情况下，第一信号源ENBO提供的刷新信号的高电平脉冲的个数为k+1个)。例如，第一信号源ENBO和第二信号源ENBE提供的第一刷新控制信号的高电平脉冲的宽度取决于像素电路对选择控制信号脉冲宽度的需求，具体内容请参见图13C和图13D示出的实施例，在此不再赘述。For example, as shown in FIG. 6, the number of high-level pulses of the first refresh control signal supplied from the first signal source ENBO and the second signal source ENBE depends on the number of stages of the scan circuit 310 of the gate drive circuit 350. For example, the sum of the number of high-level pulses provided by the first signal source ENBO and the number of high-level pulses of the first refresh control signal provided by the second signal source ENBE may be equal to the scan circuit 310 of the gate driving circuit 350. The number N, whereby the first signal source ENBO and the second signal source ENBE cooperate with each other, so that the included second signal output terminal OUT2 of the N-stage scanning circuit outputs N low pulse signals, but the embodiment of the present disclosure does not Limited to this. For example, in the case where no blank line is set, the number of high-level pulses of the refresh signal provided by the second signal source ENBE is k, and the high-level pulse of the refresh signal provided by the first signal source ENBO The number of the signals is k or k+1 (in the case where N is an odd number, the number of high-level pulses of the refresh signal supplied from the first signal source ENBO is k+1). For example, the width of the high-level pulse of the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE depends on the pixel circuit's requirement for selecting the pulse width of the control signal. For details, please refer to FIG. 13C and FIG. 13D. The embodiments are not described here.

如图6所示，第2k级扫描电路310(也即，位于偶数行的扫描电路310)的第一信号生成电路312的第一信号输入端IN1和第二信号输入端IN2分别接收第一扫描信号EM2以及第二信号源ENBE提供的刷新信号，并生成和输出第二扫描信号Gate2。生成第二扫描信号Gate2的具体原理可参见第一信号生成电路312生成第二扫描信号Gate1的原理，在此不再赘述。As shown in FIG. 6, the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 312 of the second-kth scanning circuit 310 (that is, the scanning circuit 310 of the even-numbered row) respectively receive the first scan. The refresh signal provided by the signal EM2 and the second signal source ENBE generates and outputs a second scan signal Gate2. For the specific principle of generating the second scan signal Gate2, refer to the principle that the first signal generating circuit 312 generates the second scan signal Gate1, and details are not described herein again.

需要说明的是，第一信号源ENBO和第二信号源ENBE提供的第一刷新控制信号，不限于图6示出的形式，根据实际应用需求，第一信号源ENBO 和第二信号源ENBE还可以为如下的形式，也即，将图6示出的第一信号源ENBO和第二信号源ENBE提供的第一刷新控制信号在第1阶段st1-第4阶段st4的信号修改为图13E示出的信号。此种情况下，第二信号源ENBE提供的刷新信号与第一信号源ENBO提供的刷新信号电平相反，并且第二信号源ENBE提供的刷新信号例如可通过对第一信号源ENBO提供的刷新信号反相获得，但本公开的实施例不限于此。It should be noted that the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE is not limited to the form shown in FIG. 6. According to actual application requirements, the first signal source ENBO and the second signal source ENBE are further It may be in the form that the signals of the first refresh control signal provided by the first signal source ENBO and the second signal source ENBE shown in FIG. 6 are modified in the first stage st1 - the fourth stage st4 to be shown in FIG. 13E. The signal. In this case, the refresh signal provided by the second signal source ENBE is opposite to the refresh signal level provided by the first signal source ENBO, and the refresh signal provided by the second signal source ENBE can be refreshed, for example, by the first signal source ENBO. The signal is obtained in reverse phase, but embodiments of the present disclosure are not limited thereto.

需要说明的是，本公开中对晶体管的具体类型不做限制，例如可以是TFT(Thin Film Transistor)。It should be noted that the specific type of the transistor is not limited in the present disclosure, and may be, for example, a TFT (Thin Film Transistor).

下面结合图15A对本公开的实施例提供的显示面板300的做示例性说明。图15A示出的显示面板可以是OLED面板。An exemplary illustration of a display panel 300 provided by an embodiment of the present disclosure will be described below with reference to FIG. 15A. The display panel shown in FIG. 15A may be an OLED panel.

如图15A所示，显示面板300包括像素电路阵列，以及图14A示出的栅极驱动电路350。如图15A所示，像素电路阵列包括阵列排布的多个像素电路321，多个像素电路321在列方向上排布成N行，每个像素电路321包括发光控制端EM、选择控制端GAT和复位控制端RESET。As shown in FIG. 15A, the display panel 300 includes a pixel circuit array, and the gate driving circuit 350 shown in FIG. 14A. As shown in FIG. 15A, the pixel circuit array includes a plurality of pixel circuits 321 arranged in an array. The plurality of pixel circuits 321 are arranged in N rows in the column direction, and each of the pixel circuits 321 includes an emission control terminal EM and a selection control terminal GAT. And reset the control terminal RESET.

如图15A所示，第j级扫描电路310的第一信号输出端OUT1连接至第j行的像素电路321的发光控制端EM；第j级扫描电路310的第二信号输出端OUT2连接至第j行像素电路321的选择控制端GAT；第m-1级扫描电路310的第二信号输出端OUT2连接至第m行的像素电路321的复位控制端RESE。此处，j为大于等于1且小于等于N的整数，m为大于1且小于等于N的整数。As shown in FIG. 15A, the first signal output terminal OUT1 of the jth stage scanning circuit 310 is connected to the light emission control terminal EM of the pixel circuit 321 of the jth row; the second signal output terminal OUT2 of the jth stage scanning circuit 310 is connected to the The selection control terminal GAT of the j-row pixel circuit 321; the second signal output terminal OUT2 of the m-1th-th scan circuit 310 is connected to the reset control terminal RESE of the pixel circuit 321 of the m-th row. Here, j is an integer greater than or equal to 1 and less than or equal to N, and m is an integer greater than 1 and less than or equal to N.

通过使得第一信号生成电路312配置为基于第一刷新控制信号与第一扫描信号生成并输出第二扫描信号，扫描电路可以为像素电路的发光控制端EM、选择控制端GAT以及复位控制端RESET分别提供发光控制信号、选择控制信号和复位控制信号，而无需针对像素电路的发光控制端EM、选择控制端GAT以及复位控制端RESET设置至少两个扫描电路，进而可以降低包括该扫描电路310的显示面板的边框尺寸。By causing the first signal generating circuit 312 to be configured to generate and output a second scan signal based on the first refresh control signal and the first scan signal, the scan circuit may be the light emitting control terminal EM of the pixel circuit, the selection control terminal GAT, and the reset control terminal RESET The illumination control signal, the selection control signal, and the reset control signal are respectively provided, and at least two scanning circuits are not required for the illumination control terminal EM of the pixel circuit, the selection control terminal GAT, and the reset control terminal RESET, thereby further reducing the scanning circuit 310. The border size of the display panel.

下面结合图15A示出的显示面板300对本公开的实施例提供的显示面板的驱动方法的做示例性说明。显示面板的驱动方法可以包括以下的步骤S110-S120。The driving method of the display panel provided by the embodiment of the present disclosure is exemplarily described below with reference to the display panel 300 illustrated in FIG. 15A. The driving method of the display panel may include the following steps S110-S120.

步骤S110：使得第j级的扫描电路310的移位寄存电路311生成第一扫描信号，并将第一扫描信号提供给第j级的扫描电路310的第一信号生成电路的第一信号输入端IN1以及第j行的像素电路321的发光控制端EM。Step S110: The shift register circuit 311 of the scan circuit 310 of the jth stage is caused to generate a first scan signal, and the first scan signal is supplied to the first signal input end of the first signal generation circuit of the scan circuit 310 of the jth stage. The light emission control terminal EM of the pixel circuit 321 of IN1 and the jth row.

步骤S120：使得第j级的扫描电路310的第一信号生成电路312基于第一扫描信号和第一刷新控制信号生成第二扫描信号，并将第二扫描信号提供给第j行的像素电路321的选择控制端GAT；同时，对于第n级之外的扫描电路310，将第j级的扫描电路310的第一信号生成电路312生成的第二扫描信号提供给第j+1行的像素电路321的复位控制端RESE。Step S120: The first signal generating circuit 312 of the scanning circuit 310 of the jth stage is caused to generate a second scan signal based on the first scan signal and the first refresh control signal, and supply the second scan signal to the pixel circuit 321 of the jth row. Selecting the control terminal GAT; at the same time, for the scan circuit 310 other than the nth stage, the second scan signal generated by the first signal generating circuit 312 of the scanning circuit 310 of the jth stage is supplied to the pixel circuit of the j+1th row The reset control terminal RESE of 321 .

通过使得第一信号生成电路312基于第一刷新控制信号与第一扫描信号生成并输出第二扫描信号，扫描电路可以为像素电路的发光控制端EM、选择控制端GAT以及复位控制端RESET分别提供发光控制信号、选择控制信号和复位控制信号，而无需针对像素电路的发光控制端EM、选择控制端GAT以及复位控制端RESET设置至少两个扫描电路，进而可以降低包括该扫描电路310的显示面板的边框尺寸。By causing the first signal generating circuit 312 to generate and output a second scan signal based on the first refresh control signal and the first scan signal, the scan circuit can provide the light-emitting control terminal EM, the selection control terminal GAT, and the reset control terminal RESET of the pixel circuit, respectively. The illumination control signal, the selection control signal, and the reset control signal are provided without setting at least two scanning circuits for the illumination control terminal EM, the selection control terminal GAT, and the reset control terminal RESET of the pixel circuit, thereby further reducing the display panel including the scan circuit 310 The border size.

需要说明的是，上述的显示面板的驱动方法不仅可用于显示面板的全面板刷新，还可用于显示面板的部分面板刷。此处，如图8所示，全面板刷新是指，在显示每帧图像时，对显示面板包括的所有显示像素的选择控制端GAT执行逐行开启，以使得显示面板的所有显示像素均能接收到该帧图像对应的数据信号；如图9所示，部分面板刷新是指，在显示每帧图像时，仅开启位于显示面板部分行的显示像素的选择控制端GAT，以使得显示面板的部分行的显示像素接收到该帧图像对应的数据信号，而位于显示面板的其它行的显示像素继续使用对应于前一帧图像的数据信号执行显示功能。通过对显示面板执行部分面板刷新，可以降低显示面板部分区域的刷新频率以及充放电次数，由此可以降低显示面板的驱动功耗。It should be noted that the above-described driving method of the display panel can be used not only for the full-plate refresh of the display panel but also for the partial panel brush of the display panel. Here, as shown in FIG. 8 , the full-board refreshing means that, when displaying each frame of image, the selection control terminal GAT of all display pixels included in the display panel is performed row-by-row, so that all display pixels of the display panel can be Receiving the data signal corresponding to the frame image; as shown in FIG. 9, part of the panel refresh means that, when displaying each frame of image, only the selection control terminal GAT of the display pixel located in the partial row of the display panel is turned on, so that the display panel is The display pixels of the partial rows receive the data signals corresponding to the frame images, while the display pixels located in the other rows of the display panel continue to perform the display function using the data signals corresponding to the images of the previous frame. By performing partial panel refresh on the display panel, the refresh frequency and the number of charge and discharge times of the partial area of the display panel can be reduced, thereby reducing the driving power consumption of the display panel.

下面结合图7和图18对部分面板刷新的远离进行示例性说明。在部分面板刷新式驱动方式中，显示面板300的显示周期包括刷新阶段T_REP和非刷新阶段T_NREP。显示面板的驱动方法包括下述的步骤S121。The distance of partial panel refreshing will be exemplified below with reference to FIGS. 7 and 18. In the partial panel refresh driving mode, the display period of the display panel 300 includes a refresh phase T_REP and a non-refresh phase T_NREP. The driving method of the display panel includes the following step S121.

步骤S121：在非刷新阶段T_NREP，使得第一信号生成电路312的第二信号输入端IN2接收低电平的刷新控制信号。Step S121: In the non-refresh phase T_NREP, the second signal input terminal IN2 of the first signal generating circuit 312 receives the refresh control signal of a low level.

如图18所示，通过使得第一信号生成电路312的第二信号输入端IN2在非刷新阶段T_NREP接收低电平的刷新控制信号(图18示出的标识了 ENBO或ENBE的信号)，位于第一行至第n-1行的像素电路的选择控制端GAT接收的信号(Gate1……Gate(n-1))均为高电平，由此使得位于第一行至第n-1行的像素电路不接收新的数据信号，进而可以降低驱动功耗。此处，n为大于等于1且小于N的整数。As shown in FIG. 18, by causing the second signal input terminal IN2 of the first signal generating circuit 312 to receive a refresh control signal of a low level (a signal indicating ENBO or ENBE shown in FIG. 18) in the non-refresh phase T_NREP, The signals (Gate1 ... Gate(n-1)) received by the selection control terminal GAT of the pixel circuits of the first to nth rows are all at a high level, thereby making the first row to the n-1th row The pixel circuit does not receive a new data signal, which in turn can reduce the driving power consumption. Here, n is an integer greater than or equal to 1 and smaller than N.

如图18所示，对于驱动位于第n行的像素电路的扫描电路的第一信号生成电路312，其第二信号输入端IN2接收正常的第一刷新控制信号，并输出具有低电平脉冲的选择控制信号Gate(n)，以使得第n行的像素电路能够接收到对应的数据信号。As shown in FIG. 18, for the first signal generating circuit 312 for driving the scanning circuit of the pixel circuit located in the nth row, the second signal input terminal IN2 receives the normal first refresh control signal and outputs a pulse having a low level. The control signal Gate(n) is selected such that the pixel circuit of the nth row is capable of receiving the corresponding data signal.

如图18所示，显示面板的驱动方法包括下述的步骤S111-S112。As shown in FIG. 18, the driving method of the display panel includes the following steps S111-S112.

步骤S111：在刷新阶段T_REP，向移位寄存电路311提供具有第一脉冲宽度的时钟信号；Step S111: providing a clock signal having a first pulse width to the shift register circuit 311 in the refresh phase T_REP;

步骤S112：在非刷新阶段T_NREP，向移位寄存电路311提供具有第二脉冲宽度的时钟信号，且第一脉冲宽度大于第二脉冲宽度。Step S112: In the non-refresh phase T_NREP, the clock register signal having the second pulse width is supplied to the shift register circuit 311, and the first pulse width is greater than the second pulse width.

通过使得移位寄存电路311在刷新阶段T_REP接收的时钟信号(第一时钟信号和第二时钟信号)的脉冲宽度大于在非刷新阶段T_NREP接收的时钟信号的脉冲宽度，可以降低移位寄存电路311在刷新阶段T_REP输出的第一扫描信号(例如，EM1、EM2、……EM_n-2)的高电平脉冲的宽度，进而可以进一步地降低驱动功耗。The shift register circuit 311 can be lowered by causing the pulse register of the clock signal (the first clock signal and the second clock signal) received by the shift register circuit 311 in the refresh phase T_REP to be larger than the pulse width of the clock signal received in the non-refresh phase T_NREP. The width of the high-level pulse of the first scan signal (for example, EM1, EM2, ... EM_n-2) outputted in the refresh phase T_REP can further reduce the driving power consumption.

需要说明的是，图7示出的驱动时序图也可用于显示面板的局部区域刷新，其工作原理可以参见图18示出的实施例，在此不再赘述。It should be noted that the driving sequence diagram shown in FIG. 7 can also be used for the local area refreshing of the display panel. For the working principle, refer to the embodiment shown in FIG. 18, and details are not described herein again.

图13B是本公开的实施例提供的另一种扫描电路的示意性框图，如图13B所示，扫描电路310包括移位寄存电路311、第一信号生成电路312、第二信号生成电路313和第一节点361。图13B示出的扫描电路可用于形成图14B示出的栅极驱动电路350以及图15B示出的显示面板300。移位寄存电路311和第一信号生成电路312的具体结构和功能可以参见图13A示出的实施例，在此不再赘述。FIG. 13B is a schematic block diagram of another scanning circuit according to an embodiment of the present disclosure. As shown in FIG. 13B, the scanning circuit 310 includes a shift register circuit 311, a first signal generating circuit 312, a second signal generating circuit 313, and The first node 361. The scanning circuit shown in FIG. 13B can be used to form the gate driving circuit 350 shown in FIG. 14B and the display panel 300 shown in FIG. 15B. The specific structure and function of the shift register circuit 311 and the first signal generating circuit 312 can be referred to the embodiment shown in FIG. 13A, and details are not described herein again.

如图13B所示，第二信号生成电路313具有第一信号输入端IIN1、第二信号输入端IIN2和第三信号输出端OUT3。第二信号生成电路313的第一信号输入端IIN1连接至第一节点361，且配置为接收第一扫描信号，第二信号生成电路313的第二信号输入端IIN2连接至第二刷新控制信号端REP2，以接收第二刷新控制信号端REP2提供的第二刷新控制信号，第二信号生成电路313配置为基于第一扫描信号和第二刷新控制信号生成第三扫描信号。第三扫描信号可以用作像素电路的复位控制端RESE的复位控制信号。As shown in FIG. 13B, the second signal generating circuit 313 has a first signal input terminal IIN1, a second signal input terminal IIN2, and a third signal output terminal OUT3. The first signal input terminal IIN1 of the second signal generating circuit 313 is connected to the first node 361 and configured to receive the first scan signal, and the second signal input terminal IIN2 of the second signal generating circuit 313 is connected to the second refresh control signal terminal. REP2, to receive the second refresh control signal provided by the second refresh control signal terminal REP2, the second signal generating circuit 313 is configured to generate a third scan signal based on the first scan signal and the second refresh control signal. The third scan signal can be used as a reset control signal for the reset control terminal RESE of the pixel circuit.

第二信号生成电路313配置为在第二信号生成电路313的第一信号输入端IIN1和第二信号生成电路313的第二信号输入端IIN2均接收到高电平信号的情况下生成并输出低电平信号；第二信号生成电路313进一步地配置为在第二信号生成电路313的第一信号输入端IIN1和第二信号生成电路313的第二信号输入端IIN2中的任意一个接收到低电平信号的情况下生成并输出高电平信号。The second signal generating circuit 313 is configured to generate and output a low level when both the first signal input terminal IIN1 of the second signal generating circuit 313 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive a high level signal. The level signal; the second signal generating circuit 313 is further configured to receive low power at any one of the first signal input terminal IIN1 of the second signal generating circuit 313 and the second signal input terminal IIN2 of the second signal generating circuit 313 A high level signal is generated and output in the case of a flat signal.

下面结合图13E对本公开的实施例提供的扫描电路为像素电路的复位控制端RESE提供复位控制的信号的原理进行示例性的说明。The principle of the scan circuit provided by the embodiment of the present disclosure for providing the reset control terminal RESE of the pixel circuit with the signal of the reset control is exemplarily described below with reference to FIG. 13E.

例如，如图13E所示，在第1阶段st1、第3阶段st3和第4阶段st4，在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2接收至少一个低电平信号，因此，第三信号输出端OUT3输出高电平信号；在第2阶段st2，在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2均接收高电平信号，因此，第三信号输出端OUT3输出低电平信号。图13E示出的由第三信号输出端OUT3输出的第三扫描信号可用作像素电路的复位控制信号。For example, as shown in FIG. 13E, at the first stage st1, the third stage st3, and the fourth stage st4, at least one low power is received at the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313. a flat signal, therefore, the third signal output terminal OUT3 outputs a high level signal; in the second phase st2, both the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive a high level signal Therefore, the third signal output terminal OUT3 outputs a low level signal. The third scan signal outputted by the third signal output terminal OUT3 shown in Fig. 13E can be used as a reset control signal of the pixel circuit.

例如，第二刷新控制信号端REP2提供的第二刷新控制信号的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。例如，如图13E所示，第二刷新控制信号端REP2提供的第二刷新控制信号与第一刷新控制信号端REP1提供的第一刷新控制信号电平相反，例如，第二刷新控制信号端REP2提供的第二刷新控制信号可通过对第一刷新控制信号端REP1提供的第一刷新控制信号反相获得，但本公开的实施例不限于此。又例如，只要第二刷新控制信号满足在第二阶段st2为高电平且在第三阶段st3为低电平即可获取图13E示出的第三扫描信号。For example, the specific structure of the second refresh control signal provided by the second refresh control signal terminal REP2 may be set according to actual application requirements, which is not specifically limited in the embodiment of the present disclosure. For example, as shown in FIG. 13E, the second refresh control signal provided by the second refresh control signal terminal REP2 is opposite to the first refresh control signal level provided by the first refresh control signal terminal REP1, for example, the second refresh control signal terminal REP2. The supplied second refresh control signal may be obtained by inverting the first refresh control signal supplied from the first refresh control signal terminal REP1, but embodiments of the present disclosure are not limited thereto. For another example, the third scan signal shown in FIG. 13E can be acquired as long as the second refresh control signal satisfies the high level in the second stage st2 and is low in the third stage st3.

需要说明的是，可以通过对第二刷新控制信号调节第三信号输出端OUT3输出的第三扫描信号的具体结构，以满足不同像素电路的驱动需求，具体调节方法可参见通过对第一刷新控制信号调节第二扫描信号的方法，在此不再赘述。It should be noted that the specific structure of the third scan signal output by the third signal output terminal OUT3 can be adjusted by the second refresh control signal to meet the driving requirements of different pixel circuits. For the specific adjustment method, refer to the first refresh control. The method of adjusting the second scan signal by signal is not described here.

图14B和图15B分别示出了本公开的实施例提供的另一种栅极驱动电路350和另一种显示面板300，图14B和图15B示出的栅极驱动电路350和显示面板300包括图13B示出的扫描电路310。图14B示出的栅极驱动电路350和图15B示出的显示面板300分别与图14A示出的栅极驱动电路350和图15A示出的显示面板300类似，在此仅阐述不同之处，相同之处不再赘述。14B and 15B illustrate another gate driving circuit 350 and another display panel 300 provided by an embodiment of the present disclosure, and the gate driving circuit 350 and the display panel 300 illustrated in FIGS. 14B and 15B include A scanning circuit 310 is shown in FIG. 13B. The gate driving circuit 350 illustrated in FIG. 14B and the display panel 300 illustrated in FIG. 15B are similar to the gate driving circuit 350 illustrated in FIG. 14A and the display panel 300 illustrated in FIG. 15A, respectively, and only differences will be explained herein. The similarities are not repeated here.

如图14B所示，第2k-1级扫描电路310(对应于图11示出的奇数行GOA单元100)的第二信号生成电路313连接的第二刷新控制信号端REP2为第二信号源ENBE，第2k级扫描电路3100(对应于图12示出的偶数行GOA单元200)的第二信号生成电路313连接的第二刷新控制信号端REP2为第一信号源ENBO；也即，第一信号源ENBO为偶数级扫描电路310的第二信号生成电路313提供第二刷新控制信号，第二信号源ENBE为奇数级扫描电路310的第二信号生成电路313提供第二刷新控制信号。如图15B所示，第j级扫描电路310的第三信号输出端OUT3连接至第j行像素电路321的复位控制端RESE。As shown in FIG. 14B, the second refresh control signal terminal REP2 connected to the second signal generating circuit 313 of the 2k-1th scanning circuit 310 (corresponding to the odd-line GOA unit 100 shown in FIG. 11) is the second signal source ENBE. The second refresh control signal terminal REP2 connected to the second signal generating circuit 313 of the 2kth scanning circuit 3100 (corresponding to the even-line GOA unit 200 shown in FIG. 12) is the first signal source ENBO; that is, the first signal The source ENBO provides a second refresh control signal for the second signal generation circuit 313 of the even-numbered scan circuit 310, and the second signal source ENBE provides a second refresh control signal for the second signal generation circuit 313 of the odd-numbered scan circuit 310. As shown in FIG. 15B, the third signal output terminal OUT3 of the jth stage scanning circuit 310 is connected to the reset control terminal RESE of the pixel circuit 321 of the jth row.

通过在扫描电路310中设置第二信号生成电路313，可以基于第一扫描信号生成可用于像素电路的复位控制信号的第三扫描信号，由此无需使用上一级扫描电路的第一信号生成电路312输出的第二扫描信号作为像素电路的复位控制信号。By providing the second signal generating circuit 313 in the scanning circuit 310, a third scan signal usable for the reset control signal of the pixel circuit can be generated based on the first scan signal, thereby eliminating the need to use the first signal generating circuit of the upper level scanning circuit The second scan signal output by 312 serves as a reset control signal for the pixel circuit.

下面结合图3-图7以及图10-图12对第一信号生成电路312、第二信号生成电路313以及移位寄存电路311的具体结构做示例性说明。The specific configurations of the first signal generating circuit 312, the second signal generating circuit 313, and the shift register circuit 311 will be exemplarily described below with reference to FIGS. 3-7 and 10-12.

例如，如图3和图4所示的具体示例中，第一信号生成电路312包括第一与非电路30(例如，第一信号生成电路312可以实现为第一与非电路30)，第一与非电路30用于对第一扫描信号以及第一刷新控制信号进行与非运算以生成第二扫描信号。For example, in the specific example shown in FIGS. 3 and 4, the first signal generating circuit 312 includes a first NAND circuit 30 (eg, the first signal generating circuit 312 can be implemented as the first NAND circuit 30), first The NAND circuit 30 is configured to perform a NAND operation on the first scan signal and the first refresh control signal to generate a second scan signal.

第一与非电路30的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。例如，如图4所示，第一与非电路30可以包括用于第一与非电路30的第一N型晶体管MN6、第二N型晶体管MN7、第一P型晶体管MP7和第二P型晶体管MP8。The specific structure of the first NAND circuit 30 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this. For example, as shown in FIG. 4, the first NAND circuit 30 may include a first N-type transistor MN6, a second N-type transistor MN7, a first P-type transistor MP7, and a second P-type for the first NAND circuit 30. Transistor MP8.

如图4所示，第一N型晶体管MN6的第一端与第二电源端VSS相连，第一N型晶体管MN6的控制端与第一信号生成电路312的第二信号输入端 IN2连接；第二N型晶体管MN7的第一端与第一N型晶体管MN6的第二端相连，第二N型晶体管MN7的控制端配置为第一信号生成电路312的第一信号输入端IN1，且与第一节点361相连，第二N型晶体管MN7的第二端连接至第二信号输出端OUT2；第一P型晶体管MP7的第一端与第一电源端VDD相连，第一P型晶体管MP7的控制端与第一信号生成电路312的第二信号输入端IN2连接，第一P型晶体管MP7的第二端连接至第二信号输出端OUT2；第二P型晶体管MP8的第一端与第一电源端VDD相连，第二P型晶体管MP8的控制端与第一节点361相连，第二P型晶体管MP8的第二端与第二信号输出端OUT2相连。As shown in FIG. 4, the first end of the first N-type transistor MN6 is connected to the second power supply terminal VSS, and the control end of the first N-type transistor MN6 is connected to the second signal input terminal IN2 of the first signal generating circuit 312; The first end of the second N-type transistor MN7 is connected to the second end of the first N-type transistor MN6, and the control end of the second N-type transistor MN7 is configured as the first signal input terminal IN1 of the first signal generating circuit 312, and A node 361 is connected, the second end of the second N-type transistor MN7 is connected to the second signal output terminal OUT2; the first end of the first P-type transistor MP7 is connected to the first power terminal VDD, and the control of the first P-type transistor MP7 The terminal is connected to the second signal input terminal IN2 of the first signal generating circuit 312, the second end of the first P-type transistor MP7 is connected to the second signal output terminal OUT2; the first end of the second P-type transistor MP8 is connected to the first power source The terminal VDD is connected, the control terminal of the second P-type transistor MP8 is connected to the first node 361, and the second terminal of the second P-type transistor MP8 is connected to the second signal output terminal OUT2.

需要说明的是，第一电源端VDD和第二电源端VSS可以均输出电压，并且第一电源端VDD输出的电压可以大于第二电源端VSS输出的电压，第二电源端VSS例如可以为接地端，或为公共低压端，但本公开的实施例不限于此。It should be noted that the first power terminal VDD and the second power terminal VSS may each output a voltage, and the voltage outputted by the first power terminal VDD may be greater than the voltage output by the second power terminal VSS, and the second power terminal VSS may be grounded, for example. The end, or a common low voltage end, but embodiments of the present disclosure are not limited thereto.

如图4所示，在第一信号生成电路312的第一信号输入端IN1和第二信号输入端IN2均接收高电平信号时，第一N型晶体管MN6和第二N型晶体管MN7处于导通状态，因此，第二信号输出端OUT2经由导通的晶体管MN6和MN7与第二电源端VSS相连，并输出低电平信号。需要说明的是，在本公开的实施例中，高电平信号的电压值(例如，大于0V)大于低电平信号的电压值(例如，0V)。As shown in FIG. 4, when both the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 312 receive a high level signal, the first N-type transistor MN6 and the second N-type transistor MN7 are in conduction. In the on state, therefore, the second signal output terminal OUT2 is connected to the second power supply terminal VSS via the turned-on transistors MN6 and MN7, and outputs a low level signal. It should be noted that, in an embodiment of the present disclosure, the voltage value of the high level signal (eg, greater than 0 V) is greater than the voltage value of the low level signal (eg, 0 V).

如图4所示，在第一信号生成电路312的第一信号输入端IN1接收低电平信号时，晶体管MP8打开且晶体管MN7关闭，由此，第二信号输出端OUT2经由导通的晶体管MP8与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 4, when the first signal input terminal IN1 of the first signal generating circuit 312 receives the low level signal, the transistor MP8 is turned on and the transistor MN7 is turned off, whereby the second signal output terminal OUT2 is turned on via the turned-on transistor MP8. It is connected to the first power terminal VDD and outputs a high level signal.

如图4所示，在第一信号生成电路312的第二信号输入端IN2接收低电平信号时，晶体管MP7打开且晶体管MN6关闭，由此，第二信号输出端OUT2经由导通的晶体管MP7与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 4, when the second signal input terminal IN2 of the first signal generating circuit 312 receives the low level signal, the transistor MP7 is turned on and the transistor MN6 is turned off, whereby the second signal output terminal OUT2 is turned on via the turned-on transistor MP7. It is connected to the first power terminal VDD and outputs a high level signal.

如图4所示，在第一信号生成电路312的第一信号输入端IN1和第二信号输入端IN2均接收低电平信号时，晶体管MP7和晶体管MP8打开且晶体管MN6和晶体管MN7关闭，由此，第二信号输出端OUT2经由导通的晶体管MP7或MP8与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 4, when both the first signal input terminal IN1 and the second signal input terminal IN2 of the first signal generating circuit 312 receive the low level signal, the transistor MP7 and the transistor MP8 are turned on and the transistor MN6 and the transistor MN7 are turned off. Thus, the second signal output terminal OUT2 is connected to the first power supply terminal VDD via the turned-on transistor MP7 or MP8, and outputs a high level signal.

基于以上描述可知，仅在第一信号生成电路312的第一信号输入端IN1 和第一信号生成电路312的第二信号输入端IN2均接收到高电平信号的情况下，第二信号输出端OUT2才输出低电平信号；而在第一信号生成电路312的第一信号输入端IN1和第一信号生成电路312的第二信号输入端IN2中的任意一个接收到低电平信号的情况下，第二信号输出端OUT2输出高电平信号，也即，图4示出的第一与非电路30可用于对第一扫描信号以及第一刷新控制信号进行与非运算以生成第二扫描信号。Based on the above description, only when the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 receive a high level signal, the second signal output terminal OUT2 outputs a low level signal; and in the case where any one of the first signal input terminal IN1 of the first signal generating circuit 312 and the second signal input terminal IN2 of the first signal generating circuit 312 receives the low level signal The second signal output terminal OUT2 outputs a high level signal, that is, the first NAND circuit 30 shown in FIG. 4 can be used to perform NAND operation on the first scan signal and the first refresh control signal to generate a second scan signal. .

需要说明的是，本公开的实施例提供的第一信号生成电路312不限于图4示出的第一与非电路30，第一信号生成电路312还可以是任何能够对第一扫描信号以及第一刷新控制信号进行与非运算的电路结构。It should be noted that the first signal generating circuit 312 provided by the embodiment of the present disclosure is not limited to the first NAND circuit 30 illustrated in FIG. 4, and the first signal generating circuit 312 may be any capable of pairing the first scanning signal and the first A circuit structure that performs a NAND operation with a refresh control signal.

移位寄存电路311的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。下面结合图3、图4和图6对移位寄存电路311的结构做示例性说明。The specific structure of the shift register circuit 311 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this. The structure of the shift register circuit 311 will be exemplarily described below with reference to Figs. 3, 4 and 6.

例如，如图3和图4所示，移位寄存电路311包括输入电路10和反相器20和第二节点362。输入电路10包括第一端、第二端、第三端和输出端，输入电路10的第一端和第二端分别配置为第一时钟信号输入端CLK1和第二时钟信号输入端CLK2，且分别连接至第一时钟信号提供端CLK和第二时钟信号提供端CLKB，以分别接收第一时钟信号和第二时钟信号。输入电路10的第三端配置为移位寄存电路311的开启信号输入端INP以接收开启信号；输入电路10用于根据开启信号、第一时钟信号和第二时钟信号生成输入控制信号，输入电路10的输出端连接至第二节点362，且配置为输出输入控制信号。For example, as shown in FIGS. 3 and 4, the shift register circuit 311 includes an input circuit 10 and an inverter 20 and a second node 362. The input circuit 10 includes a first end, a second end, a third end, and an output end, and the first end and the second end of the input circuit 10 are respectively configured as a first clock signal input terminal CLK1 and a second clock signal input terminal CLK2, and The first clock signal supply terminal CLK and the second clock signal supply terminal CLKB are respectively connected to receive the first clock signal and the second clock signal, respectively. The third end of the input circuit 10 is configured as an open signal input terminal INP of the shift register circuit 311 to receive an open signal; the input circuit 10 is configured to generate an input control signal according to the turn-on signal, the first clock signal and the second clock signal, and the input circuit The output of 10 is coupled to the second node 362 and is configured to output an input control signal.

如图3和图4所示，反相器20包括输入端和输出端；反相器20的输入端连接至第二节点362，以接收输入控制信号；反相器20用于对输入控制信号的电平进行反相以生成第一扫描信号，也即，在反相器20的输入端接收到高电平信号的情况下，反相器20的输出端接输出低电平信号，在反相器20的输入端接收到低电平信号的情况下，反相器20的输出端接输出高电平信号；反相器20的输出端连接至第一节点361，且配置为第一信号输出端OUT1，以用于输出第一扫描信号。输入电路10和反相器20的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。As shown in FIGS. 3 and 4, the inverter 20 includes an input terminal and an output terminal; the input terminal of the inverter 20 is coupled to the second node 362 to receive an input control signal; and the inverter 20 is configured to input an input control signal. The level is inverted to generate a first scan signal, that is, in the case where a high level signal is received at the input of the inverter 20, the output of the inverter 20 is connected to output a low level signal, When the input end of the phaser 20 receives the low level signal, the output end of the inverter 20 is connected to output a high level signal; the output end of the inverter 20 is connected to the first node 361, and is configured as the first signal. The output terminal OUT1 is for outputting the first scan signal. The specific structure of the input circuit 10 and the inverter 20 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this.

例如，如图4所示，输入电路10包括用于移位寄存电路311的第一N 型晶体管MN1、第二N型晶体管MN2、第一P型晶体管MP1、第二P型晶体管MP2、第三N型晶体管MN3、第四N型晶体管MN4、第三P型晶体管MP3和第四P型晶体管MP3。For example, as shown in FIG. 4, the input circuit 10 includes a first N-type transistor MN1, a second N-type transistor MN2, a first P-type transistor MP1, a second P-type transistor MP2, and a third for the shift register circuit 311. N-type transistor MN3, fourth N-type transistor MN4, third P-type transistor MP3, and fourth P-type transistor MP3.

如图4所示，第一N型晶体管MN1的第一端与第二电源端VSS相连，第一N型晶体管MN1的控制端与第二时钟信号提供端CLKB相连；第二N型晶体管MN2的第一端与第一N型晶体管MN1的第二端相连，第二N型晶体管MN2的控制端与移位寄存电路311的开启信号输入端INP相连，第二N型晶体管MN2的第二端与第二节点362相连；第一P型晶体管MP1的第一端与第一电源端VDD相连，第一P型晶体管MP1的控制端与第一时钟信号提供端CLK相连；第二P型晶体管MP2的第一端与第一P型晶体管MP1的第二端相连，第二P型晶体管MP2的控制端与移位寄存电路311的开启信号输入端INP相连，第二P型晶体管MP2的第二端与第二节点362相连。例如，图4示出的晶体管MN1、MN2、MP1和MP2相结合可构成一个三态门(参见位于图3左下方的输入电路10中左下方的三角形结构)。As shown in FIG. 4, the first end of the first N-type transistor MN1 is connected to the second power supply terminal VSS, the control end of the first N-type transistor MN1 is connected to the second clock signal supply terminal CLKB, and the second N-type transistor MN2 is connected. The first end is connected to the second end of the first N-type transistor MN1, the control end of the second N-type transistor MN2 is connected to the turn-on signal input terminal INP of the shift register circuit 311, and the second end of the second N-type transistor MN2 is The second node 362 is connected; the first end of the first P-type transistor MP1 is connected to the first power supply terminal VDD, the control end of the first P-type transistor MP1 is connected to the first clock signal supply terminal CLK; and the second P-type transistor MP2 is The first end is connected to the second end of the first P-type transistor MP1, the control end of the second P-type transistor MP2 is connected to the turn-on signal input terminal INP of the shift register circuit 311, and the second end of the second P-type transistor MP2 is The second node 362 is connected. For example, the transistors MN1, MN2, MP1, and MP2 shown in FIG. 4 may be combined to form a three-state gate (see the triangular structure at the lower left of the input circuit 10 at the lower left of FIG. 3).

如图4所示，第三N型晶体管MN3的第一端与第二电源端VSS相连，第三N型晶体管MN3的控制端与第一时钟信号提供端CLK相连；第四N型晶体管MN4的第一端与第三N型晶体管MN3的第二端相连，第四N型晶体管MN4的控制端与第一节点361相连，第四N型晶体管MN4的第二端与第二节点362相连；第三P型晶体管MP3的第二端与第二节点362相连，第三P型晶体管MP3的控制端与第一节点361相连；以及第四P型晶体管MP3的第一端与第一电源端VDD相连，第四P型晶体管MP3的控制端与第二时钟信号提供端CLKB相连，第四P型晶体管MP3的第二端与第三P型晶体管MP3的第一端相连。例如，图4示出的晶体管MN3、MN4、MP3和MP4相结合可构成另一个三态门(参见位于图3左下方的输入电路10中右上方的三角形结构)。As shown in FIG. 4, the first end of the third N-type transistor MN3 is connected to the second power supply terminal VSS, and the control end of the third N-type transistor MN3 is connected to the first clock signal supply terminal CLK; the fourth N-type transistor MN4 The first end is connected to the second end of the third N-type transistor MN3, the control end of the fourth N-type transistor MN4 is connected to the first node 361, and the second end of the fourth N-type transistor MN4 is connected to the second node 362; The second end of the three P-type transistor MP3 is connected to the second node 362, the control end of the third P-type transistor MP3 is connected to the first node 361; and the first end of the fourth P-type transistor MP3 is connected to the first power supply terminal VDD. The control terminal of the fourth P-type transistor MP3 is connected to the second clock signal supply terminal CLKB, and the second terminal of the fourth P-type transistor MP3 is connected to the first terminal of the third P-type transistor MP3. For example, the combination of transistors MN3, MN4, MP3, and MP4 shown in FIG. 4 may constitute another tri-state gate (see the triangular structure at the upper right of the input circuit 10 at the lower left of FIG. 3).

需要说明的是，第二时钟信号提供端CLKB输出的第二时钟信号与第一时钟信号提供端CLK输出的第一时钟信号的电平相反，也即，第二时钟信号提供端CLKB输出的第二时钟信号可以通过对第一时钟信号提供端CLK输出的第一时钟信号反相获得。It should be noted that the second clock signal outputted by the second clock signal providing terminal CLKB is opposite to the level of the first clock signal outputted by the first clock signal providing terminal CLK, that is, the second clock signal providing end CLKB outputs the first clock signal. The two clock signals can be obtained by inverting the first clock signal outputted by the first clock signal supply terminal CLK.

例如，如图4所示，反相器20包括第五N型晶体管MN5和第五P型晶体管MP5。第五N型晶体管MN5的第一端与第二电源端VSS相连，第五N型晶体管MN5的控制端与第二节点362相连，第五N型晶体管MN5的第二端与第一节点361相连；第五P型晶体管MP5的第一端与第一电源端VDD相连，第五P型晶体管MP5的控制端与第二节点362相连，第五P型晶体管MP5的第二端与第一节点361相连。For example, as shown in Fig. 4, the inverter 20 includes a fifth N-type transistor MN5 and a fifth P-type transistor MP5. The first end of the fifth N-type transistor MN5 is connected to the second power supply terminal VSS, the control end of the fifth N-type transistor MN5 is connected to the second node 362, and the second end of the fifth N-type transistor MN5 is connected to the first node 361. The first end of the fifth P-type transistor MP5 is connected to the first power supply terminal VDD, the control end of the fifth P-type transistor MP5 is connected to the second node 362, and the second end of the fifth P-type transistor MP5 is connected to the first node 361. Connected.

下面结合图4对反相器20对输入控制信号的电平进行反相以生成第一扫描信号的原理进行示例性说明。在第二节点362接收到高电平信号的情况下，晶体管MN5导通且晶体管MP5关闭，此种情况下，第一节点361经由导通的晶体管MN5连接至第二电源端VSS，并输出低电平信号；在第二节点362接收到低电平信号的情况下，晶体管MP5导通且晶体管MN5关闭，此种情况下，第一节点361经由导通的晶体管MP5连接至第一电源端VDD，并输出低电平信号。因此，图4示出的反相器20能够实现对输入控制信号的电平进行反相。The principle in which the inverter 20 inverts the level of the input control signal to generate the first scan signal will be exemplarily described below with reference to FIG. In the case where the second node 362 receives the high level signal, the transistor MN5 is turned on and the transistor MP5 is turned off. In this case, the first node 361 is connected to the second power supply terminal VSS via the turned-on transistor MN5, and the output is low. Level signal; in the case where the second node 362 receives the low level signal, the transistor MP5 is turned on and the transistor MN5 is turned off. In this case, the first node 361 is connected to the first power terminal VDD via the turned-on transistor MP5. And output a low level signal. Therefore, the inverter 20 shown in FIG. 4 is capable of inverting the level of the input control signal.

例如，在图4所示移位寄存电路311的开启信号输入端INP、第一时钟信号输入端CLK1和第二时钟信号输入端CLK2分别接收到图6示出的开启信号STV、第一时钟信号提供端CLK输出的第一时钟信号以及第二时钟信号提供端CLKB输出的第二时钟信号的情况下，移位寄存电路311的第一信号输出端OUT1输出图6示出的第一扫描信号(记为EM1)，且相比于开启信号STV，第一扫描信号(记为EM1)在时间上向后移位一个时钟信号的脉冲宽度。下面结合图4和图6对移位寄存电路311的工作原理做示例性说明。For example, the turn-on signal input terminal INP, the first clock signal input terminal CLK1, and the second clock signal input terminal CLK2 of the shift register circuit 311 shown in FIG. 4 respectively receive the turn-on signal STV and the first clock signal shown in FIG. In a case where the first clock signal of the terminal CLK output and the second clock signal of the second clock signal supply terminal CLKB are provided, the first signal output terminal OUT1 of the shift register circuit 311 outputs the first scan signal shown in FIG. 6 ( Recorded as EM1), and compared to the turn-on signal STV, the first scan signal (denoted as EM1) is shifted back in time by the pulse width of one clock signal. The operation of the shift register circuit 311 will be exemplarily described below with reference to FIGS. 4 and 6.

如图6所示，在第1阶段，开启信号STV和第一时钟信号CLK为高电平，第二时钟信号CLKB为低电平，并且第一节点361为低电平；此时，如图4所示，晶体管MP3和晶体管MP4打开(此时，晶体管MN2和晶体管MN3虽然开启但不形成通路)，第二节点362经由导通的晶体管MP3和晶体管MP4连接至第一电源端VDD，并输出高电平；第二节点362输出的高电平使得晶体管MN5打开，并使得第一节点361输出低电平。As shown in FIG. 6, in the first stage, the turn-on signal STV and the first clock signal CLK are at a high level, the second clock signal CLKB is at a low level, and the first node 361 is at a low level; As shown in FIG. 4, the transistor MP3 and the transistor MP4 are turned on (at this time, although the transistor MN2 and the transistor MN3 are turned on but no path is formed), the second node 362 is connected to the first power supply terminal VDD via the turned-on transistor MP3 and the transistor MP4, and is output. High level; the high level output by the second node 362 causes the transistor MN5 to turn on and causes the first node 361 to output a low level.

如图6所示，在第2阶段，开启信号STV和第二时钟信号CLKB为高电平，第一时钟信号CLK为低电平，并且第一节点361为低电平；此时，如图4所示，晶体管MN1和晶体管MN2打开(晶体管MP1和晶体管MP3虽然开启但不形成通路)，第二节点362经由导通的晶体管MN1和晶体管 MN2连接至第二电源端VSS，并输出低电平；第二节点362输出的低电平使得晶体管MP5打开，并使得第一节点361输出高电平。As shown in FIG. 6, in the second stage, the turn-on signal STV and the second clock signal CLKB are at a high level, the first clock signal CLK is at a low level, and the first node 361 is at a low level; As shown in FIG. 4, the transistor MN1 and the transistor MN2 are turned on (the transistor MP1 and the transistor MP3 are turned on but do not form a path), and the second node 362 is connected to the second power supply terminal VSS via the turned-on transistor MN1 and the transistor MN2, and outputs a low level. The low level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a high level.

如图6所示，在第3阶段，第一时钟信号CLK为高电平，开启信号STV和第二时钟信号CLKB为低电平，并且第一节点361为高电平；此时，如图4所示，晶体管MN3和晶体管MN4打开(晶体管MP2和晶体管MP4虽然开启但不形成通路)，第二节点362经由导通的晶体管MN3和晶体管MN4连接至第二电源端VSS，并输出低电平；第二节点362输出的低电平使得晶体管MP5打开，并使得第一节点361输出高电平。As shown in FIG. 6, in the third stage, the first clock signal CLK is at a high level, the turn-on signal STV and the second clock signal CLKB are at a low level, and the first node 361 is at a high level; As shown in FIG. 4, the transistor MN3 and the transistor MN4 are turned on (the transistor MP2 and the transistor MP4 are turned on but do not form a path), and the second node 362 is connected to the second power supply terminal VSS via the turned-on transistor MN3 and the transistor MN4, and outputs a low level. The low level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a high level.

如图6所示，在第4阶段，第二时钟信号CLKB为高电平，开启信号STV和第一时钟信号CLK为低电平，并且第一节点361为高电平；此时，如图4所示，晶体管MP1和晶体管MP2打开(晶体管MN1和晶体管MN4开但不形成通路)，第二节点362经由导通的晶体管MP1和晶体管MP2连接至第一电源端VDD，并输出高电平；第二节点362输出的高电平使得晶体管MP5打开，并使得第一节点361输出低电平。As shown in FIG. 6, in the fourth stage, the second clock signal CLKB is at a high level, the turn-on signal STV and the first clock signal CLK are at a low level, and the first node 361 is at a high level; 4, the transistor MP1 and the transistor MP2 are turned on (the transistor MN1 and the transistor MN4 are turned on but no path is formed), and the second node 362 is connected to the first power supply terminal VDD via the turned-on transistor MP1 and the transistor MP2, and outputs a high level; The high level output by the second node 362 causes the transistor MP5 to turn on and causes the first node 361 to output a low level.

因此，移位寄存电路311的第一信号输出端OUT1输出的第一扫描信号(记为EM1)，相比于开启信号STV，在时间上向后移位一个时钟信号的脉冲宽度。Therefore, the first scan signal (denoted as EM1) outputted from the first signal output terminal OUT1 of the shift register circuit 311 is shifted rearward by the pulse width of one clock signal in comparison with the turn-on signal STV.

例如，第二信号生成电路313的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。例如，如图10和图11所示，第二信号生成电路313还包括第二与非电路50(例如，第二信号生成电路313可以实现为第二与非电路50)，第二与非电路50用于对第一扫描信号以及第二刷新控制信号进行与非运算以生成第三扫描信号。第二与非电路50包括第一输入端、第二输入端和信号输出端，其分别配置为第二信号生成电路313的第一信号输入端IIN1、第二信号输入端IN2和信号第三信号输出端OUT3。For example, the specific structure of the second signal generating circuit 313 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this. For example, as shown in FIG. 10 and FIG. 11, the second signal generating circuit 313 further includes a second NAND circuit 50 (for example, the second signal generating circuit 313 can be implemented as the second NAND circuit 50), and the second NAND circuit The 50 is configured to perform a NAND operation on the first scan signal and the second refresh control signal to generate a third scan signal. The second NAND circuit 50 includes a first input terminal, a second input terminal, and a signal output terminal, which are respectively configured as a first signal input terminal IIN1, a second signal input terminal IN2, and a signal third signal of the second signal generating circuit 313. Output OUT3.

第二与非电路50的具体结构可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。例如，如图11所示，第二与非电路50包括第一N型晶体管MN8、第二N型晶体管MN9、第一P型晶体管MP9和第二P型晶体管MP10。The specific structure of the second NAND circuit 50 can be set according to actual application requirements, and the embodiment of the present disclosure does not specifically limit this. For example, as shown in FIG. 11, the second NAND circuit 50 includes a first N-type transistor MN8, a second N-type transistor MN9, a first P-type transistor MP9, and a second P-type transistor MP10.

如图11所示，第一N型晶体管MN8的第一端与第二电源端VSS相连，第一N型晶体管MN8的控制端与第二信号生成电路313的第二信号输入端 IIN2相连；第二N型晶体管MN9的第一端与第一N型晶体管MN8的第二端相连，第二N型晶体管MN9的控制端与第一节点361相连，第二N型晶体管MN9的第二端与第三信号输出端OUT3相连；第一P型晶体管MP9的第一端与第一电源端VDD相连，第一P型晶体管MP9的控制端与第二信号生成电路313的第二信号输入端IIN2相连，第一P型晶体管MP9的第二端与第三信号输出端OUT3相连；以及第二P型晶体管MP10的第一端与第一电源端VDD相连，第二P型晶体管MP10的控制端与第一节点361相连，第二P型晶体管MP10的第二端与第三信号输出端OUT3相连。As shown in FIG. 11, the first end of the first N-type transistor MN8 is connected to the second power supply terminal VSS, and the control end of the first N-type transistor MN8 is connected to the second signal input terminal IIN2 of the second signal generating circuit 313; The first end of the two N-type transistor MN9 is connected to the second end of the first N-type transistor MN8, the control end of the second N-type transistor MN9 is connected to the first node 361, and the second end of the second N-type transistor MN9 is connected to the second end The third signal output terminal OUT3 is connected; the first end of the first P-type transistor MP9 is connected to the first power supply terminal VDD, and the control end of the first P-type transistor MP9 is connected to the second signal input terminal IIN2 of the second signal generating circuit 313. The second end of the first P-type transistor MP9 is connected to the third signal output terminal OUT3; and the first end of the second P-type transistor MP10 is connected to the first power supply terminal VDD, and the control end of the second P-type transistor MP10 is first The node 361 is connected, and the second end of the second P-type transistor MP10 is connected to the third signal output terminal OUT3.

如图11所示，在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2均接收高电平信号时，第一N型晶体管MN8和第二N型晶体管MN9导通，因此，第三信号输出端OUT3经由导通的晶体管MN8和MN9与第二电源端VSS相连，并输出低电平信号。As shown in FIG. 11, when the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 both receive a high level signal, the first N-type transistor MN8 and the second N-type transistor MN9 are turned on. Therefore, the third signal output terminal OUT3 is connected to the second power supply terminal VSS via the turned-on transistors MN8 and MN9, and outputs a low level signal.

如图11所示，在第二信号生成电路313的第一信号输入端IIN1接收低电平信号时，晶体管MP10打开且晶体管MN9关闭，由此，第三信号输出端OUT3经由导通的晶体管MP10与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 11, when the first signal input terminal IIN1 of the second signal generating circuit 313 receives the low level signal, the transistor MP10 is turned on and the transistor MN9 is turned off, whereby the third signal output terminal OUT3 is turned on via the turned-on transistor MP10. It is connected to the first power terminal VDD and outputs a high level signal.

如图11所示，在第二信号生成电路313的第二信号输入端IIN2接收低电平信号时，晶体管MP9打开且晶体管MN8关闭，由此，第三信号输出端OUT3经由导通的晶体管MP9与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 11, when the second signal input terminal IIN2 of the second signal generating circuit 313 receives the low level signal, the transistor MP9 is turned on and the transistor MN8 is turned off, whereby the third signal output terminal OUT3 passes through the turned-on transistor MP9. It is connected to the first power terminal VDD and outputs a high level signal.

如图11所示，在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2均接收低电平信号时，晶体管MP9和MP10打开且晶体管MN8和MN9关闭，由此，第三信号输出端OUT3经由导通的晶体管MP9或MP10与第一电源端VDD相连，并输出高电平信号。As shown in FIG. 11, when both the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive the low level signal, the transistors MP9 and MP10 are turned on and the transistors MN8 and MN9 are turned off, whereby The third signal output terminal OUT3 is connected to the first power supply terminal VDD via the turned-on transistor MP9 or MP10, and outputs a high level signal.

基于以上描述可知，仅在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2均接收到高电平信号的情况下，第三信号输出端OUT3才输出低电平信号；而在第二信号生成电路313的第一信号输入端IIN1和第二信号输入端IIN2中的任意一个接收到低电平信号的情况下，第三信号输出端OUT3输出高电平信号，也即，图11示出的第二与非电路50可用于对第一扫描信号以及第二刷新控制信号进行与非运算以生成第三扫描信号。Based on the above description, only when the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receive the high level signal, the third signal output terminal OUT3 outputs the low level signal. And in the case that any one of the first signal input terminal IIN1 and the second signal input terminal IIN2 of the second signal generating circuit 313 receives the low level signal, the third signal output terminal OUT3 outputs a high level signal, That is, the second NAND circuit 50 shown in FIG. 11 can be used to perform a NAND operation on the first scan signal and the second refresh control signal to generate a third scan signal.

需要说明的是，本公开的实施例提供的第二信号生成电路313不限于图11示出的第二与非电路50，第一信号生成电路312还可以是任何能够对第一扫描信号以及第二刷新控制信号进行与非运算的电路结构。It should be noted that the second signal generating circuit 313 provided by the embodiment of the present disclosure is not limited to the second NAND circuit 50 illustrated in FIG. 11 , and the first signal generating circuit 312 may also be any capable of pairing the first scanning signal and the first The circuit structure of the second refresh control signal for NAND operation.

如图3和图4所示，扫描电路310还包括复位电路40，复位电路40连接至第二节点362，且用于对第一节点361进行初始化复位(也即，使得第一节点361为低电平)。如图4所示，复位电路40包括用于复位电路40的P型晶体管MP6；用于复位电路40的P型晶体管MP6的第一端与第一电源端VDD相连，用于复位电路40的P型晶体管MP6的控制端用于接收初始化复位信号TT_RST，并且，用于复位电路40的P型晶体管MP6的第二端与第二节点362相连。As shown in FIGS. 3 and 4, the scan circuit 310 further includes a reset circuit 40 coupled to the second node 362 and configured to perform an initial reset on the first node 361 (ie, to cause the first node 361 to be low Level). As shown in FIG. 4, the reset circuit 40 includes a P-type transistor MP6 for the reset circuit 40; the first end of the P-type transistor MP6 for the reset circuit 40 is connected to the first power supply terminal VDD for resetting the circuit 40. The control terminal of the transistor MP6 is for receiving the initialization reset signal TT_RST, and the second terminal of the P-type transistor MP6 for the reset circuit 40 is connected to the second node 362.

如图4所示，在晶体管MP6的控制端接收低电平信号的情况下，第二节点经由导通的晶体管MP6与第一电源端VDD相连，并使得晶体管MN5打开，因此，第一节点361经由导通的晶体管MN5与第二电源端VSS相连，并输出低电平的信号。由此，复位电路40实现了对第一节点361的初始化复位。As shown in FIG. 4, in the case where the control terminal of the transistor MP6 receives the low-level signal, the second node is connected to the first power supply terminal VDD via the turned-on transistor MP6, and causes the transistor MN5 to be turned on. Therefore, the first node 361 The transistor MN5 that is turned on is connected to the second power supply terminal VSS, and outputs a signal of a low level. Thus, the reset circuit 40 implements an initial reset of the first node 361.

需要说明的是，复位电路40不限于包括P型晶体管的电路结构，根据实际应用需求，复位电路40还可以实现为包括N型晶体管的电路结构，此种情况下，初始化复位信号TT_RST需要设置为高电平信号。It should be noted that the reset circuit 40 is not limited to a circuit structure including a P-type transistor. According to actual application requirements, the reset circuit 40 can also be implemented as a circuit structure including an N-type transistor. In this case, the initialization reset signal TT_RST needs to be set to High level signal.

需要说明的是，复位电路40对第一节点361进行初始化复位的时间可以根据实际应用需求进行设定，本公开的实施例对此不做具体限定。例如，对于包括多个像素电路的显示面板，可以在每帧图像显示完毕后、显示下一帧图像前(也即，相邻显示帧之间的空白时间)，对显示面板包括的多个像素电路的第一节点361同时执行复位操作。又例如，还可以对显示面板包括的多个像素电路进行逐行复位，在此不再赘述。It should be noted that the time for the resetting and resetting of the first node 361 by the reset circuit 40 may be set according to actual application requirements, which is not specifically limited in the embodiment of the present disclosure. For example, for a display panel including a plurality of pixel circuits, a plurality of pixels included in the display panel may be displayed after each frame of image is displayed and before the next frame image is displayed (that is, a blank time between adjacent display frames). The first node 361 of the circuit simultaneously performs a reset operation. For example, a plurality of pixel circuits included in the display panel may be reset line by line, and details are not described herein again.

本公开的至少一个实施例还提供了一种显示装置1，如图16所示，该显示装置1包括由多个像素电路321构成的像素电路阵列。例如，该显示装置1还可以包括数据驱动电路。数据驱动电路通过数据线332与像素电路321电连接并用于提供数据信号给对应的像素电路；栅极驱动电路310通过栅线331与像素电路321电连接并用于提供栅极扫描信号(例如，选择控制信号)给对应的像素电路。At least one embodiment of the present disclosure also provides a display device 1 including a pixel circuit array composed of a plurality of pixel circuits 321 as shown in FIG. For example, the display device 1 may further include a data driving circuit. The data driving circuit is electrically connected to the pixel circuit 321 through the data line 332 and used to supply a data signal to the corresponding pixel circuit; the gate driving circuit 310 is electrically connected to the pixel circuit 321 through the gate line 331 and used to provide a gate scanning signal (for example, selection) The control signal is given to the corresponding pixel circuit.

本公开的至少一个实施例还提供了一种显示装置1，如图17所示，该显示装置包括本公开任一实施例提供的扫描电路310、本公开任一实施例提供的栅极驱动电路350或本公开任一实施例提供的任一显示面板300。At least one embodiment of the present disclosure further provides a display device 1 , as shown in FIG. 17 , the display device includes the scan circuit 310 provided by any embodiment of the present disclosure, and the gate drive circuit provided by any embodiment of the present disclosure. 350 or any of the display panels 300 provided by any of the embodiments of the present disclosure.

需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。It should be noted that the display device 1 in this embodiment may be: a liquid crystal panel, a liquid crystal television, a display, an OLED panel, an OLED television, an electronic paper display device, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigation device, and the like. A product or part that has a display function.

参考附图3至附图5所示，本公开的一个实施例还提供了一种显示面板的驱动电路，其包括奇数行GOA单元100和偶数行GOA单元200，奇数行GOA单元100对应驱动奇数行像素电路101，偶数行GOA单元200对应驱动偶数行像素电路201，奇数行GOA单元100和偶数行GOA单元200中的每个GOA单元包括：输入电路10、反相器20和第一与非电路30。Referring to FIG. 3 to FIG. 5, an embodiment of the present disclosure further provides a driving circuit for a display panel including an odd row GOA unit 100 and an even row GOA unit 200, and the odd row GOA unit 100 correspondingly drives an odd number. The row pixel circuit 101, the even row GOA unit 200 correspondingly drives the even row pixel circuit 201, and each of the odd row GOA unit 100 and the even row GOA unit 200 includes: an input circuit 10, an inverter 20, and a first AND Circuit 30.

如图3所示，输入电路10分别与第一时钟信号提供端CLK和第二时钟信号提供端CLKB相连，位于第一行的输入电路10与信号输入端INPT相连以接收初始信号(例如，初始信号STV)，位于其余行的输入电路10与位于上一行的反相器20的输出端相连，以将反相器20输出的EM信号(也即，第一扫描信号)作为初始信号。输入电路10用于基于初始信号、第一时钟信号提供端CLK提供的第一时钟信号和第二时钟信号提供端CLKB提供的第二时钟信号生成输入控制信号。As shown in FIG. 3, the input circuit 10 is connected to the first clock signal supply terminal CLK and the second clock signal supply terminal CLKB, respectively, and the input circuit 10 located in the first row is connected to the signal input terminal INPT to receive an initial signal (for example, an initial The signal STV), the input circuit 10 located in the remaining row, is connected to the output of the inverter 20 located in the upper row to use the EM signal (i.e., the first scan signal) output from the inverter 20 as an initial signal. The input circuit 10 is configured to generate an input control signal based on the initial signal, the first clock signal provided by the first clock signal providing terminal CLK, and the second clock signal provided by the second clock signal providing terminal CLKB.

反相器20与输入电路10相连，反相器20用于对所述输入控制信号进行反相以输出EM信号(也即，第一扫描信号)至本行GOA单元对应的像素电路，例如奇数行GOA单元100中的反相器20输出的是EM_n信号至对应的像素电路101，偶数行GOA单元200中的反相器20输出的是EM_n+1信号至对应的像素电路201，并且奇数行GOA单元100中的反相器20输出的EM信号可记作EM_O(参见图4)，偶数行GOA单元200中的反相器20输出的EM信号可记作EM_E(参见图4)。The inverter 20 is connected to the input circuit 10, and the inverter 20 is configured to invert the input control signal to output an EM signal (that is, a first scan signal) to a pixel circuit corresponding to the GOA unit of the row, for example, an odd number. The inverter 20 in the row GOA unit 100 outputs an EM_n signal to the corresponding pixel circuit 101, and the inverter 20 in the even-line GOA unit 200 outputs an EM_n+1 signal to the corresponding pixel circuit 201, and an odd line. The EM signal output from the inverter 20 in the GOA unit 100 can be referred to as EM_O (see FIG. 4), and the EM signal output from the inverter 20 in the even-line GOA unit 200 can be referred to as EM_E (see FIG. 4).

第一与非电路30的第一输入端与反相器20相连，第一与非电路30的第二输入端与第一刷新控制信号端REP1(第一信号源ENBO或第二信号源ENBE)相连，例如奇数行GOA单元100对应的第一刷新控制信号端记作ENBO、偶数行GOA单元200对应的第一刷新控制信号端记作ENBE，第一与非电路30用于对EM信号和第一刷新控制信号端提供的第一刷新控制信号进行与非运算以输出第二扫描信号例如Gate(n)(也记为Gate_n)至本行GOA单元对应的像素电路，例如奇数行GOA单元100输出的是Gate_n信号至对应的像素电路101，偶数行GOA单元200输出的是Gate_n+1信号至对应的像素电路201。The first input end of the first NAND circuit 30 is connected to the inverter 20, and the second input end of the first NAND circuit 30 and the first refresh control signal terminal REP1 (the first signal source ENBO or the second signal source ENBE) Connected, for example, the first refresh control signal end corresponding to the odd row GOA unit 100 is referred to as ENBO, the first refresh control signal end corresponding to the even row GOA unit 200 is denoted as ENBE, and the first NAND circuit 30 is used for the EM signal and the a first refresh control signal provided by the refresh control signal terminal performs a NAND operation to output a second scan signal such as Gate(n) (also referred to as Gate_n) to a pixel circuit corresponding to the GOA unit of the row, for example, an odd-line GOA unit 100 output The Gate_n signal is sent to the corresponding pixel circuit 101, and the even-line GOA unit 200 outputs the Gate_n+1 signal to the corresponding pixel circuit 201.

像素电路可如图1所示，其包括7个晶体管T1至T7，但本公开的实施例不限于此。The pixel circuit may be as shown in FIG. 1, which includes seven transistors T1 to T7, but embodiments of the present disclosure are not limited thereto.

本公开实施例提出的显示面板的驱动电路，可以使得EM信号(也即，第一扫描信号)和第二扫描信号通过单个GOA单元输出，从而可减小边框，并且通过控制第一刷新控制信号使其既可以实现显示面板全面板刷新，又可以实现局部刷新，这样在显示面板显示的不同帧的显示图像变化区域较小的情况下，对应于不发生变化的显示区域不刷新，由此可以降低功耗。此外，本公开的显示面板还可以具有局部区域显示功能，由此可以根据实际应用需求使得显示面板的部分显示区域执行实现功能，以降低功耗。The driving circuit of the display panel proposed by the embodiment of the present disclosure may enable the EM signal (that is, the first scan signal) and the second scan signal to be output through a single GOA unit, thereby reducing the frame and controlling the first refresh control signal The display panel can be fully refreshed and partially refreshed, so that when the display image change area of different frames displayed on the display panel is small, the display area corresponding to the non-change is not refreshed, thereby Reduce power consumption. In addition, the display panel of the present disclosure may also have a partial area display function, whereby a part of the display area of the display panel can be implemented to implement functions according to actual application requirements to reduce power consumption.

根据本公开的一个实施例，如图3至图5所示，本行GOA单元输出的第一扫描信号作为下一行GOA单元的初始信号，本行GOA单元输出的第二扫描信号作为下一行GOA单元对应的像素电路的复位信号。According to an embodiment of the present disclosure, as shown in FIG. 3 to FIG. 5, the first scan signal output by the GOA unit of the row is used as the initial signal of the next row of GOA units, and the second scan signal output by the GOA unit of the row is used as the next row of GOA. The reset signal of the pixel circuit corresponding to the unit.

并且，如图3至图5所示，每个GOA单元还包括复位电路40，复位电路40用于对第一节点361进行初始化复位。Moreover, as shown in FIG. 3 to FIG. 5, each GOA unit further includes a reset circuit 40 for performing an initial reset on the first node 361.

在本公开的一个实施例中，如图4或图5所示，输入电路10包括：第一NMOS管MN1(也即，用于移位寄存电路311的第一N型晶体管的一种示例)、第二NMOS管MN2(也即，用于移位寄存电路311的第二N型晶体管的一种示例)、第一PMOS管MP1(也即，用于移位寄存电路311的第一P型晶体管的一种示例)、第二PMOS管MP2(也即，用于移位寄存电路311的第二P型晶体管的一种示例)、第三NMOS管MN3(也即，用于移位寄存电路311的第三N型晶体管的一种示例)、第四NMOS管MN4(也即，用于移位寄存电路311的第四N型晶体管的一种示例)、第三PMOS管MP3(也即，用于移位寄存电路311的第三P型晶体管的一种示例)和第四PMOS管MP4(也即，用于移位寄存电路311的第四P型晶体管的一种示例)。In one embodiment of the present disclosure, as shown in FIG. 4 or FIG. 5, the input circuit 10 includes: a first NMOS transistor MN1 (that is, an example of a first N-type transistor for shift register circuit 311) a second NMOS transistor MN2 (that is, an example of a second N-type transistor for shift register circuit 311), a first PMOS transistor MP1 (that is, a first P-type for shift register circuit 311) An example of a transistor), a second PMOS transistor MP2 (ie, an example of a second P-type transistor for shift register circuit 311), and a third NMOS transistor MN3 (ie, for shift register circuits) An example of a third N-type transistor of 311), a fourth NMOS transistor MN4 (that is, an example of a fourth N-type transistor for shift register circuit 311), and a third PMOS transistor MP3 (ie, One example of the third P-type transistor for the shift register circuit 311) and the fourth PMOS transistor MP4 (that is, one example of the fourth P-type transistor for shift register circuit 311).

如图4或图5所示，第一NMOS管MN1的第一端与第二电源端VSS相连，第一NMOS管MN1的控制端与第二时钟信号提供端CLKB相连；第二 NMOS管MN2的第一端与第一NMOS管MN1的第二端相连，第二NMOS管MN2的控制端与输入电路10的输入端相连；第一PMOS管MP1的第一端与第一电源端VDD相连，第一PMOS管MP1的控制端与第一时钟信号提供端CLK相连；第二PMOS管MP2的第一端与第一PMOS管MP1的第二端相连，第二PMOS管MP2的控制端与输入电路10的输入端相连，第二PMOS管MP2的第二端与第二NMOS管MN2的第二端均与第二节点362相连，第二节点362作为输入电路10的输出端；如图3所示，第一NMOS管MN1、第二NMOS管MN2以及第一PMOS管MP1、第二PMOS管MP2形成了一个三态门。As shown in FIG. 4 or FIG. 5, the first end of the first NMOS transistor MN1 is connected to the second power supply terminal VSS, the control end of the first NMOS transistor MN1 is connected to the second clock signal supply terminal CLKB, and the second NMOS transistor MN2 is connected. The first end is connected to the second end of the first NMOS transistor MN1, the control end of the second NMOS transistor MN2 is connected to the input end of the input circuit 10; the first end of the first PMOS transistor MP1 is connected to the first power supply terminal VDD, The control terminal of the PMOS transistor MP1 is connected to the first clock signal supply terminal CLK; the first terminal of the second PMOS transistor MP2 is connected to the second terminal of the first PMOS transistor MP1, and the control terminal of the second PMOS transistor MP2 and the input circuit 10 The input ends are connected, the second end of the second PMOS transistor MP2 and the second end of the second NMOS transistor MN2 are both connected to the second node 362, and the second node 362 is used as the output end of the input circuit 10; as shown in FIG. The first NMOS transistor MN1, the second NMOS transistor MN2, and the first PMOS transistor MP1 and the second PMOS transistor MP2 form a three-state gate.

第三NMOS管MN3的第一端与第二电源端VSS相连，第三NMOS管MN3的控制端与第一时钟信号提供端CLK相连；第四NMOS管MN4的第一端与第三NMOS管MN3的第二端相连；第三PMOS管MP3的第二端与第四NMOS管MN4的第二端相连且与第二节点362相连，第三PMOS管MP3的控制端与第四NMOS管MN4的控制端相连且与反相器20的输出端相连；第四PMOS管MP4的第一端与第一电源端VDD相连，第四PMOS管MP4的控制端与第二时钟信号提供端CLKB相连，第四PMOS管MP4的第二端与第三PMOS管MP3的第一端相连。如图3所示，第三NMOS管MN3、第四NMOS管MN4以及第三PMOS管MP3、第四PMOS管MP4组成了另一个三态门。也即，输入模块20可以由两个三态门组成。The first end of the third NMOS transistor MN3 is connected to the second power supply terminal VSS, and the control end of the third NMOS transistor MN3 is connected to the first clock signal supply terminal CLK; the first end of the fourth NMOS transistor MN4 and the third NMOS transistor MN3 The second end of the third PMOS transistor MP3 is connected to the second end of the fourth NMOS transistor MN4 and is connected to the second node 362. The control terminal of the third PMOS transistor MP3 and the fourth NMOS transistor MN4 are controlled. The terminal is connected to the output terminal of the inverter 20; the first terminal of the fourth PMOS transistor MP4 is connected to the first power terminal VDD, and the control terminal of the fourth PMOS transistor MP4 is connected to the second clock signal supply terminal CLKB. The second end of the PMOS transistor MP4 is connected to the first end of the third PMOS transistor MP3. As shown in FIG. 3, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the third PMOS transistor MP3 and the fourth PMOS transistor MP4 constitute another tri-state gate. That is, the input module 20 can be composed of two three-state gates.

根据本公开的一个实施例，如图4或图5所示，反相器20包括：第五NMOS管MN5(也即，用于移位寄存电路311的第五N型晶体管的一种示例)和第五PMOS管MP5(也即，用于移位寄存电路311的第五P型晶体管的一种示例)。第五NMOS管MN5的第一端与第二电源端VSS相连，第五NMOS管MN5的控制端与所述第二节点362相连；第五PMOS管MP5的第一端与第一电源端VDD相连，第五PMOS管MP5的控制端与所述第二节点362相连，第五PMOS管MP5的第二端与第五NMOS管MN5的第二端均与第一节点361，即N点，相连，所述第一节点361作为反相器20的输出端。第一节点361还作为下一行GOA单元的信号输入端INPT。According to an embodiment of the present disclosure, as shown in FIG. 4 or FIG. 5, the inverter 20 includes: a fifth NMOS transistor MN5 (that is, an example of a fifth N-type transistor for shift register circuit 311) And a fifth PMOS transistor MP5 (that is, an example of a fifth P-type transistor for shift register circuit 311). The first end of the fifth NMOS transistor MN5 is connected to the second power supply terminal VSS, the control end of the fifth NMOS transistor MN5 is connected to the second node 362, and the first end of the fifth PMOS transistor MP5 is connected to the first power supply terminal VDD. The control end of the fifth PMOS transistor MP5 is connected to the second node 362, and the second end of the fifth PMOS transistor MP5 and the second end of the fifth NMOS transistor MN5 are connected to the first node 361, that is, the N point. The first node 361 acts as an output of the inverter 20. The first node 361 also serves as the signal input INPT of the next row of GOA units.

根据本公开的一个实施例，如图4或图5所示，第一与非电路包括第六NMOS管MN6(也即，用于第一与非电路30的第一N型晶体管的一种示例)、第七NMOS管MN7(也即，用于第一与非电路30的第二N型晶体管的一种示例)、第七PMOS管MP7(也即，用于第一与非电路30的第一P型晶体管的一种示例)和第八PMOS管MP8(也即，用于第一与非电路30的第二P型晶体管的一种示例)。According to an embodiment of the present disclosure, as shown in FIG. 4 or FIG. 5, the first NAND circuit includes a sixth NMOS transistor MN6 (that is, an example of the first N-type transistor for the first NAND circuit 30). a seventh NMOS transistor MN7 (that is, an example of a second N-type transistor for the first NAND circuit 30), a seventh PMOS transistor MP7 (that is, a first NAND circuit 30) An example of a P-type transistor) and an eighth PMOS transistor MP8 (ie, an example of a second P-type transistor for the first NAND circuit 30).

如图4或图5所示，第六NMOS管MN6的第一端与第二电源端VSS相连，第七NMOS管MN7的第一端与第六NMOS管MN6的第二端相连，第七NMOS管MN7的控制端与第一节点361相连；第七PMOS管MP7的第一端与第一电源端VDD相连，第七PMOS管MP7的控制端与第六NMOS管MN6的控制端相连后与第一刷新控制信号端(第一信号源ENBO或第二信号源ENBE)相连，第七PMOS管MP7的第二端与第七NMOS管MN7的第二端均与第三节点相连，第三节点作为第一与非电路30的输出端Gate_O(Gate_E)；第八PMOS管MP8的第一端与第一电源端VDD相连，第八PMOS管MP8的控制端与第一节点361相连，第八PMOS管MP8的第二端与第三节点相连。As shown in FIG. 4 or FIG. 5, the first end of the sixth NMOS transistor MN6 is connected to the second power supply terminal VSS, and the first end of the seventh NMOS transistor MN7 is connected to the second end of the sixth NMOS transistor MN6, and the seventh NMOS is connected. The control terminal of the MN7 is connected to the first node 361; the first end of the seventh PMOS transistor MP7 is connected to the first power terminal VDD, and the control terminal of the seventh PMOS transistor MP7 is connected to the control terminal of the sixth NMOS transistor MN6. A refresh control signal terminal (the first signal source ENBO or the second signal source ENBE) is connected, and the second end of the seventh PMOS transistor MP7 and the second end of the seventh NMOS transistor MN7 are both connected to the third node, and the third node is The output end Gate_O (Gate_E) of the first NAND circuit 30; the first end of the eighth PMOS transistor MP8 is connected to the first power supply terminal VDD, and the control end of the eighth PMOS transistor MP8 is connected to the first node 361, and the eighth PMOS transistor The second end of the MP8 is connected to the third node.

如图4或图5所示，复位电路40包括第六PMOS管MP6(也即，用于复位电路40的P型晶体管的一种示例)，第六PMOS管MP6的第一端与第一电源端VDD相连，第六PMOS管MP6的控制端用于接收初始化复位信号TT_RST，第六PMOS管MP6的第二端与输入电路10的输出端即第二节点362相连。As shown in FIG. 4 or FIG. 5, the reset circuit 40 includes a sixth PMOS transistor MP6 (that is, an example of a P-type transistor for the reset circuit 40), and the first end of the sixth PMOS transistor MP6 and the first power supply The terminal VDD is connected, the control terminal of the sixth PMOS transistor MP6 is configured to receive the initialization reset signal TT_RST, and the second terminal of the sixth PMOS transistor MP6 is connected to the output terminal of the input circuit 10, that is, the second node 362.

下面参照附图4以及附图6来说明本公开实施例的显示面板的驱动电路的工作原理。The operation principle of the driving circuit of the display panel of the embodiment of the present disclosure will be described below with reference to FIG. 4 and FIG.

需要说明的是，图6中CLKB对应的第二时钟信号提供端提供的第二时钟信号，CLK对应的是第一时钟信号提供端提供的第一时钟信号，此处CLKB可以为CLK反相后的信号；TT_RST信号为复位电路40接收到的初始化复位信号；例如，在每帧图像显示结束后、下一帧图像显示开始前，通过复位使得N点初始化为低电平；ENBO与ENBE的电平可以相反，且可以分别对应奇数行GOA单元和偶数行GOA单元，如图6所示，ENBO与ENBE可以分别与EM信号(例如，所在行的EM信号)作“与非”运算生成本行的第二扫描信号，例如Gate(n)(例如，在一些实施例中，可以作为下一行的复位信号)，其脉冲宽度根据像素电路的需求进行设置，脉冲个数与奇数行或偶数行行数一致。It should be noted that the second clock signal provided by the second clock signal providing end corresponding to the CLKB in FIG. 6 corresponds to the first clock signal provided by the first clock signal providing end, where CLKB can be after the CLK is inverted. The TT_RST signal is an initialization reset signal received by the reset circuit 40; for example, after the end of each frame of image display, before the start of the next frame image display, the N point is initialized to a low level by reset; the power of ENBO and ENBE The flats can be reversed and can correspond to odd-line GOA units and even-numbered GOA units, respectively. As shown in FIG. 6, ENBO and ENBE can perform NAND operations with the EM signal (for example, the EM signal of the line) to generate the line. a second scan signal, such as Gate(n) (eg, in some embodiments, can be used as a reset signal for the next row), the pulse width of which is set according to the requirements of the pixel circuit, the number of pulses and the odd or even rows The number is the same.

图6中的STV为位于第一行的输入电路10接收的初始信号，N点初始状态可以为低电平。The STV in FIG. 6 is an initial signal received by the input circuit 10 located in the first row, and the initial state of the N point may be a low level.

在第1阶段，STV为高电平，CLK为高电平，CLKB为低电平，MP3与MP4管打开，输入控制信号为高电平，即高电平输入至反相器20，反相器20输出低电平，N点维持初始状态的低电平；In the first stage, STV is high, CLK is high, CLKB is low, MP3 and MP4 are open, input control signal is high, ie high level input to inverter 20, inverting The device 20 outputs a low level, and the N point maintains a low level of the initial state;

第2阶段，STV仍为高电平，CLK为低电平，CLKB为高电平，MN1与MN2管打开，输入控制信号为低电平，即低电平输入至反相器20，反相器20输出高电平，因此N点为高电平；In the second stage, STV is still high, CLK is low, CLKB is high, MN1 and MN2 are open, input control signal is low, ie low level input to inverter 20, inverting The device 20 outputs a high level, so the N point is a high level;

第3阶段，STV为低电平，CLK为高电平，CLKB为低电平，MN3与MN4管打开，输入控制信号为低电平，即低电平输入至反相器20，反相器20输出高电平，因此N点维持上一阶段高电平状态；In the third stage, STV is low, CLK is high, CLKB is low, MN3 and MN4 are open, input control signal is low, ie low level input to inverter 20, inverter 20 outputs a high level, so the N point maintains the previous stage high state;

第4阶段，STV为低电平，CLK为低电平，CLKB为高电平，MP1与MP2管打开，输入控制信号为高电平，即高电平输入至反相器20，反相器20输出低电平，因此N点为低电平。In the fourth stage, STV is low, CLK is low, CLKB is high, MP1 and MP2 are open, input control signal is high, ie high level is input to inverter 20, inverter 20 outputs a low level, so the N point is low.

经过上述四个阶段，初始信号STV移位形成EM1，基于同样原理，位于其它行的GOA单元向后逐行移位形成EM2,EM3……EMn。After the above four stages, the initial signal STV shifts to form EM1, and based on the same principle, the GOA units located in other rows are shifted backward by line to form EM2, EM3, ... EMn.

在EM1所在行为Dummy行(虚拟行或空行)的情况下，EM2所在行输入为起始行(充当第二行的EM信号)。MN6、MN7、MP7、MP8相互配合实现“与非”门电路的功能，也即，实现为第一与非电路，只有EM信号及第一刷新控制信号均为高电平时，第一与非电路才输出低电平，其余情况第一与非电路输出高电平。当EM1与第一信号源ENBO的第一个脉冲作“与非”运算后，形成Gate1(充当第2行的Reset信号)，EM2与第二信号源ENBE第一个脉冲作“与非”运算后，形成Gate2(充当第2行的Gate信号及第三行的Reset信号)，如此完成第2行的像素控制信号输出。并且，后续行的GOA单元工作原理与此类似，以前一行GOA单元输出的第二扫描信号(例如Gate_n)作为与本行GOA单元位于同一行的像素电路的复位信号,本行的GOA单元输出的第二扫描信号作为与本行GOA单元位于同一行的像素电路的选择控制信号，本行的GOA单元输出的第一扫描信号(EM信号)作为与本行GOA单元位于同一行的像素电路的发光控制信号，由此可以实现像素电路的逐行驱动。In the case where the EM1 is in the Dummy line (virtual line or blank line), the line in which EM2 is located is the start line (acting as the EM signal of the second line). MN6, MN7, MP7, and MP8 cooperate to realize the function of the NAND gate circuit, that is, the first NAND circuit, and only the EM signal and the first refresh control signal are high level, the first NAND circuit Only the low level is output, and the rest of the first and second circuit outputs a high level. When EM1 is NANDed with the first pulse of the first signal source ENBO, Gate1 is formed (acting as the Reset signal of the second row), and the first pulse of EM2 and the second signal source ENBE is NANDed. Thereafter, Gate2 (serving as the Gate signal of the second row and the Reset signal of the third row) is formed, thus completing the pixel control signal output of the second row. Moreover, the working principle of the GOA unit of the subsequent row is similar. The second scan signal (for example, Gate_n) outputted by the previous row of GOA units is used as the reset signal of the pixel circuit in the same row as the GOA unit of the row, and the GOA unit output of the row is output. The second scan signal is a selection control signal of the pixel circuit located in the same row as the GOA unit of the row, and the first scan signal (EM signal) output by the GOA unit of the row is used as the light emission of the pixel circuit in the same row as the GOA unit of the row. The signal is controlled, whereby the progressive driving of the pixel circuit can be achieved.

在本公开的实施例中，第一扫描信号(例如，EM信号)和第二扫描信号(例如，Gate_n)通过单个GOA单元输出，由此可以减小边框尺寸。此外，通过控制第一刷新控制信号，显示面板既可以实现全面板刷新功能，又可以实现局部刷新功能。In an embodiment of the present disclosure, the first scan signal (eg, EM signal) and the second scan signal (eg, Gate_n) are output through a single GOA unit, whereby the frame size can be reduced. In addition, by controlling the first refresh control signal, the display panel can realize the full-plate refresh function and the partial refresh function.

图6是本公开的实施例提供的一种显示面板的驱动时序图，该驱动时序图可用于实现显示面板的全面板刷新功能，该驱动时序图示出了EM信号与Gate信号的波形图。图7是本公开的实施例提供的另一种显示面板的驱动时序图，该驱动时序图可用于实现显示面板的局部刷新功能，并且示出了EM信号与Gate信号的波形图，局部刷新功能的远离可以参见图18示出的实施例，在此不再赘述。并且显示面板全面板刷新与局部刷新对应的显示效果分别如图8和图9所示，局部刷新显示模式下，显示图像的部分区域不刷新。FIG. 6 is a driving timing diagram of a display panel provided by an embodiment of the present disclosure. The driving timing diagram can be used to implement a full-board refresh function of the display panel, and the driving timing diagram shows waveform diagrams of the EM signal and the Gate signal. 7 is a driving timing diagram of another display panel provided by an embodiment of the present disclosure, which can be used to implement a partial refresh function of the display panel, and shows a waveform diagram of the EM signal and the Gate signal, and a partial refresh function. For the distance, refer to the embodiment shown in FIG. 18, and details are not described herein again. Moreover, the display effects corresponding to the display panel full-board refresh and the partial refresh are respectively shown in FIG. 8 and FIG. 9, and in the partial refresh display mode, the partial area of the display image is not refreshed.

结合图7和图9所示，通过设置第一刷新控制信号，可以使得显示面板的部分行的像素电路接收数据信号，其余行的像素电路不接收数据信号，由此可以实现显示面板的局部刷新功能，并可以降低功耗。As shown in FIG. 7 and FIG. 9, by setting the first refresh control signal, the pixel circuit of the partial row of the display panel can receive the data signal, and the pixel circuits of the remaining rows do not receive the data signal, thereby realizing partial refresh of the display panel. Features and can reduce power consumption.

需要说明的是，在本公开的实施例中，所谓局部刷新是指，当显示面板显示的画面的部分区域需要改变灰度(以显示不同的图像信息)，而其余大部分都维持原灰度的时，维持原灰度的像素电路可以不接收新的数据信号，如图9所示。当某行不需要刷新时，对应于该行的第一刷新控制信号维持低电平，由此可以降低显示面板部分显示像素的刷新频率，对应地，数据信号可设置为不变化以进一步地降低驱动功耗；此种情况下，对应于不刷新行的像素电路中，像素电路接收的选择控制信号(Gate信号)为高电平(接收的复位信号也可以为高电平)，与之相关的TFT(T1/T2/T4/T7)处于关闭状态，无电流流通，且无电容充放电发生，由此可以降低功耗。It should be noted that, in the embodiment of the present disclosure, the partial refresh refers to that the partial area of the screen displayed by the display panel needs to change the gradation (to display different image information), and most of the rest maintain the original gray scale. At the time, the pixel circuit that maintains the original gradation may not receive a new data signal, as shown in FIG. When a row does not need to be refreshed, the first refresh control signal corresponding to the row is maintained at a low level, thereby reducing the refresh frequency of the display pixels of the display panel portion, and correspondingly, the data signal can be set to be unchanged to further reduce Driving power consumption; in this case, in the pixel circuit corresponding to the non-refresh row, the selection control signal (Gate signal) received by the pixel circuit is at a high level (the received reset signal may also be a high level), and is related thereto. The TFT (T1/T2/T4/T7) is turned off, no current flows, and no capacitor charge and discharge occurs, thereby reducing power consumption.

根据本公开实施例的显示面板的驱动电路，每个GOA单元都包括输入模块、反相器和第一与非电路，通过输入模块根据初始信号、第一时钟信号提供端提供的第一时钟信号和第二时钟信号提供端提供的第二时钟信号生成输入控制信号，反相器对输入控制信号进行反相以输出EM信号至本行GOA单元对应的像素电路；第一与非电路对第一扫描信号和第一刷新控制信号端提供的刷新控制信号进行与非运算以输出第二扫描信号至本行GOA单元对应的像素电路，从而可使得第一扫描信号(EM信号)和第二扫描信号(Gate信号)由单个GOA单元输出，进而可以减小显示边框，提高用户体验，并且通过控制第一刷新控制信号端提供的刷新控制信号，可以实现显示面板全面板刷新功能和局部刷新功能，由此可以降低功耗。According to the driving circuit of the display panel of the embodiment of the present disclosure, each GOA unit includes an input module, an inverter, and a first NAND circuit, and the first clock signal provided by the first clock signal providing end according to the initial signal by the input module And generating, by the second clock signal provided by the second clock signal providing end, an input control signal, the inverter inverting the input control signal to output the EM signal to the pixel circuit corresponding to the GOA unit of the row; the first NAND circuit pair first And performing a NAND operation on the scan signal and the refresh control signal provided by the first refresh control signal terminal to output the second scan signal to the pixel circuit corresponding to the GOA unit of the row, so that the first scan signal (EM signal) and the second scan signal are made (Gate signal) is output by a single GOA unit, thereby reducing the display frame and improving the user experience, and by controlling the refresh control signal provided by the first refresh control signal end, the full panel refresh function and the partial refresh function of the display panel can be realized. This can reduce power consumption.

在本公开的实施例中，显示面板可以是OLED面板。In an embodiment of the present disclosure, the display panel may be an OLED panel.

根据本公开的另一个实施例，如图10所示，当本行GOA单元为奇数行GOA单元100时，所述本行GOA单元还包括第二与非电路50，第二与非电路50的第一输入端与反相器20相连，第二与非电路50的第二输入端与第二刷新控制信号端(第二信号源ENBE)相连，第二与非电路50用于对第一扫描信号EM_n信号和第二刷新控制信号端(第二信号源ENBE)提供的第二刷新控制信号进行与非运算以输出复位信号Reset_n至本行GOA单元对应的像素电路101。而当所述本行GOA单元为偶数行GOA单元200时，所述本行GOA单元还包括第二与非电路50，第二与非电路50的第一输入端与反相器20相连，第二与非电路50的第二输入端与第二刷新控制信号端(第一信号源ENBO)相连，第二与非电路50用于对第一扫描信号EM_n+1和第二刷新控制信号端(第一信号源ENBO)提供的第二刷新控制信号进行与非运算以输出复位信号Reset_n+1至所述本行GOA单元对应的像素电路201。According to another embodiment of the present disclosure, as shown in FIG. 10, when the row GOA unit is an odd row GOA unit 100, the row GOA unit further includes a second NAND circuit 50, and the second NAND circuit 50 The first input terminal is connected to the inverter 20, the second input terminal of the second NAND circuit 50 is connected to the second refresh control signal terminal (second signal source ENBE), and the second NAND circuit 50 is used for the first scan. The signal EM_n signal and the second refresh control signal provided by the second refresh control signal terminal (second signal source ENBE) perform NAND operation to output the reset signal Reset_n to the pixel circuit 101 corresponding to the GOA unit of the row. When the GOA unit of the row is an even row GOA unit 200, the GOA unit of the row further includes a second NAND circuit 50, and the first input end of the second NAND circuit 50 is connected to the inverter 20, The second input end of the second NAND circuit 50 is connected to the second refresh control signal end (first signal source ENBO), and the second NAND circuit 50 is used for the first scan signal EM_n+1 and the second refresh control signal end ( The second refresh control signal provided by the first signal source ENBO) performs a NAND operation to output a reset signal Reset_n+1 to the pixel circuit 201 corresponding to the LOA unit of the row.

也就是说，在本实施例中，Reset信号和Gate信号以及EM信号均由单个GOA单元生成，并输出至对应的像素电路。That is to say, in the present embodiment, the Reset signal and the Gate signal and the EM signal are both generated by a single GOA unit and output to the corresponding pixel circuit.

具体地，根据本公开的一个实施例，如图11或图12所示，第二与非电路50包括第八NMOS管MN8(也即，用于第二与非电路50的第一N型晶体管的一个示例)、第九NMOS管MN9(也即，用于第二与非电路50的第二N型晶体管的一个示例)、第九PMOS管MP9(也即，用于第二与非电路50的第一P型晶体管的一个示例)和第十PMOS管MP10(也即，用于第二与非电路50的第二P型晶体管的一个示例)。Specifically, according to an embodiment of the present disclosure, as shown in FIG. 11 or FIG. 12, the second NAND circuit 50 includes an eighth NMOS transistor MN8 (that is, a first N-type transistor for the second NAND circuit 50). An example of the ninth NMOS transistor MN9 (ie, one example of a second N-type transistor for the second NAND circuit 50), the ninth PMOS transistor MP9 (ie, for the second NAND circuit 50) An example of the first P-type transistor) and the tenth PMOS transistor MP10 (that is, one example of the second P-type transistor for the second NAND circuit 50).

第八NMOS管MN8的第一端与第二电源端VSS相连，第九NMOS管MN9的第一端与第八NMOS管MN8的第二端相连，第九NMOS管MN9的控制端与第一节点361，即N点，相连；第九PMOS管MP9的第一端与第一电源端VDD相连，第九PMOS管MP9的控制端与第八NMOS管MN8的控制端相连后对应与第二刷新控制信号端(第二信号源ENBE或第一信号源ENBO)相连，第九PMOS管MP9的第二端与第九NMOS管MN9的第二端均与第四节点相连，所述第四节点作为第二与非电路50的输出端，输出复位信号；第十PMOS管MP10的第一端与第一电源端VDD相连，第十PMOS管MP10的控制端与第一节点361相连，第十PMOS管MP10的第二端与所述第四节点相连。The first end of the eighth NMOS transistor MN8 is connected to the second power supply terminal VSS, the first end of the ninth NMOS transistor MN9 is connected to the second end of the eighth NMOS transistor MN8, and the control end of the ninth NMOS transistor MN9 is connected to the first node. 361, that is, N point, connected; the first end of the ninth PMOS transistor MP9 is connected to the first power supply terminal VDD, and the control end of the ninth PMOS transistor MP9 is connected to the control end of the eighth NMOS transistor MN8, and corresponding to the second refresh control The signal terminal (the second signal source ENBE or the first signal source ENBO) is connected, and the second end of the ninth PMOS transistor MP9 and the second end of the ninth NMOS transistor MN9 are both connected to the fourth node, and the fourth node is The output end of the second NAND circuit 50 outputs a reset signal; the first end of the tenth PMOS transistor MP10 is connected to the first power terminal VDD, the control end of the tenth PMOS transistor MP10 is connected to the first node 361, and the tenth PMOS transistor MP10 The second end is connected to the fourth node.

本公开实施例还提出了一种显示装置，其包括上述的显示面板的驱动电路。在本公开实施例的显示装置中，通过上述的显示面板的驱动电路，能够使得EM信号和Gate信号由单个GOA单元输出，进而可以减小显示边框，提高用户体验；此外，通过控制刷新控制信号端提供的刷新控制信号，可以实现显示面板全面板刷新功能和局部刷新功能，以降低功耗。Embodiments of the present disclosure also provide a display device including the above-described driving circuit of the display panel. In the display device of the embodiment of the present disclosure, the EM signal and the Gate signal can be outputted by a single GOA unit through the driving circuit of the display panel described above, thereby reducing the display frame and improving the user experience; further, by controlling the refresh control signal The refresh control signal provided by the terminal can realize the full panel refresh function and the partial refresh function of the display panel to reduce power consumption.

以上所述仅是本公开的实施例的示范性实施方式，而非用于限制本公开的实施例的保护范围，本公开的实施例的保护范围由所附的权利要求确定。The above is only an exemplary embodiment of the embodiments of the present disclosure, and is not intended to limit the scope of the embodiments of the present disclosure. The scope of the embodiments of the present disclosure is determined by the appended claims.

Claims

一种扫描电路，包括：移位寄存电路和第一信号生成电路，其中，A scanning circuit comprising: a shift register circuit and a first signal generating circuit, wherein

所述移位寄存电路具有第一信号输出端且配置为输出第一扫描信号；以及The shift register circuit has a first signal output and is configured to output a first scan signal;

所述第一信号生成电路具有第二信号输出端且配置为基于第一刷新控制信号与所述第一扫描信号生成并输出第二扫描信号。The first signal generating circuit has a second signal output and is configured to generate and output a second scan signal based on the first refresh control signal and the first scan signal.
如权利要求1所述的扫描电路，还包括第一节点，其中，The scanning circuit of claim 1 further comprising a first node, wherein

所述第一信号输出端连接至所述第一节点，且配置为输出所述第一扫描信号；以及The first signal output is coupled to the first node and configured to output the first scan signal;

所述第一信号生成电路还具有第一信号输入端和第二信号输入端，其中，所述第一信号生成电路的第一信号输入端连接至所述第一节点，且配置为接收所述第一扫描信号，所述第一信号生成电路的第二信号输入端连接至第一刷新控制信号端，以接收所述第一刷新控制信号。The first signal generating circuit further has a first signal input end and a second signal input end, wherein the first signal input end of the first signal generating circuit is connected to the first node, and is configured to receive the The first scan signal, the second signal input end of the first signal generating circuit is connected to the first refresh control signal end to receive the first refresh control signal.
如权利要求2所述的扫描电路，其中，The scanning circuit according to claim 2, wherein

所述第一信号生成电路包括第一与非电路；以及The first signal generating circuit includes a first NAND circuit;

所述第一与非电路用于对所述第一扫描信号以及所述第一刷新控制信号进行与非运算以生成所述第二扫描信号。The first NAND circuit is configured to perform a NAND operation on the first scan signal and the first refresh control signal to generate the second scan signal.
如权利要求3所述的扫描电路，其中，The scanning circuit according to claim 3, wherein

所述第一与非电路包括用于所述第一与非电路的第一N型晶体管、用于所述第一与非电路的第二N型晶体管、用于所述第一与非电路的第一P型晶体管和用于所述第一与非电路的第二P型晶体管；The first NAND circuit includes a first N-type transistor for the first NAND circuit, a second N-type transistor for the first NAND circuit, and the first NAND circuit a first P-type transistor and a second P-type transistor for the first NAND circuit;

所述用于所述第一与非电路的第一N型晶体管的第一端与第二电源端相连，所述用于所述第一与非电路的第一N型晶体管的控制端与所述第一信号生成电路的第二信号输入端连接；The first end of the first N-type transistor for the first NAND circuit is connected to the second power terminal, and the control end of the first N-type transistor for the first NAND circuit is Connecting the second signal input end of the first signal generating circuit;

所述用于所述第一与非电路的第二N型晶体管的第一端与所述用于所述第一与非电路的第一N型晶体管的第二端相连，所述用于所述第一与非电路的第二N型晶体管的控制端配置为所述第一信号生成电路的第一信号输入端，且与所述第一节点相连，所述用于所述第一与非电路的第二N型晶体管的第二端连接至所述第二信号输出端；The first end of the second N-type transistor for the first NAND circuit is connected to the second end of the first N-type transistor for the first NAND circuit, the a control end of the second N-type transistor of the first NAND circuit is configured as a first signal input end of the first signal generating circuit, and is connected to the first node, where the first and the second are used a second end of the second N-type transistor of the circuit is coupled to the second signal output;

所述用于所述第一与非电路的第一P型晶体管的第一端与第一电源端相连，所述用于所述第一与非电路的第一P型晶体管的控制端与所述第一信号生成电路的第二信号输入端连接，所述用于所述第一与非电路的第一P型晶体管的第二端连接至所述第二信号输出端；以及The first end of the first P-type transistor for the first NAND circuit is connected to the first power terminal, and the control terminal of the first P-type transistor for the first NAND circuit a second signal input terminal of the first signal generating circuit is connected, and a second end of the first P-type transistor for the first NAND circuit is connected to the second signal output terminal;

所述用于所述第一与非电路的第二P型晶体管的第一端与所述第一电源端相连，所述用于所述第一与非电路的第二P型晶体管的控制端与所述第一节点相连，所述用于所述第一与非电路的第二P型晶体管的第二端与所述第二信号输出端相连。The first end of the second P-type transistor for the first NAND circuit is connected to the first power terminal, and the control end of the second P-type transistor for the first NAND circuit Connected to the first node, the second end of the second P-type transistor for the first NAND circuit is connected to the second signal output end.
如权利要求2-4任一所述的扫描电路，其中，A scanning circuit according to any one of claims 2 to 4, wherein

所述移位寄存电路还具有开启信号输入端、第一时钟信号输入端和第二时钟信号输入端，且包括输入电路和反相器和第二节点；The shift register circuit further has an open signal input terminal, a first clock signal input terminal and a second clock signal input terminal, and includes an input circuit and an inverter and a second node;

所述输入电路包括第一端、第二端、第三端和输出端，其中，The input circuit includes a first end, a second end, a third end, and an output end, wherein

所述输入电路的第一端和所述输入电路的第二端分别配置为所述第一时钟信号输入端和所述第二时钟信号输入端，且分别连接至第一时钟信号提供端和第二时钟信号提供端，以分别接收第一时钟信号和所述第二时钟信号，The first end of the input circuit and the second end of the input circuit are respectively configured as the first clock signal input end and the second clock signal input end, and are respectively connected to the first clock signal providing end and the first a second clock signal providing end for receiving the first clock signal and the second clock signal, respectively

所述输入电路的第三端配置为所述移位寄存电路的开启信号输入端以接收开启信号，The third end of the input circuit is configured as an open signal input end of the shift register circuit to receive an open signal,

所述输入电路用于根据所述开启信号、所述第一时钟信号和所述第二时钟信号生成输入控制信号，The input circuit is configured to generate an input control signal according to the turn-on signal, the first clock signal, and the second clock signal,

所述输入电路的输出端连接至所述第二节点，且配置为输出所述输入控制信号；An output of the input circuit is coupled to the second node and configured to output the input control signal;

所述反相器包括输入端和输出端，其中The inverter includes an input end and an output end, wherein

所述反相器的输入端连接至所述第二节点，以接收所述输入控制信号，An input of the inverter is coupled to the second node to receive the input control signal,

所述反相器用于对所述输入控制信号的电平进行反相以生成所述第一扫描信号；The inverter is configured to invert a level of the input control signal to generate the first scan signal;

所述反相器的输出端连接至所述第一节点，且配置为所述第一信号输出端，以用于输出所述第一扫描信号。An output of the inverter is coupled to the first node and configured as the first signal output for outputting the first scan signal.
如权利要求5所述的扫描电路，其中，The scanning circuit according to claim 5, wherein

所述输入电路包括用于所述移位寄存电路的第一N型晶体管、用于所述移位寄存电路的第二N型晶体管、用于所述移位寄存电路的第一P型晶体管、用于所述移位寄存电路的第二P型晶体管、用于所述移位寄存电路的第三N型晶体管、用于所述移位寄存电路的第四N型晶体管、用于所述移位寄存电路的第三P型晶体管和用于所述移位寄存电路的第四P型晶体管，其中，The input circuit includes a first N-type transistor for the shift register circuit, a second N-type transistor for the shift register circuit, a first P-type transistor for the shift register circuit, a second P-type transistor for the shift register circuit, a third N-type transistor for the shift register circuit, a fourth N-type transistor for the shift register circuit, for the shift a third P-type transistor of the bit register circuit and a fourth P-type transistor for the shift register circuit, wherein

所述用于所述移位寄存电路的第一N型晶体管的第一端与第二电源端相连，所述用于所述移位寄存电路的第一N型晶体管的控制端与所述第二时钟信号提供端相连；The first end of the first N-type transistor for the shift register circuit is connected to a second power supply terminal, and the control terminal of the first N-type transistor for the shift register circuit and the first Two clock signal supply ends are connected;

所述用于所述移位寄存电路的第二N型晶体管的第一端与所述用于所述移位寄存电路的第一N型晶体管的第二端相连，所述用于所述移位寄存电路的第二N型晶体管的控制端与所述移位寄存电路的开启信号输入端相连，所述用于所述移位寄存电路的第二N型晶体管的第二端与所述第二节点相连；The first end of the second N-type transistor for the shift register circuit is coupled to the second end of the first N-type transistor for the shift register circuit, the a control end of the second N-type transistor of the bit register circuit is coupled to an enable signal input terminal of the shift register circuit, the second end of the second N-type transistor for the shift register circuit and the first Two nodes connected;

所述用于所述移位寄存电路的第一P型晶体管的第一端与第一电源端相连，所述用于所述移位寄存电路的第一P型晶体管的控制端与所述第一时钟信号提供端相连；The first end of the first P-type transistor for the shift register circuit is connected to the first power supply terminal, and the control terminal of the first P-type transistor for the shift register circuit and the first a clock signal providing end connected;

所述用于所述移位寄存电路的第二P型晶体管的第一端与所述用于所述移位寄存电路的第一P型晶体管的第二端相连，所述用于所述移位寄存电路的第二P型晶体管的控制端与所述移位寄存电路的开启信号输入端相连，所述用于所述移位寄存电路的第二P型晶体管的第二端与所述第二节点相连；The first end of the second P-type transistor for the shift register circuit is coupled to the second end of the first P-type transistor for the shift register circuit, the a control terminal of the second P-type transistor of the bit register circuit is coupled to an enable signal input terminal of the shift register circuit, the second terminal of the second P-type transistor for the shift register circuit and the first Two nodes connected;

所述用于所述移位寄存电路的第三N型晶体管的第一端与所述第二电源端相连，所述用于所述移位寄存电路的第三N型晶体管的控制端与所述第一时钟信号提供端相连；The first end of the third N-type transistor for the shift register circuit is connected to the second power terminal, and the control terminal of the third N-type transistor for the shift register circuit The first clock signal providing end is connected;

所述用于所述移位寄存电路的第四N型晶体管的第一端与所述用于所述移位寄存电路的第三N型晶体管的第二端相连，所述用于所述移位寄存电路的第四N型晶体管的控制端与所述第一节点相连，所述用于所述移位寄存电路的第四N型晶体管的第二端与所述第二节点相连；The first end of the fourth N-type transistor for the shift register circuit is coupled to the second end of the third N-type transistor for the shift register circuit, the a control end of the fourth N-type transistor of the bit register circuit is connected to the first node, and a second end of the fourth N-type transistor for the shift register circuit is connected to the second node;

所述用于所述移位寄存电路的第三P型晶体管的第二端与所述第二节点相连，所述用于所述移位寄存电路的第三P型晶体管的控制端与所述第一节点相连；以及The second end of the third P-type transistor for the shift register circuit is connected to the second node, and the control terminal of the third P-type transistor for the shift register circuit is The first node is connected;

所述用于所述移位寄存电路的第四P型晶体管的第一端与所述第一电源端相连，所述用于所述移位寄存电路的第四P型晶体管的控制端与所述第二时钟信号提供端相连，所述用于所述移位寄存电路的第四P型晶体管的第二端与所述用于所述移位寄存电路的第三P型晶体管的第一端相连；The first end of the fourth P-type transistor for the shift register circuit is connected to the first power terminal, and the control terminal of the fourth P-type transistor for the shift register circuit a second clock signal supply terminal connected to the second end of the fourth P-type transistor for the shift register circuit and the first end of the third P-type transistor for the shift register circuit Connected

所述反相器包括用于所述移位寄存电路的第五N型晶体管和用于所述移位寄存电路的第五P型晶体管；The inverter includes a fifth N-type transistor for the shift register circuit and a fifth P-type transistor for the shift register circuit;

所述用于所述移位寄存电路的第五N型晶体管的第一端与所述第二电源端相连，所述用于所述移位寄存电路的第五N型晶体管的控制端与所述第二节点相连，所述用于所述移位寄存电路的第五N型晶体管的第二端与所述第一节点相连；The first end of the fifth N-type transistor for the shift register circuit is connected to the second power terminal, and the control terminal of the fifth N-type transistor for the shift register circuit Connected to the second node, the second end of the fifth N-type transistor for the shift register circuit is connected to the first node;

所述用于所述移位寄存电路的第五P型晶体管的第一端与所述第一电源端相连，所述用于所述移位寄存电路的第五P型晶体管的控制端与所述第二节点相连，所述用于所述移位寄存电路的第五P型晶体管的第二端与所述第一节点相连。The first end of the fifth P-type transistor for the shift register circuit is connected to the first power terminal, and the control terminal of the fifth P-type transistor for the shift register circuit The second node is connected, and the second end of the fifth P-type transistor for the shift register circuit is connected to the first node.
如权利要求5或6所述的扫描电路，还包括复位电路，其中，A scanning circuit according to claim 5 or 6, further comprising a reset circuit, wherein

所述复位电路连接至所述第二节点，且用于对所述第一节点进行初始化复位；以及The reset circuit is coupled to the second node and configured to perform an initial reset on the first node;

所述复位电路包括用于所述复位电路的P型晶体管，所述用于所述复位电路的P型晶体管的第一端与第一电源端相连，所述用于所述复位电路的P型晶体管的控制端用于接收初始化复位信号，所述用于所述复位电路的P型晶体管的第二端与所述第二节点相连。The reset circuit includes a P-type transistor for the reset circuit, the first end of the P-type transistor for the reset circuit is connected to a first power supply terminal, and the P-type for the reset circuit The control terminal of the transistor is configured to receive an initialization reset signal, and the second end of the P-type transistor for the reset circuit is coupled to the second node.
如权利要求2-7任一所述的扫描电路，还包括第二信号生成电路，其中，A scanning circuit according to any one of claims 2-7, further comprising a second signal generating circuit, wherein

所述第二信号生成电路具有第一信号输入端、第二信号输入端和第三信号输出端，其中，The second signal generating circuit has a first signal input end, a second signal input end, and a third signal output end, wherein

所述第二信号生成电路的第一信号输入端连接至所述第一节点，且配置为接收所述第一扫描信号，a first signal input end of the second signal generating circuit is coupled to the first node, and configured to receive the first scan signal,

所述第二信号生成电路的第二信号输入端连接至第二刷新控制信号端，以接收所述第二刷新控制信号端提供的第二刷新控制信号，The second signal input end of the second signal generating circuit is connected to the second refresh control signal end to receive the second refresh control signal provided by the second refresh control signal end,

所述第二信号生成电路配置为基于所述第一扫描信号和所述第二刷新控制信号生成第三扫描信号；以及The second signal generating circuit is configured to generate a third scan signal based on the first scan signal and the second refresh control signal;

所述第二信号生成电路包括第二与非电路，所述第二与非电路包括第一输入端、第二输入端和信号输出端，其分别配置为所述第二信号生成电路的第一信号输入端、第二信号输入端和第三信号输出端，所述第二与非电路用于对所述第一扫描信号以及所述第二刷新控制信号进行与非运算以生成所述第三扫描信号。The second signal generating circuit includes a second NAND circuit, and the second NAND circuit includes a first input end, a second input end, and a signal output end, which are respectively configured as the first of the second signal generating circuit a signal input end, a second signal input end, and a third signal output end, wherein the second NAND circuit is configured to perform NAND operation on the first scan signal and the second refresh control signal to generate the third Scan the signal.
如权利要求8所述的扫描电路，其中，The scanning circuit according to claim 8, wherein

所述第二与非电路包括用于所述第二与非电路的第一N型晶体管、用于所述第二与非电路的第二N型晶体管、用于所述第二与非电路的第一P型晶体管和用于所述第二与非电路的第二P型晶体管；The second NAND circuit includes a first N-type transistor for the second NAND circuit, a second N-type transistor for the second NAND circuit, and the second NAND circuit a first P-type transistor and a second P-type transistor for the second NAND circuit;

所述用于所述第二与非电路的第一N型晶体管的第一端与所述第二电源端相连，所述用于所述第二与非电路的第一N型晶体管的控制端与所述第二信号生成电路的第二信号输入端相连；The first end of the first N-type transistor for the second NAND circuit is connected to the second power terminal, and the control end of the first N-type transistor for the second NAND circuit Connected to the second signal input end of the second signal generating circuit;

所述用于所述第二与非电路的第二N型晶体管的第一端与所述用于所述第二与非电路的第一N型晶体管的第二端相连，所述用于所述第二与非电路的第二N型晶体管的控制端与所述第一节点相连，所述用于所述第二与非电路的第二N型晶体管的第二端与所述第三信号输出端相连；The first end of the second N-type transistor for the second NAND circuit is connected to the second end of the first N-type transistor for the second NAND circuit, the a control end of the second N-type transistor of the second NAND circuit is connected to the first node, the second end of the second N-type transistor for the second NAND circuit and the third signal The output is connected;

所述用于所述第二与非电路的第一P型晶体管的第一端与所述第一电源端相连，所述用于所述第二与非电路的第一P型晶体管的控制端与所述第二信号生成电路的第二信号输入端相连，所述用于所述第二与非电路的第一P型晶体管的第二端与所述第三信号输出端相连；以及The first end of the first P-type transistor for the second NAND circuit is connected to the first power terminal, and the control end of the first P-type transistor for the second NAND circuit Connected to a second signal input terminal of the second signal generating circuit, the second end of the first P-type transistor for the second NAND circuit is connected to the third signal output terminal;

所述用于所述第二与非电路的第二P型晶体管的第一端与所述第一电源端相连，所述用于所述第二与非电路的第二P型晶体管的控制端与所述第一节点相连，所述用于所述第二与非电路的第二P型晶体管的第二端与所述第三信号输出端相连。The first end of the second P-type transistor for the second NAND circuit is connected to the first power terminal, and the control terminal of the second P-type transistor for the second NAND circuit Connected to the first node, the second end of the second P-type transistor for the second NAND circuit is connected to the third signal output end.
一种栅极驱动电路，包括：N个级联的如权利要求1所述扫描电路，其中，A gate driving circuit comprising: N cascaded scanning circuits according to claim 1, wherein

每级所述扫描电路的移位寄存电路具有第一信号输出端和开启信号输入端；以及a shift register circuit of each of the scanning circuits has a first signal output end and an open signal input end;

第m级所述扫描电路的移位寄存电路的开启信号输入端连接至第m-1级所述扫描电路的第一信号输出端，其中，N为大于等于1的整数，m为大于1且小于等于N的整数。The open signal input end of the shift register circuit of the mth stage is connected to the first signal output end of the scanning circuit of the m-1th stage, wherein N is an integer greater than or equal to 1, and m is greater than 1 and An integer less than or equal to N.
如权利要求10所述的栅极驱动电路，其中，The gate driving circuit according to claim 10, wherein

第2k-1级所述扫描电路的第一信号生成电路连接的第一刷新控制信号端为第一信号源；以及a first refresh control signal end connected to the first signal generating circuit of the scanning circuit of the 2k-1th stage is a first signal source;

第2k级所述扫描电路的第一信号生成电路连接的所述第一刷新控制信号端为第二信号源，其中，k为大于等于1且小于等于N/2的整数。The first refresh control signal end connected to the first signal generating circuit of the scanning circuit of the 2kth stage is a second signal source, where k is an integer greater than or equal to 1 and less than or equal to N/2.
如权利要求11所述的栅极驱动电路，其中，The gate driving circuit according to claim 11, wherein

每级所述扫描电路还包括第二信号生成电路；以及Each stage of the scanning circuit further includes a second signal generating circuit;

所述第2k-1级扫描电路的第二信号生成电路连接的第二刷新控制信号端为所述第二信号源，所述第2k级扫描电路的第二信号生成电路连接的所述第二刷新控制信号端为所述第一信号源。a second refresh control signal end connected to the second signal generating circuit of the 2k-1th stage scanning circuit is the second signal source, and the second signal generating circuit of the 2kth stage scanning circuit is connected to the second The refresh control signal end is the first signal source.
一种显示面板，包括像素电路阵列以及如权利要求10所述的栅极驱动电路，其中，A display panel comprising a pixel circuit array and the gate driving circuit according to claim 10, wherein

所述像素电路阵列包括阵列排布的多个像素电路，所述多个像素电路在列方向上排布成N行，每个所述像素电路包括发光控制端和选择控制端；以及The pixel circuit array includes a plurality of pixel circuits arranged in an array, the plurality of pixel circuits being arranged in N rows in a column direction, each of the pixel circuits including a light emission control end and a selection control end;

第j级所述扫描电路的第一信号输出端连接至第j行的所述像素电路的发光控制端，所述第j级扫描电路的第二信号输出端连接至所述第j行像素电路的选择控制端，其中，j为大于等于1且小于等于N的整数。a first signal output end of the scanning circuit of the jth stage is connected to an emission control end of the pixel circuit of the jth row, and a second signal output end of the jth stage scanning circuit is connected to the pixel circuit of the jth row The selection control terminal, wherein j is an integer greater than or equal to 1 and less than or equal to N.
如权利要求13所述的显示面板，其中，The display panel according to claim 13, wherein

每个所述像素电路还包括复位控制端；以及Each of the pixel circuits further includes a reset control terminal;

第m-1级所述扫描电路的第二信号输出端连接至第m行的所述像素电路的复位控制端。The second signal output of the scanning circuit of the m-1th stage is connected to the reset control terminal of the pixel circuit of the mth row.
如权利要求13所述的显示面板，其中，The display panel according to claim 13, wherein

每个所述像素电路还包括复位控制端；Each of the pixel circuits further includes a reset control terminal;

每级所述扫描电路还包括第二信号生成电路，所述第二信号生成电路包括第三信号输出端；以及Each stage of the scanning circuit further includes a second signal generating circuit, the second signal generating circuit including a third signal output;

所述第j级扫描电路的第三信号输出端连接至所述第j行像素电路的复位控制端。The third signal output terminal of the jth stage scanning circuit is connected to the reset control terminal of the pixel circuit of the jth row.
一种显示装置，包括如权利要求1-9中任一项所述的扫描电路、如权利要求10-12中任一项所述的栅极驱动电路或如权利要求13-15任一所述的显示面板。A display device comprising the scanning circuit according to any one of claims 1 to 9, the gate driving circuit according to any one of claims 10 to 12, or the method of any one of claims 13-15 Display panel.
一种如权利要求13所述的显示面板的驱动方法，包括：A method of driving a display panel according to claim 13, comprising:

使得所述第j级的扫描电路的移位寄存电路生成所述第一扫描信号，并将所述第一扫描信号提供给所述第j级的扫描电路的第一信号生成电路的第一信号输入端以及所述第j行的像素电路的发光控制端；以及And causing a shift register circuit of the scanning circuit of the jth stage to generate the first scan signal, and supplying the first scan signal to a first signal of a first signal generating circuit of the scanning circuit of the jth stage An input end and an illumination control end of the pixel circuit of the jth row;

使得所述第j级的扫描电路的第一信号生成电路基于所述第一扫描信号和第一刷新控制信号生成所述第二扫描信号，并将所述第二扫描信号提供给所述第j行的像素电路的选择控制端。And causing the first signal generating circuit of the scanning circuit of the jth stage to generate the second scan signal based on the first scan signal and the first refresh control signal, and provide the second scan signal to the jth The selection control terminal of the pixel circuit of the row.
如权利要求17所述的驱动方法，其中，The driving method according to claim 17, wherein

每个所述像素电路还包括复位控制端；Each of the pixel circuits further includes a reset control terminal;

所述驱动方法还包括：The driving method further includes:

将所述第m-1级的扫描电路的第一信号生成电路生成的所述第二扫描信号提供给所述第m行的像素电路的复位控制端；或者Supplying the second scan signal generated by the first signal generating circuit of the m-1th scanning circuit to the reset control terminal of the pixel circuit of the mth row; or

将所述第j级的扫描电路的第二信号生成电路生成的第三扫描信号提供给所述第j行的像素电路的复位控制端。And supplying a third scan signal generated by the second signal generating circuit of the scanning circuit of the jth stage to a reset control terminal of the pixel circuit of the jth row.
如权利要求17或18所述的驱动方法，其中，The driving method according to claim 17 or 18, wherein

所述显示面板的显示周期包括刷新阶段和非刷新阶段；以及The display period of the display panel includes a refresh phase and a non-refresh phase;

所述驱动方法包括：在所述非刷新阶段，使得所述第一信号生成电路的第二信号输入端接收低电平的刷新控制信号。The driving method includes, in the non-refresh phase, causing a second signal input terminal of the first signal generating circuit to receive a refresh control signal of a low level.
如权利要求19所述的驱动方法，其中，The driving method according to claim 19, wherein

所述移位寄存电路响应于时钟信号生成所述第一扫描信号；The shift register circuit generates the first scan signal in response to a clock signal;

所述驱动方法包括：The driving method includes:

在所述刷新阶段，向所述移位寄存电路提供具有第一脉冲宽度的时钟信号；Providing, in the refreshing phase, a clock signal having a first pulse width to the shift register circuit;

在所述非刷新阶段，向所述移位寄存电路提供具有第二脉冲宽度的时钟信号；以及Providing, in the non-refresh phase, a clock signal having a second pulse width to the shift register circuit;

所述第一脉冲宽度大于所述第二脉冲宽度。The first pulse width is greater than the second pulse width.