CN204102543U - Shift register cell and use its gate driver circuit and display device - Google Patents
Shift register cell and use its gate driver circuit and display device Download PDFInfo
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- CN204102543U CN204102543U CN201420661459.1U CN201420661459U CN204102543U CN 204102543 U CN204102543 U CN 204102543U CN 201420661459 U CN201420661459 U CN 201420661459U CN 204102543 U CN204102543 U CN 204102543U
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Abstract
This application provides a kind of shift register cell and use its gate driver circuit and display device.This shift register cell comprises load module, Sheffer stroke gate module, inverter modules, pull-up module and drop-down module.This load module receives input signal and the first clock signal, and input signal is delivered to the first input end of described Sheffer stroke gate module and described drop-down module under the control of the first clock signal.Second input end of described Sheffer stroke gate module receives the input of second clock signal, and its output terminal connects described inverter modules.The output terminal of described inverter modules connects described pull-up module.Output signal pull-up is high level according to the output of described inverter modules by described pull-up module.It is low level that described drop-down module will output signal drop-down under the control of the input signal received and second clock signal.By arranging described inverter modules, can ensure that output transistor gates place does not exist suspension point, making it not affect by leak source, thus maintain stable signal output, promote the stable output ability of shift register.
Description
Technical field
The utility model relates to display technique field, particularly relates to a kind of shift register cell and uses gate driver circuit and the display device of this shift register cell.
Background technology
As the technology relevant to the driving circuit of existing liquid crystal indicator, GOA(Gate-driver on Array has been developed in this area) technology, namely by photoetching process, gate driver circuit is directly integrated on the array of display substrate of liquid crystal indicator.GOA circuit generally includes the shift register cell of multiple cascade, each shift register cell is connected with the shift register cell of adjacent lines respectively, the equal corresponding a line grid line of each shift register cell, output signal can be supplied to next shift register cell by each shift register cell while output gate drive signal, to ensure that next shift register cell realizes the output of gate drive signal within the next clock period.
But in the shift register cell adopted in current most of GOA structure, under certain clock signal, the Controlling vertex place of output transistor can be in suspended state always, the current potential of this Nodes can be subject to surrounding transistor effect of leakage, cause output transistor gates controlling potential to change, thus affect the stable output of shift register.
Fig. 1 illustrates the electrical block diagram of a kind of 8T1C shift register cell of the prior art, and Fig. 2 illustrates the signal sequence oscillogram of the shift register cell of 8T1C shown in Fig. 1.As shown in the figure, described shift register cell comprises two clock input CLK1 and CLK2, and two clock signals of their inputs have the identical cycle, but phase place is contrary.In addition, described shift register cell also comprises an an input end STV and output terminal OUT, and described output terminal exports the input signal through displacement.In actual use, the gate driver circuit of liquid crystal indicator comprises the shift register of multiple cascade, the input end received frame scanning of first shift register starts pulse signal STV, and the input end of each follow-up shift register receives the output signal of previous shift register.Like this, each shift register exports a STV signal be shifted through different number of times accordingly, i.e. Out_put1, Out_put2 ...Wherein, the beginning of a described STV signal designation frame, after the multiple shift registers being transfused to cascade, each in multiple shift register exports a STV signal be shifted through different number of times accordingly, can as the grid horizontal-drive signal of the corresponding row of array of display substrate of liquid crystal indicator, for driving the display of the corresponding row pixel of the array of display substrate of this liquid crystal indicator.
Defect as above is just there is in shift register cell shown in Fig. 1, namely, under certain clock signal, the Controlling vertex place of output transistor can be in suspended state always, the current potential of this Nodes can be subject to surrounding transistor effect of leakage, cause output transistor gates controlling potential to change, affect the stable output of shift register.
Specifically, in the shift register cell circuit structure shown in Fig. 1, transistor M19 is output transistor, and its Controlling vertex is the node A at its grid place.Node A CLK2 second and third, four clock signals time will be in suspended state always, thus occur a unstable signal, as shown in Fig. 2 the 4th row oscillogram.The reason producing this situation is, at second of second clock signal CLK2, three, before four clock signals, node C keeps a relatively high signal, and node A keeps a relatively low signal, as second of CLK2, three, when there is low level signal in four clock signals, when transistor M20 opens by this low level signal, thus make node A and node C conducting, and now these two nodes all provide voltage without outside direct signal source, therefore now can there is unstable signal in node A and node C, the node A of electronegative potential should be kept to be driven high, the output of output transistor M19 will be caused like this to be deteriorated, affect the output signal Out of shift register.
Therefore, there is a need in the art for a kind of shift register cell of improvement, to overcome the defect existed in above-mentioned prior art shift register cell.
Utility model content
An object of the present utility model is to provide a kind of novel shift register cell, and it can overcome above-mentioned defect and/or other defect of prior art shift register cell.
According to an aspect of the present utility model, provide a kind of shift register cell, this shift register cell comprises load module, Sheffer stroke gate module, inverter modules, pull-up module and drop-down module.Described load module connects input end and first clock signal input terminal of shift register cell, for receiving input signal and the first clock signal.Described load module is also connected to the first input end of described Sheffer stroke gate module and described drop-down module, for input signal being delivered to the first input end of described Sheffer stroke gate module and described drop-down module under the control of the first clock signal.Second input end of described Sheffer stroke gate module connects second clock signal input part for receiving the input of second clock signal, and the output terminal of described Sheffer stroke gate module connects described inverter modules.The output terminal of described inverter modules connects described pull-up module.Described pull-up module also connects the output terminal of shift register cell, for being high level according to the output of described inverter modules by the signal pull-up that the output terminal of described shift register cell exports.Described drop-down module also connects the output terminal of second clock signal input part and shift register cell, and the signal for being exported by the output terminal of described shift register cell under the control of the input signal received and second clock signal is drop-down is low level.
In one embodiment, described load module comprises: the first transistor, its first pole is connected to the input end of shift register cell to receive input signal, its grid is connected to described first clock signal input terminal, and its second pole is connected to the first input end of described drop-down module and described Sheffer stroke gate module.
In one embodiment, described Sheffer stroke gate module also connects high level signal input end and low level signal input end.
In one embodiment, described Sheffer stroke gate module comprises transistor seconds, third transistor, the 4th transistor.First pole of transistor seconds connects described high level signal input end, and the second pole of transistor seconds and grid are interconnected and are connected to the first pole of third transistor and the output terminal of described Sheffer stroke gate module.The grid of third transistor is connected to described second clock signal input part, and the second pole of third transistor connects the first pole of the 4th transistor.The grid of the 4th transistor connects described load module, and the second pole of the 4th transistor connects described low level signal input end.
In one embodiment, wherein said inverter modules also connects high level signal input end and low level signal input end.
In one embodiment, described inverter modules comprises the 5th transistor and the 6th transistor.First pole of the 5th transistor connects described high level signal input end, and the grid of the 5th transistor connects the output terminal of described Sheffer stroke gate module, and the second pole of the 5th transistor connects the first pole of the 6th crystal and described pull-up module.Grid and second pole of the 6th transistor link together, and connect described low level signal input end.
In one embodiment, described pull-up module also connects high level signal input end.
In one embodiment, described pull-up module comprises: the 7th transistor, and its first pole connects described high level signal input end, and its grid connects the output terminal of described inverter modules, and its second pole connects the output terminal of described drop-down module and shift register cell.
In one embodiment, described drop-down module comprises: the 8th transistor, and its first pole connects the output terminal of shift register cell, and its grid connects described load module, and its second pole connects second clock signal input part; Capacitor, between its first pole being connected to the 8th transistor and grid.
In one embodiment, the transistor in described shift register cell all adopts P-type crystal pipe.
In one embodiment, described input signal is a burst enable signal
In one embodiment, described first clock signal and described second clock signal inversion signal each other.
According to another aspect of the present utility model, provide a kind of gate driver circuit, shown gate driver circuit comprises multiple any one shift register cell as above.The mutual cascade of described multiple shift register cell, except afterbody shift register cell, the output terminal of all the other each shift register cells all connects the input end of the next stage shift register cell be adjacent, wherein the output terminal of each shift register cell is all for exporting write control signal, for controlling the write of one-row pixels.
In one embodiment, the signal input part incoming frame start signal of described first order shift register cell.
According to another aspect of the present utility model, provide a kind of display device, it comprises any one gate driver circuit as above.
Embodiments more of the present utility model propose a kind of novel shift register, at the output terminal of this shift register cell, in order to control the transistor gate of stable state output terminal, an inverter structure is set, to ensure that output transistor gates place does not exist suspension point, make it not affect by leak source, thus maintain stable signal output, promote the stable output ability of shift register.
In addition, embodiment more of the present utility model adopts simple two clock signals to drive, essence simplifying transistor and electric capacity quantity, by arranging inverter structure at output transistor gates place, the current potential of this node can be kept to stablize, guarantee the stable output of output transistor, improve transistor tracking-resistant ability.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme of embodiments more described herein, these embodiments are described below with reference to accompanying drawings.Apparently, the accompanying drawing in the following describes relates to embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the electrical block diagram of a kind of 8T1C shift register cell in prior art;
Fig. 2 is the signal sequence oscillogram of the shift register cell of 8T1C shown in Fig. 1;
Fig. 3 is the structural representation of a kind of shift register cell according to the utility model embodiment;
Fig. 4 is the electrical block diagram of a kind of 8T1C shift register cell according to the utility model embodiment;
Fig. 5 is the signal sequence oscillogram of the shift register cell of 8T1C shown in Fig. 4;
Fig. 6 is the structural representation of a kind of gate driver circuit according to the utility model embodiment.
Embodiment
For making the object of embodiments more described herein, technical scheme and advantage clearly, be clearly and completely described below in conjunction with the technical scheme of accompanying drawing to these embodiments.It is pointed out that the following specific descriptions to embodiment are only for illustration of the utility model, instead of be not used for limiting protection domain of the present utility model.Embodiment described herein is only a part of embodiment of the present utility model, instead of whole embodiments.Based on these embodiments described herein, those of ordinary skill in the art can obtain other different embodiments, and all these embodiments are all within protection domain of the present utility model.
The transistor adopted in embodiment described herein can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics, because the source electrode of the transistor that adopts here, drain electrode are symmetrical, so its source electrode, drain electrode are as broad as long.In this application, in order to distinguish transistor the two poles of the earth except grid, sometimes a pole being wherein called the first pole, another pole is called the second pole.In addition, distinguish transistor can be divided into N-type and P-type crystal pipe according to the characteristic of transistor, following examples are all described for P-type crystal pipe, when adopting P-type crystal pipe, first can be extremely the source electrode of this P-type crystal pipe, and the second pole can be then the drain electrode of this P-type crystal pipe.Based on herein to description and the instruction of P-type crystal pipe implementation; those of ordinary skill in the art easily can expect the implementation of the utility model embodiment employing N-type transistor under creative work prerequisite not making, therefore these implementations are also in protection domain of the present utility model.
Fig. 3 illustrates the structural representation of a kind of shift register cell according to the utility model embodiment.As shown in the figure, shift register cell 300 can comprise load module 310, Sheffer stroke gate module 330, inverter modules 350, pull-up module 370 and drop-down module 390.
Described load module 310 can connect input end Input and the first clock signal input terminal CLK1 of shift register cell 300, for receiving input signal and the first clock signal.Described load module 310 can also be connected to the first input end of described Sheffer stroke gate module 330 and described drop-down module 390, for input signal being delivered to the first input end of described Sheffer stroke gate module 330 and described drop-down module 390 under the control of the first clock signal.In one embodiment, described input signal is an enabling signal.
Second input end of described Sheffer stroke gate module 330 connects second clock signal input part CLK2 for receiving the input of second clock signal, and the output terminal of described Sheffer stroke gate module 330 connects described inverter modules 350.In one embodiment, described Sheffer stroke gate module 330 also connects high level signal input end and low level signal input end, is high level voltage end VGH and low level voltage end VGL in the example of fig. 3.
The output terminal of described inverter modules 350 connects described pull-up module 370.In one embodiment, described inverter modules 350 also connects high level signal input end and low level signal input end, is high level voltage end VGH and low level voltage end VGL in the example of fig. 3.
Described pull-up module 370 also connects the output terminal of shift register cell 300, is high level for the signal pull-up exported by the output terminal of described shift register cell 300 according to the output of described inverter modules 350.In one embodiment, described pull-up module 370 also connects high level signal input end, is high level voltage end VGH in the example of fig. 3.In one embodiment, high level voltage signal VGH is outputted to the output terminal of described shift register cell 300 by described pull-up module 370 according to the output of described inverter modules 350.
Described drop-down module 390 also connects the output terminal of second clock signal input part CLK2 and shift register cell 300, for the input signal being received from load module 310 and the signal that under being received from the control of the second clock signal of second clock signal input part CLK2, the output terminal of described shift register cell exported drop-down for low level.In one embodiment, described drop-down module 390 receives described input signal and second clock signal, under the control of a signal wherein, the low level signal of another signal is outputted to the output terminal of described shift register cell 300.
In one embodiment, the clock signal that the first clock signal input terminal CLK1 and second clock signal input part CLK2 inputs is square-like clock signal and has identical cycle and dutycycle, but the phase place of these two clock signals is contrary.That is, when CLK1 input high level, CLK2 input low level, and when CLK1 input low level, CLK2 input high level.
In one embodiment, the input end of described shift register cell 300 receives the enabling signal as pulse signal form, and the output terminal of shift register cell 300 exports the pulse signal through displacement.
Fig. 4 illustrates the electrical block diagram of a kind of 8T1C shift register cell according to the utility model embodiment.In fact, Fig. 4 illustrates the circuit structure more specifically of a specific implementation of shift register cell 300 shown in Fig. 3.
As shown in Figure 4, load module 310 can comprise the first transistor M3.First pole of the first transistor M3 is connected to the input end of shift register cell 300 to receive input signal (enabling signal of such as enabling signal or impulse form), its grid is connected to described first clock signal input terminal CLK1, and its second pole is connected to the first input end of described drop-down module 390 and described Sheffer stroke gate module 330.
As shown in the figure, described Sheffer stroke gate module 330 can comprise transistor seconds M2, third transistor M7, the 4th transistor M1.First pole of transistor seconds M2 connects high level voltage end VGH, and second pole of transistor seconds M2 and grid are interconnected and are connected to the first pole and the described inverter modules 350 of third transistor M7.The grid of third transistor M7 is connected to first pole of second pole connection the 4th transistor M1 of described second clock signal input part CLK2, third transistor M7.The grid of the 4th transistor M1 connects described load module 310, namely connects second pole of the first transistor M3 in described load module 310.Second pole of the 4th transistor M1 connects low level voltage end VGL.
As shown in the figure, inverter modules 350 comprises the 5th transistor M5 and the 6th transistor M6.First pole of the 5th transistor M5 connects described high level voltage end, and the grid of the 5th transistor M5 connects the output terminal of described Sheffer stroke gate module 330, and second pole of the 5th transistor M5 connects first pole of the 6th transistor M6 and described pull-up module 370.Grid and second pole of the 6th transistor M6 link together, and connect described low level voltage end VGL.
As shown in the figure, pull-up module 370 comprises the 7th transistor M4.First pole of the 7th transistor M4 connects described high level voltage end VGH, and its grid connects the output terminal of described inverter modules 350, and its second pole connects the output terminal of described drop-down module 390 and shift register cell 300.
As shown in the figure, drop-down module 390 comprises the 8th transistor M9 and capacitor C1.First pole of the 8th transistor M9 connects the output terminal of shift register cell 300, and its grid connects described load module 310, and its second pole connects second clock signal input part CLK2.Between the first pole that capacitor C1 is connected to the 8th transistor M9 and grid.
All be described for P-type crystal pipe in circuit structure shown in Fig. 4, in the above description, use the first pole and second extremely to refer to source electrode and the drain electrode of this P-type crystal pipe respectively.It is to be noted in addition; although be all described for P-type crystal pipe in circuit structure shown in Fig. 4; but those of ordinary skill in the art are based on herein to description and the instruction of P-type crystal pipe implementation; in the implementation not needing also can easily expect under the prerequisite paying creative work adopting N-type transistor, all these implementations are all encompassed in protection domain of the present utility model.
Fig. 5 illustrates the signal sequence oscillogram of the shift register cell of 8T1C shown in Fig. 4.The principle of work of the 8T1C shift register cell according to the utility model embodiment is described below in conjunction with this oscillogram.
Those of ordinary skill in the art know, above-mentioned shift register cell can be used in the gate drivers of liquid crystal display.A work period of this gate drivers is exactly a frame period, and the type of drive of each work period is identical.The oscillogram in two frame periods has been shown in Fig. 4, can have found out, the oscillogram in two frame periods is on all four.
And each frame period can be described by following 4 sequential sections:
The a stage:
As shown in the figure, a stage is the first half of the one-period of the first clock signal clk 1 within a frame period.As shown in the figure, be low level at a stage STV and CLK1 signal, because the shift register cell shown in Fig. 4 all adopts P-type crystal pipe, therefore low level signal is start signal, and transistor M3 is opened.Like this, STV signal is just output to the grid of transistor M9 by transistor M3, and transistor M9 is opened, thus high level (shutoff) signal of CLK2 is outputted to the output terminal Out_Put of shift register cell by transistor M9.STV signal is also output to the grid of transistor M1 by transistor M3 simultaneously, so just makes transistor M1 open.But now because CLK2 is the cut-off signals of high level, transistor M7 is in closed condition, so the VGL signal transmitted by transistor M1 is not exported by transistor M7.By transistor M1, in the Sheffer stroke gate structure that M2, M7 are formed, because CLK2 is high level shutdown signal, so this Sheffer stroke gate structure output VGH signal is to the grid of transistor M5, transistor M5 is made to be in closed condition, like this in the inverter structure be made up of transistor M5, M6, will by transistor M6 output low level signal, make the grid of transistor M4 be low level signal, transistor M4 conducting, thus high-voltage level VGH is delivered to output terminal Out_Put.So the final output of this stage shift register cell is VGH high-voltage signal.
B-stage:
As shown in the figure, b-stage is the latter half of the one-period of the first clock signal clk 1 within a frame period.As shown in the figure, be high level cut-off signals at b-stage STV and CLK1, CLK2 is low level start signal.Because CLK1 is high level cut-off signals, transistor M3 is closed.Therefore, the low level STV signal inputted by transistor M3 in a stage remains on transistor M9 grid by electric capacity C1, makes transistor M9 still be in opening, is outputted on output terminal Out_Put by the low level signal of CLK2.The low level STV signal simultaneously inputted by transistor M3 in a stage also remains on the grid of transistor M1 by electric capacity C1, transistor M1 is also in opening.Transistor M7 is also because the CLK2 of its grid is that low level signal becomes opening, such Sheffer stroke gate structure just exports VGL low level by transistor M1 and M7 and opens signal, transistor M5 in inverter structure is opened, VGH is exported to the grid of transistor M4, transistor M4 is closed, ensures the output of transistor M9.So the final output of this stage shift register cell is low level signal.
The c stage:
As shown in the figure, the c stage is the first half of the second period of the first clock signal clk 1 within a frame period.As shown in the figure, be low level start signal at c stage CLK1, CLK2 is high level shutdown signal, and STV is high level shutdown signal.Transistor M3 opens by CLK1, thus STV high level signal is transferred to the grid of transistor M9, and transistor M9 is closed.Meanwhile, STV high level signal is also transferred to the grid of transistor M1.Like this, in Sheffer stroke gate structure, the signal controlling transistor M1 and M7 is all shutdown signal, therefore Sheffer stroke gate structure exports the grid of VGH signal to the transistor M5 of inverter structure by transistor M2, make inverter structure by transistor M6 output low level signal VGL, transistor M4 is opened, by VGH Signal transmissions on output terminal Out_Put.So the final output of this stage shift register cell is high level signal.
The d stage:
As shown in the figure, the d stage is the latter half of the second period of the first clock signal clk 1 within a frame period.As shown in the figure, in the d stage, CLK1 is high level cut-off signals, and CLK2 is low level start signal, and STV is high level shutdown signal.The signal now controlling transistor M1 in Sheffer stroke gate structure is high level shutdown signal, therefore, Sheffer stroke gate structure exports the gate terminal of high level shutdown signal to the transistor M5 of inverter structure by transistor M2, make inverter structure by the grid of transistor M6 output low level signal VGL to transistor M4, transistor M4 is opened, thus VGH signal is transferred on output terminal Out_Put by transistor M4.Transistor M9 is also in closed condition simultaneously.So the final output of this stage shift register cell is high level signal.
Process after inherent a, b, c and d stage in described frame period is all repetition c stage and d stage.
The 4th row oscillogram as can be seen from above description and Fig. 4:
In a stage, VGL signal exports to the grid of the transistor M4 controlling output signal by transistor M6, stably control the opening of output transistor M4, thus VGH signal stabilization can be outputted on the output terminal Out_Put of shift register cell by transistor M4.Finally can guarantee the stable output of shift register cell.
In b-stage, VGH signal exports to the grid of the transistor M4 controlling output signal by transistor M5, stably control the closed condition of output transistor M4, thus transistor M4 has blocked its source electrode and signal to the interference of output terminal Out_Put, makes it possible to the output terminal the Out_Put stably low level signal of CLK2 being outputted to shift register cell by transistor M9.Finally can guarantee the stable output of shift register cell.
In each c stage and d stage, the grid controlling the transistor M4 of output signal has stable low level signal input always, stably control the opening of output transistor M4, thus VGH signal stabilization can be outputted on the output terminal Out_Put of shift register cell by transistor M4.Finally can guarantee the stable output of shift register cell.
In sum, in above-mentioned shift register cell, there is not suspension point in output transistor gates place, thus can not affect by leak source, the current potential of this node can be kept to stablize, thus the stable signal output of transistor can be maintained, promote tracking-resistant ability and the stable output ability of shift register cell.
Fig. 6 illustrates the structural representation of a kind of gate driver circuit according to the utility model embodiment.Described gate driver circuit is used as the gate driver circuit of the array of display substrate of a liquid crystal display, for driving lining by line scan or writing line by line of described array of display substrate.As shown in the figure, gate driver circuit comprises multiple shift register cell, and wherein each shift register cell can be the shift register cell according to any one embodiment mentioned above.The mutual cascade of described multiple shift register cell, except afterbody shift register cell, output terminal (the OUTPUT1 of all the other each shift register cells, OUTPUT2, OUTPUT3 ...) all connect the input end (INPUT2 of the next stage shift register cell be adjacent, INPUT3 ...), wherein output terminal (the OUTPUT1 of each shift register cell, OUTPUT2, OUTPUT3 ...) all for exporting gate drive signal OG1, OG2, OG3 ..., for driving the scanning of corresponding row pixel in array of display substrate.Described gate drive signal also can be called as write control signal, for controlling the write of corresponding row pixel in array of display substrate.The number of described shift register cell can equal the line number of pixel in the array of display substrate that will drive.That is, array of display substrate comprises the pixel how many row will drive, and described gate driver circuit just needs how many shift register cells.But those of ordinary skill in the art know, the number of described shift register cell also can be not equal to the line number of pixel in the array of display substrate that will drive, and a shift register cell also may be used for driving the multirow pixel in array of display substrate.
Described gate driver circuit can comprise the first input end of clock CLK1, second clock input end CLK2, for inputting the first clock signal and second clock signal to each register cell.Described gate driver circuit can also comprise high level voltage end VGH and low level voltage end VGL, for providing high level voltage signal and low level voltage signal to each register cell.
The input end incoming frame start signal of the first order shift register cell of described gate driver circuit.In one embodiment, described frame start signal is a pulse signal, is used to indicate the beginning of a frame, is also referred to as frame scan and starts pulse signal STV.Described gate driver circuit is after receiving described frame start signal, after the shift LD of the shift register cell of described multiple cascade, produce multiple pulse signal through displacement, be respectively used to the scanning driving corresponding row pixel in array of display substrate.Such as, first shift register cell drive the scanning of the first row pixel or control the write of the first row pixel, second shift register cell drive the scanning of the second row pixel or control the write of the second row pixel, the 3rd shift register cell drives the scanning of the third line pixel or controls the write of the third line pixel, the rest may be inferred.In this way, described gate driver circuit just can realize the control write line by line on array of display substrate a frame two field picture raster data model or the realization of array of display substrate.
According to another embodiment, can also provide a kind of display device, described display device comprises gate driver circuit mentioned above, for carrying out raster data model to described display device or controlling the capable write of described display device.Because the structure of gate driver circuit has done detailed description in the aforementioned embodiment, do not repeated herein.According to another embodiment, described display device is liquid crystal display.
Although certain embodiments have been concrete description above with reference to accompanying drawing to of the present utility model, but one of ordinary skill in the art will appreciate that, above specific descriptions are only used to explain the utility model, and the utility model is never only confined to above-mentioned concrete embodiment.Based on herein to specific descriptions and the instruction of these embodiments; those of ordinary skill in the art can carry out various amendment, increase, displacement and modification to these embodiments and not depart from protection domain of the present utility model; that is, these amendments, increase, displacement and modification all should be encompassed in protection domain of the present utility model.Protection domain of the present utility model should described be as the criterion with the protection domain of claim.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operational zone, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also other key elements clearly do not listed can be comprised, or can also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the "a" or "an" before key element is also not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.As used herein, the indefinite article " a " before any key element or " an " do not get rid of and there is multiple such key element.
Claims (15)
1. a shift register cell, comprises load module, Sheffer stroke gate module, inverter modules, pull-up module and drop-down module,
Wherein said load module connects input end and first clock signal input terminal of shift register cell, for receiving input signal and the first clock signal, described load module is also connected to the first input end of described Sheffer stroke gate module and described drop-down module, for input signal being delivered to the first input end of described Sheffer stroke gate module and described drop-down module under the control of the first clock signal;
Second input end of wherein said Sheffer stroke gate module connects second clock signal input part for receiving the input of second clock signal, and the output terminal of described Sheffer stroke gate module connects described inverter modules;
The output terminal of wherein said inverter modules connects described pull-up module;
Wherein said pull-up module also connects the output terminal of shift register cell, for being high level according to the output of described inverter modules by the signal pull-up that the output terminal of described shift register cell exports;
Wherein said drop-down module also connects the output terminal of second clock signal input part and shift register cell, and the signal for being exported by the output terminal of described shift register cell under the control of the input signal received and second clock signal is drop-down is low level.
2. shift register cell according to claim 1, wherein, described load module comprises:
The first transistor, its first pole is connected to the input end of shift register cell to receive input signal, and its grid is connected to described first clock signal input terminal, and its second pole is connected to the first input end of described drop-down module and described Sheffer stroke gate module.
3. shift register cell according to claim 1, wherein, described Sheffer stroke gate module also connects high level signal input end and low level signal input end.
4. shift register cell according to claim 3, wherein, described Sheffer stroke gate module comprises transistor seconds, third transistor, the 4th transistor,
Wherein the first pole of transistor seconds connects described high level signal input end, and the second pole of transistor seconds and grid are interconnected and are connected to the first pole of third transistor and the output terminal of described Sheffer stroke gate module;
Wherein the grid of third transistor is connected to described second clock signal input part, and the second pole of third transistor connects the first pole of the 4th transistor;
Wherein the grid of the 4th transistor connects described load module, and the second pole of the 4th transistor connects described low level signal input end.
5. shift register cell according to claim 1, wherein, described inverter modules also connects high level signal input end and low level signal input end.
6. shift register cell according to claim 5, wherein, described inverter modules comprises the 5th transistor and the 6th transistor,
Wherein the first pole of the 5th transistor connects described high level signal input end, and the grid of the 5th transistor connects the output terminal of described Sheffer stroke gate module, and the second pole of the 5th transistor connects the first pole of the 6th crystal and described pull-up module;
Wherein the grid of the 6th transistor and the second pole link together, and connect described low level signal input end.
7. shift register cell according to claim 1, wherein, described pull-up module also connects high level signal input end.
8. shift register cell according to claim 7, wherein, described pull-up module comprises:
7th transistor, its first pole connects described high level signal input end, and its grid connects the output terminal of described inverter modules, and its second pole connects the output terminal of described drop-down module and shift register cell.
9. shift register cell according to claim 1, wherein, described drop-down module comprises:
8th transistor, its first pole connects the output terminal of shift register cell, and its grid connects described load module, and its second pole connects second clock signal input part;
Capacitor, between its first pole being connected to the 8th transistor and grid.
10. the transistor according to the shift register cell in claim 1-9 described in any one, wherein, in described shift register cell all adopts P-type crystal pipe.
11. according to the shift register cell in claim 1-9 described in any one, and wherein, described input signal is a burst enable signal.
12. according to the shift register cell in claim 1-9 described in any one, wherein, and described first clock signal and described second clock signal inversion signal each other.
13. 1 kinds of gate driver circuits, wherein, comprise multiple according to the shift register cell in claim 1-12 described in any one,
The mutual cascade of wherein said multiple shift register cell, except afterbody shift register cell, the output terminal of all the other each shift register cells all connects the input end of the next stage shift register cell be adjacent, wherein the output terminal of each shift register cell is all for exporting write control signal, for controlling the write of one-row pixels.
14. gate driver circuits according to claim 13, wherein, the input end incoming frame start signal of described first order shift register cell.
15. 1 kinds of display devices, is characterized in that, comprise as the gate driver circuit in claim 13-14 as described in any one.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420661459.1U CN204102543U (en) | 2014-11-07 | 2014-11-07 | Shift register cell and use its gate driver circuit and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420661459.1U CN204102543U (en) | 2014-11-07 | 2014-11-07 | Shift register cell and use its gate driver circuit and display device |
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| CN204102543U true CN204102543U (en) | 2015-01-14 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104282288A (en) * | 2014-11-07 | 2015-01-14 | 京东方科技集团股份有限公司 | Shifting register unit as well as grid electrode driving circuit and display device utilizing shifting register unit |
| CN106971692A (en) * | 2017-06-06 | 2017-07-21 | 京东方科技集团股份有限公司 | The drive circuit and display device of display panel |
| CN111210776A (en) * | 2020-01-19 | 2020-05-29 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
-
2014
- 2014-11-07 CN CN201420661459.1U patent/CN204102543U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104282288A (en) * | 2014-11-07 | 2015-01-14 | 京东方科技集团股份有限公司 | Shifting register unit as well as grid electrode driving circuit and display device utilizing shifting register unit |
| US9911503B2 (en) | 2014-11-07 | 2018-03-06 | Boe Technology Group Co., Ltd. | Shift register unit, gate drive circuit, and display device |
| CN106971692A (en) * | 2017-06-06 | 2017-07-21 | 京东方科技集团股份有限公司 | The drive circuit and display device of display panel |
| CN106971692B (en) * | 2017-06-06 | 2018-12-28 | 京东方科技集团股份有限公司 | The driving circuit and display device of display panel |
| CN111210776A (en) * | 2020-01-19 | 2020-05-29 | 京东方科技集团股份有限公司 | Gate drive circuit and display panel |
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