WO2018214758A1 - 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置 - Google Patents

金属导线、薄膜晶体管及制作方法、阵列基板和显示装置 Download PDF

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WO2018214758A1
WO2018214758A1 PCT/CN2018/086560 CN2018086560W WO2018214758A1 WO 2018214758 A1 WO2018214758 A1 WO 2018214758A1 CN 2018086560 W CN2018086560 W CN 2018086560W WO 2018214758 A1 WO2018214758 A1 WO 2018214758A1
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metal wire
conductive layer
layer
film transistor
zirconium
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PCT/CN2018/086560
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English (en)
French (fr)
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李海旭
曹占锋
姚琪
孟凡娜
汪建国
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Embodiments of the present disclosure relate to a metal wire, a thin film transistor, a fabrication method, an array substrate, and a display device.
  • the metal layer is made of a metal such as copper or silver having a small resistivity.
  • the metal film layer if copper is used as the metal film layer, there is a problem that copper has weak oxidation resistance; if a three-layer structure is considered to solve the problem that copper has weak oxidation resistance, etching is unstable and the uppermost layer is present.
  • the problem is that the conductivity is too low to guarantee normal operation.
  • Embodiments of the present disclosure provide a metal wire, a thin film transistor, a fabrication method, an array substrate, and a display device.
  • the metal wire includes a copper alloy, and the copper alloy contains chromium and zirconium. Among them, since chromium and zirconium have a high corrosion potential, the copper potential is increased after the copper is added, thereby improving the oxidation resistance of the copper.
  • Embodiments of the present disclosure provide a metal wire for use in a thin film transistor including a copper alloy containing a chromium, zirconium element.
  • the copper alloy has a chromium content of from 0.20 to 0.50% by weight and a zirconium content of from 0.20 to 0.30% by weight.
  • the metal wire includes a conductive layer and a precipitate layer formed on the upper surface by conductive chromatography of the precipitate; the conductive layer includes a copper alloy, and the precipitate layer includes a chromium, zirconium element.
  • the conductive layer has a thickness of
  • the metal wire further includes a bottom layer that conforms to a lower surface of the conductive layer, the bottom layer including a molybdenum alloy containing a zirconium element.
  • the molybdenum alloy has a zirconium content of from 0.25 to 0.35% by weight.
  • the bottom layer thickness is
  • Embodiments of the present disclosure also provide another thin film transistor including the metal wiring described in the above embodiments.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain, wherein the gate, the source, and the drain adopt a two-layer structure.
  • both the source and the drain in the thin film transistor employ the metal wire as a conductive electrode.
  • the gate insulating layer is an upper film layer that is attached to the gate, such as at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film.
  • a silicon oxide film such as at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film.
  • the active layer is deposited using indium gallium zinc oxide.
  • Another embodiment of the present disclosure further provides a method for fabricating a thin film transistor, which is applied to the thin film transistor described in the above embodiments, comprising forming a conductive layer in the thin film transistor by using a copper alloy containing chromium and zirconium elements.
  • Solid solution, the substrate carrying the conductive layer is solution treated at a temperature of 280-350 ° C for 20 min ⁇ 40 min;
  • the substrate carrying the conductive layer was rapidly cooled at a rate of 10-15 ° C/min.
  • Embodiments of the present disclosure also provide an array substrate including the thin film transistor described in the above embodiments.
  • An embodiment of the present disclosure further provides a display device including the array substrate described in the above embodiments.
  • FIG. 1 is a schematic structural view of a thin film transistor in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural view of a metal wire according to an embodiment of the present disclosure, which is a schematic structural view of a conductive layer and a precipitate layer.
  • FIG 3 is a schematic structural view of a metal wire according to another embodiment of the present disclosure, which is a structural intention of a conductive layer, a precipitate layer, and a bottom layer.
  • FIG. 4 is a flow chart of a method of fabricating a thin film transistor in an embodiment of the present disclosure.
  • the core of a high-quality flat panel display is a thin film transistor (TFT).
  • the process of fabricating a TFT substrate generally includes: cleaning, film formation, PR coating, exposure, development, etching, and PR stripping. Among them, the film is divided into a metal film and a non-metal film.
  • the metal film is formed by PVD, that is, physical vapor deposition, which is also called sputtering.
  • the non-metal film is formed by CVD, that is, chemical vapor deposition. Like the semiconductor process, it is mainly formed by plasma CVD or PECVD.
  • the PECVD film formation includes: G-SiNx (gate switch), La Si (Electronic channel), Ha Si (reduced photocurrent), n+a Si (signal line transmission), PA-SiNx (protective layer, anti-corrosion).
  • G-SiNx gate switch
  • La Si Electrode
  • Ha Si reduced photocurrent
  • n+a Si signal line transmission
  • PA-SiNx protecting layer, anti-corrosion
  • the metal film includes deposition of a metal electrode such as a gate electrode, a source electrode, and a drain electrode.
  • a TFT metal wire is formed on the deposition of the film layer.
  • an embodiment of the present disclosure provides a thin film transistor including a metal wire.
  • the metal wires can be used for the gate 1, the source 2, and the drain 3, for example, in the present embodiment, the metal wires are used for the source 2 and the drain 3.
  • the metal wire includes a copper Cu alloy containing chromium Cr, zirconium Zr elements. It will be apparent to those skilled in the art that when other materials are added or doped to the metal, the original properties of the metal are affected. In the present embodiment, when a copper metal having a high conductivity is used as a metal wire target, since the oxidation resistance of copper is considered to be weak, when the oxidation resistance is desired, the metal conductivity is lowered.
  • the other substances are chromium or zirconium.
  • the copper alloy has a chromium content of 0.20-0.50% by weight and a zirconium content of 0.20-0.30%wt. Since both alloy chromium and zirconium have high corrosion potential, the addition of chromium and zirconium to the copper can effectively increase the copper potential and improve the oxidation resistance. At the same time, since chromium and zirconium are easily passivated, uniform and dense on the metal surface is formed. The protective film layer can better improve the oxidation resistance of the metal.
  • the present disclosure also provides another embodiment, for example, using the copper alloy (including chromium, zirconium elements, and the copper alloys mentioned below all contain chromium and zirconium elements).
  • the copper alloy serves as a metal target to form a conductive layer 11 in the metal wire (wherein the conductivity of the conductive layer 11 is determined by the copper alloy).
  • the thickness of the conductive layer 11 is After the conductive layer 11 is formed, after treatment, a uniform layer of chromium- and zirconium-rich precipitates is formed on the surface of the conductive layer 11 (including the upper and lower surfaces, in this embodiment, for example, the upper surface).
  • the protective conductive layer 11 is protected from external oxygen and the roughness of the surface is improved.
  • the precipitate layer 111 is mainly formed of precipitates in the conductive layer 11, for example, the precipitate layer 111 includes CrCu 2 (Zr) accompanied by a small amount of Cu 5 Cr. Since the precipitate layer 111 includes chromium and zirconium, it is proved that the content of chromium and zirconium originally contained in the conductive layer 11 is reduced, and precipitation of precipitates is accompanied by a decrease in particles inside the conductive layer 11, which makes the copper alloy The conductivity is improved (the conductivity of copper is lowered when other alloys are added, and the conductivity of the copper alloy is restored when some other substances in the copper alloy are precipitated). In this embodiment, it is determined by the test when precipitation When precipitated, the conductivity of the copper alloy can be restored to 92% IACS (pure copper is greater than 98% IACS).
  • the metal wire further includes a molybdenum Mo alloy containing zirconium element, for example, the molybdenum alloy (including zirconium element, mentioned below)
  • the molybdenum alloy is a molybdenum alloy containing zirconium elements, except for the others, and the zirconium content is 0.25-0.35% by weight.
  • the molybdenum alloy serves as a metal target to form a bottom layer 12 of the metal wire to which the lower surface of the conductive layer 11 is attached (the thickness of the bottom layer 12 is ).
  • the conductive layer 11 and the bottom layer 12 can be better at the cross-line. Ground contact.
  • the metal wire includes the following film layers:
  • the conductive layer 11 is composed of a copper alloy containing chromium and zirconium elements
  • the underlayer 12 is bonded to the lower surface of the conductive layer 11 and is made of a zirconium-containing molybdenum alloy.
  • a precipitate layer 111 formed on the upper surface of the conductive layer 11 is further included, and the precipitate layer 111 is composed of precipitates of the conductive layer 11.
  • the deposit layer 111 is present on the upper surface of the conductive layer 11, and the conductive layer 11 is well protected from external oxygen. Therefore, in the embodiment, the double layer structure is selected to prevent the copper surface. Oxidation problem occurs, and the use of a two-layer structure also improves the stability of the etching, and since the surface of the film layer is the precipitate layer 111, the adhesion of the upper film layer to the photoresist in the prior art is better solved. The problem.
  • the source 2 and the drain 3 formed are formed to have a structure in which the metal wire is formed due to easy contact with air.
  • the gate electrode 1 can be formed by conventional metal film layer deposition.
  • the gate electrode 1 since the existence of the gate insulating layer is considered, the gate electrode 1 has a two-layer structure.
  • the conductive layer in the gate 1 may be formed by a conventional metal target (which may also be formed by using the alloy target provided by the present disclosure), and the bottom layer 12 of the metal wire in the above embodiment is selected as the bottom layer.
  • the gate insulating layer is at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film. Adjacent to the gate insulating layer is an active layer, and the active layer is deposited using indium gallium zinc oxide.
  • the film structure in the metal wires described in the above embodiments is selected, that is, the conductive layers of the source 2 and the drain 3 are selected from the conductive layer 11 in the above embodiment, and the conductive layer 11 is used.
  • the upper surface includes a precipitate layer 111; the bottom layer of the source electrode 2 and the drain electrode 3 is selected from the bottom layer 12 of the metal wires described in the above embodiments.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, which is mainly applied to the thin film transistor described in any of the above embodiments, which comprises forming a copper alloy containing chromium and zirconium elements.
  • a step of forming a precipitate layer 111 on the upper surface of the conductive layer 11 is as follows:
  • S101 is solid-solved, and the substrate carrying the conductive layer 11 is solution-treated at a temperature of 280-350 ° C for 20 min to 40 min. For example, it is solution treated for 30 min.
  • S102 is aged, and the substrate carrying the conductive layer 11 is subjected to aging treatment for 20 min to 40 min when the furnace is cooled to 150-200 ° C. For example, it is aged for 30 minutes.
  • the step of solid solution and aging causes the conductive layer 11 to form a precipitate on the surface after a certain treatment, and the step of cooling causes the precipitate to rapidly solidify to form the precipitate layer 111.
  • the conductive layer 11 is precipitated to form a precipitate layer 111, and the conductivity of the conductive layer 11 is ensured, and the conductive layer 11 is better due to the presence of the precipitate layer 111. protection of.
  • an array substrate comprising the thin film transistor according to any of the above embodiments, for example, an alloyed high conductivity, high toughness TFT.
  • a display device comprising the array substrate as described in any of the above embodiments.
  • the display device refers to a device for obtaining information by a person through visual perception.
  • the display device naturally inherits all the advantages of the array substrate, and may be a single display panel, such as a display panel for mounting on a screen of a computer; Further, the display device may be any product or component having a display function such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure forms a conductive layer by using a copper alloy, and forms a precipitate layer on the upper surface after a certain treatment process, and forms a bottom layer by using a molybdenum alloy, thereby achieving high conductivity and high toughness to a certain extent. Effectively reducing power consumption increases the response time of the display panel, ensuring display performance and display stability, while simplifying the metal film structure, reducing the complexity of the overall manufacturing of the corresponding device or system, and effectively saving costs.
  • the present disclosure has the following advantages:
  • the metal wire provided by the embodiment of the present disclosure includes a copper alloy containing chromium and zirconium, wherein since chromium and zirconium have a high corrosion potential, the copper potential is increased after the copper is added, thereby improving the resistance of the copper. Oxidation ability.
  • the copper alloy forms a conductive layer in the metal wire, and the conductive layer precipitates a precipitate on the upper surface thereof to form a precipitate layer. Due to the formation of the precipitate layer, the reaction between the metal wire and the oxygen is due to the first contact The precipitate layer provides a strong protective effect on the conductive layer.
  • the metal wire further comprises a bottom layer, wherein the bottom layer is formed of a molybdenum alloy, and the molybdenum alloy comprises a zirconium element, and the zirconium has higher toughness and can reduce the stacking fault energy of the alloy, that is, soften the metal. It gives it a higher toughness and metal wires for better performance.
  • the above-mentioned metal wires are used, which naturally inherits all the advantages of the metal wires.
  • the source and the drain are formed by the metal wire, which may have a two-layer structure, which improves the stability of etching and the efficiency of production.
  • the step of forming the conductive layer in the metal wire in the step of forming a precipitate layer on the surface of the conductive layer, by solute aging treatment of the substrate carrying the conductive layer, copper is The alloy is used as a target to form a precipitate of conductive chromatography, which is cooled to form a solidified precipitate layer; due to the solid solution and aging treatment by the method, the internal particles are reduced, and the conductivity of the copper alloy is improved; The precipitates quickly solidify on the surface of the film formed by the copper alloy, enhancing the protection of the thin film transistor.
  • the array substrate provided by the embodiment of the present disclosure is formed by using the above-described thin film transistor, and therefore, the array naturally inherits all the advantages of the thin film transistor.
  • the display device provided by the embodiment of the present disclosure may be a display panel, which is fabricated by using the above array substrate; in addition, the display device may also be a device with a display panel.
  • the embodiments of the present disclosure can not only achieve high conductivity and high toughness to a certain extent, but also reduce power consumption more effectively, improve response time of the display panel, ensure display effect and display stability, and simplify metal film structure and reduce The complexity of the overall fabrication of the corresponding device or system and the effective cost savings.

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Abstract

本公开的实施例涉及一种金属导线、薄膜晶体管及制作方法、阵列基板和显示装置。所述一种金属导线，应用于薄膜晶体管，其包括含有铬、锆元素的铜合金。本公开通过采用铜合金形成导电层，经过一定处理工艺后再上表面形成析出物层，采用钼合金形成底层，不仅可在一定程度上实现高导电性、高韧性，更有效地降低功耗提高显示面板的响应时间，确保显示效果与显示稳定性，同时简化金属膜结构、降低相应装置或***整体制造的复杂性及有效地节约成本。

Description

金属导线、薄膜晶体管及制作方法、阵列基板和显示装置
本申请要求于2017年5月25日递交的中国专利申请第201710379101.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种金属导线、薄膜晶体管及制作方法、阵列基板和显示装置。
背景技术
随着液晶显示技术的不断发展，人们对于高分辨率，高色彩度以及高清晰度的显示屏需求愈发强烈。在提高显示面板的响应时间以及降低功耗方面，在制作TFT阵列基板时，金属层多采用电阻率较小的铜、银等金属制成。
但是，已知技术中，如果采用铜作为金属膜层，则存在铜耐氧化能力弱的问题；如果考虑采用三层结构解决铜的耐氧化能力弱的问题，则存在刻蚀不稳定以及最上层膜层与光刻胶粘附的问题，其中，三层结构一般为上下层均采用Mo制成而中间层采用导电率较高的金属制成；同时，如果考虑采用合金作为金属膜层解决上述问题，则存在导电性过低而无法保证正常工作的问题。
发明内容
本公开的实施例提供一种金属导线、薄膜晶体管及制作方法、阵列基板和显示装置。所述金属导线中，包括铜合金，铜合金中包含铬和锆，其中由于铬、锆具有较高的腐蚀电位，加入铜后提高了铜的金属电位，从而提高了铜的耐氧化能力。
本公开的实施例提供了一种金属导线，应用于薄膜晶体管，包括含有铬、锆元素的铜合金。
在一些示例中，所述铜合金中铬含量为0.20-0.50％wt，锆含量为 0.20-0.30％wt。
在一些示例中，所述金属导线包括导电层以及由导电层析出析出物于上表面形成的析出物层；所述导电层包括铜合金，所述析出物层包括铬、锆元素。
在一些示例中，所述导电层厚度为
Figure PCTCN2018086560-appb-000001
在一些示例中，所述金属导线还包括贴合所述导电层下表面的底层，所述底层包括含锆元素的钼合金。
在一些示例中，所述钼合金中锆含量为0.25-0.35％wt。
在一些示例中，所述底层厚度为
Figure PCTCN2018086560-appb-000002
本公开的实施例还提供另一种薄膜晶体管，包括上述实施例所述的金属导线。
在一些示例中，所述薄膜晶体管包括栅极、栅极绝缘层、有源层、源极以及漏极，其中，所述栅极、源极以及漏极采用双层结构。
在一些示例中，所述薄膜晶体管中的源极与漏极皆采用所述金属导线充当导电电极。
在一些示例中，所述栅极绝缘层为贴合所述栅极的上层膜层，例如为二氧化硅薄膜、氮化硅薄膜、氮氧化硅薄膜、氧化铝薄膜、氧化钛薄膜中的至少一种。
在一些示例中，所述有源层采用铟镓锌氧化物沉积而成。
本公开的另一实施例还提供一种薄膜晶体管的制作方法，应用于上述实施例所述的薄膜晶体管，包括采用含铬、锆元素的铜合金形成所述薄膜晶体管中导电层后，在所述导电层上表面形成析出物层的步骤：
固溶，将承载所述导电层的基板在温度为280-350℃下固溶处理20min～40min；
时效，将承载所述导电层的基板随炉冷却到150-200℃时，进行时效处理20min～40min；
冷却，将承载所述导电层的基板以10-15℃/min的速度快速冷却。
本公开的实施例还提供一种阵列基板，包括上述实施例所述的薄膜晶体管。
本公开的实施例还提供一种显示装置，包括上述实施例所述的阵列基板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开的实施例中一种薄膜晶体管的结构示意图。
图2为本公开的实施例中一种金属导线的结构示意图，为导电层以及析出物层的结构示意图。
图3为本公开中另一实施例中一种金属导线的结构示意图，为导电层、析出物层以及底层的结构意图。
图4为本公开的实施例中一种薄膜晶体管的制作方法流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
高质量的平板显示器的核心是薄膜晶体管(Thinfilmtransistor,TFT)，TFT基板制作的工序一般包括：清洗、成膜、PR涂布、曝光、显影、刻蚀、PR剥离。其中，成膜分金属膜和非金属膜。金属膜采用PVD，即物理气相淀积的方式成膜，又叫溅射。非金属膜采用CVD，即化学气相淀积的方式成膜，与半导体工艺相同，主要采取等离子CVD即PECVD的方式成膜，PECVD成膜膜种包括：G-SiNx(栅极开关)、L-a Si(电子沟道)、H-a Si(降低光电流)、n+a Si(信号线传输)、PA-SiNx(保护层，抗腐蚀)。在金属膜的成膜过程中，其包括对栅极、源极、漏极等金属电极的沉积。而对其膜层的沉积，形成了TFT金属导线。
如图1所示，本公开的实施例提供了一种薄膜晶体管，所述薄膜晶体管中包括一种金属导线。所述金属导线可用于栅极1、源极2以及漏极3，例如，在本实施例中，所述金属导线用于源极2以及漏极3。所述金属导线包括含 有铬Cr、锆Zr元素的铜Cu合金。本领域技术人员可知，在金属中加入或掺杂其他物质时，会影响其金属本来的特性。在本实施例中，当采用到导电率高的铜金属作为金属导线靶材时，由于考虑到铜的耐氧化能力较弱，当想提高其耐氧化能力时，却又面临金属导电率降低的问题，所以本申请发明人选择往铜中加入总含量小于1％的其他物质，例如，所述其他物质为铬、锆。其中，所述铜合金中铬含量为0.20-0.50％wt，锆含量为0.20-0.30％wt。由于合金铬、锆均具有较高的腐蚀电位，所以往铜中加入铬、锆可有效地提高铜金属电位从而提高耐氧化能力；同时，由于铬、锆容易钝化，在金属表面形成均匀致密的保护膜层，能更好地提高金属的耐氧化能力。
如图2所示，区别于上述实施例，本公开还提供另一种实施例，例如为采用所述铜合金(包含铬、锆元素，以下提及铜合金时均为含有铬、锆元素的铜合金，另有说明的除外)作为金属靶材，形成金属导线中的导电层11(此时导电层11的导电率决定于铜合金)。所述导电层11的厚度为
Figure PCTCN2018086560-appb-000003
当形成所述导电层11后，经过处理后，会在导电层11的表面(包括上、下表面，在本实施中例如为上表面)形成一层均匀的富含铬、锆的析出物层111保护导电层11不受外界氧的影响，且提高了表面的粗糙度。所述析出物层111主要由导电层11中析出物形成，例如，所述析出物层111包括CrCu 2(Zr)，并伴有少量Cu 5Cr。由于所述析出物层111中包括铬、锆，证明着导电层11中原来所含有的铬、锆含量减少，且析出物的析出还伴有导电层11内部颗粒的减少，其使得铜合金的导电率得到提高(当加入其他合金时会降低铜的导电率，当铜合金中的部分其他物质析出时，将使得铜合金的导电率恢复)，在本实施例中，通过测试得出当析出析出物时，铜合金的导电性可以恢复到92％IACS(纯铜为大于98％IACS)。
如图3所示，区别于上述实施例，本公开还提供另一种实施例，所述金属导线还包括含锆元素的钼Mo合金，例如，所述钼合金(包含锆元素，以下提及钼合金时均为含有锆元素的钼合金，另有说明的除外)中锆含量为0.25-0.35％wt。所述钼合金作为金属靶材，形成金属导线中贴合所述导电层11下表面的底层12(所述底层12厚度为
Figure PCTCN2018086560-appb-000004
)。进一步地，由于所述底层12中少量锆的存在可以降低合金的堆垛层错能(即软化金属使其具有更高的韧性)，其有利于导电层11与底层12在跨线处更好地接触。
例如，通过上述实施例的说明可见，所述金属导线包括如下膜层：
导电层11，由含铬、锆元素的铜合金构成；
底层12，贴合在所述导电层11的下表面，由含锆元素的钼合金构成。
进一步地，还包括形成在所述导电层11上表面的析出物层111，所述析出物层111由导电层11的析出物构成。由于在本实施例中，导电层11的上表面存有析出物层111，能很好地保护导电层11不受外界氧的影响，所以在本实施例中，选用双层结构足以防止铜表面氧化问题的发生，同时采用双层结构还提高了刻蚀的稳定性，且由于膜层的表面为析出物层111，更好地解决了已知技术中上层膜层与光刻胶粘附力的问题。
在薄膜晶体管成膜过程中，形成的源极2、漏极3由于容易接触空气，形成所述金属导线的结构。在沉积栅极1时，由于栅极1的上层膜层通常为栅极绝缘层，不涉及氧气氧化的问题，所以所述栅极1可选用常规金属膜层沉积形成。在本实施例中，由于考虑到所述栅极绝缘层的存在，所以所述栅极1选用双层结构。所述栅极1中的导电层可采用常规金属靶材形成(也可选用本公开提供的合金靶材形成)，底层选用上述实施例中金属导线的底层12。所述栅极绝缘层为二氧化硅薄膜、氮化硅薄膜、氮氧化硅薄膜、氧化铝薄膜、氧化钛薄膜中的至少一种。贴近所述栅极绝缘层的为有源层，所述有源层采用铟镓锌氧化物沉积而成。
在沉积源极2、漏极3时，选用上述实施例所述金属导线中的膜层结构，即源极2、漏极3的导电层选用上述实施例中的导电层11，导电层11的上表面包括析出物层111；源极2、漏极3的底层选用上述实施例所述金属导线中的底层12。
如图4所示，本公开的实施例还提供一种薄膜晶体管的制作方法，主要应用于上述任一实施例中所述的薄膜晶体管中，其包括采用含铬、锆元素的铜合金形成所述薄膜晶体管中导电层11后，在所述导电层11上表面形成析出物层111的步骤：
S101固溶，将承载所述导电层11的基板在温度为280-350℃下固溶处理20min～40min。例如，其固溶处理30min。
S102时效，将承载所述导电层11的基板随炉冷却到150-200℃时，进行时效处理20min～40min。例如，其时效处理30min。
S103冷却，将承载所述导电层11的基板以10-15℃/min的速度快速冷却。
所述固溶、时效的步骤使得导电层11经过一定的处理后在表面形成析出物，所述冷却的步骤使得析出物快速固化形成析出物层111。通过本实施例所提供的制作方法后，使得导电层11析出析出物以构成析出物层111，在保证了导电层11的导电率的同时由于析出物层111的存在使得导电层11得到较好的保护。
在另一实施例中，还提供一种阵列基板，包括如上述任一实施例所述的薄膜晶体管，例如为一种合金化高导电性、高韧性的TFT。
在另一实施例中，还提供一种显示装置，包括如上述任一实施例中所述的阵列基板。所述显示装置指人通过视感觉而获得信息的装置，所述显示装置自然继承了所述阵列基板的全部优点，其可为单一的显示面板，如用于安装在电脑的屏幕的显示面板；进一步地，所述显示装置可以为电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
综上，本公开的实施例通过采用铜合金形成导电层，经过一定处理工艺后再上表面形成析出物层，采用钼合金形成底层，不仅可在一定程度上实现高导电性、高韧性，更有效地降低功耗提高显示面板的响应时间，确保显示效果与显示稳定性，同时简化金属膜结构、降低相应装置或***整体制造的复杂性及有效地节约成本。
与已知技术相比，本公开具备如下优点：
本公开的实施例提供的金属导线中，包括铜合金，铜合金中包含铬和锆，其中由于铬、锆具有较高的腐蚀电位，加入铜后提高了铜的金属电位从而提高了铜的耐氧化能力。所述铜合金形成金属导线中的导电层，所述导电层在其上表面析出析出物形成析出物层，由于析出物层的形成，使得金属导线与氧气的反应过程中，由于先接触的是析出物层，给导电层带来较强的保护作用。同时，由于导电层中铬、锆元素的析出形成析出物层，降低了导电层物质的掺杂，提高了导电层的导电率。其中，所述金属导线还包括底层，其中底层的形成材料为钼合金，而钼合金中包括锆元素，由于锆存在较高的韧性，且能降低合金的堆垛层错能，亦即软化金属使其具有更高的韧性，金属导线获得更优的性能。
本公开提供的薄膜晶体管中，采用上述的金属导线，自然继承了所述金属导线的全部优点。例如，提供的薄膜晶体管中，源极以及漏极采用所述金属导线构成，其可以为双层结构，提高了刻蚀的稳定性，以及生产的效率。
同时，本公开的实施例提供的金属导线中形成所述导电层后，在所述导电层的表面形成析出物层的步骤中，通过将承载所述导电层的基板固溶时效处理，由铜合金作为靶材形成的导电层析出析出物，经过冷却形成固化的析出物层；由于经过该方法固溶、时效的处理，内部颗粒的减少，提高了铜合金的导电性；由于冷却的处理，析出物很快地在铜合金形成的膜层表面固化，加强了对薄膜晶体管的保护作用。
同时，本公开的实施例提供的阵列基板是采用上述的薄膜晶体管而成，因此，所述阵列自然继承了所述薄膜晶体管的全部优点。
相应地，本公开的实施例提供的显示装置可为显示面板，所述显示面板为采用上述阵列基板制作而成；另外，显示装置还可为带有显示面板的装置。
综上，本公开的实施例不仅可在一定程度上实现高导电性、高韧性，更有效地降低功耗提高显示面板的响应时间，确保显示效果与显示稳定性，同时简化金属膜结构、降低相应装置或***整体制造的复杂性及有效地节约成本。
以上所述仅是本公开的示范性实施方式，而非用于限制本公开的保护范围，本公开的保护范围由所附的权利要求确定。

Claims (10)

  1. 一种金属导线，应用于薄膜晶体管，包括含有铬、锆元素的铜合金。
  2. 根据权利要求1所述的金属导线，其中，所述铜合金中铬含量为0.20-0.50％wt，锆含量为0.20-0.30％wt。
  3. 根据权利要求1或2所述的金属导线，其中，所述金属导线包括导电层以及由导电层析出析出物于上表面形成的析出物层；所述导电层包括铜合金，所述析出物层包括铬、锆元素。
  4. 根据权利要求3所述的金属导线，其中，所述金属导线还包括贴合所述导电层下表面的底层，所述底层包括含锆元素的钼合金。
  5. 根据权利要求4所述的金属导线，其中，所述钼合金中锆含量为0.25-0.35％wt。
  6. 一种薄膜晶体管，包括如权利要求1～5任一项所述的金属导线。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述薄膜晶体管中的源极与漏极皆采用所述金属导线充当导电电极。
  8. 一种薄膜晶体管的制作方法，应用于权利要求6或7所述的薄膜晶体管，包括采用含铬、锆元素的铜合金形成所述薄膜晶体管中的导电层后，在所述导电层上表面形成析出物层的步骤：
    固溶，将承载所述导电层的基板在温度为280-350℃下固溶处理20min～40min；
    时效，将承载所述导电层的基板随炉冷却到150-200℃时，进行时效处理20min～40min；
    冷却，将承载所述导电层的基板以10-15℃/min的速度快速冷却。
  9. 一种阵列基板，包括权利要求6或7所述的薄膜晶体管。
  10. 一种显示装置，包括权利要求9所述的阵列基板。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102314271A (zh) * 2010-07-07 2012-01-11 宸鸿科技(厦门)有限公司 一种电容式触控图形结构及其制法、触控面板及触控显示装置
EP3064604A1 (en) * 2013-11-01 2016-09-07 AutoNetworks Technologies, Ltd. Copper alloy wire, copper alloy stranded wire, coated electric wire, wire harness and manufacturing method of copper alloy wire
CN106086511A (zh) * 2016-08-10 2016-11-09 安徽晋源铜业有限公司 一种高性能铜导线及其制备方法
CN106544533A (zh) * 2014-11-11 2017-03-29 芜湖市民泰铜业有限责任公司 一种高强高导导线用铜合金的制备方法
CN107204320A (zh) * 2017-05-25 2017-09-26 京东方科技集团股份有限公司 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195395C (zh) * 2001-01-30 2005-03-30 日鉱金属股份有限公司 积层板用铜合金箔
KR100550505B1 (ko) * 2001-03-01 2006-02-13 가부시끼가이샤 도시바 반도체 장치 및 반도체 장치의 제조 방법
JP3731600B2 (ja) * 2003-09-19 2006-01-05 住友金属工業株式会社 銅合金およびその製造方法
CN104701384A (zh) * 2015-04-09 2015-06-10 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN105112720A (zh) * 2015-09-08 2015-12-02 周欢 一种用于导线的铜合金

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102314271A (zh) * 2010-07-07 2012-01-11 宸鸿科技(厦门)有限公司 一种电容式触控图形结构及其制法、触控面板及触控显示装置
EP3064604A1 (en) * 2013-11-01 2016-09-07 AutoNetworks Technologies, Ltd. Copper alloy wire, copper alloy stranded wire, coated electric wire, wire harness and manufacturing method of copper alloy wire
CN106544533A (zh) * 2014-11-11 2017-03-29 芜湖市民泰铜业有限责任公司 一种高强高导导线用铜合金的制备方法
CN106086511A (zh) * 2016-08-10 2016-11-09 安徽晋源铜业有限公司 一种高性能铜导线及其制备方法
CN107204320A (zh) * 2017-05-25 2017-09-26 京东方科技集团股份有限公司 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置

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