WO2018214758A1 - Fil métallique, transistor à couches minces et son procédé de fabrication, substrat de réseau et dispositif d'affichage - Google Patents

Fil métallique, transistor à couches minces et son procédé de fabrication, substrat de réseau et dispositif d'affichage Download PDF

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Publication number
WO2018214758A1
WO2018214758A1 PCT/CN2018/086560 CN2018086560W WO2018214758A1 WO 2018214758 A1 WO2018214758 A1 WO 2018214758A1 CN 2018086560 W CN2018086560 W CN 2018086560W WO 2018214758 A1 WO2018214758 A1 WO 2018214758A1
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WO
WIPO (PCT)
Prior art keywords
metal wire
conductive layer
layer
film transistor
zirconium
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PCT/CN2018/086560
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English (en)
Chinese (zh)
Inventor
李海旭
曹占锋
姚琪
孟凡娜
汪建国
Original Assignee
京东方科技集团股份有限公司
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Publication of WO2018214758A1 publication Critical patent/WO2018214758A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01B—CABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B1/00—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors
    • H01B1/02—Conductors or conductive bodies characterised by the conductive materials; Selection of materials as conductors mainly consisting of metals or alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • Embodiments of the present disclosure relate to a metal wire, a thin film transistor, a fabrication method, an array substrate, and a display device.
  • the metal layer is made of a metal such as copper or silver having a small resistivity.
  • the metal film layer if copper is used as the metal film layer, there is a problem that copper has weak oxidation resistance; if a three-layer structure is considered to solve the problem that copper has weak oxidation resistance, etching is unstable and the uppermost layer is present.
  • the problem is that the conductivity is too low to guarantee normal operation.
  • Embodiments of the present disclosure provide a metal wire, a thin film transistor, a fabrication method, an array substrate, and a display device.
  • the metal wire includes a copper alloy, and the copper alloy contains chromium and zirconium. Among them, since chromium and zirconium have a high corrosion potential, the copper potential is increased after the copper is added, thereby improving the oxidation resistance of the copper.
  • Embodiments of the present disclosure provide a metal wire for use in a thin film transistor including a copper alloy containing a chromium, zirconium element.
  • the copper alloy has a chromium content of from 0.20 to 0.50% by weight and a zirconium content of from 0.20 to 0.30% by weight.
  • the metal wire includes a conductive layer and a precipitate layer formed on the upper surface by conductive chromatography of the precipitate; the conductive layer includes a copper alloy, and the precipitate layer includes a chromium, zirconium element.
  • the conductive layer has a thickness of
  • the metal wire further includes a bottom layer that conforms to a lower surface of the conductive layer, the bottom layer including a molybdenum alloy containing a zirconium element.
  • the molybdenum alloy has a zirconium content of from 0.25 to 0.35% by weight.
  • the bottom layer thickness is
  • Embodiments of the present disclosure also provide another thin film transistor including the metal wiring described in the above embodiments.
  • the thin film transistor includes a gate, a gate insulating layer, an active layer, a source, and a drain, wherein the gate, the source, and the drain adopt a two-layer structure.
  • both the source and the drain in the thin film transistor employ the metal wire as a conductive electrode.
  • the gate insulating layer is an upper film layer that is attached to the gate, such as at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film.
  • a silicon oxide film such as at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film.
  • the active layer is deposited using indium gallium zinc oxide.
  • Another embodiment of the present disclosure further provides a method for fabricating a thin film transistor, which is applied to the thin film transistor described in the above embodiments, comprising forming a conductive layer in the thin film transistor by using a copper alloy containing chromium and zirconium elements.
  • Solid solution, the substrate carrying the conductive layer is solution treated at a temperature of 280-350 ° C for 20 min ⁇ 40 min;
  • the substrate carrying the conductive layer was rapidly cooled at a rate of 10-15 ° C/min.
  • Embodiments of the present disclosure also provide an array substrate including the thin film transistor described in the above embodiments.
  • An embodiment of the present disclosure further provides a display device including the array substrate described in the above embodiments.
  • FIG. 1 is a schematic structural view of a thin film transistor in an embodiment of the present disclosure.
  • FIG. 2 is a schematic structural view of a metal wire according to an embodiment of the present disclosure, which is a schematic structural view of a conductive layer and a precipitate layer.
  • FIG 3 is a schematic structural view of a metal wire according to another embodiment of the present disclosure, which is a structural intention of a conductive layer, a precipitate layer, and a bottom layer.
  • FIG. 4 is a flow chart of a method of fabricating a thin film transistor in an embodiment of the present disclosure.
  • the core of a high-quality flat panel display is a thin film transistor (TFT).
  • the process of fabricating a TFT substrate generally includes: cleaning, film formation, PR coating, exposure, development, etching, and PR stripping. Among them, the film is divided into a metal film and a non-metal film.
  • the metal film is formed by PVD, that is, physical vapor deposition, which is also called sputtering.
  • the non-metal film is formed by CVD, that is, chemical vapor deposition. Like the semiconductor process, it is mainly formed by plasma CVD or PECVD.
  • the PECVD film formation includes: G-SiNx (gate switch), La Si (Electronic channel), Ha Si (reduced photocurrent), n+a Si (signal line transmission), PA-SiNx (protective layer, anti-corrosion).
  • G-SiNx gate switch
  • La Si Electrode
  • Ha Si reduced photocurrent
  • n+a Si signal line transmission
  • PA-SiNx protecting layer, anti-corrosion
  • the metal film includes deposition of a metal electrode such as a gate electrode, a source electrode, and a drain electrode.
  • a TFT metal wire is formed on the deposition of the film layer.
  • an embodiment of the present disclosure provides a thin film transistor including a metal wire.
  • the metal wires can be used for the gate 1, the source 2, and the drain 3, for example, in the present embodiment, the metal wires are used for the source 2 and the drain 3.
  • the metal wire includes a copper Cu alloy containing chromium Cr, zirconium Zr elements. It will be apparent to those skilled in the art that when other materials are added or doped to the metal, the original properties of the metal are affected. In the present embodiment, when a copper metal having a high conductivity is used as a metal wire target, since the oxidation resistance of copper is considered to be weak, when the oxidation resistance is desired, the metal conductivity is lowered.
  • the other substances are chromium or zirconium.
  • the copper alloy has a chromium content of 0.20-0.50% by weight and a zirconium content of 0.20-0.30%wt. Since both alloy chromium and zirconium have high corrosion potential, the addition of chromium and zirconium to the copper can effectively increase the copper potential and improve the oxidation resistance. At the same time, since chromium and zirconium are easily passivated, uniform and dense on the metal surface is formed. The protective film layer can better improve the oxidation resistance of the metal.
  • the present disclosure also provides another embodiment, for example, using the copper alloy (including chromium, zirconium elements, and the copper alloys mentioned below all contain chromium and zirconium elements).
  • the copper alloy serves as a metal target to form a conductive layer 11 in the metal wire (wherein the conductivity of the conductive layer 11 is determined by the copper alloy).
  • the thickness of the conductive layer 11 is After the conductive layer 11 is formed, after treatment, a uniform layer of chromium- and zirconium-rich precipitates is formed on the surface of the conductive layer 11 (including the upper and lower surfaces, in this embodiment, for example, the upper surface).
  • the protective conductive layer 11 is protected from external oxygen and the roughness of the surface is improved.
  • the precipitate layer 111 is mainly formed of precipitates in the conductive layer 11, for example, the precipitate layer 111 includes CrCu 2 (Zr) accompanied by a small amount of Cu 5 Cr. Since the precipitate layer 111 includes chromium and zirconium, it is proved that the content of chromium and zirconium originally contained in the conductive layer 11 is reduced, and precipitation of precipitates is accompanied by a decrease in particles inside the conductive layer 11, which makes the copper alloy The conductivity is improved (the conductivity of copper is lowered when other alloys are added, and the conductivity of the copper alloy is restored when some other substances in the copper alloy are precipitated). In this embodiment, it is determined by the test when precipitation When precipitated, the conductivity of the copper alloy can be restored to 92% IACS (pure copper is greater than 98% IACS).
  • the metal wire further includes a molybdenum Mo alloy containing zirconium element, for example, the molybdenum alloy (including zirconium element, mentioned below)
  • the molybdenum alloy is a molybdenum alloy containing zirconium elements, except for the others, and the zirconium content is 0.25-0.35% by weight.
  • the molybdenum alloy serves as a metal target to form a bottom layer 12 of the metal wire to which the lower surface of the conductive layer 11 is attached (the thickness of the bottom layer 12 is ).
  • the conductive layer 11 and the bottom layer 12 can be better at the cross-line. Ground contact.
  • the metal wire includes the following film layers:
  • the conductive layer 11 is composed of a copper alloy containing chromium and zirconium elements
  • the underlayer 12 is bonded to the lower surface of the conductive layer 11 and is made of a zirconium-containing molybdenum alloy.
  • a precipitate layer 111 formed on the upper surface of the conductive layer 11 is further included, and the precipitate layer 111 is composed of precipitates of the conductive layer 11.
  • the deposit layer 111 is present on the upper surface of the conductive layer 11, and the conductive layer 11 is well protected from external oxygen. Therefore, in the embodiment, the double layer structure is selected to prevent the copper surface. Oxidation problem occurs, and the use of a two-layer structure also improves the stability of the etching, and since the surface of the film layer is the precipitate layer 111, the adhesion of the upper film layer to the photoresist in the prior art is better solved. The problem.
  • the source 2 and the drain 3 formed are formed to have a structure in which the metal wire is formed due to easy contact with air.
  • the gate electrode 1 can be formed by conventional metal film layer deposition.
  • the gate electrode 1 since the existence of the gate insulating layer is considered, the gate electrode 1 has a two-layer structure.
  • the conductive layer in the gate 1 may be formed by a conventional metal target (which may also be formed by using the alloy target provided by the present disclosure), and the bottom layer 12 of the metal wire in the above embodiment is selected as the bottom layer.
  • the gate insulating layer is at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, and a titanium oxide film. Adjacent to the gate insulating layer is an active layer, and the active layer is deposited using indium gallium zinc oxide.
  • the film structure in the metal wires described in the above embodiments is selected, that is, the conductive layers of the source 2 and the drain 3 are selected from the conductive layer 11 in the above embodiment, and the conductive layer 11 is used.
  • the upper surface includes a precipitate layer 111; the bottom layer of the source electrode 2 and the drain electrode 3 is selected from the bottom layer 12 of the metal wires described in the above embodiments.
  • an embodiment of the present disclosure further provides a method for fabricating a thin film transistor, which is mainly applied to the thin film transistor described in any of the above embodiments, which comprises forming a copper alloy containing chromium and zirconium elements.
  • a step of forming a precipitate layer 111 on the upper surface of the conductive layer 11 is as follows:
  • S101 is solid-solved, and the substrate carrying the conductive layer 11 is solution-treated at a temperature of 280-350 ° C for 20 min to 40 min. For example, it is solution treated for 30 min.
  • S102 is aged, and the substrate carrying the conductive layer 11 is subjected to aging treatment for 20 min to 40 min when the furnace is cooled to 150-200 ° C. For example, it is aged for 30 minutes.
  • the step of solid solution and aging causes the conductive layer 11 to form a precipitate on the surface after a certain treatment, and the step of cooling causes the precipitate to rapidly solidify to form the precipitate layer 111.
  • the conductive layer 11 is precipitated to form a precipitate layer 111, and the conductivity of the conductive layer 11 is ensured, and the conductive layer 11 is better due to the presence of the precipitate layer 111. protection of.
  • an array substrate comprising the thin film transistor according to any of the above embodiments, for example, an alloyed high conductivity, high toughness TFT.
  • a display device comprising the array substrate as described in any of the above embodiments.
  • the display device refers to a device for obtaining information by a person through visual perception.
  • the display device naturally inherits all the advantages of the array substrate, and may be a single display panel, such as a display panel for mounting on a screen of a computer; Further, the display device may be any product or component having a display function such as an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
  • the embodiment of the present disclosure forms a conductive layer by using a copper alloy, and forms a precipitate layer on the upper surface after a certain treatment process, and forms a bottom layer by using a molybdenum alloy, thereby achieving high conductivity and high toughness to a certain extent. Effectively reducing power consumption increases the response time of the display panel, ensuring display performance and display stability, while simplifying the metal film structure, reducing the complexity of the overall manufacturing of the corresponding device or system, and effectively saving costs.
  • the present disclosure has the following advantages:
  • the metal wire provided by the embodiment of the present disclosure includes a copper alloy containing chromium and zirconium, wherein since chromium and zirconium have a high corrosion potential, the copper potential is increased after the copper is added, thereby improving the resistance of the copper. Oxidation ability.
  • the copper alloy forms a conductive layer in the metal wire, and the conductive layer precipitates a precipitate on the upper surface thereof to form a precipitate layer. Due to the formation of the precipitate layer, the reaction between the metal wire and the oxygen is due to the first contact The precipitate layer provides a strong protective effect on the conductive layer.
  • the metal wire further comprises a bottom layer, wherein the bottom layer is formed of a molybdenum alloy, and the molybdenum alloy comprises a zirconium element, and the zirconium has higher toughness and can reduce the stacking fault energy of the alloy, that is, soften the metal. It gives it a higher toughness and metal wires for better performance.
  • the above-mentioned metal wires are used, which naturally inherits all the advantages of the metal wires.
  • the source and the drain are formed by the metal wire, which may have a two-layer structure, which improves the stability of etching and the efficiency of production.
  • the step of forming the conductive layer in the metal wire in the step of forming a precipitate layer on the surface of the conductive layer, by solute aging treatment of the substrate carrying the conductive layer, copper is The alloy is used as a target to form a precipitate of conductive chromatography, which is cooled to form a solidified precipitate layer; due to the solid solution and aging treatment by the method, the internal particles are reduced, and the conductivity of the copper alloy is improved; The precipitates quickly solidify on the surface of the film formed by the copper alloy, enhancing the protection of the thin film transistor.
  • the array substrate provided by the embodiment of the present disclosure is formed by using the above-described thin film transistor, and therefore, the array naturally inherits all the advantages of the thin film transistor.
  • the display device provided by the embodiment of the present disclosure may be a display panel, which is fabricated by using the above array substrate; in addition, the display device may also be a device with a display panel.
  • the embodiments of the present disclosure can not only achieve high conductivity and high toughness to a certain extent, but also reduce power consumption more effectively, improve response time of the display panel, ensure display effect and display stability, and simplify metal film structure and reduce The complexity of the overall fabrication of the corresponding device or system and the effective cost savings.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

Des modes de réalisation de la présente invention concernent un fil métallique, un transistor à couches minces et un procédé de fabrication de celui-ci, un substrat de réseau et un dispositif d'affichage. Le fil métallique est appliqué au transistor à couches minces, et comprend un alliage de cuivre contenant du chrome et du zirconium. Selon la présente invention, au moyen de la formation d'une couche conductrice à l'aide de l'alliage de cuivre, la formation d'une couche de précipité sur une surface supérieure de celle-ci après traitement au moyen d'un certain processus, et la formation d'une couche de base à l'aide d'un alliage de molybdène, non seulement une conductivité élevée et une ténacité élevée peuvent être obtenues dans une certaine mesure, la consommation d'énergie peut être réduite de manière plus efficace et le temps de réponse d'un panneau d'affichage est amélioré, et peut afficher des effets et la stabilité d'affichage est assurée, mais une structure de film métallique peut également être simplifiée, la complexité de fabrication globale d'un dispositif ou d'un système correspondant peut être réduite, et les coûts peuvent être efficacement réduits.
PCT/CN2018/086560 2017-05-25 2018-05-11 Fil métallique, transistor à couches minces et son procédé de fabrication, substrat de réseau et dispositif d'affichage WO2018214758A1 (fr)

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CN201710379101.8A CN107204320B (zh) 2017-05-25 2017-05-25 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置
CN201710379101.8 2017-05-25

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CN107204320B (zh) * 2017-05-25 2019-11-29 京东方科技集团股份有限公司 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置
CN110085602A (zh) 2019-04-22 2019-08-02 武汉华星光电半导体显示技术有限公司 金属配线膜及其制作方法、薄膜晶体管

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102314271A (zh) * 2010-07-07 2012-01-11 宸鸿科技(厦门)有限公司 一种电容式触控图形结构及其制法、触控面板及触控显示装置
EP3064604A1 (fr) * 2013-11-01 2016-09-07 AutoNetworks Technologies, Ltd. Fil d'alliage de cuivre, fil multibrin d'alliage de cuivre, fil électrique enrobé, faisceau de fils et procédé de fabrication de fil d'alliage de cuivre
CN106086511A (zh) * 2016-08-10 2016-11-09 安徽晋源铜业有限公司 一种高性能铜导线及其制备方法
CN106544533A (zh) * 2014-11-11 2017-03-29 芜湖市民泰铜业有限责任公司 一种高强高导导线用铜合金的制备方法
CN107204320A (zh) * 2017-05-25 2017-09-26 京东方科技集团股份有限公司 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1195395C (zh) * 2001-01-30 2005-03-30 日鉱金属股份有限公司 积层板用铜合金箔
US6727593B2 (en) * 2001-03-01 2004-04-27 Kabushiki Kaisha Toshiba Semiconductor device with improved bonding
JP3731600B2 (ja) * 2003-09-19 2006-01-05 住友金属工業株式会社 銅合金およびその製造方法
CN104701384A (zh) * 2015-04-09 2015-06-10 京东方科技集团股份有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN105112720A (zh) * 2015-09-08 2015-12-02 周欢 一种用于导线的铜合金

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102314271A (zh) * 2010-07-07 2012-01-11 宸鸿科技(厦门)有限公司 一种电容式触控图形结构及其制法、触控面板及触控显示装置
EP3064604A1 (fr) * 2013-11-01 2016-09-07 AutoNetworks Technologies, Ltd. Fil d'alliage de cuivre, fil multibrin d'alliage de cuivre, fil électrique enrobé, faisceau de fils et procédé de fabrication de fil d'alliage de cuivre
CN106544533A (zh) * 2014-11-11 2017-03-29 芜湖市民泰铜业有限责任公司 一种高强高导导线用铜合金的制备方法
CN106086511A (zh) * 2016-08-10 2016-11-09 安徽晋源铜业有限公司 一种高性能铜导线及其制备方法
CN107204320A (zh) * 2017-05-25 2017-09-26 京东方科技集团股份有限公司 金属导线、薄膜晶体管及制作方法、阵列基板和显示装置

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