WO2018195420A1

WO2018195420A1 - Methods and structures to reduce contact resistance for finfet devices

Info

Publication number: WO2018195420A1
Application number: PCT/US2018/028563
Authority: WO
Inventors: Gaurav THAREJA; Gill Lee
Original assignee: Micromaterials Llc
Priority date: 2017-04-20
Filing date: 2018-04-20
Publication date: 2018-10-25
Also published as: TW201903841A; TWI778048B

Abstract

Processing methods may be performed to form semiconductor structures that may include structures to reduce contact resistance. The methods may include depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on a first silicon-containing material relative to a second silicon-containing material. The methods may also include depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.

Description

METHODS AND STRUCTURES TO REDUCE CONTACT RESISTANCE

FOR FINFET DEVICES

RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 62/487,662, filed April 20, 2017, the disclosure of which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL FIELD

[0002] The present technology relates to semiconductor systems, processes, and equipment. More specifically, the present technology relates to systems and methods for selectively forming material layers on a semiconductor device.

BACKGROUND

[0003] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers, or thinning lateral dimensions of features already present on the surface. Often it is desirable to have an etch process that etches one material faster than another facilitating, for example, a pattern transfer process or individual material removal. Such an etch process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etch processes have been developed with a selectivity towards a variety of materials. Deposition processes, however, continue to be performed across substrates generally utilizing a blanket coat or a conformal fill. [0004] As device sizes continue to shrink in next-generation devices, selectivity may play a larger role when only a few nanometers of material are formed in a particular layer, especially when the material is critical in the transistor formation. Many different etch process selectivities have been developed between various materials, although standard selectivities may no longer be suitable at current and future device scale. Additionally, queue times for processes continue to rise based on the number of masking, formation, and removal operations needed to form and protect the various critical dimensions of features across a device while patterning and formation are performed elsewhere on a substrate. [0005] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.

SUMMARY

[0006] Processing methods may be performed to form semiconductor structures that may include structures to reduce contact resistance. The methods may include depositing a first semiconductor material on a semiconductor substrate. The first semiconductor material may be selectively deposited on a first silicon-containing material relative to a second silicon-containing material. The methods may also include depositing a second semiconductor material on the semiconductor substrate. The second semiconductor material may be selectively deposited on the second silicon-containing material relative to the first semiconductor material.

[0007] In some embodiments, the first semiconductor material may be deposited on a PMOS region of the semiconductor substrate relative to an MOS region of the semiconductor substrate. The first semiconductor material may include germanium, and the first silicon- containing material may include silicon germanium. The second silicon-containing material may include phosphorous. The method may be performed without conducting a reactive ion etching operation. The first semiconductor material deposition may be performed with a selectivity towards the first silicon-containing material relative to the second silicon-containing material greater than or about 2: 1. The deposition may occur on an NMOS region of the semiconductor substrate relative to a PMOS region of the semiconductor substrate. The method may be performed without forming a photoresist over the PMOS region. The first semiconductor material may include indium, and the first silicon-containing material may include silicon phosphide. The second silicon-containing material may include germanium. The first semiconductor material may be or include indium gallium arsenide.

[0008] The present technology additionally includes methods of forming a semiconductor structure. The methods may include depositing a first alloy material over a first semiconductor material. The alloy material may be selectively deposited on the first semiconductor material relative to a nitride material or an oxide material. The methods may also include subsequently depositing a second alloy material over a second semiconductor material. The second alloy material may be selectively deposited on the second semiconductor material relative to the nitride material or the oxide material.

[0009] In some embodiments, the first alloy material may be deposited on an indium- containing material located in an MOS region of the semiconductor substrate. The second alloy material may be deposited on a germanium-containing material located in a PMOS region of the semiconductor substrate. The nitride material may include silicon nitride, and the oxide material may include silicon oxide, silicon oxycarbide, or a metal oxide. The metal oxide may be or include tungsten oxide or aluminum oxide. The method may be performed without conducting a reactive ion etching operation. The second alloy material may be or include a nickel-containing material. The second alloy material may be or include nickel silicon germanium. The first alloy material may be or include a titanium-containing material. The first alloy material may be or include titanium silicon nitride.

[0010] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes may protect critical dimensions by utilizing techniques that do not include a reactive ion etch, and provide improved selectivity. Additionally, by performing selective operations, fewer masking and removal operations may be performed, which may reduce fabrication queue times dramatically. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0012] FIG. 1 shows a top plan view of an exemplary processing system according to embodiments of the present technology. [0013] FIG. 2A shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0014] FIG. 2B shows a detailed view of an exemplary faceplate according to embodiments of the present technology. [0015] FIG. 3 shows a bottom plan view of an exemplary showerhead according to

embodiments of the present technology.

[0016] FIG. 4 shows a schematic cross-sectional view of an exemplary processing chamber according to embodiments of the present technology.

[0017] FIG. 5 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology.

[0018] FIGS. 6A-6B show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.

[0019] FIG. 7 shows selected operations in a method of forming a semiconductor structure according to embodiments of the present technology. [0020] FIGS. 8A-8B show schematic cross-sectional views of exemplary substrates according to embodiments of the present technology.

[0021] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes, and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations, and may include exaggerated material for illustrative purposes.

[0022] In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter. DETAILED DESCRIPTION

[0023] The present technology includes systems and components for semiconductor processing of small pitch features. In traditional silicidation processes, the PMOS region and the NMOS region may be blocked with photoresist while the other region is processed. Because several materials across the substrate may be formed of similar materials, such as silicon nitride or oxide, for example, the etching processes to remove these materials as well as materials formed within the regions may not provide sufficient selectivity relative to other critical features.

During various opening processes, the multiple critical dimension sizes may cause a loading effect to etch beyond budget availability of material. For example, traditional processes may include a mask layer followed by a reactive-ion etch ("RIE") process that allows opening of the structure for a gap fill layer. Despite being a relatively anisotropic process, the RIE etch may still have selectivity causing sidewall losses. Although budgeting for this loss may be considered during formation, such as with over-formation of material, because regions within the structure being etched have different dimensions, calculating for the amount of loss in one area may not be suitable for the amount of loss in a larger area. Accordingly, although 5 nm of loss may occur in one section that is budgeted, loss in a larger section of 6-7 nm may still occur, causing mismatches during fabrication.

[0024] Additionally, RIE processes produce an etch byproduct or polymer residue that is generally removed with a wet etching process. This wet etch often over-etches sidewall protection layers beyond critical dimensions, which can cause problems with formation and spacing of adjacent transistor layers, and further etches low-k nitride spacers and inter-layer dielectric oxide. Moreover, the removal of metal materials and dielectrics is often performed with an anisotropic etch that may further reduce exposed regions of cap materials and spacer materials in other regions, unless additional masking or protective layers are formed. Because the selectivity of such RIE removal may be in the range of 10: 1, the amount of masking required may be substantial.

[0025] Deposition of both masking material and other material layers may be performed in conventional technologies that utilizes either a blanket coating of material or a conformal development of material across all exposed areas on a semiconductor substrate. These types of deposition may require further patterning and removal operations that can substantially increase queue times for the device fabrication. Between the additional operations and deficiencies of RIE removal, and the multiple operations utilized in conventional deposition, queue times may be increased by hours for individual device layers.

[0026] The present technology overcomes these issues by modifying the processes for removal and formation. By performing selective deposition operations in particular equipment, reduced masking, patterning, and removal may be utilized in the structure formation. Additionally, removal operations that may be performed may be done selectively as well. By removing many of the patterning operations by using selective deposition and utilizing alternative etching, these processes may save hours over conventional processes utilizing RIE and standard deposition. [0027] Although the remaining disclosure will routinely identify specific etching and deposition processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to a variety of other etching, deposition, and cleaning processes as may occur in the described chambers. Accordingly, the technology should not be considered to be so limited as for use with the described etching and deposition processes alone. The disclosure will discuss one possible system and chambers that can be used with the present technology to perform certain of the removal and deposition operations before describing operations of an exemplary process sequence according to the present technology.

[0028] FIG. 1 shows a top plan view of one embodiment of a processing system 100 of deposition, etching, baking, and curing chambers according to embodiments. In the figure, a pair of front opening unified pods (FOUPs) 102 supply substrates of a variety of sizes that are received by robotic arms 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f, positioned in tandem sections 109a- c. A second robotic arm 1 10 may be used to transport the substrate wafers from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f, can be outfitted to perform a number of substrate processing operations including the dry etch processes and selective deposition described herein in addition to cyclical layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), wet etch, pre-clean, degas, orientation, and other substrate processes.

[0029] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and/or etching a dielectric film on the substrate wafer. In one configuration, two pairs of the processing chambers, e.g., 108c-d and 108e-f, may be used to deposit dielectric material or metal-containing material on the substrate, and the third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on the substrate. Any one or more of the processes described may be carried out in chamber(s) separated from the fabrication system shown in different embodiments.

[0030] In some embodiments the chambers specifically include at least one etching chamber as described below as well as at least one deposition chamber as described below. By including these chambers in combination on the processing side of the factory interface, all etching and deposition processes discussed below may be performed in a controlled environment. For example, a vacuum environment may be maintained on the processing side of holding area 106, so that all chambers and transfers are maintained under vacuum in embodiments. This may also limit water vapor and other air components from contacting the substrates being processed. It will be appreciated that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are contemplated by system 100.

[0031] FIG. 2A shows a cross-sectional view of an exemplary process chamber system 200 with partitioned plasma generation regions within the processing chamber. During film etching, e.g., titanium nitride, tantalum nitride, tungsten, cobalt, aluminum oxide, tungsten oxide, silicon, poly silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxy carbide, etc., a process gas may be flowed into the first plasma region 215 through a gas inlet assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system, and may process a first gas which then travels through gas inlet assembly 205. The inlet assembly 205 may include two or more distinct gas supply channels where the second channel (not shown) may bypass the RPS 201, if included. [0032] A cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, and a substrate support 265, having a substrate 255 disposed thereon, are shown and may each be included according to embodiments. The pedestal 265 may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate, which may be operated to heat and/or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated in order to achieve relatively high temperatures, such as from up to or about 100°C to above or about 1100°C, using an embedded resistive heater element.

[0033] The faceplate 217 may be pyramidal, conical, or of another similar structure with a narrow top portion expanding to a wide bottom portion. The faceplate 217 may additionally be flat as shown and include a plurality of through-channels used to distribute process gases.

Plasma generating gases and/or plasma excited species, depending on use of the RPS 201, may pass through a plurality of holes, shown in FIG. 2B, in faceplate 217 for a more uniform delivery into the first plasma region 215. [0034] Exemplary configurations may include having the gas inlet assembly 205 open into a gas supply region 258 partitioned from the first plasma region 215 by faceplate 217 so that the gases/species flow through the holes in the faceplate 217 into the first plasma region 215.

Structural and operational features may be selected to prevent significant backflow of plasma from the first plasma region 215 back into the supply region 258, gas inlet assembly 205, and fluid supply system 210. The faceplate 217, or a conductive top portion of the chamber, and showerhead 225 are shown with an insulating ring 220 located between the features, which allows an AC potential to be applied to the faceplate 217 relative to showerhead 225 and/or ion suppressor 223. The insulating ring 220 may be positioned between the faceplate 217 and the showerhead 225 and/or ion suppressor 223 enabling a capacitively coupled plasma (CCP) to be formed in the first plasma region. A baffle (not shown) may additionally be located in the first plasma region 215, or otherwise coupled with gas inlet assembly 205, to affect the flow of fluid into the region through gas inlet assembly 205.

[0035] The ion suppressor 223 may comprise a plate or other geometry that defines a plurality of apertures throughout the structure that are configured to suppress the migration of ionically- charged species out of the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 into an activated gas delivery region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may comprise a perforated plate with a variety of aperture configurations. These uncharged species may include highly reactive species that are transported with less reactive carrier gas through the apertures. As noted above, the migration of ionic species through the holes may be reduced, and in some instances completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 may advantageously provide increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn may increase control of the deposition and/or etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can significantly alter its etch selectivity, e.g., SiNx:SiOx etch ratios, Si:SiOx etch ratios, etc. In alternative embodiments in which deposition is performed, it can also shift the balance of conformal-to-flowable style depositions for dielectric materials.

[0036] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor 223. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor 223 is reduced. The holes in the ion suppressor 223 may include a tapered portion that faces the plasma excitation region 215, and a cylindrical portion that faces the showerhead 225. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead 225. An adjustable electrical bias may also be applied to the ion suppressor 223 as an additional means to control the flow of ionic species through the suppressor.

[0037] The ion suppressor 223 may function to reduce or eliminate the amount of ionically charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may still pass through the openings in the ion suppressor to react with the substrate. It should be noted that the complete elimination of ionically charged species in the reaction region surrounding the substrate may not be performed in embodiments. In certain instances, ionic species are intended to reach the substrate in order to perform the etch and/or deposition process. In these instances, the ion suppressor may help to control the concentration of ionic species in the reaction region at a level that assists the process.

[0038] Showerhead 225 in combination with ion suppressor 223 may allow a plasma present in first plasma region 215 to avoid directly exciting gases in substrate processing region 233, while still allowing excited species to travel from chamber plasma region 215 into substrate processing region 233. In this way, the chamber may be configured to prevent the plasma from contacting a substrate 255 being etched. This may advantageously protect a variety of intricate structures and films patterned on the substrate, which may be damaged, dislocated, or otherwise warped if directly contacted by a generated plasma. Additionally, when plasma is allowed to contact the substrate or approach the substrate level, the rate at which oxide species etch may increase. Accordingly, if an exposed region of material is oxide, this material may be further protected by maintaining the plasma remotely from the substrate.

[0039] The processing system may further include a power supply 240 electrically coupled with the processing chamber to provide electric power to the faceplate 217, ion suppressor 223, showerhead 225, and/or pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to deliver an adjustable amount of power to the chamber depending on the process performed. Such a configuration may allow for a tunable plasma to be used in the processes being performed. Unlike a remote plasma unit, which is often presented with on or off functionality, a tunable plasma may be configured to deliver a specific amount of power to the plasma region 215. This in turn may allow

development of particular plasma characteristics such that precursors may be dissociated in specific ways to enhance the etching profiles produced by these precursors.

[0040] A plasma may be ignited either in chamber plasma region 215 above showerhead 225 or substrate processing region 233 below showerhead 225. In embodiments, the plasma formed in substrate processing region 233 may be a DC biased plasma formed with the pedestal acting as an electrode. Plasma may be present in chamber plasma region 215 to produce the radical precursors from an inflow of, for example, a fluorine-containing precursor or other precursor. An AC voltage typically in the radio frequency (RF) range may be applied between the conductive top portion of the processing chamber, such as faceplate 217, and showerhead 225 and/or ion suppressor 223 to ignite a plasma in chamber plasma region 215 during deposition. An RF power supply may generate a high RF frequency of 13.56 MHz but may also generate other frequencies alone or in combination with the 13.56 MHz frequency.

[0041] FIG. 2B shows a detailed view 253 of the features affecting the processing gas distribution through faceplate 217. As shown in FIGS. 2A and 2B, faceplate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas supply region 258 into which process gases may be delivered from gas inlet 205. The gases may fill the gas supply region 258 and flow to first plasma region 215 through apertures 259 in faceplate 217. The apertures 259 may be configured to direct flow in a substantially unidirectional manner such that process gases may flow into processing region 233, but may be partially or fully prevented from backflow into the gas supply region 258 after traversing the faceplate 217.

[0042] The gas distribution assemblies such as showerhead 225 for use in the processing chamber section 200 may be referred to as dual channel showerheads (DCSH) and are additionally detailed in the embodiments described in FIG. 3. The dual channel showerhead may provide for etching processes that allow for separation of etchants outside of the processing region 233 to provide limited interaction with chamber components and each other prior to being delivered into the processing region. [0043] The showerhead 225 may comprise an upper plate 214 and a lower plate 216. The plates may be coupled with one another to define a volume 218 between the plates. The coupling of the plates may be so as to provide first fluid channels 219 through the upper and lower plates, and second fluid channels 221 through the lower plate 216. The formed channels may be configured to provide fluid access from the volume 218 through the lower plate 216 via second fluid channels 221 alone, and the first fluid channels 219 may be fiuidly isolated from the volume 218 between the plates and the second fluid channels 221. The volume 218 may be fiuidly accessible through a side of the gas distribution assembly 225.

[0044] FIG. 3 is a bottom view of a showerhead 325 for use with a processing chamber according to embodiments. Showerhead 325 may correspond with the showerhead 225 shown in FIG. 2A. Through-holes 365, which show a view of first fluid channels 219, may have a plurality of shapes and configurations in order to control and affect the flow of precursors through the showerhead 225. Small holes 375, which show a view of second fluid channels 221, may be distributed substantially evenly over the surface of the showerhead, even amongst the through-holes 365, and may help to provide more even mixing of the precursors as they exit the showerhead than other configurations.

[0045] Turning to FIG. 4 is shown a schematic cross-sectional view of an atomic layer deposition system 400 or reactor in accordance with one or more embodiments of the present technology. The system 400 may include a load lock chamber 10 and a processing chamber 20. The processing chamber 20 may be generally a sealable enclosure, which may be operated under vacuum, or at least low pressure. The processing chamber 20 may be isolated from the load lock chamber 10 by an isolation valve 15. The isolation valve 15 may seal the processing chamber 20 from the load lock chamber 10 in a closed position and may allow a substrate 60 to be transferred from the load lock chamber 10 through the valve to the processing chamber 20 and vice versa in an open position. [0046] The system 400 may include a gas distribution plate 30 capable of distributing one or more gases across a substrate 60. The gas distribution plate 30 may be any suitable distribution plate known to those skilled in the art, and specific gas distribution plates described should not be taken as limiting the scope of the technology. The output face of the gas distribution plate 30 may face the first surface 61 of the substrate 60. [0047] The gas distribution plate 30 may include a plurality of gas ports configured to transmit one or more gas streams to the substrate 60 and a plurality of vacuum ports disposed between each gas port and configured to transmit the gas streams out of the processing chamber 20. As illustrated in FIG. 4, the gas distribution plate 30 may include a first precursor injector 420, a second precursor injector 430 and a purge gas injector 440. The injectors 420, 430, 440 may be controlled by a system computer (not shown), such as a mainframe, or by a chamber-specific controller, such as a programmable logic controller. The precursor injector 420 may be configured to inject a continuous or pulse stream of a reactive precursor of compound A into the processing chamber 20 through a plurality of gas ports 425. The precursor injector 430 may be configured to inject a continuous or pulse stream of a reactive precursor of compound B into the processing chamber 20 through a plurality of gas ports 435. The purge gas injector 440 may be configured to inject a continuous or pulse stream of a non-reactive or purge gas into the processing chamber 20 through a plurality of gas ports 445. The purge gas may be configured to remove reactive material and reactive by-products from the processing chamber 20. The purge gas may typically be an inert gas, such as nitrogen, argon or helium. Gas ports 445 may be disposed in between gas ports 425 and gas ports 435 so as to separate the precursor of compound A from the precursor of compound B, thereby avoiding cross-contamination between the precursors.

[0048] In another aspect, a remote plasma source (not shown) may be connected to the precursor injector 420 and the precursor injector 430 prior to injecting the precursors into the processing chamber 20. The plasma of reactive species may be generated by applying an electric field to a compound within the remote plasma source. Any power source that is capable of activating the intended compounds may be used. For example, power sources using DC, radio frequency, and microwave based discharge techniques may be used. If an RF power source is used, it can be either capacitively or inductively coupled. The activation may also be generated by a thermally based technique, a gas breakdown technique, a high intensity light source, such as ultraviolet light, or exposure to an x-ray source.

[0049] The system 400 may further include a pumping system 450 connected to the processing chamber 20. The pumping system 450 may be generally configured to evacuate the gas streams out of the processing chamber 20 through one or more vacuum ports 455. The vacuum ports 455 may be disposed between each gas port so as to evacuate the gas streams out of the processing chamber 20 after the gas streams react with the substrate surface and to further limit cross- contamination between the precursors.

[0050] The system 400 may include a plurality of partitions 460 disposed on the processing chamber 20 between each port. A lower portion of each partition may extend close to the first surface 61 of substrate 60, such as, for example, about 0.5 mm or greater from the first surface 61. In this manner, the lower portions of the partitions 460 may be separated from the substrate surface by a distance sufficient to allow the gas streams to flow around the lower portions toward the vacuum ports 455 after the gas streams react with the substrate surface. Arrows 498 indicate the direction of the gas streams. Since the partitions 460 may operate as a physical barrier to the gas streams, they may also limit cross contamination between the precursors. The arrangement shown is merely illustrative and should not be taken as limiting the scope of the technology. It will be understood by those skilled in the art that the gas distribution system shown is merely one possible distribution system and that other types of showerheads may be employed.

[0051] In operation, a substrate 60 may be delivered, such as by a robot, to the load lock chamber 10 and may be placed on a shuttle 65. After the isolation valve 15 is opened, the shuttle 65 may be moved along the track 70. Once the shuttle 65 enters in the processing chamber 20, the isolation valve 15 may close, sealing the processing chamber 20. The shuttle 65 may then be moved through the processing chamber 20 for processing. In one embodiment, the shuttle 65 may be moved in a linear path through the chamber. [0052] As the substrate 60 moves through the processing chamber 20, the first surface 61 of substrate 60 may be repeatedly exposed to the precursor of compound A coming from gas ports 425 and the precursor of compound B coming from gas ports 435, with the purge gas coming from gas ports 445 in between. Injection of the purge gas may be designed to remove unreacted material from the previous precursor prior to exposing the substrate surface 61 to the next precursor. After each exposure to the various gas streams, the gas streams may be evacuated through the vacuum ports 455 by the pumping system 450. Since a vacuum port may be disposed on both sides of each gas port, the gas streams may be evacuated through the vacuum ports 455 on both sides. Thus, the gas streams may flow from the respective gas ports vertically downward toward the first surface 61 of the substrate 60, across the first surface 410 and around the lower portions of the partitions 460, and finally upward toward the vacuum ports 455. In this manner, each gas may be uniformly distributed across the substrate surface 61. Substrate 60 may also be rotated while being exposed to the various gas streams. Rotation of the substrate may be useful in preventing the formation of strips in the formed layers. Rotation of the substrate may be continuous or in discreet steps.

[0053] The extent to which the substrate surface 61 is exposed to each gas may be determined by, for example, the flow rates of each gas coming out of the gas port and the rate of movement of the substrate 60. In one embodiment, the flow rates of each gas may be configured so as not to remove adsorbed precursors from the substrate surface 61. The width between each partition, the number of gas ports disposed on the processing chamber 20, and the number of times the substrate may be passed back and forth may also determine the extent to which the substrate surface 61 is exposed to the various gases. Consequently, the quantity and quality of a deposited film may be optimized by varying the above-referenced factors.

[0054] In another embodiment, the system 400 may include a precursor injector 420 and a precursor injector 430, without a purge gas injector 440. Consequently, as the substrate 60 moves through the processing chamber 20, the substrate surface 61 may be alternately exposed to the precursor of compound A and the precursor of compound B, without being exposed to purge gas in between.

[0055] The embodiment shown in FIG. 4 has the gas distribution plate 30 above the substrate. While the embodiments have been described and shown with respect to this upright orientation, it will be understood that the inverted orientation is also possible. In that situation, the first surface 61 of the substrate 60 may face downward, while the gas flows toward the substrate may be directed upward. In one or more embodiments, at least one radiant heat source 90 may be positioned to heat the second side of the substrate. [0056] In some embodiments, the shuttle 65 may be susceptor 66 for carrying the substrate 60. Generally, the susceptor 66 may be a carrier which helps to form a uniform temperature across the substrate. The susceptor 66 may be movable in both directions left-to-right and right-to-left, relative to the arrangement of FIG. 4, between the load lock chamber 10 and the processing chamber 20. The susceptor 66 may have a top surface 67 for carrying the substrate 60. The susceptor 66 may be a heated susceptor so that the substrate 60 may be heated for processing. As an example, the susceptor 66 may be heated by radiant heat source 90, a heating plate, resistive coils, or other heating devices, disposed underneath the susceptor 66. Although illustrated as a lateral transition, embodiments of system 400 may also be utilized in a rotationally based system in which a wheel may rotate clockwise or counter-clockwise to successively treat one or more substrates positioned under the gas distribution system illustrated. Additional modifications are similarly understood to be encompassed by the present technology.

[0057] FIG. 5 illustrates a method 500 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. The method may include aspects of epitaxial growth on MOS and PMOS regions of a substrate. Method 500 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations, which may or may not be specifically associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 500 describes the operations shown schematically in FIGS. 6A-6B, the illustrations of which will be described in conjunction with the operations of method 500. It is to be understood that FIG. 6 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures. [0058] FIG. 7 illustrates a method 700 of forming a semiconductor structure, many operations of which may be performed, for example, in the chambers 200 and 400 as previously described. The method may include aspects of silicidation on MOS and PMOS regions of a substrate. The method may include aspects of epitaxial growth on source drain regions. Method 700 may include one or more operations prior to the initiation of the method, including front end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to the described operations. The method may include a number of optional operations, which may or may not be specifically associated with the method according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as will be discussed further below. Method 700 describes the operations shown schematically in FIGS. 8A-8B, the illustrations of which will be described in conjunction with the operations of method 700. It is to be understood that FIG. 8 illustrates only partial schematic views, and a substrate may contain any number of transistor sections having aspects as illustrated in the figures. It is to be understood that methods 500 and 700 are exemplary only, and in embodiments either N-region or P-region may be processed first. Both processing ways are encompassed by the present technology.

[0059] Method 500 may involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing a transistor structure. As illustrated in FIG. 6A, a portion of a processed substrate 600 is shown including a substrate 605, a p-region source and drain 610, an n-region source and drain 615, metal gates 620, cap layers 625, and gate spacers 630. The materials may have been formed in prior operations, and may have been polished, etched, or processed to produce the illustrated structure. The operations of method 500 may be performed to limit or eliminate masking operations, RTE processes including ashing and cleaning, and may reduce process queue times for providing an epitaxial material during production of structures to reduce contact resistance in the NMOS and PMOS regions of the structure.

[0060] Method 700 may also involve operations performed on a substrate having multiple exposed regions, such as on a substrate including regions to be further developed in producing a transistor structure. As illustrated in FIG. 8A, a portion of a processed substrate 600 is shown including a substrate 605, a p-region source and drain 610, an n-region source and drain 615, metal gates 620, cap layers 625, and gate spacers 630. The structure may also include a first semiconductor material 635 and a second semiconductor material 640 as formed during method 500, for example. The materials may have been formed in prior operations, and may have been polished, etched, or processed to produce the illustrated structure. The operations of method 700 may be performed to limit or eliminate masking operations, RTE processes including ashing and cleaning, and may reduce process queue times for providing silicidation material during production of structures to reduce contact resistance in the MOS and PMOS regions of the structure. [0061] The materials used may be a variety of dielectric, metal, and semiconductor materials known in the art. For example, the substrate 605 may be silicon or some silicon-containing material. The p-region source and drain 610 may be formed in the PMOS region of the structure, and may be silicon germanium, or some other p-channel metal-oxide semiconductor material. The n-region source and drain 615 may be silicon phosphide, or some other n-channel metal - oxide semiconductor material. The metal gates 620 may be tungsten, cobalt, or some other conductive material. The cap material 625 may be a self-aligned contact cap, and may be silicon nitride, silicon carbide, or some oxide material including metal oxides such as tungsten oxide or aluminum oxide. The gate spacer 630 may be any dielectric material, and for example, may be a silicon-containing material, an oxygen-containing material, a carbon-containing material, or some combination, such as silicon oxycarbide, for example.

[0062] Method 500 may initially include depositing a semiconductor material 635 at operation 505 as illustrated in FIG. 6A. The semiconductor material 635 may be any known

semiconductor material, and in embodiments may be germanium that is deposited as

semiconductor material 635 because, as illustrated, it may be formed over the PMOS source and drain materials. The deposition of semiconductor material 635 may be selectively deposited on p-region source and drain sections 610, and may not be formed over any other exposed materials, including cap material 625, gate spacer 630, or any of the materials that may remain exposed in the NMOS region. In embodiments the deposition may be performed without first blocking the NMOS region, such as by forming a photoresist or hardmask. The semiconductor material 635 may be formed in any number of ways, and may be epitaxially grown with precursors in order to utilize one or more of the selective deposition operations discussed further below. For example, with an exemplary semiconductor material 635 being germanium, the process may be performed utilizing metalorganic vapor phase epitaxy using a germanium-containing precursor and a hydride, such as a metal hydride including a Group II, Group III, Group IV, or Group V metal hydride or organometal precursor, such as methylated metals, or other organic structures. The process may be performed at temperatures greater than or less than or about 500° C, and may be performed at pressures below about 1 Torr, and may be performed at pressures below or about 1 mTorr.

[0063] Method 500 may also include depositing a semiconductor material 640 at operation 510 as illustrated in FIG. 6B. The semiconductor material 640 may be any known semiconductor material, and in embodiments may be a III-V semiconductor, such as indium gallium arsenide, that is deposited as semiconductor material 640 because, as illustrated, it may be formed over the MOS source and drain materials. The deposition of semiconductor material 640 may be selectively deposited on n-region source and drain sections 615, and may not be formed over any other exposed materials, including cap material 625, gate spacer 630, or any of the materials that may remain exposed in the PMOS region. In embodiments the deposition may be performed without first blocking the PMOS region, such as by forming a photoresist or hardmask. The semiconductor material 640 may be formed in any number of ways, and may be epitaxially grown with precursors in order to utilize one or more of the selective deposition operations discussed further below. For example, with an exemplary semiconductor material 640 being indium gallium arsenide, the process may be performed utilizing metalorganic vapor phase epitaxy using an indium-containing precursor, a gallium containing precursor, and a hydride, such as a metal hydride including a Group II, Group III, Group IV, or Group V metal hydride or organometal precursor, such as methylated metals, or other organic structures. In embodiments, the additional precursor may be an arsenic-containing precursor. The process may be performed at temperatures greater than or less than or about 500° C, and may be performed at pressures below about 1 Torr, and may be performed at pressures below or about 1 mTorr.

[0064] Method 700 may include depositing a first alloy material 845 at operation 715 as illustrated in FIG. 8 A. A previous operation may occur at operation 712 in which a silicon- containing material may be formed over semiconductor material 635, for example. The silicon- containing material may be used to produce the alloy with a subsequent anneal operation. The alloy material may be any number of materials including alloys of nickel. First alloy material 845 may be formed by alloying nickel with a silicon-containing material such as silicon germanium to form nickel silicon germanium. The silicon germanium may be formed initially at operation 712, followed by an anneal with nickel. Additional secondary and tertiary nickel- containing alloys or other metal alloys may be formed as well. Nickel may be used, for example, as the material layer because, as illustrated, it may also be formed over the PMOS source and drain materials. The deposition of first alloy material 845 may be selectively deposited on first semiconductor material 635, and may not be formed over any other exposed materials, including cap material 625, gate spacer 630, or any of the materials that may remain exposed in the NMOS region. In embodiments the deposition may be performed without first blocking the NMOS region, such as by forming a photoresist or hardmask.

[0065] The alloy material may be formed in a number of ways, and may be formed by producing a first material layer followed by formation of the alloying material. In one example in which nickel silicon germanium is formed, a layer of silicon germanium may be formed followed by a layer of nickel. Additional intermediate layers may be formed as well, such as a titanium or an aluminum layer between the silicon germanium and nickel layers, in order to assist formation of the alloy. An annealing operation, such as a rapid thermal anneal may then be performed at temperatures above 400° C in order to allow the nickel to permeate the silicon germanium and form nickel silicon germanium. The process may also be performed at pressures below about 1 Torr, and may be performed at pressures below or about 1 mTorr.

[0066] Method 700 may include depositing a second alloy material 850 at operation 720 as illustrated in FIG. 8B. The alloy material may be any number of materials including alloys of titanium. Again, a second silicon-containing material may first be deposited at operation 718 for forming the alloy as noted above. Second alloy material 850 may be formed by alloying titanium with a silicon-containing material such as silicon nitride to form titanium silicon nitride. Additional secondary and tertiary titanium-containing alloys or other metal alloys may be formed as well. Titanium may be used, for example, as the material layer because, as illustrated, it may also be formed over the NMOS source and drain materials. The deposition of second alloy material 850 may be selectively deposited on second semiconductor material 640, and may not be formed over any other exposed materials, including cap material 625, gate spacer 630, or any of the materials that may remain exposed in the PMOS region.

[0067] In embodiments the deposition may be performed without first blocking the PMOS region, such as by forming a photoresist or hardmask. The alloy material may be formed in a number of ways, and may be formed by producing a first material layer followed by formation of the alloying material. In one example in which titanium silicon nitride is formed, a layer of silicon nitride may be formed followed by a layer of titanium. Again, additional intermediate layers may be formed as well as previously described. An annealing operation, such as a rapid thermal anneal may then be performed at temperatures above 400° C in order to allow the titanium to permeate the silicon nitride and form titanium silicon nitride. The process may also be performed at pressures below about 1 Torr, and may be performed at pressures below or about 1 mTorr.

[0068] Because many of the materials are positioned or formed in specific regions, the layers being deposited generally may be different from the other exposed material layers on which deposition is not to occur, or occur to a lesser degree. By depositing material layers composed of materials different from other exposed materials, a number of selective deposition techniques may be used to form one or more of the layers 635, 640, 845, and 850.

[0069] The selective deposition of any of the disclosed materials may be performed in a chamber capable of deposition, and which may be capable of atomic layer deposition, including chamber 400 as described above. The deposition may be premised on selectively depositing a metal or semiconductor material relative to dielectric or insulative materials including cap material 625 and gate spacer 630 as well as other exposed materials in the region other than in which the deposition is to occur. For example, the first semiconductor material 635, which may be germanium in some embodiments, may be formed substantially on p-region source and drain materials 610, which may be silicon germanium, while being minimally formed or limited from gate spacer 630, which may be silicon oxycarbide among other materials. The first

semiconductor material 635 may also be minimally formed or limited from nitride, carbide, or oxide cap material 625, as well as exposed materials in the MOS region, such as n-region source and drain materials 615, which may be silicon phosphide. The following selective depositions may be similarly performed to deposit more material in the intended location than over any other exposed materials, which may also include substrate 605, which may be silicon, or some other semiconductor material. The selective deposition may be performed by multiple operations, which may include formation of a self-assembled monolayer to facilitate selective deposition, or may include actively inhibiting formation of material on other dielectric materials. [0070] Self-assembled monolayers may be formed on regions of the structure to tune deposition. For example, a first self-assembled monolayer may be formed over the structure, and then exposed to a lithographic mask to remove the monolayer from whichever region is to receive the deposition, such as over p-region source and drain materials 610, or n-region source and drain materials 615. Previously formed materials in these regions may also be the target of subsequent deposition. The monolayer may be maintained over dielectric or insulative materials such as cap material 625 and gate spacer 630. The monolayer may have termination moieties that may repel or fail to interact with later delivered precursors. For example, the termination moieties may be hydrophobic in embodiments, and may terminate with hydrogen-containing moieties, such as methyl groups, which may not interact with additional precursors. A second self-assembled monolayer may be formed over the target region, such as over p-region source and drain materials 610, or n-region source and drain materials 615. This self-assembled monolayer may be hydrophilic or reactive with one or more precursors utilized to produce the specific deposition material, which may be any of the previously described materials. The second self-assembled monolayer may be formed selectively over the target region, as the material may be repelled from the first self-assembled monolayer, or may be drawn selectively to the target region. The second self-assembled monolayer may terminate with hydroxyl or other hydrophilic moieties, or with moieties that interact specifically with additional precursors used to form the specified deposition material, such as a metal or dielectric material.

[0071] An atomic layer deposition may then be performed utilizing two or more precursors to develop the deposition material, which may be any of the previously described materials for layers 635, 640, 845, 850. The precursors of the deposition may include a metal-containing or silicon-containing precursor and a precursor configured to interact with the moieties terminating the second self-assembled monolayer, but not the first self-assembled monolayer. For example, when hydrophilic and hydrophobic terminating monolayers are utilized, one of the atomic layer deposition precursors may include water. In this way, the deposition may not form over the first self-assembled monolayer, which may be hydrophobic. If the deposited material includes a metal oxide, the precursors used in the atomic layer deposition may include a specific metal- containing precursor as well as water. Once the formation is complete, the oxide may be removed to leave a metal layer, for example. In other embodiments silicon-containing precursors may be used. The water may then fail to interact with the first self-assembled monolayer formed over the other exposed materials during the half reaction with water, and thus the deposition may not form over the first self-assembled monolayer. In this way, the specific material may be selectively formed over the target region, or preferentially formed over the target region. It is to be understood that this is merely a single example, and other precursors may be used with similar operating principles in order to form the specific material previously described for each deposition region.

[0072] After the identified deposition has been formed to a suitable height, the first self- assembled monolayer may be exposed to UV light and removed from the substrate, or some other removal may be performed. In this way, multiple operations utilized in conventional formation may be obviated, which may reduce queue times significantly, such as by hours. In other embodiments a slight recess may be performed subsequent the selective deposition to remove residual material from the other exposed regions as discussed below, depending on the operations performed. It is to be understood that this is just an example of utilizing self- assembled monolayers based on one set of deposition materials. [0073] Depending on what material is being used for the particular deposition material, the self-assembled monolayers may be tuned towards that material. Water may be used as one of the precursors, such as previously described, and the self-assembled monolayers may be structured as previously discussed, such as to include a hydroxyl-terminating material over the target location to facilitate formation on that material relative to other exposed materials. Additionally, a nitrogen-containing material may be utilized as one of the self-assembled monolayers on a material for which deposition is to occur, such as in one of the termination moieties of the monolayers, which may allow attraction of particular precursors used in the formation of one or more of the materials previously described. Additional precursors may be used that also enable or facilitate a metal-on-metal deposition, or semiconductor deposition. [0074] Because of the structure of some of the exposed metal or semiconductor materials, the exposed materials may also be corroded or passivated to reduce activity relative to other materials on which deposition is to occur, which may allow increased deposition on the target materials. Passivation of a material may include exposure to silicon-substituted or halogen- substituted materials, which may limit deposition of other materials. Oxidation of the material may utilize oxygen-containing materials or halogen-containing materials, for example, which may allow preferential deposition on other surfaces. Once oxidized, such as by exposure to an oxygen-containing material, an atomic layer deposition may be performed similarly as described, where one of the precursors may include an oxygen-containing material, which may not interact with the oxidized material.

[0075] Passivation may also be performed on exposed insulative and dielectric materials. For example, cap material 625 may include an oxide, for example, which may be treated to adjust termination groups to be silicon-containing, hydrogen-based, or halogen-containing. This may allow preferential deposition of a metal material or semiconductor material on other exposed regions. In still other embodiments, nitrogen-containing precursors may be used as one or both precursors in an atomic layer deposition process, which may allow preferential deposition on a metal surface relative to an oxide surface.

[0076] Embodiments may also utilize an inhibitor to form one of the deposition materials selectively over a target surface, while not forming the deposition material over dielectric or insulative materials, or other exposed surfaces. For example, a sprayed inhibitor may be applied across a surface of the substrate, which may apply along a top surface of the substrate, but which may not penetrate within recessed portions of the substrate. The inhibitor may be any number of materials that may be characterized by a siloxane backbone, such as silicone, or a

tetrafluoroethylene backbone, such as PTFE, along with other oil or surfactant materials. The material may be applied across the top surface of the substrate to cover exposed portions of cap material 625 and gate spacer 630. By use of a spray or coating application, the material may not be applied within recessed portions of the substrate, and may not contact the source and drain regions on which deposition may be performed. Additional selective techniques may be employed in combination, such as to form self-assembled monolayers as previously described over the PMOS and MOS regions to facilitate deposition at one location but not the other. The selected material may then be formed, such as by atomic layer deposition or other vapor deposition or physical deposition mechanisms.

[0077] The inhibitor material may prevent adhesion or adsorption of the material being deposited, which may form or deposit normally on the target location. Subsequent formation of the material, a removal agent may be applied to the substrate to remove the inhibitor material. The removal agent may be a wet etchant, reactant, or surfactant cleanser that may remove residual inhibitor material exposing the underlying dielectric and insulative materials. Utilizing an inhibitor may allow formation of the individual layers in a defined region that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes.

[0078] The inhibitor may also be a product of a plasma application that may neutralize or render inert a surface of the substrate. For example, a modifying plasma may be formed from one or more precursors, which may include inert precursors. The plasma may be applied to a surface of the substrate, or materials raised above the substrate, which may alter a top surface of the exposed materials, but which may not penetrate within recessed portions of the substrate, or portions at the substrate surface. For example, a nitrogen-containing precursor, which may be nitrogen, may be delivered to a plasma processing region of a processing chamber, where a plasma is generated. The plasma effluents, which may include nitrogen-containing plasma effluents, may be delivered to a substrate, and may form a nitrogenized surface along the exposed portions of the substrate along a top surface, which may include exposed regions of the cap material 625 and the gate spacer 630.

[0079] The plasma effluents may not be delivered, or may not flow, to the surface of the substrate, which may maintain a neat or unreacted surface along the source and drain materials. The deposition materials may then be formed with one or more deposition techniques and/or additional selective techniques such as the formation of self-assembled monolayers, which may include atomic layer deposition or other vapor or physical deposition. For example, an atomic layer deposition technique may be utilized subsequent processing with the plasma effluents, and formation of self-assembled monolayers on the PMOS and MOS regions of the substrate. After each cycle of the deposition, a nitrogen-containing plasma may be reapplied to a surface region of the substrate, such as over the dielectric or insulative materials. In this way, the surface of the dielectric materials may be passivated to prevent or limit formation of deposition materials over those regions. Utilizing these plasma effluents on raised portions from the substrate may allow formation of the deposition materials in a defined region along the substrate surface that need not be defined via subsequent patterning and/or etching of a blanket film. By removing prior and subsequent patterning operations, the processes may further reduce queue times over conventional processes.

[0080] Additional selective deposition techniques may utilize temperature differentials to enhance deposition on silicon-containing materials relative to oxygen-containing materials. For example, an atomic layer deposition utilizing a silicon-containing precursor may be performed at temperatures above or about 500° C, and may be performed at temperatures above or about 750° C, above or about 900° C, above or about 1000° C, or up to, above, or about 1100° C.

[0081] As temperature is increased within this range, the deposition may occur on certain exposed materials at a higher rate than on oxide-containing materials, such as may be cap material 625. A selective etch of the formed material may then be performed to remove the first dielectric material from the oxide surface. Although the first semiconductor material may also be reduced on the target surface, because the thickness may be many times greater than that on the oxide surface, full removal from the oxide surface may be performed while maintaining a thickness on the target surface greater than or about 1 nm, greater than or about 2 nm, greater than or about 3 nm, greater than or about 4 nm, greater than or about 5 nm, greater than or about 6 nm, greater than or about 7 nm, greater than or about 8 nm, greater than or about 9 nm, greater than or about 10 nm, or more. This effect may enable the present technology in ways that conventional technologies are limited. During normal conformal or blanket depositions, the thickness on some portions of the target surface would be equivalent to the thickness on the cap material, or may be less thick than on the cap material. Accordingly, an etch back process may over etch the target area, or may cause perforations in the layer.

[0082] Any of these techniques may selectively deposit or form the previously specified materials over specific target regions relative to one or more other metal, semiconductor, non- metal, dielectric, or insulative regions. Additionally, two or more of these techniques may be combined, or performed in iterations, to produce a surface with a particular region in which deposition may occur, or may occur at a higher rate. The selectivity may be complete in that the deposition material forms only over the target location, such as p-region source and drain 610 or n-region source and drain 615, or an intervening layer, and the deposition material may not form at all over other exposed materials. In other embodiments the selectivity may not be complete, and may be in a ratio of deposition on the target location relative to other exposed materials greater than or about 2: 1. The selectivity may also be greater than or about 5: 1, greater than or about 10: 1, greater than or about 15: 1, greater than or about 20: 1, greater than or about 25: 1, greater than or about 30: 1, greater than or about 35: 1, greater than or about 40: 1, greater than or about 45: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 200: 1, or more. As previously stated, the thickness of deposition of the materials may be less than or about 20 nm, less than or about 10 nm, less than or about 5 nm, less than or about 4 nm, less than or about 3 nm, less than or about 2 nm, less than or about 1 nm, or less. Accordingly, selectivities below 20: 1 may be acceptable to fully deposit the individual layers while forming a limited amount or essentially not forming material over the other exposed regions.

[0083] The deposition operations may be performed at any of the temperature or pressures previously described, and may be performed at temperatures greater than or about 300° C, and may be performed greater than or about 400° C, greater than or about 450° C, greater than or about 500° C, greater than or about 600° C, greater than or about 700° C, greater than or about 800° C, greater than or about 900° C, greater than or about 1,000° C, or higher. For example, temperatures greater than or about 500° C may be utilized during atomic layer deposition operations in order to activate precursors to interact with one another as layers of material are being formed.

[0084] Based on the type of deposition performed, certain operations may be performed in different order from previously described. For example, if a monolayer formed to resist or prevent formation may work with more than one material, the layer may be maintained during a subsequent operation for added efficiency. For example, method 500 is illustrated as forming indium gallium arsenide prior to forming the nickel alloy material on germanium in the PMOS region in method 700. However, if self-assembled monolayers are used to resist, reduce, or prevent the germanium layer from forming on other exposed materials, the layers may be maintained during a subsequent operation for the alloying metal, such as formation of an initial silicon germanium layer. In this way, operations 510 and 715 may be reversed in some embodiments, and all PMOS operations may be performed successively, and all MOS operations may be performed successively. [0085] Based on the amount of formation and the selectivity of the individual depositions, one or more etching operations may be performed as well. The etching operations may utilize dry etch chemistries, and may utilize plasma chemistries in embodiments. The etch backs may be performed in chamber 200, for example, which may be on the same cluster tool as one or more deposition chamber performing the previous depositions. In this way, several of the deposition and etching operations may be performed within a single environment, such as shared on a cluster tool between chambers. For example, along with one or more etching chambers 200 and deposition chambers 400, may be additional chambers, such as for performing UV treatments as may be utilized in some of the deposition techniques described below. Each transfer may occur under vacuum, and the chambers may each reside on the same cluster tool to allow the transfer to occur in a controlled environment. For example, vacuum conditions may be maintained during the transfer, and the transfer can occur without breaking vacuum. As opposed to conventional technologies that may include additional masking operations, lithography, and other operations that may require transfer among many tools, method 500 may be performed on a single tool in which vacuum conditions are not broken in embodiments. Additionally, method 500 may not utilize any RIE operations, which may reduce polymer buildup and the necessary ashing and cleaning operations associated with RIE.

[0086] The etching operations may be performed with plasma excited precursors, and may involve additional precursors along with particular fluorine-containing precursors. Nitrogen trifluoride may be utilized to generate plasma effluents in some embodiments. Additional or alternative fluorine-containing precursors may also be utilized. For example, a fluorine- containing precursor may be flowed into the remote plasma region and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, bromine trifluoride, chlorine trifluoride, nitrogen trifluoride, hydrogen fluoride, sulfur hexafluoride, and xenon difluoride. The remote plasma region may be within a distinct module from the processing chamber or a compartment within the processing chamber. As illustrated in FIG. 2, both RPS unit 201 and first plasma region 215 may be utilized as the remote plasma region. An RPS may allow dissociation of plasma effluents without damage to other chamber components, while first plasma region 215 may provide a shorter path length to the substrate during which recombination may occur. [0087] An additional precursor may also be delivered to the remote plasma region to augment the fluorine-containing precursor. For example, a nitrogen-and-hydrogen-containing precursor, an oxygen-containing precursor, or a hydrogen precursor may be delivered with the fluorine- containing precursor. The additional precursor may be a nitrogen-containing precursor such as ammonia, for example, or may be oxygen, hydrogen, or any number of precursors including one or more of these components. The additional precursors may be flowed in an unexcited state into the processing chamber to interact with the substrate surface. These recipes may selectively etch one of the exposed materials relative to one or more of the other exposed materials. For example, the etch chemistries may be used to recess one or more of the alloy materials, as well as any of the epitaxially grown materials relative to the exposed cap and spacer materials, as well as in relation to the other formed materials. The selectivity of the etch may be greater than or about 10: 1, greater than or about 20: 1, greater than or about 50: 1, greater than or about 75: 1, greater than or about 100: 1, greater than or about 150: 1, or more. In this way, all additional material that may have been formed during the deposition may be removed with minimal loss of material as formed in the intended location. This may occur because the selectivity of the deposition may produce at least twice as much material in the intended location as over other exposed materials.

[0088] The etching operations may be performed below about 10 Torr in embodiments, and may be performed below or about 5 Torr in embodiments. The process may also be performed at a temperature below about 100° C in embodiments, and may be performed below about 50° C. As performed in chamber 200, or a variation on this chamber, or in a different chamber capable of performing similar operations, the process may remove portions of a deposited material selective to other exposed materials across the substrate. By utilizing the present technology, fabrication may be performed with more selective formation and removal over conventional techniques, and may reduce queue times by hours over conventional processes.

[0089] In the preceding description, for the purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details.

[0090] Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology.

[0091] Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0092] As used herein and in the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the precursor" includes reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0093] Also, the words "comprise(s)", "comprising", "contain(s)", "containing", "include(s)", and "including", when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

CLAIMS: 1. A method of forming a semiconductor structure, the method comprising: depositing a first semiconductor material on a semiconductor substrate, wherein the first semiconductor material is selectively deposited on a first silicon-containing material relative to a second silicon-containing material; and

depositing a second semiconductor material on the semiconductor substrate, wherein the second semiconductor material is selectively deposited on the second silicon- containing material relative to the first semiconductor material.

2. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material is deposited on a PMOS region of the semiconductor substrate relative to an NMOS region of the semiconductor substrate.

3. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material comprises germanium, and wherein the first silicon-containing material comprises silicon germanium.

4. The method of forming a semiconductor structure of claim 3, wherein the second silicon-containing material comprises phosphorous.

5. The method of forming a semiconductor structure of claim 1, wherein the method is performed without conducting a reactive ion etching operation.

6. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material deposition is performed with a selectivity towards the first silicon- containing material relative to the second silicon-containing material greater than or about 2: 1.

7. The method of forming a semiconductor structure of claim 1, wherein the deposition occurs on an NMOS region of the semiconductor substrate relative to a PMOS region of the semiconductor substrate, and wherein the method is performed without forming a photoresist over the PMOS region.

8. The method of forming a semiconductor structure of claim 1, wherein the first semiconductor material comprises indium gallium arsenide, and wherein the first silicon- containing material comprises silicon phosphide.

9. The method of forming a semiconductor structure of claim 8, wherein the second silicon-containing material comprises germanium.

10. A method of forming a semiconductor structure, the method comprising: depositing a first alloy material over a first semiconductor material, wherein the alloy material is selectively deposited on the first semiconductor material relative to a nitride material or an oxide material; and

subsequently depositing a second alloy material over a second semiconductor material, wherein the second alloy material is selectively deposited on the second semiconductor material relative to the nitride material or the oxide material.

11. The method of forming a semiconductor structure of claim 10, wherein the first alloy material is deposited on an indium-containing material located in an NMOS region of the semiconductor substrate, and wherein the second alloy material is deposited on a germanium- containing material located in a PMOS region of the semiconductor substrate.

12. The method of forming a semiconductor structure of claim 10, wherein the nitride material comprises silicon nitride, and wherein the oxide material comprises silicon oxide, silicon oxycarbide, or a metal oxide.

13. The method of forming a semiconductor structure of claim 12, wherein the metal oxide comprises tungsten oxide or aluminum oxide.

14. The method of forming a semiconductor structure of claim 10, wherein the method is performed without conducting a reactive ion etching operation.

15. The method of forming a semiconductor structure of claim 10, wherein the second alloy material comprises nickel silicon germanium, and wherein the first alloy material comprises a titanium-containing material.